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radeonsi: move remaining sampler state into si_state.c
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_pack_color.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "radeonsi_pipe.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * inferred framebuffer and blender state
38 */
39 static void si_update_fb_blend_state(struct r600_context *rctx)
40 {
41 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
42 struct si_state_blend *blend = rctx->queued.named.blend;
43 uint32_t mask;
44
45 if (pm4 == NULL || blend == NULL)
46 return;
47
48 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
49 mask &= blend->cb_target_mask;
50 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
51
52 si_pm4_set_state(rctx, fb_blend, pm4);
53 }
54
55 /*
56 * Blender functions
57 */
58
59 static uint32_t si_translate_blend_function(int blend_func)
60 {
61 switch (blend_func) {
62 case PIPE_BLEND_ADD:
63 return V_028780_COMB_DST_PLUS_SRC;
64 case PIPE_BLEND_SUBTRACT:
65 return V_028780_COMB_SRC_MINUS_DST;
66 case PIPE_BLEND_REVERSE_SUBTRACT:
67 return V_028780_COMB_DST_MINUS_SRC;
68 case PIPE_BLEND_MIN:
69 return V_028780_COMB_MIN_DST_SRC;
70 case PIPE_BLEND_MAX:
71 return V_028780_COMB_MAX_DST_SRC;
72 default:
73 R600_ERR("Unknown blend function %d\n", blend_func);
74 assert(0);
75 break;
76 }
77 return 0;
78 }
79
80 static uint32_t si_translate_blend_factor(int blend_fact)
81 {
82 switch (blend_fact) {
83 case PIPE_BLENDFACTOR_ONE:
84 return V_028780_BLEND_ONE;
85 case PIPE_BLENDFACTOR_SRC_COLOR:
86 return V_028780_BLEND_SRC_COLOR;
87 case PIPE_BLENDFACTOR_SRC_ALPHA:
88 return V_028780_BLEND_SRC_ALPHA;
89 case PIPE_BLENDFACTOR_DST_ALPHA:
90 return V_028780_BLEND_DST_ALPHA;
91 case PIPE_BLENDFACTOR_DST_COLOR:
92 return V_028780_BLEND_DST_COLOR;
93 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
94 return V_028780_BLEND_SRC_ALPHA_SATURATE;
95 case PIPE_BLENDFACTOR_CONST_COLOR:
96 return V_028780_BLEND_CONSTANT_COLOR;
97 case PIPE_BLENDFACTOR_CONST_ALPHA:
98 return V_028780_BLEND_CONSTANT_ALPHA;
99 case PIPE_BLENDFACTOR_ZERO:
100 return V_028780_BLEND_ZERO;
101 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
102 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
103 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
105 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
106 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
107 case PIPE_BLENDFACTOR_INV_DST_COLOR:
108 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
109 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
110 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
111 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
112 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
113 case PIPE_BLENDFACTOR_SRC1_COLOR:
114 return V_028780_BLEND_SRC1_COLOR;
115 case PIPE_BLENDFACTOR_SRC1_ALPHA:
116 return V_028780_BLEND_SRC1_ALPHA;
117 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
118 return V_028780_BLEND_INV_SRC1_COLOR;
119 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
120 return V_028780_BLEND_INV_SRC1_ALPHA;
121 default:
122 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
123 assert(0);
124 break;
125 }
126 return 0;
127 }
128
129 static void *si_create_blend_state(struct pipe_context *ctx,
130 const struct pipe_blend_state *state)
131 {
132 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
133 struct si_pm4_state *pm4 = &blend->pm4;
134
135 uint32_t color_control;
136
137 if (blend == NULL)
138 return NULL;
139
140 color_control = S_028808_MODE(V_028808_CB_NORMAL);
141 if (state->logicop_enable) {
142 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
143 } else {
144 color_control |= S_028808_ROP3(0xcc);
145 }
146 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
147
148 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
149 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
150
151 blend->cb_target_mask = 0;
152 for (int i = 0; i < 8; i++) {
153 /* state->rt entries > 0 only written if independent blending */
154 const int j = state->independent_blend_enable ? i : 0;
155
156 unsigned eqRGB = state->rt[j].rgb_func;
157 unsigned srcRGB = state->rt[j].rgb_src_factor;
158 unsigned dstRGB = state->rt[j].rgb_dst_factor;
159 unsigned eqA = state->rt[j].alpha_func;
160 unsigned srcA = state->rt[j].alpha_src_factor;
161 unsigned dstA = state->rt[j].alpha_dst_factor;
162
163 unsigned blend_cntl = 0;
164
165 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
166 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
167
168 if (!state->rt[j].blend_enable) {
169 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
170 continue;
171 }
172
173 blend_cntl |= S_028780_ENABLE(1);
174 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
175 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
176 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
177
178 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
179 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
180 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
181 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
182 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
183 }
184 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
185 }
186
187 return blend;
188 }
189
190 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
191 {
192 struct r600_context *rctx = (struct r600_context *)ctx;
193 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
194 si_update_fb_blend_state(rctx);
195 }
196
197 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
201 }
202
203 static void si_set_blend_color(struct pipe_context *ctx,
204 const struct pipe_blend_color *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
208
209 if (pm4 == NULL)
210 return;
211
212 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
213 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
214 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
215 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
216
217 si_pm4_set_state(rctx, blend_color, pm4);
218 }
219
220 /*
221 * Clipping, scissors and viewport
222 */
223
224 static void si_set_clip_state(struct pipe_context *ctx,
225 const struct pipe_clip_state *state)
226 {
227 struct r600_context *rctx = (struct r600_context *)ctx;
228 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
229
230 if (pm4 == NULL)
231 return;
232
233 for (int i = 0; i < 6; i++) {
234 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
235 fui(state->ucp[i][0]));
236 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
237 fui(state->ucp[i][1]));
238 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
239 fui(state->ucp[i][2]));
240 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
241 fui(state->ucp[i][3]));
242 }
243
244 si_pm4_set_state(rctx, clip, pm4);
245 }
246
247 static void si_set_scissor_state(struct pipe_context *ctx,
248 const struct pipe_scissor_state *state)
249 {
250 struct r600_context *rctx = (struct r600_context *)ctx;
251 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
252 uint32_t tl, br;
253
254 if (pm4 == NULL)
255 return;
256
257 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
258 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
259 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
260 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
261 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
262 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
263 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
264 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
265 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
266 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
267
268 si_pm4_set_state(rctx, scissor, pm4);
269 }
270
271 static void si_set_viewport_state(struct pipe_context *ctx,
272 const struct pipe_viewport_state *state)
273 {
274 struct r600_context *rctx = (struct r600_context *)ctx;
275 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
276 struct si_pm4_state *pm4 = &viewport->pm4;
277
278 if (viewport == NULL)
279 return;
280
281 viewport->viewport = *state;
282 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
283 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
284 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
285 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
286 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
287 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
288 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
289 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
290 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
291 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
292
293 si_pm4_set_state(rctx, viewport, viewport);
294 }
295
296 /*
297 * inferred state between framebuffer and rasterizer
298 */
299 static void si_update_fb_rs_state(struct r600_context *rctx)
300 {
301 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
302 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
303 unsigned offset_db_fmt_cntl = 0, depth;
304 float offset_units;
305
306 if (!rs || !rctx->framebuffer.zsbuf) {
307 FREE(pm4);
308 return;
309 }
310
311 offset_units = rctx->queued.named.rasterizer->offset_units;
312 switch (rctx->framebuffer.zsbuf->texture->format) {
313 case PIPE_FORMAT_Z24X8_UNORM:
314 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
315 depth = -24;
316 offset_units *= 2.0f;
317 break;
318 case PIPE_FORMAT_Z32_FLOAT:
319 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
320 depth = -23;
321 offset_units *= 1.0f;
322 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
323 break;
324 case PIPE_FORMAT_Z16_UNORM:
325 depth = -16;
326 offset_units *= 4.0f;
327 break;
328 default:
329 return;
330 }
331
332 /* FIXME some of those reg can be computed with cso */
333 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
334 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
335 fui(rctx->queued.named.rasterizer->offset_scale));
336 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
337 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
338 fui(rctx->queued.named.rasterizer->offset_scale));
339 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
340 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
341
342 si_pm4_set_state(rctx, fb_rs, pm4);
343 }
344
345 /*
346 * Rasterizer
347 */
348
349 static uint32_t si_translate_fill(uint32_t func)
350 {
351 switch(func) {
352 case PIPE_POLYGON_MODE_FILL:
353 return V_028814_X_DRAW_TRIANGLES;
354 case PIPE_POLYGON_MODE_LINE:
355 return V_028814_X_DRAW_LINES;
356 case PIPE_POLYGON_MODE_POINT:
357 return V_028814_X_DRAW_POINTS;
358 default:
359 assert(0);
360 return V_028814_X_DRAW_POINTS;
361 }
362 }
363
364 static void *si_create_rs_state(struct pipe_context *ctx,
365 const struct pipe_rasterizer_state *state)
366 {
367 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
368 struct si_pm4_state *pm4 = &rs->pm4;
369 unsigned tmp;
370 unsigned prov_vtx = 1, polygon_dual_mode;
371 unsigned clip_rule;
372 float psize_min, psize_max;
373
374 if (rs == NULL) {
375 return NULL;
376 }
377
378 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
379 state->fill_back != PIPE_POLYGON_MODE_FILL);
380
381 if (state->flatshade_first)
382 prov_vtx = 0;
383
384 rs->flatshade = state->flatshade;
385 rs->sprite_coord_enable = state->sprite_coord_enable;
386 rs->pa_sc_line_stipple = state->line_stipple_enable ?
387 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
388 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
389 rs->pa_su_sc_mode_cntl =
390 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
391 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
392 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
393 S_028814_FACE(!state->front_ccw) |
394 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
395 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
396 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
397 S_028814_POLY_MODE(polygon_dual_mode) |
398 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
399 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
400 rs->pa_cl_clip_cntl =
401 S_028810_PS_UCP_MODE(3) |
402 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
403 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
404 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
405 rs->pa_cl_vs_out_cntl =
406 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
407 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
408
409 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
410
411 /* offset */
412 rs->offset_units = state->offset_units;
413 rs->offset_scale = state->offset_scale * 12.0f;
414
415 /* XXX: Flat shading hangs the GPU */
416 tmp = S_0286D4_FLAT_SHADE_ENA(0);
417 if (state->sprite_coord_enable) {
418 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
419 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
420 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
421 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
422 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
423 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
424 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
425 }
426 }
427 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
428
429 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
430 /* point size 12.4 fixed point */
431 tmp = (unsigned)(state->point_size * 8.0);
432 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
433
434 if (state->point_size_per_vertex) {
435 psize_min = util_get_min_point_size(state);
436 psize_max = 8192;
437 } else {
438 /* Force the point size to be as if the vertex output was disabled. */
439 psize_min = state->point_size;
440 psize_max = state->point_size;
441 }
442 /* Divide by two, because 0.5 = 1 pixel. */
443 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
444 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
445 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
446
447 tmp = (unsigned)state->line_width * 8;
448 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
449 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
450 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
451
452 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
453 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
454 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
455 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
456 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
457 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
458 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
459
460 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
461 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
462
463 return rs;
464 }
465
466 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
467 {
468 struct r600_context *rctx = (struct r600_context *)ctx;
469 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
470
471 if (state == NULL)
472 return;
473
474 // TODO
475 rctx->sprite_coord_enable = rs->sprite_coord_enable;
476 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
477 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
478 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
479 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
480
481 si_pm4_bind_state(rctx, rasterizer, rs);
482 si_update_fb_rs_state(rctx);
483 }
484
485 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
489 }
490
491 /*
492 * infeered state between dsa and stencil ref
493 */
494 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
495 {
496 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
497 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
498 struct si_state_dsa *dsa = rctx->queued.named.dsa;
499
500 if (pm4 == NULL)
501 return;
502
503 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
504 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
505 S_028430_STENCILMASK(dsa->valuemask[0]) |
506 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
507 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
508 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
509 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
510 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
511
512 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
513 }
514
515 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
516 const struct pipe_stencil_ref *state)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519 rctx->stencil_ref = *state;
520 si_update_dsa_stencil_ref(rctx);
521 }
522
523
524 /*
525 * DSA
526 */
527
528 /* transnates straight */
529 static uint32_t si_translate_ds_func(int func)
530 {
531 return func;
532 }
533
534 static void *si_create_dsa_state(struct pipe_context *ctx,
535 const struct pipe_depth_stencil_alpha_state *state)
536 {
537 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
538 struct si_pm4_state *pm4 = &dsa->pm4;
539 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
540 unsigned db_render_override, db_render_control;
541
542 if (dsa == NULL) {
543 return NULL;
544 }
545
546 dsa->valuemask[0] = state->stencil[0].valuemask;
547 dsa->valuemask[1] = state->stencil[1].valuemask;
548 dsa->writemask[0] = state->stencil[0].writemask;
549 dsa->writemask[1] = state->stencil[1].writemask;
550
551 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
552 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
553 S_028800_ZFUNC(state->depth.func);
554
555 /* stencil */
556 if (state->stencil[0].enabled) {
557 db_depth_control |= S_028800_STENCIL_ENABLE(1);
558 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
559 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
560 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
561 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
562
563 if (state->stencil[1].enabled) {
564 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
565 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
566 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
567 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
568 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
569 }
570 }
571
572 /* alpha */
573 //alpha_test_control = 0;
574 alpha_ref = 0;
575 if (state->alpha.enabled) {
576 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
577 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
578 alpha_ref = fui(state->alpha.ref_value);
579 }
580 dsa->alpha_ref = alpha_ref;
581
582 /* misc */
583 db_render_control = 0;
584 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
585 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
586 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
587 /* TODO db_render_override depends on query */
588 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
589 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
590 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
591 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
592 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
593 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
594 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
595 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
596 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
597 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
598 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
599 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
600 dsa->db_render_override = db_render_override;
601
602 return dsa;
603 }
604
605 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
606 {
607 struct r600_context *rctx = (struct r600_context *)ctx;
608 struct si_state_dsa *dsa = state;
609
610 if (state == NULL)
611 return;
612
613 si_pm4_bind_state(rctx, dsa, dsa);
614 si_update_dsa_stencil_ref(rctx);
615
616 // TODO
617 rctx->alpha_ref = dsa->alpha_ref;
618 rctx->alpha_ref_dirty = true;
619 }
620
621 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
622 {
623 struct r600_context *rctx = (struct r600_context *)ctx;
624 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
625 }
626
627 static void *si_create_db_flush_dsa(struct r600_context *rctx)
628 {
629 struct pipe_depth_stencil_alpha_state dsa;
630 struct si_state_dsa *state;
631
632 memset(&dsa, 0, sizeof(dsa));
633
634 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
635 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
636 S_028000_DEPTH_COPY(1) |
637 S_028000_STENCIL_COPY(1) |
638 S_028000_COPY_CENTROID(1));
639 return state;
640 }
641
642 /*
643 * format translation
644 */
645 static uint32_t si_translate_colorformat(enum pipe_format format)
646 {
647 switch (format) {
648 /* 8-bit buffers. */
649 case PIPE_FORMAT_A8_UNORM:
650 case PIPE_FORMAT_A8_UINT:
651 case PIPE_FORMAT_A8_SINT:
652 case PIPE_FORMAT_I8_UNORM:
653 case PIPE_FORMAT_I8_UINT:
654 case PIPE_FORMAT_I8_SINT:
655 case PIPE_FORMAT_L8_UNORM:
656 case PIPE_FORMAT_L8_UINT:
657 case PIPE_FORMAT_L8_SINT:
658 case PIPE_FORMAT_L8_SRGB:
659 case PIPE_FORMAT_R8_UNORM:
660 case PIPE_FORMAT_R8_SNORM:
661 case PIPE_FORMAT_R8_UINT:
662 case PIPE_FORMAT_R8_SINT:
663 return V_028C70_COLOR_8;
664
665 /* 16-bit buffers. */
666 case PIPE_FORMAT_B5G6R5_UNORM:
667 return V_028C70_COLOR_5_6_5;
668
669 case PIPE_FORMAT_B5G5R5A1_UNORM:
670 case PIPE_FORMAT_B5G5R5X1_UNORM:
671 return V_028C70_COLOR_1_5_5_5;
672
673 case PIPE_FORMAT_B4G4R4A4_UNORM:
674 case PIPE_FORMAT_B4G4R4X4_UNORM:
675 return V_028C70_COLOR_4_4_4_4;
676
677 case PIPE_FORMAT_L8A8_UNORM:
678 case PIPE_FORMAT_L8A8_UINT:
679 case PIPE_FORMAT_L8A8_SINT:
680 case PIPE_FORMAT_L8A8_SRGB:
681 case PIPE_FORMAT_R8G8_UNORM:
682 case PIPE_FORMAT_R8G8_UINT:
683 case PIPE_FORMAT_R8G8_SINT:
684 return V_028C70_COLOR_8_8;
685
686 case PIPE_FORMAT_Z16_UNORM:
687 case PIPE_FORMAT_R16_UNORM:
688 case PIPE_FORMAT_R16_UINT:
689 case PIPE_FORMAT_R16_SINT:
690 case PIPE_FORMAT_R16_FLOAT:
691 case PIPE_FORMAT_R16G16_FLOAT:
692 return V_028C70_COLOR_16;
693
694 /* 32-bit buffers. */
695 case PIPE_FORMAT_A8B8G8R8_SRGB:
696 case PIPE_FORMAT_A8B8G8R8_UNORM:
697 case PIPE_FORMAT_A8R8G8B8_UNORM:
698 case PIPE_FORMAT_B8G8R8A8_SRGB:
699 case PIPE_FORMAT_B8G8R8A8_UNORM:
700 case PIPE_FORMAT_B8G8R8X8_UNORM:
701 case PIPE_FORMAT_R8G8B8A8_SNORM:
702 case PIPE_FORMAT_R8G8B8A8_UNORM:
703 case PIPE_FORMAT_R8G8B8X8_UNORM:
704 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
705 case PIPE_FORMAT_X8B8G8R8_UNORM:
706 case PIPE_FORMAT_X8R8G8B8_UNORM:
707 case PIPE_FORMAT_R8G8B8_UNORM:
708 case PIPE_FORMAT_R8G8B8A8_SSCALED:
709 case PIPE_FORMAT_R8G8B8A8_USCALED:
710 case PIPE_FORMAT_R8G8B8A8_SINT:
711 case PIPE_FORMAT_R8G8B8A8_UINT:
712 return V_028C70_COLOR_8_8_8_8;
713
714 case PIPE_FORMAT_R10G10B10A2_UNORM:
715 case PIPE_FORMAT_R10G10B10X2_SNORM:
716 case PIPE_FORMAT_B10G10R10A2_UNORM:
717 case PIPE_FORMAT_B10G10R10A2_UINT:
718 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
719 return V_028C70_COLOR_2_10_10_10;
720
721 case PIPE_FORMAT_Z24X8_UNORM:
722 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
723 return V_028C70_COLOR_8_24;
724
725 case PIPE_FORMAT_X8Z24_UNORM:
726 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
727 return V_028C70_COLOR_24_8;
728
729 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
730 return V_028C70_COLOR_X24_8_32_FLOAT;
731
732 case PIPE_FORMAT_R32_FLOAT:
733 case PIPE_FORMAT_Z32_FLOAT:
734 return V_028C70_COLOR_32;
735
736 case PIPE_FORMAT_R16G16_SSCALED:
737 case PIPE_FORMAT_R16G16_UNORM:
738 case PIPE_FORMAT_R16G16_UINT:
739 case PIPE_FORMAT_R16G16_SINT:
740 return V_028C70_COLOR_16_16;
741
742 case PIPE_FORMAT_R11G11B10_FLOAT:
743 return V_028C70_COLOR_10_11_11;
744
745 /* 64-bit buffers. */
746 case PIPE_FORMAT_R16G16B16_USCALED:
747 case PIPE_FORMAT_R16G16B16_SSCALED:
748 case PIPE_FORMAT_R16G16B16A16_UINT:
749 case PIPE_FORMAT_R16G16B16A16_SINT:
750 case PIPE_FORMAT_R16G16B16A16_USCALED:
751 case PIPE_FORMAT_R16G16B16A16_SSCALED:
752 case PIPE_FORMAT_R16G16B16A16_UNORM:
753 case PIPE_FORMAT_R16G16B16A16_SNORM:
754 case PIPE_FORMAT_R16G16B16_FLOAT:
755 case PIPE_FORMAT_R16G16B16A16_FLOAT:
756 return V_028C70_COLOR_16_16_16_16;
757
758 case PIPE_FORMAT_R32G32_FLOAT:
759 case PIPE_FORMAT_R32G32_USCALED:
760 case PIPE_FORMAT_R32G32_SSCALED:
761 case PIPE_FORMAT_R32G32_SINT:
762 case PIPE_FORMAT_R32G32_UINT:
763 return V_028C70_COLOR_32_32;
764
765 /* 128-bit buffers. */
766 case PIPE_FORMAT_R32G32B32A32_SNORM:
767 case PIPE_FORMAT_R32G32B32A32_UNORM:
768 case PIPE_FORMAT_R32G32B32A32_SSCALED:
769 case PIPE_FORMAT_R32G32B32A32_USCALED:
770 case PIPE_FORMAT_R32G32B32A32_SINT:
771 case PIPE_FORMAT_R32G32B32A32_UINT:
772 case PIPE_FORMAT_R32G32B32A32_FLOAT:
773 return V_028C70_COLOR_32_32_32_32;
774
775 /* YUV buffers. */
776 case PIPE_FORMAT_UYVY:
777 case PIPE_FORMAT_YUYV:
778 /* 96-bit buffers. */
779 case PIPE_FORMAT_R32G32B32_FLOAT:
780 /* 8-bit buffers. */
781 case PIPE_FORMAT_L4A4_UNORM:
782 case PIPE_FORMAT_R4A4_UNORM:
783 case PIPE_FORMAT_A4R4_UNORM:
784 default:
785 return ~0U; /* Unsupported. */
786 }
787 }
788
789 static uint32_t si_translate_colorswap(enum pipe_format format)
790 {
791 switch (format) {
792 /* 8-bit buffers. */
793 case PIPE_FORMAT_L4A4_UNORM:
794 case PIPE_FORMAT_A4R4_UNORM:
795 return V_028C70_SWAP_ALT;
796
797 case PIPE_FORMAT_A8_UNORM:
798 case PIPE_FORMAT_A8_UINT:
799 case PIPE_FORMAT_A8_SINT:
800 case PIPE_FORMAT_R4A4_UNORM:
801 return V_028C70_SWAP_ALT_REV;
802 case PIPE_FORMAT_I8_UNORM:
803 case PIPE_FORMAT_L8_UNORM:
804 case PIPE_FORMAT_I8_UINT:
805 case PIPE_FORMAT_I8_SINT:
806 case PIPE_FORMAT_L8_UINT:
807 case PIPE_FORMAT_L8_SINT:
808 case PIPE_FORMAT_L8_SRGB:
809 case PIPE_FORMAT_R8_UNORM:
810 case PIPE_FORMAT_R8_SNORM:
811 case PIPE_FORMAT_R8_UINT:
812 case PIPE_FORMAT_R8_SINT:
813 return V_028C70_SWAP_STD;
814
815 /* 16-bit buffers. */
816 case PIPE_FORMAT_B5G6R5_UNORM:
817 return V_028C70_SWAP_STD_REV;
818
819 case PIPE_FORMAT_B5G5R5A1_UNORM:
820 case PIPE_FORMAT_B5G5R5X1_UNORM:
821 return V_028C70_SWAP_ALT;
822
823 case PIPE_FORMAT_B4G4R4A4_UNORM:
824 case PIPE_FORMAT_B4G4R4X4_UNORM:
825 return V_028C70_SWAP_ALT;
826
827 case PIPE_FORMAT_Z16_UNORM:
828 return V_028C70_SWAP_STD;
829
830 case PIPE_FORMAT_L8A8_UNORM:
831 case PIPE_FORMAT_L8A8_UINT:
832 case PIPE_FORMAT_L8A8_SINT:
833 case PIPE_FORMAT_L8A8_SRGB:
834 return V_028C70_SWAP_ALT;
835 case PIPE_FORMAT_R8G8_UNORM:
836 case PIPE_FORMAT_R8G8_UINT:
837 case PIPE_FORMAT_R8G8_SINT:
838 return V_028C70_SWAP_STD;
839
840 case PIPE_FORMAT_R16_UNORM:
841 case PIPE_FORMAT_R16_UINT:
842 case PIPE_FORMAT_R16_SINT:
843 case PIPE_FORMAT_R16_FLOAT:
844 return V_028C70_SWAP_STD;
845
846 /* 32-bit buffers. */
847 case PIPE_FORMAT_A8B8G8R8_SRGB:
848 return V_028C70_SWAP_STD_REV;
849 case PIPE_FORMAT_B8G8R8A8_SRGB:
850 return V_028C70_SWAP_ALT;
851
852 case PIPE_FORMAT_B8G8R8A8_UNORM:
853 case PIPE_FORMAT_B8G8R8X8_UNORM:
854 return V_028C70_SWAP_ALT;
855
856 case PIPE_FORMAT_A8R8G8B8_UNORM:
857 case PIPE_FORMAT_X8R8G8B8_UNORM:
858 return V_028C70_SWAP_ALT_REV;
859 case PIPE_FORMAT_R8G8B8A8_SNORM:
860 case PIPE_FORMAT_R8G8B8A8_UNORM:
861 case PIPE_FORMAT_R8G8B8A8_SSCALED:
862 case PIPE_FORMAT_R8G8B8A8_USCALED:
863 case PIPE_FORMAT_R8G8B8A8_SINT:
864 case PIPE_FORMAT_R8G8B8A8_UINT:
865 case PIPE_FORMAT_R8G8B8X8_UNORM:
866 return V_028C70_SWAP_STD;
867
868 case PIPE_FORMAT_A8B8G8R8_UNORM:
869 case PIPE_FORMAT_X8B8G8R8_UNORM:
870 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
871 return V_028C70_SWAP_STD_REV;
872
873 case PIPE_FORMAT_Z24X8_UNORM:
874 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
875 return V_028C70_SWAP_STD;
876
877 case PIPE_FORMAT_X8Z24_UNORM:
878 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
879 return V_028C70_SWAP_STD;
880
881 case PIPE_FORMAT_R10G10B10A2_UNORM:
882 case PIPE_FORMAT_R10G10B10X2_SNORM:
883 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
884 return V_028C70_SWAP_STD;
885
886 case PIPE_FORMAT_B10G10R10A2_UNORM:
887 case PIPE_FORMAT_B10G10R10A2_UINT:
888 return V_028C70_SWAP_ALT;
889
890 case PIPE_FORMAT_R11G11B10_FLOAT:
891 case PIPE_FORMAT_R32_FLOAT:
892 case PIPE_FORMAT_R32_UINT:
893 case PIPE_FORMAT_R32_SINT:
894 case PIPE_FORMAT_Z32_FLOAT:
895 case PIPE_FORMAT_R16G16_FLOAT:
896 case PIPE_FORMAT_R16G16_UNORM:
897 case PIPE_FORMAT_R16G16_UINT:
898 case PIPE_FORMAT_R16G16_SINT:
899 return V_028C70_SWAP_STD;
900
901 /* 64-bit buffers. */
902 case PIPE_FORMAT_R32G32_FLOAT:
903 case PIPE_FORMAT_R32G32_UINT:
904 case PIPE_FORMAT_R32G32_SINT:
905 case PIPE_FORMAT_R16G16B16A16_UNORM:
906 case PIPE_FORMAT_R16G16B16A16_SNORM:
907 case PIPE_FORMAT_R16G16B16A16_USCALED:
908 case PIPE_FORMAT_R16G16B16A16_SSCALED:
909 case PIPE_FORMAT_R16G16B16A16_UINT:
910 case PIPE_FORMAT_R16G16B16A16_SINT:
911 case PIPE_FORMAT_R16G16B16A16_FLOAT:
912 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
913
914 /* 128-bit buffers. */
915 case PIPE_FORMAT_R32G32B32A32_FLOAT:
916 case PIPE_FORMAT_R32G32B32A32_SNORM:
917 case PIPE_FORMAT_R32G32B32A32_UNORM:
918 case PIPE_FORMAT_R32G32B32A32_SSCALED:
919 case PIPE_FORMAT_R32G32B32A32_USCALED:
920 case PIPE_FORMAT_R32G32B32A32_SINT:
921 case PIPE_FORMAT_R32G32B32A32_UINT:
922 return V_028C70_SWAP_STD;
923 default:
924 R600_ERR("unsupported colorswap format %d\n", format);
925 return ~0U;
926 }
927 return ~0U;
928 }
929
930 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
931 {
932 if (R600_BIG_ENDIAN) {
933 switch(colorformat) {
934 /* 8-bit buffers. */
935 case V_028C70_COLOR_8:
936 return V_028C70_ENDIAN_NONE;
937
938 /* 16-bit buffers. */
939 case V_028C70_COLOR_5_6_5:
940 case V_028C70_COLOR_1_5_5_5:
941 case V_028C70_COLOR_4_4_4_4:
942 case V_028C70_COLOR_16:
943 case V_028C70_COLOR_8_8:
944 return V_028C70_ENDIAN_8IN16;
945
946 /* 32-bit buffers. */
947 case V_028C70_COLOR_8_8_8_8:
948 case V_028C70_COLOR_2_10_10_10:
949 case V_028C70_COLOR_8_24:
950 case V_028C70_COLOR_24_8:
951 case V_028C70_COLOR_16_16:
952 return V_028C70_ENDIAN_8IN32;
953
954 /* 64-bit buffers. */
955 case V_028C70_COLOR_16_16_16_16:
956 return V_028C70_ENDIAN_8IN16;
957
958 case V_028C70_COLOR_32_32:
959 return V_028C70_ENDIAN_8IN32;
960
961 /* 128-bit buffers. */
962 case V_028C70_COLOR_32_32_32_32:
963 return V_028C70_ENDIAN_8IN32;
964 default:
965 return V_028C70_ENDIAN_NONE; /* Unsupported. */
966 }
967 } else {
968 return V_028C70_ENDIAN_NONE;
969 }
970 }
971
972 static uint32_t si_translate_dbformat(enum pipe_format format)
973 {
974 switch (format) {
975 case PIPE_FORMAT_Z16_UNORM:
976 return V_028040_Z_16;
977 case PIPE_FORMAT_Z24X8_UNORM:
978 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
979 return V_028040_Z_24; /* XXX no longer supported on SI */
980 case PIPE_FORMAT_Z32_FLOAT:
981 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
982 return V_028040_Z_32_FLOAT;
983 default:
984 return ~0U;
985 }
986 }
987
988 /*
989 * Texture translation
990 */
991
992 static uint32_t si_translate_texformat(struct pipe_screen *screen,
993 enum pipe_format format,
994 const struct util_format_description *desc,
995 int first_non_void)
996 {
997 boolean uniform = TRUE;
998 int i;
999
1000 /* Colorspace (return non-RGB formats directly). */
1001 switch (desc->colorspace) {
1002 /* Depth stencil formats */
1003 case UTIL_FORMAT_COLORSPACE_ZS:
1004 switch (format) {
1005 case PIPE_FORMAT_Z16_UNORM:
1006 return V_008F14_IMG_DATA_FORMAT_16;
1007 case PIPE_FORMAT_X24S8_UINT:
1008 case PIPE_FORMAT_Z24X8_UNORM:
1009 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1010 return V_008F14_IMG_DATA_FORMAT_24_8;
1011 case PIPE_FORMAT_S8X24_UINT:
1012 case PIPE_FORMAT_X8Z24_UNORM:
1013 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1014 return V_008F14_IMG_DATA_FORMAT_8_24;
1015 case PIPE_FORMAT_S8_UINT:
1016 return V_008F14_IMG_DATA_FORMAT_8;
1017 case PIPE_FORMAT_Z32_FLOAT:
1018 return V_008F14_IMG_DATA_FORMAT_32;
1019 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1020 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1021 default:
1022 goto out_unknown;
1023 }
1024
1025 case UTIL_FORMAT_COLORSPACE_YUV:
1026 goto out_unknown; /* TODO */
1027
1028 case UTIL_FORMAT_COLORSPACE_SRGB:
1029 break;
1030
1031 default:
1032 break;
1033 }
1034
1035 /* TODO compressed formats */
1036
1037 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1038 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1039 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1040 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1041 }
1042
1043 /* R8G8Bx_SNORM - TODO CxV8U8 */
1044
1045 /* See whether the components are of the same size. */
1046 for (i = 1; i < desc->nr_channels; i++) {
1047 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1048 }
1049
1050 /* Non-uniform formats. */
1051 if (!uniform) {
1052 switch(desc->nr_channels) {
1053 case 3:
1054 if (desc->channel[0].size == 5 &&
1055 desc->channel[1].size == 6 &&
1056 desc->channel[2].size == 5) {
1057 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1058 }
1059 goto out_unknown;
1060 case 4:
1061 if (desc->channel[0].size == 5 &&
1062 desc->channel[1].size == 5 &&
1063 desc->channel[2].size == 5 &&
1064 desc->channel[3].size == 1) {
1065 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1066 }
1067 if (desc->channel[0].size == 10 &&
1068 desc->channel[1].size == 10 &&
1069 desc->channel[2].size == 10 &&
1070 desc->channel[3].size == 2) {
1071 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1072 }
1073 goto out_unknown;
1074 }
1075 goto out_unknown;
1076 }
1077
1078 if (first_non_void < 0 || first_non_void > 3)
1079 goto out_unknown;
1080
1081 /* uniform formats */
1082 switch (desc->channel[first_non_void].size) {
1083 case 4:
1084 switch (desc->nr_channels) {
1085 case 2:
1086 return V_008F14_IMG_DATA_FORMAT_4_4;
1087 case 4:
1088 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1089 }
1090 break;
1091 case 8:
1092 switch (desc->nr_channels) {
1093 case 1:
1094 return V_008F14_IMG_DATA_FORMAT_8;
1095 case 2:
1096 return V_008F14_IMG_DATA_FORMAT_8_8;
1097 case 4:
1098 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1099 }
1100 break;
1101 case 16:
1102 switch (desc->nr_channels) {
1103 case 1:
1104 return V_008F14_IMG_DATA_FORMAT_16;
1105 case 2:
1106 return V_008F14_IMG_DATA_FORMAT_16_16;
1107 case 4:
1108 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1109 }
1110 break;
1111 case 32:
1112 switch (desc->nr_channels) {
1113 case 1:
1114 return V_008F14_IMG_DATA_FORMAT_32;
1115 case 2:
1116 return V_008F14_IMG_DATA_FORMAT_32_32;
1117 case 3:
1118 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1119 case 4:
1120 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1121 }
1122 }
1123
1124 out_unknown:
1125 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1126 return ~0;
1127 }
1128
1129 static unsigned si_tex_wrap(unsigned wrap)
1130 {
1131 switch (wrap) {
1132 default:
1133 case PIPE_TEX_WRAP_REPEAT:
1134 return V_008F30_SQ_TEX_WRAP;
1135 case PIPE_TEX_WRAP_CLAMP:
1136 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1137 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1138 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1139 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1140 return V_008F30_SQ_TEX_CLAMP_BORDER;
1141 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1142 return V_008F30_SQ_TEX_MIRROR;
1143 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1144 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1145 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1146 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1147 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1148 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1149 }
1150 }
1151
1152 static unsigned si_tex_filter(unsigned filter)
1153 {
1154 switch (filter) {
1155 default:
1156 case PIPE_TEX_FILTER_NEAREST:
1157 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1158 case PIPE_TEX_FILTER_LINEAR:
1159 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1160 }
1161 }
1162
1163 static unsigned si_tex_mipfilter(unsigned filter)
1164 {
1165 switch (filter) {
1166 case PIPE_TEX_MIPFILTER_NEAREST:
1167 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1168 case PIPE_TEX_MIPFILTER_LINEAR:
1169 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1170 default:
1171 case PIPE_TEX_MIPFILTER_NONE:
1172 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1173 }
1174 }
1175
1176 static unsigned si_tex_compare(unsigned compare)
1177 {
1178 switch (compare) {
1179 default:
1180 case PIPE_FUNC_NEVER:
1181 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1182 case PIPE_FUNC_LESS:
1183 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1184 case PIPE_FUNC_EQUAL:
1185 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1186 case PIPE_FUNC_LEQUAL:
1187 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1188 case PIPE_FUNC_GREATER:
1189 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1190 case PIPE_FUNC_NOTEQUAL:
1191 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1192 case PIPE_FUNC_GEQUAL:
1193 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1194 case PIPE_FUNC_ALWAYS:
1195 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1196 }
1197 }
1198
1199 static unsigned si_tex_dim(unsigned dim)
1200 {
1201 switch (dim) {
1202 default:
1203 case PIPE_TEXTURE_1D:
1204 return V_008F1C_SQ_RSRC_IMG_1D;
1205 case PIPE_TEXTURE_1D_ARRAY:
1206 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1207 case PIPE_TEXTURE_2D:
1208 case PIPE_TEXTURE_RECT:
1209 return V_008F1C_SQ_RSRC_IMG_2D;
1210 case PIPE_TEXTURE_2D_ARRAY:
1211 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1212 case PIPE_TEXTURE_3D:
1213 return V_008F1C_SQ_RSRC_IMG_3D;
1214 case PIPE_TEXTURE_CUBE:
1215 return V_008F1C_SQ_RSRC_IMG_CUBE;
1216 }
1217 }
1218
1219 /*
1220 * framebuffer handling
1221 */
1222
1223 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1224 const struct pipe_framebuffer_state *state, int cb)
1225 {
1226 struct r600_resource_texture *rtex;
1227 struct r600_surface *surf;
1228 unsigned level = state->cbufs[cb]->u.tex.level;
1229 unsigned pitch, slice;
1230 unsigned color_info, color_attrib;
1231 unsigned format, swap, ntype, endian;
1232 uint64_t offset;
1233 unsigned blocksize;
1234 const struct util_format_description *desc;
1235 int i;
1236 unsigned blend_clamp = 0, blend_bypass = 0;
1237
1238 surf = (struct r600_surface *)state->cbufs[cb];
1239 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1240 blocksize = util_format_get_blocksize(rtex->real_format);
1241
1242 if (rtex->depth)
1243 rctx->have_depth_fb = TRUE;
1244
1245 if (rtex->depth && !rtex->is_flushing_texture) {
1246 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1247 rtex = rtex->flushed_depth_texture;
1248 }
1249
1250 offset = rtex->surface.level[level].offset;
1251 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1252 offset += rtex->surface.level[level].slice_size *
1253 state->cbufs[cb]->u.tex.first_layer;
1254 }
1255 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1256 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1257 if (slice) {
1258 slice = slice - 1;
1259 }
1260
1261 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1262 switch (rtex->surface.level[level].mode) {
1263 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1264 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1265 break;
1266 case RADEON_SURF_MODE_1D:
1267 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1268 break;
1269 case RADEON_SURF_MODE_2D:
1270 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1271 switch (blocksize) {
1272 case 1:
1273 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1274 break;
1275 case 2:
1276 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1277 break;
1278 case 4:
1279 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1280 break;
1281 }
1282 break;
1283 } else switch (blocksize) {
1284 case 1:
1285 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1286 break;
1287 case 2:
1288 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1289 break;
1290 case 4:
1291 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1292 break;
1293 case 8:
1294 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1295 break;
1296 default:
1297 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1298 }
1299 break;
1300 }
1301
1302 desc = util_format_description(surf->base.format);
1303 for (i = 0; i < 4; i++) {
1304 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1305 break;
1306 }
1307 }
1308 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1309 ntype = V_028C70_NUMBER_FLOAT;
1310 } else {
1311 ntype = V_028C70_NUMBER_UNORM;
1312 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1313 ntype = V_028C70_NUMBER_SRGB;
1314 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1315 if (desc->channel[i].normalized)
1316 ntype = V_028C70_NUMBER_SNORM;
1317 else if (desc->channel[i].pure_integer)
1318 ntype = V_028C70_NUMBER_SINT;
1319 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1320 if (desc->channel[i].normalized)
1321 ntype = V_028C70_NUMBER_UNORM;
1322 else if (desc->channel[i].pure_integer)
1323 ntype = V_028C70_NUMBER_UINT;
1324 }
1325 }
1326
1327 format = si_translate_colorformat(surf->base.format);
1328 swap = si_translate_colorswap(surf->base.format);
1329 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1330 endian = V_028C70_ENDIAN_NONE;
1331 } else {
1332 endian = si_colorformat_endian_swap(format);
1333 }
1334
1335 /* blend clamp should be set for all NORM/SRGB types */
1336 if (ntype == V_028C70_NUMBER_UNORM ||
1337 ntype == V_028C70_NUMBER_SNORM ||
1338 ntype == V_028C70_NUMBER_SRGB)
1339 blend_clamp = 1;
1340
1341 /* set blend bypass according to docs if SINT/UINT or
1342 8/24 COLOR variants */
1343 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1344 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1345 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1346 blend_clamp = 0;
1347 blend_bypass = 1;
1348 }
1349
1350 color_info = S_028C70_FORMAT(format) |
1351 S_028C70_COMP_SWAP(swap) |
1352 S_028C70_BLEND_CLAMP(blend_clamp) |
1353 S_028C70_BLEND_BYPASS(blend_bypass) |
1354 S_028C70_NUMBER_TYPE(ntype) |
1355 S_028C70_ENDIAN(endian);
1356
1357 rctx->alpha_ref_dirty = true;
1358
1359 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1360 offset >>= 8;
1361
1362 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1363 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1364 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1365 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1366 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1367
1368 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1369 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1370 } else {
1371 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1372 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1373 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1374 }
1375 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1376 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1377 }
1378
1379 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1380 const struct pipe_framebuffer_state *state)
1381 {
1382 struct r600_resource_texture *rtex;
1383 struct r600_surface *surf;
1384 unsigned level, first_layer, pitch, slice, format;
1385 uint32_t db_z_info, stencil_info;
1386 uint64_t offset;
1387
1388 if (state->zsbuf == NULL) {
1389 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1390 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1391 return;
1392 }
1393
1394 surf = (struct r600_surface *)state->zsbuf;
1395 level = surf->base.u.tex.level;
1396 rtex = (struct r600_resource_texture*)surf->base.texture;
1397
1398 first_layer = surf->base.u.tex.first_layer;
1399 format = si_translate_dbformat(rtex->real_format);
1400
1401 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1402 offset += rtex->surface.level[level].offset;
1403 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1404 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1405 if (slice) {
1406 slice = slice - 1;
1407 }
1408 offset >>= 8;
1409
1410 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1411 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, offset);
1412 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, offset);
1413 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1414 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1415 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1416
1417 db_z_info = S_028040_FORMAT(format);
1418 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1419
1420 switch (format) {
1421 case V_028040_Z_16:
1422 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1423 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1424 break;
1425 case V_028040_Z_24:
1426 case V_028040_Z_32_FLOAT:
1427 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1428 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1429 break;
1430 default:
1431 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1432 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1433 }
1434
1435 if (rtex->stencil) {
1436 uint64_t stencil_offset =
1437 r600_texture_get_offset(rtex->stencil, level, first_layer);
1438
1439 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1440 stencil_offset >>= 8;
1441
1442 si_pm4_add_bo(pm4, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1443 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, stencil_offset);
1444 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, stencil_offset);
1445 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, stencil_info);
1446 } else {
1447 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1448 }
1449
1450 if (format != ~0U) {
1451 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1452 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, db_z_info);
1453 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1454 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1455
1456 } else {
1457 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1458 }
1459 }
1460
1461 static void si_set_framebuffer_state(struct pipe_context *ctx,
1462 const struct pipe_framebuffer_state *state)
1463 {
1464 struct r600_context *rctx = (struct r600_context *)ctx;
1465 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1466 uint32_t shader_mask, tl, br;
1467 int tl_x, tl_y, br_x, br_y;
1468
1469 if (pm4 == NULL)
1470 return;
1471
1472 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1473
1474 if (state->zsbuf)
1475 si_pm4_inval_zsbuf_cache(pm4);
1476
1477 util_copy_framebuffer_state(&rctx->framebuffer, state);
1478
1479 /* build states */
1480 rctx->have_depth_fb = 0;
1481 for (int i = 0; i < state->nr_cbufs; i++) {
1482 si_cb(rctx, pm4, state, i);
1483 }
1484 si_db(rctx, pm4, state);
1485
1486 shader_mask = 0;
1487 for (int i = 0; i < state->nr_cbufs; i++) {
1488 shader_mask |= 0xf << (i * 4);
1489 }
1490 tl_x = 0;
1491 tl_y = 0;
1492 br_x = state->width;
1493 br_y = state->height;
1494 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1495 /* EG hw workaround */
1496 if (br_x == 0)
1497 tl_x = 1;
1498 if (br_y == 0)
1499 tl_y = 1;
1500 /* cayman hw workaround */
1501 if (rctx->chip_class == CAYMAN) {
1502 if (br_x == 1 && br_y == 1)
1503 br_x = 2;
1504 }
1505 #endif
1506 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1507 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1508
1509 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1510 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1511 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1512 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1513 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1514 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1515 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1516 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1517 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1518 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1519 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1520 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1521
1522 si_pm4_set_state(rctx, framebuffer, pm4);
1523 si_update_fb_rs_state(rctx);
1524 si_update_fb_blend_state(rctx);
1525 }
1526
1527 /*
1528 * shaders
1529 */
1530
1531 static void *si_create_shader_state(struct pipe_context *ctx,
1532 const struct pipe_shader_state *state)
1533 {
1534 struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
1535
1536 shader->tokens = tgsi_dup_tokens(state->tokens);
1537 shader->so = state->stream_output;
1538
1539 return shader;
1540 }
1541
1542 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1543 {
1544 struct r600_context *rctx = (struct r600_context *)ctx;
1545 struct si_pipe_shader *shader = state;
1546
1547 if (rctx->vs_shader == state)
1548 return;
1549
1550 rctx->shader_dirty = true;
1551 rctx->vs_shader = shader;
1552 si_pm4_bind_state(rctx, vs, shader->pm4);
1553 }
1554
1555 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1556 {
1557 struct r600_context *rctx = (struct r600_context *)ctx;
1558 struct si_pipe_shader *shader = state;
1559
1560 if (rctx->ps_shader == state)
1561 return;
1562
1563 rctx->shader_dirty = true;
1564 rctx->ps_shader = shader;
1565 si_pm4_bind_state(rctx, ps, shader->pm4);
1566 }
1567
1568 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
1569 {
1570 struct r600_context *rctx = (struct r600_context *)ctx;
1571 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1572
1573 if (rctx->vs_shader == shader) {
1574 rctx->vs_shader = NULL;
1575 }
1576
1577 si_pm4_delete_state(rctx, vs, shader->pm4);
1578 free(shader->tokens);
1579 si_pipe_shader_destroy(ctx, shader);
1580 free(shader);
1581 }
1582
1583 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
1584 {
1585 struct r600_context *rctx = (struct r600_context *)ctx;
1586 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1587
1588 if (rctx->ps_shader == shader) {
1589 rctx->ps_shader = NULL;
1590 }
1591
1592 si_pm4_delete_state(rctx, ps, shader->pm4);
1593 free(shader->tokens);
1594 si_pipe_shader_destroy(ctx, shader);
1595 free(shader);
1596 }
1597
1598 /*
1599 * Samplers
1600 */
1601
1602 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
1603 struct pipe_resource *texture,
1604 const struct pipe_sampler_view *state)
1605 {
1606 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1607 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1608 const struct util_format_description *desc = util_format_description(state->format);
1609 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
1610 unsigned format, num_format, /*endian,*/ tiling_index;
1611 uint32_t pitch = 0;
1612 unsigned char state_swizzle[4], swizzle[4];
1613 unsigned height, depth, width;
1614 int first_non_void;
1615 uint64_t va;
1616
1617 if (view == NULL)
1618 return NULL;
1619
1620 /* initialize base object */
1621 view->base = *state;
1622 view->base.texture = NULL;
1623 pipe_reference(NULL, &texture->reference);
1624 view->base.texture = texture;
1625 view->base.reference.count = 1;
1626 view->base.context = ctx;
1627
1628 state_swizzle[0] = state->swizzle_r;
1629 state_swizzle[1] = state->swizzle_g;
1630 state_swizzle[2] = state->swizzle_b;
1631 state_swizzle[3] = state->swizzle_a;
1632 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
1633
1634 first_non_void = util_format_get_first_non_void_channel(state->format);
1635 switch (desc->channel[first_non_void].type) {
1636 case UTIL_FORMAT_TYPE_FLOAT:
1637 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
1638 break;
1639 case UTIL_FORMAT_TYPE_SIGNED:
1640 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
1641 break;
1642 case UTIL_FORMAT_TYPE_UNSIGNED:
1643 default:
1644 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
1645 }
1646
1647 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
1648 if (format == ~0) {
1649 format = 0;
1650 }
1651
1652 if (tmp->depth && !tmp->is_flushing_texture) {
1653 r600_texture_depth_flush(ctx, texture, TRUE);
1654 tmp = tmp->flushed_depth_texture;
1655 }
1656
1657 /* not supported any more */
1658 //endian = si_colorformat_endian_swap(format);
1659
1660 height = texture->height0;
1661 depth = texture->depth0;
1662 width = texture->width0;
1663 pitch = align(tmp->pitch_in_blocks[0] *
1664 util_format_get_blockwidth(state->format), 8);
1665
1666 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1667 height = 1;
1668 depth = texture->array_size;
1669 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1670 depth = texture->array_size;
1671 }
1672
1673 tiling_index = 8;
1674 switch (tmp->surface.level[state->u.tex.first_level].mode) {
1675 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1676 tiling_index = 8;
1677 break;
1678 case RADEON_SURF_MODE_1D:
1679 tiling_index = 9;
1680 break;
1681 case RADEON_SURF_MODE_2D:
1682 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1683 switch (blocksize) {
1684 case 1:
1685 tiling_index = 10;
1686 break;
1687 case 2:
1688 tiling_index = 11;
1689 break;
1690 case 4:
1691 tiling_index = 12;
1692 break;
1693 }
1694 break;
1695 } else switch (blocksize) {
1696 case 1:
1697 tiling_index = 14;
1698 break;
1699 case 2:
1700 tiling_index = 15;
1701 break;
1702 case 4:
1703 tiling_index = 16;
1704 break;
1705 case 8:
1706 tiling_index = 17;
1707 break;
1708 default:
1709 tiling_index = 13;
1710 }
1711 break;
1712 }
1713
1714 va = r600_resource_va(ctx->screen, texture);
1715 if (state->u.tex.last_level) {
1716 view->state[0] = (va + tmp->offset[1]) >> 8;
1717 } else {
1718 view->state[0] = (va + tmp->offset[0]) >> 8;
1719 }
1720 view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
1721 S_008F14_DATA_FORMAT(format) |
1722 S_008F14_NUM_FORMAT(num_format));
1723 view->state[2] = (S_008F18_WIDTH(width - 1) |
1724 S_008F18_HEIGHT(height - 1));
1725 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
1726 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
1727 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
1728 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
1729 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
1730 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
1731 S_008F1C_TILING_INDEX(tiling_index) |
1732 S_008F1C_TYPE(si_tex_dim(texture->target)));
1733 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
1734 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
1735 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
1736 view->state[6] = 0;
1737 view->state[7] = 0;
1738
1739 return &view->base;
1740 }
1741
1742 static void *si_create_sampler_state(struct pipe_context *ctx,
1743 const struct pipe_sampler_state *state)
1744 {
1745 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
1746 union util_color uc;
1747 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1748 unsigned border_color_type;
1749
1750 if (rstate == NULL) {
1751 return NULL;
1752 }
1753
1754 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1755 switch (uc.ui) {
1756 case 0x000000FF:
1757 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1758 break;
1759 case 0x00000000:
1760 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1761 break;
1762 case 0xFFFFFFFF:
1763 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1764 break;
1765 default: /* Use border color pointer */
1766 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
1767 }
1768
1769 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
1770 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
1771 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
1772 (state->max_anisotropy & 0x7) << 9 | /* XXX */
1773 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
1774 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
1775 aniso_flag_offset << 16 | /* XXX */
1776 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
1777 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1778 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
1779 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1780 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
1781 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
1782 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
1783 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
1784
1785 #if 0
1786 if (border_color_type == 3) {
1787 si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]));
1788 si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]));
1789 si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]));
1790 si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]));
1791 }
1792 #endif
1793 return rstate;
1794 }
1795
1796 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1797 struct pipe_sampler_view **views)
1798 {
1799 assert(count == 0);
1800 }
1801
1802 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1803 struct pipe_sampler_view **views)
1804 {
1805 struct r600_context *rctx = (struct r600_context *)ctx;
1806 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1807 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1808 struct r600_resource *bo;
1809 int i;
1810 int has_depth = 0;
1811 uint64_t va;
1812 char *ptr;
1813
1814 if (!count)
1815 goto out;
1816
1817 si_pm4_inval_texture_cache(pm4);
1818
1819 bo = (struct r600_resource*)
1820 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1821 count * sizeof(resource[0]->state));
1822 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1823
1824 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1825 struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
1826
1827 pipe_sampler_view_reference(
1828 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1829 views[i]);
1830
1831 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
1832
1833 if (resource[i]) {
1834 if (tex->depth)
1835 has_depth = 1;
1836
1837 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1838 } else
1839 memset(ptr, 0, sizeof(resource[0]->state));
1840 }
1841
1842 rctx->ws->buffer_unmap(bo->cs_buf);
1843
1844 for (i = count; i < NUM_TEX_UNITS; i++) {
1845 if (rctx->ps_samplers.views[i])
1846 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1847 }
1848
1849 va = r600_resource_va(ctx->screen, (void *)bo);
1850 si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
1851 si_pm4_set_reg(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4, va);
1852 si_pm4_set_reg(pm4, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32);
1853
1854 out:
1855 si_pm4_set_state(rctx, ps_sampler_views, pm4);
1856 rctx->have_depth_texture = has_depth;
1857 rctx->ps_samplers.n_views = count;
1858 }
1859
1860 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1861 {
1862 assert(0);
1863 }
1864
1865 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1866 {
1867 struct r600_context *rctx = (struct r600_context *)ctx;
1868 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
1869 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1870 struct r600_resource *bo;
1871 uint64_t va;
1872 char *ptr;
1873 int i;
1874
1875 if (!count)
1876 goto out;
1877
1878 si_pm4_inval_texture_cache(pm4);
1879
1880 bo = (struct r600_resource*)
1881 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1882 count * sizeof(rstates[0]->val));
1883 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1884
1885 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
1886 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
1887 }
1888
1889 rctx->ws->buffer_unmap(bo->cs_buf);
1890
1891 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1892
1893 va = r600_resource_va(ctx->screen, (void *)bo);
1894 si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
1895 si_pm4_set_reg(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2, va);
1896 si_pm4_set_reg(pm4, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32);
1897
1898 out:
1899 si_pm4_set_state(rctx, ps_sampler, pm4);
1900 rctx->ps_samplers.n_samplers = count;
1901 }
1902
1903 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1904 {
1905 }
1906
1907 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
1908 {
1909 free(state);
1910 }
1911
1912 /*
1913 * Constants
1914 */
1915 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1916 struct pipe_constant_buffer *cb)
1917 {
1918 struct r600_context *rctx = (struct r600_context *)ctx;
1919 struct r600_resource *rbuffer = cb ? r600_resource(cb->buffer) : NULL;
1920 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1921 uint64_t va_offset;
1922 uint32_t offset;
1923
1924 /* Note that the state tracker can unbind constant buffers by
1925 * passing NULL here.
1926 */
1927 if (cb == NULL) {
1928 FREE(pm4);
1929 return;
1930 }
1931
1932 si_pm4_inval_shader_cache(pm4);
1933
1934 if (cb->user_buffer)
1935 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
1936 else
1937 offset = 0;
1938 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
1939 va_offset += offset;
1940
1941 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
1942
1943 switch (shader) {
1944 case PIPE_SHADER_VERTEX:
1945 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset);
1946 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32);
1947 si_pm4_set_state(rctx, vs_const, pm4);
1948 break;
1949
1950 case PIPE_SHADER_FRAGMENT:
1951 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset);
1952 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32);
1953 si_pm4_set_state(rctx, ps_const, pm4);
1954 break;
1955
1956 default:
1957 R600_ERR("unsupported %d\n", shader);
1958 return;
1959 }
1960
1961 if (cb->buffer != &rbuffer->b.b)
1962 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
1963 }
1964
1965 void si_init_state_functions(struct r600_context *rctx)
1966 {
1967 rctx->context.create_blend_state = si_create_blend_state;
1968 rctx->context.bind_blend_state = si_bind_blend_state;
1969 rctx->context.delete_blend_state = si_delete_blend_state;
1970 rctx->context.set_blend_color = si_set_blend_color;
1971
1972 rctx->context.create_rasterizer_state = si_create_rs_state;
1973 rctx->context.bind_rasterizer_state = si_bind_rs_state;
1974 rctx->context.delete_rasterizer_state = si_delete_rs_state;
1975
1976 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
1977 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
1978 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
1979 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
1980
1981 rctx->context.set_clip_state = si_set_clip_state;
1982 rctx->context.set_scissor_state = si_set_scissor_state;
1983 rctx->context.set_viewport_state = si_set_viewport_state;
1984 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
1985
1986 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
1987
1988 rctx->context.create_vs_state = si_create_shader_state;
1989 rctx->context.create_fs_state = si_create_shader_state;
1990 rctx->context.bind_vs_state = si_bind_vs_shader;
1991 rctx->context.bind_fs_state = si_bind_ps_shader;
1992 rctx->context.delete_vs_state = si_delete_vs_shader;
1993 rctx->context.delete_fs_state = si_delete_ps_shader;
1994
1995 rctx->context.create_sampler_state = si_create_sampler_state;
1996 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
1997 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
1998 rctx->context.delete_sampler_state = si_delete_sampler_state;
1999
2000 rctx->context.create_sampler_view = si_create_sampler_view;
2001 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2002 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2003
2004 rctx->context.set_sample_mask = si_set_sample_mask;
2005
2006 rctx->context.set_constant_buffer = si_set_constant_buffer;
2007
2008 rctx->context.draw_vbo = si_draw_vbo;
2009 }
2010
2011 void si_init_config(struct r600_context *rctx)
2012 {
2013 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2014
2015 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2016
2017 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2018 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2019 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2020 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2021 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2022 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2023 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2024 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2025 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2026 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2027 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2028 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2029 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2030 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2031 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2032 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2033 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2034 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2035 S_028AA8_SWITCH_ON_EOP(1) |
2036 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2037 S_028AA8_PRIMGROUP_SIZE(63));
2038 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2039 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2040 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2041
2042 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2043 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2044 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2045
2046 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2047
2048 si_pm4_set_state(rctx, init, pm4);
2049 }