projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: remove upload code for zero-stride vertex attribs
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
607 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
608 sctx->do_update_shaders = true;
609 }
610
611 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
612 {
613 struct si_context *sctx = (struct si_context *)ctx;
614 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
615 }
616
617 static void si_set_blend_color(struct pipe_context *ctx,
618 const struct pipe_blend_color *state)
619 {
620 struct si_context *sctx = (struct si_context *)ctx;
621
622 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
623 return;
624
625 sctx->blend_color.state = *state;
626 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
627 }
628
629 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
630 {
631 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
632
633 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
634 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
635 }
636
637 /*
638 * Clipping
639 */
640
641 static void si_set_clip_state(struct pipe_context *ctx,
642 const struct pipe_clip_state *state)
643 {
644 struct si_context *sctx = (struct si_context *)ctx;
645 struct pipe_constant_buffer cb;
646
647 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
648 return;
649
650 sctx->clip_state.state = *state;
651 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
652
653 cb.buffer = NULL;
654 cb.user_buffer = state->ucp;
655 cb.buffer_offset = 0;
656 cb.buffer_size = 4*4*8;
657 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
658 pipe_resource_reference(&cb.buffer, NULL);
659 }
660
661 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
662 {
663 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
664
665 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
666 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
667 }
668
669 #define SIX_BITS 0x3F
670
671 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
672 {
673 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
674 struct si_shader *vs = si_get_vs_state(sctx);
675 struct tgsi_shader_info *info = si_get_vs_info(sctx);
676 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
677 unsigned window_space =
678 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
679 unsigned clipdist_mask =
680 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
681 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
682 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
683 unsigned total_mask;
684 bool misc_vec_ena;
685
686 if (vs->key.opt.hw_vs.clip_disable) {
687 assert(!info->culldist_writemask);
688 clipdist_mask = 0;
689 culldist_mask = 0;
690 }
691 total_mask = clipdist_mask | culldist_mask;
692
693 /* Clip distances on points have no effect, so need to be implemented
694 * as cull distances. This applies for the clipvertex case as well.
695 *
696 * Setting this for primitives other than points should have no adverse
697 * effects.
698 */
699 clipdist_mask &= rs->clip_plane_enable;
700 culldist_mask |= clipdist_mask;
701
702 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
703 info->writes_layer || info->writes_viewport_index;
704
705 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
706 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
707 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
708 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
709 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
710 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
711 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
712 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
713 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
714 clipdist_mask | (culldist_mask << 8));
715 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
716 rs->pa_cl_clip_cntl |
717 ucp_mask |
718 S_028810_CLIP_DISABLE(window_space));
719
720 if (sctx->b.chip_class <= VI) {
721 /* reuse needs to be set off if we write oViewport */
722 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
723 S_028AB4_REUSE_OFF(info->writes_viewport_index));
724 }
725 }
726
727 /*
728 * inferred state between framebuffer and rasterizer
729 */
730 static void si_update_poly_offset_state(struct si_context *sctx)
731 {
732 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
733
734 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
735 si_pm4_bind_state(sctx, poly_offset, NULL);
736 return;
737 }
738
739 /* Use the user format, not db_render_format, so that the polygon
740 * offset behaves as expected by applications.
741 */
742 switch (sctx->framebuffer.state.zsbuf->texture->format) {
743 case PIPE_FORMAT_Z16_UNORM:
744 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
745 break;
746 default: /* 24-bit */
747 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
748 break;
749 case PIPE_FORMAT_Z32_FLOAT:
750 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
751 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
752 break;
753 }
754 }
755
756 /*
757 * Rasterizer
758 */
759
760 static uint32_t si_translate_fill(uint32_t func)
761 {
762 switch(func) {
763 case PIPE_POLYGON_MODE_FILL:
764 return V_028814_X_DRAW_TRIANGLES;
765 case PIPE_POLYGON_MODE_LINE:
766 return V_028814_X_DRAW_LINES;
767 case PIPE_POLYGON_MODE_POINT:
768 return V_028814_X_DRAW_POINTS;
769 default:
770 assert(0);
771 return V_028814_X_DRAW_POINTS;
772 }
773 }
774
775 static void *si_create_rs_state(struct pipe_context *ctx,
776 const struct pipe_rasterizer_state *state)
777 {
778 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
779 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
780 struct si_pm4_state *pm4 = &rs->pm4;
781 unsigned tmp, i;
782 float psize_min, psize_max;
783
784 if (!rs) {
785 return NULL;
786 }
787
788 rs->scissor_enable = state->scissor;
789 rs->clip_halfz = state->clip_halfz;
790 rs->two_side = state->light_twoside;
791 rs->multisample_enable = state->multisample;
792 rs->force_persample_interp = state->force_persample_interp;
793 rs->clip_plane_enable = state->clip_plane_enable;
794 rs->line_stipple_enable = state->line_stipple_enable;
795 rs->poly_stipple_enable = state->poly_stipple_enable;
796 rs->line_smooth = state->line_smooth;
797 rs->poly_smooth = state->poly_smooth;
798 rs->uses_poly_offset = state->offset_point || state->offset_line ||
799 state->offset_tri;
800 rs->clamp_fragment_color = state->clamp_fragment_color;
801 rs->clamp_vertex_color = state->clamp_vertex_color;
802 rs->flatshade = state->flatshade;
803 rs->sprite_coord_enable = state->sprite_coord_enable;
804 rs->rasterizer_discard = state->rasterizer_discard;
805 rs->pa_sc_line_stipple = state->line_stipple_enable ?
806 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
807 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
808 rs->pa_cl_clip_cntl =
809 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
810 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
811 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
812 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
813 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
814
815 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
816 S_0286D4_FLAT_SHADE_ENA(1) |
817 S_0286D4_PNT_SPRITE_ENA(1) |
818 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
819 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
820 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
821 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
822 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
823
824 /* point size 12.4 fixed point */
825 tmp = (unsigned)(state->point_size * 8.0);
826 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
827
828 if (state->point_size_per_vertex) {
829 psize_min = util_get_min_point_size(state);
830 psize_max = 8192;
831 } else {
832 /* Force the point size to be as if the vertex output was disabled. */
833 psize_min = state->point_size;
834 psize_max = state->point_size;
835 }
836 /* Divide by two, because 0.5 = 1 pixel. */
837 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
838 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
839 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
840
841 tmp = (unsigned)state->line_width * 8;
842 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
843 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
844 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
845 S_028A48_MSAA_ENABLE(state->multisample ||
846 state->poly_smooth ||
847 state->line_smooth) |
848 S_028A48_VPORT_SCISSOR_ENABLE(1) |
849 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
850
851 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
852 S_028BE4_PIX_CENTER(state->half_pixel_center) |
853 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
854
855 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
856 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
857 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
858 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
859 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
860 S_028814_FACE(!state->front_ccw) |
861 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
862 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
863 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
864 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
865 state->fill_back != PIPE_POLYGON_MODE_FILL) |
866 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
867 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
868
869 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
870 for (i = 0; i < 3; i++) {
871 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
872 float offset_units = state->offset_units;
873 float offset_scale = state->offset_scale * 16.0f;
874 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
875
876 if (!state->offset_units_unscaled) {
877 switch (i) {
878 case 0: /* 16-bit zbuffer */
879 offset_units *= 4.0f;
880 pa_su_poly_offset_db_fmt_cntl =
881 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
882 break;
883 case 1: /* 24-bit zbuffer */
884 offset_units *= 2.0f;
885 pa_su_poly_offset_db_fmt_cntl =
886 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
887 break;
888 case 2: /* 32-bit zbuffer */
889 offset_units *= 1.0f;
890 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
891 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
892 break;
893 }
894 }
895
896 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
897 fui(offset_scale));
898 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
899 fui(offset_units));
900 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
901 fui(offset_scale));
902 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
903 fui(offset_units));
904 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
905 pa_su_poly_offset_db_fmt_cntl);
906 }
907
908 return rs;
909 }
910
911 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
912 {
913 struct si_context *sctx = (struct si_context *)ctx;
914 struct si_state_rasterizer *old_rs =
915 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
916 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
917
918 if (!state)
919 return;
920
921 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
922 si_mark_atom_dirty(sctx, &sctx->db_render_state);
923
924 /* Update the small primitive filter workaround if necessary. */
925 if (sctx->screen->has_msaa_sample_loc_bug &&
926 sctx->framebuffer.nr_samples > 1)
927 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
928 }
929
930 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
931 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
932
933 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
934
935 si_pm4_bind_state(sctx, rasterizer, rs);
936 si_update_poly_offset_state(sctx);
937
938 si_mark_atom_dirty(sctx, &sctx->clip_regs);
939 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
940 rs->line_stipple_enable;
941 sctx->do_update_shaders = true;
942 }
943
944 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
945 {
946 struct si_context *sctx = (struct si_context *)ctx;
947
948 if (sctx->queued.named.rasterizer == state)
949 si_pm4_bind_state(sctx, poly_offset, NULL);
950 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
951 }
952
953 /*
954 * infeered state between dsa and stencil ref
955 */
956 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
957 {
958 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
959 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
960 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
961
962 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
963 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
964 S_028430_STENCILMASK(dsa->valuemask[0]) |
965 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
966 S_028430_STENCILOPVAL(1));
967 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
968 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
969 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
970 S_028434_STENCILOPVAL_BF(1));
971 }
972
973 static void si_set_stencil_ref(struct pipe_context *ctx,
974 const struct pipe_stencil_ref *state)
975 {
976 struct si_context *sctx = (struct si_context *)ctx;
977
978 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
979 return;
980
981 sctx->stencil_ref.state = *state;
982 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
983 }
984
985
986 /*
987 * DSA
988 */
989
990 static uint32_t si_translate_stencil_op(int s_op)
991 {
992 switch (s_op) {
993 case PIPE_STENCIL_OP_KEEP:
994 return V_02842C_STENCIL_KEEP;
995 case PIPE_STENCIL_OP_ZERO:
996 return V_02842C_STENCIL_ZERO;
997 case PIPE_STENCIL_OP_REPLACE:
998 return V_02842C_STENCIL_REPLACE_TEST;
999 case PIPE_STENCIL_OP_INCR:
1000 return V_02842C_STENCIL_ADD_CLAMP;
1001 case PIPE_STENCIL_OP_DECR:
1002 return V_02842C_STENCIL_SUB_CLAMP;
1003 case PIPE_STENCIL_OP_INCR_WRAP:
1004 return V_02842C_STENCIL_ADD_WRAP;
1005 case PIPE_STENCIL_OP_DECR_WRAP:
1006 return V_02842C_STENCIL_SUB_WRAP;
1007 case PIPE_STENCIL_OP_INVERT:
1008 return V_02842C_STENCIL_INVERT;
1009 default:
1010 R600_ERR("Unknown stencil op %d", s_op);
1011 assert(0);
1012 break;
1013 }
1014 return 0;
1015 }
1016
1017 static void *si_create_dsa_state(struct pipe_context *ctx,
1018 const struct pipe_depth_stencil_alpha_state *state)
1019 {
1020 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1021 struct si_pm4_state *pm4 = &dsa->pm4;
1022 unsigned db_depth_control;
1023 uint32_t db_stencil_control = 0;
1024
1025 if (!dsa) {
1026 return NULL;
1027 }
1028
1029 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1030 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1031 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1032 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1033
1034 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1035 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1036 S_028800_ZFUNC(state->depth.func) |
1037 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1038
1039 /* stencil */
1040 if (state->stencil[0].enabled) {
1041 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1042 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1043 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1044 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1045 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1046
1047 if (state->stencil[1].enabled) {
1048 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1049 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1050 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1051 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1052 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1053 }
1054 }
1055
1056 /* alpha */
1057 if (state->alpha.enabled) {
1058 dsa->alpha_func = state->alpha.func;
1059
1060 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1061 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1062 } else {
1063 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1064 }
1065
1066 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1067 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1068 if (state->depth.bounds_test) {
1069 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1070 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1071 }
1072
1073 return dsa;
1074 }
1075
1076 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1077 {
1078 struct si_context *sctx = (struct si_context *)ctx;
1079 struct si_state_dsa *dsa = state;
1080
1081 if (!state)
1082 return;
1083
1084 si_pm4_bind_state(sctx, dsa, dsa);
1085
1086 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1087 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1088 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1089 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1090 }
1091 sctx->do_update_shaders = true;
1092 }
1093
1094 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1095 {
1096 struct si_context *sctx = (struct si_context *)ctx;
1097 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1098 }
1099
1100 static void *si_create_db_flush_dsa(struct si_context *sctx)
1101 {
1102 struct pipe_depth_stencil_alpha_state dsa = {};
1103
1104 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1105 }
1106
1107 /* DB RENDER STATE */
1108
1109 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1110 {
1111 struct si_context *sctx = (struct si_context*)ctx;
1112
1113 /* Pipeline stat & streamout queries. */
1114 if (enable) {
1115 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1116 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1117 } else {
1118 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1119 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1120 }
1121
1122 /* Occlusion queries. */
1123 if (sctx->occlusion_queries_disabled != !enable) {
1124 sctx->occlusion_queries_disabled = !enable;
1125 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1126 }
1127 }
1128
1129 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1130 {
1131 struct si_context *sctx = (struct si_context*)ctx;
1132
1133 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1134 }
1135
1136 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1137 {
1138 struct si_context *sctx = (struct si_context*)ctx;
1139
1140 st->saved_compute = sctx->cs_shader_state.program;
1141
1142 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1143 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1144 }
1145
1146 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1147 {
1148 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1149 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1150 unsigned db_shader_control;
1151
1152 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1153
1154 /* DB_RENDER_CONTROL */
1155 if (sctx->dbcb_depth_copy_enabled ||
1156 sctx->dbcb_stencil_copy_enabled) {
1157 radeon_emit(cs,
1158 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1159 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1160 S_028000_COPY_CENTROID(1) |
1161 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1162 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1163 radeon_emit(cs,
1164 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1165 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1166 } else {
1167 radeon_emit(cs,
1168 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1169 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1170 }
1171
1172 /* DB_COUNT_CONTROL (occlusion queries) */
1173 if (sctx->b.num_occlusion_queries > 0 &&
1174 !sctx->occlusion_queries_disabled) {
1175 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1176
1177 if (sctx->b.chip_class >= CIK) {
1178 radeon_emit(cs,
1179 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1180 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1181 S_028004_ZPASS_ENABLE(1) |
1182 S_028004_SLICE_EVEN_ENABLE(1) |
1183 S_028004_SLICE_ODD_ENABLE(1));
1184 } else {
1185 radeon_emit(cs,
1186 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1187 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1188 }
1189 } else {
1190 /* Disable occlusion queries. */
1191 if (sctx->b.chip_class >= CIK) {
1192 radeon_emit(cs, 0);
1193 } else {
1194 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1195 }
1196 }
1197
1198 /* DB_RENDER_OVERRIDE2 */
1199 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1200 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1201 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1202 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1203
1204 db_shader_control = sctx->ps_db_shader_control;
1205
1206 /* Bug workaround for smoothing (overrasterization) on SI. */
1207 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1208 db_shader_control &= C_02880C_Z_ORDER;
1209 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1210 }
1211
1212 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1213 if (!rs || !rs->multisample_enable)
1214 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1215
1216 if (sctx->screen->b.has_rbplus &&
1217 !sctx->screen->b.rbplus_allowed)
1218 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1219
1220 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1221 db_shader_control);
1222 }
1223
1224 /*
1225 * format translation
1226 */
1227 static uint32_t si_translate_colorformat(enum pipe_format format)
1228 {
1229 const struct util_format_description *desc = util_format_description(format);
1230
1231 #define HAS_SIZE(x,y,z,w) \
1232 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1233 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1234
1235 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1236 return V_028C70_COLOR_10_11_11;
1237
1238 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1239 return V_028C70_COLOR_INVALID;
1240
1241 /* hw cannot support mixed formats (except depth/stencil, since
1242 * stencil is not written to). */
1243 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1244 return V_028C70_COLOR_INVALID;
1245
1246 switch (desc->nr_channels) {
1247 case 1:
1248 switch (desc->channel[0].size) {
1249 case 8:
1250 return V_028C70_COLOR_8;
1251 case 16:
1252 return V_028C70_COLOR_16;
1253 case 32:
1254 return V_028C70_COLOR_32;
1255 }
1256 break;
1257 case 2:
1258 if (desc->channel[0].size == desc->channel[1].size) {
1259 switch (desc->channel[0].size) {
1260 case 8:
1261 return V_028C70_COLOR_8_8;
1262 case 16:
1263 return V_028C70_COLOR_16_16;
1264 case 32:
1265 return V_028C70_COLOR_32_32;
1266 }
1267 } else if (HAS_SIZE(8,24,0,0)) {
1268 return V_028C70_COLOR_24_8;
1269 } else if (HAS_SIZE(24,8,0,0)) {
1270 return V_028C70_COLOR_8_24;
1271 }
1272 break;
1273 case 3:
1274 if (HAS_SIZE(5,6,5,0)) {
1275 return V_028C70_COLOR_5_6_5;
1276 } else if (HAS_SIZE(32,8,24,0)) {
1277 return V_028C70_COLOR_X24_8_32_FLOAT;
1278 }
1279 break;
1280 case 4:
1281 if (desc->channel[0].size == desc->channel[1].size &&
1282 desc->channel[0].size == desc->channel[2].size &&
1283 desc->channel[0].size == desc->channel[3].size) {
1284 switch (desc->channel[0].size) {
1285 case 4:
1286 return V_028C70_COLOR_4_4_4_4;
1287 case 8:
1288 return V_028C70_COLOR_8_8_8_8;
1289 case 16:
1290 return V_028C70_COLOR_16_16_16_16;
1291 case 32:
1292 return V_028C70_COLOR_32_32_32_32;
1293 }
1294 } else if (HAS_SIZE(5,5,5,1)) {
1295 return V_028C70_COLOR_1_5_5_5;
1296 } else if (HAS_SIZE(10,10,10,2)) {
1297 return V_028C70_COLOR_2_10_10_10;
1298 }
1299 break;
1300 }
1301 return V_028C70_COLOR_INVALID;
1302 }
1303
1304 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1305 {
1306 if (SI_BIG_ENDIAN) {
1307 switch(colorformat) {
1308 /* 8-bit buffers. */
1309 case V_028C70_COLOR_8:
1310 return V_028C70_ENDIAN_NONE;
1311
1312 /* 16-bit buffers. */
1313 case V_028C70_COLOR_5_6_5:
1314 case V_028C70_COLOR_1_5_5_5:
1315 case V_028C70_COLOR_4_4_4_4:
1316 case V_028C70_COLOR_16:
1317 case V_028C70_COLOR_8_8:
1318 return V_028C70_ENDIAN_8IN16;
1319
1320 /* 32-bit buffers. */
1321 case V_028C70_COLOR_8_8_8_8:
1322 case V_028C70_COLOR_2_10_10_10:
1323 case V_028C70_COLOR_8_24:
1324 case V_028C70_COLOR_24_8:
1325 case V_028C70_COLOR_16_16:
1326 return V_028C70_ENDIAN_8IN32;
1327
1328 /* 64-bit buffers. */
1329 case V_028C70_COLOR_16_16_16_16:
1330 return V_028C70_ENDIAN_8IN16;
1331
1332 case V_028C70_COLOR_32_32:
1333 return V_028C70_ENDIAN_8IN32;
1334
1335 /* 128-bit buffers. */
1336 case V_028C70_COLOR_32_32_32_32:
1337 return V_028C70_ENDIAN_8IN32;
1338 default:
1339 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1340 }
1341 } else {
1342 return V_028C70_ENDIAN_NONE;
1343 }
1344 }
1345
1346 static uint32_t si_translate_dbformat(enum pipe_format format)
1347 {
1348 switch (format) {
1349 case PIPE_FORMAT_Z16_UNORM:
1350 return V_028040_Z_16;
1351 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1352 case PIPE_FORMAT_X8Z24_UNORM:
1353 case PIPE_FORMAT_Z24X8_UNORM:
1354 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1355 return V_028040_Z_24; /* deprecated on SI */
1356 case PIPE_FORMAT_Z32_FLOAT:
1357 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1358 return V_028040_Z_32_FLOAT;
1359 default:
1360 return V_028040_Z_INVALID;
1361 }
1362 }
1363
1364 /*
1365 * Texture translation
1366 */
1367
1368 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1369 enum pipe_format format,
1370 const struct util_format_description *desc,
1371 int first_non_void)
1372 {
1373 struct si_screen *sscreen = (struct si_screen*)screen;
1374 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1375 sscreen->b.info.drm_minor >= 31) ||
1376 sscreen->b.info.drm_major == 3;
1377 bool uniform = true;
1378 int i;
1379
1380 /* Colorspace (return non-RGB formats directly). */
1381 switch (desc->colorspace) {
1382 /* Depth stencil formats */
1383 case UTIL_FORMAT_COLORSPACE_ZS:
1384 switch (format) {
1385 case PIPE_FORMAT_Z16_UNORM:
1386 return V_008F14_IMG_DATA_FORMAT_16;
1387 case PIPE_FORMAT_X24S8_UINT:
1388 case PIPE_FORMAT_S8X24_UINT:
1389 /*
1390 * Implemented as an 8_8_8_8 data format to fix texture
1391 * gathers in stencil sampling. This affects at least
1392 * GL45-CTS.texture_cube_map_array.sampling on VI.
1393 */
1394 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1395 case PIPE_FORMAT_Z24X8_UNORM:
1396 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1397 return V_008F14_IMG_DATA_FORMAT_8_24;
1398 case PIPE_FORMAT_X8Z24_UNORM:
1399 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1400 return V_008F14_IMG_DATA_FORMAT_24_8;
1401 case PIPE_FORMAT_S8_UINT:
1402 return V_008F14_IMG_DATA_FORMAT_8;
1403 case PIPE_FORMAT_Z32_FLOAT:
1404 return V_008F14_IMG_DATA_FORMAT_32;
1405 case PIPE_FORMAT_X32_S8X24_UINT:
1406 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1407 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1408 default:
1409 goto out_unknown;
1410 }
1411
1412 case UTIL_FORMAT_COLORSPACE_YUV:
1413 goto out_unknown; /* TODO */
1414
1415 case UTIL_FORMAT_COLORSPACE_SRGB:
1416 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1417 goto out_unknown;
1418 break;
1419
1420 default:
1421 break;
1422 }
1423
1424 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1425 if (!enable_compressed_formats)
1426 goto out_unknown;
1427
1428 switch (format) {
1429 case PIPE_FORMAT_RGTC1_SNORM:
1430 case PIPE_FORMAT_LATC1_SNORM:
1431 case PIPE_FORMAT_RGTC1_UNORM:
1432 case PIPE_FORMAT_LATC1_UNORM:
1433 return V_008F14_IMG_DATA_FORMAT_BC4;
1434 case PIPE_FORMAT_RGTC2_SNORM:
1435 case PIPE_FORMAT_LATC2_SNORM:
1436 case PIPE_FORMAT_RGTC2_UNORM:
1437 case PIPE_FORMAT_LATC2_UNORM:
1438 return V_008F14_IMG_DATA_FORMAT_BC5;
1439 default:
1440 goto out_unknown;
1441 }
1442 }
1443
1444 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1445 (sscreen->b.family == CHIP_STONEY ||
1446 sscreen->b.chip_class >= GFX9)) {
1447 switch (format) {
1448 case PIPE_FORMAT_ETC1_RGB8:
1449 case PIPE_FORMAT_ETC2_RGB8:
1450 case PIPE_FORMAT_ETC2_SRGB8:
1451 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1452 case PIPE_FORMAT_ETC2_RGB8A1:
1453 case PIPE_FORMAT_ETC2_SRGB8A1:
1454 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1455 case PIPE_FORMAT_ETC2_RGBA8:
1456 case PIPE_FORMAT_ETC2_SRGBA8:
1457 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1458 case PIPE_FORMAT_ETC2_R11_UNORM:
1459 case PIPE_FORMAT_ETC2_R11_SNORM:
1460 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1461 case PIPE_FORMAT_ETC2_RG11_UNORM:
1462 case PIPE_FORMAT_ETC2_RG11_SNORM:
1463 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1464 default:
1465 goto out_unknown;
1466 }
1467 }
1468
1469 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1470 if (!enable_compressed_formats)
1471 goto out_unknown;
1472
1473 switch (format) {
1474 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1475 case PIPE_FORMAT_BPTC_SRGBA:
1476 return V_008F14_IMG_DATA_FORMAT_BC7;
1477 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1478 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1479 return V_008F14_IMG_DATA_FORMAT_BC6;
1480 default:
1481 goto out_unknown;
1482 }
1483 }
1484
1485 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1486 switch (format) {
1487 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1488 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1489 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1490 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1491 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1492 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1493 default:
1494 goto out_unknown;
1495 }
1496 }
1497
1498 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1499 if (!enable_compressed_formats)
1500 goto out_unknown;
1501
1502 if (!util_format_s3tc_enabled) {
1503 goto out_unknown;
1504 }
1505
1506 switch (format) {
1507 case PIPE_FORMAT_DXT1_RGB:
1508 case PIPE_FORMAT_DXT1_RGBA:
1509 case PIPE_FORMAT_DXT1_SRGB:
1510 case PIPE_FORMAT_DXT1_SRGBA:
1511 return V_008F14_IMG_DATA_FORMAT_BC1;
1512 case PIPE_FORMAT_DXT3_RGBA:
1513 case PIPE_FORMAT_DXT3_SRGBA:
1514 return V_008F14_IMG_DATA_FORMAT_BC2;
1515 case PIPE_FORMAT_DXT5_RGBA:
1516 case PIPE_FORMAT_DXT5_SRGBA:
1517 return V_008F14_IMG_DATA_FORMAT_BC3;
1518 default:
1519 goto out_unknown;
1520 }
1521 }
1522
1523 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1524 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1525 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1526 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1527 }
1528
1529 /* R8G8Bx_SNORM - TODO CxV8U8 */
1530
1531 /* hw cannot support mixed formats (except depth/stencil, since only
1532 * depth is read).*/
1533 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1534 goto out_unknown;
1535
1536 /* See whether the components are of the same size. */
1537 for (i = 1; i < desc->nr_channels; i++) {
1538 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1539 }
1540
1541 /* Non-uniform formats. */
1542 if (!uniform) {
1543 switch(desc->nr_channels) {
1544 case 3:
1545 if (desc->channel[0].size == 5 &&
1546 desc->channel[1].size == 6 &&
1547 desc->channel[2].size == 5) {
1548 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1549 }
1550 goto out_unknown;
1551 case 4:
1552 if (desc->channel[0].size == 5 &&
1553 desc->channel[1].size == 5 &&
1554 desc->channel[2].size == 5 &&
1555 desc->channel[3].size == 1) {
1556 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1557 }
1558 if (desc->channel[0].size == 10 &&
1559 desc->channel[1].size == 10 &&
1560 desc->channel[2].size == 10 &&
1561 desc->channel[3].size == 2) {
1562 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1563 }
1564 goto out_unknown;
1565 }
1566 goto out_unknown;
1567 }
1568
1569 if (first_non_void < 0 || first_non_void > 3)
1570 goto out_unknown;
1571
1572 /* uniform formats */
1573 switch (desc->channel[first_non_void].size) {
1574 case 4:
1575 switch (desc->nr_channels) {
1576 #if 0 /* Not supported for render targets */
1577 case 2:
1578 return V_008F14_IMG_DATA_FORMAT_4_4;
1579 #endif
1580 case 4:
1581 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1582 }
1583 break;
1584 case 8:
1585 switch (desc->nr_channels) {
1586 case 1:
1587 return V_008F14_IMG_DATA_FORMAT_8;
1588 case 2:
1589 return V_008F14_IMG_DATA_FORMAT_8_8;
1590 case 4:
1591 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1592 }
1593 break;
1594 case 16:
1595 switch (desc->nr_channels) {
1596 case 1:
1597 return V_008F14_IMG_DATA_FORMAT_16;
1598 case 2:
1599 return V_008F14_IMG_DATA_FORMAT_16_16;
1600 case 4:
1601 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1602 }
1603 break;
1604 case 32:
1605 switch (desc->nr_channels) {
1606 case 1:
1607 return V_008F14_IMG_DATA_FORMAT_32;
1608 case 2:
1609 return V_008F14_IMG_DATA_FORMAT_32_32;
1610 #if 0 /* Not supported for render targets */
1611 case 3:
1612 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1613 #endif
1614 case 4:
1615 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1616 }
1617 }
1618
1619 out_unknown:
1620 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1621 return ~0;
1622 }
1623
1624 static unsigned si_tex_wrap(unsigned wrap)
1625 {
1626 switch (wrap) {
1627 default:
1628 case PIPE_TEX_WRAP_REPEAT:
1629 return V_008F30_SQ_TEX_WRAP;
1630 case PIPE_TEX_WRAP_CLAMP:
1631 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1632 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1633 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1634 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1635 return V_008F30_SQ_TEX_CLAMP_BORDER;
1636 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1637 return V_008F30_SQ_TEX_MIRROR;
1638 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1639 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1640 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1641 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1642 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1643 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1644 }
1645 }
1646
1647 static unsigned si_tex_mipfilter(unsigned filter)
1648 {
1649 switch (filter) {
1650 case PIPE_TEX_MIPFILTER_NEAREST:
1651 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1652 case PIPE_TEX_MIPFILTER_LINEAR:
1653 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1654 default:
1655 case PIPE_TEX_MIPFILTER_NONE:
1656 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1657 }
1658 }
1659
1660 static unsigned si_tex_compare(unsigned compare)
1661 {
1662 switch (compare) {
1663 default:
1664 case PIPE_FUNC_NEVER:
1665 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1666 case PIPE_FUNC_LESS:
1667 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1668 case PIPE_FUNC_EQUAL:
1669 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1670 case PIPE_FUNC_LEQUAL:
1671 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1672 case PIPE_FUNC_GREATER:
1673 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1674 case PIPE_FUNC_NOTEQUAL:
1675 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1676 case PIPE_FUNC_GEQUAL:
1677 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1678 case PIPE_FUNC_ALWAYS:
1679 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1680 }
1681 }
1682
1683 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1684 unsigned view_target, unsigned nr_samples)
1685 {
1686 unsigned res_target = rtex->resource.b.b.target;
1687
1688 if (view_target == PIPE_TEXTURE_CUBE ||
1689 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1690 res_target = view_target;
1691 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1692 else if (res_target == PIPE_TEXTURE_CUBE ||
1693 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1694 res_target = PIPE_TEXTURE_2D_ARRAY;
1695
1696 /* GFX9 allocates 1D textures as 2D. */
1697 if ((res_target == PIPE_TEXTURE_1D ||
1698 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1699 sscreen->b.chip_class >= GFX9 &&
1700 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1701 if (res_target == PIPE_TEXTURE_1D)
1702 res_target = PIPE_TEXTURE_2D;
1703 else
1704 res_target = PIPE_TEXTURE_2D_ARRAY;
1705 }
1706
1707 switch (res_target) {
1708 default:
1709 case PIPE_TEXTURE_1D:
1710 return V_008F1C_SQ_RSRC_IMG_1D;
1711 case PIPE_TEXTURE_1D_ARRAY:
1712 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1713 case PIPE_TEXTURE_2D:
1714 case PIPE_TEXTURE_RECT:
1715 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1716 V_008F1C_SQ_RSRC_IMG_2D;
1717 case PIPE_TEXTURE_2D_ARRAY:
1718 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1719 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1720 case PIPE_TEXTURE_3D:
1721 return V_008F1C_SQ_RSRC_IMG_3D;
1722 case PIPE_TEXTURE_CUBE:
1723 case PIPE_TEXTURE_CUBE_ARRAY:
1724 return V_008F1C_SQ_RSRC_IMG_CUBE;
1725 }
1726 }
1727
1728 /*
1729 * Format support testing
1730 */
1731
1732 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1733 {
1734 return si_translate_texformat(screen, format, util_format_description(format),
1735 util_format_get_first_non_void_channel(format)) != ~0U;
1736 }
1737
1738 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1739 const struct util_format_description *desc,
1740 int first_non_void)
1741 {
1742 int i;
1743
1744 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1745 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1746
1747 assert(first_non_void >= 0);
1748
1749 if (desc->nr_channels == 4 &&
1750 desc->channel[0].size == 10 &&
1751 desc->channel[1].size == 10 &&
1752 desc->channel[2].size == 10 &&
1753 desc->channel[3].size == 2)
1754 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1755
1756 /* See whether the components are of the same size. */
1757 for (i = 0; i < desc->nr_channels; i++) {
1758 if (desc->channel[first_non_void].size != desc->channel[i].size)
1759 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1760 }
1761
1762 switch (desc->channel[first_non_void].size) {
1763 case 8:
1764 switch (desc->nr_channels) {
1765 case 1:
1766 case 3: /* 3 loads */
1767 return V_008F0C_BUF_DATA_FORMAT_8;
1768 case 2:
1769 return V_008F0C_BUF_DATA_FORMAT_8_8;
1770 case 4:
1771 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1772 }
1773 break;
1774 case 16:
1775 switch (desc->nr_channels) {
1776 case 1:
1777 case 3: /* 3 loads */
1778 return V_008F0C_BUF_DATA_FORMAT_16;
1779 case 2:
1780 return V_008F0C_BUF_DATA_FORMAT_16_16;
1781 case 4:
1782 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1783 }
1784 break;
1785 case 32:
1786 switch (desc->nr_channels) {
1787 case 1:
1788 return V_008F0C_BUF_DATA_FORMAT_32;
1789 case 2:
1790 return V_008F0C_BUF_DATA_FORMAT_32_32;
1791 case 3:
1792 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1793 case 4:
1794 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1795 }
1796 break;
1797 case 64:
1798 /* Legacy double formats. */
1799 switch (desc->nr_channels) {
1800 case 1: /* 1 load */
1801 return V_008F0C_BUF_DATA_FORMAT_32_32;
1802 case 2: /* 1 load */
1803 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1804 case 3: /* 3 loads */
1805 return V_008F0C_BUF_DATA_FORMAT_32_32;
1806 case 4: /* 2 loads */
1807 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1808 }
1809 break;
1810 }
1811
1812 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1813 }
1814
1815 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1816 const struct util_format_description *desc,
1817 int first_non_void)
1818 {
1819 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1820 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1821
1822 assert(first_non_void >= 0);
1823
1824 switch (desc->channel[first_non_void].type) {
1825 case UTIL_FORMAT_TYPE_SIGNED:
1826 case UTIL_FORMAT_TYPE_FIXED:
1827 if (desc->channel[first_non_void].size >= 32 ||
1828 desc->channel[first_non_void].pure_integer)
1829 return V_008F0C_BUF_NUM_FORMAT_SINT;
1830 else if (desc->channel[first_non_void].normalized)
1831 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1832 else
1833 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1834 break;
1835 case UTIL_FORMAT_TYPE_UNSIGNED:
1836 if (desc->channel[first_non_void].size >= 32 ||
1837 desc->channel[first_non_void].pure_integer)
1838 return V_008F0C_BUF_NUM_FORMAT_UINT;
1839 else if (desc->channel[first_non_void].normalized)
1840 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1841 else
1842 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1843 break;
1844 case UTIL_FORMAT_TYPE_FLOAT:
1845 default:
1846 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1847 }
1848 }
1849
1850 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1851 enum pipe_format format,
1852 unsigned usage)
1853 {
1854 const struct util_format_description *desc;
1855 int first_non_void;
1856 unsigned data_format;
1857
1858 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1859 PIPE_BIND_SAMPLER_VIEW |
1860 PIPE_BIND_VERTEX_BUFFER)) == 0);
1861
1862 desc = util_format_description(format);
1863
1864 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1865 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1866 * for read-only access (with caveats surrounding bounds checks), but
1867 * obviously fails for write access which we have to implement for
1868 * shader images. Luckily, OpenGL doesn't expect this to be supported
1869 * anyway, and so the only impact is on PBO uploads / downloads, which
1870 * shouldn't be expected to be fast for GL_RGB anyway.
1871 */
1872 if (desc->block.bits == 3 * 8 ||
1873 desc->block.bits == 3 * 16) {
1874 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1875 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1876 if (!usage)
1877 return 0;
1878 }
1879 }
1880
1881 first_non_void = util_format_get_first_non_void_channel(format);
1882 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1883 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1884 return 0;
1885
1886 return usage;
1887 }
1888
1889 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1890 {
1891 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1892 r600_translate_colorswap(format, false) != ~0U;
1893 }
1894
1895 static bool si_is_zs_format_supported(enum pipe_format format)
1896 {
1897 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1898 }
1899
1900 static boolean si_is_format_supported(struct pipe_screen *screen,
1901 enum pipe_format format,
1902 enum pipe_texture_target target,
1903 unsigned sample_count,
1904 unsigned usage)
1905 {
1906 unsigned retval = 0;
1907
1908 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1909 R600_ERR("r600: unsupported texture type %d\n", target);
1910 return false;
1911 }
1912
1913 if (!util_format_is_supported(format, usage))
1914 return false;
1915
1916 if (sample_count > 1) {
1917 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1918 return false;
1919
1920 if (usage & PIPE_BIND_SHADER_IMAGE)
1921 return false;
1922
1923 switch (sample_count) {
1924 case 2:
1925 case 4:
1926 case 8:
1927 break;
1928 case 16:
1929 if (format == PIPE_FORMAT_NONE)
1930 return true;
1931 else
1932 return false;
1933 default:
1934 return false;
1935 }
1936 }
1937
1938 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1939 PIPE_BIND_SHADER_IMAGE)) {
1940 if (target == PIPE_BUFFER) {
1941 retval |= si_is_vertex_format_supported(
1942 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1943 PIPE_BIND_SHADER_IMAGE));
1944 } else {
1945 if (si_is_sampler_format_supported(screen, format))
1946 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1947 PIPE_BIND_SHADER_IMAGE);
1948 }
1949 }
1950
1951 if ((usage & (PIPE_BIND_RENDER_TARGET |
1952 PIPE_BIND_DISPLAY_TARGET |
1953 PIPE_BIND_SCANOUT |
1954 PIPE_BIND_SHARED |
1955 PIPE_BIND_BLENDABLE)) &&
1956 si_is_colorbuffer_format_supported(format)) {
1957 retval |= usage &
1958 (PIPE_BIND_RENDER_TARGET |
1959 PIPE_BIND_DISPLAY_TARGET |
1960 PIPE_BIND_SCANOUT |
1961 PIPE_BIND_SHARED);
1962 if (!util_format_is_pure_integer(format) &&
1963 !util_format_is_depth_or_stencil(format))
1964 retval |= usage & PIPE_BIND_BLENDABLE;
1965 }
1966
1967 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1968 si_is_zs_format_supported(format)) {
1969 retval |= PIPE_BIND_DEPTH_STENCIL;
1970 }
1971
1972 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1973 retval |= si_is_vertex_format_supported(screen, format,
1974 PIPE_BIND_VERTEX_BUFFER);
1975 }
1976
1977 if ((usage & PIPE_BIND_LINEAR) &&
1978 !util_format_is_compressed(format) &&
1979 !(usage & PIPE_BIND_DEPTH_STENCIL))
1980 retval |= PIPE_BIND_LINEAR;
1981
1982 return retval == usage;
1983 }
1984
1985 /*
1986 * framebuffer handling
1987 */
1988
1989 static void si_choose_spi_color_formats(struct r600_surface *surf,
1990 unsigned format, unsigned swap,
1991 unsigned ntype, bool is_depth)
1992 {
1993 /* Alpha is needed for alpha-to-coverage.
1994 * Blending may be with or without alpha.
1995 */
1996 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1997 unsigned alpha = 0; /* exports alpha, but may not support blending */
1998 unsigned blend = 0; /* supports blending, but may not export alpha */
1999 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2000
2001 /* Choose the SPI color formats. These are required values for RB+.
2002 * Other chips have multiple choices, though they are not necessarily better.
2003 */
2004 switch (format) {
2005 case V_028C70_COLOR_5_6_5:
2006 case V_028C70_COLOR_1_5_5_5:
2007 case V_028C70_COLOR_5_5_5_1:
2008 case V_028C70_COLOR_4_4_4_4:
2009 case V_028C70_COLOR_10_11_11:
2010 case V_028C70_COLOR_11_11_10:
2011 case V_028C70_COLOR_8:
2012 case V_028C70_COLOR_8_8:
2013 case V_028C70_COLOR_8_8_8_8:
2014 case V_028C70_COLOR_10_10_10_2:
2015 case V_028C70_COLOR_2_10_10_10:
2016 if (ntype == V_028C70_NUMBER_UINT)
2017 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2018 else if (ntype == V_028C70_NUMBER_SINT)
2019 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2020 else
2021 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2022 break;
2023
2024 case V_028C70_COLOR_16:
2025 case V_028C70_COLOR_16_16:
2026 case V_028C70_COLOR_16_16_16_16:
2027 if (ntype == V_028C70_NUMBER_UNORM ||
2028 ntype == V_028C70_NUMBER_SNORM) {
2029 /* UNORM16 and SNORM16 don't support blending */
2030 if (ntype == V_028C70_NUMBER_UNORM)
2031 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2032 else
2033 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2034
2035 /* Use 32 bits per channel for blending. */
2036 if (format == V_028C70_COLOR_16) {
2037 if (swap == V_028C70_SWAP_STD) { /* R */
2038 blend = V_028714_SPI_SHADER_32_R;
2039 blend_alpha = V_028714_SPI_SHADER_32_AR;
2040 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2041 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2042 else
2043 assert(0);
2044 } else if (format == V_028C70_COLOR_16_16) {
2045 if (swap == V_028C70_SWAP_STD) { /* RG */
2046 blend = V_028714_SPI_SHADER_32_GR;
2047 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2048 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2049 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2050 else
2051 assert(0);
2052 } else /* 16_16_16_16 */
2053 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2054 } else if (ntype == V_028C70_NUMBER_UINT)
2055 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2056 else if (ntype == V_028C70_NUMBER_SINT)
2057 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2058 else if (ntype == V_028C70_NUMBER_FLOAT)
2059 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2060 else
2061 assert(0);
2062 break;
2063
2064 case V_028C70_COLOR_32:
2065 if (swap == V_028C70_SWAP_STD) { /* R */
2066 blend = normal = V_028714_SPI_SHADER_32_R;
2067 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2068 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2069 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2070 else
2071 assert(0);
2072 break;
2073
2074 case V_028C70_COLOR_32_32:
2075 if (swap == V_028C70_SWAP_STD) { /* RG */
2076 blend = normal = V_028714_SPI_SHADER_32_GR;
2077 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2078 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2079 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2080 else
2081 assert(0);
2082 break;
2083
2084 case V_028C70_COLOR_32_32_32_32:
2085 case V_028C70_COLOR_8_24:
2086 case V_028C70_COLOR_24_8:
2087 case V_028C70_COLOR_X24_8_32_FLOAT:
2088 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2089 break;
2090
2091 default:
2092 assert(0);
2093 return;
2094 }
2095
2096 /* The DB->CB copy needs 32_ABGR. */
2097 if (is_depth)
2098 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2099
2100 surf->spi_shader_col_format = normal;
2101 surf->spi_shader_col_format_alpha = alpha;
2102 surf->spi_shader_col_format_blend = blend;
2103 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2104 }
2105
2106 static void si_initialize_color_surface(struct si_context *sctx,
2107 struct r600_surface *surf)
2108 {
2109 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2110 unsigned color_info, color_attrib, color_view;
2111 unsigned format, swap, ntype, endian;
2112 const struct util_format_description *desc;
2113 int i;
2114 unsigned blend_clamp = 0, blend_bypass = 0;
2115
2116 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2117 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2118
2119 desc = util_format_description(surf->base.format);
2120 for (i = 0; i < 4; i++) {
2121 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2122 break;
2123 }
2124 }
2125 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2126 ntype = V_028C70_NUMBER_FLOAT;
2127 } else {
2128 ntype = V_028C70_NUMBER_UNORM;
2129 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2130 ntype = V_028C70_NUMBER_SRGB;
2131 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2132 if (desc->channel[i].pure_integer) {
2133 ntype = V_028C70_NUMBER_SINT;
2134 } else {
2135 assert(desc->channel[i].normalized);
2136 ntype = V_028C70_NUMBER_SNORM;
2137 }
2138 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2139 if (desc->channel[i].pure_integer) {
2140 ntype = V_028C70_NUMBER_UINT;
2141 } else {
2142 assert(desc->channel[i].normalized);
2143 ntype = V_028C70_NUMBER_UNORM;
2144 }
2145 }
2146 }
2147
2148 format = si_translate_colorformat(surf->base.format);
2149 if (format == V_028C70_COLOR_INVALID) {
2150 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2151 }
2152 assert(format != V_028C70_COLOR_INVALID);
2153 swap = r600_translate_colorswap(surf->base.format, false);
2154 endian = si_colorformat_endian_swap(format);
2155
2156 /* blend clamp should be set for all NORM/SRGB types */
2157 if (ntype == V_028C70_NUMBER_UNORM ||
2158 ntype == V_028C70_NUMBER_SNORM ||
2159 ntype == V_028C70_NUMBER_SRGB)
2160 blend_clamp = 1;
2161
2162 /* set blend bypass according to docs if SINT/UINT or
2163 8/24 COLOR variants */
2164 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2165 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2166 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2167 blend_clamp = 0;
2168 blend_bypass = 1;
2169 }
2170
2171 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2172 if (format == V_028C70_COLOR_8 ||
2173 format == V_028C70_COLOR_8_8 ||
2174 format == V_028C70_COLOR_8_8_8_8)
2175 surf->color_is_int8 = true;
2176 else if (format == V_028C70_COLOR_10_10_10_2 ||
2177 format == V_028C70_COLOR_2_10_10_10)
2178 surf->color_is_int10 = true;
2179 }
2180
2181 color_info = S_028C70_FORMAT(format) |
2182 S_028C70_COMP_SWAP(swap) |
2183 S_028C70_BLEND_CLAMP(blend_clamp) |
2184 S_028C70_BLEND_BYPASS(blend_bypass) |
2185 S_028C70_SIMPLE_FLOAT(1) |
2186 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2187 ntype != V_028C70_NUMBER_SNORM &&
2188 ntype != V_028C70_NUMBER_SRGB &&
2189 format != V_028C70_COLOR_8_24 &&
2190 format != V_028C70_COLOR_24_8) |
2191 S_028C70_NUMBER_TYPE(ntype) |
2192 S_028C70_ENDIAN(endian);
2193
2194 /* Intensity is implemented as Red, so treat it that way. */
2195 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2196 util_format_is_intensity(surf->base.format));
2197
2198 if (rtex->resource.b.b.nr_samples > 1) {
2199 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2200
2201 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2202 S_028C74_NUM_FRAGMENTS(log_samples);
2203
2204 if (rtex->fmask.size) {
2205 color_info |= S_028C70_COMPRESSION(1);
2206 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2207
2208 if (sctx->b.chip_class == SI) {
2209 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2210 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2211 }
2212 }
2213 }
2214
2215 surf->cb_color_view = color_view;
2216 surf->cb_color_info = color_info;
2217 surf->cb_color_attrib = color_attrib;
2218
2219 if (sctx->b.chip_class >= VI) {
2220 unsigned max_uncompressed_block_size = 2;
2221
2222 if (rtex->resource.b.b.nr_samples > 1) {
2223 if (rtex->surface.bpe == 1)
2224 max_uncompressed_block_size = 0;
2225 else if (rtex->surface.bpe == 2)
2226 max_uncompressed_block_size = 1;
2227 }
2228
2229 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2230 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2231 }
2232
2233 /* This must be set for fast clear to work without FMASK. */
2234 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2235 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2236 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2237 }
2238
2239 if (sctx->b.chip_class >= GFX9) {
2240 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2241
2242 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2243 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2244 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2245 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2246 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2247 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2248 }
2249
2250 /* Determine pixel shader export format */
2251 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2252
2253 surf->color_initialized = true;
2254 }
2255
2256 static void si_init_depth_surface(struct si_context *sctx,
2257 struct r600_surface *surf)
2258 {
2259 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2260 unsigned level = surf->base.u.tex.level;
2261 unsigned format, stencil_format;
2262 uint32_t z_info, s_info;
2263
2264 format = si_translate_dbformat(rtex->db_render_format);
2265 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2266 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2267
2268 assert(format != V_028040_Z_INVALID);
2269 if (format == V_028040_Z_INVALID)
2270 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2271
2272 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2273 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2274 surf->db_htile_data_base = 0;
2275 surf->db_htile_surface = 0;
2276
2277 if (sctx->b.chip_class >= GFX9) {
2278 assert(rtex->surface.u.gfx9.surf_offset == 0);
2279 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2280 surf->db_stencil_base = (rtex->resource.gpu_address +
2281 rtex->surface.u.gfx9.stencil_offset) >> 8;
2282 z_info = S_028038_FORMAT(format) |
2283 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2284 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2285 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2286 s_info = S_02803C_FORMAT(stencil_format) |
2287 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2288 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2289 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2290 surf->db_depth_view |= S_028008_MIPID(level);
2291 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2292 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2293
2294 /* Only use HTILE for the first level. */
2295 if (rtex->htile_buffer && !level) {
2296 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2297 S_028038_ALLOW_EXPCLEAR(1);
2298
2299 if (rtex->tc_compatible_htile) {
2300 unsigned max_zplanes = 4;
2301
2302 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2303 rtex->resource.b.b.nr_samples > 1)
2304 max_zplanes = 2;
2305
2306 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2307 S_028038_ITERATE_FLUSH(1);
2308 s_info |= S_02803C_ITERATE_FLUSH(1);
2309 }
2310
2311 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2312 /* Stencil buffer workaround ported from the SI-CI-VI code.
2313 * See that for explanation.
2314 */
2315 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2316 } else {
2317 /* Use all HTILE for depth if there's no stencil. */
2318 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2319 }
2320
2321 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2322 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2323 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2324 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2325 }
2326 } else {
2327 /* SI-CI-VI */
2328 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2329
2330 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2331
2332 surf->db_depth_base = (rtex->resource.gpu_address +
2333 rtex->surface.u.legacy.level[level].offset) >> 8;
2334 surf->db_stencil_base = (rtex->resource.gpu_address +
2335 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2336
2337 z_info = S_028040_FORMAT(format) |
2338 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2339 s_info = S_028044_FORMAT(stencil_format);
2340 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2341
2342 if (sctx->b.chip_class >= CIK) {
2343 struct radeon_info *info = &sctx->screen->b.info;
2344 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2345 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2346 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2347 unsigned tile_mode = info->si_tile_mode_array[index];
2348 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2349 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2350
2351 surf->db_depth_info |=
2352 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2353 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2354 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2355 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2356 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2357 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2358 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2359 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2360 } else {
2361 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2362 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2363 tile_mode_index = si_tile_mode_index(rtex, level, true);
2364 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2365 }
2366
2367 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2368 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2369 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2370 levelinfo->nblk_y) / 64 - 1);
2371
2372 /* Only use HTILE for the first level. */
2373 if (rtex->htile_buffer && !level) {
2374 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2375 S_028040_ALLOW_EXPCLEAR(1);
2376
2377 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2378 /* Workaround: For a not yet understood reason, the
2379 * combination of MSAA, fast stencil clear and stencil
2380 * decompress messes with subsequent stencil buffer
2381 * uses. Problem was reproduced on Verde, Bonaire,
2382 * Tonga, and Carrizo.
2383 *
2384 * Disabling EXPCLEAR works around the problem.
2385 *
2386 * Check piglit's arb_texture_multisample-stencil-clear
2387 * test if you want to try changing this.
2388 */
2389 if (rtex->resource.b.b.nr_samples <= 1)
2390 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2391 } else if (!rtex->tc_compatible_htile) {
2392 /* Use all of the htile_buffer for depth if there's no stencil.
2393 * This must not be set when TC-compatible HTILE is enabled
2394 * due to a hw bug.
2395 */
2396 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2397 }
2398
2399 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2400 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2401
2402 if (rtex->tc_compatible_htile) {
2403 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2404
2405 if (rtex->resource.b.b.nr_samples <= 1)
2406 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2407 else if (rtex->resource.b.b.nr_samples <= 4)
2408 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2409 else
2410 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2411 }
2412 }
2413 }
2414
2415 surf->db_z_info = z_info;
2416 surf->db_stencil_info = s_info;
2417
2418 surf->depth_initialized = true;
2419 }
2420
2421 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2422 {
2423 for (int i = 0; i < state->nr_cbufs; ++i) {
2424 struct r600_surface *surf = NULL;
2425 struct r600_texture *rtex;
2426
2427 if (!state->cbufs[i])
2428 continue;
2429 surf = (struct r600_surface*)state->cbufs[i];
2430 rtex = (struct r600_texture*)surf->base.texture;
2431
2432 p_atomic_dec(&rtex->framebuffers_bound);
2433 }
2434 }
2435
2436 static void si_set_framebuffer_state(struct pipe_context *ctx,
2437 const struct pipe_framebuffer_state *state)
2438 {
2439 struct si_context *sctx = (struct si_context *)ctx;
2440 struct pipe_constant_buffer constbuf = {0};
2441 struct r600_surface *surf = NULL;
2442 struct r600_texture *rtex;
2443 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2444 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2445 bool unbound = false;
2446 int i;
2447
2448 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2449 if (!sctx->framebuffer.state.cbufs[i])
2450 continue;
2451
2452 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2453 if (rtex->dcc_gather_statistics)
2454 vi_separate_dcc_stop_query(ctx, rtex);
2455 }
2456
2457 /* Disable DCC if the formats are incompatible. */
2458 for (i = 0; i < state->nr_cbufs; i++) {
2459 if (!state->cbufs[i])
2460 continue;
2461
2462 surf = (struct r600_surface*)state->cbufs[i];
2463 rtex = (struct r600_texture*)surf->base.texture;
2464
2465 if (!surf->dcc_incompatible)
2466 continue;
2467
2468 /* Since the DCC decompression calls back into set_framebuffer-
2469 * _state, we need to unbind the framebuffer, so that
2470 * vi_separate_dcc_stop_query isn't called twice with the same
2471 * color buffer.
2472 */
2473 if (!unbound) {
2474 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2475 unbound = true;
2476 }
2477
2478 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2479 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2480 sctx->b.decompress_dcc(ctx, rtex);
2481
2482 surf->dcc_incompatible = false;
2483 }
2484
2485 /* Only flush TC when changing the framebuffer state, because
2486 * the only client not using TC that can change textures is
2487 * the framebuffer.
2488 *
2489 * Flush all CB and DB caches here because all buffers can be used
2490 * for write by both TC (with shader image stores) and CB/DB.
2491 */
2492 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2493 SI_CONTEXT_INV_GLOBAL_L2 |
2494 SI_CONTEXT_FLUSH_AND_INV_CB |
2495 SI_CONTEXT_FLUSH_AND_INV_DB |
2496 SI_CONTEXT_CS_PARTIAL_FLUSH;
2497
2498 /* Take the maximum of the old and new count. If the new count is lower,
2499 * dirtying is needed to disable the unbound colorbuffers.
2500 */
2501 sctx->framebuffer.dirty_cbufs |=
2502 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2503 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2504
2505 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2506 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2507
2508 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2509 sctx->framebuffer.spi_shader_col_format = 0;
2510 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2511 sctx->framebuffer.spi_shader_col_format_blend = 0;
2512 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2513 sctx->framebuffer.color_is_int8 = 0;
2514 sctx->framebuffer.color_is_int10 = 0;
2515
2516 sctx->framebuffer.compressed_cb_mask = 0;
2517 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2518 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2519 sctx->framebuffer.any_dst_linear = false;
2520
2521 for (i = 0; i < state->nr_cbufs; i++) {
2522 if (!state->cbufs[i])
2523 continue;
2524
2525 surf = (struct r600_surface*)state->cbufs[i];
2526 rtex = (struct r600_texture*)surf->base.texture;
2527
2528 if (!surf->color_initialized) {
2529 si_initialize_color_surface(sctx, surf);
2530 }
2531
2532 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2533 sctx->framebuffer.spi_shader_col_format |=
2534 surf->spi_shader_col_format << (i * 4);
2535 sctx->framebuffer.spi_shader_col_format_alpha |=
2536 surf->spi_shader_col_format_alpha << (i * 4);
2537 sctx->framebuffer.spi_shader_col_format_blend |=
2538 surf->spi_shader_col_format_blend << (i * 4);
2539 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2540 surf->spi_shader_col_format_blend_alpha << (i * 4);
2541
2542 if (surf->color_is_int8)
2543 sctx->framebuffer.color_is_int8 |= 1 << i;
2544 if (surf->color_is_int10)
2545 sctx->framebuffer.color_is_int10 |= 1 << i;
2546
2547 if (rtex->fmask.size) {
2548 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2549 }
2550
2551 if (rtex->surface.is_linear)
2552 sctx->framebuffer.any_dst_linear = true;
2553
2554 r600_context_add_resource_size(ctx, surf->base.texture);
2555
2556 p_atomic_inc(&rtex->framebuffers_bound);
2557
2558 if (rtex->dcc_gather_statistics) {
2559 /* Dirty tracking must be enabled for DCC usage analysis. */
2560 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2561 vi_separate_dcc_start_query(ctx, rtex);
2562 }
2563 }
2564
2565 if (state->zsbuf) {
2566 surf = (struct r600_surface*)state->zsbuf;
2567 rtex = (struct r600_texture*)surf->base.texture;
2568
2569 if (!surf->depth_initialized) {
2570 si_init_depth_surface(sctx, surf);
2571 }
2572 r600_context_add_resource_size(ctx, surf->base.texture);
2573 }
2574
2575 si_update_poly_offset_state(sctx);
2576 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2577 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2578
2579 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2580 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2581
2582 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2583 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2584 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2585
2586 /* Set sample locations as fragment shader constants. */
2587 switch (sctx->framebuffer.nr_samples) {
2588 case 1:
2589 constbuf.user_buffer = sctx->b.sample_locations_1x;
2590 break;
2591 case 2:
2592 constbuf.user_buffer = sctx->b.sample_locations_2x;
2593 break;
2594 case 4:
2595 constbuf.user_buffer = sctx->b.sample_locations_4x;
2596 break;
2597 case 8:
2598 constbuf.user_buffer = sctx->b.sample_locations_8x;
2599 break;
2600 case 16:
2601 constbuf.user_buffer = sctx->b.sample_locations_16x;
2602 break;
2603 default:
2604 R600_ERR("Requested an invalid number of samples %i.\n",
2605 sctx->framebuffer.nr_samples);
2606 assert(0);
2607 }
2608 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2609 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2610
2611 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2612 }
2613
2614 sctx->need_check_render_feedback = true;
2615 sctx->do_update_shaders = true;
2616 sctx->framebuffer.do_update_surf_dirtiness = true;
2617 }
2618
2619 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2620 {
2621 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2622 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2623 unsigned i, nr_cbufs = state->nr_cbufs;
2624 struct r600_texture *tex = NULL;
2625 struct r600_surface *cb = NULL;
2626 unsigned cb_color_info = 0;
2627
2628 /* Colorbuffers. */
2629 for (i = 0; i < nr_cbufs; i++) {
2630 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2631 unsigned cb_color_attrib;
2632
2633 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2634 continue;
2635
2636 cb = (struct r600_surface*)state->cbufs[i];
2637 if (!cb) {
2638 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2639 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2640 continue;
2641 }
2642
2643 tex = (struct r600_texture *)cb->base.texture;
2644 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2645 &tex->resource, RADEON_USAGE_READWRITE,
2646 tex->resource.b.b.nr_samples > 1 ?
2647 RADEON_PRIO_COLOR_BUFFER_MSAA :
2648 RADEON_PRIO_COLOR_BUFFER);
2649
2650 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2651 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2652 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2653 RADEON_PRIO_CMASK);
2654 }
2655
2656 if (tex->dcc_separate_buffer)
2657 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2658 tex->dcc_separate_buffer,
2659 RADEON_USAGE_READWRITE,
2660 RADEON_PRIO_DCC);
2661
2662 /* Compute mutable surface parameters. */
2663 cb_color_base = tex->resource.gpu_address >> 8;
2664 cb_color_fmask = cb_color_base;
2665 cb_dcc_base = 0;
2666 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2667 cb_color_attrib = cb->cb_color_attrib;
2668
2669 if (tex->fmask.size)
2670 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2671
2672 /* Set up DCC. */
2673 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2674 bool is_msaa_resolve_dst = state->cbufs[0] &&
2675 state->cbufs[0]->texture->nr_samples > 1 &&
2676 state->cbufs[1] == &cb->base &&
2677 state->cbufs[1]->texture->nr_samples <= 1;
2678
2679 if (!is_msaa_resolve_dst)
2680 cb_color_info |= S_028C70_DCC_ENABLE(1);
2681
2682 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2683 tex->dcc_offset) >> 8;
2684 }
2685
2686 if (sctx->b.chip_class >= GFX9) {
2687 struct gfx9_surf_meta_flags meta;
2688
2689 if (tex->dcc_offset)
2690 meta = tex->surface.u.gfx9.dcc;
2691 else
2692 meta = tex->surface.u.gfx9.cmask;
2693
2694 /* Set mutable surface parameters. */
2695 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2696 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2697 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2698 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2699 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2700
2701 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2702 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2703 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2704 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2705 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2706 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2707 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2708 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2709 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2710 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2711 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2712 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2713 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2714 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2715 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2716 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2717
2718 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2719 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2720 } else {
2721 /* Compute mutable surface parameters (SI-CI-VI). */
2722 const struct legacy_surf_level *level_info =
2723 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2724 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2725 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2726
2727 cb_color_base += level_info->offset >> 8;
2728 if (cb_dcc_base)
2729 cb_dcc_base += level_info->dcc_offset >> 8;
2730
2731 pitch_tile_max = level_info->nblk_x / 8 - 1;
2732 slice_tile_max = level_info->nblk_x *
2733 level_info->nblk_y / 64 - 1;
2734 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2735
2736 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2737 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2738 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2739
2740 if (tex->fmask.size) {
2741 if (sctx->b.chip_class >= CIK)
2742 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2743 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2744 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2745 } else {
2746 /* This must be set for fast clear to work without FMASK. */
2747 if (sctx->b.chip_class >= CIK)
2748 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2749 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2750 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2751 }
2752
2753 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2754 sctx->b.chip_class >= VI ? 14 : 13);
2755 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2756 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2757 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2758 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2759 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2760 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2761 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2762 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2763 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2764 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2765 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2766 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2767 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2768
2769 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2770 radeon_emit(cs, cb_dcc_base);
2771 }
2772 }
2773 for (; i < 8 ; i++)
2774 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2775 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2776
2777 /* ZS buffer. */
2778 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2779 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2780 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2781
2782 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2783 &rtex->resource, RADEON_USAGE_READWRITE,
2784 zb->base.texture->nr_samples > 1 ?
2785 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2786 RADEON_PRIO_DEPTH_BUFFER);
2787
2788 if (zb->db_htile_data_base) {
2789 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2790 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2791 RADEON_PRIO_HTILE);
2792 }
2793
2794 if (sctx->b.chip_class >= GFX9) {
2795 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2796 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2797 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2798 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2799
2800 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2801 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2802 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2803 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2804 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2805 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2806 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2807 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2808 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2809 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2810 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2811 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2812
2813 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2814 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2815 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2816 } else {
2817 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2818
2819 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2820 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2821 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2822 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2823 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2824 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2825 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2826 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2827 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2828 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2829 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2830 }
2831
2832 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2833 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2834 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2835
2836 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2837 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2838 } else if (sctx->framebuffer.dirty_zsbuf) {
2839 if (sctx->b.chip_class >= GFX9)
2840 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2841 else
2842 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2843
2844 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2845 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2846 }
2847
2848 /* Framebuffer dimensions. */
2849 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2850 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2851 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2852
2853 if (sctx->b.chip_class >= GFX9) {
2854 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2855 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2856 }
2857
2858 sctx->framebuffer.dirty_cbufs = 0;
2859 sctx->framebuffer.dirty_zsbuf = false;
2860 }
2861
2862 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2863 struct r600_atom *atom)
2864 {
2865 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2866 unsigned nr_samples = sctx->framebuffer.nr_samples;
2867 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2868
2869 /* Smoothing (only possible with nr_samples == 1) uses the same
2870 * sample locations as the MSAA it simulates.
2871 */
2872 if (nr_samples <= 1 && sctx->smoothing_enabled)
2873 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2874
2875 /* On Polaris, the small primitive filter uses the sample locations
2876 * even when MSAA is off, so we need to make sure they're set to 0.
2877 */
2878 if (has_msaa_sample_loc_bug)
2879 nr_samples = MAX2(nr_samples, 1);
2880
2881 if (nr_samples >= 1 &&
2882 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2883 sctx->msaa_sample_locs.nr_samples = nr_samples;
2884 cayman_emit_msaa_sample_locs(cs, nr_samples);
2885 }
2886
2887 if (sctx->b.family >= CHIP_POLARIS10) {
2888 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2889 unsigned small_prim_filter_cntl =
2890 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2891 /* line bug */
2892 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2893
2894 /* The alternative of setting sample locations to 0 would
2895 * require a DB flush to avoid Z errors, see
2896 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2897 */
2898 if (has_msaa_sample_loc_bug &&
2899 sctx->framebuffer.nr_samples > 1 &&
2900 rs && !rs->multisample_enable)
2901 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2902
2903 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2904 small_prim_filter_cntl);
2905 }
2906 }
2907
2908 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2909 {
2910 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2911 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2912 /* 33% faster rendering to linear color buffers */
2913 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2914 unsigned sc_mode_cntl_1 =
2915 S_028A4C_WALK_SIZE(dst_is_linear) |
2916 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2917 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2918 /* always 1: */
2919 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2920 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2921 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2922 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2923 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2924 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2925
2926 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2927 sctx->ps_iter_samples,
2928 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2929 sc_mode_cntl_1);
2930
2931 /* GFX9: Flush DFSM when the AA mode changes. */
2932 if (sctx->b.chip_class >= GFX9) {
2933 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2934 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2935 }
2936 }
2937
2938 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2939 {
2940 struct si_context *sctx = (struct si_context *)ctx;
2941
2942 if (sctx->ps_iter_samples == min_samples)
2943 return;
2944
2945 sctx->ps_iter_samples = min_samples;
2946 sctx->do_update_shaders = true;
2947
2948 if (sctx->framebuffer.nr_samples > 1)
2949 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2950 }
2951
2952 /*
2953 * Samplers
2954 */
2955
2956 /**
2957 * Build the sampler view descriptor for a buffer texture.
2958 * @param state 256-bit descriptor; only the high 128 bits are filled in
2959 */
2960 void
2961 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2962 enum pipe_format format,
2963 unsigned offset, unsigned size,
2964 uint32_t *state)
2965 {
2966 const struct util_format_description *desc;
2967 int first_non_void;
2968 unsigned stride;
2969 unsigned num_records;
2970 unsigned num_format, data_format;
2971
2972 desc = util_format_description(format);
2973 first_non_void = util_format_get_first_non_void_channel(format);
2974 stride = desc->block.bits / 8;
2975 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2976 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2977
2978 num_records = size / stride;
2979 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2980
2981 /* The NUM_RECORDS field has a different meaning depending on the chip,
2982 * instruction type, STRIDE, and SWIZZLE_ENABLE.
2983 *
2984 * SI-CIK:
2985 * - If STRIDE == 0, it's in byte units.
2986 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
2987 *
2988 * VI:
2989 * - For SMEM and STRIDE == 0, it's in byte units.
2990 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
2991 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
2992 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
2993 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
2994 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
2995 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
2996 * That way the same descriptor can be used by both SMEM and VMEM.
2997 *
2998 * GFX9:
2999 * - For SMEM and STRIDE == 0, it's in byte units.
3000 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3001 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3002 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3003 */
3004 if (screen->b.chip_class >= GFX9)
3005 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3006 * from STRIDE to bytes. This works around it by setting
3007 * NUM_RECORDS to at least the size of one element, so that
3008 * the first element is readable when IDXEN == 0.
3009 *
3010 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3011 * IDXEN is enforced?
3012 */
3013 num_records = num_records ? MAX2(num_records, stride) : 0;
3014 else if (screen->b.chip_class == VI)
3015 num_records *= stride;
3016
3017 state[4] = 0;
3018 state[5] = S_008F04_STRIDE(stride);
3019 state[6] = num_records;
3020 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3021 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3022 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3023 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3024 S_008F0C_NUM_FORMAT(num_format) |
3025 S_008F0C_DATA_FORMAT(data_format);
3026 }
3027
3028 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3029 {
3030 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3031
3032 if (swizzle[3] == PIPE_SWIZZLE_X) {
3033 /* For the pre-defined border color values (white, opaque
3034 * black, transparent black), the only thing that matters is
3035 * that the alpha channel winds up in the correct place
3036 * (because the RGB channels are all the same) so either of
3037 * these enumerations will work.
3038 */
3039 if (swizzle[2] == PIPE_SWIZZLE_Y)
3040 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3041 else
3042 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3043 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3044 if (swizzle[1] == PIPE_SWIZZLE_Y)
3045 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3046 else
3047 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3048 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3049 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3050 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3051 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3052 }
3053
3054 return bc_swizzle;
3055 }
3056
3057 /**
3058 * Build the sampler view descriptor for a texture.
3059 */
3060 void
3061 si_make_texture_descriptor(struct si_screen *screen,
3062 struct r600_texture *tex,
3063 bool sampler,
3064 enum pipe_texture_target target,
3065 enum pipe_format pipe_format,
3066 const unsigned char state_swizzle[4],
3067 unsigned first_level, unsigned last_level,
3068 unsigned first_layer, unsigned last_layer,
3069 unsigned width, unsigned height, unsigned depth,
3070 uint32_t *state,
3071 uint32_t *fmask_state)
3072 {
3073 struct pipe_resource *res = &tex->resource.b.b;
3074 const struct util_format_description *base_desc, *desc;
3075 unsigned char swizzle[4];
3076 int first_non_void;
3077 unsigned num_format, data_format, type;
3078 uint64_t va;
3079
3080 desc = util_format_description(pipe_format);
3081 base_desc = util_format_description(res->format);
3082
3083 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3084 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3085 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3086 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3087
3088 switch (pipe_format) {
3089 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3090 case PIPE_FORMAT_X32_S8X24_UINT:
3091 case PIPE_FORMAT_X8Z24_UNORM:
3092 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3093 break;
3094 case PIPE_FORMAT_X24S8_UINT:
3095 /*
3096 * X24S8 is implemented as an 8_8_8_8 data format, to
3097 * fix texture gathers. This affects at least
3098 * GL45-CTS.texture_cube_map_array.sampling on VI.
3099 */
3100 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3101 break;
3102 default:
3103 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3104 }
3105 } else {
3106 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3107 }
3108
3109 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3110
3111 switch (pipe_format) {
3112 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3113 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3114 break;
3115 default:
3116 if (first_non_void < 0) {
3117 if (util_format_is_compressed(pipe_format)) {
3118 switch (pipe_format) {
3119 case PIPE_FORMAT_DXT1_SRGB:
3120 case PIPE_FORMAT_DXT1_SRGBA:
3121 case PIPE_FORMAT_DXT3_SRGBA:
3122 case PIPE_FORMAT_DXT5_SRGBA:
3123 case PIPE_FORMAT_BPTC_SRGBA:
3124 case PIPE_FORMAT_ETC2_SRGB8:
3125 case PIPE_FORMAT_ETC2_SRGB8A1:
3126 case PIPE_FORMAT_ETC2_SRGBA8:
3127 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3128 break;
3129 case PIPE_FORMAT_RGTC1_SNORM:
3130 case PIPE_FORMAT_LATC1_SNORM:
3131 case PIPE_FORMAT_RGTC2_SNORM:
3132 case PIPE_FORMAT_LATC2_SNORM:
3133 case PIPE_FORMAT_ETC2_R11_SNORM:
3134 case PIPE_FORMAT_ETC2_RG11_SNORM:
3135 /* implies float, so use SNORM/UNORM to determine
3136 whether data is signed or not */
3137 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3138 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3139 break;
3140 default:
3141 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3142 break;
3143 }
3144 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3145 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3146 } else {
3147 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3148 }
3149 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3150 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3151 } else {
3152 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3153
3154 switch (desc->channel[first_non_void].type) {
3155 case UTIL_FORMAT_TYPE_FLOAT:
3156 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3157 break;
3158 case UTIL_FORMAT_TYPE_SIGNED:
3159 if (desc->channel[first_non_void].normalized)
3160 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3161 else if (desc->channel[first_non_void].pure_integer)
3162 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3163 else
3164 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3165 break;
3166 case UTIL_FORMAT_TYPE_UNSIGNED:
3167 if (desc->channel[first_non_void].normalized)
3168 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3169 else if (desc->channel[first_non_void].pure_integer)
3170 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3171 else
3172 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3173 }
3174 }
3175 }
3176
3177 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3178 if (data_format == ~0) {
3179 data_format = 0;
3180 }
3181
3182 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3183 if (screen->b.chip_class >= GFX9 &&
3184 util_format_has_depth(desc) &&
3185 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3186 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3187 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3188 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3189 }
3190
3191 if (!sampler &&
3192 (res->target == PIPE_TEXTURE_CUBE ||
3193 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3194 (screen->b.chip_class <= VI &&
3195 res->target == PIPE_TEXTURE_3D))) {
3196 /* For the purpose of shader images, treat cube maps and 3D
3197 * textures as 2D arrays. For 3D textures, the address
3198 * calculations for mipmaps are different, so we rely on the
3199 * caller to effectively disable mipmaps.
3200 */
3201 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3202
3203 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3204 } else {
3205 type = si_tex_dim(screen, tex, target, res->nr_samples);
3206 }
3207
3208 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3209 height = 1;
3210 depth = res->array_size;
3211 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3212 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3213 if (sampler || res->target != PIPE_TEXTURE_3D)
3214 depth = res->array_size;
3215 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3216 depth = res->array_size / 6;
3217
3218 state[0] = 0;
3219 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3220 S_008F14_NUM_FORMAT_GFX6(num_format));
3221 state[2] = (S_008F18_WIDTH(width - 1) |
3222 S_008F18_HEIGHT(height - 1) |
3223 S_008F18_PERF_MOD(4));
3224 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3225 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3226 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3227 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3228 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3229 0 : first_level) |
3230 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3231 util_logbase2(res->nr_samples) :
3232 last_level) |
3233 S_008F1C_TYPE(type));
3234 state[4] = 0;
3235 state[5] = S_008F24_BASE_ARRAY(first_layer);
3236 state[6] = 0;
3237 state[7] = 0;
3238
3239 if (screen->b.chip_class >= GFX9) {
3240 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3241
3242 /* Depth is the the last accessible layer on Gfx9.
3243 * The hw doesn't need to know the total number of layers.
3244 */
3245 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3246 state[4] |= S_008F20_DEPTH(depth - 1);
3247 else
3248 state[4] |= S_008F20_DEPTH(last_layer);
3249
3250 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3251 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3252 util_logbase2(res->nr_samples) :
3253 tex->resource.b.b.last_level);
3254 } else {
3255 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3256 state[4] |= S_008F20_DEPTH(depth - 1);
3257 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3258 }
3259
3260 if (tex->dcc_offset) {
3261 unsigned swap = r600_translate_colorswap(pipe_format, false);
3262
3263 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3264 } else {
3265 /* The last dword is unused by hw. The shader uses it to clear
3266 * bits in the first dword of sampler state.
3267 */
3268 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3269 if (first_level == last_level)
3270 state[7] = C_008F30_MAX_ANISO_RATIO;
3271 else
3272 state[7] = 0xffffffff;
3273 }
3274 }
3275
3276 /* Initialize the sampler view for FMASK. */
3277 if (tex->fmask.size) {
3278 uint32_t data_format, num_format;
3279
3280 va = tex->resource.gpu_address + tex->fmask.offset;
3281
3282 if (screen->b.chip_class >= GFX9) {
3283 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3284 switch (res->nr_samples) {
3285 case 2:
3286 num_format = V_008F14_IMG_FMASK_8_2_2;
3287 break;
3288 case 4:
3289 num_format = V_008F14_IMG_FMASK_8_4_4;
3290 break;
3291 case 8:
3292 num_format = V_008F14_IMG_FMASK_32_8_8;
3293 break;
3294 default:
3295 unreachable("invalid nr_samples");
3296 }
3297 } else {
3298 switch (res->nr_samples) {
3299 case 2:
3300 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3301 break;
3302 case 4:
3303 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3304 break;
3305 case 8:
3306 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3307 break;
3308 default:
3309 unreachable("invalid nr_samples");
3310 }
3311 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3312 }
3313
3314 fmask_state[0] = va >> 8;
3315 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3316 S_008F14_DATA_FORMAT_GFX6(data_format) |
3317 S_008F14_NUM_FORMAT_GFX6(num_format);
3318 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3319 S_008F18_HEIGHT(height - 1);
3320 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3321 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3322 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3323 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3324 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3325 fmask_state[4] = 0;
3326 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3327 fmask_state[6] = 0;
3328 fmask_state[7] = 0;
3329
3330 if (screen->b.chip_class >= GFX9) {
3331 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3332 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3333 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3334 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3335 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3336 } else {
3337 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3338 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3339 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3340 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3341 }
3342 }
3343 }
3344
3345 /**
3346 * Create a sampler view.
3347 *
3348 * @param ctx context
3349 * @param texture texture
3350 * @param state sampler view template
3351 * @param width0 width0 override (for compressed textures as int)
3352 * @param height0 height0 override (for compressed textures as int)
3353 * @param force_level set the base address to the level (for compressed textures)
3354 */
3355 struct pipe_sampler_view *
3356 si_create_sampler_view_custom(struct pipe_context *ctx,
3357 struct pipe_resource *texture,
3358 const struct pipe_sampler_view *state,
3359 unsigned width0, unsigned height0,
3360 unsigned force_level)
3361 {
3362 struct si_context *sctx = (struct si_context*)ctx;
3363 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3364 struct r600_texture *tmp = (struct r600_texture*)texture;
3365 unsigned base_level, first_level, last_level;
3366 unsigned char state_swizzle[4];
3367 unsigned height, depth, width;
3368 unsigned last_layer = state->u.tex.last_layer;
3369 enum pipe_format pipe_format;
3370 const struct legacy_surf_level *surflevel;
3371
3372 if (!view)
3373 return NULL;
3374
3375 /* initialize base object */
3376 view->base = *state;
3377 view->base.texture = NULL;
3378 view->base.reference.count = 1;
3379 view->base.context = ctx;
3380
3381 assert(texture);
3382 pipe_resource_reference(&view->base.texture, texture);
3383
3384 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3385 state->format == PIPE_FORMAT_S8X24_UINT ||
3386 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3387 state->format == PIPE_FORMAT_S8_UINT)
3388 view->is_stencil_sampler = true;
3389
3390 /* Buffer resource. */
3391 if (texture->target == PIPE_BUFFER) {
3392 si_make_buffer_descriptor(sctx->screen,
3393 (struct r600_resource *)texture,
3394 state->format,
3395 state->u.buf.offset,
3396 state->u.buf.size,
3397 view->state);
3398 return &view->base;
3399 }
3400
3401 state_swizzle[0] = state->swizzle_r;
3402 state_swizzle[1] = state->swizzle_g;
3403 state_swizzle[2] = state->swizzle_b;
3404 state_swizzle[3] = state->swizzle_a;
3405
3406 base_level = 0;
3407 first_level = state->u.tex.first_level;
3408 last_level = state->u.tex.last_level;
3409 width = width0;
3410 height = height0;
3411 depth = texture->depth0;
3412
3413 if (sctx->b.chip_class <= VI && force_level) {
3414 assert(force_level == first_level &&
3415 force_level == last_level);
3416 base_level = force_level;
3417 first_level = 0;
3418 last_level = 0;
3419 width = u_minify(width, force_level);
3420 height = u_minify(height, force_level);
3421 depth = u_minify(depth, force_level);
3422 }
3423
3424 /* This is not needed if state trackers set last_layer correctly. */
3425 if (state->target == PIPE_TEXTURE_1D ||
3426 state->target == PIPE_TEXTURE_2D ||
3427 state->target == PIPE_TEXTURE_RECT ||
3428 state->target == PIPE_TEXTURE_CUBE)
3429 last_layer = state->u.tex.first_layer;
3430
3431 /* Texturing with separate depth and stencil. */
3432 pipe_format = state->format;
3433
3434 /* Depth/stencil texturing sometimes needs separate texture. */
3435 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3436 if (!tmp->flushed_depth_texture &&
3437 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3438 pipe_resource_reference(&view->base.texture, NULL);
3439 FREE(view);
3440 return NULL;
3441 }
3442
3443 assert(tmp->flushed_depth_texture);
3444
3445 /* Override format for the case where the flushed texture
3446 * contains only Z or only S.
3447 */
3448 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3449 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3450
3451 tmp = tmp->flushed_depth_texture;
3452 }
3453
3454 surflevel = tmp->surface.u.legacy.level;
3455
3456 if (tmp->db_compatible) {
3457 if (!view->is_stencil_sampler)
3458 pipe_format = tmp->db_render_format;
3459
3460 switch (pipe_format) {
3461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3462 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3463 break;
3464 case PIPE_FORMAT_X8Z24_UNORM:
3465 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3466 /* Z24 is always stored like this for DB
3467 * compatibility.
3468 */
3469 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3470 break;
3471 case PIPE_FORMAT_X24S8_UINT:
3472 case PIPE_FORMAT_S8X24_UINT:
3473 case PIPE_FORMAT_X32_S8X24_UINT:
3474 pipe_format = PIPE_FORMAT_S8_UINT;
3475 surflevel = tmp->surface.u.legacy.stencil_level;
3476 break;
3477 default:;
3478 }
3479 }
3480
3481 view->dcc_incompatible =
3482 vi_dcc_formats_are_incompatible(texture,
3483 state->u.tex.first_level,
3484 state->format);
3485
3486 si_make_texture_descriptor(sctx->screen, tmp, true,
3487 state->target, pipe_format, state_swizzle,
3488 first_level, last_level,
3489 state->u.tex.first_layer, last_layer,
3490 width, height, depth,
3491 view->state, view->fmask_state);
3492
3493 view->base_level_info = &surflevel[base_level];
3494 view->base_level = base_level;
3495 view->block_width = util_format_get_blockwidth(pipe_format);
3496 return &view->base;
3497 }
3498
3499 static struct pipe_sampler_view *
3500 si_create_sampler_view(struct pipe_context *ctx,
3501 struct pipe_resource *texture,
3502 const struct pipe_sampler_view *state)
3503 {
3504 return si_create_sampler_view_custom(ctx, texture, state,
3505 texture ? texture->width0 : 0,
3506 texture ? texture->height0 : 0, 0);
3507 }
3508
3509 static void si_sampler_view_destroy(struct pipe_context *ctx,
3510 struct pipe_sampler_view *state)
3511 {
3512 struct si_sampler_view *view = (struct si_sampler_view *)state;
3513
3514 pipe_resource_reference(&state->texture, NULL);
3515 FREE(view);
3516 }
3517
3518 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3519 {
3520 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3521 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3522 (linear_filter &&
3523 (wrap == PIPE_TEX_WRAP_CLAMP ||
3524 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3525 }
3526
3527 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3528 {
3529 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3530 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3531
3532 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3533 state->border_color.ui[2] || state->border_color.ui[3]) &&
3534 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3535 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3536 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3537 }
3538
3539 static void *si_create_sampler_state(struct pipe_context *ctx,
3540 const struct pipe_sampler_state *state)
3541 {
3542 struct si_context *sctx = (struct si_context *)ctx;
3543 struct r600_common_screen *rscreen = sctx->b.screen;
3544 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3545 unsigned border_color_type, border_color_index = 0;
3546 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3547 : state->max_anisotropy;
3548 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3549
3550 if (!rstate) {
3551 return NULL;
3552 }
3553
3554 if (!sampler_state_needs_border_color(state))
3555 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3556 else if (state->border_color.f[0] == 0 &&
3557 state->border_color.f[1] == 0 &&
3558 state->border_color.f[2] == 0 &&
3559 state->border_color.f[3] == 0)
3560 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3561 else if (state->border_color.f[0] == 0 &&
3562 state->border_color.f[1] == 0 &&
3563 state->border_color.f[2] == 0 &&
3564 state->border_color.f[3] == 1)
3565 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3566 else if (state->border_color.f[0] == 1 &&
3567 state->border_color.f[1] == 1 &&
3568 state->border_color.f[2] == 1 &&
3569 state->border_color.f[3] == 1)
3570 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3571 else {
3572 int i;
3573
3574 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3575
3576 /* Check if the border has been uploaded already. */
3577 for (i = 0; i < sctx->border_color_count; i++)
3578 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3579 sizeof(state->border_color)) == 0)
3580 break;
3581
3582 if (i >= SI_MAX_BORDER_COLORS) {
3583 /* Getting 4096 unique border colors is very unlikely. */
3584 fprintf(stderr, "radeonsi: The border color table is full. "
3585 "Any new border colors will be just black. "
3586 "Please file a bug.\n");
3587 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3588 } else {
3589 if (i == sctx->border_color_count) {
3590 /* Upload a new border color. */
3591 memcpy(&sctx->border_color_table[i], &state->border_color,
3592 sizeof(state->border_color));
3593 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3594 &state->border_color,
3595 sizeof(state->border_color));
3596 sctx->border_color_count++;
3597 }
3598
3599 border_color_index = i;
3600 }
3601 }
3602
3603 #ifdef DEBUG
3604 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3605 #endif
3606 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3607 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3608 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3609 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3610 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3611 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3612 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3613 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3614 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3615 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3616 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3617 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3618 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3619 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3620 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3621 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3622 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3623 S_008F38_MIP_POINT_PRECLAMP(1) |
3624 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3625 S_008F38_FILTER_PREC_FIX(1) |
3626 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3627 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3628 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3629 return rstate;
3630 }
3631
3632 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3633 {
3634 struct si_context *sctx = (struct si_context *)ctx;
3635
3636 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3637 return;
3638
3639 sctx->sample_mask.sample_mask = sample_mask;
3640 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3641 }
3642
3643 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3644 {
3645 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3646 unsigned mask = sctx->sample_mask.sample_mask;
3647
3648 /* Needed for line and polygon smoothing as well as for the Polaris
3649 * small primitive filter. We expect the state tracker to take care of
3650 * this for us.
3651 */
3652 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3653 (mask & 1 && sctx->blitter->running));
3654
3655 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3656 radeon_emit(cs, mask | (mask << 16));
3657 radeon_emit(cs, mask | (mask << 16));
3658 }
3659
3660 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3661 {
3662 #ifdef DEBUG
3663 struct si_sampler_state *s = state;
3664
3665 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3666 s->magic = 0;
3667 #endif
3668 free(state);
3669 }
3670
3671 /*
3672 * Vertex elements & buffers
3673 */
3674
3675 static void *si_create_vertex_elements(struct pipe_context *ctx,
3676 unsigned count,
3677 const struct pipe_vertex_element *elements)
3678 {
3679 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3680 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3681 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3682 int i;
3683
3684 assert(count <= SI_MAX_ATTRIBS);
3685 if (!v)
3686 return NULL;
3687
3688 v->count = count;
3689 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3690
3691 for (i = 0; i < count; ++i) {
3692 const struct util_format_description *desc;
3693 const struct util_format_channel_description *channel;
3694 unsigned data_format, num_format;
3695 int first_non_void;
3696 unsigned vbo_index = elements[i].vertex_buffer_index;
3697 unsigned char swizzle[4];
3698
3699 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3700 FREE(v);
3701 return NULL;
3702 }
3703
3704 if (!used[vbo_index]) {
3705 v->first_vb_use_mask |= 1 << i;
3706 used[vbo_index] = true;
3707 }
3708
3709 desc = util_format_description(elements[i].src_format);
3710 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3711 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3712 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3713 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3714 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3715
3716 v->format_size[i] = desc->block.bits / 8;
3717
3718 /* The hardware always treats the 2-bit alpha channel as
3719 * unsigned, so a shader workaround is needed. The affected
3720 * chips are VI and older except Stoney (GFX8.1).
3721 */
3722 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3723 sscreen->b.chip_class <= VI &&
3724 sscreen->b.family != CHIP_STONEY) {
3725 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3726 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3727 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3728 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3729 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3730 /* This isn't actually used in OpenGL. */
3731 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3732 }
3733 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3734 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3735 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3736 else
3737 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3738 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3739 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3740 if (channel->normalized) {
3741 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3742 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3743 else
3744 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3745 } else {
3746 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3747 }
3748 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3749 if (channel->normalized) {
3750 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3751 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3752 else
3753 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3754 } else {
3755 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3756 }
3757 }
3758 } else if (channel && channel->size == 64 &&
3759 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3760 switch (desc->nr_channels) {
3761 case 1:
3762 case 2:
3763 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3764 swizzle[0] = PIPE_SWIZZLE_X;
3765 swizzle[1] = PIPE_SWIZZLE_Y;
3766 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3767 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3768 break;
3769 case 3:
3770 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3771 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3772 swizzle[1] = PIPE_SWIZZLE_Y;
3773 swizzle[2] = PIPE_SWIZZLE_0;
3774 swizzle[3] = PIPE_SWIZZLE_0;
3775 break;
3776 case 4:
3777 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3778 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3779 swizzle[1] = PIPE_SWIZZLE_Y;
3780 swizzle[2] = PIPE_SWIZZLE_Z;
3781 swizzle[3] = PIPE_SWIZZLE_W;
3782 break;
3783 default:
3784 assert(0);
3785 }
3786 } else if (channel && desc->nr_channels == 3) {
3787 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3788
3789 if (channel->size == 8) {
3790 if (channel->pure_integer)
3791 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3792 else
3793 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3794 } else if (channel->size == 16) {
3795 if (channel->pure_integer)
3796 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3797 else
3798 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3799 }
3800 }
3801
3802 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3803 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3804 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3805 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3806 S_008F0C_NUM_FORMAT(num_format) |
3807 S_008F0C_DATA_FORMAT(data_format);
3808 }
3809 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3810
3811 return v;
3812 }
3813
3814 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3815 {
3816 struct si_context *sctx = (struct si_context *)ctx;
3817 struct si_vertex_element *v = (struct si_vertex_element*)state;
3818
3819 sctx->vertex_elements = v;
3820 sctx->vertex_buffers_dirty = true;
3821 sctx->do_update_shaders = true;
3822 }
3823
3824 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3825 {
3826 struct si_context *sctx = (struct si_context *)ctx;
3827
3828 if (sctx->vertex_elements == state)
3829 sctx->vertex_elements = NULL;
3830 FREE(state);
3831 }
3832
3833 static void si_set_vertex_buffers(struct pipe_context *ctx,
3834 unsigned start_slot, unsigned count,
3835 const struct pipe_vertex_buffer *buffers)
3836 {
3837 struct si_context *sctx = (struct si_context *)ctx;
3838 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3839 int i;
3840
3841 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3842
3843 if (buffers) {
3844 for (i = 0; i < count; i++) {
3845 const struct pipe_vertex_buffer *src = buffers + i;
3846 struct pipe_vertex_buffer *dsti = dst + i;
3847 struct pipe_resource *buf = src->buffer.resource;
3848
3849 pipe_resource_reference(&dsti->buffer.resource, buf);
3850 dsti->buffer_offset = src->buffer_offset;
3851 dsti->stride = src->stride;
3852 r600_context_add_resource_size(ctx, buf);
3853 if (buf)
3854 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3855 }
3856 } else {
3857 for (i = 0; i < count; i++) {
3858 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3859 }
3860 }
3861 sctx->vertex_buffers_dirty = true;
3862 }
3863
3864 /*
3865 * Misc
3866 */
3867
3868 static void si_set_tess_state(struct pipe_context *ctx,
3869 const float default_outer_level[4],
3870 const float default_inner_level[2])
3871 {
3872 struct si_context *sctx = (struct si_context *)ctx;
3873 struct pipe_constant_buffer cb;
3874 float array[8];
3875
3876 memcpy(array, default_outer_level, sizeof(float) * 4);
3877 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3878
3879 cb.buffer = NULL;
3880 cb.user_buffer = NULL;
3881 cb.buffer_size = sizeof(array);
3882
3883 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3884 (void*)array, sizeof(array),
3885 &cb.buffer_offset);
3886
3887 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3888 pipe_resource_reference(&cb.buffer, NULL);
3889 }
3890
3891 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3892 {
3893 struct si_context *sctx = (struct si_context *)ctx;
3894
3895 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3896 SI_CONTEXT_INV_GLOBAL_L2 |
3897 SI_CONTEXT_FLUSH_AND_INV_CB;
3898 sctx->framebuffer.do_update_surf_dirtiness = true;
3899 }
3900
3901 /* This only ensures coherency for shader image/buffer stores. */
3902 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3903 {
3904 struct si_context *sctx = (struct si_context *)ctx;
3905
3906 /* Subsequent commands must wait for all shader invocations to
3907 * complete. */
3908 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3909 SI_CONTEXT_CS_PARTIAL_FLUSH;
3910
3911 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3912 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3913 SI_CONTEXT_INV_VMEM_L1;
3914
3915 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3916 PIPE_BARRIER_SHADER_BUFFER |
3917 PIPE_BARRIER_TEXTURE |
3918 PIPE_BARRIER_IMAGE |
3919 PIPE_BARRIER_STREAMOUT_BUFFER |
3920 PIPE_BARRIER_GLOBAL_BUFFER)) {
3921 /* As far as I can tell, L1 contents are written back to L2
3922 * automatically at end of shader, but the contents of other
3923 * L1 caches might still be stale. */
3924 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3925 }
3926
3927 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3928 /* Indices are read through TC L2 since VI.
3929 * L1 isn't used.
3930 */
3931 if (sctx->screen->b.chip_class <= CIK)
3932 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3933 }
3934
3935 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3936 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3937 SI_CONTEXT_FLUSH_AND_INV_DB;
3938
3939 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3940 PIPE_BARRIER_INDIRECT_BUFFER))
3941 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3942 }
3943
3944 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3945 {
3946 struct pipe_blend_state blend;
3947
3948 memset(&blend, 0, sizeof(blend));
3949 blend.independent_blend_enable = true;
3950 blend.rt[0].colormask = 0xf;
3951 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3952 }
3953
3954 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3955 bool include_draw_vbo)
3956 {
3957 si_need_cs_space((struct si_context*)ctx);
3958 }
3959
3960 static void si_init_config(struct si_context *sctx);
3961
3962 void si_init_state_functions(struct si_context *sctx)
3963 {
3964 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3965 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3966 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3967 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3968 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3969
3970 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3971 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3972 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3973 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3974 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3975 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3976 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3977 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3978 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3979 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3980
3981 sctx->b.b.create_blend_state = si_create_blend_state;
3982 sctx->b.b.bind_blend_state = si_bind_blend_state;
3983 sctx->b.b.delete_blend_state = si_delete_blend_state;
3984 sctx->b.b.set_blend_color = si_set_blend_color;
3985
3986 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3987 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3988 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3989
3990 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3991 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3992 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3993
3994 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3995 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3996 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3997 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3998 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3999
4000 sctx->b.b.set_clip_state = si_set_clip_state;
4001 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4002
4003 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4004 sctx->b.b.get_sample_position = cayman_get_sample_position;
4005
4006 sctx->b.b.create_sampler_state = si_create_sampler_state;
4007 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4008
4009 sctx->b.b.create_sampler_view = si_create_sampler_view;
4010 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4011
4012 sctx->b.b.set_sample_mask = si_set_sample_mask;
4013
4014 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4015 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4016 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4017 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4018
4019 sctx->b.b.texture_barrier = si_texture_barrier;
4020 sctx->b.b.memory_barrier = si_memory_barrier;
4021 sctx->b.b.set_min_samples = si_set_min_samples;
4022 sctx->b.b.set_tess_state = si_set_tess_state;
4023
4024 sctx->b.b.set_active_query_state = si_set_active_query_state;
4025 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4026 sctx->b.save_qbo_state = si_save_qbo_state;
4027 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4028
4029 sctx->b.b.draw_vbo = si_draw_vbo;
4030
4031 si_init_config(sctx);
4032 }
4033
4034 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4035 {
4036 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4037 }
4038
4039 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4040 struct r600_texture *rtex,
4041 struct radeon_bo_metadata *md)
4042 {
4043 struct si_screen *sscreen = (struct si_screen*)rscreen;
4044 struct pipe_resource *res = &rtex->resource.b.b;
4045 static const unsigned char swizzle[] = {
4046 PIPE_SWIZZLE_X,
4047 PIPE_SWIZZLE_Y,
4048 PIPE_SWIZZLE_Z,
4049 PIPE_SWIZZLE_W
4050 };
4051 uint32_t desc[8], i;
4052 bool is_array = util_resource_is_array_texture(res);
4053
4054 /* DRM 2.x.x doesn't support this. */
4055 if (rscreen->info.drm_major != 3)
4056 return;
4057
4058 assert(rtex->dcc_separate_buffer == NULL);
4059 assert(rtex->fmask.size == 0);
4060
4061 /* Metadata image format format version 1:
4062 * [0] = 1 (metadata format identifier)
4063 * [1] = (VENDOR_ID << 16) | PCI_ID
4064 * [2:9] = image descriptor for the whole resource
4065 * [2] is always 0, because the base address is cleared
4066 * [9] is the DCC offset bits [39:8] from the beginning of
4067 * the buffer
4068 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4069 */
4070
4071 md->metadata[0] = 1; /* metadata image format version 1 */
4072
4073 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4074 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4075
4076 si_make_texture_descriptor(sscreen, rtex, true,
4077 res->target, res->format,
4078 swizzle, 0, res->last_level, 0,
4079 is_array ? res->array_size - 1 : 0,
4080 res->width0, res->height0, res->depth0,
4081 desc, NULL);
4082
4083 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4084 0, 0, rtex->surface.blk_w, false, desc);
4085
4086 /* Clear the base address and set the relative DCC offset. */
4087 desc[0] = 0;
4088 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4089 desc[7] = rtex->dcc_offset >> 8;
4090
4091 /* Dwords [2:9] contain the image descriptor. */
4092 memcpy(&md->metadata[2], desc, sizeof(desc));
4093 md->size_metadata = 10 * 4;
4094
4095 /* Dwords [10:..] contain the mipmap level offsets. */
4096 if (rscreen->chip_class <= VI) {
4097 for (i = 0; i <= res->last_level; i++)
4098 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4099
4100 md->size_metadata += (1 + res->last_level) * 4;
4101 }
4102 }
4103
4104 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4105 struct r600_texture *rtex,
4106 struct radeon_bo_metadata *md)
4107 {
4108 uint32_t *desc = &md->metadata[2];
4109
4110 if (rscreen->chip_class < VI)
4111 return;
4112
4113 /* Return if DCC is enabled. The texture should be set up with it
4114 * already.
4115 */
4116 if (md->size_metadata >= 11 * 4 &&
4117 md->metadata[0] != 0 &&
4118 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4119 G_008F28_COMPRESSION_EN(desc[6])) {
4120 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4121 return;
4122 }
4123
4124 /* Disable DCC. These are always set by texture_from_handle and must
4125 * be cleared here.
4126 */
4127 rtex->dcc_offset = 0;
4128 }
4129
4130 void si_init_screen_state_functions(struct si_screen *sscreen)
4131 {
4132 sscreen->b.b.is_format_supported = si_is_format_supported;
4133 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4134 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4135 }
4136
4137 static void
4138 si_write_harvested_raster_configs(struct si_context *sctx,
4139 struct si_pm4_state *pm4,
4140 unsigned raster_config,
4141 unsigned raster_config_1)
4142 {
4143 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4144 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4145 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4146 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4147 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4148 unsigned rb_per_se = num_rb / num_se;
4149 unsigned se_mask[4];
4150 unsigned se;
4151
4152 se_mask[0] = ((1 << rb_per_se) - 1);
4153 se_mask[1] = (se_mask[0] << rb_per_se);
4154 se_mask[2] = (se_mask[1] << rb_per_se);
4155 se_mask[3] = (se_mask[2] << rb_per_se);
4156
4157 se_mask[0] &= rb_mask;
4158 se_mask[1] &= rb_mask;
4159 se_mask[2] &= rb_mask;
4160 se_mask[3] &= rb_mask;
4161
4162 assert(num_se == 1 || num_se == 2 || num_se == 4);
4163 assert(sh_per_se == 1 || sh_per_se == 2);
4164 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4165
4166 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4167 * fields are for, so I'm leaving them as their default
4168 * values. */
4169
4170 for (se = 0; se < num_se; se++) {
4171 unsigned raster_config_se = raster_config;
4172 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4173 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4174 int idx = (se / 2) * 2;
4175
4176 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4177 raster_config_se &= C_028350_SE_MAP;
4178
4179 if (!se_mask[idx]) {
4180 raster_config_se |=
4181 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4182 } else {
4183 raster_config_se |=
4184 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4185 }
4186 }
4187
4188 pkr0_mask &= rb_mask;
4189 pkr1_mask &= rb_mask;
4190 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4191 raster_config_se &= C_028350_PKR_MAP;
4192
4193 if (!pkr0_mask) {
4194 raster_config_se |=
4195 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4196 } else {
4197 raster_config_se |=
4198 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4199 }
4200 }
4201
4202 if (rb_per_se >= 2) {
4203 unsigned rb0_mask = 1 << (se * rb_per_se);
4204 unsigned rb1_mask = rb0_mask << 1;
4205
4206 rb0_mask &= rb_mask;
4207 rb1_mask &= rb_mask;
4208 if (!rb0_mask || !rb1_mask) {
4209 raster_config_se &= C_028350_RB_MAP_PKR0;
4210
4211 if (!rb0_mask) {
4212 raster_config_se |=
4213 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4214 } else {
4215 raster_config_se |=
4216 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4217 }
4218 }
4219
4220 if (rb_per_se > 2) {
4221 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4222 rb1_mask = rb0_mask << 1;
4223 rb0_mask &= rb_mask;
4224 rb1_mask &= rb_mask;
4225 if (!rb0_mask || !rb1_mask) {
4226 raster_config_se &= C_028350_RB_MAP_PKR1;
4227
4228 if (!rb0_mask) {
4229 raster_config_se |=
4230 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4231 } else {
4232 raster_config_se |=
4233 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4234 }
4235 }
4236 }
4237 }
4238
4239 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4240 if (sctx->b.chip_class < CIK)
4241 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4242 SE_INDEX(se) | SH_BROADCAST_WRITES |
4243 INSTANCE_BROADCAST_WRITES);
4244 else
4245 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4246 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4247 S_030800_INSTANCE_BROADCAST_WRITES(1));
4248 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4249 }
4250
4251 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4252 if (sctx->b.chip_class < CIK)
4253 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4254 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4255 INSTANCE_BROADCAST_WRITES);
4256 else {
4257 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4258 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4259 S_030800_INSTANCE_BROADCAST_WRITES(1));
4260
4261 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4262 (!se_mask[2] && !se_mask[3]))) {
4263 raster_config_1 &= C_028354_SE_PAIR_MAP;
4264
4265 if (!se_mask[0] && !se_mask[1]) {
4266 raster_config_1 |=
4267 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4268 } else {
4269 raster_config_1 |=
4270 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4271 }
4272 }
4273
4274 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4275 }
4276 }
4277
4278 static void si_init_config(struct si_context *sctx)
4279 {
4280 struct si_screen *sscreen = sctx->screen;
4281 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4282 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4283 unsigned raster_config, raster_config_1;
4284 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4285 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4286
4287 if (!pm4)
4288 return;
4289
4290 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4291 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4292 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4293 si_pm4_cmd_end(pm4, false);
4294
4295 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4296 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4297
4298 /* FIXME calculate these values somehow ??? */
4299 if (sctx->b.chip_class <= VI) {
4300 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4301 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4302 }
4303 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4304
4305 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4306 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4307
4308 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4309 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4310 if (sctx->b.chip_class >= GFX9)
4311 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4312 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4313 if (sctx->b.chip_class < CIK)
4314 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4315 S_008A14_CLIP_VTX_REORDER_ENA(1));
4316
4317 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4318 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4319
4320 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4321
4322 switch (sctx->screen->b.family) {
4323 case CHIP_TAHITI:
4324 case CHIP_PITCAIRN:
4325 raster_config = 0x2a00126a;
4326 raster_config_1 = 0x00000000;
4327 break;
4328 case CHIP_VERDE:
4329 raster_config = 0x0000124a;
4330 raster_config_1 = 0x00000000;
4331 break;
4332 case CHIP_OLAND:
4333 raster_config = 0x00000082;
4334 raster_config_1 = 0x00000000;
4335 break;
4336 case CHIP_HAINAN:
4337 raster_config = 0x00000000;
4338 raster_config_1 = 0x00000000;
4339 break;
4340 case CHIP_BONAIRE:
4341 raster_config = 0x16000012;
4342 raster_config_1 = 0x00000000;
4343 break;
4344 case CHIP_HAWAII:
4345 raster_config = 0x3a00161a;
4346 raster_config_1 = 0x0000002e;
4347 break;
4348 case CHIP_FIJI:
4349 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4350 /* old kernels with old tiling config */
4351 raster_config = 0x16000012;
4352 raster_config_1 = 0x0000002a;
4353 } else {
4354 raster_config = 0x3a00161a;
4355 raster_config_1 = 0x0000002e;
4356 }
4357 break;
4358 case CHIP_POLARIS10:
4359 raster_config = 0x16000012;
4360 raster_config_1 = 0x0000002a;
4361 break;
4362 case CHIP_POLARIS11:
4363 case CHIP_POLARIS12:
4364 raster_config = 0x16000012;
4365 raster_config_1 = 0x00000000;
4366 break;
4367 case CHIP_TONGA:
4368 raster_config = 0x16000012;
4369 raster_config_1 = 0x0000002a;
4370 break;
4371 case CHIP_ICELAND:
4372 if (num_rb == 1)
4373 raster_config = 0x00000000;
4374 else
4375 raster_config = 0x00000002;
4376 raster_config_1 = 0x00000000;
4377 break;
4378 case CHIP_CARRIZO:
4379 raster_config = 0x00000002;
4380 raster_config_1 = 0x00000000;
4381 break;
4382 case CHIP_KAVERI:
4383 /* KV should be 0x00000002, but that causes problems with radeon */
4384 raster_config = 0x00000000; /* 0x00000002 */
4385 raster_config_1 = 0x00000000;
4386 break;
4387 case CHIP_KABINI:
4388 case CHIP_MULLINS:
4389 case CHIP_STONEY:
4390 raster_config = 0x00000000;
4391 raster_config_1 = 0x00000000;
4392 break;
4393 default:
4394 if (sctx->b.chip_class <= VI) {
4395 fprintf(stderr,
4396 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4397 raster_config = 0x00000000;
4398 raster_config_1 = 0x00000000;
4399 }
4400 break;
4401 }
4402
4403 if (sctx->b.chip_class <= VI) {
4404 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4405 /* Always use the default config when all backends are enabled
4406 * (or when we failed to determine the enabled backends).
4407 */
4408 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4409 raster_config);
4410 if (sctx->b.chip_class >= CIK)
4411 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4412 raster_config_1);
4413 } else {
4414 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4415 }
4416 }
4417
4418 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4419 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4420 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4421 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4422 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4423 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4424 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4425
4426 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4427 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4428 S_028230_ER_TRI(0xA) |
4429 S_028230_ER_POINT(0xA) |
4430 S_028230_ER_RECT(0xA) |
4431 /* Required by DX10_DIAMOND_TEST_ENA: */
4432 S_028230_ER_LINE_LR(0x1A) |
4433 S_028230_ER_LINE_RL(0x26) |
4434 S_028230_ER_LINE_TB(0xA) |
4435 S_028230_ER_LINE_BT(0xA));
4436 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4437 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4438 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4439 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4440 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4441 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4442 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4443
4444 if (sctx->b.chip_class >= GFX9) {
4445 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4446 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4447 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4448 } else {
4449 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4450 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4451 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4452 }
4453
4454 if (sctx->b.chip_class >= CIK) {
4455 if (sctx->b.chip_class >= GFX9) {
4456 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4457 } else {
4458 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4459 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4460 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4461
4462 /* If this is 0, Bonaire can hang even if GS isn't being used.
4463 * Other chips are unaffected. These are suboptimal values,
4464 * but we don't use on-chip GS.
4465 */
4466 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4467 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4468 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4469 }
4470 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4471
4472 if (sscreen->b.info.num_good_compute_units /
4473 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4474 /* Too few available compute units per SH. Disallowing
4475 * VS to run on CU0 could hurt us more than late VS
4476 * allocation would help.
4477 *
4478 * LATE_ALLOC_VS = 2 is the highest safe number.
4479 */
4480 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4481 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4482 } else {
4483 /* Set LATE_ALLOC_VS == 31. It should be less than
4484 * the number of scratch waves. Limitations:
4485 * - VS can't execute on CU0.
4486 * - If HS writes outputs to LDS, LS can't execute on CU0.
4487 */
4488 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4489 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4490 }
4491
4492 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4493 }
4494
4495 if (sctx->b.chip_class >= VI) {
4496 unsigned vgt_tess_distribution;
4497
4498 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4499 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4500 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4501 if (sctx->b.family < CHIP_POLARIS10)
4502 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4503 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4504
4505 vgt_tess_distribution =
4506 S_028B50_ACCUM_ISOLINE(32) |
4507 S_028B50_ACCUM_TRI(11) |
4508 S_028B50_ACCUM_QUAD(11) |
4509 S_028B50_DONUT_SPLIT(16);
4510
4511 /* Testing with Unigine Heaven extreme tesselation yielded best results
4512 * with TRAP_SPLIT = 3.
4513 */
4514 if (sctx->b.family == CHIP_FIJI ||
4515 sctx->b.family >= CHIP_POLARIS10)
4516 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4517
4518 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4519 } else {
4520 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4521 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4522 }
4523
4524 if (sctx->screen->b.has_rbplus)
4525 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4526
4527 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4528 if (sctx->b.chip_class >= CIK)
4529 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4530 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4531 RADEON_PRIO_BORDER_COLORS);
4532
4533 if (sctx->b.chip_class >= GFX9) {
4534 unsigned num_se = sscreen->b.info.max_se;
4535 unsigned pc_lines = 0;
4536
4537 switch (sctx->b.family) {
4538 case CHIP_VEGA10:
4539 pc_lines = 4096;
4540 break;
4541 default:
4542 assert(0);
4543 }
4544
4545 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4546 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4547 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4548 /* TODO: We can use this to disable RBs for rendering to GART: */
4549 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4550 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4551 /* TODO: Enable the binner: */
4552 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4553 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4554 S_028C44_DISABLE_START_OF_PRIM(1));
4555 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4556 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4557 S_028C48_MAX_PRIM_PER_BATCH(1023));
4558 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4559 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4560 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4561 }
4562
4563 si_pm4_upload_indirect_buffer(sctx, pm4);
4564 sctx->init_config = pm4;
4565 }