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radeonsi: implement MSAA for CIK
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528 rs->line_stipple_enable = state->line_stipple_enable;
529
530 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
531 state->fill_back != PIPE_POLYGON_MODE_FILL);
532
533 if (state->flatshade_first)
534 prov_vtx = 0;
535
536 rs->flatshade = state->flatshade;
537 rs->sprite_coord_enable = state->sprite_coord_enable;
538 rs->pa_sc_line_stipple = state->line_stipple_enable ?
539 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
540 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
541 rs->pa_su_sc_mode_cntl =
542 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
543 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
544 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
545 S_028814_FACE(!state->front_ccw) |
546 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
548 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
549 S_028814_POLY_MODE(polygon_dual_mode) |
550 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
551 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
552 rs->pa_cl_clip_cntl =
553 S_028810_PS_UCP_MODE(3) |
554 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
555 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
556 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
557 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
558
559 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
560
561 /* offset */
562 rs->offset_units = state->offset_units;
563 rs->offset_scale = state->offset_scale * 12.0f;
564
565 tmp = S_0286D4_FLAT_SHADE_ENA(1);
566 if (state->sprite_coord_enable) {
567 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
568 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
569 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
570 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
571 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
572 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
573 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
574 }
575 }
576 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
577
578 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
579 /* point size 12.4 fixed point */
580 tmp = (unsigned)(state->point_size * 8.0);
581 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
582
583 if (state->point_size_per_vertex) {
584 psize_min = util_get_min_point_size(state);
585 psize_max = 8192;
586 } else {
587 /* Force the point size to be as if the vertex output was disabled. */
588 psize_min = state->point_size;
589 psize_max = state->point_size;
590 }
591 /* Divide by two, because 0.5 = 1 pixel. */
592 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
593 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
594 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
595
596 tmp = (unsigned)state->line_width * 8;
597 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
598 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
599 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
600 S_028A48_MSAA_ENABLE(state->multisample));
601
602 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
603 S_028BE4_PIX_CENTER(state->half_pixel_center) |
604 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
605 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
608 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
609
610 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
611 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
612
613 return rs;
614 }
615
616 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
617 {
618 struct r600_context *rctx = (struct r600_context *)ctx;
619 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
620
621 if (state == NULL)
622 return;
623
624 // TODO
625 rctx->sprite_coord_enable = rs->sprite_coord_enable;
626 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
627 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
628
629 si_pm4_bind_state(rctx, rasterizer, rs);
630 si_update_fb_rs_state(rctx);
631 }
632
633 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
634 {
635 struct r600_context *rctx = (struct r600_context *)ctx;
636 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
637 }
638
639 /*
640 * infeered state between dsa and stencil ref
641 */
642 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
643 {
644 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
645 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
646 struct si_state_dsa *dsa = rctx->queued.named.dsa;
647
648 if (pm4 == NULL)
649 return;
650
651 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
652 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
653 S_028430_STENCILMASK(dsa->valuemask[0]) |
654 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
655 S_028430_STENCILOPVAL(1));
656 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
657 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
658 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
659 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
660 S_028434_STENCILOPVAL_BF(1));
661
662 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
663 }
664
665 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
666 const struct pipe_stencil_ref *state)
667 {
668 struct r600_context *rctx = (struct r600_context *)ctx;
669 rctx->stencil_ref = *state;
670 si_update_dsa_stencil_ref(rctx);
671 }
672
673
674 /*
675 * DSA
676 */
677
678 static uint32_t si_translate_stencil_op(int s_op)
679 {
680 switch (s_op) {
681 case PIPE_STENCIL_OP_KEEP:
682 return V_02842C_STENCIL_KEEP;
683 case PIPE_STENCIL_OP_ZERO:
684 return V_02842C_STENCIL_ZERO;
685 case PIPE_STENCIL_OP_REPLACE:
686 return V_02842C_STENCIL_REPLACE_TEST;
687 case PIPE_STENCIL_OP_INCR:
688 return V_02842C_STENCIL_ADD_CLAMP;
689 case PIPE_STENCIL_OP_DECR:
690 return V_02842C_STENCIL_SUB_CLAMP;
691 case PIPE_STENCIL_OP_INCR_WRAP:
692 return V_02842C_STENCIL_ADD_WRAP;
693 case PIPE_STENCIL_OP_DECR_WRAP:
694 return V_02842C_STENCIL_SUB_WRAP;
695 case PIPE_STENCIL_OP_INVERT:
696 return V_02842C_STENCIL_INVERT;
697 default:
698 R600_ERR("Unknown stencil op %d", s_op);
699 assert(0);
700 break;
701 }
702 return 0;
703 }
704
705 static void *si_create_dsa_state(struct pipe_context *ctx,
706 const struct pipe_depth_stencil_alpha_state *state)
707 {
708 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
709 struct si_pm4_state *pm4 = &dsa->pm4;
710 unsigned db_depth_control;
711 unsigned db_render_override, db_render_control;
712 uint32_t db_stencil_control = 0;
713
714 if (dsa == NULL) {
715 return NULL;
716 }
717
718 dsa->valuemask[0] = state->stencil[0].valuemask;
719 dsa->valuemask[1] = state->stencil[1].valuemask;
720 dsa->writemask[0] = state->stencil[0].writemask;
721 dsa->writemask[1] = state->stencil[1].writemask;
722
723 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
724 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
725 S_028800_ZFUNC(state->depth.func);
726
727 /* stencil */
728 if (state->stencil[0].enabled) {
729 db_depth_control |= S_028800_STENCIL_ENABLE(1);
730 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
731 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
732 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
733 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
734
735 if (state->stencil[1].enabled) {
736 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
737 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
738 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
739 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
740 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
741 }
742 }
743
744 /* alpha */
745 if (state->alpha.enabled) {
746 dsa->alpha_func = state->alpha.func;
747 dsa->alpha_ref = state->alpha.ref_value;
748
749 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
750 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
751 } else {
752 dsa->alpha_func = PIPE_FUNC_ALWAYS;
753 }
754
755 /* misc */
756 db_render_control = 0;
757 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
758 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
759 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
760 /* TODO db_render_override depends on query */
761 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
762 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
763 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
764 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
765 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
766 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
767 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
768 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
769 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
770 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
771 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
772 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
773 dsa->db_render_override = db_render_override;
774
775 return dsa;
776 }
777
778 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
779 {
780 struct r600_context *rctx = (struct r600_context *)ctx;
781 struct si_state_dsa *dsa = state;
782
783 if (state == NULL)
784 return;
785
786 si_pm4_bind_state(rctx, dsa, dsa);
787 si_update_dsa_stencil_ref(rctx);
788 }
789
790 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
791 {
792 struct r600_context *rctx = (struct r600_context *)ctx;
793 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
794 }
795
796 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
797 bool copy_stencil, int sample)
798 {
799 struct pipe_depth_stencil_alpha_state dsa;
800 struct si_state_dsa *state;
801
802 memset(&dsa, 0, sizeof(dsa));
803
804 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
805 if (copy_depth || copy_stencil) {
806 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
807 S_028000_DEPTH_COPY(copy_depth) |
808 S_028000_STENCIL_COPY(copy_stencil) |
809 S_028000_COPY_CENTROID(1) |
810 S_028000_COPY_SAMPLE(sample));
811 } else {
812 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
813 S_028000_DEPTH_COMPRESS_DISABLE(1) |
814 S_028000_STENCIL_COMPRESS_DISABLE(1));
815 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
816 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
817 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
818 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
819 S_02800C_DISABLE_TILE_RATE_TILES(1));
820 }
821
822 return state;
823 }
824
825 /*
826 * format translation
827 */
828 static uint32_t si_translate_colorformat(enum pipe_format format)
829 {
830 const struct util_format_description *desc = util_format_description(format);
831
832 #define HAS_SIZE(x,y,z,w) \
833 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
834 desc->channel[2].size == (z) && desc->channel[3].size == (w))
835
836 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
837 return V_028C70_COLOR_10_11_11;
838
839 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
840 return V_028C70_COLOR_INVALID;
841
842 switch (desc->nr_channels) {
843 case 1:
844 switch (desc->channel[0].size) {
845 case 8:
846 return V_028C70_COLOR_8;
847 case 16:
848 return V_028C70_COLOR_16;
849 case 32:
850 return V_028C70_COLOR_32;
851 }
852 break;
853 case 2:
854 if (desc->channel[0].size == desc->channel[1].size) {
855 switch (desc->channel[0].size) {
856 case 8:
857 return V_028C70_COLOR_8_8;
858 case 16:
859 return V_028C70_COLOR_16_16;
860 case 32:
861 return V_028C70_COLOR_32_32;
862 }
863 } else if (HAS_SIZE(8,24,0,0)) {
864 return V_028C70_COLOR_24_8;
865 } else if (HAS_SIZE(24,8,0,0)) {
866 return V_028C70_COLOR_8_24;
867 }
868 break;
869 case 3:
870 if (HAS_SIZE(5,6,5,0)) {
871 return V_028C70_COLOR_5_6_5;
872 } else if (HAS_SIZE(32,8,24,0)) {
873 return V_028C70_COLOR_X24_8_32_FLOAT;
874 }
875 break;
876 case 4:
877 if (desc->channel[0].size == desc->channel[1].size &&
878 desc->channel[0].size == desc->channel[2].size &&
879 desc->channel[0].size == desc->channel[3].size) {
880 switch (desc->channel[0].size) {
881 case 4:
882 return V_028C70_COLOR_4_4_4_4;
883 case 8:
884 return V_028C70_COLOR_8_8_8_8;
885 case 16:
886 return V_028C70_COLOR_16_16_16_16;
887 case 32:
888 return V_028C70_COLOR_32_32_32_32;
889 }
890 } else if (HAS_SIZE(5,5,5,1)) {
891 return V_028C70_COLOR_1_5_5_5;
892 } else if (HAS_SIZE(10,10,10,2)) {
893 return V_028C70_COLOR_2_10_10_10;
894 }
895 break;
896 }
897 return V_028C70_COLOR_INVALID;
898 }
899
900 static uint32_t si_translate_colorswap(enum pipe_format format)
901 {
902 const struct util_format_description *desc = util_format_description(format);
903
904 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
905
906 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
907 return V_028C70_SWAP_STD;
908
909 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
910 return ~0;
911
912 switch (desc->nr_channels) {
913 case 1:
914 if (HAS_SWIZZLE(0,X))
915 return V_028C70_SWAP_STD; /* X___ */
916 else if (HAS_SWIZZLE(3,X))
917 return V_028C70_SWAP_ALT_REV; /* ___X */
918 break;
919 case 2:
920 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
921 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
922 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
923 return V_028C70_SWAP_STD; /* XY__ */
924 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
925 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
926 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
927 return V_028C70_SWAP_STD_REV; /* YX__ */
928 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
929 return V_028C70_SWAP_ALT; /* X__Y */
930 break;
931 case 3:
932 if (HAS_SWIZZLE(0,X))
933 return V_028C70_SWAP_STD; /* XYZ */
934 else if (HAS_SWIZZLE(0,Z))
935 return V_028C70_SWAP_STD_REV; /* ZYX */
936 break;
937 case 4:
938 /* check the middle channels, the 1st and 4th channel can be NONE */
939 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
940 return V_028C70_SWAP_STD; /* XYZW */
941 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
942 return V_028C70_SWAP_STD_REV; /* WZYX */
943 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
944 return V_028C70_SWAP_ALT; /* ZYXW */
945 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
946 return V_028C70_SWAP_ALT_REV; /* WXYZ */
947 break;
948 }
949 return ~0U;
950 }
951
952 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
953 {
954 if (R600_BIG_ENDIAN) {
955 switch(colorformat) {
956 /* 8-bit buffers. */
957 case V_028C70_COLOR_8:
958 return V_028C70_ENDIAN_NONE;
959
960 /* 16-bit buffers. */
961 case V_028C70_COLOR_5_6_5:
962 case V_028C70_COLOR_1_5_5_5:
963 case V_028C70_COLOR_4_4_4_4:
964 case V_028C70_COLOR_16:
965 case V_028C70_COLOR_8_8:
966 return V_028C70_ENDIAN_8IN16;
967
968 /* 32-bit buffers. */
969 case V_028C70_COLOR_8_8_8_8:
970 case V_028C70_COLOR_2_10_10_10:
971 case V_028C70_COLOR_8_24:
972 case V_028C70_COLOR_24_8:
973 case V_028C70_COLOR_16_16:
974 return V_028C70_ENDIAN_8IN32;
975
976 /* 64-bit buffers. */
977 case V_028C70_COLOR_16_16_16_16:
978 return V_028C70_ENDIAN_8IN16;
979
980 case V_028C70_COLOR_32_32:
981 return V_028C70_ENDIAN_8IN32;
982
983 /* 128-bit buffers. */
984 case V_028C70_COLOR_32_32_32_32:
985 return V_028C70_ENDIAN_8IN32;
986 default:
987 return V_028C70_ENDIAN_NONE; /* Unsupported. */
988 }
989 } else {
990 return V_028C70_ENDIAN_NONE;
991 }
992 }
993
994 /* Returns the size in bits of the widest component of a CB format */
995 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
996 {
997 switch(colorformat) {
998 case V_028C70_COLOR_4_4_4_4:
999 return 4;
1000
1001 case V_028C70_COLOR_1_5_5_5:
1002 case V_028C70_COLOR_5_5_5_1:
1003 return 5;
1004
1005 case V_028C70_COLOR_5_6_5:
1006 return 6;
1007
1008 case V_028C70_COLOR_8:
1009 case V_028C70_COLOR_8_8:
1010 case V_028C70_COLOR_8_8_8_8:
1011 return 8;
1012
1013 case V_028C70_COLOR_10_10_10_2:
1014 case V_028C70_COLOR_2_10_10_10:
1015 return 10;
1016
1017 case V_028C70_COLOR_10_11_11:
1018 case V_028C70_COLOR_11_11_10:
1019 return 11;
1020
1021 case V_028C70_COLOR_16:
1022 case V_028C70_COLOR_16_16:
1023 case V_028C70_COLOR_16_16_16_16:
1024 return 16;
1025
1026 case V_028C70_COLOR_8_24:
1027 case V_028C70_COLOR_24_8:
1028 return 24;
1029
1030 case V_028C70_COLOR_32:
1031 case V_028C70_COLOR_32_32:
1032 case V_028C70_COLOR_32_32_32_32:
1033 case V_028C70_COLOR_X24_8_32_FLOAT:
1034 return 32;
1035 }
1036
1037 assert(!"Unknown maximum component size");
1038 return 0;
1039 }
1040
1041 static uint32_t si_translate_dbformat(enum pipe_format format)
1042 {
1043 switch (format) {
1044 case PIPE_FORMAT_Z16_UNORM:
1045 return V_028040_Z_16;
1046 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1047 case PIPE_FORMAT_X8Z24_UNORM:
1048 case PIPE_FORMAT_Z24X8_UNORM:
1049 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1050 return V_028040_Z_24; /* deprecated on SI */
1051 case PIPE_FORMAT_Z32_FLOAT:
1052 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1053 return V_028040_Z_32_FLOAT;
1054 default:
1055 return V_028040_Z_INVALID;
1056 }
1057 }
1058
1059 /*
1060 * Texture translation
1061 */
1062
1063 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1064 enum pipe_format format,
1065 const struct util_format_description *desc,
1066 int first_non_void)
1067 {
1068 struct r600_screen *rscreen = (struct r600_screen*)screen;
1069 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1070 boolean uniform = TRUE;
1071 int i;
1072
1073 /* Colorspace (return non-RGB formats directly). */
1074 switch (desc->colorspace) {
1075 /* Depth stencil formats */
1076 case UTIL_FORMAT_COLORSPACE_ZS:
1077 switch (format) {
1078 case PIPE_FORMAT_Z16_UNORM:
1079 return V_008F14_IMG_DATA_FORMAT_16;
1080 case PIPE_FORMAT_X24S8_UINT:
1081 case PIPE_FORMAT_Z24X8_UNORM:
1082 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1083 return V_008F14_IMG_DATA_FORMAT_8_24;
1084 case PIPE_FORMAT_X8Z24_UNORM:
1085 case PIPE_FORMAT_S8X24_UINT:
1086 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1087 return V_008F14_IMG_DATA_FORMAT_24_8;
1088 case PIPE_FORMAT_S8_UINT:
1089 return V_008F14_IMG_DATA_FORMAT_8;
1090 case PIPE_FORMAT_Z32_FLOAT:
1091 return V_008F14_IMG_DATA_FORMAT_32;
1092 case PIPE_FORMAT_X32_S8X24_UINT:
1093 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1094 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1095 default:
1096 goto out_unknown;
1097 }
1098
1099 case UTIL_FORMAT_COLORSPACE_YUV:
1100 goto out_unknown; /* TODO */
1101
1102 case UTIL_FORMAT_COLORSPACE_SRGB:
1103 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1104 goto out_unknown;
1105 break;
1106
1107 default:
1108 break;
1109 }
1110
1111 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1112 if (!enable_s3tc)
1113 goto out_unknown;
1114
1115 switch (format) {
1116 case PIPE_FORMAT_RGTC1_SNORM:
1117 case PIPE_FORMAT_LATC1_SNORM:
1118 case PIPE_FORMAT_RGTC1_UNORM:
1119 case PIPE_FORMAT_LATC1_UNORM:
1120 return V_008F14_IMG_DATA_FORMAT_BC4;
1121 case PIPE_FORMAT_RGTC2_SNORM:
1122 case PIPE_FORMAT_LATC2_SNORM:
1123 case PIPE_FORMAT_RGTC2_UNORM:
1124 case PIPE_FORMAT_LATC2_UNORM:
1125 return V_008F14_IMG_DATA_FORMAT_BC5;
1126 default:
1127 goto out_unknown;
1128 }
1129 }
1130
1131 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1132
1133 if (!enable_s3tc)
1134 goto out_unknown;
1135
1136 if (!util_format_s3tc_enabled) {
1137 goto out_unknown;
1138 }
1139
1140 switch (format) {
1141 case PIPE_FORMAT_DXT1_RGB:
1142 case PIPE_FORMAT_DXT1_RGBA:
1143 case PIPE_FORMAT_DXT1_SRGB:
1144 case PIPE_FORMAT_DXT1_SRGBA:
1145 return V_008F14_IMG_DATA_FORMAT_BC1;
1146 case PIPE_FORMAT_DXT3_RGBA:
1147 case PIPE_FORMAT_DXT3_SRGBA:
1148 return V_008F14_IMG_DATA_FORMAT_BC2;
1149 case PIPE_FORMAT_DXT5_RGBA:
1150 case PIPE_FORMAT_DXT5_SRGBA:
1151 return V_008F14_IMG_DATA_FORMAT_BC3;
1152 default:
1153 goto out_unknown;
1154 }
1155 }
1156
1157 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1158 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1159 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1160 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1161 }
1162
1163 /* R8G8Bx_SNORM - TODO CxV8U8 */
1164
1165 /* See whether the components are of the same size. */
1166 for (i = 1; i < desc->nr_channels; i++) {
1167 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1168 }
1169
1170 /* Non-uniform formats. */
1171 if (!uniform) {
1172 switch(desc->nr_channels) {
1173 case 3:
1174 if (desc->channel[0].size == 5 &&
1175 desc->channel[1].size == 6 &&
1176 desc->channel[2].size == 5) {
1177 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1178 }
1179 goto out_unknown;
1180 case 4:
1181 if (desc->channel[0].size == 5 &&
1182 desc->channel[1].size == 5 &&
1183 desc->channel[2].size == 5 &&
1184 desc->channel[3].size == 1) {
1185 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1186 }
1187 if (desc->channel[0].size == 10 &&
1188 desc->channel[1].size == 10 &&
1189 desc->channel[2].size == 10 &&
1190 desc->channel[3].size == 2) {
1191 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1192 }
1193 goto out_unknown;
1194 }
1195 goto out_unknown;
1196 }
1197
1198 if (first_non_void < 0 || first_non_void > 3)
1199 goto out_unknown;
1200
1201 /* uniform formats */
1202 switch (desc->channel[first_non_void].size) {
1203 case 4:
1204 switch (desc->nr_channels) {
1205 #if 0 /* Not supported for render targets */
1206 case 2:
1207 return V_008F14_IMG_DATA_FORMAT_4_4;
1208 #endif
1209 case 4:
1210 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1211 }
1212 break;
1213 case 8:
1214 switch (desc->nr_channels) {
1215 case 1:
1216 return V_008F14_IMG_DATA_FORMAT_8;
1217 case 2:
1218 return V_008F14_IMG_DATA_FORMAT_8_8;
1219 case 4:
1220 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1221 }
1222 break;
1223 case 16:
1224 switch (desc->nr_channels) {
1225 case 1:
1226 return V_008F14_IMG_DATA_FORMAT_16;
1227 case 2:
1228 return V_008F14_IMG_DATA_FORMAT_16_16;
1229 case 4:
1230 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1231 }
1232 break;
1233 case 32:
1234 switch (desc->nr_channels) {
1235 case 1:
1236 return V_008F14_IMG_DATA_FORMAT_32;
1237 case 2:
1238 return V_008F14_IMG_DATA_FORMAT_32_32;
1239 #if 0 /* Not supported for render targets */
1240 case 3:
1241 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1242 #endif
1243 case 4:
1244 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1245 }
1246 }
1247
1248 out_unknown:
1249 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1250 return ~0;
1251 }
1252
1253 static unsigned si_tex_wrap(unsigned wrap)
1254 {
1255 switch (wrap) {
1256 default:
1257 case PIPE_TEX_WRAP_REPEAT:
1258 return V_008F30_SQ_TEX_WRAP;
1259 case PIPE_TEX_WRAP_CLAMP:
1260 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1261 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1262 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1263 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1264 return V_008F30_SQ_TEX_CLAMP_BORDER;
1265 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1266 return V_008F30_SQ_TEX_MIRROR;
1267 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1268 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1269 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1270 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1271 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1272 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1273 }
1274 }
1275
1276 static unsigned si_tex_filter(unsigned filter)
1277 {
1278 switch (filter) {
1279 default:
1280 case PIPE_TEX_FILTER_NEAREST:
1281 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1282 case PIPE_TEX_FILTER_LINEAR:
1283 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1284 }
1285 }
1286
1287 static unsigned si_tex_mipfilter(unsigned filter)
1288 {
1289 switch (filter) {
1290 case PIPE_TEX_MIPFILTER_NEAREST:
1291 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1292 case PIPE_TEX_MIPFILTER_LINEAR:
1293 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1294 default:
1295 case PIPE_TEX_MIPFILTER_NONE:
1296 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1297 }
1298 }
1299
1300 static unsigned si_tex_compare(unsigned compare)
1301 {
1302 switch (compare) {
1303 default:
1304 case PIPE_FUNC_NEVER:
1305 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1306 case PIPE_FUNC_LESS:
1307 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1308 case PIPE_FUNC_EQUAL:
1309 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1310 case PIPE_FUNC_LEQUAL:
1311 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1312 case PIPE_FUNC_GREATER:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1314 case PIPE_FUNC_NOTEQUAL:
1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1316 case PIPE_FUNC_GEQUAL:
1317 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1318 case PIPE_FUNC_ALWAYS:
1319 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1320 }
1321 }
1322
1323 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1324 {
1325 switch (dim) {
1326 default:
1327 case PIPE_TEXTURE_1D:
1328 return V_008F1C_SQ_RSRC_IMG_1D;
1329 case PIPE_TEXTURE_1D_ARRAY:
1330 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1331 case PIPE_TEXTURE_2D:
1332 case PIPE_TEXTURE_RECT:
1333 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1334 V_008F1C_SQ_RSRC_IMG_2D;
1335 case PIPE_TEXTURE_2D_ARRAY:
1336 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1337 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1338 case PIPE_TEXTURE_3D:
1339 return V_008F1C_SQ_RSRC_IMG_3D;
1340 case PIPE_TEXTURE_CUBE:
1341 return V_008F1C_SQ_RSRC_IMG_CUBE;
1342 }
1343 }
1344
1345 /*
1346 * Format support testing
1347 */
1348
1349 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1350 {
1351 return si_translate_texformat(screen, format, util_format_description(format),
1352 util_format_get_first_non_void_channel(format)) != ~0U;
1353 }
1354
1355 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1356 const struct util_format_description *desc,
1357 int first_non_void)
1358 {
1359 unsigned type = desc->channel[first_non_void].type;
1360 int i;
1361
1362 if (type == UTIL_FORMAT_TYPE_FIXED)
1363 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1364
1365 if (desc->nr_channels == 4 &&
1366 desc->channel[0].size == 10 &&
1367 desc->channel[1].size == 10 &&
1368 desc->channel[2].size == 10 &&
1369 desc->channel[3].size == 2)
1370 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1371
1372 /* See whether the components are of the same size. */
1373 for (i = 0; i < desc->nr_channels; i++) {
1374 if (desc->channel[first_non_void].size != desc->channel[i].size)
1375 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1376 }
1377
1378 switch (desc->channel[first_non_void].size) {
1379 case 8:
1380 switch (desc->nr_channels) {
1381 case 1:
1382 return V_008F0C_BUF_DATA_FORMAT_8;
1383 case 2:
1384 return V_008F0C_BUF_DATA_FORMAT_8_8;
1385 case 3:
1386 case 4:
1387 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1388 }
1389 break;
1390 case 16:
1391 switch (desc->nr_channels) {
1392 case 1:
1393 return V_008F0C_BUF_DATA_FORMAT_16;
1394 case 2:
1395 return V_008F0C_BUF_DATA_FORMAT_16_16;
1396 case 3:
1397 case 4:
1398 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1399 }
1400 break;
1401 case 32:
1402 /* From the Southern Islands ISA documentation about MTBUF:
1403 * 'Memory reads of data in memory that is 32 or 64 bits do not
1404 * undergo any format conversion.'
1405 */
1406 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1407 !desc->channel[first_non_void].pure_integer)
1408 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1409
1410 switch (desc->nr_channels) {
1411 case 1:
1412 return V_008F0C_BUF_DATA_FORMAT_32;
1413 case 2:
1414 return V_008F0C_BUF_DATA_FORMAT_32_32;
1415 case 3:
1416 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1417 case 4:
1418 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1419 }
1420 break;
1421 }
1422
1423 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1424 }
1425
1426 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1427 const struct util_format_description *desc,
1428 int first_non_void)
1429 {
1430 switch (desc->channel[first_non_void].type) {
1431 case UTIL_FORMAT_TYPE_SIGNED:
1432 if (desc->channel[first_non_void].normalized)
1433 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1434 else if (desc->channel[first_non_void].pure_integer)
1435 return V_008F0C_BUF_NUM_FORMAT_SINT;
1436 else
1437 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1438 break;
1439 case UTIL_FORMAT_TYPE_UNSIGNED:
1440 if (desc->channel[first_non_void].normalized)
1441 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1442 else if (desc->channel[first_non_void].pure_integer)
1443 return V_008F0C_BUF_NUM_FORMAT_UINT;
1444 else
1445 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1446 break;
1447 case UTIL_FORMAT_TYPE_FLOAT:
1448 default:
1449 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1450 }
1451 }
1452
1453 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1454 {
1455 const struct util_format_description *desc;
1456 int first_non_void;
1457 unsigned data_format;
1458
1459 desc = util_format_description(format);
1460 first_non_void = util_format_get_first_non_void_channel(format);
1461 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1462 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1463 }
1464
1465 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1466 {
1467 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1468 si_translate_colorswap(format) != ~0U;
1469 }
1470
1471 static bool si_is_zs_format_supported(enum pipe_format format)
1472 {
1473 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1474 }
1475
1476 boolean si_is_format_supported(struct pipe_screen *screen,
1477 enum pipe_format format,
1478 enum pipe_texture_target target,
1479 unsigned sample_count,
1480 unsigned usage)
1481 {
1482 struct r600_screen *rscreen = (struct r600_screen *)screen;
1483 unsigned retval = 0;
1484
1485 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1486 R600_ERR("r600: unsupported texture type %d\n", target);
1487 return FALSE;
1488 }
1489
1490 if (!util_format_is_supported(format, usage))
1491 return FALSE;
1492
1493 if (sample_count > 1) {
1494 if (HAVE_LLVM < 0x0304)
1495 return FALSE;
1496
1497 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1498 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1499 return FALSE;
1500
1501 switch (sample_count) {
1502 case 2:
1503 case 4:
1504 case 8:
1505 break;
1506 default:
1507 return FALSE;
1508 }
1509 }
1510
1511 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1512 if (target == PIPE_BUFFER) {
1513 if (si_is_vertex_format_supported(screen, format))
1514 retval |= PIPE_BIND_SAMPLER_VIEW;
1515 } else {
1516 if (si_is_sampler_format_supported(screen, format))
1517 retval |= PIPE_BIND_SAMPLER_VIEW;
1518 }
1519 }
1520
1521 if ((usage & (PIPE_BIND_RENDER_TARGET |
1522 PIPE_BIND_DISPLAY_TARGET |
1523 PIPE_BIND_SCANOUT |
1524 PIPE_BIND_SHARED)) &&
1525 si_is_colorbuffer_format_supported(format)) {
1526 retval |= usage &
1527 (PIPE_BIND_RENDER_TARGET |
1528 PIPE_BIND_DISPLAY_TARGET |
1529 PIPE_BIND_SCANOUT |
1530 PIPE_BIND_SHARED);
1531 }
1532
1533 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1534 si_is_zs_format_supported(format)) {
1535 retval |= PIPE_BIND_DEPTH_STENCIL;
1536 }
1537
1538 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1539 si_is_vertex_format_supported(screen, format)) {
1540 retval |= PIPE_BIND_VERTEX_BUFFER;
1541 }
1542
1543 if (usage & PIPE_BIND_TRANSFER_READ)
1544 retval |= PIPE_BIND_TRANSFER_READ;
1545 if (usage & PIPE_BIND_TRANSFER_WRITE)
1546 retval |= PIPE_BIND_TRANSFER_WRITE;
1547
1548 return retval == usage;
1549 }
1550
1551 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1552 {
1553 unsigned tile_mode_index = 0;
1554
1555 if (stencil) {
1556 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1557 } else {
1558 tile_mode_index = rtex->surface.tiling_index[level];
1559 }
1560 return tile_mode_index;
1561 }
1562
1563 /*
1564 * framebuffer handling
1565 */
1566
1567 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1568 const struct pipe_framebuffer_state *state, int cb)
1569 {
1570 struct r600_texture *rtex;
1571 struct r600_surface *surf;
1572 unsigned level = state->cbufs[cb]->u.tex.level;
1573 unsigned pitch, slice;
1574 unsigned color_info, color_attrib, color_pitch;
1575 unsigned tile_mode_index;
1576 unsigned format, swap, ntype, endian;
1577 uint64_t offset;
1578 const struct util_format_description *desc;
1579 int i;
1580 unsigned blend_clamp = 0, blend_bypass = 0;
1581 unsigned max_comp_size;
1582
1583 surf = (struct r600_surface *)state->cbufs[cb];
1584 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1585
1586 offset = rtex->surface.level[level].offset;
1587 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1588 offset += rtex->surface.level[level].slice_size *
1589 state->cbufs[cb]->u.tex.first_layer;
1590 }
1591 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1592 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1593 if (slice) {
1594 slice = slice - 1;
1595 }
1596
1597 tile_mode_index = si_tile_mode_index(rtex, level, false);
1598
1599 desc = util_format_description(surf->base.format);
1600 for (i = 0; i < 4; i++) {
1601 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1602 break;
1603 }
1604 }
1605 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1606 ntype = V_028C70_NUMBER_FLOAT;
1607 } else {
1608 ntype = V_028C70_NUMBER_UNORM;
1609 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1610 ntype = V_028C70_NUMBER_SRGB;
1611 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1612 if (desc->channel[i].pure_integer) {
1613 ntype = V_028C70_NUMBER_SINT;
1614 } else {
1615 assert(desc->channel[i].normalized);
1616 ntype = V_028C70_NUMBER_SNORM;
1617 }
1618 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1619 if (desc->channel[i].pure_integer) {
1620 ntype = V_028C70_NUMBER_UINT;
1621 } else {
1622 assert(desc->channel[i].normalized);
1623 ntype = V_028C70_NUMBER_UNORM;
1624 }
1625 }
1626 }
1627
1628 format = si_translate_colorformat(surf->base.format);
1629 if (format == V_028C70_COLOR_INVALID) {
1630 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1631 }
1632 assert(format != V_028C70_COLOR_INVALID);
1633 swap = si_translate_colorswap(surf->base.format);
1634 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1635 endian = V_028C70_ENDIAN_NONE;
1636 } else {
1637 endian = si_colorformat_endian_swap(format);
1638 }
1639
1640 /* blend clamp should be set for all NORM/SRGB types */
1641 if (ntype == V_028C70_NUMBER_UNORM ||
1642 ntype == V_028C70_NUMBER_SNORM ||
1643 ntype == V_028C70_NUMBER_SRGB)
1644 blend_clamp = 1;
1645
1646 /* set blend bypass according to docs if SINT/UINT or
1647 8/24 COLOR variants */
1648 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1649 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1650 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1651 blend_clamp = 0;
1652 blend_bypass = 1;
1653 }
1654
1655 color_info = S_028C70_FORMAT(format) |
1656 S_028C70_COMP_SWAP(swap) |
1657 S_028C70_BLEND_CLAMP(blend_clamp) |
1658 S_028C70_BLEND_BYPASS(blend_bypass) |
1659 S_028C70_NUMBER_TYPE(ntype) |
1660 S_028C70_ENDIAN(endian);
1661
1662 color_pitch = S_028C64_TILE_MAX(pitch);
1663
1664 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1665 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1666
1667 if (rtex->resource.b.b.nr_samples > 1) {
1668 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1669
1670 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1671 S_028C74_NUM_FRAGMENTS(log_samples);
1672
1673 if (rtex->fmask.size) {
1674 color_info |= S_028C70_COMPRESSION(1);
1675 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1676
1677 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1678
1679 if (rctx->b.chip_class == SI) {
1680 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1681 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1682 }
1683 if (rctx->b.chip_class >= CIK) {
1684 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1685 }
1686 }
1687 }
1688
1689 if (rtex->cmask.size) {
1690 color_info |= S_028C70_FAST_CLEAR(1);
1691 }
1692
1693 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1694 offset >>= 8;
1695
1696 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1697 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1698 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1699 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1700
1701 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1702 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1703 } else {
1704 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1705 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1706 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1707 }
1708 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1709 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1710
1711 if (rtex->cmask.size) {
1712 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1713 offset + (rtex->cmask.offset >> 8));
1714 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1715 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1716 }
1717 if (rtex->fmask.size) {
1718 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1719 offset + (rtex->fmask.offset >> 8));
1720 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1721 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1722 }
1723
1724 /* set CB_COLOR1_INFO for possible dual-src blending */
1725 if (state->nr_cbufs == 1) {
1726 assert(cb == 0);
1727 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1728 }
1729
1730 /* Determine pixel shader export format */
1731 max_comp_size = si_colorformat_max_comp_size(format);
1732 if (ntype == V_028C70_NUMBER_SRGB ||
1733 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1734 max_comp_size <= 10) ||
1735 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1736 rctx->export_16bpc |= 1 << cb;
1737 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1738 if (state->nr_cbufs == 1)
1739 rctx->export_16bpc |= 1 << 1;
1740 }
1741 }
1742
1743 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1744 const struct pipe_framebuffer_state *state)
1745 {
1746 struct r600_screen *rscreen = rctx->screen;
1747 struct r600_texture *rtex;
1748 struct r600_surface *surf;
1749 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1750 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1751 uint32_t z_info, s_info, db_depth_info;
1752 uint64_t z_offs, s_offs;
1753
1754 if (state->zsbuf == NULL) {
1755 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1756 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1757 return;
1758 }
1759
1760 surf = (struct r600_surface *)state->zsbuf;
1761 level = surf->base.u.tex.level;
1762 rtex = (struct r600_texture*)surf->base.texture;
1763
1764 format = si_translate_dbformat(rtex->resource.b.b.format);
1765
1766 if (format == V_028040_Z_INVALID) {
1767 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1768 }
1769 assert(format != V_028040_Z_INVALID);
1770
1771 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1772 z_offs += rtex->surface.level[level].offset;
1773 s_offs += rtex->surface.stencil_level[level].offset;
1774
1775 z_offs >>= 8;
1776 s_offs >>= 8;
1777
1778 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1779 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1780 if (slice) {
1781 slice = slice - 1;
1782 }
1783
1784 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1785
1786 z_info = S_028040_FORMAT(format);
1787 if (rtex->resource.b.b.nr_samples > 1) {
1788 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1789 }
1790
1791 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1792 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1793 else
1794 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1795
1796 if (rctx->b.chip_class >= CIK) {
1797 switch (rtex->surface.level[level].mode) {
1798 case RADEON_SURF_MODE_2D:
1799 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1800 break;
1801 case RADEON_SURF_MODE_1D:
1802 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1803 case RADEON_SURF_MODE_LINEAR:
1804 default:
1805 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1806 break;
1807 }
1808 tile_split = rtex->surface.tile_split;
1809 stile_split = rtex->surface.stencil_tile_split;
1810 macro_aspect = rtex->surface.mtilea;
1811 bankw = rtex->surface.bankw;
1812 bankh = rtex->surface.bankh;
1813 tile_split = cik_tile_split(tile_split);
1814 stile_split = cik_tile_split(stile_split);
1815 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1816 bankw = cik_bank_wh(bankw);
1817 bankh = cik_bank_wh(bankh);
1818 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1819 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1820 rscreen->b.info.r600_num_backends);
1821
1822 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1823 S_02803C_PIPE_CONFIG(pipe_config) |
1824 S_02803C_BANK_WIDTH(bankw) |
1825 S_02803C_BANK_HEIGHT(bankh) |
1826 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1827 S_02803C_NUM_BANKS(nbanks);
1828 z_info |= S_028040_TILE_SPLIT(tile_split);
1829 s_info |= S_028044_TILE_SPLIT(stile_split);
1830 } else {
1831 tile_mode_index = si_tile_mode_index(rtex, level, false);
1832 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1833 tile_mode_index = si_tile_mode_index(rtex, level, true);
1834 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1835 }
1836
1837 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1838 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1839 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1840
1841 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1842 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1843 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1844
1845 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1846 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1847 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1848 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1849 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1850
1851 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1852 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1853 }
1854
1855 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1856 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1857 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1858 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1859 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1860
1861 /* 2xMSAA
1862 * There are two locations (-4, 4), (4, -4). */
1863 static uint32_t sample_locs_2x[] = {
1864 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1865 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1866 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1867 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1868 };
1869 static unsigned max_dist_2x = 4;
1870 /* 4xMSAA
1871 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1872 static uint32_t sample_locs_4x[] = {
1873 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1874 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1875 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1876 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1877 };
1878 static unsigned max_dist_4x = 6;
1879 /* Cayman/SI 8xMSAA */
1880 static uint32_t cm_sample_locs_8x[] = {
1881 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1882 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1883 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1884 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1885 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1886 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1887 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1888 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1889 };
1890 static unsigned cm_max_dist_8x = 8;
1891 /* Cayman/SI 16xMSAA */
1892 static uint32_t cm_sample_locs_16x[] = {
1893 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1894 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1895 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1896 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1897 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1898 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1899 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1900 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1901 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1902 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1903 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1904 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1905 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1906 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1907 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1908 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1909 };
1910 static unsigned cm_max_dist_16x = 8;
1911
1912 static void si_get_sample_position(struct pipe_context *ctx,
1913 unsigned sample_count,
1914 unsigned sample_index,
1915 float *out_value)
1916 {
1917 int offset, index;
1918 struct {
1919 int idx:4;
1920 } val;
1921 switch (sample_count) {
1922 case 1:
1923 default:
1924 out_value[0] = out_value[1] = 0.5;
1925 break;
1926 case 2:
1927 offset = 4 * (sample_index * 2);
1928 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1929 out_value[0] = (float)(val.idx + 8) / 16.0f;
1930 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1931 out_value[1] = (float)(val.idx + 8) / 16.0f;
1932 break;
1933 case 4:
1934 offset = 4 * (sample_index * 2);
1935 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1936 out_value[0] = (float)(val.idx + 8) / 16.0f;
1937 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1938 out_value[1] = (float)(val.idx + 8) / 16.0f;
1939 break;
1940 case 8:
1941 offset = 4 * (sample_index % 4 * 2);
1942 index = (sample_index / 4) * 4;
1943 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1944 out_value[0] = (float)(val.idx + 8) / 16.0f;
1945 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1946 out_value[1] = (float)(val.idx + 8) / 16.0f;
1947 break;
1948 case 16:
1949 offset = 4 * (sample_index % 4 * 2);
1950 index = (sample_index / 4) * 4;
1951 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1952 out_value[0] = (float)(val.idx + 8) / 16.0f;
1953 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1954 out_value[1] = (float)(val.idx + 8) / 16.0f;
1955 break;
1956 }
1957 }
1958
1959 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1960 {
1961 unsigned max_dist = 0;
1962
1963 switch (nr_samples) {
1964 default:
1965 nr_samples = 0;
1966 break;
1967 case 2:
1968 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1969 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1970 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1971 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1972 max_dist = max_dist_2x;
1973 break;
1974 case 4:
1975 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1976 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1977 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1978 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1979 max_dist = max_dist_4x;
1980 break;
1981 case 8:
1982 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1983 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1984 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1985 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1986 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1987 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1988 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1989 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1990 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1991 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1992 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1993 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
1994 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
1995 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
1996 max_dist = cm_max_dist_8x;
1997 break;
1998 case 16:
1999 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2000 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2001 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2002 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2003 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2004 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2005 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2006 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2007 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2008 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2009 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2010 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2011 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2012 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2013 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2014 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2015 max_dist = cm_max_dist_16x;
2016 break;
2017 }
2018
2019 if (nr_samples > 1) {
2020 unsigned log_samples = util_logbase2(nr_samples);
2021
2022 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2023 S_028BDC_LAST_PIXEL(1) |
2024 S_028BDC_EXPAND_LINE_WIDTH(1));
2025 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2026 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2027 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2028 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2029
2030 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2031 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2032 S_028804_PS_ITER_SAMPLES(log_samples) |
2033 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2034 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2035 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2036 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2037 } else {
2038 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2039 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2040
2041 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2042 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2043 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2044 }
2045 }
2046
2047 static void si_set_framebuffer_state(struct pipe_context *ctx,
2048 const struct pipe_framebuffer_state *state)
2049 {
2050 struct r600_context *rctx = (struct r600_context *)ctx;
2051 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2052 uint32_t tl, br;
2053 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2054
2055 if (pm4 == NULL)
2056 return;
2057
2058 if (rctx->framebuffer.nr_cbufs) {
2059 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2060 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2061 }
2062 if (rctx->framebuffer.zsbuf) {
2063 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2064 }
2065
2066 util_copy_framebuffer_state(&rctx->framebuffer, state);
2067
2068 /* build states */
2069 rctx->export_16bpc = 0;
2070 rctx->fb_compressed_cb_mask = 0;
2071 for (i = 0; i < state->nr_cbufs; i++) {
2072 struct r600_texture *rtex =
2073 (struct r600_texture*)state->cbufs[i]->texture;
2074
2075 si_cb(rctx, pm4, state, i);
2076
2077 if (rtex->fmask.size || rtex->cmask.size) {
2078 rctx->fb_compressed_cb_mask |= 1 << i;
2079 }
2080 }
2081 for (; i < 8; i++) {
2082 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2083 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2084 }
2085
2086 assert(!(rctx->export_16bpc & ~0xff));
2087 si_db(rctx, pm4, state);
2088
2089 tl_x = 0;
2090 tl_y = 0;
2091 br_x = state->width;
2092 br_y = state->height;
2093
2094 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2095 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2096
2097 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2098 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2099 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2100 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2101 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2102 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2103 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2104 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2105 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2106 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2107
2108 if (state->nr_cbufs)
2109 nr_samples = state->cbufs[0]->texture->nr_samples;
2110 else if (state->zsbuf)
2111 nr_samples = state->zsbuf->texture->nr_samples;
2112 else
2113 nr_samples = 0;
2114
2115 si_set_msaa_state(rctx, pm4, nr_samples);
2116 rctx->fb_log_samples = util_logbase2(nr_samples);
2117 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2118 util_format_is_pure_integer(state->cbufs[0]->format);
2119
2120 si_pm4_set_state(rctx, framebuffer, pm4);
2121 si_update_fb_rs_state(rctx);
2122 si_update_fb_blend_state(rctx);
2123 }
2124
2125 /*
2126 * shaders
2127 */
2128
2129 /* Compute the key for the hw shader variant */
2130 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2131 struct si_pipe_shader_selector *sel,
2132 union si_shader_key *key)
2133 {
2134 struct r600_context *rctx = (struct r600_context *)ctx;
2135 memset(key, 0, sizeof(*key));
2136
2137 if (sel->type == PIPE_SHADER_VERTEX) {
2138 unsigned i;
2139 if (!rctx->vertex_elements)
2140 return;
2141
2142 for (i = 0; i < rctx->vertex_elements->count; ++i)
2143 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2144
2145 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2146 key->vs.ucps_enabled |= 0x2;
2147 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2148 key->vs.ucps_enabled |= 0x1;
2149 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2150 if (sel->fs_write_all)
2151 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2152 key->ps.export_16bpc = rctx->export_16bpc;
2153
2154 if (rctx->queued.named.rasterizer) {
2155 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2156 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2157
2158 if (rctx->queued.named.blend) {
2159 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2160 rctx->queued.named.rasterizer->multisample_enable &&
2161 !rctx->fb_cb0_is_integer;
2162 }
2163 }
2164 if (rctx->queued.named.dsa) {
2165 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2166
2167 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2168 if (rctx->framebuffer.nr_cbufs &&
2169 rctx->framebuffer.cbufs[0] &&
2170 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2171 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2172 } else {
2173 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2174 }
2175 }
2176 }
2177
2178 /* Select the hw shader variant depending on the current state.
2179 * (*dirty) is set to 1 if current variant was changed */
2180 int si_shader_select(struct pipe_context *ctx,
2181 struct si_pipe_shader_selector *sel,
2182 unsigned *dirty)
2183 {
2184 union si_shader_key key;
2185 struct si_pipe_shader * shader = NULL;
2186 int r;
2187
2188 si_shader_selector_key(ctx, sel, &key);
2189
2190 /* Check if we don't need to change anything.
2191 * This path is also used for most shaders that don't need multiple
2192 * variants, it will cost just a computation of the key and this
2193 * test. */
2194 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2195 return 0;
2196 }
2197
2198 /* lookup if we have other variants in the list */
2199 if (sel->num_shaders > 1) {
2200 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2201
2202 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2203 p = c;
2204 c = c->next_variant;
2205 }
2206
2207 if (c) {
2208 p->next_variant = c->next_variant;
2209 shader = c;
2210 }
2211 }
2212
2213 if (unlikely(!shader)) {
2214 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2215 shader->selector = sel;
2216 shader->key = key;
2217
2218 r = si_pipe_shader_create(ctx, shader);
2219 if (unlikely(r)) {
2220 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2221 sel->type, r);
2222 sel->current = NULL;
2223 FREE(shader);
2224 return r;
2225 }
2226
2227 /* We don't know the value of fs_write_all property until we built
2228 * at least one variant, so we may need to recompute the key (include
2229 * rctx->framebuffer.nr_cbufs) after building first variant. */
2230 if (sel->type == PIPE_SHADER_FRAGMENT &&
2231 sel->num_shaders == 0 &&
2232 shader->shader.fs_write_all) {
2233 sel->fs_write_all = 1;
2234 si_shader_selector_key(ctx, sel, &shader->key);
2235 }
2236
2237 sel->num_shaders++;
2238 }
2239
2240 if (dirty)
2241 *dirty = 1;
2242
2243 shader->next_variant = sel->current;
2244 sel->current = shader;
2245
2246 return 0;
2247 }
2248
2249 static void *si_create_shader_state(struct pipe_context *ctx,
2250 const struct pipe_shader_state *state,
2251 unsigned pipe_shader_type)
2252 {
2253 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2254 int r;
2255
2256 sel->type = pipe_shader_type;
2257 sel->tokens = tgsi_dup_tokens(state->tokens);
2258 sel->so = state->stream_output;
2259
2260 r = si_shader_select(ctx, sel, NULL);
2261 if (r) {
2262 free(sel);
2263 return NULL;
2264 }
2265
2266 return sel;
2267 }
2268
2269 static void *si_create_fs_state(struct pipe_context *ctx,
2270 const struct pipe_shader_state *state)
2271 {
2272 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2273 }
2274
2275 static void *si_create_vs_state(struct pipe_context *ctx,
2276 const struct pipe_shader_state *state)
2277 {
2278 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2279 }
2280
2281 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2282 {
2283 struct r600_context *rctx = (struct r600_context *)ctx;
2284 struct si_pipe_shader_selector *sel = state;
2285
2286 if (rctx->vs_shader == sel)
2287 return;
2288
2289 rctx->vs_shader = sel;
2290
2291 if (sel && sel->current) {
2292 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2293 rctx->b.streamout.stride_in_dw = sel->so.stride;
2294 } else {
2295 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2296 }
2297
2298 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2299 }
2300
2301 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2302 {
2303 struct r600_context *rctx = (struct r600_context *)ctx;
2304 struct si_pipe_shader_selector *sel = state;
2305
2306 if (rctx->ps_shader == sel)
2307 return;
2308
2309 rctx->ps_shader = sel;
2310
2311 if (sel && sel->current)
2312 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2313 else
2314 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2315
2316 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2317 }
2318
2319 static void si_delete_shader_selector(struct pipe_context *ctx,
2320 struct si_pipe_shader_selector *sel)
2321 {
2322 struct r600_context *rctx = (struct r600_context *)ctx;
2323 struct si_pipe_shader *p = sel->current, *c;
2324
2325 while (p) {
2326 c = p->next_variant;
2327 si_pm4_delete_state(rctx, vs, p->pm4);
2328 si_pipe_shader_destroy(ctx, p);
2329 free(p);
2330 p = c;
2331 }
2332
2333 free(sel->tokens);
2334 free(sel);
2335 }
2336
2337 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2338 {
2339 struct r600_context *rctx = (struct r600_context *)ctx;
2340 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2341
2342 if (rctx->vs_shader == sel) {
2343 rctx->vs_shader = NULL;
2344 }
2345
2346 si_delete_shader_selector(ctx, sel);
2347 }
2348
2349 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2350 {
2351 struct r600_context *rctx = (struct r600_context *)ctx;
2352 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2353
2354 if (rctx->ps_shader == sel) {
2355 rctx->ps_shader = NULL;
2356 }
2357
2358 si_delete_shader_selector(ctx, sel);
2359 }
2360
2361 /*
2362 * Samplers
2363 */
2364
2365 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2366 struct pipe_resource *texture,
2367 const struct pipe_sampler_view *state)
2368 {
2369 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2370 struct r600_texture *tmp = (struct r600_texture*)texture;
2371 const struct util_format_description *desc;
2372 unsigned format, num_format;
2373 uint32_t pitch = 0;
2374 unsigned char state_swizzle[4], swizzle[4];
2375 unsigned height, depth, width;
2376 enum pipe_format pipe_format = state->format;
2377 struct radeon_surface_level *surflevel;
2378 int first_non_void;
2379 uint64_t va;
2380
2381 if (view == NULL)
2382 return NULL;
2383
2384 /* initialize base object */
2385 view->base = *state;
2386 view->base.texture = NULL;
2387 pipe_resource_reference(&view->base.texture, texture);
2388 view->base.reference.count = 1;
2389 view->base.context = ctx;
2390 view->resource = &tmp->resource;
2391
2392 /* Buffer resource. */
2393 if (texture->target == PIPE_BUFFER) {
2394 unsigned stride;
2395
2396 desc = util_format_description(state->format);
2397 first_non_void = util_format_get_first_non_void_channel(state->format);
2398 stride = desc->block.bits / 8;
2399 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2400 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2401 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2402
2403 view->state[0] = va;
2404 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2405 S_008F04_STRIDE(stride);
2406 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2407 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2408 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2409 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2410 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2411 S_008F0C_NUM_FORMAT(num_format) |
2412 S_008F0C_DATA_FORMAT(format);
2413 return &view->base;
2414 }
2415
2416 state_swizzle[0] = state->swizzle_r;
2417 state_swizzle[1] = state->swizzle_g;
2418 state_swizzle[2] = state->swizzle_b;
2419 state_swizzle[3] = state->swizzle_a;
2420
2421 surflevel = tmp->surface.level;
2422
2423 /* Texturing with separate depth and stencil. */
2424 if (tmp->is_depth && !tmp->is_flushing_texture) {
2425 switch (pipe_format) {
2426 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2427 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2428 break;
2429 case PIPE_FORMAT_X8Z24_UNORM:
2430 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2431 /* Z24 is always stored like this. */
2432 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2433 break;
2434 case PIPE_FORMAT_X24S8_UINT:
2435 case PIPE_FORMAT_S8X24_UINT:
2436 case PIPE_FORMAT_X32_S8X24_UINT:
2437 pipe_format = PIPE_FORMAT_S8_UINT;
2438 surflevel = tmp->surface.stencil_level;
2439 break;
2440 default:;
2441 }
2442 }
2443
2444 desc = util_format_description(pipe_format);
2445
2446 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2447 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2448 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2449
2450 switch (pipe_format) {
2451 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2452 case PIPE_FORMAT_X24S8_UINT:
2453 case PIPE_FORMAT_X32_S8X24_UINT:
2454 case PIPE_FORMAT_X8Z24_UNORM:
2455 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2456 break;
2457 default:
2458 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2459 }
2460 } else {
2461 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2462 }
2463
2464 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2465
2466 switch (pipe_format) {
2467 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2468 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2469 break;
2470 default:
2471 if (first_non_void < 0) {
2472 if (util_format_is_compressed(pipe_format)) {
2473 switch (pipe_format) {
2474 case PIPE_FORMAT_DXT1_SRGB:
2475 case PIPE_FORMAT_DXT1_SRGBA:
2476 case PIPE_FORMAT_DXT3_SRGBA:
2477 case PIPE_FORMAT_DXT5_SRGBA:
2478 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2479 break;
2480 case PIPE_FORMAT_RGTC1_SNORM:
2481 case PIPE_FORMAT_LATC1_SNORM:
2482 case PIPE_FORMAT_RGTC2_SNORM:
2483 case PIPE_FORMAT_LATC2_SNORM:
2484 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2485 break;
2486 default:
2487 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2488 break;
2489 }
2490 } else {
2491 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2492 }
2493 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2494 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2495 } else {
2496 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2497
2498 switch (desc->channel[first_non_void].type) {
2499 case UTIL_FORMAT_TYPE_FLOAT:
2500 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2501 break;
2502 case UTIL_FORMAT_TYPE_SIGNED:
2503 if (desc->channel[first_non_void].normalized)
2504 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2505 else if (desc->channel[first_non_void].pure_integer)
2506 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2507 else
2508 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2509 break;
2510 case UTIL_FORMAT_TYPE_UNSIGNED:
2511 if (desc->channel[first_non_void].normalized)
2512 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2513 else if (desc->channel[first_non_void].pure_integer)
2514 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2515 else
2516 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2517 }
2518 }
2519 }
2520
2521 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2522 if (format == ~0) {
2523 format = 0;
2524 }
2525
2526 /* not supported any more */
2527 //endian = si_colorformat_endian_swap(format);
2528
2529 width = surflevel[0].npix_x;
2530 height = surflevel[0].npix_y;
2531 depth = surflevel[0].npix_z;
2532 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2533
2534 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2535 height = 1;
2536 depth = texture->array_size;
2537 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2538 depth = texture->array_size;
2539 }
2540
2541 va = r600_resource_va(ctx->screen, texture);
2542 va += surflevel[0].offset;
2543 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2544 view->state[0] = va >> 8;
2545 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2546 S_008F14_DATA_FORMAT(format) |
2547 S_008F14_NUM_FORMAT(num_format));
2548 view->state[2] = (S_008F18_WIDTH(width - 1) |
2549 S_008F18_HEIGHT(height - 1));
2550 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2551 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2552 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2553 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2554 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2555 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2556 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2557 util_logbase2(texture->nr_samples) :
2558 state->u.tex.last_level - tmp->mipmap_shift) |
2559 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2560 S_008F1C_POW2_PAD(texture->last_level > 0) |
2561 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2562 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2563 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2564 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2565 view->state[6] = 0;
2566 view->state[7] = 0;
2567
2568 /* Initialize the sampler view for FMASK. */
2569 if (tmp->fmask.size) {
2570 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2571 uint32_t fmask_format;
2572
2573 switch (texture->nr_samples) {
2574 case 2:
2575 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2576 break;
2577 case 4:
2578 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2579 break;
2580 case 8:
2581 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2582 break;
2583 default:
2584 assert(0);
2585 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2586 }
2587
2588 view->fmask_state[0] = va >> 8;
2589 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2590 S_008F14_DATA_FORMAT(fmask_format) |
2591 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2592 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2593 S_008F18_HEIGHT(height - 1);
2594 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2595 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2596 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2597 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2598 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2599 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2600 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2601 S_008F20_PITCH(tmp->fmask.pitch - 1);
2602 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2603 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2604 view->fmask_state[6] = 0;
2605 view->fmask_state[7] = 0;
2606 }
2607
2608 return &view->base;
2609 }
2610
2611 static void si_sampler_view_destroy(struct pipe_context *ctx,
2612 struct pipe_sampler_view *state)
2613 {
2614 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2615
2616 pipe_resource_reference(&state->texture, NULL);
2617 FREE(resource);
2618 }
2619
2620 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2621 {
2622 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2623 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2624 (linear_filter &&
2625 (wrap == PIPE_TEX_WRAP_CLAMP ||
2626 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2627 }
2628
2629 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2630 {
2631 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2632 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2633
2634 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2635 state->border_color.ui[2] || state->border_color.ui[3]) &&
2636 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2637 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2638 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2639 }
2640
2641 static void *si_create_sampler_state(struct pipe_context *ctx,
2642 const struct pipe_sampler_state *state)
2643 {
2644 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2645 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2646 unsigned border_color_type;
2647
2648 if (rstate == NULL) {
2649 return NULL;
2650 }
2651
2652 if (sampler_state_needs_border_color(state))
2653 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2654 else
2655 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2656
2657 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2658 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2659 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2660 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2661 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2662 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2663 aniso_flag_offset << 16 | /* XXX */
2664 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2665 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2666 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2667 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2668 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2669 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2670 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2671 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2672
2673 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2674 memcpy(rstate->border_color, state->border_color.ui,
2675 sizeof(rstate->border_color));
2676 }
2677
2678 return rstate;
2679 }
2680
2681 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2682 * the si_set_sampler_view calls. LTO might help too. */
2683 static void si_set_sampler_views(struct pipe_context *ctx,
2684 unsigned shader, unsigned start,
2685 unsigned count,
2686 struct pipe_sampler_view **views)
2687 {
2688 struct r600_context *rctx = (struct r600_context *)ctx;
2689 struct r600_textures_info *samplers = &rctx->samplers[shader];
2690 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2691 int i;
2692
2693 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2694 return;
2695
2696 assert(start == 0);
2697
2698 for (i = 0; i < count; i++) {
2699 if (!views[i]) {
2700 samplers->depth_texture_mask &= ~(1 << i);
2701 samplers->compressed_colortex_mask &= ~(1 << i);
2702 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2703 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2704 NULL, NULL);
2705 continue;
2706 }
2707
2708 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2709
2710 if (views[i]->texture->target != PIPE_BUFFER) {
2711 struct r600_texture *rtex =
2712 (struct r600_texture*)views[i]->texture;
2713
2714 if (rtex->is_depth && !rtex->is_flushing_texture) {
2715 samplers->depth_texture_mask |= 1 << i;
2716 } else {
2717 samplers->depth_texture_mask &= ~(1 << i);
2718 }
2719 if (rtex->cmask.size || rtex->fmask.size) {
2720 samplers->compressed_colortex_mask |= 1 << i;
2721 } else {
2722 samplers->compressed_colortex_mask &= ~(1 << i);
2723 }
2724
2725 if (rtex->fmask.size) {
2726 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2727 views[i], rviews[i]->fmask_state);
2728 } else {
2729 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2730 NULL, NULL);
2731 }
2732 }
2733 }
2734 for (; i < samplers->n_views; i++) {
2735 samplers->depth_texture_mask &= ~(1 << i);
2736 samplers->compressed_colortex_mask &= ~(1 << i);
2737 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2738 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2739 NULL, NULL);
2740 }
2741
2742 samplers->n_views = count;
2743 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2744 }
2745
2746 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2747 void **states,
2748 struct r600_textures_info *samplers,
2749 unsigned user_data_reg)
2750 {
2751 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2752 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2753 uint32_t *border_color_table = NULL;
2754 int i, j;
2755
2756 if (!count)
2757 goto out;
2758
2759 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2760
2761 si_pm4_sh_data_begin(pm4);
2762 for (i = 0; i < count; i++) {
2763 if (rstates[i] &&
2764 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2765 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2766 if (!rctx->border_color_table ||
2767 ((rctx->border_color_offset + count - i) &
2768 C_008F3C_BORDER_COLOR_PTR)) {
2769 r600_resource_reference(&rctx->border_color_table, NULL);
2770 rctx->border_color_offset = 0;
2771
2772 rctx->border_color_table =
2773 r600_resource_create_custom(&rctx->screen->b.b,
2774 PIPE_USAGE_STAGING,
2775 4096 * 4 * 4);
2776 }
2777
2778 if (!border_color_table) {
2779 border_color_table =
2780 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2781 rctx->b.rings.gfx.cs,
2782 PIPE_TRANSFER_WRITE |
2783 PIPE_TRANSFER_UNSYNCHRONIZED);
2784 }
2785
2786 for (j = 0; j < 4; j++) {
2787 border_color_table[4 * rctx->border_color_offset + j] =
2788 util_le32_to_cpu(rstates[i]->border_color[j]);
2789 }
2790
2791 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2792 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2793 }
2794
2795 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2796 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2797 }
2798 }
2799 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2800
2801 if (border_color_table) {
2802 uint64_t va_offset =
2803 r600_resource_va(&rctx->screen->b.b,
2804 (void*)rctx->border_color_table);
2805
2806 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2807 if (rctx->b.chip_class >= CIK)
2808 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2809 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2810 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2811 }
2812
2813 memcpy(samplers->samplers, states, sizeof(void*) * count);
2814
2815 out:
2816 samplers->n_samplers = count;
2817 return pm4;
2818 }
2819
2820 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2821 {
2822 struct r600_context *rctx = (struct r600_context *)ctx;
2823 struct si_pm4_state *pm4;
2824
2825 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2826 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2827 si_pm4_set_state(rctx, vs_sampler, pm4);
2828 }
2829
2830 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2831 {
2832 struct r600_context *rctx = (struct r600_context *)ctx;
2833 struct si_pm4_state *pm4;
2834
2835 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2836 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2837 si_pm4_set_state(rctx, ps_sampler, pm4);
2838 }
2839
2840
2841 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2842 unsigned start, unsigned count,
2843 void **states)
2844 {
2845 assert(start == 0);
2846
2847 switch (shader) {
2848 case PIPE_SHADER_VERTEX:
2849 si_bind_vs_sampler_states(ctx, count, states);
2850 break;
2851 case PIPE_SHADER_FRAGMENT:
2852 si_bind_ps_sampler_states(ctx, count, states);
2853 break;
2854 default:
2855 ;
2856 }
2857 }
2858
2859
2860
2861 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2862 {
2863 struct r600_context *rctx = (struct r600_context *)ctx;
2864 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2865 uint16_t mask = sample_mask;
2866
2867 if (pm4 == NULL)
2868 return;
2869
2870 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2871 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2872
2873 si_pm4_set_state(rctx, sample_mask, pm4);
2874 }
2875
2876 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2877 {
2878 free(state);
2879 }
2880
2881 /*
2882 * Vertex elements & buffers
2883 */
2884
2885 static void *si_create_vertex_elements(struct pipe_context *ctx,
2886 unsigned count,
2887 const struct pipe_vertex_element *elements)
2888 {
2889 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2890 int i;
2891
2892 assert(count < PIPE_MAX_ATTRIBS);
2893 if (!v)
2894 return NULL;
2895
2896 v->count = count;
2897 for (i = 0; i < count; ++i) {
2898 const struct util_format_description *desc;
2899 unsigned data_format, num_format;
2900 int first_non_void;
2901
2902 desc = util_format_description(elements[i].src_format);
2903 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2904 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2905 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2906
2907 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2908 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2909 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2910 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2911 S_008F0C_NUM_FORMAT(num_format) |
2912 S_008F0C_DATA_FORMAT(data_format);
2913 }
2914 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2915
2916 return v;
2917 }
2918
2919 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2920 {
2921 struct r600_context *rctx = (struct r600_context *)ctx;
2922 struct si_vertex_element *v = (struct si_vertex_element*)state;
2923
2924 rctx->vertex_elements = v;
2925 }
2926
2927 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2928 {
2929 struct r600_context *rctx = (struct r600_context *)ctx;
2930
2931 if (rctx->vertex_elements == state)
2932 rctx->vertex_elements = NULL;
2933 FREE(state);
2934 }
2935
2936 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2937 const struct pipe_vertex_buffer *buffers)
2938 {
2939 struct r600_context *rctx = (struct r600_context *)ctx;
2940
2941 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2942 }
2943
2944 static void si_set_index_buffer(struct pipe_context *ctx,
2945 const struct pipe_index_buffer *ib)
2946 {
2947 struct r600_context *rctx = (struct r600_context *)ctx;
2948
2949 if (ib) {
2950 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2951 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2952 } else {
2953 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2954 }
2955 }
2956
2957 /*
2958 * Misc
2959 */
2960 static void si_set_polygon_stipple(struct pipe_context *ctx,
2961 const struct pipe_poly_stipple *state)
2962 {
2963 }
2964
2965 static void si_texture_barrier(struct pipe_context *ctx)
2966 {
2967 struct r600_context *rctx = (struct r600_context *)ctx;
2968
2969 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2970 R600_CONTEXT_FLUSH_AND_INV_CB;
2971 }
2972
2973 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2974 {
2975 struct pipe_blend_state blend;
2976
2977 memset(&blend, 0, sizeof(blend));
2978 blend.independent_blend_enable = true;
2979 blend.rt[0].colormask = 0xf;
2980 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2981 }
2982
2983 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2984 struct pipe_resource *texture,
2985 const struct pipe_surface *surf_tmpl)
2986 {
2987 struct r600_texture *rtex = (struct r600_texture*)texture;
2988 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2989 unsigned level = surf_tmpl->u.tex.level;
2990
2991 if (surface == NULL)
2992 return NULL;
2993
2994 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2995 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2996 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
2997
2998 pipe_reference_init(&surface->base.reference, 1);
2999 pipe_resource_reference(&surface->base.texture, texture);
3000 surface->base.context = pipe;
3001 surface->base.format = surf_tmpl->format;
3002 surface->base.width = rtex->surface.level[level].npix_x;
3003 surface->base.height = rtex->surface.level[level].npix_y;
3004 surface->base.texture = texture;
3005 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3006 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3007 surface->base.u.tex.level = level;
3008
3009 return &surface->base;
3010 }
3011
3012 static void r600_surface_destroy(struct pipe_context *pipe,
3013 struct pipe_surface *surface)
3014 {
3015 pipe_resource_reference(&surface->texture, NULL);
3016 FREE(surface);
3017 }
3018
3019 static boolean si_dma_copy(struct pipe_context *ctx,
3020 struct pipe_resource *dst,
3021 unsigned dst_level,
3022 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3023 struct pipe_resource *src,
3024 unsigned src_level,
3025 const struct pipe_box *src_box)
3026 {
3027 /* XXX implement this or share evergreen_dma_blit with r600g */
3028 return FALSE;
3029 }
3030
3031 void si_init_state_functions(struct r600_context *rctx)
3032 {
3033 int i;
3034
3035 rctx->b.b.create_blend_state = si_create_blend_state;
3036 rctx->b.b.bind_blend_state = si_bind_blend_state;
3037 rctx->b.b.delete_blend_state = si_delete_blend_state;
3038 rctx->b.b.set_blend_color = si_set_blend_color;
3039
3040 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3041 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3042 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3043
3044 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3045 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3046 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3047
3048 for (i = 0; i < 8; i++) {
3049 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3050 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3051 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3052 }
3053 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3054 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3055 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3056
3057 rctx->b.b.set_clip_state = si_set_clip_state;
3058 rctx->b.b.set_scissor_states = si_set_scissor_states;
3059 rctx->b.b.set_viewport_states = si_set_viewport_states;
3060 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3061
3062 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3063 rctx->b.b.get_sample_position = si_get_sample_position;
3064
3065 rctx->b.b.create_vs_state = si_create_vs_state;
3066 rctx->b.b.create_fs_state = si_create_fs_state;
3067 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3068 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3069 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3070 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3071
3072 rctx->b.b.create_sampler_state = si_create_sampler_state;
3073 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3074 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3075
3076 rctx->b.b.create_sampler_view = si_create_sampler_view;
3077 rctx->b.b.set_sampler_views = si_set_sampler_views;
3078 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3079
3080 rctx->b.b.set_sample_mask = si_set_sample_mask;
3081
3082 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3083 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3084 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3085 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3086 rctx->b.b.set_index_buffer = si_set_index_buffer;
3087
3088 rctx->b.b.texture_barrier = si_texture_barrier;
3089 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3090 rctx->b.b.create_surface = r600_create_surface;
3091 rctx->b.b.surface_destroy = r600_surface_destroy;
3092 rctx->b.dma_copy = si_dma_copy;
3093
3094 rctx->b.b.draw_vbo = si_draw_vbo;
3095 }
3096
3097 void si_init_config(struct r600_context *rctx)
3098 {
3099 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3100
3101 if (pm4 == NULL)
3102 return;
3103
3104 si_cmd_context_control(pm4);
3105
3106 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3107
3108 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3109 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3110 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3111 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3112 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3113 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3114 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3115 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3116 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3117 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3118 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3119 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3120 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3121 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3122 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3123 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3124 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3125 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3126 if (rctx->b.chip_class == SI) {
3127 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3128 S_028AA8_SWITCH_ON_EOP(1) |
3129 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3130 S_028AA8_PRIMGROUP_SIZE(63));
3131 }
3132 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3133 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3134 if (rctx->b.chip_class < CIK)
3135 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3136 S_008A14_CLIP_VTX_REORDER_ENA(1));
3137
3138 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3139 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3140 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3141
3142 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3143
3144 if (rctx->b.chip_class >= CIK) {
3145 switch (rctx->screen->b.family) {
3146 case CHIP_BONAIRE:
3147 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3148 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3149 break;
3150 case CHIP_HAWAII:
3151 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3152 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3153 break;
3154 case CHIP_KAVERI:
3155 /* XXX todo */
3156 case CHIP_KABINI:
3157 /* XXX todo */
3158 default:
3159 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3160 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3161 break;
3162 }
3163 } else {
3164 switch (rctx->screen->b.family) {
3165 case CHIP_TAHITI:
3166 case CHIP_PITCAIRN:
3167 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3168 break;
3169 case CHIP_VERDE:
3170 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3171 break;
3172 case CHIP_OLAND:
3173 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3174 break;
3175 case CHIP_HAINAN:
3176 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3177 break;
3178 default:
3179 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3180 break;
3181 }
3182 }
3183
3184 si_pm4_set_state(rctx, init, pm4);
3185 }