projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: check if value is negative
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.info.r600_num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.num_render_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case PIPE_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case PIPE_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case PIPE_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case PIPE_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case PIPE_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* PIPE_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
243 * is that:
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
248 *
249 * Another reason is to avoid a hang with dual source blending.
250 */
251 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
252 {
253 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
254 struct si_state_blend *blend = sctx->queued.named.blend;
255 uint32_t cb_target_mask = 0, i;
256
257 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
258 if (sctx->framebuffer.state.cbufs[i])
259 cb_target_mask |= 0xf << (4*i);
260
261 if (blend)
262 cb_target_mask &= blend->cb_target_mask;
263
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
267 *
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
269 */
270 if (blend && blend->dual_src_blend &&
271 sctx->ps_shader.cso &&
272 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
273 cb_target_mask = 0;
274
275 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
276
277 /* STONEY-specific register settings. */
278 if (sctx->b.family == CHIP_STONEY) {
279 unsigned spi_shader_col_format =
280 sctx->ps_shader.cso ?
281 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
282 unsigned sx_ps_downconvert = 0;
283 unsigned sx_blend_opt_epsilon = 0;
284 unsigned sx_blend_opt_control = 0;
285
286 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
287 struct r600_surface *surf =
288 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
289 unsigned format, swap, spi_format, colormask;
290 bool has_alpha, has_rgb;
291
292 if (!surf)
293 continue;
294
295 format = G_028C70_FORMAT(surf->cb_color_info);
296 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
297 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
298 colormask = (cb_target_mask >> (i * 4)) & 0xf;
299
300 /* Set if RGB and A are present. */
301 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
302
303 if (format == V_028C70_COLOR_8 ||
304 format == V_028C70_COLOR_16 ||
305 format == V_028C70_COLOR_32)
306 has_rgb = !has_alpha;
307 else
308 has_rgb = true;
309
310 /* Check the colormask and export format. */
311 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
312 has_rgb = false;
313 if (!(colormask & PIPE_MASK_A))
314 has_alpha = false;
315
316 if (spi_format == V_028714_SPI_SHADER_ZERO) {
317 has_rgb = false;
318 has_alpha = false;
319 }
320
321 /* Disable value checking for disabled channels. */
322 if (!has_rgb)
323 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
324 if (!has_alpha)
325 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
326
327 /* Enable down-conversion for 32bpp and smaller formats. */
328 switch (format) {
329 case V_028C70_COLOR_8:
330 case V_028C70_COLOR_8_8:
331 case V_028C70_COLOR_8_8_8_8:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
335 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
336 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
337 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
338 }
339 break;
340
341 case V_028C70_COLOR_5_6_5:
342 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
343 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
344 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
345 }
346 break;
347
348 case V_028C70_COLOR_1_5_5_5:
349 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
350 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
351 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
352 }
353 break;
354
355 case V_028C70_COLOR_4_4_4_4:
356 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
357 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
358 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
359 }
360 break;
361
362 case V_028C70_COLOR_32:
363 if (swap == V_0280A0_SWAP_STD &&
364 spi_format == V_028714_SPI_SHADER_32_R)
365 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
366 else if (swap == V_0280A0_SWAP_ALT_REV &&
367 spi_format == V_028714_SPI_SHADER_32_AR)
368 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
369 break;
370
371 case V_028C70_COLOR_16:
372 case V_028C70_COLOR_16_16:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
377 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
378 if (swap == V_0280A0_SWAP_STD ||
379 swap == V_0280A0_SWAP_STD_REV)
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
381 else
382 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
383 }
384 break;
385
386 case V_028C70_COLOR_10_11_11:
387 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
388 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
389 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
390 }
391 break;
392
393 case V_028C70_COLOR_2_10_10_10:
394 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
395 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
396 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
397 }
398 break;
399 }
400 }
401
402 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
403 sx_ps_downconvert = 0;
404 sx_blend_opt_epsilon = 0;
405 sx_blend_opt_control = 0;
406 }
407
408 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
409 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
412 }
413 }
414
415 /*
416 * Blender functions
417 */
418
419 static uint32_t si_translate_blend_function(int blend_func)
420 {
421 switch (blend_func) {
422 case PIPE_BLEND_ADD:
423 return V_028780_COMB_DST_PLUS_SRC;
424 case PIPE_BLEND_SUBTRACT:
425 return V_028780_COMB_SRC_MINUS_DST;
426 case PIPE_BLEND_REVERSE_SUBTRACT:
427 return V_028780_COMB_DST_MINUS_SRC;
428 case PIPE_BLEND_MIN:
429 return V_028780_COMB_MIN_DST_SRC;
430 case PIPE_BLEND_MAX:
431 return V_028780_COMB_MAX_DST_SRC;
432 default:
433 R600_ERR("Unknown blend function %d\n", blend_func);
434 assert(0);
435 break;
436 }
437 return 0;
438 }
439
440 static uint32_t si_translate_blend_factor(int blend_fact)
441 {
442 switch (blend_fact) {
443 case PIPE_BLENDFACTOR_ONE:
444 return V_028780_BLEND_ONE;
445 case PIPE_BLENDFACTOR_SRC_COLOR:
446 return V_028780_BLEND_SRC_COLOR;
447 case PIPE_BLENDFACTOR_SRC_ALPHA:
448 return V_028780_BLEND_SRC_ALPHA;
449 case PIPE_BLENDFACTOR_DST_ALPHA:
450 return V_028780_BLEND_DST_ALPHA;
451 case PIPE_BLENDFACTOR_DST_COLOR:
452 return V_028780_BLEND_DST_COLOR;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE;
455 case PIPE_BLENDFACTOR_CONST_COLOR:
456 return V_028780_BLEND_CONSTANT_COLOR;
457 case PIPE_BLENDFACTOR_CONST_ALPHA:
458 return V_028780_BLEND_CONSTANT_ALPHA;
459 case PIPE_BLENDFACTOR_ZERO:
460 return V_028780_BLEND_ZERO;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
473 case PIPE_BLENDFACTOR_SRC1_COLOR:
474 return V_028780_BLEND_SRC1_COLOR;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA:
476 return V_028780_BLEND_SRC1_ALPHA;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
478 return V_028780_BLEND_INV_SRC1_COLOR;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
480 return V_028780_BLEND_INV_SRC1_ALPHA;
481 default:
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
483 assert(0);
484 break;
485 }
486 return 0;
487 }
488
489 static uint32_t si_translate_blend_opt_function(int blend_func)
490 {
491 switch (blend_func) {
492 case PIPE_BLEND_ADD:
493 return V_028760_OPT_COMB_ADD;
494 case PIPE_BLEND_SUBTRACT:
495 return V_028760_OPT_COMB_SUBTRACT;
496 case PIPE_BLEND_REVERSE_SUBTRACT:
497 return V_028760_OPT_COMB_REVSUBTRACT;
498 case PIPE_BLEND_MIN:
499 return V_028760_OPT_COMB_MIN;
500 case PIPE_BLEND_MAX:
501 return V_028760_OPT_COMB_MAX;
502 default:
503 return V_028760_OPT_COMB_BLEND_DISABLED;
504 }
505 }
506
507 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
508 {
509 switch (blend_fact) {
510 case PIPE_BLENDFACTOR_ZERO:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
512 case PIPE_BLENDFACTOR_ONE:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
514 case PIPE_BLENDFACTOR_SRC_COLOR:
515 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
518 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
520 case PIPE_BLENDFACTOR_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
525 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
527 default:
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
529 }
530 }
531
532 /**
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 */
536 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
537 unsigned *dst_factor, unsigned expected_dst,
538 unsigned replacement_src)
539 {
540 if (*src_factor == expected_dst &&
541 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
542 *src_factor = PIPE_BLENDFACTOR_ZERO;
543 *dst_factor = replacement_src;
544
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func == PIPE_BLEND_SUBTRACT)
547 *func = PIPE_BLEND_REVERSE_SUBTRACT;
548 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
549 *func = PIPE_BLEND_SUBTRACT;
550 }
551 }
552
553 static bool si_blend_factor_uses_dst(unsigned factor)
554 {
555 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
556 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
559 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
560 }
561
562 static void *si_create_blend_state_mode(struct pipe_context *ctx,
563 const struct pipe_blend_state *state,
564 unsigned mode)
565 {
566 struct si_context *sctx = (struct si_context*)ctx;
567 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
568 struct si_pm4_state *pm4 = &blend->pm4;
569 uint32_t sx_mrt_blend_opt[8] = {0};
570 uint32_t color_control = 0;
571
572 if (!blend)
573 return NULL;
574
575 blend->alpha_to_coverage = state->alpha_to_coverage;
576 blend->alpha_to_one = state->alpha_to_one;
577 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
578
579 if (state->logicop_enable) {
580 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
581 } else {
582 color_control |= S_028808_ROP3(0xcc);
583 }
584
585 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
591
592 if (state->alpha_to_coverage)
593 blend->need_src_alpha_4bit |= 0xf;
594
595 blend->cb_target_mask = 0;
596 for (int i = 0; i < 8; i++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j = state->independent_blend_enable ? i : 0;
599
600 unsigned eqRGB = state->rt[j].rgb_func;
601 unsigned srcRGB = state->rt[j].rgb_src_factor;
602 unsigned dstRGB = state->rt[j].rgb_dst_factor;
603 unsigned eqA = state->rt[j].alpha_func;
604 unsigned srcA = state->rt[j].alpha_src_factor;
605 unsigned dstA = state->rt[j].alpha_dst_factor;
606
607 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
608 unsigned blend_cntl = 0;
609
610 sx_mrt_blend_opt[i] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
613
614 if (!state->rt[j].colormask)
615 continue;
616
617 /* cb_render_state will disable unused ones */
618 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
619
620 if (!state->rt[j].blend_enable) {
621 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 continue;
623 }
624
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
627 *
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
630 */
631 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
632 PIPE_BLENDFACTOR_DST_COLOR,
633 PIPE_BLENDFACTOR_SRC_COLOR);
634 si_blend_remove_dst(&eqA, &srcA, &dstA,
635 PIPE_BLENDFACTOR_DST_COLOR,
636 PIPE_BLENDFACTOR_SRC_COLOR);
637 si_blend_remove_dst(&eqA, &srcA, &dstA,
638 PIPE_BLENDFACTOR_DST_ALPHA,
639 PIPE_BLENDFACTOR_SRC_ALPHA);
640
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
643 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
644 srcA_opt = si_translate_blend_opt_factor(srcA, true);
645 dstA_opt = si_translate_blend_opt_factor(dstA, true);
646
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650 if (si_blend_factor_uses_dst(srcA))
651 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
652
653 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
654 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
656 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
657 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
658
659 /* Set the final value. */
660 sx_mrt_blend_opt[i] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt) |
665 S_028760_ALPHA_DST_OPT(dstA_opt) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
667
668 /* Set blend state. */
669 blend_cntl |= S_028780_ENABLE(1);
670 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
671 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
672 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
673
674 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
675 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
677 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
678 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
679 }
680 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
681
682 blend->blend_enable_4bit |= 0xf << (i * 4);
683
684 /* This is only important for formats without alpha. */
685 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
687 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
689 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
690 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
691 blend->need_src_alpha_4bit |= 0xf << (i * 4);
692 }
693
694 if (blend->cb_target_mask) {
695 color_control |= S_028808_MODE(mode);
696 } else {
697 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
698 }
699
700 if (sctx->b.family == CHIP_STONEY) {
701 for (int i = 0; i < 8; i++)
702 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
703 sx_mrt_blend_opt[i]);
704
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend->dual_src_blend || state->logicop_enable ||
707 mode == V_028808_CB_RESOLVE)
708 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
709 }
710
711 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
712 return blend;
713 }
714
715 static void *si_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
719 }
720
721 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
725 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
726 }
727
728 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
729 {
730 struct si_context *sctx = (struct si_context *)ctx;
731 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
732 }
733
734 static void si_set_blend_color(struct pipe_context *ctx,
735 const struct pipe_blend_color *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738
739 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->blend_color.state = *state;
743 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
744 }
745
746 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
747 {
748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
749
750 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
751 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
752 }
753
754 /*
755 * Clipping
756 */
757
758 static void si_set_clip_state(struct pipe_context *ctx,
759 const struct pipe_clip_state *state)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_constant_buffer cb;
763
764 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
765 return;
766
767 sctx->clip_state.state = *state;
768 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
769
770 cb.buffer = NULL;
771 cb.user_buffer = state->ucp;
772 cb.buffer_offset = 0;
773 cb.buffer_size = 4*4*8;
774 si_set_constant_buffer(sctx, &sctx->rw_buffers,
775 SI_VS_CONST_CLIP_PLANES, &cb);
776 pipe_resource_reference(&cb.buffer, NULL);
777 }
778
779 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
780 {
781 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
782
783 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
784 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
785 }
786
787 #define SIX_BITS 0x3F
788
789 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
790 {
791 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
792 struct tgsi_shader_info *info = si_get_vs_info(sctx);
793 unsigned window_space =
794 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
795 unsigned clipdist_mask =
796 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
797
798 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
799 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
800 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
801 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
802 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
803 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
804 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
805 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
806 info->writes_edgeflag ||
807 info->writes_layer ||
808 info->writes_viewport_index) |
809 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
810 (sctx->queued.named.rasterizer->clip_plane_enable &
811 clipdist_mask));
812 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
813 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
814 (clipdist_mask ? 0 :
815 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
816 S_028810_CLIP_DISABLE(window_space));
817
818 /* reuse needs to be set off if we write oViewport */
819 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
820 S_028AB4_REUSE_OFF(info->writes_viewport_index));
821 }
822
823 /*
824 * inferred state between framebuffer and rasterizer
825 */
826 static void si_update_poly_offset_state(struct si_context *sctx)
827 {
828 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
829
830 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
831 return;
832
833 switch (sctx->framebuffer.state.zsbuf->texture->format) {
834 case PIPE_FORMAT_Z16_UNORM:
835 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
836 break;
837 default: /* 24-bit */
838 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
839 break;
840 case PIPE_FORMAT_Z32_FLOAT:
841 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
842 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
843 break;
844 }
845 }
846
847 /*
848 * Rasterizer
849 */
850
851 static uint32_t si_translate_fill(uint32_t func)
852 {
853 switch(func) {
854 case PIPE_POLYGON_MODE_FILL:
855 return V_028814_X_DRAW_TRIANGLES;
856 case PIPE_POLYGON_MODE_LINE:
857 return V_028814_X_DRAW_LINES;
858 case PIPE_POLYGON_MODE_POINT:
859 return V_028814_X_DRAW_POINTS;
860 default:
861 assert(0);
862 return V_028814_X_DRAW_POINTS;
863 }
864 }
865
866 static void *si_create_rs_state(struct pipe_context *ctx,
867 const struct pipe_rasterizer_state *state)
868 {
869 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
870 struct si_pm4_state *pm4 = &rs->pm4;
871 unsigned tmp, i;
872 float psize_min, psize_max;
873
874 if (!rs) {
875 return NULL;
876 }
877
878 rs->scissor_enable = state->scissor;
879 rs->two_side = state->light_twoside;
880 rs->multisample_enable = state->multisample;
881 rs->force_persample_interp = state->force_persample_interp;
882 rs->clip_plane_enable = state->clip_plane_enable;
883 rs->line_stipple_enable = state->line_stipple_enable;
884 rs->poly_stipple_enable = state->poly_stipple_enable;
885 rs->line_smooth = state->line_smooth;
886 rs->poly_smooth = state->poly_smooth;
887 rs->uses_poly_offset = state->offset_point || state->offset_line ||
888 state->offset_tri;
889 rs->clamp_fragment_color = state->clamp_fragment_color;
890 rs->flatshade = state->flatshade;
891 rs->sprite_coord_enable = state->sprite_coord_enable;
892 rs->rasterizer_discard = state->rasterizer_discard;
893 rs->pa_sc_line_stipple = state->line_stipple_enable ?
894 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
895 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
896 rs->pa_cl_clip_cntl =
897 S_028810_PS_UCP_MODE(3) |
898 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
899 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
900 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
901 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
902 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
903
904 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
905 S_0286D4_FLAT_SHADE_ENA(1) |
906 S_0286D4_PNT_SPRITE_ENA(1) |
907 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
908 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
909 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
910 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
911 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
912
913 /* point size 12.4 fixed point */
914 tmp = (unsigned)(state->point_size * 8.0);
915 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
916
917 if (state->point_size_per_vertex) {
918 psize_min = util_get_min_point_size(state);
919 psize_max = 8192;
920 } else {
921 /* Force the point size to be as if the vertex output was disabled. */
922 psize_min = state->point_size;
923 psize_max = state->point_size;
924 }
925 /* Divide by two, because 0.5 = 1 pixel. */
926 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
927 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
928 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
929
930 tmp = (unsigned)state->line_width * 8;
931 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
932 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
933 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
934 S_028A48_MSAA_ENABLE(state->multisample ||
935 state->poly_smooth ||
936 state->line_smooth) |
937 S_028A48_VPORT_SCISSOR_ENABLE(1));
938
939 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
940 S_028BE4_PIX_CENTER(state->half_pixel_center) |
941 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
942
943 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
944 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
945 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
946 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
947 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
948 S_028814_FACE(!state->front_ccw) |
949 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
950 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
951 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
952 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
953 state->fill_back != PIPE_POLYGON_MODE_FILL) |
954 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
955 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
956 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
957 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
958
959 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
960 for (i = 0; i < 3; i++) {
961 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
962 float offset_units = state->offset_units;
963 float offset_scale = state->offset_scale * 16.0f;
964
965 switch (i) {
966 case 0: /* 16-bit zbuffer */
967 offset_units *= 4.0f;
968 break;
969 case 1: /* 24-bit zbuffer */
970 offset_units *= 2.0f;
971 break;
972 case 2: /* 32-bit zbuffer */
973 offset_units *= 1.0f;
974 break;
975 }
976
977 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
978 fui(offset_scale));
979 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
980 fui(offset_units));
981 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
982 fui(offset_scale));
983 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
984 fui(offset_units));
985 }
986
987 return rs;
988 }
989
990 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
991 {
992 struct si_context *sctx = (struct si_context *)ctx;
993 struct si_state_rasterizer *old_rs =
994 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
995 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
996
997 if (!state)
998 return;
999
1000 if (sctx->framebuffer.nr_samples > 1 &&
1001 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1002 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1003
1004 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
1005
1006 si_pm4_bind_state(sctx, rasterizer, rs);
1007 si_update_poly_offset_state(sctx);
1008
1009 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1010 }
1011
1012 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct si_context *sctx = (struct si_context *)ctx;
1015
1016 if (sctx->queued.named.rasterizer == state)
1017 si_pm4_bind_state(sctx, poly_offset, NULL);
1018 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1019 }
1020
1021 /*
1022 * infeered state between dsa and stencil ref
1023 */
1024 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1025 {
1026 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1027 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1028 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1029
1030 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1031 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1032 S_028430_STENCILMASK(dsa->valuemask[0]) |
1033 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1034 S_028430_STENCILOPVAL(1));
1035 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1036 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1037 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1038 S_028434_STENCILOPVAL_BF(1));
1039 }
1040
1041 static void si_set_stencil_ref(struct pipe_context *ctx,
1042 const struct pipe_stencil_ref *state)
1043 {
1044 struct si_context *sctx = (struct si_context *)ctx;
1045
1046 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1047 return;
1048
1049 sctx->stencil_ref.state = *state;
1050 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1051 }
1052
1053
1054 /*
1055 * DSA
1056 */
1057
1058 static uint32_t si_translate_stencil_op(int s_op)
1059 {
1060 switch (s_op) {
1061 case PIPE_STENCIL_OP_KEEP:
1062 return V_02842C_STENCIL_KEEP;
1063 case PIPE_STENCIL_OP_ZERO:
1064 return V_02842C_STENCIL_ZERO;
1065 case PIPE_STENCIL_OP_REPLACE:
1066 return V_02842C_STENCIL_REPLACE_TEST;
1067 case PIPE_STENCIL_OP_INCR:
1068 return V_02842C_STENCIL_ADD_CLAMP;
1069 case PIPE_STENCIL_OP_DECR:
1070 return V_02842C_STENCIL_SUB_CLAMP;
1071 case PIPE_STENCIL_OP_INCR_WRAP:
1072 return V_02842C_STENCIL_ADD_WRAP;
1073 case PIPE_STENCIL_OP_DECR_WRAP:
1074 return V_02842C_STENCIL_SUB_WRAP;
1075 case PIPE_STENCIL_OP_INVERT:
1076 return V_02842C_STENCIL_INVERT;
1077 default:
1078 R600_ERR("Unknown stencil op %d", s_op);
1079 assert(0);
1080 break;
1081 }
1082 return 0;
1083 }
1084
1085 static void *si_create_dsa_state(struct pipe_context *ctx,
1086 const struct pipe_depth_stencil_alpha_state *state)
1087 {
1088 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1089 struct si_pm4_state *pm4 = &dsa->pm4;
1090 unsigned db_depth_control;
1091 uint32_t db_stencil_control = 0;
1092
1093 if (!dsa) {
1094 return NULL;
1095 }
1096
1097 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1098 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1099 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1100 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1101
1102 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1103 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1104 S_028800_ZFUNC(state->depth.func) |
1105 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1106
1107 /* stencil */
1108 if (state->stencil[0].enabled) {
1109 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1110 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1111 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1112 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1113 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1114
1115 if (state->stencil[1].enabled) {
1116 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1117 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1118 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1119 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1120 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1121 }
1122 }
1123
1124 /* alpha */
1125 if (state->alpha.enabled) {
1126 dsa->alpha_func = state->alpha.func;
1127
1128 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1129 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1130 } else {
1131 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1132 }
1133
1134 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1135 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1136 if (state->depth.bounds_test) {
1137 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1138 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1139 }
1140
1141 return dsa;
1142 }
1143
1144 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1145 {
1146 struct si_context *sctx = (struct si_context *)ctx;
1147 struct si_state_dsa *dsa = state;
1148
1149 if (!state)
1150 return;
1151
1152 si_pm4_bind_state(sctx, dsa, dsa);
1153
1154 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1155 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1156 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1157 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1158 }
1159 }
1160
1161 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1162 {
1163 struct si_context *sctx = (struct si_context *)ctx;
1164 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1165 }
1166
1167 static void *si_create_db_flush_dsa(struct si_context *sctx)
1168 {
1169 struct pipe_depth_stencil_alpha_state dsa = {};
1170
1171 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1172 }
1173
1174 /* DB RENDER STATE */
1175
1176 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1177 {
1178 struct si_context *sctx = (struct si_context*)ctx;
1179
1180 /* Pipeline stat & streamout queries. */
1181 if (enable) {
1182 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1183 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1184 } else {
1185 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1186 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1187 }
1188
1189 /* Occlusion queries. */
1190 if (sctx->occlusion_queries_disabled != !enable) {
1191 sctx->occlusion_queries_disabled = !enable;
1192 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1193 }
1194 }
1195
1196 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1197 {
1198 struct si_context *sctx = (struct si_context*)ctx;
1199
1200 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1201 }
1202
1203 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1204 {
1205 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1206 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1207 unsigned db_shader_control;
1208
1209 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1210
1211 /* DB_RENDER_CONTROL */
1212 if (sctx->dbcb_depth_copy_enabled ||
1213 sctx->dbcb_stencil_copy_enabled) {
1214 radeon_emit(cs,
1215 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1216 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1217 S_028000_COPY_CENTROID(1) |
1218 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1219 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1220 radeon_emit(cs,
1221 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1222 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1223 } else {
1224 radeon_emit(cs,
1225 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1226 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1227 }
1228
1229 /* DB_COUNT_CONTROL (occlusion queries) */
1230 if (sctx->b.num_occlusion_queries > 0 &&
1231 !sctx->occlusion_queries_disabled) {
1232 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1233
1234 if (sctx->b.chip_class >= CIK) {
1235 radeon_emit(cs,
1236 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1237 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1238 S_028004_ZPASS_ENABLE(1) |
1239 S_028004_SLICE_EVEN_ENABLE(1) |
1240 S_028004_SLICE_ODD_ENABLE(1));
1241 } else {
1242 radeon_emit(cs,
1243 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1244 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1245 }
1246 } else {
1247 /* Disable occlusion queries. */
1248 if (sctx->b.chip_class >= CIK) {
1249 radeon_emit(cs, 0);
1250 } else {
1251 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1252 }
1253 }
1254
1255 /* DB_RENDER_OVERRIDE2 */
1256 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1257 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1258 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1259
1260 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1261 sctx->ps_db_shader_control;
1262
1263 /* Bug workaround for smoothing (overrasterization) on SI. */
1264 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1265 db_shader_control &= C_02880C_Z_ORDER;
1266 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1267 }
1268
1269 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1270 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1271 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1272
1273 if (sctx->b.family == CHIP_STONEY &&
1274 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1275 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1276
1277 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1278 db_shader_control);
1279 }
1280
1281 /*
1282 * format translation
1283 */
1284 static uint32_t si_translate_colorformat(enum pipe_format format)
1285 {
1286 const struct util_format_description *desc = util_format_description(format);
1287
1288 #define HAS_SIZE(x,y,z,w) \
1289 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1290 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1291
1292 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1293 return V_028C70_COLOR_10_11_11;
1294
1295 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1296 return V_028C70_COLOR_INVALID;
1297
1298 switch (desc->nr_channels) {
1299 case 1:
1300 switch (desc->channel[0].size) {
1301 case 8:
1302 return V_028C70_COLOR_8;
1303 case 16:
1304 return V_028C70_COLOR_16;
1305 case 32:
1306 return V_028C70_COLOR_32;
1307 }
1308 break;
1309 case 2:
1310 if (desc->channel[0].size == desc->channel[1].size) {
1311 switch (desc->channel[0].size) {
1312 case 8:
1313 return V_028C70_COLOR_8_8;
1314 case 16:
1315 return V_028C70_COLOR_16_16;
1316 case 32:
1317 return V_028C70_COLOR_32_32;
1318 }
1319 } else if (HAS_SIZE(8,24,0,0)) {
1320 return V_028C70_COLOR_24_8;
1321 } else if (HAS_SIZE(24,8,0,0)) {
1322 return V_028C70_COLOR_8_24;
1323 }
1324 break;
1325 case 3:
1326 if (HAS_SIZE(5,6,5,0)) {
1327 return V_028C70_COLOR_5_6_5;
1328 } else if (HAS_SIZE(32,8,24,0)) {
1329 return V_028C70_COLOR_X24_8_32_FLOAT;
1330 }
1331 break;
1332 case 4:
1333 if (desc->channel[0].size == desc->channel[1].size &&
1334 desc->channel[0].size == desc->channel[2].size &&
1335 desc->channel[0].size == desc->channel[3].size) {
1336 switch (desc->channel[0].size) {
1337 case 4:
1338 return V_028C70_COLOR_4_4_4_4;
1339 case 8:
1340 return V_028C70_COLOR_8_8_8_8;
1341 case 16:
1342 return V_028C70_COLOR_16_16_16_16;
1343 case 32:
1344 return V_028C70_COLOR_32_32_32_32;
1345 }
1346 } else if (HAS_SIZE(5,5,5,1)) {
1347 return V_028C70_COLOR_1_5_5_5;
1348 } else if (HAS_SIZE(10,10,10,2)) {
1349 return V_028C70_COLOR_2_10_10_10;
1350 }
1351 break;
1352 }
1353 return V_028C70_COLOR_INVALID;
1354 }
1355
1356 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1357 {
1358 if (SI_BIG_ENDIAN) {
1359 switch(colorformat) {
1360 /* 8-bit buffers. */
1361 case V_028C70_COLOR_8:
1362 return V_028C70_ENDIAN_NONE;
1363
1364 /* 16-bit buffers. */
1365 case V_028C70_COLOR_5_6_5:
1366 case V_028C70_COLOR_1_5_5_5:
1367 case V_028C70_COLOR_4_4_4_4:
1368 case V_028C70_COLOR_16:
1369 case V_028C70_COLOR_8_8:
1370 return V_028C70_ENDIAN_8IN16;
1371
1372 /* 32-bit buffers. */
1373 case V_028C70_COLOR_8_8_8_8:
1374 case V_028C70_COLOR_2_10_10_10:
1375 case V_028C70_COLOR_8_24:
1376 case V_028C70_COLOR_24_8:
1377 case V_028C70_COLOR_16_16:
1378 return V_028C70_ENDIAN_8IN32;
1379
1380 /* 64-bit buffers. */
1381 case V_028C70_COLOR_16_16_16_16:
1382 return V_028C70_ENDIAN_8IN16;
1383
1384 case V_028C70_COLOR_32_32:
1385 return V_028C70_ENDIAN_8IN32;
1386
1387 /* 128-bit buffers. */
1388 case V_028C70_COLOR_32_32_32_32:
1389 return V_028C70_ENDIAN_8IN32;
1390 default:
1391 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1392 }
1393 } else {
1394 return V_028C70_ENDIAN_NONE;
1395 }
1396 }
1397
1398 static uint32_t si_translate_dbformat(enum pipe_format format)
1399 {
1400 switch (format) {
1401 case PIPE_FORMAT_Z16_UNORM:
1402 return V_028040_Z_16;
1403 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1404 case PIPE_FORMAT_X8Z24_UNORM:
1405 case PIPE_FORMAT_Z24X8_UNORM:
1406 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1407 return V_028040_Z_24; /* deprecated on SI */
1408 case PIPE_FORMAT_Z32_FLOAT:
1409 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1410 return V_028040_Z_32_FLOAT;
1411 default:
1412 return V_028040_Z_INVALID;
1413 }
1414 }
1415
1416 /*
1417 * Texture translation
1418 */
1419
1420 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1421 enum pipe_format format,
1422 const struct util_format_description *desc,
1423 int first_non_void)
1424 {
1425 struct si_screen *sscreen = (struct si_screen*)screen;
1426 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1427 sscreen->b.info.drm_minor >= 31) ||
1428 sscreen->b.info.drm_major == 3;
1429 boolean uniform = TRUE;
1430 int i;
1431
1432 /* Colorspace (return non-RGB formats directly). */
1433 switch (desc->colorspace) {
1434 /* Depth stencil formats */
1435 case UTIL_FORMAT_COLORSPACE_ZS:
1436 switch (format) {
1437 case PIPE_FORMAT_Z16_UNORM:
1438 return V_008F14_IMG_DATA_FORMAT_16;
1439 case PIPE_FORMAT_X24S8_UINT:
1440 case PIPE_FORMAT_Z24X8_UNORM:
1441 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1442 return V_008F14_IMG_DATA_FORMAT_8_24;
1443 case PIPE_FORMAT_X8Z24_UNORM:
1444 case PIPE_FORMAT_S8X24_UINT:
1445 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1446 return V_008F14_IMG_DATA_FORMAT_24_8;
1447 case PIPE_FORMAT_S8_UINT:
1448 return V_008F14_IMG_DATA_FORMAT_8;
1449 case PIPE_FORMAT_Z32_FLOAT:
1450 return V_008F14_IMG_DATA_FORMAT_32;
1451 case PIPE_FORMAT_X32_S8X24_UINT:
1452 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1453 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1454 default:
1455 goto out_unknown;
1456 }
1457
1458 case UTIL_FORMAT_COLORSPACE_YUV:
1459 goto out_unknown; /* TODO */
1460
1461 case UTIL_FORMAT_COLORSPACE_SRGB:
1462 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1463 goto out_unknown;
1464 break;
1465
1466 default:
1467 break;
1468 }
1469
1470 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1471 if (!enable_compressed_formats)
1472 goto out_unknown;
1473
1474 switch (format) {
1475 case PIPE_FORMAT_RGTC1_SNORM:
1476 case PIPE_FORMAT_LATC1_SNORM:
1477 case PIPE_FORMAT_RGTC1_UNORM:
1478 case PIPE_FORMAT_LATC1_UNORM:
1479 return V_008F14_IMG_DATA_FORMAT_BC4;
1480 case PIPE_FORMAT_RGTC2_SNORM:
1481 case PIPE_FORMAT_LATC2_SNORM:
1482 case PIPE_FORMAT_RGTC2_UNORM:
1483 case PIPE_FORMAT_LATC2_UNORM:
1484 return V_008F14_IMG_DATA_FORMAT_BC5;
1485 default:
1486 goto out_unknown;
1487 }
1488 }
1489
1490 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1491 sscreen->b.family == CHIP_STONEY) {
1492 switch (format) {
1493 case PIPE_FORMAT_ETC1_RGB8:
1494 case PIPE_FORMAT_ETC2_RGB8:
1495 case PIPE_FORMAT_ETC2_SRGB8:
1496 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1497 case PIPE_FORMAT_ETC2_RGB8A1:
1498 case PIPE_FORMAT_ETC2_SRGB8A1:
1499 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1500 case PIPE_FORMAT_ETC2_RGBA8:
1501 case PIPE_FORMAT_ETC2_SRGBA8:
1502 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1503 case PIPE_FORMAT_ETC2_R11_UNORM:
1504 case PIPE_FORMAT_ETC2_R11_SNORM:
1505 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1506 case PIPE_FORMAT_ETC2_RG11_UNORM:
1507 case PIPE_FORMAT_ETC2_RG11_SNORM:
1508 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1509 default:
1510 goto out_unknown;
1511 }
1512 }
1513
1514 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1515 if (!enable_compressed_formats)
1516 goto out_unknown;
1517
1518 switch (format) {
1519 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1520 case PIPE_FORMAT_BPTC_SRGBA:
1521 return V_008F14_IMG_DATA_FORMAT_BC7;
1522 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1523 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1524 return V_008F14_IMG_DATA_FORMAT_BC6;
1525 default:
1526 goto out_unknown;
1527 }
1528 }
1529
1530 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1531 switch (format) {
1532 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1533 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1534 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1535 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1536 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1537 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1538 default:
1539 goto out_unknown;
1540 }
1541 }
1542
1543 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1544 if (!enable_compressed_formats)
1545 goto out_unknown;
1546
1547 if (!util_format_s3tc_enabled) {
1548 goto out_unknown;
1549 }
1550
1551 switch (format) {
1552 case PIPE_FORMAT_DXT1_RGB:
1553 case PIPE_FORMAT_DXT1_RGBA:
1554 case PIPE_FORMAT_DXT1_SRGB:
1555 case PIPE_FORMAT_DXT1_SRGBA:
1556 return V_008F14_IMG_DATA_FORMAT_BC1;
1557 case PIPE_FORMAT_DXT3_RGBA:
1558 case PIPE_FORMAT_DXT3_SRGBA:
1559 return V_008F14_IMG_DATA_FORMAT_BC2;
1560 case PIPE_FORMAT_DXT5_RGBA:
1561 case PIPE_FORMAT_DXT5_SRGBA:
1562 return V_008F14_IMG_DATA_FORMAT_BC3;
1563 default:
1564 goto out_unknown;
1565 }
1566 }
1567
1568 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1569 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1570 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1571 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1572 }
1573
1574 /* R8G8Bx_SNORM - TODO CxV8U8 */
1575
1576 /* See whether the components are of the same size. */
1577 for (i = 1; i < desc->nr_channels; i++) {
1578 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1579 }
1580
1581 /* Non-uniform formats. */
1582 if (!uniform) {
1583 switch(desc->nr_channels) {
1584 case 3:
1585 if (desc->channel[0].size == 5 &&
1586 desc->channel[1].size == 6 &&
1587 desc->channel[2].size == 5) {
1588 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1589 }
1590 goto out_unknown;
1591 case 4:
1592 if (desc->channel[0].size == 5 &&
1593 desc->channel[1].size == 5 &&
1594 desc->channel[2].size == 5 &&
1595 desc->channel[3].size == 1) {
1596 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1597 }
1598 if (desc->channel[0].size == 10 &&
1599 desc->channel[1].size == 10 &&
1600 desc->channel[2].size == 10 &&
1601 desc->channel[3].size == 2) {
1602 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1603 }
1604 goto out_unknown;
1605 }
1606 goto out_unknown;
1607 }
1608
1609 if (first_non_void < 0 || first_non_void > 3)
1610 goto out_unknown;
1611
1612 /* uniform formats */
1613 switch (desc->channel[first_non_void].size) {
1614 case 4:
1615 switch (desc->nr_channels) {
1616 #if 0 /* Not supported for render targets */
1617 case 2:
1618 return V_008F14_IMG_DATA_FORMAT_4_4;
1619 #endif
1620 case 4:
1621 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1622 }
1623 break;
1624 case 8:
1625 switch (desc->nr_channels) {
1626 case 1:
1627 return V_008F14_IMG_DATA_FORMAT_8;
1628 case 2:
1629 return V_008F14_IMG_DATA_FORMAT_8_8;
1630 case 4:
1631 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1632 }
1633 break;
1634 case 16:
1635 switch (desc->nr_channels) {
1636 case 1:
1637 return V_008F14_IMG_DATA_FORMAT_16;
1638 case 2:
1639 return V_008F14_IMG_DATA_FORMAT_16_16;
1640 case 4:
1641 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1642 }
1643 break;
1644 case 32:
1645 switch (desc->nr_channels) {
1646 case 1:
1647 return V_008F14_IMG_DATA_FORMAT_32;
1648 case 2:
1649 return V_008F14_IMG_DATA_FORMAT_32_32;
1650 #if 0 /* Not supported for render targets */
1651 case 3:
1652 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1653 #endif
1654 case 4:
1655 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1656 }
1657 }
1658
1659 out_unknown:
1660 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1661 return ~0;
1662 }
1663
1664 static unsigned si_tex_wrap(unsigned wrap)
1665 {
1666 switch (wrap) {
1667 default:
1668 case PIPE_TEX_WRAP_REPEAT:
1669 return V_008F30_SQ_TEX_WRAP;
1670 case PIPE_TEX_WRAP_CLAMP:
1671 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1672 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1673 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1674 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1675 return V_008F30_SQ_TEX_CLAMP_BORDER;
1676 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1677 return V_008F30_SQ_TEX_MIRROR;
1678 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1679 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1680 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1681 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1682 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1683 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1684 }
1685 }
1686
1687 static unsigned si_tex_mipfilter(unsigned filter)
1688 {
1689 switch (filter) {
1690 case PIPE_TEX_MIPFILTER_NEAREST:
1691 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1692 case PIPE_TEX_MIPFILTER_LINEAR:
1693 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1694 default:
1695 case PIPE_TEX_MIPFILTER_NONE:
1696 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1697 }
1698 }
1699
1700 static unsigned si_tex_compare(unsigned compare)
1701 {
1702 switch (compare) {
1703 default:
1704 case PIPE_FUNC_NEVER:
1705 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1706 case PIPE_FUNC_LESS:
1707 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1708 case PIPE_FUNC_EQUAL:
1709 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1710 case PIPE_FUNC_LEQUAL:
1711 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1712 case PIPE_FUNC_GREATER:
1713 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1714 case PIPE_FUNC_NOTEQUAL:
1715 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1716 case PIPE_FUNC_GEQUAL:
1717 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1718 case PIPE_FUNC_ALWAYS:
1719 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1720 }
1721 }
1722
1723 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1724 unsigned nr_samples)
1725 {
1726 if (view_target == PIPE_TEXTURE_CUBE ||
1727 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1728 res_target = view_target;
1729
1730 switch (res_target) {
1731 default:
1732 case PIPE_TEXTURE_1D:
1733 return V_008F1C_SQ_RSRC_IMG_1D;
1734 case PIPE_TEXTURE_1D_ARRAY:
1735 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1736 case PIPE_TEXTURE_2D:
1737 case PIPE_TEXTURE_RECT:
1738 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1739 V_008F1C_SQ_RSRC_IMG_2D;
1740 case PIPE_TEXTURE_2D_ARRAY:
1741 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1742 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1743 case PIPE_TEXTURE_3D:
1744 return V_008F1C_SQ_RSRC_IMG_3D;
1745 case PIPE_TEXTURE_CUBE:
1746 case PIPE_TEXTURE_CUBE_ARRAY:
1747 return V_008F1C_SQ_RSRC_IMG_CUBE;
1748 }
1749 }
1750
1751 /*
1752 * Format support testing
1753 */
1754
1755 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1756 {
1757 return si_translate_texformat(screen, format, util_format_description(format),
1758 util_format_get_first_non_void_channel(format)) != ~0U;
1759 }
1760
1761 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1762 const struct util_format_description *desc,
1763 int first_non_void)
1764 {
1765 if (first_non_void < 0)
1766 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1767
1768 unsigned type = desc->channel[first_non_void].type;
1769 int i;
1770
1771 if (type == UTIL_FORMAT_TYPE_FIXED)
1772 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1773
1774 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1775 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1776
1777 if (desc->nr_channels == 4 &&
1778 desc->channel[0].size == 10 &&
1779 desc->channel[1].size == 10 &&
1780 desc->channel[2].size == 10 &&
1781 desc->channel[3].size == 2)
1782 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1783
1784 /* See whether the components are of the same size. */
1785 for (i = 0; i < desc->nr_channels; i++) {
1786 if (desc->channel[first_non_void].size != desc->channel[i].size)
1787 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1788 }
1789
1790 switch (desc->channel[first_non_void].size) {
1791 case 8:
1792 switch (desc->nr_channels) {
1793 case 1:
1794 return V_008F0C_BUF_DATA_FORMAT_8;
1795 case 2:
1796 return V_008F0C_BUF_DATA_FORMAT_8_8;
1797 case 3:
1798 case 4:
1799 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1800 }
1801 break;
1802 case 16:
1803 switch (desc->nr_channels) {
1804 case 1:
1805 return V_008F0C_BUF_DATA_FORMAT_16;
1806 case 2:
1807 return V_008F0C_BUF_DATA_FORMAT_16_16;
1808 case 3:
1809 case 4:
1810 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1811 }
1812 break;
1813 case 32:
1814 /* From the Southern Islands ISA documentation about MTBUF:
1815 * 'Memory reads of data in memory that is 32 or 64 bits do not
1816 * undergo any format conversion.'
1817 */
1818 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1819 !desc->channel[first_non_void].pure_integer)
1820 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1821
1822 switch (desc->nr_channels) {
1823 case 1:
1824 return V_008F0C_BUF_DATA_FORMAT_32;
1825 case 2:
1826 return V_008F0C_BUF_DATA_FORMAT_32_32;
1827 case 3:
1828 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1829 case 4:
1830 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1831 }
1832 break;
1833 }
1834
1835 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1836 }
1837
1838 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1839 const struct util_format_description *desc,
1840 int first_non_void)
1841 {
1842 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT || first_non_void < 0)
1843 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1844
1845 switch (desc->channel[first_non_void].type) {
1846 case UTIL_FORMAT_TYPE_SIGNED:
1847 if (desc->channel[first_non_void].normalized)
1848 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1849 else if (desc->channel[first_non_void].pure_integer)
1850 return V_008F0C_BUF_NUM_FORMAT_SINT;
1851 else
1852 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1853 break;
1854 case UTIL_FORMAT_TYPE_UNSIGNED:
1855 if (desc->channel[first_non_void].normalized)
1856 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1857 else if (desc->channel[first_non_void].pure_integer)
1858 return V_008F0C_BUF_NUM_FORMAT_UINT;
1859 else
1860 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1861 break;
1862 case UTIL_FORMAT_TYPE_FLOAT:
1863 default:
1864 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1865 }
1866 }
1867
1868 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1869 {
1870 const struct util_format_description *desc;
1871 int first_non_void;
1872 unsigned data_format;
1873
1874 desc = util_format_description(format);
1875 first_non_void = util_format_get_first_non_void_channel(format);
1876 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1877 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1878 }
1879
1880 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1881 {
1882 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1883 r600_translate_colorswap(format, FALSE) != ~0U;
1884 }
1885
1886 static bool si_is_zs_format_supported(enum pipe_format format)
1887 {
1888 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1889 }
1890
1891 boolean si_is_format_supported(struct pipe_screen *screen,
1892 enum pipe_format format,
1893 enum pipe_texture_target target,
1894 unsigned sample_count,
1895 unsigned usage)
1896 {
1897 unsigned retval = 0;
1898
1899 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1900 R600_ERR("r600: unsupported texture type %d\n", target);
1901 return FALSE;
1902 }
1903
1904 if (!util_format_is_supported(format, usage))
1905 return FALSE;
1906
1907 if (sample_count > 1) {
1908 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1909 return FALSE;
1910
1911 switch (sample_count) {
1912 case 2:
1913 case 4:
1914 case 8:
1915 break;
1916 case 16:
1917 if (format == PIPE_FORMAT_NONE)
1918 return TRUE;
1919 else
1920 return FALSE;
1921 default:
1922 return FALSE;
1923 }
1924 }
1925
1926 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1927 if (target == PIPE_BUFFER) {
1928 if (si_is_vertex_format_supported(screen, format))
1929 retval |= PIPE_BIND_SAMPLER_VIEW;
1930 } else {
1931 if (si_is_sampler_format_supported(screen, format))
1932 retval |= PIPE_BIND_SAMPLER_VIEW;
1933 }
1934 }
1935
1936 if ((usage & (PIPE_BIND_RENDER_TARGET |
1937 PIPE_BIND_DISPLAY_TARGET |
1938 PIPE_BIND_SCANOUT |
1939 PIPE_BIND_SHARED |
1940 PIPE_BIND_BLENDABLE)) &&
1941 si_is_colorbuffer_format_supported(format)) {
1942 retval |= usage &
1943 (PIPE_BIND_RENDER_TARGET |
1944 PIPE_BIND_DISPLAY_TARGET |
1945 PIPE_BIND_SCANOUT |
1946 PIPE_BIND_SHARED);
1947 if (!util_format_is_pure_integer(format) &&
1948 !util_format_is_depth_or_stencil(format))
1949 retval |= usage & PIPE_BIND_BLENDABLE;
1950 }
1951
1952 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1953 si_is_zs_format_supported(format)) {
1954 retval |= PIPE_BIND_DEPTH_STENCIL;
1955 }
1956
1957 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1958 si_is_vertex_format_supported(screen, format)) {
1959 retval |= PIPE_BIND_VERTEX_BUFFER;
1960 }
1961
1962 if (usage & PIPE_BIND_TRANSFER_READ)
1963 retval |= PIPE_BIND_TRANSFER_READ;
1964 if (usage & PIPE_BIND_TRANSFER_WRITE)
1965 retval |= PIPE_BIND_TRANSFER_WRITE;
1966
1967 if ((usage & PIPE_BIND_LINEAR) &&
1968 !util_format_is_compressed(format) &&
1969 !(usage & PIPE_BIND_DEPTH_STENCIL))
1970 retval |= PIPE_BIND_LINEAR;
1971
1972 return retval == usage;
1973 }
1974
1975 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1976 {
1977 unsigned tile_mode_index = 0;
1978
1979 if (stencil) {
1980 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1981 } else {
1982 tile_mode_index = rtex->surface.tiling_index[level];
1983 }
1984 return tile_mode_index;
1985 }
1986
1987 /*
1988 * framebuffer handling
1989 */
1990
1991 static void si_choose_spi_color_formats(struct r600_surface *surf,
1992 unsigned format, unsigned swap,
1993 unsigned ntype, bool is_depth)
1994 {
1995 /* Alpha is needed for alpha-to-coverage.
1996 * Blending may be with or without alpha.
1997 */
1998 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1999 unsigned alpha = 0; /* exports alpha, but may not support blending */
2000 unsigned blend = 0; /* supports blending, but may not export alpha */
2001 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2002
2003 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2004 * Other chips have multiple choices, though they are not necessarily better.
2005 */
2006 switch (format) {
2007 case V_028C70_COLOR_5_6_5:
2008 case V_028C70_COLOR_1_5_5_5:
2009 case V_028C70_COLOR_5_5_5_1:
2010 case V_028C70_COLOR_4_4_4_4:
2011 case V_028C70_COLOR_10_11_11:
2012 case V_028C70_COLOR_11_11_10:
2013 case V_028C70_COLOR_8:
2014 case V_028C70_COLOR_8_8:
2015 case V_028C70_COLOR_8_8_8_8:
2016 case V_028C70_COLOR_10_10_10_2:
2017 case V_028C70_COLOR_2_10_10_10:
2018 if (ntype == V_028C70_NUMBER_UINT)
2019 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2020 else if (ntype == V_028C70_NUMBER_SINT)
2021 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2022 else
2023 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2024 break;
2025
2026 case V_028C70_COLOR_16:
2027 case V_028C70_COLOR_16_16:
2028 case V_028C70_COLOR_16_16_16_16:
2029 if (ntype == V_028C70_NUMBER_UNORM ||
2030 ntype == V_028C70_NUMBER_SNORM) {
2031 /* UNORM16 and SNORM16 don't support blending */
2032 if (ntype == V_028C70_NUMBER_UNORM)
2033 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2034 else
2035 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2036
2037 /* Use 32 bits per channel for blending. */
2038 if (format == V_028C70_COLOR_16) {
2039 if (swap == V_028C70_SWAP_STD) { /* R */
2040 blend = V_028714_SPI_SHADER_32_R;
2041 blend_alpha = V_028714_SPI_SHADER_32_AR;
2042 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2043 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2044 else
2045 assert(0);
2046 } else if (format == V_028C70_COLOR_16_16) {
2047 if (swap == V_028C70_SWAP_STD) { /* RG */
2048 blend = V_028714_SPI_SHADER_32_GR;
2049 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2050 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2051 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2052 else
2053 assert(0);
2054 } else /* 16_16_16_16 */
2055 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2056 } else if (ntype == V_028C70_NUMBER_UINT)
2057 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2058 else if (ntype == V_028C70_NUMBER_SINT)
2059 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2060 else if (ntype == V_028C70_NUMBER_FLOAT)
2061 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2062 else
2063 assert(0);
2064 break;
2065
2066 case V_028C70_COLOR_32:
2067 if (swap == V_028C70_SWAP_STD) { /* R */
2068 blend = normal = V_028714_SPI_SHADER_32_R;
2069 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2070 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2071 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2072 else
2073 assert(0);
2074 break;
2075
2076 case V_028C70_COLOR_32_32:
2077 if (swap == V_028C70_SWAP_STD) { /* RG */
2078 blend = normal = V_028714_SPI_SHADER_32_GR;
2079 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2080 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2081 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2082 else
2083 assert(0);
2084 break;
2085
2086 case V_028C70_COLOR_32_32_32_32:
2087 case V_028C70_COLOR_8_24:
2088 case V_028C70_COLOR_24_8:
2089 case V_028C70_COLOR_X24_8_32_FLOAT:
2090 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2091 break;
2092
2093 default:
2094 assert(0);
2095 return;
2096 }
2097
2098 /* The DB->CB copy needs 32_ABGR. */
2099 if (is_depth)
2100 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2101
2102 surf->spi_shader_col_format = normal;
2103 surf->spi_shader_col_format_alpha = alpha;
2104 surf->spi_shader_col_format_blend = blend;
2105 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2106 }
2107
2108 static void si_initialize_color_surface(struct si_context *sctx,
2109 struct r600_surface *surf)
2110 {
2111 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2112 unsigned level = surf->base.u.tex.level;
2113 uint64_t offset = rtex->surface.level[level].offset;
2114 unsigned pitch, slice;
2115 unsigned color_info, color_attrib, color_pitch, color_view;
2116 unsigned tile_mode_index;
2117 unsigned format, swap, ntype, endian;
2118 const struct util_format_description *desc;
2119 int i;
2120 unsigned blend_clamp = 0, blend_bypass = 0;
2121
2122 /* Layered rendering doesn't work with LINEAR_GENERAL.
2123 * (LINEAR_ALIGNED and others work) */
2124 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2125 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2126 offset += rtex->surface.level[level].slice_size *
2127 surf->base.u.tex.first_layer;
2128 color_view = 0;
2129 } else {
2130 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2131 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2132 }
2133
2134 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2135 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2136 if (slice) {
2137 slice = slice - 1;
2138 }
2139
2140 tile_mode_index = si_tile_mode_index(rtex, level, false);
2141
2142 desc = util_format_description(surf->base.format);
2143 for (i = 0; i < 4; i++) {
2144 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2145 break;
2146 }
2147 }
2148 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2149 ntype = V_028C70_NUMBER_FLOAT;
2150 } else {
2151 ntype = V_028C70_NUMBER_UNORM;
2152 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2153 ntype = V_028C70_NUMBER_SRGB;
2154 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2155 if (desc->channel[i].pure_integer) {
2156 ntype = V_028C70_NUMBER_SINT;
2157 } else {
2158 assert(desc->channel[i].normalized);
2159 ntype = V_028C70_NUMBER_SNORM;
2160 }
2161 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2162 if (desc->channel[i].pure_integer) {
2163 ntype = V_028C70_NUMBER_UINT;
2164 } else {
2165 assert(desc->channel[i].normalized);
2166 ntype = V_028C70_NUMBER_UNORM;
2167 }
2168 }
2169 }
2170
2171 format = si_translate_colorformat(surf->base.format);
2172 if (format == V_028C70_COLOR_INVALID) {
2173 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2174 }
2175 assert(format != V_028C70_COLOR_INVALID);
2176 swap = r600_translate_colorswap(surf->base.format, FALSE);
2177 endian = si_colorformat_endian_swap(format);
2178
2179 /* blend clamp should be set for all NORM/SRGB types */
2180 if (ntype == V_028C70_NUMBER_UNORM ||
2181 ntype == V_028C70_NUMBER_SNORM ||
2182 ntype == V_028C70_NUMBER_SRGB)
2183 blend_clamp = 1;
2184
2185 /* set blend bypass according to docs if SINT/UINT or
2186 8/24 COLOR variants */
2187 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2188 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2189 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2190 blend_clamp = 0;
2191 blend_bypass = 1;
2192 }
2193
2194 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2195 (format == V_028C70_COLOR_8 ||
2196 format == V_028C70_COLOR_8_8 ||
2197 format == V_028C70_COLOR_8_8_8_8))
2198 surf->color_is_int8 = true;
2199
2200 color_info = S_028C70_FORMAT(format) |
2201 S_028C70_COMP_SWAP(swap) |
2202 S_028C70_BLEND_CLAMP(blend_clamp) |
2203 S_028C70_BLEND_BYPASS(blend_bypass) |
2204 S_028C70_NUMBER_TYPE(ntype) |
2205 S_028C70_ENDIAN(endian);
2206
2207 color_pitch = S_028C64_TILE_MAX(pitch);
2208
2209 /* Intensity is implemented as Red, so treat it that way. */
2210 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2211 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2212 util_format_is_intensity(surf->base.format));
2213
2214 if (rtex->resource.b.b.nr_samples > 1) {
2215 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2216
2217 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2218 S_028C74_NUM_FRAGMENTS(log_samples);
2219
2220 if (rtex->fmask.size) {
2221 color_info |= S_028C70_COMPRESSION(1);
2222 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2223
2224 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2225
2226 if (sctx->b.chip_class == SI) {
2227 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2228 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2229 }
2230 if (sctx->b.chip_class >= CIK) {
2231 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2232 }
2233 }
2234 }
2235
2236 offset += rtex->resource.gpu_address;
2237
2238 surf->cb_color_base = offset >> 8;
2239 surf->cb_color_pitch = color_pitch;
2240 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2241 surf->cb_color_view = color_view;
2242 surf->cb_color_info = color_info;
2243 surf->cb_color_attrib = color_attrib;
2244
2245 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2246 unsigned max_uncompressed_block_size = 2;
2247
2248 if (rtex->surface.nsamples > 1) {
2249 if (rtex->surface.bpe == 1)
2250 max_uncompressed_block_size = 0;
2251 else if (rtex->surface.bpe == 2)
2252 max_uncompressed_block_size = 1;
2253 }
2254
2255 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2256 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2257 surf->cb_dcc_base = (rtex->resource.gpu_address +
2258 rtex->dcc_offset +
2259 rtex->surface.level[level].dcc_offset) >> 8;
2260 }
2261
2262 if (rtex->fmask.size) {
2263 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2264 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2265 } else {
2266 /* This must be set for fast clear to work without FMASK. */
2267 surf->cb_color_fmask = surf->cb_color_base;
2268 surf->cb_color_fmask_slice = surf->cb_color_slice;
2269 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2270
2271 if (sctx->b.chip_class == SI) {
2272 unsigned bankh = util_logbase2(rtex->surface.bankh);
2273 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2274 }
2275
2276 if (sctx->b.chip_class >= CIK) {
2277 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2278 }
2279 }
2280
2281 /* Determine pixel shader export format */
2282 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2283
2284 surf->color_initialized = true;
2285 }
2286
2287 static void si_init_depth_surface(struct si_context *sctx,
2288 struct r600_surface *surf)
2289 {
2290 struct si_screen *sscreen = sctx->screen;
2291 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2292 unsigned level = surf->base.u.tex.level;
2293 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2294 unsigned format, tile_mode_index, array_mode;
2295 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2296 uint32_t z_info, s_info, db_depth_info;
2297 uint64_t z_offs, s_offs;
2298 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2299
2300 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2301 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2302 case PIPE_FORMAT_X8Z24_UNORM:
2303 case PIPE_FORMAT_Z24X8_UNORM:
2304 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2305 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2306 break;
2307 case PIPE_FORMAT_Z32_FLOAT:
2308 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2309 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2310 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2311 break;
2312 case PIPE_FORMAT_Z16_UNORM:
2313 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2314 break;
2315 default:
2316 assert(0);
2317 }
2318
2319 format = si_translate_dbformat(rtex->resource.b.b.format);
2320
2321 if (format == V_028040_Z_INVALID) {
2322 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2323 }
2324 assert(format != V_028040_Z_INVALID);
2325
2326 s_offs = z_offs = rtex->resource.gpu_address;
2327 z_offs += rtex->surface.level[level].offset;
2328 s_offs += rtex->surface.stencil_level[level].offset;
2329
2330 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2331
2332 z_info = S_028040_FORMAT(format);
2333 if (rtex->resource.b.b.nr_samples > 1) {
2334 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2335 }
2336
2337 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2338 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2339 else
2340 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2341
2342 if (sctx->b.chip_class >= CIK) {
2343 switch (rtex->surface.level[level].mode) {
2344 case RADEON_SURF_MODE_2D:
2345 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2346 break;
2347 case RADEON_SURF_MODE_1D:
2348 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2349 case RADEON_SURF_MODE_LINEAR:
2350 default:
2351 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2352 break;
2353 }
2354 tile_split = rtex->surface.tile_split;
2355 stile_split = rtex->surface.stencil_tile_split;
2356 macro_aspect = rtex->surface.mtilea;
2357 bankw = rtex->surface.bankw;
2358 bankh = rtex->surface.bankh;
2359 tile_split = cik_tile_split(tile_split);
2360 stile_split = cik_tile_split(stile_split);
2361 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2362 bankw = cik_bank_wh(bankw);
2363 bankh = cik_bank_wh(bankh);
2364 nbanks = si_num_banks(sscreen, rtex);
2365 tile_mode_index = si_tile_mode_index(rtex, level, false);
2366 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2367
2368 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2369 S_02803C_PIPE_CONFIG(pipe_config) |
2370 S_02803C_BANK_WIDTH(bankw) |
2371 S_02803C_BANK_HEIGHT(bankh) |
2372 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2373 S_02803C_NUM_BANKS(nbanks);
2374 z_info |= S_028040_TILE_SPLIT(tile_split);
2375 s_info |= S_028044_TILE_SPLIT(stile_split);
2376 } else {
2377 tile_mode_index = si_tile_mode_index(rtex, level, false);
2378 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2379 tile_mode_index = si_tile_mode_index(rtex, level, true);
2380 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2381 }
2382
2383 /* HiZ aka depth buffer htile */
2384 /* use htile only for first level */
2385 if (rtex->htile_buffer && !level) {
2386 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2387 S_028040_ALLOW_EXPCLEAR(1);
2388
2389 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2390 /* Workaround: For a not yet understood reason, the
2391 * combination of MSAA, fast stencil clear and stencil
2392 * decompress messes with subsequent stencil buffer
2393 * uses. Problem was reproduced on Verde, Bonaire,
2394 * Tonga, and Carrizo.
2395 *
2396 * Disabling EXPCLEAR works around the problem.
2397 *
2398 * Check piglit's arb_texture_multisample-stencil-clear
2399 * test if you want to try changing this.
2400 */
2401 if (rtex->resource.b.b.nr_samples <= 1)
2402 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2403 } else
2404 /* Use all of the htile_buffer for depth if there's no stencil. */
2405 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2406
2407 uint64_t va = rtex->htile_buffer->gpu_address;
2408 db_htile_data_base = va >> 8;
2409 db_htile_surface = S_028ABC_FULL_CACHE(1);
2410 } else {
2411 db_htile_data_base = 0;
2412 db_htile_surface = 0;
2413 }
2414
2415 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2416
2417 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2418 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2419 surf->db_htile_data_base = db_htile_data_base;
2420 surf->db_depth_info = db_depth_info;
2421 surf->db_z_info = z_info;
2422 surf->db_stencil_info = s_info;
2423 surf->db_depth_base = z_offs >> 8;
2424 surf->db_stencil_base = s_offs >> 8;
2425 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2426 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2427 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2428 levelinfo->nblk_y) / 64 - 1);
2429 surf->db_htile_surface = db_htile_surface;
2430 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2431
2432 surf->depth_initialized = true;
2433 }
2434
2435 static void si_set_framebuffer_state(struct pipe_context *ctx,
2436 const struct pipe_framebuffer_state *state)
2437 {
2438 struct si_context *sctx = (struct si_context *)ctx;
2439 struct pipe_constant_buffer constbuf = {0};
2440 struct r600_surface *surf = NULL;
2441 struct r600_texture *rtex;
2442 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2443 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2444 int i;
2445
2446 /* Only flush TC when changing the framebuffer state, because
2447 * the only client not using TC that can change textures is
2448 * the framebuffer.
2449 *
2450 * Flush all CB and DB caches here because all buffers can be used
2451 * for write by both TC (with shader image stores) and CB/DB.
2452 */
2453 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2454 SI_CONTEXT_INV_GLOBAL_L2 |
2455 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2456 SI_CONTEXT_CS_PARTIAL_FLUSH;
2457
2458 /* Take the maximum of the old and new count. If the new count is lower,
2459 * dirtying is needed to disable the unbound colorbuffers.
2460 */
2461 sctx->framebuffer.dirty_cbufs |=
2462 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2463 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2464
2465 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2466
2467 sctx->framebuffer.spi_shader_col_format = 0;
2468 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2469 sctx->framebuffer.spi_shader_col_format_blend = 0;
2470 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2471 sctx->framebuffer.color_is_int8 = 0;
2472
2473 sctx->framebuffer.compressed_cb_mask = 0;
2474 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2475 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2476 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2477 util_format_is_pure_integer(state->cbufs[0]->format);
2478
2479 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2480 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2481
2482 for (i = 0; i < state->nr_cbufs; i++) {
2483 if (!state->cbufs[i])
2484 continue;
2485
2486 surf = (struct r600_surface*)state->cbufs[i];
2487 rtex = (struct r600_texture*)surf->base.texture;
2488
2489 if (!surf->color_initialized) {
2490 si_initialize_color_surface(sctx, surf);
2491 }
2492
2493 sctx->framebuffer.spi_shader_col_format |=
2494 surf->spi_shader_col_format << (i * 4);
2495 sctx->framebuffer.spi_shader_col_format_alpha |=
2496 surf->spi_shader_col_format_alpha << (i * 4);
2497 sctx->framebuffer.spi_shader_col_format_blend |=
2498 surf->spi_shader_col_format_blend << (i * 4);
2499 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2500 surf->spi_shader_col_format_blend_alpha << (i * 4);
2501
2502 if (surf->color_is_int8)
2503 sctx->framebuffer.color_is_int8 |= 1 << i;
2504
2505 if (rtex->fmask.size && rtex->cmask.size) {
2506 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2507 }
2508 r600_context_add_resource_size(ctx, surf->base.texture);
2509 }
2510 /* Set the second SPI format for possible dual-src blending. */
2511 if (i == 1 && surf) {
2512 sctx->framebuffer.spi_shader_col_format |=
2513 surf->spi_shader_col_format << (i * 4);
2514 sctx->framebuffer.spi_shader_col_format_alpha |=
2515 surf->spi_shader_col_format_alpha << (i * 4);
2516 sctx->framebuffer.spi_shader_col_format_blend |=
2517 surf->spi_shader_col_format_blend << (i * 4);
2518 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2519 surf->spi_shader_col_format_blend_alpha << (i * 4);
2520 }
2521
2522 if (state->zsbuf) {
2523 surf = (struct r600_surface*)state->zsbuf;
2524
2525 if (!surf->depth_initialized) {
2526 si_init_depth_surface(sctx, surf);
2527 }
2528 r600_context_add_resource_size(ctx, surf->base.texture);
2529 }
2530
2531 si_update_poly_offset_state(sctx);
2532 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2533 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2534
2535 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2536 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2537 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2538
2539 /* Set sample locations as fragment shader constants. */
2540 switch (sctx->framebuffer.nr_samples) {
2541 case 1:
2542 constbuf.user_buffer = sctx->b.sample_locations_1x;
2543 break;
2544 case 2:
2545 constbuf.user_buffer = sctx->b.sample_locations_2x;
2546 break;
2547 case 4:
2548 constbuf.user_buffer = sctx->b.sample_locations_4x;
2549 break;
2550 case 8:
2551 constbuf.user_buffer = sctx->b.sample_locations_8x;
2552 break;
2553 case 16:
2554 constbuf.user_buffer = sctx->b.sample_locations_16x;
2555 break;
2556 default:
2557 R600_ERR("Requested an invalid number of samples %i.\n",
2558 sctx->framebuffer.nr_samples);
2559 assert(0);
2560 }
2561 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2562 si_set_constant_buffer(sctx, &sctx->rw_buffers,
2563 SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2564
2565 /* Smoothing (only possible with nr_samples == 1) uses the same
2566 * sample locations as the MSAA it simulates.
2567 *
2568 * Therefore, don't update the sample locations when
2569 * transitioning from no AA to smoothing-equivalent AA, and
2570 * vice versa.
2571 */
2572 if ((sctx->framebuffer.nr_samples != 1 ||
2573 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2574 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2575 old_nr_samples != 1))
2576 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2577 }
2578 }
2579
2580 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2581 {
2582 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2583 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2584 unsigned i, nr_cbufs = state->nr_cbufs;
2585 struct r600_texture *tex = NULL;
2586 struct r600_surface *cb = NULL;
2587
2588 /* Colorbuffers. */
2589 for (i = 0; i < nr_cbufs; i++) {
2590 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2591 continue;
2592
2593 cb = (struct r600_surface*)state->cbufs[i];
2594 if (!cb) {
2595 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2596 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2597 continue;
2598 }
2599
2600 tex = (struct r600_texture *)cb->base.texture;
2601 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2602 &tex->resource, RADEON_USAGE_READWRITE,
2603 tex->surface.nsamples > 1 ?
2604 RADEON_PRIO_COLOR_BUFFER_MSAA :
2605 RADEON_PRIO_COLOR_BUFFER);
2606
2607 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2608 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2609 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2610 RADEON_PRIO_CMASK);
2611 }
2612
2613 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2614 sctx->b.chip_class >= VI ? 14 : 13);
2615 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2616 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2617 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2618 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2619 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2620 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2621 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2622 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2623 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2624 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2625 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2626 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2627 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2628
2629 if (sctx->b.chip_class >= VI)
2630 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2631 }
2632 /* set CB_COLOR1_INFO for possible dual-src blending */
2633 if (i == 1 && state->cbufs[0] &&
2634 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2635 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2636 cb->cb_color_info | tex->cb_color_info);
2637 i++;
2638 }
2639 for (; i < 8 ; i++)
2640 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2641 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2642
2643 /* ZS buffer. */
2644 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2645 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2646 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2647
2648 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2649 &rtex->resource, RADEON_USAGE_READWRITE,
2650 zb->base.texture->nr_samples > 1 ?
2651 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2652 RADEON_PRIO_DEPTH_BUFFER);
2653
2654 if (zb->db_htile_data_base) {
2655 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2656 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2657 RADEON_PRIO_HTILE);
2658 }
2659
2660 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2661 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2662
2663 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2664 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2665 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2666 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2667 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2668 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2669 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2670 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2671 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2672 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2673 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2674
2675 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2676 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2677 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2678
2679 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2680 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2681 zb->pa_su_poly_offset_db_fmt_cntl);
2682 } else if (sctx->framebuffer.dirty_zsbuf) {
2683 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2684 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2685 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2686 }
2687
2688 /* Framebuffer dimensions. */
2689 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2690 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2691 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2692
2693 sctx->framebuffer.dirty_cbufs = 0;
2694 sctx->framebuffer.dirty_zsbuf = false;
2695 }
2696
2697 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2698 struct r600_atom *atom)
2699 {
2700 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2701 unsigned nr_samples = sctx->framebuffer.nr_samples;
2702
2703 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2704 SI_NUM_SMOOTH_AA_SAMPLES);
2705 }
2706
2707 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2708 {
2709 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2710
2711 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2712 sctx->ps_iter_samples,
2713 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2714 }
2715
2716
2717 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2718 {
2719 struct si_context *sctx = (struct si_context *)ctx;
2720
2721 if (sctx->ps_iter_samples == min_samples)
2722 return;
2723
2724 sctx->ps_iter_samples = min_samples;
2725
2726 if (sctx->framebuffer.nr_samples > 1)
2727 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2728 }
2729
2730 /*
2731 * Samplers
2732 */
2733
2734 /**
2735 * Build the sampler view descriptor for a buffer texture.
2736 * @param state 256-bit descriptor; only the high 128 bits are filled in
2737 */
2738 void
2739 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2740 enum pipe_format format,
2741 unsigned first_element, unsigned last_element,
2742 uint32_t *state)
2743 {
2744 const struct util_format_description *desc;
2745 int first_non_void;
2746 uint64_t va;
2747 unsigned stride;
2748 unsigned num_records;
2749 unsigned num_format, data_format;
2750
2751 desc = util_format_description(format);
2752 first_non_void = util_format_get_first_non_void_channel(format);
2753 stride = desc->block.bits / 8;
2754 va = buf->gpu_address + first_element * stride;
2755 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2756 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2757
2758 num_records = last_element + 1 - first_element;
2759 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2760
2761 if (screen->b.chip_class >= VI)
2762 num_records *= stride;
2763
2764 state[4] = va;
2765 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2766 S_008F04_STRIDE(stride);
2767 state[6] = num_records;
2768 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2769 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2770 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2771 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2772 S_008F0C_NUM_FORMAT(num_format) |
2773 S_008F0C_DATA_FORMAT(data_format);
2774 }
2775
2776 /**
2777 * Build the sampler view descriptor for a texture.
2778 */
2779 void
2780 si_make_texture_descriptor(struct si_screen *screen,
2781 struct r600_texture *tex,
2782 bool sampler,
2783 enum pipe_texture_target target,
2784 enum pipe_format pipe_format,
2785 const unsigned char state_swizzle[4],
2786 unsigned base_level, unsigned first_level, unsigned last_level,
2787 unsigned first_layer, unsigned last_layer,
2788 unsigned width, unsigned height, unsigned depth,
2789 uint32_t *state,
2790 uint32_t *fmask_state)
2791 {
2792 struct pipe_resource *res = &tex->resource.b.b;
2793 const struct radeon_surf_level *surflevel = tex->surface.level;
2794 const struct util_format_description *desc;
2795 unsigned char swizzle[4];
2796 int first_non_void;
2797 unsigned num_format, data_format, type;
2798 uint32_t pitch;
2799 uint64_t va;
2800
2801 /* Texturing with separate depth and stencil. */
2802 if (tex->is_depth && !tex->is_flushing_texture) {
2803 switch (pipe_format) {
2804 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2805 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2806 break;
2807 case PIPE_FORMAT_X8Z24_UNORM:
2808 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2809 /* Z24 is always stored like this. */
2810 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2811 break;
2812 case PIPE_FORMAT_X24S8_UINT:
2813 case PIPE_FORMAT_S8X24_UINT:
2814 case PIPE_FORMAT_X32_S8X24_UINT:
2815 pipe_format = PIPE_FORMAT_S8_UINT;
2816 surflevel = tex->surface.stencil_level;
2817 break;
2818 default:;
2819 }
2820 }
2821
2822 desc = util_format_description(pipe_format);
2823
2824 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2825 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2826 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2827
2828 switch (pipe_format) {
2829 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2830 case PIPE_FORMAT_X24S8_UINT:
2831 case PIPE_FORMAT_X32_S8X24_UINT:
2832 case PIPE_FORMAT_X8Z24_UNORM:
2833 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2834 break;
2835 default:
2836 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2837 }
2838 } else {
2839 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2840 }
2841
2842 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2843
2844 switch (pipe_format) {
2845 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2846 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2847 break;
2848 default:
2849 if (first_non_void < 0) {
2850 if (util_format_is_compressed(pipe_format)) {
2851 switch (pipe_format) {
2852 case PIPE_FORMAT_DXT1_SRGB:
2853 case PIPE_FORMAT_DXT1_SRGBA:
2854 case PIPE_FORMAT_DXT3_SRGBA:
2855 case PIPE_FORMAT_DXT5_SRGBA:
2856 case PIPE_FORMAT_BPTC_SRGBA:
2857 case PIPE_FORMAT_ETC2_SRGB8:
2858 case PIPE_FORMAT_ETC2_SRGB8A1:
2859 case PIPE_FORMAT_ETC2_SRGBA8:
2860 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2861 break;
2862 case PIPE_FORMAT_RGTC1_SNORM:
2863 case PIPE_FORMAT_LATC1_SNORM:
2864 case PIPE_FORMAT_RGTC2_SNORM:
2865 case PIPE_FORMAT_LATC2_SNORM:
2866 case PIPE_FORMAT_ETC2_R11_SNORM:
2867 case PIPE_FORMAT_ETC2_RG11_SNORM:
2868 /* implies float, so use SNORM/UNORM to determine
2869 whether data is signed or not */
2870 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2871 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2872 break;
2873 default:
2874 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2875 break;
2876 }
2877 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2878 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2879 } else {
2880 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2881 }
2882 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2883 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2884 } else {
2885 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2886
2887 switch (desc->channel[first_non_void].type) {
2888 case UTIL_FORMAT_TYPE_FLOAT:
2889 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2890 break;
2891 case UTIL_FORMAT_TYPE_SIGNED:
2892 if (desc->channel[first_non_void].normalized)
2893 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2894 else if (desc->channel[first_non_void].pure_integer)
2895 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2896 else
2897 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2898 break;
2899 case UTIL_FORMAT_TYPE_UNSIGNED:
2900 if (desc->channel[first_non_void].normalized)
2901 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2902 else if (desc->channel[first_non_void].pure_integer)
2903 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2904 else
2905 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2906 }
2907 }
2908 }
2909
2910 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2911 if (data_format == ~0) {
2912 data_format = 0;
2913 }
2914
2915 if (!sampler &&
2916 (res->target == PIPE_TEXTURE_CUBE ||
2917 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2918 res->target == PIPE_TEXTURE_3D)) {
2919 /* For the purpose of shader images, treat cube maps and 3D
2920 * textures as 2D arrays. For 3D textures, the address
2921 * calculations for mipmaps are different, so we rely on the
2922 * caller to effectively disable mipmaps.
2923 */
2924 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2925
2926 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2927 } else {
2928 type = si_tex_dim(res->target, target, res->nr_samples);
2929 }
2930
2931 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2932 height = 1;
2933 depth = res->array_size;
2934 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2935 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2936 if (sampler || res->target != PIPE_TEXTURE_3D)
2937 depth = res->array_size;
2938 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2939 depth = res->array_size / 6;
2940
2941 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2942 va = tex->resource.gpu_address + surflevel[base_level].offset;
2943
2944 state[0] = va >> 8;
2945 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2946 S_008F14_DATA_FORMAT(data_format) |
2947 S_008F14_NUM_FORMAT(num_format));
2948 state[2] = (S_008F18_WIDTH(width - 1) |
2949 S_008F18_HEIGHT(height - 1));
2950 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2951 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2952 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2953 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2954 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2955 0 : first_level) |
2956 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2957 util_logbase2(res->nr_samples) :
2958 last_level) |
2959 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
2960 S_008F1C_POW2_PAD(res->last_level > 0) |
2961 S_008F1C_TYPE(type));
2962 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2963 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2964 S_008F24_LAST_ARRAY(last_layer));
2965
2966 if (tex->dcc_offset) {
2967 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2968
2969 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2970 state[7] = (tex->resource.gpu_address +
2971 tex->dcc_offset +
2972 surflevel[base_level].dcc_offset) >> 8;
2973 } else {
2974 state[6] = 0;
2975 state[7] = 0;
2976
2977 /* The last dword is unused by hw. The shader uses it to clear
2978 * bits in the first dword of sampler state.
2979 */
2980 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2981 if (first_level == last_level)
2982 state[7] = C_008F30_MAX_ANISO_RATIO;
2983 else
2984 state[7] = 0xffffffff;
2985 }
2986 }
2987
2988 /* Initialize the sampler view for FMASK. */
2989 if (tex->fmask.size) {
2990 uint32_t fmask_format;
2991
2992 va = tex->resource.gpu_address + tex->fmask.offset;
2993
2994 switch (res->nr_samples) {
2995 case 2:
2996 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2997 break;
2998 case 4:
2999 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3000 break;
3001 case 8:
3002 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3003 break;
3004 default:
3005 assert(0);
3006 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3007 }
3008
3009 fmask_state[0] = va >> 8;
3010 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3011 S_008F14_DATA_FORMAT(fmask_format) |
3012 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3013 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3014 S_008F18_HEIGHT(height - 1);
3015 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3016 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3017 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3018 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3019 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3020 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3021 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3022 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3023 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3024 S_008F24_LAST_ARRAY(last_layer);
3025 fmask_state[6] = 0;
3026 fmask_state[7] = 0;
3027 }
3028 }
3029
3030 /**
3031 * Create a sampler view.
3032 *
3033 * @param ctx context
3034 * @param texture texture
3035 * @param state sampler view template
3036 * @param width0 width0 override (for compressed textures as int)
3037 * @param height0 height0 override (for compressed textures as int)
3038 * @param force_level set the base address to the level (for compressed textures)
3039 */
3040 struct pipe_sampler_view *
3041 si_create_sampler_view_custom(struct pipe_context *ctx,
3042 struct pipe_resource *texture,
3043 const struct pipe_sampler_view *state,
3044 unsigned width0, unsigned height0,
3045 unsigned force_level)
3046 {
3047 struct si_context *sctx = (struct si_context*)ctx;
3048 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3049 struct r600_texture *tmp = (struct r600_texture*)texture;
3050 unsigned base_level, first_level, last_level;
3051 unsigned char state_swizzle[4];
3052 unsigned height, depth, width;
3053 unsigned last_layer = state->u.tex.last_layer;
3054
3055 if (!view)
3056 return NULL;
3057
3058 /* initialize base object */
3059 view->base = *state;
3060 view->base.texture = NULL;
3061 view->base.reference.count = 1;
3062 view->base.context = ctx;
3063
3064 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3065 if (!texture) {
3066 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3067 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3068 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3069 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3070 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3071 return &view->base;
3072 }
3073
3074 pipe_resource_reference(&view->base.texture, texture);
3075
3076 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3077 state->format == PIPE_FORMAT_S8X24_UINT ||
3078 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3079 state->format == PIPE_FORMAT_S8_UINT)
3080 view->is_stencil_sampler = true;
3081
3082 /* Buffer resource. */
3083 if (texture->target == PIPE_BUFFER) {
3084 si_make_buffer_descriptor(sctx->screen,
3085 (struct r600_resource *)texture,
3086 state->format,
3087 state->u.buf.first_element,
3088 state->u.buf.last_element,
3089 view->state);
3090
3091 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3092 return &view->base;
3093 }
3094
3095 state_swizzle[0] = state->swizzle_r;
3096 state_swizzle[1] = state->swizzle_g;
3097 state_swizzle[2] = state->swizzle_b;
3098 state_swizzle[3] = state->swizzle_a;
3099
3100 base_level = 0;
3101 first_level = state->u.tex.first_level;
3102 last_level = state->u.tex.last_level;
3103 width = width0;
3104 height = height0;
3105 depth = texture->depth0;
3106
3107 if (force_level) {
3108 assert(force_level == first_level &&
3109 force_level == last_level);
3110 base_level = force_level;
3111 first_level = 0;
3112 last_level = 0;
3113 width = u_minify(width, force_level);
3114 height = u_minify(height, force_level);
3115 depth = u_minify(depth, force_level);
3116 }
3117
3118 /* This is not needed if state trackers set last_layer correctly. */
3119 if (state->target == PIPE_TEXTURE_1D ||
3120 state->target == PIPE_TEXTURE_2D ||
3121 state->target == PIPE_TEXTURE_RECT ||
3122 state->target == PIPE_TEXTURE_CUBE)
3123 last_layer = state->u.tex.first_layer;
3124
3125 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3126 state->format, state_swizzle,
3127 base_level, first_level, last_level,
3128 state->u.tex.first_layer, last_layer,
3129 width, height, depth,
3130 view->state, view->fmask_state);
3131
3132 return &view->base;
3133 }
3134
3135 static struct pipe_sampler_view *
3136 si_create_sampler_view(struct pipe_context *ctx,
3137 struct pipe_resource *texture,
3138 const struct pipe_sampler_view *state)
3139 {
3140 return si_create_sampler_view_custom(ctx, texture, state,
3141 texture ? texture->width0 : 0,
3142 texture ? texture->height0 : 0, 0);
3143 }
3144
3145 static void si_sampler_view_destroy(struct pipe_context *ctx,
3146 struct pipe_sampler_view *state)
3147 {
3148 struct si_sampler_view *view = (struct si_sampler_view *)state;
3149
3150 if (state->texture && state->texture->target == PIPE_BUFFER)
3151 LIST_DELINIT(&view->list);
3152
3153 pipe_resource_reference(&state->texture, NULL);
3154 FREE(view);
3155 }
3156
3157 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3158 {
3159 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3160 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3161 (linear_filter &&
3162 (wrap == PIPE_TEX_WRAP_CLAMP ||
3163 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3164 }
3165
3166 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3167 {
3168 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3169 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3170
3171 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3172 state->border_color.ui[2] || state->border_color.ui[3]) &&
3173 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3174 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3175 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3176 }
3177
3178 static void *si_create_sampler_state(struct pipe_context *ctx,
3179 const struct pipe_sampler_state *state)
3180 {
3181 struct si_context *sctx = (struct si_context *)ctx;
3182 struct r600_common_screen *rscreen = sctx->b.screen;
3183 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3184 unsigned border_color_type, border_color_index = 0;
3185 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3186 : state->max_anisotropy;
3187 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3188
3189 if (!rstate) {
3190 return NULL;
3191 }
3192
3193 if (!sampler_state_needs_border_color(state))
3194 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3195 else if (state->border_color.f[0] == 0 &&
3196 state->border_color.f[1] == 0 &&
3197 state->border_color.f[2] == 0 &&
3198 state->border_color.f[3] == 0)
3199 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3200 else if (state->border_color.f[0] == 0 &&
3201 state->border_color.f[1] == 0 &&
3202 state->border_color.f[2] == 0 &&
3203 state->border_color.f[3] == 1)
3204 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3205 else if (state->border_color.f[0] == 1 &&
3206 state->border_color.f[1] == 1 &&
3207 state->border_color.f[2] == 1 &&
3208 state->border_color.f[3] == 1)
3209 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3210 else {
3211 int i;
3212
3213 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3214
3215 /* Check if the border has been uploaded already. */
3216 for (i = 0; i < sctx->border_color_count; i++)
3217 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3218 sizeof(state->border_color)) == 0)
3219 break;
3220
3221 if (i >= SI_MAX_BORDER_COLORS) {
3222 /* Getting 4096 unique border colors is very unlikely. */
3223 fprintf(stderr, "radeonsi: The border color table is full. "
3224 "Any new border colors will be just black. "
3225 "Please file a bug.\n");
3226 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3227 } else {
3228 if (i == sctx->border_color_count) {
3229 /* Upload a new border color. */
3230 memcpy(&sctx->border_color_table[i], &state->border_color,
3231 sizeof(state->border_color));
3232 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3233 &state->border_color,
3234 sizeof(state->border_color));
3235 sctx->border_color_count++;
3236 }
3237
3238 border_color_index = i;
3239 }
3240 }
3241
3242 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3243 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3244 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3245 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3246 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3247 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3248 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3249 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3250 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3251 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3252 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3253 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3254 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3255 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3256 S_008F38_MIP_POINT_PRECLAMP(1) |
3257 S_008F38_DISABLE_LSB_CEIL(1) |
3258 S_008F38_FILTER_PREC_FIX(1) |
3259 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3260 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3261 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3262 return rstate;
3263 }
3264
3265 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3266 {
3267 struct si_context *sctx = (struct si_context *)ctx;
3268
3269 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3270 return;
3271
3272 sctx->sample_mask.sample_mask = sample_mask;
3273 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3274 }
3275
3276 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3277 {
3278 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3279 unsigned mask = sctx->sample_mask.sample_mask;
3280
3281 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3282 radeon_emit(cs, mask | (mask << 16));
3283 radeon_emit(cs, mask | (mask << 16));
3284 }
3285
3286 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3287 {
3288 free(state);
3289 }
3290
3291 /*
3292 * Vertex elements & buffers
3293 */
3294
3295 static void *si_create_vertex_elements(struct pipe_context *ctx,
3296 unsigned count,
3297 const struct pipe_vertex_element *elements)
3298 {
3299 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3300 int i;
3301
3302 assert(count <= SI_MAX_ATTRIBS);
3303 if (!v)
3304 return NULL;
3305
3306 v->count = count;
3307 for (i = 0; i < count; ++i) {
3308 const struct util_format_description *desc;
3309 unsigned data_format, num_format;
3310 int first_non_void;
3311
3312 desc = util_format_description(elements[i].src_format);
3313 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3314 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3315 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3316
3317 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3318 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3319 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3320 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3321 S_008F0C_NUM_FORMAT(num_format) |
3322 S_008F0C_DATA_FORMAT(data_format);
3323 v->format_size[i] = desc->block.bits / 8;
3324 }
3325 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3326
3327 return v;
3328 }
3329
3330 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3331 {
3332 struct si_context *sctx = (struct si_context *)ctx;
3333 struct si_vertex_element *v = (struct si_vertex_element*)state;
3334
3335 sctx->vertex_elements = v;
3336 sctx->vertex_buffers_dirty = true;
3337 }
3338
3339 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3340 {
3341 struct si_context *sctx = (struct si_context *)ctx;
3342
3343 if (sctx->vertex_elements == state)
3344 sctx->vertex_elements = NULL;
3345 FREE(state);
3346 }
3347
3348 static void si_set_vertex_buffers(struct pipe_context *ctx,
3349 unsigned start_slot, unsigned count,
3350 const struct pipe_vertex_buffer *buffers)
3351 {
3352 struct si_context *sctx = (struct si_context *)ctx;
3353 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3354 int i;
3355
3356 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3357
3358 if (buffers) {
3359 for (i = 0; i < count; i++) {
3360 const struct pipe_vertex_buffer *src = buffers + i;
3361 struct pipe_vertex_buffer *dsti = dst + i;
3362
3363 pipe_resource_reference(&dsti->buffer, src->buffer);
3364 dsti->buffer_offset = src->buffer_offset;
3365 dsti->stride = src->stride;
3366 r600_context_add_resource_size(ctx, src->buffer);
3367 }
3368 } else {
3369 for (i = 0; i < count; i++) {
3370 pipe_resource_reference(&dst[i].buffer, NULL);
3371 }
3372 }
3373 sctx->vertex_buffers_dirty = true;
3374 }
3375
3376 static void si_set_index_buffer(struct pipe_context *ctx,
3377 const struct pipe_index_buffer *ib)
3378 {
3379 struct si_context *sctx = (struct si_context *)ctx;
3380
3381 if (ib) {
3382 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3383 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3384 r600_context_add_resource_size(ctx, ib->buffer);
3385 } else {
3386 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3387 }
3388 }
3389
3390 /*
3391 * Misc
3392 */
3393
3394 static void si_set_tess_state(struct pipe_context *ctx,
3395 const float default_outer_level[4],
3396 const float default_inner_level[2])
3397 {
3398 struct si_context *sctx = (struct si_context *)ctx;
3399 struct pipe_constant_buffer cb;
3400 float array[8];
3401
3402 memcpy(array, default_outer_level, sizeof(float) * 4);
3403 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3404
3405 cb.buffer = NULL;
3406 cb.user_buffer = NULL;
3407 cb.buffer_size = sizeof(array);
3408
3409 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3410 (void*)array, sizeof(array),
3411 &cb.buffer_offset);
3412
3413 si_set_constant_buffer(sctx, &sctx->rw_buffers,
3414 SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3415 pipe_resource_reference(&cb.buffer, NULL);
3416 }
3417
3418 static void si_texture_barrier(struct pipe_context *ctx)
3419 {
3420 struct si_context *sctx = (struct si_context *)ctx;
3421
3422 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3423 SI_CONTEXT_INV_GLOBAL_L2 |
3424 SI_CONTEXT_FLUSH_AND_INV_CB |
3425 SI_CONTEXT_CS_PARTIAL_FLUSH;
3426 }
3427
3428 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3429 {
3430 struct si_context *sctx = (struct si_context *)ctx;
3431
3432 /* Subsequent commands must wait for all shader invocations to
3433 * complete. */
3434 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3435 SI_CONTEXT_CS_PARTIAL_FLUSH;
3436
3437 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3438 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3439 SI_CONTEXT_INV_VMEM_L1;
3440
3441 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3442 PIPE_BARRIER_SHADER_BUFFER |
3443 PIPE_BARRIER_TEXTURE |
3444 PIPE_BARRIER_IMAGE |
3445 PIPE_BARRIER_STREAMOUT_BUFFER |
3446 PIPE_BARRIER_GLOBAL_BUFFER)) {
3447 /* As far as I can tell, L1 contents are written back to L2
3448 * automatically at end of shader, but the contents of other
3449 * L1 caches might still be stale. */
3450 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3451 }
3452
3453 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3454 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3455
3456 /* Indices are read through TC L2 since VI. */
3457 if (sctx->screen->b.chip_class <= CIK)
3458 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3459 }
3460
3461 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3462 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3463
3464 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3465 PIPE_BARRIER_FRAMEBUFFER |
3466 PIPE_BARRIER_INDIRECT_BUFFER)) {
3467 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3468 *
3469 * We need to make sure that TC L1 & L2 are written back to
3470 * memory, because neither CPU accesses nor CB fetches consider
3471 * TC, but there's no need to invalidate any TC cache lines. */
3472 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3473 }
3474 }
3475
3476 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3477 {
3478 struct pipe_blend_state blend;
3479
3480 memset(&blend, 0, sizeof(blend));
3481 blend.independent_blend_enable = true;
3482 blend.rt[0].colormask = 0xf;
3483 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3484 }
3485
3486 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3487 bool include_draw_vbo)
3488 {
3489 si_need_cs_space((struct si_context*)ctx);
3490 }
3491
3492 static void si_init_config(struct si_context *sctx);
3493
3494 void si_init_state_functions(struct si_context *sctx)
3495 {
3496 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3497 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3498 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3499 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3500 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3501
3502 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3503 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3504 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3505 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3506 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3507 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3508 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3509 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3510 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3511 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3512 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3513
3514 sctx->b.b.create_blend_state = si_create_blend_state;
3515 sctx->b.b.bind_blend_state = si_bind_blend_state;
3516 sctx->b.b.delete_blend_state = si_delete_blend_state;
3517 sctx->b.b.set_blend_color = si_set_blend_color;
3518
3519 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3520 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3521 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3522
3523 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3524 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3525 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3526
3527 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3528 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3529 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3530 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3531 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3532
3533 sctx->b.b.set_clip_state = si_set_clip_state;
3534 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3535
3536 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3537 sctx->b.b.get_sample_position = cayman_get_sample_position;
3538
3539 sctx->b.b.create_sampler_state = si_create_sampler_state;
3540 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3541
3542 sctx->b.b.create_sampler_view = si_create_sampler_view;
3543 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3544
3545 sctx->b.b.set_sample_mask = si_set_sample_mask;
3546
3547 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3548 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3549 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3550 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3551 sctx->b.b.set_index_buffer = si_set_index_buffer;
3552
3553 sctx->b.b.texture_barrier = si_texture_barrier;
3554 sctx->b.b.memory_barrier = si_memory_barrier;
3555 sctx->b.b.set_min_samples = si_set_min_samples;
3556 sctx->b.b.set_tess_state = si_set_tess_state;
3557
3558 sctx->b.b.set_active_query_state = si_set_active_query_state;
3559 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3560 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3561
3562 sctx->b.b.draw_vbo = si_draw_vbo;
3563
3564 if (sctx->b.chip_class >= CIK) {
3565 sctx->b.dma_copy = cik_sdma_copy;
3566 } else {
3567 sctx->b.dma_copy = si_dma_copy;
3568 }
3569
3570 si_init_config(sctx);
3571 }
3572
3573 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3574 struct r600_texture *rtex,
3575 struct radeon_bo_metadata *md)
3576 {
3577 struct si_screen *sscreen = (struct si_screen*)rscreen;
3578 struct pipe_resource *res = &rtex->resource.b.b;
3579 static const unsigned char swizzle[] = {
3580 PIPE_SWIZZLE_X,
3581 PIPE_SWIZZLE_Y,
3582 PIPE_SWIZZLE_Z,
3583 PIPE_SWIZZLE_W
3584 };
3585 uint32_t desc[8], i;
3586 bool is_array = util_resource_is_array_texture(res);
3587
3588 /* DRM 2.x.x doesn't support this. */
3589 if (rscreen->info.drm_major != 3)
3590 return;
3591
3592 assert(rtex->fmask.size == 0);
3593
3594 /* Metadata image format format version 1:
3595 * [0] = 1 (metadata format identifier)
3596 * [1] = (VENDOR_ID << 16) | PCI_ID
3597 * [2:9] = image descriptor for the whole resource
3598 * [2] is always 0, because the base address is cleared
3599 * [9] is the DCC offset bits [39:8] from the beginning of
3600 * the buffer
3601 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3602 */
3603
3604 md->metadata[0] = 1; /* metadata image format version 1 */
3605
3606 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3607 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3608
3609 si_make_texture_descriptor(sscreen, rtex, true,
3610 res->target, res->format,
3611 swizzle, 0, 0, res->last_level, 0,
3612 is_array ? res->array_size - 1 : 0,
3613 res->width0, res->height0, res->depth0,
3614 desc, NULL);
3615
3616 /* Clear the base address and set the relative DCC offset. */
3617 desc[0] = 0;
3618 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3619 desc[7] = rtex->dcc_offset >> 8;
3620
3621 /* Dwords [2:9] contain the image descriptor. */
3622 memcpy(&md->metadata[2], desc, sizeof(desc));
3623
3624 /* Dwords [10:..] contain the mipmap level offsets. */
3625 for (i = 0; i <= res->last_level; i++)
3626 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3627
3628 md->size_metadata = (11 + res->last_level) * 4;
3629 }
3630
3631 void si_init_screen_state_functions(struct si_screen *sscreen)
3632 {
3633 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3634 }
3635
3636 static void
3637 si_write_harvested_raster_configs(struct si_context *sctx,
3638 struct si_pm4_state *pm4,
3639 unsigned raster_config,
3640 unsigned raster_config_1)
3641 {
3642 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3643 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3644 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3645 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3646 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3647 unsigned rb_per_se = num_rb / num_se;
3648 unsigned se_mask[4];
3649 unsigned se;
3650
3651 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3652 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3653 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3654 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3655
3656 assert(num_se == 1 || num_se == 2 || num_se == 4);
3657 assert(sh_per_se == 1 || sh_per_se == 2);
3658 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3659
3660 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3661 * fields are for, so I'm leaving them as their default
3662 * values. */
3663
3664 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3665 (!se_mask[2] && !se_mask[3]))) {
3666 raster_config_1 &= C_028354_SE_PAIR_MAP;
3667
3668 if (!se_mask[0] && !se_mask[1]) {
3669 raster_config_1 |=
3670 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3671 } else {
3672 raster_config_1 |=
3673 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3674 }
3675 }
3676
3677 for (se = 0; se < num_se; se++) {
3678 unsigned raster_config_se = raster_config;
3679 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3680 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3681 int idx = (se / 2) * 2;
3682
3683 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3684 raster_config_se &= C_028350_SE_MAP;
3685
3686 if (!se_mask[idx]) {
3687 raster_config_se |=
3688 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3689 } else {
3690 raster_config_se |=
3691 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3692 }
3693 }
3694
3695 pkr0_mask &= rb_mask;
3696 pkr1_mask &= rb_mask;
3697 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3698 raster_config_se &= C_028350_PKR_MAP;
3699
3700 if (!pkr0_mask) {
3701 raster_config_se |=
3702 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3703 } else {
3704 raster_config_se |=
3705 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3706 }
3707 }
3708
3709 if (rb_per_se >= 2) {
3710 unsigned rb0_mask = 1 << (se * rb_per_se);
3711 unsigned rb1_mask = rb0_mask << 1;
3712
3713 rb0_mask &= rb_mask;
3714 rb1_mask &= rb_mask;
3715 if (!rb0_mask || !rb1_mask) {
3716 raster_config_se &= C_028350_RB_MAP_PKR0;
3717
3718 if (!rb0_mask) {
3719 raster_config_se |=
3720 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3721 } else {
3722 raster_config_se |=
3723 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3724 }
3725 }
3726
3727 if (rb_per_se > 2) {
3728 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3729 rb1_mask = rb0_mask << 1;
3730 rb0_mask &= rb_mask;
3731 rb1_mask &= rb_mask;
3732 if (!rb0_mask || !rb1_mask) {
3733 raster_config_se &= C_028350_RB_MAP_PKR1;
3734
3735 if (!rb0_mask) {
3736 raster_config_se |=
3737 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3738 } else {
3739 raster_config_se |=
3740 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3741 }
3742 }
3743 }
3744 }
3745
3746 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3747 if (sctx->b.chip_class < CIK)
3748 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3749 SE_INDEX(se) | SH_BROADCAST_WRITES |
3750 INSTANCE_BROADCAST_WRITES);
3751 else
3752 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3753 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3754 S_030800_INSTANCE_BROADCAST_WRITES(1));
3755 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3756 if (sctx->b.chip_class >= CIK)
3757 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3758 }
3759
3760 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3761 if (sctx->b.chip_class < CIK)
3762 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3763 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3764 INSTANCE_BROADCAST_WRITES);
3765 else
3766 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3767 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3768 S_030800_INSTANCE_BROADCAST_WRITES(1));
3769 }
3770
3771 static void si_init_config(struct si_context *sctx)
3772 {
3773 struct si_screen *sscreen = sctx->screen;
3774 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3775 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3776 unsigned raster_config, raster_config_1;
3777 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3778 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3779 int i;
3780
3781 if (!pm4)
3782 return;
3783
3784 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3785 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3786 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3787 si_pm4_cmd_end(pm4, false);
3788
3789 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3790 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3791
3792 /* FIXME calculate these values somehow ??? */
3793 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3794 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3795 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3796
3797 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3798 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3799
3800 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3801 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3802 if (sctx->b.chip_class < CIK)
3803 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3804 S_008A14_CLIP_VTX_REORDER_ENA(1));
3805
3806 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3807 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3808
3809 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3810
3811 for (i = 0; i < 16; i++) {
3812 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3813 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3814 }
3815
3816 switch (sctx->screen->b.family) {
3817 case CHIP_TAHITI:
3818 case CHIP_PITCAIRN:
3819 raster_config = 0x2a00126a;
3820 raster_config_1 = 0x00000000;
3821 break;
3822 case CHIP_VERDE:
3823 raster_config = 0x0000124a;
3824 raster_config_1 = 0x00000000;
3825 break;
3826 case CHIP_OLAND:
3827 raster_config = 0x00000082;
3828 raster_config_1 = 0x00000000;
3829 break;
3830 case CHIP_HAINAN:
3831 raster_config = 0x00000000;
3832 raster_config_1 = 0x00000000;
3833 break;
3834 case CHIP_BONAIRE:
3835 raster_config = 0x16000012;
3836 raster_config_1 = 0x00000000;
3837 break;
3838 case CHIP_HAWAII:
3839 raster_config = 0x3a00161a;
3840 raster_config_1 = 0x0000002e;
3841 break;
3842 case CHIP_FIJI:
3843 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3844 /* old kernels with old tiling config */
3845 raster_config = 0x16000012;
3846 raster_config_1 = 0x0000002a;
3847 } else {
3848 raster_config = 0x3a00161a;
3849 raster_config_1 = 0x0000002e;
3850 }
3851 break;
3852 case CHIP_POLARIS10:
3853 raster_config = 0x16000012;
3854 raster_config_1 = 0x0000002a;
3855 break;
3856 case CHIP_POLARIS11:
3857 raster_config = 0x16000012;
3858 raster_config_1 = 0x00000000;
3859 break;
3860 case CHIP_TONGA:
3861 raster_config = 0x16000012;
3862 raster_config_1 = 0x0000002a;
3863 break;
3864 case CHIP_ICELAND:
3865 raster_config = 0x00000002;
3866 raster_config_1 = 0x00000000;
3867 break;
3868 case CHIP_CARRIZO:
3869 raster_config = 0x00000002;
3870 raster_config_1 = 0x00000000;
3871 break;
3872 case CHIP_KAVERI:
3873 /* KV should be 0x00000002, but that causes problems with radeon */
3874 raster_config = 0x00000000; /* 0x00000002 */
3875 raster_config_1 = 0x00000000;
3876 break;
3877 case CHIP_KABINI:
3878 case CHIP_MULLINS:
3879 case CHIP_STONEY:
3880 raster_config = 0x00000000;
3881 raster_config_1 = 0x00000000;
3882 break;
3883 default:
3884 fprintf(stderr,
3885 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3886 raster_config = 0x00000000;
3887 raster_config_1 = 0x00000000;
3888 break;
3889 }
3890
3891 /* Always use the default config when all backends are enabled
3892 * (or when we failed to determine the enabled backends).
3893 */
3894 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3895 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3896 raster_config);
3897 if (sctx->b.chip_class >= CIK)
3898 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3899 raster_config_1);
3900 } else {
3901 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3902 }
3903
3904 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3905 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3906 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3907 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3908 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3909 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3910 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3911
3912 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3913 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3914 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3915 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3916 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3917 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3918 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3919 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3920 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3921 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3922 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3923
3924 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3925 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3926 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3927
3928 if (sctx->b.chip_class >= CIK) {
3929 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3930 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3931 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3932
3933 if (sscreen->b.info.num_good_compute_units /
3934 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3935 /* Too few available compute units per SH. Disallowing
3936 * VS to run on CU0 could hurt us more than late VS
3937 * allocation would help.
3938 *
3939 * LATE_ALLOC_VS = 2 is the highest safe number.
3940 */
3941 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3942 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3943 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3944 } else {
3945 /* Set LATE_ALLOC_VS == 31. It should be less than
3946 * the number of scratch waves. Limitations:
3947 * - VS can't execute on CU0.
3948 * - If HS writes outputs to LDS, LS can't execute on CU0.
3949 */
3950 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3951 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3952 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3953 }
3954
3955 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3956 }
3957
3958 if (sctx->b.chip_class >= VI) {
3959 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3960 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3961 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3962 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3963 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3964 }
3965
3966 if (sctx->b.family == CHIP_STONEY)
3967 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3968
3969 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3970 if (sctx->b.chip_class >= CIK)
3971 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3972 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3973 RADEON_PRIO_BORDER_COLORS);
3974
3975 si_pm4_upload_indirect_buffer(sctx, pm4);
3976 sctx->init_config = pm4;
3977 }