2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_math.h"
31 #include "util/u_pack_color.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "radeonsi_pipe.h"
34 #include "radeonsi_shader.h"
39 * inferred framebuffer and blender state
41 static void si_update_fb_blend_state(struct r600_context
*rctx
)
43 struct si_pm4_state
*pm4
;
44 struct si_state_blend
*blend
= rctx
->queued
.named
.blend
;
50 pm4
= CALLOC_STRUCT(si_pm4_state
);
54 mask
= (1ULL << ((unsigned)rctx
->framebuffer
.nr_cbufs
* 4)) - 1;
55 mask
&= blend
->cb_target_mask
;
56 si_pm4_set_reg(pm4
, R_028238_CB_TARGET_MASK
, mask
);
58 si_pm4_set_state(rctx
, fb_blend
, pm4
);
65 static uint32_t si_translate_blend_function(int blend_func
)
69 return V_028780_COMB_DST_PLUS_SRC
;
70 case PIPE_BLEND_SUBTRACT
:
71 return V_028780_COMB_SRC_MINUS_DST
;
72 case PIPE_BLEND_REVERSE_SUBTRACT
:
73 return V_028780_COMB_DST_MINUS_SRC
;
75 return V_028780_COMB_MIN_DST_SRC
;
77 return V_028780_COMB_MAX_DST_SRC
;
79 R600_ERR("Unknown blend function %d\n", blend_func
);
86 static uint32_t si_translate_blend_factor(int blend_fact
)
89 case PIPE_BLENDFACTOR_ONE
:
90 return V_028780_BLEND_ONE
;
91 case PIPE_BLENDFACTOR_SRC_COLOR
:
92 return V_028780_BLEND_SRC_COLOR
;
93 case PIPE_BLENDFACTOR_SRC_ALPHA
:
94 return V_028780_BLEND_SRC_ALPHA
;
95 case PIPE_BLENDFACTOR_DST_ALPHA
:
96 return V_028780_BLEND_DST_ALPHA
;
97 case PIPE_BLENDFACTOR_DST_COLOR
:
98 return V_028780_BLEND_DST_COLOR
;
99 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
100 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
101 case PIPE_BLENDFACTOR_CONST_COLOR
:
102 return V_028780_BLEND_CONSTANT_COLOR
;
103 case PIPE_BLENDFACTOR_CONST_ALPHA
:
104 return V_028780_BLEND_CONSTANT_ALPHA
;
105 case PIPE_BLENDFACTOR_ZERO
:
106 return V_028780_BLEND_ZERO
;
107 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
108 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
109 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
110 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
111 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
112 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
113 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
114 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
115 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
116 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
117 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
118 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
119 case PIPE_BLENDFACTOR_SRC1_COLOR
:
120 return V_028780_BLEND_SRC1_COLOR
;
121 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
122 return V_028780_BLEND_SRC1_ALPHA
;
123 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
124 return V_028780_BLEND_INV_SRC1_COLOR
;
125 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
126 return V_028780_BLEND_INV_SRC1_ALPHA
;
128 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
135 static void *si_create_blend_state(struct pipe_context
*ctx
,
136 const struct pipe_blend_state
*state
)
138 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
139 struct si_pm4_state
*pm4
= &blend
->pm4
;
141 uint32_t color_control
;
146 color_control
= S_028808_MODE(V_028808_CB_NORMAL
);
147 if (state
->logicop_enable
) {
148 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
150 color_control
|= S_028808_ROP3(0xcc);
152 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
154 si_pm4_set_reg(pm4
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, ~0);
155 si_pm4_set_reg(pm4
, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, ~0);
157 blend
->cb_target_mask
= 0;
158 for (int i
= 0; i
< 8; i
++) {
159 /* state->rt entries > 0 only written if independent blending */
160 const int j
= state
->independent_blend_enable
? i
: 0;
162 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
163 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
164 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
165 unsigned eqA
= state
->rt
[j
].alpha_func
;
166 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
167 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
169 unsigned blend_cntl
= 0;
171 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
172 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
174 if (!state
->rt
[j
].blend_enable
) {
175 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
179 blend_cntl
|= S_028780_ENABLE(1);
180 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
181 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
182 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
184 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
185 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
186 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
187 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
188 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
190 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
196 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
198 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
199 si_pm4_bind_state(rctx
, blend
, (struct si_state_blend
*)state
);
200 si_update_fb_blend_state(rctx
);
203 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
205 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
206 si_pm4_delete_state(rctx
, blend
, (struct si_state_blend
*)state
);
209 static void si_set_blend_color(struct pipe_context
*ctx
,
210 const struct pipe_blend_color
*state
)
212 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
213 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
218 si_pm4_set_reg(pm4
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
219 si_pm4_set_reg(pm4
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
220 si_pm4_set_reg(pm4
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
221 si_pm4_set_reg(pm4
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
223 si_pm4_set_state(rctx
, blend_color
, pm4
);
227 * Clipping, scissors and viewport
230 static void si_set_clip_state(struct pipe_context
*ctx
,
231 const struct pipe_clip_state
*state
)
233 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
234 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
239 for (int i
= 0; i
< 6; i
++) {
240 si_pm4_set_reg(pm4
, R_0285BC_PA_CL_UCP_0_X
+ i
* 16,
241 fui(state
->ucp
[i
][0]));
242 si_pm4_set_reg(pm4
, R_0285C0_PA_CL_UCP_0_Y
+ i
* 16,
243 fui(state
->ucp
[i
][1]));
244 si_pm4_set_reg(pm4
, R_0285C4_PA_CL_UCP_0_Z
+ i
* 16,
245 fui(state
->ucp
[i
][2]));
246 si_pm4_set_reg(pm4
, R_0285C8_PA_CL_UCP_0_W
+ i
* 16,
247 fui(state
->ucp
[i
][3]));
250 si_pm4_set_state(rctx
, clip
, pm4
);
253 static void si_set_scissor_state(struct pipe_context
*ctx
,
254 const struct pipe_scissor_state
*state
)
256 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
257 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
263 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
264 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
265 si_pm4_set_reg(pm4
, R_028210_PA_SC_CLIPRECT_0_TL
, tl
);
266 si_pm4_set_reg(pm4
, R_028214_PA_SC_CLIPRECT_0_BR
, br
);
267 si_pm4_set_reg(pm4
, R_028218_PA_SC_CLIPRECT_1_TL
, tl
);
268 si_pm4_set_reg(pm4
, R_02821C_PA_SC_CLIPRECT_1_BR
, br
);
269 si_pm4_set_reg(pm4
, R_028220_PA_SC_CLIPRECT_2_TL
, tl
);
270 si_pm4_set_reg(pm4
, R_028224_PA_SC_CLIPRECT_2_BR
, br
);
271 si_pm4_set_reg(pm4
, R_028228_PA_SC_CLIPRECT_3_TL
, tl
);
272 si_pm4_set_reg(pm4
, R_02822C_PA_SC_CLIPRECT_3_BR
, br
);
274 si_pm4_set_state(rctx
, scissor
, pm4
);
277 static void si_set_viewport_state(struct pipe_context
*ctx
,
278 const struct pipe_viewport_state
*state
)
280 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
281 struct si_state_viewport
*viewport
= CALLOC_STRUCT(si_state_viewport
);
282 struct si_pm4_state
*pm4
= &viewport
->pm4
;
284 if (viewport
== NULL
)
287 viewport
->viewport
= *state
;
288 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000);
289 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000);
290 si_pm4_set_reg(pm4
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
291 si_pm4_set_reg(pm4
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
292 si_pm4_set_reg(pm4
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
293 si_pm4_set_reg(pm4
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
294 si_pm4_set_reg(pm4
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
295 si_pm4_set_reg(pm4
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
296 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
298 si_pm4_set_state(rctx
, viewport
, viewport
);
302 * inferred state between framebuffer and rasterizer
304 static void si_update_fb_rs_state(struct r600_context
*rctx
)
306 struct si_state_rasterizer
*rs
= rctx
->queued
.named
.rasterizer
;
307 struct si_pm4_state
*pm4
;
308 unsigned offset_db_fmt_cntl
= 0, depth
;
311 if (!rs
|| !rctx
->framebuffer
.zsbuf
)
314 offset_units
= rctx
->queued
.named
.rasterizer
->offset_units
;
315 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
316 case PIPE_FORMAT_Z24X8_UNORM
:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
319 offset_units
*= 2.0f
;
321 case PIPE_FORMAT_Z32_FLOAT
:
322 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
324 offset_units
*= 1.0f
;
325 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
327 case PIPE_FORMAT_Z16_UNORM
:
329 offset_units
*= 4.0f
;
335 pm4
= CALLOC_STRUCT(si_pm4_state
);
336 /* FIXME some of those reg can be computed with cso */
337 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
338 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
339 fui(rctx
->queued
.named
.rasterizer
->offset_scale
));
340 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
341 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
342 fui(rctx
->queued
.named
.rasterizer
->offset_scale
));
343 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
344 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, offset_db_fmt_cntl
);
346 si_pm4_set_state(rctx
, fb_rs
, pm4
);
353 static uint32_t si_translate_fill(uint32_t func
)
356 case PIPE_POLYGON_MODE_FILL
:
357 return V_028814_X_DRAW_TRIANGLES
;
358 case PIPE_POLYGON_MODE_LINE
:
359 return V_028814_X_DRAW_LINES
;
360 case PIPE_POLYGON_MODE_POINT
:
361 return V_028814_X_DRAW_POINTS
;
364 return V_028814_X_DRAW_POINTS
;
368 static void *si_create_rs_state(struct pipe_context
*ctx
,
369 const struct pipe_rasterizer_state
*state
)
371 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
372 struct si_pm4_state
*pm4
= &rs
->pm4
;
374 unsigned prov_vtx
= 1, polygon_dual_mode
;
376 float psize_min
, psize_max
;
382 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
383 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
385 if (state
->flatshade_first
)
388 rs
->flatshade
= state
->flatshade
;
389 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
390 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
391 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
392 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
393 rs
->pa_su_sc_mode_cntl
=
394 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
395 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
396 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
397 S_028814_FACE(!state
->front_ccw
) |
398 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
399 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
400 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
401 S_028814_POLY_MODE(polygon_dual_mode
) |
402 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
403 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
));
404 rs
->pa_cl_clip_cntl
=
405 S_028810_PS_UCP_MODE(3) |
406 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
407 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
408 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
409 rs
->pa_cl_vs_out_cntl
=
410 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
411 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
);
413 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
416 rs
->offset_units
= state
->offset_units
;
417 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
419 /* XXX: Flat shading hangs the GPU */
420 tmp
= S_0286D4_FLAT_SHADE_ENA(0);
421 if (state
->sprite_coord_enable
) {
422 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
423 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
424 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
425 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
426 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
);
427 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
428 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
431 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
433 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000);
434 /* point size 12.4 fixed point */
435 tmp
= (unsigned)(state
->point_size
* 8.0);
436 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
438 if (state
->point_size_per_vertex
) {
439 psize_min
= util_get_min_point_size(state
);
442 /* Force the point size to be as if the vertex output was disabled. */
443 psize_min
= state
->point_size
;
444 psize_max
= state
->point_size
;
446 /* Divide by two, because 0.5 = 1 pixel. */
447 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
448 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
449 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
451 tmp
= (unsigned)state
->line_width
* 8;
452 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
453 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
454 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
456 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
, 0x00000400);
457 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
458 S_028BE4_PIX_CENTER(state
->gl_rasterization_rules
));
459 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000);
460 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000);
461 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000);
462 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000);
464 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
465 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
);
470 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
472 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
473 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
479 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
480 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
481 rctx
->pa_su_sc_mode_cntl
= rs
->pa_su_sc_mode_cntl
;
482 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
483 rctx
->pa_cl_vs_out_cntl
= rs
->pa_cl_vs_out_cntl
;
485 si_pm4_bind_state(rctx
, rasterizer
, rs
);
486 si_update_fb_rs_state(rctx
);
489 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
491 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
492 si_pm4_delete_state(rctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
496 * infeered state between dsa and stencil ref
498 static void si_update_dsa_stencil_ref(struct r600_context
*rctx
)
500 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
501 struct pipe_stencil_ref
*ref
= &rctx
->stencil_ref
;
502 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
507 si_pm4_set_reg(pm4
, R_028430_DB_STENCILREFMASK
,
508 S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
509 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
510 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]));
511 si_pm4_set_reg(pm4
, R_028434_DB_STENCILREFMASK_BF
,
512 S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
513 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
514 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]));
516 si_pm4_set_state(rctx
, dsa_stencil_ref
, pm4
);
519 static void si_set_pipe_stencil_ref(struct pipe_context
*ctx
,
520 const struct pipe_stencil_ref
*state
)
522 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
523 rctx
->stencil_ref
= *state
;
524 si_update_dsa_stencil_ref(rctx
);
532 static uint32_t si_translate_stencil_op(int s_op
)
535 case PIPE_STENCIL_OP_KEEP
:
536 return V_02842C_STENCIL_KEEP
;
537 case PIPE_STENCIL_OP_ZERO
:
538 return V_02842C_STENCIL_ZERO
;
539 case PIPE_STENCIL_OP_REPLACE
:
540 return V_02842C_STENCIL_REPLACE_TEST
;
541 case PIPE_STENCIL_OP_INCR
:
542 return V_02842C_STENCIL_ADD_CLAMP
;
543 case PIPE_STENCIL_OP_DECR
:
544 return V_02842C_STENCIL_SUB_CLAMP
;
545 case PIPE_STENCIL_OP_INCR_WRAP
:
546 return V_02842C_STENCIL_ADD_WRAP
;
547 case PIPE_STENCIL_OP_DECR_WRAP
:
548 return V_02842C_STENCIL_SUB_WRAP
;
549 case PIPE_STENCIL_OP_INVERT
:
550 return V_02842C_STENCIL_INVERT
;
552 R600_ERR("Unknown stencil op %d", s_op
);
559 static void *si_create_dsa_state(struct pipe_context
*ctx
,
560 const struct pipe_depth_stencil_alpha_state
*state
)
562 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
563 struct si_pm4_state
*pm4
= &dsa
->pm4
;
564 unsigned db_depth_control
, /* alpha_test_control, */ alpha_ref
;
565 unsigned db_render_override
, db_render_control
;
566 uint32_t db_stencil_control
= 0;
572 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
573 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
574 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
575 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
577 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
578 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
579 S_028800_ZFUNC(state
->depth
.func
);
582 if (state
->stencil
[0].enabled
) {
583 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
584 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
585 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
586 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
587 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
589 if (state
->stencil
[1].enabled
) {
590 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
591 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
592 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
593 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
594 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
599 //alpha_test_control = 0;
601 if (state
->alpha
.enabled
) {
602 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
603 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
604 alpha_ref
= fui(state
->alpha
.ref_value
);
606 dsa
->alpha_ref
= alpha_ref
;
609 db_render_control
= 0;
610 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
611 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
612 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
613 /* TODO db_render_override depends on query */
614 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, 0x00000000);
615 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, 0x00000000);
616 si_pm4_set_reg(pm4
, R_028028_DB_STENCIL_CLEAR
, 0x00000000);
617 si_pm4_set_reg(pm4
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000);
618 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
619 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
620 si_pm4_set_reg(pm4
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
621 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
622 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
623 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
624 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
625 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
626 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00);
627 dsa
->db_render_override
= db_render_override
;
632 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
634 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
635 struct si_state_dsa
*dsa
= state
;
640 si_pm4_bind_state(rctx
, dsa
, dsa
);
641 si_update_dsa_stencil_ref(rctx
);
644 rctx
->alpha_ref
= dsa
->alpha_ref
;
645 rctx
->alpha_ref_dirty
= true;
648 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
650 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
651 si_pm4_delete_state(rctx
, dsa
, (struct si_state_dsa
*)state
);
654 static void *si_create_db_flush_dsa(struct r600_context
*rctx
)
656 struct pipe_depth_stencil_alpha_state dsa
;
657 struct si_state_dsa
*state
;
659 memset(&dsa
, 0, sizeof(dsa
));
661 state
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
662 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
663 S_028000_DEPTH_COPY(1) |
664 S_028000_STENCIL_COPY(1) |
665 S_028000_COPY_CENTROID(1));
672 static uint32_t si_translate_colorformat(enum pipe_format format
)
676 case PIPE_FORMAT_A8_UNORM
:
677 case PIPE_FORMAT_A8_SNORM
:
678 case PIPE_FORMAT_A8_UINT
:
679 case PIPE_FORMAT_A8_SINT
:
680 case PIPE_FORMAT_I8_UNORM
:
681 case PIPE_FORMAT_I8_SNORM
:
682 case PIPE_FORMAT_I8_UINT
:
683 case PIPE_FORMAT_I8_SINT
:
684 case PIPE_FORMAT_L8_UNORM
:
685 case PIPE_FORMAT_L8_SNORM
:
686 case PIPE_FORMAT_L8_UINT
:
687 case PIPE_FORMAT_L8_SINT
:
688 case PIPE_FORMAT_L8_SRGB
:
689 case PIPE_FORMAT_R8_UNORM
:
690 case PIPE_FORMAT_R8_SNORM
:
691 case PIPE_FORMAT_R8_UINT
:
692 case PIPE_FORMAT_R8_SINT
:
693 return V_028C70_COLOR_8
;
695 /* 16-bit buffers. */
696 case PIPE_FORMAT_B5G6R5_UNORM
:
697 return V_028C70_COLOR_5_6_5
;
699 case PIPE_FORMAT_B5G5R5A1_UNORM
:
700 case PIPE_FORMAT_B5G5R5X1_UNORM
:
701 return V_028C70_COLOR_1_5_5_5
;
703 case PIPE_FORMAT_B4G4R4A4_UNORM
:
704 case PIPE_FORMAT_B4G4R4X4_UNORM
:
705 return V_028C70_COLOR_4_4_4_4
;
707 case PIPE_FORMAT_L8A8_UNORM
:
708 case PIPE_FORMAT_L8A8_SNORM
:
709 case PIPE_FORMAT_L8A8_UINT
:
710 case PIPE_FORMAT_L8A8_SINT
:
711 case PIPE_FORMAT_L8A8_SRGB
:
712 case PIPE_FORMAT_R8G8_SNORM
:
713 case PIPE_FORMAT_R8G8_UNORM
:
714 case PIPE_FORMAT_R8G8_UINT
:
715 case PIPE_FORMAT_R8G8_SINT
:
716 return V_028C70_COLOR_8_8
;
718 case PIPE_FORMAT_Z16_UNORM
:
719 case PIPE_FORMAT_R16_UNORM
:
720 case PIPE_FORMAT_R16_SNORM
:
721 case PIPE_FORMAT_R16_UINT
:
722 case PIPE_FORMAT_R16_SINT
:
723 case PIPE_FORMAT_R16_FLOAT
:
724 case PIPE_FORMAT_L16_UNORM
:
725 case PIPE_FORMAT_L16_SNORM
:
726 case PIPE_FORMAT_L16_FLOAT
:
727 case PIPE_FORMAT_I16_UNORM
:
728 case PIPE_FORMAT_I16_SNORM
:
729 case PIPE_FORMAT_I16_FLOAT
:
730 case PIPE_FORMAT_A16_UNORM
:
731 case PIPE_FORMAT_A16_SNORM
:
732 case PIPE_FORMAT_A16_FLOAT
:
733 return V_028C70_COLOR_16
;
735 /* 32-bit buffers. */
736 case PIPE_FORMAT_A8B8G8R8_SRGB
:
737 case PIPE_FORMAT_A8B8G8R8_UNORM
:
738 case PIPE_FORMAT_A8R8G8B8_UNORM
:
739 case PIPE_FORMAT_B8G8R8A8_SRGB
:
740 case PIPE_FORMAT_B8G8R8A8_UNORM
:
741 case PIPE_FORMAT_B8G8R8X8_UNORM
:
742 case PIPE_FORMAT_R8G8B8A8_SNORM
:
743 case PIPE_FORMAT_R8G8B8A8_UNORM
:
744 case PIPE_FORMAT_R8G8B8X8_UNORM
:
745 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
746 case PIPE_FORMAT_X8B8G8R8_UNORM
:
747 case PIPE_FORMAT_X8R8G8B8_UNORM
:
748 case PIPE_FORMAT_R8G8B8_UNORM
:
749 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
750 case PIPE_FORMAT_R8G8B8A8_USCALED
:
751 case PIPE_FORMAT_R8G8B8A8_SINT
:
752 case PIPE_FORMAT_R8G8B8A8_UINT
:
753 return V_028C70_COLOR_8_8_8_8
;
755 case PIPE_FORMAT_R10G10B10A2_UNORM
:
756 case PIPE_FORMAT_R10G10B10X2_SNORM
:
757 case PIPE_FORMAT_B10G10R10A2_UNORM
:
758 case PIPE_FORMAT_B10G10R10A2_UINT
:
759 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
760 return V_028C70_COLOR_2_10_10_10
;
762 case PIPE_FORMAT_Z24X8_UNORM
:
763 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
764 return V_028C70_COLOR_8_24
;
766 case PIPE_FORMAT_X8Z24_UNORM
:
767 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
768 return V_028C70_COLOR_24_8
;
770 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
771 return V_028C70_COLOR_X24_8_32_FLOAT
;
773 case PIPE_FORMAT_I32_FLOAT
:
774 case PIPE_FORMAT_L32_FLOAT
:
775 case PIPE_FORMAT_R32_FLOAT
:
776 case PIPE_FORMAT_A32_FLOAT
:
777 case PIPE_FORMAT_Z32_FLOAT
:
778 return V_028C70_COLOR_32
;
780 case PIPE_FORMAT_L16A16_UNORM
:
781 case PIPE_FORMAT_L16A16_SNORM
:
782 case PIPE_FORMAT_L16A16_FLOAT
:
783 case PIPE_FORMAT_R16G16_SSCALED
:
784 case PIPE_FORMAT_R16G16_UNORM
:
785 case PIPE_FORMAT_R16G16_SNORM
:
786 case PIPE_FORMAT_R16G16_UINT
:
787 case PIPE_FORMAT_R16G16_SINT
:
788 case PIPE_FORMAT_R16G16_FLOAT
:
789 return V_028C70_COLOR_16_16
;
791 case PIPE_FORMAT_R11G11B10_FLOAT
:
792 return V_028C70_COLOR_10_11_11
;
794 /* 64-bit buffers. */
795 case PIPE_FORMAT_R16G16B16_USCALED
:
796 case PIPE_FORMAT_R16G16B16_SSCALED
:
797 case PIPE_FORMAT_R16G16B16A16_UINT
:
798 case PIPE_FORMAT_R16G16B16A16_SINT
:
799 case PIPE_FORMAT_R16G16B16A16_USCALED
:
800 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
801 case PIPE_FORMAT_R16G16B16A16_UNORM
:
802 case PIPE_FORMAT_R16G16B16A16_SNORM
:
803 case PIPE_FORMAT_R16G16B16_FLOAT
:
804 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
805 return V_028C70_COLOR_16_16_16_16
;
807 case PIPE_FORMAT_L32A32_FLOAT
:
808 case PIPE_FORMAT_R32G32_FLOAT
:
809 case PIPE_FORMAT_R32G32_USCALED
:
810 case PIPE_FORMAT_R32G32_SSCALED
:
811 case PIPE_FORMAT_R32G32_SINT
:
812 case PIPE_FORMAT_R32G32_UINT
:
813 return V_028C70_COLOR_32_32
;
815 /* 128-bit buffers. */
816 case PIPE_FORMAT_R32G32B32A32_SNORM
:
817 case PIPE_FORMAT_R32G32B32A32_UNORM
:
818 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
819 case PIPE_FORMAT_R32G32B32A32_USCALED
:
820 case PIPE_FORMAT_R32G32B32A32_SINT
:
821 case PIPE_FORMAT_R32G32B32A32_UINT
:
822 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
823 return V_028C70_COLOR_32_32_32_32
;
826 case PIPE_FORMAT_UYVY
:
827 case PIPE_FORMAT_YUYV
:
828 /* 96-bit buffers. */
829 case PIPE_FORMAT_R32G32B32_FLOAT
:
831 case PIPE_FORMAT_L4A4_UNORM
:
832 case PIPE_FORMAT_R4A4_UNORM
:
833 case PIPE_FORMAT_A4R4_UNORM
:
835 return ~0U; /* Unsupported. */
839 static uint32_t si_translate_colorswap(enum pipe_format format
)
843 case PIPE_FORMAT_L4A4_UNORM
:
844 case PIPE_FORMAT_A4R4_UNORM
:
845 return V_028C70_SWAP_ALT
;
847 case PIPE_FORMAT_A8_UNORM
:
848 case PIPE_FORMAT_A8_SNORM
:
849 case PIPE_FORMAT_A8_UINT
:
850 case PIPE_FORMAT_A8_SINT
:
851 case PIPE_FORMAT_R4A4_UNORM
:
852 return V_028C70_SWAP_ALT_REV
;
853 case PIPE_FORMAT_I8_UNORM
:
854 case PIPE_FORMAT_I8_SNORM
:
855 case PIPE_FORMAT_L8_UNORM
:
856 case PIPE_FORMAT_L8_SNORM
:
857 case PIPE_FORMAT_I8_UINT
:
858 case PIPE_FORMAT_I8_SINT
:
859 case PIPE_FORMAT_L8_UINT
:
860 case PIPE_FORMAT_L8_SINT
:
861 case PIPE_FORMAT_L8_SRGB
:
862 case PIPE_FORMAT_R8_UNORM
:
863 case PIPE_FORMAT_R8_SNORM
:
864 case PIPE_FORMAT_R8_UINT
:
865 case PIPE_FORMAT_R8_SINT
:
866 return V_028C70_SWAP_STD
;
868 /* 16-bit buffers. */
869 case PIPE_FORMAT_B5G6R5_UNORM
:
870 return V_028C70_SWAP_STD_REV
;
872 case PIPE_FORMAT_B5G5R5A1_UNORM
:
873 case PIPE_FORMAT_B5G5R5X1_UNORM
:
874 return V_028C70_SWAP_ALT
;
876 case PIPE_FORMAT_B4G4R4A4_UNORM
:
877 case PIPE_FORMAT_B4G4R4X4_UNORM
:
878 return V_028C70_SWAP_ALT
;
880 case PIPE_FORMAT_Z16_UNORM
:
881 return V_028C70_SWAP_STD
;
883 case PIPE_FORMAT_L8A8_UNORM
:
884 case PIPE_FORMAT_L8A8_SNORM
:
885 case PIPE_FORMAT_L8A8_UINT
:
886 case PIPE_FORMAT_L8A8_SINT
:
887 case PIPE_FORMAT_L8A8_SRGB
:
888 return V_028C70_SWAP_ALT
;
889 case PIPE_FORMAT_R8G8_SNORM
:
890 case PIPE_FORMAT_R8G8_UNORM
:
891 case PIPE_FORMAT_R8G8_UINT
:
892 case PIPE_FORMAT_R8G8_SINT
:
893 return V_028C70_SWAP_STD
;
895 case PIPE_FORMAT_I16_UNORM
:
896 case PIPE_FORMAT_I16_SNORM
:
897 case PIPE_FORMAT_I16_FLOAT
:
898 case PIPE_FORMAT_L16_UNORM
:
899 case PIPE_FORMAT_L16_SNORM
:
900 case PIPE_FORMAT_L16_FLOAT
:
901 case PIPE_FORMAT_R16_UNORM
:
902 case PIPE_FORMAT_R16_SNORM
:
903 case PIPE_FORMAT_R16_UINT
:
904 case PIPE_FORMAT_R16_SINT
:
905 case PIPE_FORMAT_R16_FLOAT
:
906 return V_028C70_SWAP_STD
;
908 case PIPE_FORMAT_A16_UNORM
:
909 case PIPE_FORMAT_A16_SNORM
:
910 case PIPE_FORMAT_A16_FLOAT
:
911 return V_028C70_SWAP_ALT_REV
;
913 /* 32-bit buffers. */
914 case PIPE_FORMAT_A8B8G8R8_SRGB
:
915 return V_028C70_SWAP_STD_REV
;
916 case PIPE_FORMAT_B8G8R8A8_SRGB
:
917 return V_028C70_SWAP_ALT
;
919 case PIPE_FORMAT_B8G8R8A8_UNORM
:
920 case PIPE_FORMAT_B8G8R8X8_UNORM
:
921 return V_028C70_SWAP_ALT
;
923 case PIPE_FORMAT_A8R8G8B8_UNORM
:
924 case PIPE_FORMAT_X8R8G8B8_UNORM
:
925 return V_028C70_SWAP_ALT_REV
;
926 case PIPE_FORMAT_R8G8B8A8_SNORM
:
927 case PIPE_FORMAT_R8G8B8A8_UNORM
:
928 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
929 case PIPE_FORMAT_R8G8B8A8_USCALED
:
930 case PIPE_FORMAT_R8G8B8A8_SINT
:
931 case PIPE_FORMAT_R8G8B8A8_UINT
:
932 case PIPE_FORMAT_R8G8B8X8_UNORM
:
933 return V_028C70_SWAP_STD
;
935 case PIPE_FORMAT_A8B8G8R8_UNORM
:
936 case PIPE_FORMAT_X8B8G8R8_UNORM
:
937 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
938 return V_028C70_SWAP_STD_REV
;
940 case PIPE_FORMAT_Z24X8_UNORM
:
941 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
942 return V_028C70_SWAP_STD
;
944 case PIPE_FORMAT_X8Z24_UNORM
:
945 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
946 return V_028C70_SWAP_STD
;
948 case PIPE_FORMAT_R10G10B10A2_UNORM
:
949 case PIPE_FORMAT_R10G10B10X2_SNORM
:
950 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
951 return V_028C70_SWAP_STD
;
953 case PIPE_FORMAT_B10G10R10A2_UNORM
:
954 case PIPE_FORMAT_B10G10R10A2_UINT
:
955 return V_028C70_SWAP_ALT
;
957 case PIPE_FORMAT_R11G11B10_FLOAT
:
958 case PIPE_FORMAT_I32_FLOAT
:
959 case PIPE_FORMAT_L32_FLOAT
:
960 case PIPE_FORMAT_R32_FLOAT
:
961 case PIPE_FORMAT_R32_UINT
:
962 case PIPE_FORMAT_R32_SINT
:
963 case PIPE_FORMAT_Z32_FLOAT
:
964 case PIPE_FORMAT_R16G16_FLOAT
:
965 case PIPE_FORMAT_R16G16_UNORM
:
966 case PIPE_FORMAT_R16G16_SNORM
:
967 case PIPE_FORMAT_R16G16_UINT
:
968 case PIPE_FORMAT_R16G16_SINT
:
969 return V_028C70_SWAP_STD
;
971 case PIPE_FORMAT_L16A16_UNORM
:
972 case PIPE_FORMAT_L16A16_SNORM
:
973 case PIPE_FORMAT_L16A16_FLOAT
:
974 return V_028C70_SWAP_ALT
;
976 case PIPE_FORMAT_A32_FLOAT
:
977 return V_028C70_SWAP_ALT_REV
;
979 /* 64-bit buffers. */
980 case PIPE_FORMAT_R32G32_FLOAT
:
981 case PIPE_FORMAT_R32G32_UINT
:
982 case PIPE_FORMAT_R32G32_SINT
:
983 case PIPE_FORMAT_R16G16B16A16_UNORM
:
984 case PIPE_FORMAT_R16G16B16A16_SNORM
:
985 case PIPE_FORMAT_R16G16B16A16_USCALED
:
986 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
987 case PIPE_FORMAT_R16G16B16A16_UINT
:
988 case PIPE_FORMAT_R16G16B16A16_SINT
:
989 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
990 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
991 return V_028C70_SWAP_STD
;
993 case PIPE_FORMAT_L32A32_FLOAT
:
994 return V_028C70_SWAP_ALT
;
996 /* 128-bit buffers. */
997 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
998 case PIPE_FORMAT_R32G32B32A32_SNORM
:
999 case PIPE_FORMAT_R32G32B32A32_UNORM
:
1000 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
1001 case PIPE_FORMAT_R32G32B32A32_USCALED
:
1002 case PIPE_FORMAT_R32G32B32A32_SINT
:
1003 case PIPE_FORMAT_R32G32B32A32_UINT
:
1004 return V_028C70_SWAP_STD
;
1006 R600_ERR("unsupported colorswap format %d\n", format
);
1012 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1014 if (R600_BIG_ENDIAN
) {
1015 switch(colorformat
) {
1016 /* 8-bit buffers. */
1017 case V_028C70_COLOR_8
:
1018 return V_028C70_ENDIAN_NONE
;
1020 /* 16-bit buffers. */
1021 case V_028C70_COLOR_5_6_5
:
1022 case V_028C70_COLOR_1_5_5_5
:
1023 case V_028C70_COLOR_4_4_4_4
:
1024 case V_028C70_COLOR_16
:
1025 case V_028C70_COLOR_8_8
:
1026 return V_028C70_ENDIAN_8IN16
;
1028 /* 32-bit buffers. */
1029 case V_028C70_COLOR_8_8_8_8
:
1030 case V_028C70_COLOR_2_10_10_10
:
1031 case V_028C70_COLOR_8_24
:
1032 case V_028C70_COLOR_24_8
:
1033 case V_028C70_COLOR_16_16
:
1034 return V_028C70_ENDIAN_8IN32
;
1036 /* 64-bit buffers. */
1037 case V_028C70_COLOR_16_16_16_16
:
1038 return V_028C70_ENDIAN_8IN16
;
1040 case V_028C70_COLOR_32_32
:
1041 return V_028C70_ENDIAN_8IN32
;
1043 /* 128-bit buffers. */
1044 case V_028C70_COLOR_32_32_32_32
:
1045 return V_028C70_ENDIAN_8IN32
;
1047 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1050 return V_028C70_ENDIAN_NONE
;
1054 /* Returns the size in bits of the widest component of a CB format */
1055 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
1057 switch(colorformat
) {
1058 case V_028C70_COLOR_4_4_4_4
:
1061 case V_028C70_COLOR_1_5_5_5
:
1062 case V_028C70_COLOR_5_5_5_1
:
1065 case V_028C70_COLOR_5_6_5
:
1068 case V_028C70_COLOR_8
:
1069 case V_028C70_COLOR_8_8
:
1070 case V_028C70_COLOR_8_8_8_8
:
1073 case V_028C70_COLOR_10_10_10_2
:
1074 case V_028C70_COLOR_2_10_10_10
:
1077 case V_028C70_COLOR_10_11_11
:
1078 case V_028C70_COLOR_11_11_10
:
1081 case V_028C70_COLOR_16
:
1082 case V_028C70_COLOR_16_16
:
1083 case V_028C70_COLOR_16_16_16_16
:
1086 case V_028C70_COLOR_8_24
:
1087 case V_028C70_COLOR_24_8
:
1090 case V_028C70_COLOR_32
:
1091 case V_028C70_COLOR_32_32
:
1092 case V_028C70_COLOR_32_32_32_32
:
1093 case V_028C70_COLOR_X24_8_32_FLOAT
:
1097 assert(!"Unknown maximum component size");
1101 static uint32_t si_translate_dbformat(enum pipe_format format
)
1104 //case PIPE_FORMAT_Z16_UNORM:
1105 // return V_028040_Z_16;
1106 case PIPE_FORMAT_Z24X8_UNORM
:
1107 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1108 return V_028040_Z_24
; /* XXX no longer supported on SI */
1109 case PIPE_FORMAT_Z32_FLOAT
:
1110 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1111 return V_028040_Z_32_FLOAT
;
1118 * Texture translation
1121 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1122 enum pipe_format format
,
1123 const struct util_format_description
*desc
,
1126 boolean uniform
= TRUE
;
1129 /* Colorspace (return non-RGB formats directly). */
1130 switch (desc
->colorspace
) {
1131 /* Depth stencil formats */
1132 case UTIL_FORMAT_COLORSPACE_ZS
:
1134 case PIPE_FORMAT_Z16_UNORM
:
1135 return V_008F14_IMG_DATA_FORMAT_16
;
1136 case PIPE_FORMAT_X24S8_UINT
:
1137 case PIPE_FORMAT_Z24X8_UNORM
:
1138 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1139 return V_008F14_IMG_DATA_FORMAT_24_8
;
1140 case PIPE_FORMAT_S8X24_UINT
:
1141 case PIPE_FORMAT_X8Z24_UNORM
:
1142 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1143 return V_008F14_IMG_DATA_FORMAT_8_24
;
1144 case PIPE_FORMAT_S8_UINT
:
1145 return V_008F14_IMG_DATA_FORMAT_8
;
1146 case PIPE_FORMAT_Z32_FLOAT
:
1147 return V_008F14_IMG_DATA_FORMAT_32
;
1148 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1149 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1154 case UTIL_FORMAT_COLORSPACE_YUV
:
1155 goto out_unknown
; /* TODO */
1157 case UTIL_FORMAT_COLORSPACE_SRGB
:
1164 /* TODO compressed formats */
1166 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1167 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1168 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1169 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1172 /* R8G8Bx_SNORM - TODO CxV8U8 */
1174 /* See whether the components are of the same size. */
1175 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1176 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1179 /* Non-uniform formats. */
1181 switch(desc
->nr_channels
) {
1183 if (desc
->channel
[0].size
== 5 &&
1184 desc
->channel
[1].size
== 6 &&
1185 desc
->channel
[2].size
== 5) {
1186 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1190 if (desc
->channel
[0].size
== 5 &&
1191 desc
->channel
[1].size
== 5 &&
1192 desc
->channel
[2].size
== 5 &&
1193 desc
->channel
[3].size
== 1) {
1194 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1196 if (desc
->channel
[0].size
== 10 &&
1197 desc
->channel
[1].size
== 10 &&
1198 desc
->channel
[2].size
== 10 &&
1199 desc
->channel
[3].size
== 2) {
1200 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1207 if (first_non_void
< 0 || first_non_void
> 3)
1210 /* uniform formats */
1211 switch (desc
->channel
[first_non_void
].size
) {
1213 switch (desc
->nr_channels
) {
1214 #if 0 /* Not supported for render targets */
1216 return V_008F14_IMG_DATA_FORMAT_4_4
;
1219 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1223 switch (desc
->nr_channels
) {
1225 return V_008F14_IMG_DATA_FORMAT_8
;
1227 return V_008F14_IMG_DATA_FORMAT_8_8
;
1229 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1233 switch (desc
->nr_channels
) {
1235 return V_008F14_IMG_DATA_FORMAT_16
;
1237 return V_008F14_IMG_DATA_FORMAT_16_16
;
1239 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1243 switch (desc
->nr_channels
) {
1245 return V_008F14_IMG_DATA_FORMAT_32
;
1247 return V_008F14_IMG_DATA_FORMAT_32_32
;
1248 #if 0 /* Not supported for render targets */
1250 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1253 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1258 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1262 static unsigned si_tex_wrap(unsigned wrap
)
1266 case PIPE_TEX_WRAP_REPEAT
:
1267 return V_008F30_SQ_TEX_WRAP
;
1268 case PIPE_TEX_WRAP_CLAMP
:
1269 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1270 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1271 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1272 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1273 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1274 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1275 return V_008F30_SQ_TEX_MIRROR
;
1276 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1277 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1278 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1279 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1280 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1281 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1285 static unsigned si_tex_filter(unsigned filter
)
1289 case PIPE_TEX_FILTER_NEAREST
:
1290 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1291 case PIPE_TEX_FILTER_LINEAR
:
1292 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1296 static unsigned si_tex_mipfilter(unsigned filter
)
1299 case PIPE_TEX_MIPFILTER_NEAREST
:
1300 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1301 case PIPE_TEX_MIPFILTER_LINEAR
:
1302 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1304 case PIPE_TEX_MIPFILTER_NONE
:
1305 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1309 static unsigned si_tex_compare(unsigned compare
)
1313 case PIPE_FUNC_NEVER
:
1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1315 case PIPE_FUNC_LESS
:
1316 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1317 case PIPE_FUNC_EQUAL
:
1318 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1319 case PIPE_FUNC_LEQUAL
:
1320 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1321 case PIPE_FUNC_GREATER
:
1322 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1323 case PIPE_FUNC_NOTEQUAL
:
1324 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1325 case PIPE_FUNC_GEQUAL
:
1326 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1327 case PIPE_FUNC_ALWAYS
:
1328 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1332 static unsigned si_tex_dim(unsigned dim
)
1336 case PIPE_TEXTURE_1D
:
1337 return V_008F1C_SQ_RSRC_IMG_1D
;
1338 case PIPE_TEXTURE_1D_ARRAY
:
1339 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1340 case PIPE_TEXTURE_2D
:
1341 case PIPE_TEXTURE_RECT
:
1342 return V_008F1C_SQ_RSRC_IMG_2D
;
1343 case PIPE_TEXTURE_2D_ARRAY
:
1344 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1345 case PIPE_TEXTURE_3D
:
1346 return V_008F1C_SQ_RSRC_IMG_3D
;
1347 case PIPE_TEXTURE_CUBE
:
1348 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1353 * Format support testing
1356 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1358 return si_translate_texformat(screen
, format
, util_format_description(format
),
1359 util_format_get_first_non_void_channel(format
)) != ~0U;
1362 static uint32_t si_translate_vertexformat(struct pipe_screen
*screen
,
1363 enum pipe_format format
,
1364 const struct util_format_description
*desc
,
1367 unsigned type
= desc
->channel
[first_non_void
].type
;
1370 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1371 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1373 /* See whether the components are of the same size. */
1374 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1375 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1376 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1379 switch (desc
->channel
[first_non_void
].size
) {
1381 switch (desc
->nr_channels
) {
1383 return V_008F0C_BUF_DATA_FORMAT_8
;
1385 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1388 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1392 switch (desc
->nr_channels
) {
1394 return V_008F0C_BUF_DATA_FORMAT_16
;
1396 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1399 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1403 if (type
!= UTIL_FORMAT_TYPE_FLOAT
)
1404 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1406 switch (desc
->nr_channels
) {
1408 return V_008F0C_BUF_DATA_FORMAT_32
;
1410 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1412 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1414 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1419 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1422 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1424 const struct util_format_description
*desc
;
1426 unsigned data_format
;
1428 desc
= util_format_description(format
);
1429 first_non_void
= util_format_get_first_non_void_channel(format
);
1430 data_format
= si_translate_vertexformat(screen
, format
, desc
, first_non_void
);
1431 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1434 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1436 return si_translate_colorformat(format
) != ~0U &&
1437 si_translate_colorswap(format
) != ~0U;
1440 static bool si_is_zs_format_supported(enum pipe_format format
)
1442 return si_translate_dbformat(format
) != ~0U;
1445 bool si_is_format_supported(struct pipe_screen
*screen
,
1446 enum pipe_format format
,
1447 enum pipe_texture_target target
,
1448 unsigned sample_count
,
1451 unsigned retval
= 0;
1453 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1454 R600_ERR("r600: unsupported texture type %d\n", target
);
1458 if (!util_format_is_supported(format
, usage
))
1462 if (sample_count
> 1)
1465 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
1466 si_is_sampler_format_supported(screen
, format
)) {
1467 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1470 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1471 PIPE_BIND_DISPLAY_TARGET
|
1473 PIPE_BIND_SHARED
)) &&
1474 si_is_colorbuffer_format_supported(format
)) {
1476 (PIPE_BIND_RENDER_TARGET
|
1477 PIPE_BIND_DISPLAY_TARGET
|
1482 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1483 si_is_zs_format_supported(format
)) {
1484 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1487 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1488 si_is_vertex_format_supported(screen
, format
)) {
1489 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1492 if (usage
& PIPE_BIND_TRANSFER_READ
)
1493 retval
|= PIPE_BIND_TRANSFER_READ
;
1494 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1495 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1497 return retval
== usage
;
1501 * framebuffer handling
1504 static void si_cb(struct r600_context
*rctx
, struct si_pm4_state
*pm4
,
1505 const struct pipe_framebuffer_state
*state
, int cb
)
1507 struct r600_resource_texture
*rtex
;
1508 struct r600_surface
*surf
;
1509 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1510 unsigned pitch
, slice
;
1511 unsigned color_info
, color_attrib
;
1512 unsigned format
, swap
, ntype
, endian
;
1515 const struct util_format_description
*desc
;
1517 unsigned blend_clamp
= 0, blend_bypass
= 0;
1518 unsigned max_comp_size
;
1520 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1521 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1522 blocksize
= util_format_get_blocksize(rtex
->real_format
);
1525 rctx
->have_depth_fb
= TRUE
;
1527 if (rtex
->depth
&& !rtex
->is_flushing_texture
) {
1528 r600_texture_depth_flush(&rctx
->context
, state
->cbufs
[cb
]->texture
, TRUE
);
1529 rtex
= rtex
->flushed_depth_texture
;
1532 offset
= rtex
->surface
.level
[level
].offset
;
1533 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1534 offset
+= rtex
->surface
.level
[level
].slice_size
*
1535 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1537 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1538 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1543 color_attrib
= S_028C74_TILE_MODE_INDEX(8);
1544 switch (rtex
->surface
.level
[level
].mode
) {
1545 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1546 color_attrib
= S_028C74_TILE_MODE_INDEX(8);
1548 case RADEON_SURF_MODE_1D
:
1549 color_attrib
= S_028C74_TILE_MODE_INDEX(9);
1551 case RADEON_SURF_MODE_2D
:
1552 if (rtex
->resource
.b
.b
.bind
& PIPE_BIND_SCANOUT
) {
1553 switch (blocksize
) {
1555 color_attrib
= S_028C74_TILE_MODE_INDEX(10);
1558 color_attrib
= S_028C74_TILE_MODE_INDEX(11);
1561 color_attrib
= S_028C74_TILE_MODE_INDEX(12);
1565 } else switch (blocksize
) {
1567 color_attrib
= S_028C74_TILE_MODE_INDEX(14);
1570 color_attrib
= S_028C74_TILE_MODE_INDEX(15);
1573 color_attrib
= S_028C74_TILE_MODE_INDEX(16);
1576 color_attrib
= S_028C74_TILE_MODE_INDEX(17);
1579 color_attrib
= S_028C74_TILE_MODE_INDEX(13);
1584 desc
= util_format_description(surf
->base
.format
);
1585 for (i
= 0; i
< 4; i
++) {
1586 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1590 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1591 ntype
= V_028C70_NUMBER_FLOAT
;
1593 ntype
= V_028C70_NUMBER_UNORM
;
1594 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1595 ntype
= V_028C70_NUMBER_SRGB
;
1596 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1597 if (desc
->channel
[i
].normalized
)
1598 ntype
= V_028C70_NUMBER_SNORM
;
1599 else if (desc
->channel
[i
].pure_integer
)
1600 ntype
= V_028C70_NUMBER_SINT
;
1601 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1602 if (desc
->channel
[i
].normalized
)
1603 ntype
= V_028C70_NUMBER_UNORM
;
1604 else if (desc
->channel
[i
].pure_integer
)
1605 ntype
= V_028C70_NUMBER_UINT
;
1609 format
= si_translate_colorformat(surf
->base
.format
);
1610 swap
= si_translate_colorswap(surf
->base
.format
);
1611 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1612 endian
= V_028C70_ENDIAN_NONE
;
1614 endian
= si_colorformat_endian_swap(format
);
1617 /* blend clamp should be set for all NORM/SRGB types */
1618 if (ntype
== V_028C70_NUMBER_UNORM
||
1619 ntype
== V_028C70_NUMBER_SNORM
||
1620 ntype
== V_028C70_NUMBER_SRGB
)
1623 /* set blend bypass according to docs if SINT/UINT or
1624 8/24 COLOR variants */
1625 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1626 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1627 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1632 color_info
= S_028C70_FORMAT(format
) |
1633 S_028C70_COMP_SWAP(swap
) |
1634 S_028C70_BLEND_CLAMP(blend_clamp
) |
1635 S_028C70_BLEND_BYPASS(blend_bypass
) |
1636 S_028C70_NUMBER_TYPE(ntype
) |
1637 S_028C70_ENDIAN(endian
);
1639 rctx
->alpha_ref_dirty
= true;
1641 offset
+= r600_resource_va(rctx
->context
.screen
, state
->cbufs
[cb
]->texture
);
1644 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1645 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1646 si_pm4_set_reg(pm4
, R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C, offset
);
1647 si_pm4_set_reg(pm4
, R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C, S_028C64_TILE_MAX(pitch
));
1648 si_pm4_set_reg(pm4
, R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C, S_028C68_TILE_MAX(slice
));
1650 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1651 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C, 0x00000000);
1653 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1654 S_028C6C_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1655 S_028C6C_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
));
1657 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C, color_info
);
1658 si_pm4_set_reg(pm4
, R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C, color_attrib
);
1660 /* Determine pixel shader export format */
1661 max_comp_size
= si_colorformat_max_comp_size(format
);
1662 if (ntype
== V_028C70_NUMBER_SRGB
||
1663 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
1664 max_comp_size
<= 10) ||
1665 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
1666 rctx
->export_16bpc
|= 1 << cb
;
1667 rctx
->spi_shader_col_format
|= V_028714_SPI_SHADER_FP16_ABGR
<< (4 * cb
);
1669 rctx
->spi_shader_col_format
|= V_028714_SPI_SHADER_32_ABGR
<< (4 * cb
);
1672 static void si_db(struct r600_context
*rctx
, struct si_pm4_state
*pm4
,
1673 const struct pipe_framebuffer_state
*state
)
1675 struct r600_resource_texture
*rtex
;
1676 struct r600_surface
*surf
;
1677 unsigned level
, pitch
, slice
, format
;
1678 uint32_t z_info
, s_info
;
1679 uint64_t z_offs
, s_offs
;
1681 if (state
->zsbuf
== NULL
) {
1682 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, 0);
1683 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, 0);
1687 surf
= (struct r600_surface
*)state
->zsbuf
;
1688 level
= surf
->base
.u
.tex
.level
;
1689 rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1691 format
= si_translate_dbformat(rtex
->real_format
);
1693 z_offs
= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1694 z_offs
+= rtex
->surface
.level
[level
].offset
;
1696 s_offs
= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1697 s_offs
+= rtex
->surface
.stencil_offset
;
1698 z_offs
+= rtex
->surface
.level
[level
].offset
/ 4;
1703 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1704 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1709 z_info
= S_028040_FORMAT(format
);
1710 s_info
= S_028044_FORMAT(1);
1712 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_1D
) {
1713 z_info
|= S_028040_TILE_MODE_INDEX(4);
1714 s_info
|= S_028044_TILE_MODE_INDEX(4);
1716 } else if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_2D
) {
1719 z_info
|= S_028040_TILE_MODE_INDEX(5);
1720 s_info
|= S_028044_TILE_MODE_INDEX(5);
1723 case V_028040_Z_32_FLOAT
:
1724 z_info
|= S_028040_TILE_MODE_INDEX(6);
1725 s_info
|= S_028044_TILE_MODE_INDEX(6);
1728 z_info
|= S_028040_TILE_MODE_INDEX(7);
1729 s_info
|= S_028044_TILE_MODE_INDEX(7);
1733 R600_ERR("Invalid DB tiling mode %d!\n",
1734 rtex
->surface
.level
[level
].mode
);
1735 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, 0);
1736 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, 0);
1740 si_pm4_set_reg(pm4
, R_028008_DB_DEPTH_VIEW
,
1741 S_028008_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1742 S_028008_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
));
1744 si_pm4_set_reg(pm4
, R_02803C_DB_DEPTH_INFO
, 0x1);
1745 if (format
!= ~0U) {
1746 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, z_info
);
1749 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, 0);
1752 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1753 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, s_info
);
1755 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, 0);
1758 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1759 si_pm4_set_reg(pm4
, R_028048_DB_Z_READ_BASE
, z_offs
);
1760 si_pm4_set_reg(pm4
, R_02804C_DB_STENCIL_READ_BASE
, s_offs
);
1761 si_pm4_set_reg(pm4
, R_028050_DB_Z_WRITE_BASE
, z_offs
);
1762 si_pm4_set_reg(pm4
, R_028054_DB_STENCIL_WRITE_BASE
, s_offs
);
1764 si_pm4_set_reg(pm4
, R_028058_DB_DEPTH_SIZE
, S_028058_PITCH_TILE_MAX(pitch
));
1765 si_pm4_set_reg(pm4
, R_02805C_DB_DEPTH_SLICE
, S_02805C_SLICE_TILE_MAX(slice
));
1768 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
1769 const struct pipe_framebuffer_state
*state
)
1771 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1772 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
1773 uint32_t shader_mask
, tl
, br
;
1774 int tl_x
, tl_y
, br_x
, br_y
;
1779 si_pm4_inval_fb_cache(pm4
, state
->nr_cbufs
);
1782 si_pm4_inval_zsbuf_cache(pm4
);
1784 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1787 rctx
->have_depth_fb
= 0;
1788 rctx
->export_16bpc
= 0;
1789 rctx
->spi_shader_col_format
= 0;
1790 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1791 si_cb(rctx
, pm4
, state
, i
);
1793 assert(!(rctx
->export_16bpc
& ~0xff));
1794 si_db(rctx
, pm4
, state
);
1797 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1798 shader_mask
|= 0xf << (i
* 4);
1802 br_x
= state
->width
;
1803 br_y
= state
->height
;
1804 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1805 /* EG hw workaround */
1810 /* cayman hw workaround */
1811 if (rctx
->chip_class
== CAYMAN
) {
1812 if (br_x
== 1 && br_y
== 1)
1816 tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1817 br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1819 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
);
1820 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
);
1821 si_pm4_set_reg(pm4
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
1822 si_pm4_set_reg(pm4
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
1823 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
);
1824 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
);
1825 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
);
1826 si_pm4_set_reg(pm4
, R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
);
1827 si_pm4_set_reg(pm4
, R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000);
1828 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
1829 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, shader_mask
);
1830 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
1831 rctx
->spi_shader_col_format
);
1832 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
, 0x00000000);
1834 si_pm4_set_state(rctx
, framebuffer
, pm4
);
1835 si_update_fb_rs_state(rctx
);
1836 si_update_fb_blend_state(rctx
);
1843 /* Compute the key for the hw shader variant */
1844 static INLINE
unsigned si_shader_selector_key(struct pipe_context
*ctx
,
1845 struct si_pipe_shader_selector
*sel
)
1847 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1850 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
1851 if (sel
->fs_write_all
)
1852 key
|= rctx
->framebuffer
.nr_cbufs
;
1853 key
|= rctx
->export_16bpc
<< 4;
1854 /*if (rctx->queued.named.rasterizer)
1855 key |= rctx->queued.named.rasterizer->flatshade << 12;*/
1856 /*key |== rctx->two_side << 13;*/
1862 /* Select the hw shader variant depending on the current state.
1863 * (*dirty) is set to 1 if current variant was changed */
1864 int si_shader_select(struct pipe_context
*ctx
,
1865 struct si_pipe_shader_selector
*sel
,
1869 struct si_pipe_shader
* shader
= NULL
;
1872 key
= si_shader_selector_key(ctx
, sel
);
1874 /* Check if we don't need to change anything.
1875 * This path is also used for most shaders that don't need multiple
1876 * variants, it will cost just a computation of the key and this
1878 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
1882 /* lookup if we have other variants in the list */
1883 if (sel
->num_shaders
> 1) {
1884 struct si_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
1886 while (c
&& c
->key
!= key
) {
1888 c
= c
->next_variant
;
1892 p
->next_variant
= c
->next_variant
;
1897 if (unlikely(!shader
)) {
1898 shader
= CALLOC(1, sizeof(struct si_pipe_shader
));
1899 shader
->selector
= sel
;
1901 r
= si_pipe_shader_create(ctx
, shader
);
1903 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
1905 sel
->current
= NULL
;
1909 /* We don't know the value of fs_write_all property until we built
1910 * at least one variant, so we may need to recompute the key (include
1911 * rctx->framebuffer.nr_cbufs) after building first variant. */
1912 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
1913 sel
->num_shaders
== 0 &&
1914 shader
->shader
.fs_write_all
) {
1915 sel
->fs_write_all
= 1;
1916 key
= si_shader_selector_key(ctx
, sel
);
1926 shader
->next_variant
= sel
->current
;
1927 sel
->current
= shader
;
1932 static void *si_create_shader_state(struct pipe_context
*ctx
,
1933 const struct pipe_shader_state
*state
,
1934 unsigned pipe_shader_type
)
1936 struct si_pipe_shader_selector
*sel
= CALLOC_STRUCT(si_pipe_shader_selector
);
1939 sel
->type
= pipe_shader_type
;
1940 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1941 sel
->so
= state
->stream_output
;
1943 r
= si_shader_select(ctx
, sel
, NULL
);
1952 static void *si_create_fs_state(struct pipe_context
*ctx
,
1953 const struct pipe_shader_state
*state
)
1955 return si_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
1958 static void *si_create_vs_state(struct pipe_context
*ctx
,
1959 const struct pipe_shader_state
*state
)
1961 return si_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
1964 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1966 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1967 struct si_pipe_shader_selector
*sel
= state
;
1969 if (rctx
->vs_shader
== sel
)
1972 rctx
->vs_shader
= sel
;
1974 if (sel
&& sel
->current
)
1975 si_pm4_bind_state(rctx
, vs
, sel
->current
->pm4
);
1977 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
1980 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1982 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1983 struct si_pipe_shader_selector
*sel
= state
;
1985 if (rctx
->ps_shader
== sel
)
1988 rctx
->ps_shader
= sel
;
1990 if (sel
&& sel
->current
)
1991 si_pm4_bind_state(rctx
, ps
, sel
->current
->pm4
);
1993 si_pm4_bind_state(rctx
, ps
, rctx
->dummy_pixel_shader
->pm4
);
1996 static void si_delete_shader_selector(struct pipe_context
*ctx
,
1997 struct si_pipe_shader_selector
*sel
)
1999 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2000 struct si_pipe_shader
*p
= sel
->current
, *c
;
2003 c
= p
->next_variant
;
2004 si_pm4_delete_state(rctx
, vs
, p
->pm4
);
2005 si_pipe_shader_destroy(ctx
, p
);
2014 static void si_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
2016 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2017 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2019 if (rctx
->vs_shader
== sel
) {
2020 rctx
->vs_shader
= NULL
;
2023 si_delete_shader_selector(ctx
, sel
);
2026 static void si_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
2028 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2029 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2031 if (rctx
->ps_shader
== sel
) {
2032 rctx
->ps_shader
= NULL
;
2035 si_delete_shader_selector(ctx
, sel
);
2042 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
2043 struct pipe_resource
*texture
,
2044 const struct pipe_sampler_view
*state
)
2046 struct si_pipe_sampler_view
*view
= CALLOC_STRUCT(si_pipe_sampler_view
);
2047 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
2048 const struct util_format_description
*desc
= util_format_description(state
->format
);
2049 unsigned blocksize
= util_format_get_blocksize(tmp
->real_format
);
2050 unsigned format
, num_format
, /*endian,*/ tiling_index
;
2052 unsigned char state_swizzle
[4], swizzle
[4];
2053 unsigned height
, depth
, width
;
2060 /* initialize base object */
2061 view
->base
= *state
;
2062 view
->base
.texture
= NULL
;
2063 pipe_reference(NULL
, &texture
->reference
);
2064 view
->base
.texture
= texture
;
2065 view
->base
.reference
.count
= 1;
2066 view
->base
.context
= ctx
;
2068 state_swizzle
[0] = state
->swizzle_r
;
2069 state_swizzle
[1] = state
->swizzle_g
;
2070 state_swizzle
[2] = state
->swizzle_b
;
2071 state_swizzle
[3] = state
->swizzle_a
;
2072 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2074 first_non_void
= util_format_get_first_non_void_channel(state
->format
);
2075 switch (desc
->channel
[first_non_void
].type
) {
2076 case UTIL_FORMAT_TYPE_FLOAT
:
2077 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2079 case UTIL_FORMAT_TYPE_SIGNED
:
2080 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2082 case UTIL_FORMAT_TYPE_UNSIGNED
:
2084 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2087 format
= si_translate_texformat(ctx
->screen
, state
->format
, desc
, first_non_void
);
2092 if (tmp
->depth
&& !tmp
->is_flushing_texture
) {
2093 r600_texture_depth_flush(ctx
, texture
, TRUE
);
2094 tmp
= tmp
->flushed_depth_texture
;
2097 /* not supported any more */
2098 //endian = si_colorformat_endian_swap(format);
2100 width
= tmp
->surface
.level
[0].npix_x
;
2101 height
= tmp
->surface
.level
[0].npix_y
;
2102 depth
= tmp
->surface
.level
[0].npix_z
;
2103 pitch
= tmp
->surface
.level
[0].nblk_x
* util_format_get_blockwidth(state
->format
);
2105 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2107 depth
= texture
->array_size
;
2108 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2109 depth
= texture
->array_size
;
2113 switch (tmp
->surface
.level
[0].mode
) {
2114 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
2117 case RADEON_SURF_MODE_1D
:
2120 case RADEON_SURF_MODE_2D
:
2121 if (tmp
->resource
.b
.b
.bind
& PIPE_BIND_SCANOUT
) {
2122 switch (blocksize
) {
2134 } else switch (blocksize
) {
2153 va
= r600_resource_va(ctx
->screen
, texture
);
2154 va
+= tmp
->surface
.level
[0].offset
;
2155 view
->state
[0] = va
>> 8;
2156 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2157 S_008F14_DATA_FORMAT(format
) |
2158 S_008F14_NUM_FORMAT(num_format
));
2159 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2160 S_008F18_HEIGHT(height
- 1));
2161 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2162 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2163 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2164 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2165 S_008F1C_BASE_LEVEL(state
->u
.tex
.first_level
) |
2166 S_008F1C_LAST_LEVEL(state
->u
.tex
.last_level
) |
2167 S_008F1C_TILING_INDEX(tiling_index
) |
2168 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2169 S_008F1C_TYPE(si_tex_dim(texture
->target
)));
2170 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2171 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2172 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
));
2179 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2180 struct pipe_sampler_view
*state
)
2182 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
2184 pipe_resource_reference(&state
->texture
, NULL
);
2188 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2189 const struct pipe_sampler_state
*state
)
2191 struct si_pipe_sampler_state
*rstate
= CALLOC_STRUCT(si_pipe_sampler_state
);
2192 union util_color uc
;
2193 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2194 unsigned border_color_type
;
2196 if (rstate
== NULL
) {
2200 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_A8R8G8B8_UNORM
, &uc
);
2203 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
2206 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2209 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
2211 default: /* Use border color pointer */
2212 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2215 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2216 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2217 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2218 (state
->max_anisotropy
& 0x7) << 9 | /* XXX */
2219 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2220 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2221 aniso_flag_offset
<< 16 | /* XXX */
2222 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2223 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2224 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2225 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2226 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
)) |
2227 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
)) |
2228 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2229 rstate
->val
[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2231 if (border_color_type
== V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2232 memcpy(rstate
->border_color
, state
->border_color
.f
,
2233 sizeof(rstate
->border_color
));
2239 static void si_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
2240 struct pipe_sampler_view
**views
)
2245 static void si_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
2246 struct pipe_sampler_view
**views
)
2248 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2249 struct si_pipe_sampler_view
**resource
= (struct si_pipe_sampler_view
**)views
;
2250 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2257 si_pm4_inval_texture_cache(pm4
);
2259 si_pm4_sh_data_begin(pm4
);
2260 for (i
= 0; i
< count
; i
++) {
2261 pipe_sampler_view_reference(
2262 (struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
],
2266 struct r600_resource_texture
*tex
= (void *)resource
[i
]->base
.texture
;
2268 si_pm4_add_bo(pm4
, &tex
->resource
, RADEON_USAGE_READ
);
2271 for (j
= 0; j
< Elements(resource
[i
]->state
); ++j
) {
2272 si_pm4_sh_data_add(pm4
, resource
[i
] ? resource
[i
]->state
[j
] : 0);
2276 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
2277 if (rctx
->ps_samplers
.views
[i
])
2278 pipe_sampler_view_reference((struct pipe_sampler_view
**)&rctx
->ps_samplers
.views
[i
], NULL
);
2281 si_pm4_sh_data_end(pm4
, R_00B040_SPI_SHADER_USER_DATA_PS_4
);
2284 si_pm4_set_state(rctx
, ps_sampler_views
, pm4
);
2285 rctx
->have_depth_texture
= has_depth
;
2286 rctx
->ps_samplers
.n_views
= count
;
2289 static void si_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
2294 static void si_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
2296 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2297 struct si_pipe_sampler_state
**rstates
= (struct si_pipe_sampler_state
**)states
;
2298 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2299 uint32_t *border_color_table
= NULL
;
2305 si_pm4_inval_texture_cache(pm4
);
2307 si_pm4_sh_data_begin(pm4
);
2308 for (i
= 0; i
< count
; i
++) {
2310 G_008F3C_BORDER_COLOR_TYPE(rstates
[i
]->val
[3]) ==
2311 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2312 if (!rctx
->border_color_table
||
2313 ((rctx
->border_color_offset
+ count
- i
) &
2314 C_008F3C_BORDER_COLOR_PTR
)) {
2315 si_resource_reference(&rctx
->border_color_table
, NULL
);
2316 rctx
->border_color_offset
= 0;
2318 rctx
->border_color_table
=
2319 si_resource_create_custom(ctx
->screen
,
2324 if (!border_color_table
) {
2325 border_color_table
=
2326 rctx
->ws
->buffer_map(rctx
->border_color_table
->cs_buf
,
2328 PIPE_TRANSFER_WRITE
|
2329 PIPE_TRANSFER_UNSYNCHRONIZED
);
2332 for (j
= 0; j
< 4; j
++) {
2333 union fi border_color
;
2335 border_color
.f
= rstates
[i
]->border_color
[j
];
2336 border_color_table
[4 * rctx
->border_color_offset
+ j
] =
2337 util_le32_to_cpu(border_color
.i
);
2340 rstates
[i
]->val
[3] &= C_008F3C_BORDER_COLOR_PTR
;
2341 rstates
[i
]->val
[3] |= S_008F3C_BORDER_COLOR_PTR(rctx
->border_color_offset
++);
2344 for (j
= 0; j
< Elements(rstates
[i
]->val
); ++j
) {
2345 si_pm4_sh_data_add(pm4
, rstates
[i
] ? rstates
[i
]->val
[j
] : 0);
2348 si_pm4_sh_data_end(pm4
, R_00B038_SPI_SHADER_USER_DATA_PS_2
);
2350 if (border_color_table
) {
2351 uint64_t va_offset
=
2352 r600_resource_va(ctx
->screen
, (void*)rctx
->border_color_table
);
2354 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, va_offset
>> 8);
2355 rctx
->ws
->buffer_unmap(rctx
->border_color_table
->cs_buf
);
2356 si_pm4_add_bo(pm4
, rctx
->border_color_table
, RADEON_USAGE_READ
);
2359 memcpy(rctx
->ps_samplers
.samplers
, states
, sizeof(void*) * count
);
2362 si_pm4_set_state(rctx
, ps_sampler
, pm4
);
2363 rctx
->ps_samplers
.n_samplers
= count
;
2366 static void si_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
2370 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
2378 static void si_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
2379 struct pipe_constant_buffer
*cb
)
2381 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2382 struct si_resource
*rbuffer
= cb
? si_resource(cb
->buffer
) : NULL
;
2383 struct si_pm4_state
*pm4
;
2387 /* Note that the state tracker can unbind constant buffers by
2388 * passing NULL here.
2393 pm4
= CALLOC_STRUCT(si_pm4_state
);
2394 si_pm4_inval_shader_cache(pm4
);
2396 if (cb
->user_buffer
)
2397 r600_upload_const_buffer(rctx
, &rbuffer
, cb
->user_buffer
, cb
->buffer_size
, &offset
);
2400 va_offset
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
2401 va_offset
+= offset
;
2403 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
2406 case PIPE_SHADER_VERTEX
:
2407 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
, va_offset
);
2408 si_pm4_set_reg(pm4
, R_00B134_SPI_SHADER_USER_DATA_VS_1
, va_offset
>> 32);
2409 si_pm4_set_state(rctx
, vs_const
, pm4
);
2412 case PIPE_SHADER_FRAGMENT
:
2413 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
, va_offset
);
2414 si_pm4_set_reg(pm4
, R_00B034_SPI_SHADER_USER_DATA_PS_1
, va_offset
>> 32);
2415 si_pm4_set_state(rctx
, ps_const
, pm4
);
2419 R600_ERR("unsupported %d\n", shader
);
2422 if (cb
->buffer
!= &rbuffer
->b
.b
)
2423 si_resource_reference(&rbuffer
, NULL
);
2427 * Vertex elements & buffers
2430 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
2432 const struct pipe_vertex_element
*elements
)
2434 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
2437 assert(count
< PIPE_MAX_ATTRIBS
);
2442 for (i
= 0; i
< count
; ++i
) {
2443 const struct util_format_description
*desc
;
2444 unsigned data_format
, num_format
;
2447 desc
= util_format_description(elements
[i
].src_format
);
2448 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
2449 data_format
= si_translate_vertexformat(ctx
->screen
, elements
[i
].src_format
,
2450 desc
, first_non_void
);
2452 switch (desc
->channel
[first_non_void
].type
) {
2453 case UTIL_FORMAT_TYPE_FIXED
:
2454 num_format
= V_008F0C_BUF_NUM_FORMAT_USCALED
; /* XXX */
2456 case UTIL_FORMAT_TYPE_SIGNED
:
2457 num_format
= V_008F0C_BUF_NUM_FORMAT_SNORM
;
2459 case UTIL_FORMAT_TYPE_UNSIGNED
:
2460 num_format
= V_008F0C_BUF_NUM_FORMAT_UNORM
;
2462 case UTIL_FORMAT_TYPE_FLOAT
:
2464 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2467 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2468 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2469 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2470 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2471 S_008F0C_NUM_FORMAT(num_format
) |
2472 S_008F0C_DATA_FORMAT(data_format
);
2474 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
2479 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
2481 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2482 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
2484 rctx
->vertex_elements
= v
;
2487 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
2489 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2491 if (rctx
->vertex_elements
== state
)
2492 rctx
->vertex_elements
= NULL
;
2496 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
2497 const struct pipe_vertex_buffer
*buffers
)
2499 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2501 util_copy_vertex_buffers(rctx
->vertex_buffer
, &rctx
->nr_vertex_buffers
, buffers
, count
);
2504 static void si_set_index_buffer(struct pipe_context
*ctx
,
2505 const struct pipe_index_buffer
*ib
)
2507 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2510 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
2511 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
2513 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
2520 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
2521 const struct pipe_poly_stipple
*state
)
2525 static void si_texture_barrier(struct pipe_context
*ctx
)
2527 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2528 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2530 si_pm4_inval_texture_cache(pm4
);
2531 si_pm4_inval_fb_cache(pm4
, rctx
->framebuffer
.nr_cbufs
);
2532 si_pm4_set_state(rctx
, texture_barrier
, pm4
);
2535 void si_init_state_functions(struct r600_context
*rctx
)
2537 rctx
->context
.create_blend_state
= si_create_blend_state
;
2538 rctx
->context
.bind_blend_state
= si_bind_blend_state
;
2539 rctx
->context
.delete_blend_state
= si_delete_blend_state
;
2540 rctx
->context
.set_blend_color
= si_set_blend_color
;
2542 rctx
->context
.create_rasterizer_state
= si_create_rs_state
;
2543 rctx
->context
.bind_rasterizer_state
= si_bind_rs_state
;
2544 rctx
->context
.delete_rasterizer_state
= si_delete_rs_state
;
2546 rctx
->context
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
2547 rctx
->context
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
2548 rctx
->context
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
2549 rctx
->custom_dsa_flush
= si_create_db_flush_dsa(rctx
);
2551 rctx
->context
.set_clip_state
= si_set_clip_state
;
2552 rctx
->context
.set_scissor_state
= si_set_scissor_state
;
2553 rctx
->context
.set_viewport_state
= si_set_viewport_state
;
2554 rctx
->context
.set_stencil_ref
= si_set_pipe_stencil_ref
;
2556 rctx
->context
.set_framebuffer_state
= si_set_framebuffer_state
;
2558 rctx
->context
.create_vs_state
= si_create_vs_state
;
2559 rctx
->context
.create_fs_state
= si_create_fs_state
;
2560 rctx
->context
.bind_vs_state
= si_bind_vs_shader
;
2561 rctx
->context
.bind_fs_state
= si_bind_ps_shader
;
2562 rctx
->context
.delete_vs_state
= si_delete_vs_shader
;
2563 rctx
->context
.delete_fs_state
= si_delete_ps_shader
;
2565 rctx
->context
.create_sampler_state
= si_create_sampler_state
;
2566 rctx
->context
.bind_vertex_sampler_states
= si_bind_vs_sampler
;
2567 rctx
->context
.bind_fragment_sampler_states
= si_bind_ps_sampler
;
2568 rctx
->context
.delete_sampler_state
= si_delete_sampler_state
;
2570 rctx
->context
.create_sampler_view
= si_create_sampler_view
;
2571 rctx
->context
.set_vertex_sampler_views
= si_set_vs_sampler_view
;
2572 rctx
->context
.set_fragment_sampler_views
= si_set_ps_sampler_view
;
2573 rctx
->context
.sampler_view_destroy
= si_sampler_view_destroy
;
2575 rctx
->context
.set_sample_mask
= si_set_sample_mask
;
2577 rctx
->context
.set_constant_buffer
= si_set_constant_buffer
;
2579 rctx
->context
.create_vertex_elements_state
= si_create_vertex_elements
;
2580 rctx
->context
.bind_vertex_elements_state
= si_bind_vertex_elements
;
2581 rctx
->context
.delete_vertex_elements_state
= si_delete_vertex_element
;
2582 rctx
->context
.set_vertex_buffers
= si_set_vertex_buffers
;
2583 rctx
->context
.set_index_buffer
= si_set_index_buffer
;
2585 rctx
->context
.create_stream_output_target
= si_create_so_target
;
2586 rctx
->context
.stream_output_target_destroy
= si_so_target_destroy
;
2587 rctx
->context
.set_stream_output_targets
= si_set_so_targets
;
2589 rctx
->context
.texture_barrier
= si_texture_barrier
;
2590 rctx
->context
.set_polygon_stipple
= si_set_polygon_stipple
;
2592 rctx
->context
.draw_vbo
= si_draw_vbo
;
2595 void si_init_config(struct r600_context
*rctx
)
2597 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2599 si_cmd_context_control(pm4
);
2601 si_pm4_set_reg(pm4
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0);
2603 si_pm4_set_reg(pm4
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0);
2604 si_pm4_set_reg(pm4
, R_028A14_VGT_HOS_CNTL
, 0x0);
2605 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0);
2606 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0);
2607 si_pm4_set_reg(pm4
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0);
2608 si_pm4_set_reg(pm4
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0);
2609 si_pm4_set_reg(pm4
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0);
2610 si_pm4_set_reg(pm4
, R_028A2C_VGT_GROUP_DECR
, 0x0);
2611 si_pm4_set_reg(pm4
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0);
2612 si_pm4_set_reg(pm4
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0);
2613 si_pm4_set_reg(pm4
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0);
2614 si_pm4_set_reg(pm4
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0);
2615 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, 0x0);
2616 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0x0);
2617 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
2618 si_pm4_set_reg(pm4
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0);
2619 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
2620 si_pm4_set_reg(pm4
, R_028AA8_IA_MULTI_VGT_PARAM
,
2621 S_028AA8_SWITCH_ON_EOP(1) |
2622 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2623 S_028AA8_PRIMGROUP_SIZE(63));
2624 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0x00000000);
2625 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
2626 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, (3 << 1) | 1);
2628 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2629 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
2630 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
2632 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
, 0x110000);
2634 si_pm4_set_state(rctx
, init
, pm4
);