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radeonsi: flush all CB/DB caches unconditionally when changing the framebuffer
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35
36 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
37 void (*emit)(struct si_context *ctx, struct r600_atom *state),
38 unsigned num_dw)
39 {
40 atom->emit = (void*)emit;
41 atom->num_dw = num_dw;
42 atom->dirty = false;
43 *list_elem = atom;
44 }
45
46 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
47 {
48 if (sscreen->b.chip_class == CIK &&
49 sscreen->b.info.cik_macrotile_mode_array_valid) {
50 unsigned index, tileb;
51
52 tileb = 8 * 8 * tex->surface.bpe;
53 tileb = MIN2(tex->surface.tile_split, tileb);
54
55 for (index = 0; tileb > 64; index++) {
56 tileb >>= 1;
57 }
58 assert(index < 16);
59
60 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
61 }
62
63 if (sscreen->b.chip_class == SI &&
64 sscreen->b.info.si_tile_mode_array_valid) {
65 /* Don't use stencil_tiling_index, because num_banks is always
66 * read from the depth mode. */
67 unsigned tile_mode_index = tex->surface.tiling_index[0];
68 assert(tile_mode_index < 32);
69
70 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
71 }
72
73 /* The old way. */
74 switch (sscreen->b.tiling_info.num_banks) {
75 case 2:
76 return V_02803C_ADDR_SURF_2_BANK;
77 case 4:
78 return V_02803C_ADDR_SURF_4_BANK;
79 case 8:
80 default:
81 return V_02803C_ADDR_SURF_8_BANK;
82 case 16:
83 return V_02803C_ADDR_SURF_16_BANK;
84 }
85 }
86
87 unsigned cik_tile_split(unsigned tile_split)
88 {
89 switch (tile_split) {
90 case 64:
91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
92 break;
93 case 128:
94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
95 break;
96 case 256:
97 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
98 break;
99 case 512:
100 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
101 break;
102 default:
103 case 1024:
104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
105 break;
106 case 2048:
107 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
108 break;
109 case 4096:
110 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
111 break;
112 }
113 return tile_split;
114 }
115
116 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
117 {
118 switch (macro_tile_aspect) {
119 default:
120 case 1:
121 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
122 break;
123 case 2:
124 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
125 break;
126 case 4:
127 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
128 break;
129 case 8:
130 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
131 break;
132 }
133 return macro_tile_aspect;
134 }
135
136 unsigned cik_bank_wh(unsigned bankwh)
137 {
138 switch (bankwh) {
139 default:
140 case 1:
141 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
142 break;
143 case 2:
144 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
145 break;
146 case 4:
147 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
148 break;
149 case 8:
150 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
151 break;
152 }
153 return bankwh;
154 }
155
156 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
157 {
158 if (sscreen->b.info.si_tile_mode_array_valid) {
159 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
160
161 return G_009910_PIPE_CONFIG(gb_tile_mode);
162 }
163
164 /* This is probably broken for a lot of chips, but it's only used
165 * if the kernel cannot return the tile mode array for CIK. */
166 switch (sscreen->b.info.r600_num_tile_pipes) {
167 case 16:
168 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
169 case 8:
170 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
171 case 4:
172 default:
173 if (sscreen->b.info.r600_num_backends == 4)
174 return V_02803C_X_ADDR_SURF_P4_16X16;
175 else
176 return V_02803C_X_ADDR_SURF_P4_8X16;
177 case 2:
178 return V_02803C_ADDR_SURF_P2;
179 }
180 }
181
182 static unsigned si_map_swizzle(unsigned swizzle)
183 {
184 switch (swizzle) {
185 case UTIL_FORMAT_SWIZZLE_Y:
186 return V_008F0C_SQ_SEL_Y;
187 case UTIL_FORMAT_SWIZZLE_Z:
188 return V_008F0C_SQ_SEL_Z;
189 case UTIL_FORMAT_SWIZZLE_W:
190 return V_008F0C_SQ_SEL_W;
191 case UTIL_FORMAT_SWIZZLE_0:
192 return V_008F0C_SQ_SEL_0;
193 case UTIL_FORMAT_SWIZZLE_1:
194 return V_008F0C_SQ_SEL_1;
195 default: /* UTIL_FORMAT_SWIZZLE_X */
196 return V_008F0C_SQ_SEL_X;
197 }
198 }
199
200 static uint32_t S_FIXED(float value, uint32_t frac_bits)
201 {
202 return value * (1 << frac_bits);
203 }
204
205 /* 12.4 fixed-point */
206 static unsigned si_pack_float_12p4(float x)
207 {
208 return x <= 0 ? 0 :
209 x >= 4096 ? 0xffff : x * 16;
210 }
211
212 /*
213 * Inferred framebuffer and blender state.
214 *
215 * One of the reasons this must be derived from the framebuffer state is that:
216 * - The blend state mask is 0xf most of the time.
217 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
218 * so COLOR1 is enabled pretty much all the time.
219 * So CB_TARGET_MASK is the only register that can disable COLOR1.
220 */
221 static void si_update_fb_blend_state(struct si_context *sctx)
222 {
223 struct si_pm4_state *pm4;
224 struct si_state_blend *blend = sctx->queued.named.blend;
225 uint32_t mask = 0, i;
226
227 if (blend == NULL)
228 return;
229
230 pm4 = CALLOC_STRUCT(si_pm4_state);
231 if (pm4 == NULL)
232 return;
233
234 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
235 if (sctx->framebuffer.state.cbufs[i])
236 mask |= 0xf << (4*i);
237 mask &= blend->cb_target_mask;
238
239 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
240 si_pm4_set_state(sctx, fb_blend, pm4);
241 }
242
243 /*
244 * Blender functions
245 */
246
247 static uint32_t si_translate_blend_function(int blend_func)
248 {
249 switch (blend_func) {
250 case PIPE_BLEND_ADD:
251 return V_028780_COMB_DST_PLUS_SRC;
252 case PIPE_BLEND_SUBTRACT:
253 return V_028780_COMB_SRC_MINUS_DST;
254 case PIPE_BLEND_REVERSE_SUBTRACT:
255 return V_028780_COMB_DST_MINUS_SRC;
256 case PIPE_BLEND_MIN:
257 return V_028780_COMB_MIN_DST_SRC;
258 case PIPE_BLEND_MAX:
259 return V_028780_COMB_MAX_DST_SRC;
260 default:
261 R600_ERR("Unknown blend function %d\n", blend_func);
262 assert(0);
263 break;
264 }
265 return 0;
266 }
267
268 static uint32_t si_translate_blend_factor(int blend_fact)
269 {
270 switch (blend_fact) {
271 case PIPE_BLENDFACTOR_ONE:
272 return V_028780_BLEND_ONE;
273 case PIPE_BLENDFACTOR_SRC_COLOR:
274 return V_028780_BLEND_SRC_COLOR;
275 case PIPE_BLENDFACTOR_SRC_ALPHA:
276 return V_028780_BLEND_SRC_ALPHA;
277 case PIPE_BLENDFACTOR_DST_ALPHA:
278 return V_028780_BLEND_DST_ALPHA;
279 case PIPE_BLENDFACTOR_DST_COLOR:
280 return V_028780_BLEND_DST_COLOR;
281 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
282 return V_028780_BLEND_SRC_ALPHA_SATURATE;
283 case PIPE_BLENDFACTOR_CONST_COLOR:
284 return V_028780_BLEND_CONSTANT_COLOR;
285 case PIPE_BLENDFACTOR_CONST_ALPHA:
286 return V_028780_BLEND_CONSTANT_ALPHA;
287 case PIPE_BLENDFACTOR_ZERO:
288 return V_028780_BLEND_ZERO;
289 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
290 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
291 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
292 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
293 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
294 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
295 case PIPE_BLENDFACTOR_INV_DST_COLOR:
296 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
297 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
298 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
300 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_SRC1_COLOR:
302 return V_028780_BLEND_SRC1_COLOR;
303 case PIPE_BLENDFACTOR_SRC1_ALPHA:
304 return V_028780_BLEND_SRC1_ALPHA;
305 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
306 return V_028780_BLEND_INV_SRC1_COLOR;
307 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
308 return V_028780_BLEND_INV_SRC1_ALPHA;
309 default:
310 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
311 assert(0);
312 break;
313 }
314 return 0;
315 }
316
317 static void *si_create_blend_state_mode(struct pipe_context *ctx,
318 const struct pipe_blend_state *state,
319 unsigned mode)
320 {
321 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
322 struct si_pm4_state *pm4 = &blend->pm4;
323
324 uint32_t color_control = 0;
325
326 if (blend == NULL)
327 return NULL;
328
329 blend->alpha_to_one = state->alpha_to_one;
330
331 if (state->logicop_enable) {
332 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
333 } else {
334 color_control |= S_028808_ROP3(0xcc);
335 }
336
337 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
338 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
339 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
340 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
341 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
342 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
343
344 blend->cb_target_mask = 0;
345 for (int i = 0; i < 8; i++) {
346 /* state->rt entries > 0 only written if independent blending */
347 const int j = state->independent_blend_enable ? i : 0;
348
349 unsigned eqRGB = state->rt[j].rgb_func;
350 unsigned srcRGB = state->rt[j].rgb_src_factor;
351 unsigned dstRGB = state->rt[j].rgb_dst_factor;
352 unsigned eqA = state->rt[j].alpha_func;
353 unsigned srcA = state->rt[j].alpha_src_factor;
354 unsigned dstA = state->rt[j].alpha_dst_factor;
355
356 unsigned blend_cntl = 0;
357
358 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
359 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
360
361 if (!state->rt[j].blend_enable) {
362 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
363 continue;
364 }
365
366 blend_cntl |= S_028780_ENABLE(1);
367 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
368 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
369 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
370
371 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
372 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
373 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
374 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
375 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
376 }
377 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
378 }
379
380 if (blend->cb_target_mask) {
381 color_control |= S_028808_MODE(mode);
382 } else {
383 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
384 }
385 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
386
387 return blend;
388 }
389
390 static void *si_create_blend_state(struct pipe_context *ctx,
391 const struct pipe_blend_state *state)
392 {
393 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
394 }
395
396 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
397 {
398 struct si_context *sctx = (struct si_context *)ctx;
399 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
400 si_update_fb_blend_state(sctx);
401 }
402
403 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
404 {
405 struct si_context *sctx = (struct si_context *)ctx;
406 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
407 }
408
409 static void si_set_blend_color(struct pipe_context *ctx,
410 const struct pipe_blend_color *state)
411 {
412 struct si_context *sctx = (struct si_context *)ctx;
413 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
414
415 if (pm4 == NULL)
416 return;
417
418 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
419 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
420 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
421 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
422
423 si_pm4_set_state(sctx, blend_color, pm4);
424 }
425
426 /*
427 * Clipping, scissors and viewport
428 */
429
430 static void si_set_clip_state(struct pipe_context *ctx,
431 const struct pipe_clip_state *state)
432 {
433 struct si_context *sctx = (struct si_context *)ctx;
434 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
435 struct pipe_constant_buffer cb;
436
437 if (pm4 == NULL)
438 return;
439
440 for (int i = 0; i < 6; i++) {
441 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
442 fui(state->ucp[i][0]));
443 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
444 fui(state->ucp[i][1]));
445 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
446 fui(state->ucp[i][2]));
447 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
448 fui(state->ucp[i][3]));
449 }
450
451 cb.buffer = NULL;
452 cb.user_buffer = state->ucp;
453 cb.buffer_offset = 0;
454 cb.buffer_size = 4*4*8;
455 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
456 pipe_resource_reference(&cb.buffer, NULL);
457
458 si_pm4_set_state(sctx, clip, pm4);
459 }
460
461 #define SIX_BITS 0x3F
462
463 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
464 {
465 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
466 struct tgsi_shader_info *info = si_get_vs_info(sctx);
467 struct si_shader *vs = si_get_vs_state(sctx);
468 unsigned window_space =
469 vs->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
470 unsigned clipdist_mask =
471 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
472
473 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
474 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
475 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
476 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
477 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
478 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
479 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
480 info->writes_edgeflag ||
481 info->writes_layer) |
482 (sctx->queued.named.rasterizer->clip_plane_enable &
483 clipdist_mask));
484 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
485 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
486 (clipdist_mask ? 0 :
487 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
488 S_028810_CLIP_DISABLE(window_space));
489 }
490
491 static void si_set_scissor_states(struct pipe_context *ctx,
492 unsigned start_slot,
493 unsigned num_scissors,
494 const struct pipe_scissor_state *state)
495 {
496 struct si_context *sctx = (struct si_context *)ctx;
497 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
498 struct si_pm4_state *pm4 = &scissor->pm4;
499
500 if (scissor == NULL)
501 return;
502
503 scissor->scissor = *state;
504 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
505 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
506 S_028250_WINDOW_OFFSET_DISABLE(1));
507 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
508 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
509
510 si_pm4_set_state(sctx, scissor, scissor);
511 }
512
513 static void si_set_viewport_states(struct pipe_context *ctx,
514 unsigned start_slot,
515 unsigned num_viewports,
516 const struct pipe_viewport_state *state)
517 {
518 struct si_context *sctx = (struct si_context *)ctx;
519 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
520 struct si_pm4_state *pm4 = &viewport->pm4;
521
522 if (viewport == NULL)
523 return;
524
525 viewport->viewport = *state;
526 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
527 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
528 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
529 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
530 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
531 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
532
533 si_pm4_set_state(sctx, viewport, viewport);
534 }
535
536 /*
537 * inferred state between framebuffer and rasterizer
538 */
539 static void si_update_fb_rs_state(struct si_context *sctx)
540 {
541 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
542 struct si_pm4_state *pm4;
543 float offset_units;
544
545 if (!rs || !sctx->framebuffer.state.zsbuf)
546 return;
547
548 offset_units = sctx->queued.named.rasterizer->offset_units;
549 switch (sctx->framebuffer.state.zsbuf->texture->format) {
550 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
551 case PIPE_FORMAT_X8Z24_UNORM:
552 case PIPE_FORMAT_Z24X8_UNORM:
553 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
554 offset_units *= 2.0f;
555 break;
556 case PIPE_FORMAT_Z32_FLOAT:
557 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
558 offset_units *= 1.0f;
559 break;
560 case PIPE_FORMAT_Z16_UNORM:
561 offset_units *= 4.0f;
562 break;
563 default:
564 return;
565 }
566
567 pm4 = CALLOC_STRUCT(si_pm4_state);
568
569 if (pm4 == NULL)
570 return;
571
572 /* FIXME some of those reg can be computed with cso */
573 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
574 fui(sctx->queued.named.rasterizer->offset_scale));
575 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
576 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
577 fui(sctx->queued.named.rasterizer->offset_scale));
578 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
579
580 si_pm4_set_state(sctx, fb_rs, pm4);
581 }
582
583 /*
584 * Rasterizer
585 */
586
587 static uint32_t si_translate_fill(uint32_t func)
588 {
589 switch(func) {
590 case PIPE_POLYGON_MODE_FILL:
591 return V_028814_X_DRAW_TRIANGLES;
592 case PIPE_POLYGON_MODE_LINE:
593 return V_028814_X_DRAW_LINES;
594 case PIPE_POLYGON_MODE_POINT:
595 return V_028814_X_DRAW_POINTS;
596 default:
597 assert(0);
598 return V_028814_X_DRAW_POINTS;
599 }
600 }
601
602 static void *si_create_rs_state(struct pipe_context *ctx,
603 const struct pipe_rasterizer_state *state)
604 {
605 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
606 struct si_pm4_state *pm4 = &rs->pm4;
607 unsigned tmp;
608 unsigned prov_vtx = 1, polygon_dual_mode;
609 float psize_min, psize_max;
610
611 if (rs == NULL) {
612 return NULL;
613 }
614
615 rs->two_side = state->light_twoside;
616 rs->multisample_enable = state->multisample;
617 rs->clip_plane_enable = state->clip_plane_enable;
618 rs->line_stipple_enable = state->line_stipple_enable;
619
620 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
621 state->fill_back != PIPE_POLYGON_MODE_FILL);
622
623 if (state->flatshade_first)
624 prov_vtx = 0;
625
626 rs->flatshade = state->flatshade;
627 rs->sprite_coord_enable = state->sprite_coord_enable;
628 rs->pa_sc_line_stipple = state->line_stipple_enable ?
629 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
630 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
631 rs->pa_su_sc_mode_cntl =
632 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
633 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
634 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
635 S_028814_FACE(!state->front_ccw) |
636 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
637 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
638 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
639 S_028814_POLY_MODE(polygon_dual_mode) |
640 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
641 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
642 rs->pa_cl_clip_cntl =
643 S_028810_PS_UCP_MODE(3) |
644 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
645 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
646 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
647 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
648 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
649
650 /* offset */
651 rs->offset_units = state->offset_units;
652 rs->offset_scale = state->offset_scale * 12.0f;
653
654 tmp = S_0286D4_FLAT_SHADE_ENA(1);
655 if (state->sprite_coord_enable) {
656 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
657 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
658 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
659 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
660 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
661 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
662 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
663 }
664 }
665 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
666
667 /* point size 12.4 fixed point */
668 tmp = (unsigned)(state->point_size * 8.0);
669 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
670
671 if (state->point_size_per_vertex) {
672 psize_min = util_get_min_point_size(state);
673 psize_max = 8192;
674 } else {
675 /* Force the point size to be as if the vertex output was disabled. */
676 psize_min = state->point_size;
677 psize_max = state->point_size;
678 }
679 /* Divide by two, because 0.5 = 1 pixel. */
680 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
681 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
682 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
683
684 tmp = (unsigned)state->line_width * 8;
685 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
686 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
687 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
688 S_028A48_MSAA_ENABLE(state->multisample) |
689 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
690
691 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
692 S_028BE4_PIX_CENTER(state->half_pixel_center) |
693 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
694
695 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
696
697 return rs;
698 }
699
700 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
701 {
702 struct si_context *sctx = (struct si_context *)ctx;
703 struct si_state_rasterizer *old_rs =
704 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
705 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
706
707 if (state == NULL)
708 return;
709
710 // TODO
711 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
712 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
713
714 if (sctx->framebuffer.nr_samples > 1 &&
715 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
716 sctx->db_render_state.dirty = true;
717
718 si_pm4_bind_state(sctx, rasterizer, rs);
719 si_update_fb_rs_state(sctx);
720
721 sctx->clip_regs.dirty = true;
722 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
723 }
724
725 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
726 {
727 struct si_context *sctx = (struct si_context *)ctx;
728 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
729 }
730
731 /*
732 * infeered state between dsa and stencil ref
733 */
734 static void si_update_dsa_stencil_ref(struct si_context *sctx)
735 {
736 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
737 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
738 struct si_state_dsa *dsa = sctx->queued.named.dsa;
739
740 if (pm4 == NULL)
741 return;
742
743 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
744 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
745 S_028430_STENCILMASK(dsa->valuemask[0]) |
746 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
747 S_028430_STENCILOPVAL(1));
748 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
749 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
750 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
751 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
752 S_028434_STENCILOPVAL_BF(1));
753
754 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
755 }
756
757 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
758 const struct pipe_stencil_ref *state)
759 {
760 struct si_context *sctx = (struct si_context *)ctx;
761 sctx->stencil_ref = *state;
762 si_update_dsa_stencil_ref(sctx);
763 }
764
765
766 /*
767 * DSA
768 */
769
770 static uint32_t si_translate_stencil_op(int s_op)
771 {
772 switch (s_op) {
773 case PIPE_STENCIL_OP_KEEP:
774 return V_02842C_STENCIL_KEEP;
775 case PIPE_STENCIL_OP_ZERO:
776 return V_02842C_STENCIL_ZERO;
777 case PIPE_STENCIL_OP_REPLACE:
778 return V_02842C_STENCIL_REPLACE_TEST;
779 case PIPE_STENCIL_OP_INCR:
780 return V_02842C_STENCIL_ADD_CLAMP;
781 case PIPE_STENCIL_OP_DECR:
782 return V_02842C_STENCIL_SUB_CLAMP;
783 case PIPE_STENCIL_OP_INCR_WRAP:
784 return V_02842C_STENCIL_ADD_WRAP;
785 case PIPE_STENCIL_OP_DECR_WRAP:
786 return V_02842C_STENCIL_SUB_WRAP;
787 case PIPE_STENCIL_OP_INVERT:
788 return V_02842C_STENCIL_INVERT;
789 default:
790 R600_ERR("Unknown stencil op %d", s_op);
791 assert(0);
792 break;
793 }
794 return 0;
795 }
796
797 static void *si_create_dsa_state(struct pipe_context *ctx,
798 const struct pipe_depth_stencil_alpha_state *state)
799 {
800 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
801 struct si_pm4_state *pm4 = &dsa->pm4;
802 unsigned db_depth_control;
803 uint32_t db_stencil_control = 0;
804
805 if (dsa == NULL) {
806 return NULL;
807 }
808
809 dsa->valuemask[0] = state->stencil[0].valuemask;
810 dsa->valuemask[1] = state->stencil[1].valuemask;
811 dsa->writemask[0] = state->stencil[0].writemask;
812 dsa->writemask[1] = state->stencil[1].writemask;
813
814 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
815 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
816 S_028800_ZFUNC(state->depth.func);
817
818 /* stencil */
819 if (state->stencil[0].enabled) {
820 db_depth_control |= S_028800_STENCIL_ENABLE(1);
821 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
822 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
823 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
824 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
825
826 if (state->stencil[1].enabled) {
827 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
828 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
829 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
830 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
831 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
832 }
833 }
834
835 /* alpha */
836 if (state->alpha.enabled) {
837 dsa->alpha_func = state->alpha.func;
838
839 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
840 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
841 } else {
842 dsa->alpha_func = PIPE_FUNC_ALWAYS;
843 }
844
845 /* misc */
846 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
847 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
848
849 return dsa;
850 }
851
852 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
853 {
854 struct si_context *sctx = (struct si_context *)ctx;
855 struct si_state_dsa *dsa = state;
856
857 if (state == NULL)
858 return;
859
860 si_pm4_bind_state(sctx, dsa, dsa);
861 si_update_dsa_stencil_ref(sctx);
862 }
863
864 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
865 {
866 struct si_context *sctx = (struct si_context *)ctx;
867 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
868 }
869
870 static void *si_create_db_flush_dsa(struct si_context *sctx)
871 {
872 struct pipe_depth_stencil_alpha_state dsa = {};
873
874 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
875 }
876
877 /* DB RENDER STATE */
878
879 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
880 {
881 struct si_context *sctx = (struct si_context*)ctx;
882
883 sctx->db_render_state.dirty = true;
884 }
885
886 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
887 {
888 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
889 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
890 unsigned db_shader_control;
891
892 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
893
894 /* DB_RENDER_CONTROL */
895 if (sctx->dbcb_depth_copy_enabled ||
896 sctx->dbcb_stencil_copy_enabled) {
897 radeon_emit(cs,
898 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
899 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
900 S_028000_COPY_CENTROID(1) |
901 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
902 } else if (sctx->db_inplace_flush_enabled) {
903 radeon_emit(cs,
904 S_028000_DEPTH_COMPRESS_DISABLE(1) |
905 S_028000_STENCIL_COMPRESS_DISABLE(1));
906 } else if (sctx->db_depth_clear) {
907 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
908 } else {
909 radeon_emit(cs, 0);
910 }
911
912 /* DB_COUNT_CONTROL (occlusion queries) */
913 if (sctx->b.num_occlusion_queries > 0) {
914 if (sctx->b.chip_class >= CIK) {
915 radeon_emit(cs,
916 S_028004_PERFECT_ZPASS_COUNTS(1) |
917 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
918 S_028004_ZPASS_ENABLE(1) |
919 S_028004_SLICE_EVEN_ENABLE(1) |
920 S_028004_SLICE_ODD_ENABLE(1));
921 } else {
922 radeon_emit(cs,
923 S_028004_PERFECT_ZPASS_COUNTS(1) |
924 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
925 }
926 } else {
927 /* Disable occlusion queries. */
928 if (sctx->b.chip_class >= CIK) {
929 radeon_emit(cs, 0);
930 } else {
931 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
932 }
933 }
934
935 /* DB_RENDER_OVERRIDE2 */
936 if (sctx->db_depth_disable_expclear) {
937 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
938 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
939 } else {
940 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
941 }
942
943 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
944 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
945 sctx->ps_db_shader_control;
946
947 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
948 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
949 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
950
951 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
952 db_shader_control);
953 }
954
955 /*
956 * format translation
957 */
958 static uint32_t si_translate_colorformat(enum pipe_format format)
959 {
960 const struct util_format_description *desc = util_format_description(format);
961
962 #define HAS_SIZE(x,y,z,w) \
963 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
964 desc->channel[2].size == (z) && desc->channel[3].size == (w))
965
966 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
967 return V_028C70_COLOR_10_11_11;
968
969 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
970 return V_028C70_COLOR_INVALID;
971
972 switch (desc->nr_channels) {
973 case 1:
974 switch (desc->channel[0].size) {
975 case 8:
976 return V_028C70_COLOR_8;
977 case 16:
978 return V_028C70_COLOR_16;
979 case 32:
980 return V_028C70_COLOR_32;
981 }
982 break;
983 case 2:
984 if (desc->channel[0].size == desc->channel[1].size) {
985 switch (desc->channel[0].size) {
986 case 8:
987 return V_028C70_COLOR_8_8;
988 case 16:
989 return V_028C70_COLOR_16_16;
990 case 32:
991 return V_028C70_COLOR_32_32;
992 }
993 } else if (HAS_SIZE(8,24,0,0)) {
994 return V_028C70_COLOR_24_8;
995 } else if (HAS_SIZE(24,8,0,0)) {
996 return V_028C70_COLOR_8_24;
997 }
998 break;
999 case 3:
1000 if (HAS_SIZE(5,6,5,0)) {
1001 return V_028C70_COLOR_5_6_5;
1002 } else if (HAS_SIZE(32,8,24,0)) {
1003 return V_028C70_COLOR_X24_8_32_FLOAT;
1004 }
1005 break;
1006 case 4:
1007 if (desc->channel[0].size == desc->channel[1].size &&
1008 desc->channel[0].size == desc->channel[2].size &&
1009 desc->channel[0].size == desc->channel[3].size) {
1010 switch (desc->channel[0].size) {
1011 case 4:
1012 return V_028C70_COLOR_4_4_4_4;
1013 case 8:
1014 return V_028C70_COLOR_8_8_8_8;
1015 case 16:
1016 return V_028C70_COLOR_16_16_16_16;
1017 case 32:
1018 return V_028C70_COLOR_32_32_32_32;
1019 }
1020 } else if (HAS_SIZE(5,5,5,1)) {
1021 return V_028C70_COLOR_1_5_5_5;
1022 } else if (HAS_SIZE(10,10,10,2)) {
1023 return V_028C70_COLOR_2_10_10_10;
1024 }
1025 break;
1026 }
1027 return V_028C70_COLOR_INVALID;
1028 }
1029
1030 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1031 {
1032 if (SI_BIG_ENDIAN) {
1033 switch(colorformat) {
1034 /* 8-bit buffers. */
1035 case V_028C70_COLOR_8:
1036 return V_028C70_ENDIAN_NONE;
1037
1038 /* 16-bit buffers. */
1039 case V_028C70_COLOR_5_6_5:
1040 case V_028C70_COLOR_1_5_5_5:
1041 case V_028C70_COLOR_4_4_4_4:
1042 case V_028C70_COLOR_16:
1043 case V_028C70_COLOR_8_8:
1044 return V_028C70_ENDIAN_8IN16;
1045
1046 /* 32-bit buffers. */
1047 case V_028C70_COLOR_8_8_8_8:
1048 case V_028C70_COLOR_2_10_10_10:
1049 case V_028C70_COLOR_8_24:
1050 case V_028C70_COLOR_24_8:
1051 case V_028C70_COLOR_16_16:
1052 return V_028C70_ENDIAN_8IN32;
1053
1054 /* 64-bit buffers. */
1055 case V_028C70_COLOR_16_16_16_16:
1056 return V_028C70_ENDIAN_8IN16;
1057
1058 case V_028C70_COLOR_32_32:
1059 return V_028C70_ENDIAN_8IN32;
1060
1061 /* 128-bit buffers. */
1062 case V_028C70_COLOR_32_32_32_32:
1063 return V_028C70_ENDIAN_8IN32;
1064 default:
1065 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1066 }
1067 } else {
1068 return V_028C70_ENDIAN_NONE;
1069 }
1070 }
1071
1072 /* Returns the size in bits of the widest component of a CB format */
1073 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1074 {
1075 switch(colorformat) {
1076 case V_028C70_COLOR_4_4_4_4:
1077 return 4;
1078
1079 case V_028C70_COLOR_1_5_5_5:
1080 case V_028C70_COLOR_5_5_5_1:
1081 return 5;
1082
1083 case V_028C70_COLOR_5_6_5:
1084 return 6;
1085
1086 case V_028C70_COLOR_8:
1087 case V_028C70_COLOR_8_8:
1088 case V_028C70_COLOR_8_8_8_8:
1089 return 8;
1090
1091 case V_028C70_COLOR_10_10_10_2:
1092 case V_028C70_COLOR_2_10_10_10:
1093 return 10;
1094
1095 case V_028C70_COLOR_10_11_11:
1096 case V_028C70_COLOR_11_11_10:
1097 return 11;
1098
1099 case V_028C70_COLOR_16:
1100 case V_028C70_COLOR_16_16:
1101 case V_028C70_COLOR_16_16_16_16:
1102 return 16;
1103
1104 case V_028C70_COLOR_8_24:
1105 case V_028C70_COLOR_24_8:
1106 return 24;
1107
1108 case V_028C70_COLOR_32:
1109 case V_028C70_COLOR_32_32:
1110 case V_028C70_COLOR_32_32_32_32:
1111 case V_028C70_COLOR_X24_8_32_FLOAT:
1112 return 32;
1113 }
1114
1115 assert(!"Unknown maximum component size");
1116 return 0;
1117 }
1118
1119 static uint32_t si_translate_dbformat(enum pipe_format format)
1120 {
1121 switch (format) {
1122 case PIPE_FORMAT_Z16_UNORM:
1123 return V_028040_Z_16;
1124 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1125 case PIPE_FORMAT_X8Z24_UNORM:
1126 case PIPE_FORMAT_Z24X8_UNORM:
1127 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1128 return V_028040_Z_24; /* deprecated on SI */
1129 case PIPE_FORMAT_Z32_FLOAT:
1130 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1131 return V_028040_Z_32_FLOAT;
1132 default:
1133 return V_028040_Z_INVALID;
1134 }
1135 }
1136
1137 /*
1138 * Texture translation
1139 */
1140
1141 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1142 enum pipe_format format,
1143 const struct util_format_description *desc,
1144 int first_non_void)
1145 {
1146 struct si_screen *sscreen = (struct si_screen*)screen;
1147 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1148 boolean uniform = TRUE;
1149 int i;
1150
1151 /* Colorspace (return non-RGB formats directly). */
1152 switch (desc->colorspace) {
1153 /* Depth stencil formats */
1154 case UTIL_FORMAT_COLORSPACE_ZS:
1155 switch (format) {
1156 case PIPE_FORMAT_Z16_UNORM:
1157 return V_008F14_IMG_DATA_FORMAT_16;
1158 case PIPE_FORMAT_X24S8_UINT:
1159 case PIPE_FORMAT_Z24X8_UNORM:
1160 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1161 return V_008F14_IMG_DATA_FORMAT_8_24;
1162 case PIPE_FORMAT_X8Z24_UNORM:
1163 case PIPE_FORMAT_S8X24_UINT:
1164 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1165 return V_008F14_IMG_DATA_FORMAT_24_8;
1166 case PIPE_FORMAT_S8_UINT:
1167 return V_008F14_IMG_DATA_FORMAT_8;
1168 case PIPE_FORMAT_Z32_FLOAT:
1169 return V_008F14_IMG_DATA_FORMAT_32;
1170 case PIPE_FORMAT_X32_S8X24_UINT:
1171 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1172 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1173 default:
1174 goto out_unknown;
1175 }
1176
1177 case UTIL_FORMAT_COLORSPACE_YUV:
1178 goto out_unknown; /* TODO */
1179
1180 case UTIL_FORMAT_COLORSPACE_SRGB:
1181 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1182 goto out_unknown;
1183 break;
1184
1185 default:
1186 break;
1187 }
1188
1189 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1190 if (!enable_s3tc)
1191 goto out_unknown;
1192
1193 switch (format) {
1194 case PIPE_FORMAT_RGTC1_SNORM:
1195 case PIPE_FORMAT_LATC1_SNORM:
1196 case PIPE_FORMAT_RGTC1_UNORM:
1197 case PIPE_FORMAT_LATC1_UNORM:
1198 return V_008F14_IMG_DATA_FORMAT_BC4;
1199 case PIPE_FORMAT_RGTC2_SNORM:
1200 case PIPE_FORMAT_LATC2_SNORM:
1201 case PIPE_FORMAT_RGTC2_UNORM:
1202 case PIPE_FORMAT_LATC2_UNORM:
1203 return V_008F14_IMG_DATA_FORMAT_BC5;
1204 default:
1205 goto out_unknown;
1206 }
1207 }
1208
1209 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1210 if (!enable_s3tc)
1211 goto out_unknown;
1212
1213 switch (format) {
1214 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1215 case PIPE_FORMAT_BPTC_SRGBA:
1216 return V_008F14_IMG_DATA_FORMAT_BC7;
1217 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1218 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1219 return V_008F14_IMG_DATA_FORMAT_BC6;
1220 default:
1221 goto out_unknown;
1222 }
1223 }
1224
1225 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1226 switch (format) {
1227 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1228 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1229 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1230 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1231 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1232 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1233 default:
1234 goto out_unknown;
1235 }
1236 }
1237
1238 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1239
1240 if (!enable_s3tc)
1241 goto out_unknown;
1242
1243 if (!util_format_s3tc_enabled) {
1244 goto out_unknown;
1245 }
1246
1247 switch (format) {
1248 case PIPE_FORMAT_DXT1_RGB:
1249 case PIPE_FORMAT_DXT1_RGBA:
1250 case PIPE_FORMAT_DXT1_SRGB:
1251 case PIPE_FORMAT_DXT1_SRGBA:
1252 return V_008F14_IMG_DATA_FORMAT_BC1;
1253 case PIPE_FORMAT_DXT3_RGBA:
1254 case PIPE_FORMAT_DXT3_SRGBA:
1255 return V_008F14_IMG_DATA_FORMAT_BC2;
1256 case PIPE_FORMAT_DXT5_RGBA:
1257 case PIPE_FORMAT_DXT5_SRGBA:
1258 return V_008F14_IMG_DATA_FORMAT_BC3;
1259 default:
1260 goto out_unknown;
1261 }
1262 }
1263
1264 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1265 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1266 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1267 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1268 }
1269
1270 /* R8G8Bx_SNORM - TODO CxV8U8 */
1271
1272 /* See whether the components are of the same size. */
1273 for (i = 1; i < desc->nr_channels; i++) {
1274 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1275 }
1276
1277 /* Non-uniform formats. */
1278 if (!uniform) {
1279 switch(desc->nr_channels) {
1280 case 3:
1281 if (desc->channel[0].size == 5 &&
1282 desc->channel[1].size == 6 &&
1283 desc->channel[2].size == 5) {
1284 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1285 }
1286 goto out_unknown;
1287 case 4:
1288 if (desc->channel[0].size == 5 &&
1289 desc->channel[1].size == 5 &&
1290 desc->channel[2].size == 5 &&
1291 desc->channel[3].size == 1) {
1292 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1293 }
1294 if (desc->channel[0].size == 10 &&
1295 desc->channel[1].size == 10 &&
1296 desc->channel[2].size == 10 &&
1297 desc->channel[3].size == 2) {
1298 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1299 }
1300 goto out_unknown;
1301 }
1302 goto out_unknown;
1303 }
1304
1305 if (first_non_void < 0 || first_non_void > 3)
1306 goto out_unknown;
1307
1308 /* uniform formats */
1309 switch (desc->channel[first_non_void].size) {
1310 case 4:
1311 switch (desc->nr_channels) {
1312 #if 0 /* Not supported for render targets */
1313 case 2:
1314 return V_008F14_IMG_DATA_FORMAT_4_4;
1315 #endif
1316 case 4:
1317 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1318 }
1319 break;
1320 case 8:
1321 switch (desc->nr_channels) {
1322 case 1:
1323 return V_008F14_IMG_DATA_FORMAT_8;
1324 case 2:
1325 return V_008F14_IMG_DATA_FORMAT_8_8;
1326 case 4:
1327 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1328 }
1329 break;
1330 case 16:
1331 switch (desc->nr_channels) {
1332 case 1:
1333 return V_008F14_IMG_DATA_FORMAT_16;
1334 case 2:
1335 return V_008F14_IMG_DATA_FORMAT_16_16;
1336 case 4:
1337 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1338 }
1339 break;
1340 case 32:
1341 switch (desc->nr_channels) {
1342 case 1:
1343 return V_008F14_IMG_DATA_FORMAT_32;
1344 case 2:
1345 return V_008F14_IMG_DATA_FORMAT_32_32;
1346 #if 0 /* Not supported for render targets */
1347 case 3:
1348 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1349 #endif
1350 case 4:
1351 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1352 }
1353 }
1354
1355 out_unknown:
1356 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1357 return ~0;
1358 }
1359
1360 static unsigned si_tex_wrap(unsigned wrap)
1361 {
1362 switch (wrap) {
1363 default:
1364 case PIPE_TEX_WRAP_REPEAT:
1365 return V_008F30_SQ_TEX_WRAP;
1366 case PIPE_TEX_WRAP_CLAMP:
1367 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1368 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1369 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1370 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1371 return V_008F30_SQ_TEX_CLAMP_BORDER;
1372 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1373 return V_008F30_SQ_TEX_MIRROR;
1374 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1375 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1376 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1377 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1378 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1379 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1380 }
1381 }
1382
1383 static unsigned si_tex_filter(unsigned filter)
1384 {
1385 switch (filter) {
1386 default:
1387 case PIPE_TEX_FILTER_NEAREST:
1388 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1389 case PIPE_TEX_FILTER_LINEAR:
1390 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1391 }
1392 }
1393
1394 static unsigned si_tex_mipfilter(unsigned filter)
1395 {
1396 switch (filter) {
1397 case PIPE_TEX_MIPFILTER_NEAREST:
1398 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1399 case PIPE_TEX_MIPFILTER_LINEAR:
1400 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1401 default:
1402 case PIPE_TEX_MIPFILTER_NONE:
1403 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1404 }
1405 }
1406
1407 static unsigned si_tex_compare(unsigned compare)
1408 {
1409 switch (compare) {
1410 default:
1411 case PIPE_FUNC_NEVER:
1412 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1413 case PIPE_FUNC_LESS:
1414 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1415 case PIPE_FUNC_EQUAL:
1416 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1417 case PIPE_FUNC_LEQUAL:
1418 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1419 case PIPE_FUNC_GREATER:
1420 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1421 case PIPE_FUNC_NOTEQUAL:
1422 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1423 case PIPE_FUNC_GEQUAL:
1424 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1425 case PIPE_FUNC_ALWAYS:
1426 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1427 }
1428 }
1429
1430 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1431 {
1432 switch (dim) {
1433 default:
1434 case PIPE_TEXTURE_1D:
1435 return V_008F1C_SQ_RSRC_IMG_1D;
1436 case PIPE_TEXTURE_1D_ARRAY:
1437 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1438 case PIPE_TEXTURE_2D:
1439 case PIPE_TEXTURE_RECT:
1440 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1441 V_008F1C_SQ_RSRC_IMG_2D;
1442 case PIPE_TEXTURE_2D_ARRAY:
1443 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1444 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1445 case PIPE_TEXTURE_3D:
1446 return V_008F1C_SQ_RSRC_IMG_3D;
1447 case PIPE_TEXTURE_CUBE:
1448 case PIPE_TEXTURE_CUBE_ARRAY:
1449 return V_008F1C_SQ_RSRC_IMG_CUBE;
1450 }
1451 }
1452
1453 /*
1454 * Format support testing
1455 */
1456
1457 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1458 {
1459 return si_translate_texformat(screen, format, util_format_description(format),
1460 util_format_get_first_non_void_channel(format)) != ~0U;
1461 }
1462
1463 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1464 const struct util_format_description *desc,
1465 int first_non_void)
1466 {
1467 unsigned type = desc->channel[first_non_void].type;
1468 int i;
1469
1470 if (type == UTIL_FORMAT_TYPE_FIXED)
1471 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1472
1473 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1474 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1475
1476 if (desc->nr_channels == 4 &&
1477 desc->channel[0].size == 10 &&
1478 desc->channel[1].size == 10 &&
1479 desc->channel[2].size == 10 &&
1480 desc->channel[3].size == 2)
1481 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1482
1483 /* See whether the components are of the same size. */
1484 for (i = 0; i < desc->nr_channels; i++) {
1485 if (desc->channel[first_non_void].size != desc->channel[i].size)
1486 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1487 }
1488
1489 switch (desc->channel[first_non_void].size) {
1490 case 8:
1491 switch (desc->nr_channels) {
1492 case 1:
1493 return V_008F0C_BUF_DATA_FORMAT_8;
1494 case 2:
1495 return V_008F0C_BUF_DATA_FORMAT_8_8;
1496 case 3:
1497 case 4:
1498 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1499 }
1500 break;
1501 case 16:
1502 switch (desc->nr_channels) {
1503 case 1:
1504 return V_008F0C_BUF_DATA_FORMAT_16;
1505 case 2:
1506 return V_008F0C_BUF_DATA_FORMAT_16_16;
1507 case 3:
1508 case 4:
1509 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1510 }
1511 break;
1512 case 32:
1513 /* From the Southern Islands ISA documentation about MTBUF:
1514 * 'Memory reads of data in memory that is 32 or 64 bits do not
1515 * undergo any format conversion.'
1516 */
1517 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1518 !desc->channel[first_non_void].pure_integer)
1519 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1520
1521 switch (desc->nr_channels) {
1522 case 1:
1523 return V_008F0C_BUF_DATA_FORMAT_32;
1524 case 2:
1525 return V_008F0C_BUF_DATA_FORMAT_32_32;
1526 case 3:
1527 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1528 case 4:
1529 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1530 }
1531 break;
1532 }
1533
1534 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1535 }
1536
1537 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1538 const struct util_format_description *desc,
1539 int first_non_void)
1540 {
1541 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1542 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1543
1544 switch (desc->channel[first_non_void].type) {
1545 case UTIL_FORMAT_TYPE_SIGNED:
1546 if (desc->channel[first_non_void].normalized)
1547 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1548 else if (desc->channel[first_non_void].pure_integer)
1549 return V_008F0C_BUF_NUM_FORMAT_SINT;
1550 else
1551 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1552 break;
1553 case UTIL_FORMAT_TYPE_UNSIGNED:
1554 if (desc->channel[first_non_void].normalized)
1555 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1556 else if (desc->channel[first_non_void].pure_integer)
1557 return V_008F0C_BUF_NUM_FORMAT_UINT;
1558 else
1559 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1560 break;
1561 case UTIL_FORMAT_TYPE_FLOAT:
1562 default:
1563 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1564 }
1565 }
1566
1567 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1568 {
1569 const struct util_format_description *desc;
1570 int first_non_void;
1571 unsigned data_format;
1572
1573 desc = util_format_description(format);
1574 first_non_void = util_format_get_first_non_void_channel(format);
1575 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1576 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1577 }
1578
1579 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1580 {
1581 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1582 r600_translate_colorswap(format) != ~0U;
1583 }
1584
1585 static bool si_is_zs_format_supported(enum pipe_format format)
1586 {
1587 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1588 }
1589
1590 boolean si_is_format_supported(struct pipe_screen *screen,
1591 enum pipe_format format,
1592 enum pipe_texture_target target,
1593 unsigned sample_count,
1594 unsigned usage)
1595 {
1596 struct si_screen *sscreen = (struct si_screen *)screen;
1597 unsigned retval = 0;
1598
1599 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1600 R600_ERR("r600: unsupported texture type %d\n", target);
1601 return FALSE;
1602 }
1603
1604 if (!util_format_is_supported(format, usage))
1605 return FALSE;
1606
1607 if (sample_count > 1) {
1608 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1609 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1610 return FALSE;
1611
1612 switch (sample_count) {
1613 case 2:
1614 case 4:
1615 case 8:
1616 break;
1617 default:
1618 return FALSE;
1619 }
1620 }
1621
1622 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1623 if (target == PIPE_BUFFER) {
1624 if (si_is_vertex_format_supported(screen, format))
1625 retval |= PIPE_BIND_SAMPLER_VIEW;
1626 } else {
1627 if (si_is_sampler_format_supported(screen, format))
1628 retval |= PIPE_BIND_SAMPLER_VIEW;
1629 }
1630 }
1631
1632 if ((usage & (PIPE_BIND_RENDER_TARGET |
1633 PIPE_BIND_DISPLAY_TARGET |
1634 PIPE_BIND_SCANOUT |
1635 PIPE_BIND_SHARED |
1636 PIPE_BIND_BLENDABLE)) &&
1637 si_is_colorbuffer_format_supported(format)) {
1638 retval |= usage &
1639 (PIPE_BIND_RENDER_TARGET |
1640 PIPE_BIND_DISPLAY_TARGET |
1641 PIPE_BIND_SCANOUT |
1642 PIPE_BIND_SHARED);
1643 if (!util_format_is_pure_integer(format) &&
1644 !util_format_is_depth_or_stencil(format))
1645 retval |= usage & PIPE_BIND_BLENDABLE;
1646 }
1647
1648 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1649 si_is_zs_format_supported(format)) {
1650 retval |= PIPE_BIND_DEPTH_STENCIL;
1651 }
1652
1653 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1654 si_is_vertex_format_supported(screen, format)) {
1655 retval |= PIPE_BIND_VERTEX_BUFFER;
1656 }
1657
1658 if (usage & PIPE_BIND_TRANSFER_READ)
1659 retval |= PIPE_BIND_TRANSFER_READ;
1660 if (usage & PIPE_BIND_TRANSFER_WRITE)
1661 retval |= PIPE_BIND_TRANSFER_WRITE;
1662
1663 return retval == usage;
1664 }
1665
1666 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1667 {
1668 unsigned tile_mode_index = 0;
1669
1670 if (stencil) {
1671 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1672 } else {
1673 tile_mode_index = rtex->surface.tiling_index[level];
1674 }
1675 return tile_mode_index;
1676 }
1677
1678 /*
1679 * framebuffer handling
1680 */
1681
1682 static void si_initialize_color_surface(struct si_context *sctx,
1683 struct r600_surface *surf)
1684 {
1685 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1686 unsigned level = surf->base.u.tex.level;
1687 uint64_t offset = rtex->surface.level[level].offset;
1688 unsigned pitch, slice;
1689 unsigned color_info, color_attrib, color_pitch, color_view;
1690 unsigned tile_mode_index;
1691 unsigned format, swap, ntype, endian;
1692 const struct util_format_description *desc;
1693 int i;
1694 unsigned blend_clamp = 0, blend_bypass = 0;
1695 unsigned max_comp_size;
1696
1697 /* Layered rendering doesn't work with LINEAR_GENERAL.
1698 * (LINEAR_ALIGNED and others work) */
1699 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1700 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1701 offset += rtex->surface.level[level].slice_size *
1702 surf->base.u.tex.first_layer;
1703 color_view = 0;
1704 } else {
1705 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1706 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1707 }
1708
1709 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1710 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1711 if (slice) {
1712 slice = slice - 1;
1713 }
1714
1715 tile_mode_index = si_tile_mode_index(rtex, level, false);
1716
1717 desc = util_format_description(surf->base.format);
1718 for (i = 0; i < 4; i++) {
1719 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1720 break;
1721 }
1722 }
1723 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1724 ntype = V_028C70_NUMBER_FLOAT;
1725 } else {
1726 ntype = V_028C70_NUMBER_UNORM;
1727 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1728 ntype = V_028C70_NUMBER_SRGB;
1729 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1730 if (desc->channel[i].pure_integer) {
1731 ntype = V_028C70_NUMBER_SINT;
1732 } else {
1733 assert(desc->channel[i].normalized);
1734 ntype = V_028C70_NUMBER_SNORM;
1735 }
1736 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1737 if (desc->channel[i].pure_integer) {
1738 ntype = V_028C70_NUMBER_UINT;
1739 } else {
1740 assert(desc->channel[i].normalized);
1741 ntype = V_028C70_NUMBER_UNORM;
1742 }
1743 }
1744 }
1745
1746 format = si_translate_colorformat(surf->base.format);
1747 if (format == V_028C70_COLOR_INVALID) {
1748 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1749 }
1750 assert(format != V_028C70_COLOR_INVALID);
1751 swap = r600_translate_colorswap(surf->base.format);
1752 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1753 endian = V_028C70_ENDIAN_NONE;
1754 } else {
1755 endian = si_colorformat_endian_swap(format);
1756 }
1757
1758 /* blend clamp should be set for all NORM/SRGB types */
1759 if (ntype == V_028C70_NUMBER_UNORM ||
1760 ntype == V_028C70_NUMBER_SNORM ||
1761 ntype == V_028C70_NUMBER_SRGB)
1762 blend_clamp = 1;
1763
1764 /* set blend bypass according to docs if SINT/UINT or
1765 8/24 COLOR variants */
1766 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1767 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1768 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1769 blend_clamp = 0;
1770 blend_bypass = 1;
1771 }
1772
1773 color_info = S_028C70_FORMAT(format) |
1774 S_028C70_COMP_SWAP(swap) |
1775 S_028C70_BLEND_CLAMP(blend_clamp) |
1776 S_028C70_BLEND_BYPASS(blend_bypass) |
1777 S_028C70_NUMBER_TYPE(ntype) |
1778 S_028C70_ENDIAN(endian);
1779
1780 color_pitch = S_028C64_TILE_MAX(pitch);
1781
1782 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1783 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1784
1785 if (rtex->resource.b.b.nr_samples > 1) {
1786 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1787
1788 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1789 S_028C74_NUM_FRAGMENTS(log_samples);
1790
1791 if (rtex->fmask.size) {
1792 color_info |= S_028C70_COMPRESSION(1);
1793 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1794
1795 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1796
1797 if (sctx->b.chip_class == SI) {
1798 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1799 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1800 }
1801 if (sctx->b.chip_class >= CIK) {
1802 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1803 }
1804 }
1805 }
1806
1807 offset += rtex->resource.gpu_address;
1808
1809 surf->cb_color_base = offset >> 8;
1810 surf->cb_color_pitch = color_pitch;
1811 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1812 surf->cb_color_view = color_view;
1813 surf->cb_color_info = color_info;
1814 surf->cb_color_attrib = color_attrib;
1815
1816 if (rtex->fmask.size) {
1817 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1818 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1819 } else {
1820 /* This must be set for fast clear to work without FMASK. */
1821 surf->cb_color_fmask = surf->cb_color_base;
1822 surf->cb_color_fmask_slice = surf->cb_color_slice;
1823 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1824
1825 if (sctx->b.chip_class == SI) {
1826 unsigned bankh = util_logbase2(rtex->surface.bankh);
1827 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1828 }
1829
1830 if (sctx->b.chip_class >= CIK) {
1831 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1832 }
1833 }
1834
1835 /* Determine pixel shader export format */
1836 max_comp_size = si_colorformat_max_comp_size(format);
1837 if (ntype == V_028C70_NUMBER_SRGB ||
1838 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1839 max_comp_size <= 10) ||
1840 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1841 surf->export_16bpc = true;
1842 }
1843
1844 surf->color_initialized = true;
1845 }
1846
1847 static void si_init_depth_surface(struct si_context *sctx,
1848 struct r600_surface *surf)
1849 {
1850 struct si_screen *sscreen = sctx->screen;
1851 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1852 unsigned level = surf->base.u.tex.level;
1853 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1854 unsigned format, tile_mode_index, array_mode;
1855 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1856 uint32_t z_info, s_info, db_depth_info;
1857 uint64_t z_offs, s_offs;
1858 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1859
1860 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1861 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1862 case PIPE_FORMAT_X8Z24_UNORM:
1863 case PIPE_FORMAT_Z24X8_UNORM:
1864 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1865 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1866 break;
1867 case PIPE_FORMAT_Z32_FLOAT:
1868 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1869 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1870 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1871 break;
1872 case PIPE_FORMAT_Z16_UNORM:
1873 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1874 break;
1875 default:
1876 assert(0);
1877 }
1878
1879 format = si_translate_dbformat(rtex->resource.b.b.format);
1880
1881 if (format == V_028040_Z_INVALID) {
1882 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1883 }
1884 assert(format != V_028040_Z_INVALID);
1885
1886 s_offs = z_offs = rtex->resource.gpu_address;
1887 z_offs += rtex->surface.level[level].offset;
1888 s_offs += rtex->surface.stencil_level[level].offset;
1889
1890 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1891
1892 z_info = S_028040_FORMAT(format);
1893 if (rtex->resource.b.b.nr_samples > 1) {
1894 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1895 }
1896
1897 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1898 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1899 else
1900 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1901
1902 if (sctx->b.chip_class >= CIK) {
1903 switch (rtex->surface.level[level].mode) {
1904 case RADEON_SURF_MODE_2D:
1905 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1906 break;
1907 case RADEON_SURF_MODE_1D:
1908 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1909 case RADEON_SURF_MODE_LINEAR:
1910 default:
1911 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1912 break;
1913 }
1914 tile_split = rtex->surface.tile_split;
1915 stile_split = rtex->surface.stencil_tile_split;
1916 macro_aspect = rtex->surface.mtilea;
1917 bankw = rtex->surface.bankw;
1918 bankh = rtex->surface.bankh;
1919 tile_split = cik_tile_split(tile_split);
1920 stile_split = cik_tile_split(stile_split);
1921 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1922 bankw = cik_bank_wh(bankw);
1923 bankh = cik_bank_wh(bankh);
1924 nbanks = si_num_banks(sscreen, rtex);
1925 tile_mode_index = si_tile_mode_index(rtex, level, false);
1926 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1927
1928 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1929 S_02803C_PIPE_CONFIG(pipe_config) |
1930 S_02803C_BANK_WIDTH(bankw) |
1931 S_02803C_BANK_HEIGHT(bankh) |
1932 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1933 S_02803C_NUM_BANKS(nbanks);
1934 z_info |= S_028040_TILE_SPLIT(tile_split);
1935 s_info |= S_028044_TILE_SPLIT(stile_split);
1936 } else {
1937 tile_mode_index = si_tile_mode_index(rtex, level, false);
1938 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1939 tile_mode_index = si_tile_mode_index(rtex, level, true);
1940 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1941 }
1942
1943 /* HiZ aka depth buffer htile */
1944 /* use htile only for first level */
1945 if (rtex->htile_buffer && !level) {
1946 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1947 S_028040_ALLOW_EXPCLEAR(1);
1948
1949 /* This is optimal for the clear value of 1.0 and using
1950 * the LESS and LEQUAL test functions. Set this to 0
1951 * for the opposite case. This can only be changed when
1952 * clearing. */
1953 z_info |= S_028040_ZRANGE_PRECISION(1);
1954
1955 /* Use all of the htile_buffer for depth, because we don't
1956 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1957 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1958
1959 uint64_t va = rtex->htile_buffer->gpu_address;
1960 db_htile_data_base = va >> 8;
1961 db_htile_surface = S_028ABC_FULL_CACHE(1);
1962 } else {
1963 db_htile_data_base = 0;
1964 db_htile_surface = 0;
1965 }
1966
1967 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1968
1969 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1970 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1971 surf->db_htile_data_base = db_htile_data_base;
1972 surf->db_depth_info = db_depth_info;
1973 surf->db_z_info = z_info;
1974 surf->db_stencil_info = s_info;
1975 surf->db_depth_base = z_offs >> 8;
1976 surf->db_stencil_base = s_offs >> 8;
1977 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1978 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1979 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1980 levelinfo->nblk_y) / 64 - 1);
1981 surf->db_htile_surface = db_htile_surface;
1982 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1983
1984 surf->depth_initialized = true;
1985 }
1986
1987 static void si_set_framebuffer_state(struct pipe_context *ctx,
1988 const struct pipe_framebuffer_state *state)
1989 {
1990 struct si_context *sctx = (struct si_context *)ctx;
1991 struct pipe_constant_buffer constbuf = {0};
1992 struct r600_surface *surf = NULL;
1993 struct r600_texture *rtex;
1994 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
1995 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
1996 int i;
1997
1998 /* Only flush TC when changing the framebuffer state, because
1999 * the only client not using TC that can change textures is
2000 * the framebuffer.
2001 *
2002 * Flush all CB and DB caches here because all buffers can be used
2003 * for write by both TC (with shader image stores) and CB/DB.
2004 */
2005 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2006 SI_CONTEXT_INV_TC_L2 |
2007 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2008
2009 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2010
2011 sctx->framebuffer.export_16bpc = 0;
2012 sctx->framebuffer.compressed_cb_mask = 0;
2013 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2014 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2015 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2016 util_format_is_pure_integer(state->cbufs[0]->format);
2017
2018 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2019 sctx->db_render_state.dirty = true;
2020
2021 for (i = 0; i < state->nr_cbufs; i++) {
2022 if (!state->cbufs[i])
2023 continue;
2024
2025 surf = (struct r600_surface*)state->cbufs[i];
2026 rtex = (struct r600_texture*)surf->base.texture;
2027
2028 if (!surf->color_initialized) {
2029 si_initialize_color_surface(sctx, surf);
2030 }
2031
2032 if (surf->export_16bpc) {
2033 sctx->framebuffer.export_16bpc |= 1 << i;
2034 }
2035
2036 if (rtex->fmask.size && rtex->cmask.size) {
2037 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2038 }
2039 }
2040 /* Set the 16BPC export for possible dual-src blending. */
2041 if (i == 1 && surf && surf->export_16bpc) {
2042 sctx->framebuffer.export_16bpc |= 1 << 1;
2043 }
2044
2045 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2046
2047 if (state->zsbuf) {
2048 surf = (struct r600_surface*)state->zsbuf;
2049
2050 if (!surf->depth_initialized) {
2051 si_init_depth_surface(sctx, surf);
2052 }
2053 }
2054
2055 si_update_fb_rs_state(sctx);
2056 si_update_fb_blend_state(sctx);
2057
2058 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2059 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2060 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2061 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2062 sctx->framebuffer.atom.dirty = true;
2063
2064 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2065 sctx->msaa_config.dirty = true;
2066 sctx->db_render_state.dirty = true;
2067
2068 /* Set sample locations as fragment shader constants. */
2069 switch (sctx->framebuffer.nr_samples) {
2070 case 1:
2071 constbuf.user_buffer = sctx->b.sample_locations_1x;
2072 break;
2073 case 2:
2074 constbuf.user_buffer = sctx->b.sample_locations_2x;
2075 break;
2076 case 4:
2077 constbuf.user_buffer = sctx->b.sample_locations_4x;
2078 break;
2079 case 8:
2080 constbuf.user_buffer = sctx->b.sample_locations_8x;
2081 break;
2082 case 16:
2083 constbuf.user_buffer = sctx->b.sample_locations_16x;
2084 break;
2085 default:
2086 assert(0);
2087 }
2088 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2089 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2090 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2091 }
2092 }
2093
2094 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2095 {
2096 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2097 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2098 unsigned i, nr_cbufs = state->nr_cbufs;
2099 struct r600_texture *tex = NULL;
2100 struct r600_surface *cb = NULL;
2101
2102 /* Colorbuffers. */
2103 for (i = 0; i < nr_cbufs; i++) {
2104 cb = (struct r600_surface*)state->cbufs[i];
2105 if (!cb) {
2106 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2107 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2108 continue;
2109 }
2110
2111 tex = (struct r600_texture *)cb->base.texture;
2112 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2113 &tex->resource, RADEON_USAGE_READWRITE,
2114 tex->surface.nsamples > 1 ?
2115 RADEON_PRIO_COLOR_BUFFER_MSAA :
2116 RADEON_PRIO_COLOR_BUFFER);
2117
2118 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2119 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2120 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2121 RADEON_PRIO_COLOR_META);
2122 }
2123
2124 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2125 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2126 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2127 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2128 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2129 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2130 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2131 radeon_emit(cs, 0); /* R_028C78 unused */
2132 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2133 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2134 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2135 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2136 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2137 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2138 }
2139 /* set CB_COLOR1_INFO for possible dual-src blending */
2140 if (i == 1 && state->cbufs[0]) {
2141 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2142 cb->cb_color_info | tex->cb_color_info);
2143 i++;
2144 }
2145 for (; i < 8 ; i++) {
2146 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2147 }
2148
2149 /* ZS buffer. */
2150 if (state->zsbuf) {
2151 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2152 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2153
2154 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2155 &rtex->resource, RADEON_USAGE_READWRITE,
2156 zb->base.texture->nr_samples > 1 ?
2157 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2158 RADEON_PRIO_DEPTH_BUFFER);
2159
2160 if (zb->db_htile_data_base) {
2161 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2162 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2163 RADEON_PRIO_DEPTH_META);
2164 }
2165
2166 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2167 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2168
2169 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2170 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2171 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2172 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2173 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2174 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2175 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2176 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2177 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2178 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2179
2180 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2181 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2182 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2183 zb->pa_su_poly_offset_db_fmt_cntl);
2184 } else {
2185 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2186 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2187 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2188 }
2189
2190 /* Framebuffer dimensions. */
2191 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2192 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2193 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2194
2195 cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
2196 }
2197
2198 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2199 {
2200 struct si_context *sctx = (struct si_context *)rctx;
2201 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2202
2203 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2204 sctx->ps_iter_samples);
2205 }
2206
2207 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2208
2209 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2210 {
2211 struct si_context *sctx = (struct si_context *)ctx;
2212
2213 if (sctx->ps_iter_samples == min_samples)
2214 return;
2215
2216 sctx->ps_iter_samples = min_samples;
2217
2218 if (sctx->framebuffer.nr_samples > 1)
2219 sctx->msaa_config.dirty = true;
2220 }
2221
2222 /*
2223 * Samplers
2224 */
2225
2226 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2227 struct pipe_resource *texture,
2228 const struct pipe_sampler_view *state)
2229 {
2230 struct si_context *sctx = (struct si_context*)ctx;
2231 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2232 struct r600_texture *tmp = (struct r600_texture*)texture;
2233 const struct util_format_description *desc;
2234 unsigned format, num_format;
2235 uint32_t pitch = 0;
2236 unsigned char state_swizzle[4], swizzle[4];
2237 unsigned height, depth, width;
2238 enum pipe_format pipe_format = state->format;
2239 struct radeon_surface_level *surflevel;
2240 int first_non_void;
2241 uint64_t va;
2242
2243 if (view == NULL)
2244 return NULL;
2245
2246 /* initialize base object */
2247 view->base = *state;
2248 view->base.texture = NULL;
2249 pipe_resource_reference(&view->base.texture, texture);
2250 view->base.reference.count = 1;
2251 view->base.context = ctx;
2252 view->resource = &tmp->resource;
2253
2254 /* Buffer resource. */
2255 if (texture->target == PIPE_BUFFER) {
2256 unsigned stride;
2257
2258 desc = util_format_description(state->format);
2259 first_non_void = util_format_get_first_non_void_channel(state->format);
2260 stride = desc->block.bits / 8;
2261 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2262 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2263 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2264
2265 view->state[0] = va;
2266 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2267 S_008F04_STRIDE(stride);
2268 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2269 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2270 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2271 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2272 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2273 S_008F0C_NUM_FORMAT(num_format) |
2274 S_008F0C_DATA_FORMAT(format);
2275
2276 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2277 return &view->base;
2278 }
2279
2280 state_swizzle[0] = state->swizzle_r;
2281 state_swizzle[1] = state->swizzle_g;
2282 state_swizzle[2] = state->swizzle_b;
2283 state_swizzle[3] = state->swizzle_a;
2284
2285 surflevel = tmp->surface.level;
2286
2287 /* Texturing with separate depth and stencil. */
2288 if (tmp->is_depth && !tmp->is_flushing_texture) {
2289 switch (pipe_format) {
2290 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2291 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2292 break;
2293 case PIPE_FORMAT_X8Z24_UNORM:
2294 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2295 /* Z24 is always stored like this. */
2296 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2297 break;
2298 case PIPE_FORMAT_X24S8_UINT:
2299 case PIPE_FORMAT_S8X24_UINT:
2300 case PIPE_FORMAT_X32_S8X24_UINT:
2301 pipe_format = PIPE_FORMAT_S8_UINT;
2302 surflevel = tmp->surface.stencil_level;
2303 break;
2304 default:;
2305 }
2306 }
2307
2308 desc = util_format_description(pipe_format);
2309
2310 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2311 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2312 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2313
2314 switch (pipe_format) {
2315 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2316 case PIPE_FORMAT_X24S8_UINT:
2317 case PIPE_FORMAT_X32_S8X24_UINT:
2318 case PIPE_FORMAT_X8Z24_UNORM:
2319 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2320 break;
2321 default:
2322 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2323 }
2324 } else {
2325 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2326 }
2327
2328 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2329
2330 switch (pipe_format) {
2331 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2332 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2333 break;
2334 default:
2335 if (first_non_void < 0) {
2336 if (util_format_is_compressed(pipe_format)) {
2337 switch (pipe_format) {
2338 case PIPE_FORMAT_DXT1_SRGB:
2339 case PIPE_FORMAT_DXT1_SRGBA:
2340 case PIPE_FORMAT_DXT3_SRGBA:
2341 case PIPE_FORMAT_DXT5_SRGBA:
2342 case PIPE_FORMAT_BPTC_SRGBA:
2343 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2344 break;
2345 case PIPE_FORMAT_RGTC1_SNORM:
2346 case PIPE_FORMAT_LATC1_SNORM:
2347 case PIPE_FORMAT_RGTC2_SNORM:
2348 case PIPE_FORMAT_LATC2_SNORM:
2349 /* implies float, so use SNORM/UNORM to determine
2350 whether data is signed or not */
2351 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2352 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2353 break;
2354 default:
2355 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2356 break;
2357 }
2358 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2359 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2360 } else {
2361 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2362 }
2363 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2364 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2365 } else {
2366 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2367
2368 switch (desc->channel[first_non_void].type) {
2369 case UTIL_FORMAT_TYPE_FLOAT:
2370 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2371 break;
2372 case UTIL_FORMAT_TYPE_SIGNED:
2373 if (desc->channel[first_non_void].normalized)
2374 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2375 else if (desc->channel[first_non_void].pure_integer)
2376 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2377 else
2378 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2379 break;
2380 case UTIL_FORMAT_TYPE_UNSIGNED:
2381 if (desc->channel[first_non_void].normalized)
2382 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2383 else if (desc->channel[first_non_void].pure_integer)
2384 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2385 else
2386 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2387 }
2388 }
2389 }
2390
2391 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2392 if (format == ~0) {
2393 format = 0;
2394 }
2395
2396 /* not supported any more */
2397 //endian = si_colorformat_endian_swap(format);
2398
2399 width = surflevel[0].npix_x;
2400 height = surflevel[0].npix_y;
2401 depth = surflevel[0].npix_z;
2402 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2403
2404 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2405 height = 1;
2406 depth = texture->array_size;
2407 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2408 depth = texture->array_size;
2409 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2410 depth = texture->array_size / 6;
2411
2412 va = tmp->resource.gpu_address + surflevel[0].offset;
2413 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2414
2415 view->state[0] = va >> 8;
2416 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2417 S_008F14_DATA_FORMAT(format) |
2418 S_008F14_NUM_FORMAT(num_format));
2419 view->state[2] = (S_008F18_WIDTH(width - 1) |
2420 S_008F18_HEIGHT(height - 1));
2421 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2422 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2423 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2424 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2425 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2426 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2427 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2428 util_logbase2(texture->nr_samples) :
2429 state->u.tex.last_level - tmp->mipmap_shift) |
2430 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2431 S_008F1C_POW2_PAD(texture->last_level > 0) |
2432 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2433 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2434 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2435 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2436 view->state[6] = 0;
2437 view->state[7] = 0;
2438
2439 /* Initialize the sampler view for FMASK. */
2440 if (tmp->fmask.size) {
2441 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2442 uint32_t fmask_format;
2443
2444 switch (texture->nr_samples) {
2445 case 2:
2446 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2447 break;
2448 case 4:
2449 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2450 break;
2451 case 8:
2452 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2453 break;
2454 default:
2455 assert(0);
2456 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2457 }
2458
2459 view->fmask_state[0] = va >> 8;
2460 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2461 S_008F14_DATA_FORMAT(fmask_format) |
2462 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2463 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2464 S_008F18_HEIGHT(height - 1);
2465 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2466 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2467 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2468 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2469 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2470 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2471 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2472 S_008F20_PITCH(tmp->fmask.pitch - 1);
2473 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2474 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2475 view->fmask_state[6] = 0;
2476 view->fmask_state[7] = 0;
2477 }
2478
2479 return &view->base;
2480 }
2481
2482 static void si_sampler_view_destroy(struct pipe_context *ctx,
2483 struct pipe_sampler_view *state)
2484 {
2485 struct si_sampler_view *view = (struct si_sampler_view *)state;
2486
2487 if (view->resource->b.b.target == PIPE_BUFFER)
2488 LIST_DELINIT(&view->list);
2489
2490 pipe_resource_reference(&state->texture, NULL);
2491 FREE(view);
2492 }
2493
2494 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2495 {
2496 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2497 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2498 (linear_filter &&
2499 (wrap == PIPE_TEX_WRAP_CLAMP ||
2500 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2501 }
2502
2503 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2504 {
2505 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2506 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2507
2508 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2509 state->border_color.ui[2] || state->border_color.ui[3]) &&
2510 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2511 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2512 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2513 }
2514
2515 static void *si_create_sampler_state(struct pipe_context *ctx,
2516 const struct pipe_sampler_state *state)
2517 {
2518 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2519 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2520 unsigned border_color_type;
2521
2522 if (rstate == NULL) {
2523 return NULL;
2524 }
2525
2526 if (sampler_state_needs_border_color(state))
2527 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2528 else
2529 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2530
2531 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2532 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2533 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2534 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2535 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2536 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2537 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2538 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2539 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2540 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2541 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2542 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2543 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2544 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2545
2546 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2547 memcpy(rstate->border_color, state->border_color.ui,
2548 sizeof(rstate->border_color));
2549 }
2550
2551 return rstate;
2552 }
2553
2554 /* Upload border colors and update the pointers in resource descriptors.
2555 * There can only be 4096 border colors per context.
2556 *
2557 * XXX: This is broken if the buffer gets reallocated.
2558 */
2559 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2560 void **states)
2561 {
2562 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2563 uint32_t *border_color_table = NULL;
2564 int i, j;
2565
2566 for (i = 0; i < count; i++) {
2567 if (rstates[i] &&
2568 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2569 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2570 if (!sctx->border_color_table ||
2571 ((sctx->border_color_offset + count - i) &
2572 C_008F3C_BORDER_COLOR_PTR)) {
2573 r600_resource_reference(&sctx->border_color_table, NULL);
2574 sctx->border_color_offset = 0;
2575
2576 sctx->border_color_table =
2577 si_resource_create_custom(&sctx->screen->b.b,
2578 PIPE_USAGE_DYNAMIC,
2579 4096 * 4 * 4);
2580 }
2581
2582 if (!border_color_table) {
2583 border_color_table =
2584 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2585 sctx->b.rings.gfx.cs,
2586 PIPE_TRANSFER_WRITE |
2587 PIPE_TRANSFER_UNSYNCHRONIZED);
2588 }
2589
2590 for (j = 0; j < 4; j++) {
2591 border_color_table[4 * sctx->border_color_offset + j] =
2592 util_le32_to_cpu(rstates[i]->border_color[j]);
2593 }
2594
2595 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2596 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2597 }
2598 }
2599
2600 if (border_color_table) {
2601 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2602
2603 uint64_t va_offset = sctx->border_color_table->gpu_address;
2604
2605 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2606 if (sctx->b.chip_class >= CIK)
2607 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2608 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2609 RADEON_PRIO_SHADER_DATA);
2610 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2611 }
2612 }
2613
2614 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2615 unsigned start, unsigned count,
2616 void **states)
2617 {
2618 struct si_context *sctx = (struct si_context *)ctx;
2619
2620 if (!count || shader >= SI_NUM_SHADERS)
2621 return;
2622
2623 si_set_border_colors(sctx, count, states);
2624 si_set_sampler_descriptors(sctx, shader, start, count, states);
2625 }
2626
2627 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2628 {
2629 struct si_context *sctx = (struct si_context *)ctx;
2630 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2631 struct si_pm4_state *pm4 = &state->pm4;
2632 uint16_t mask = sample_mask;
2633
2634 if (state == NULL)
2635 return;
2636
2637 state->sample_mask = mask;
2638 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2639 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2640
2641 si_pm4_set_state(sctx, sample_mask, state);
2642 }
2643
2644 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2645 {
2646 free(state);
2647 }
2648
2649 /*
2650 * Vertex elements & buffers
2651 */
2652
2653 static void *si_create_vertex_elements(struct pipe_context *ctx,
2654 unsigned count,
2655 const struct pipe_vertex_element *elements)
2656 {
2657 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2658 int i;
2659
2660 assert(count < PIPE_MAX_ATTRIBS);
2661 if (!v)
2662 return NULL;
2663
2664 v->count = count;
2665 for (i = 0; i < count; ++i) {
2666 const struct util_format_description *desc;
2667 unsigned data_format, num_format;
2668 int first_non_void;
2669
2670 desc = util_format_description(elements[i].src_format);
2671 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2672 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2673 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2674
2675 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2676 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2677 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2678 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2679 S_008F0C_NUM_FORMAT(num_format) |
2680 S_008F0C_DATA_FORMAT(data_format);
2681 v->format_size[i] = desc->block.bits / 8;
2682 }
2683 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2684
2685 return v;
2686 }
2687
2688 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2689 {
2690 struct si_context *sctx = (struct si_context *)ctx;
2691 struct si_vertex_element *v = (struct si_vertex_element*)state;
2692
2693 sctx->vertex_elements = v;
2694 sctx->vertex_buffers_dirty = true;
2695 }
2696
2697 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2698 {
2699 struct si_context *sctx = (struct si_context *)ctx;
2700
2701 if (sctx->vertex_elements == state)
2702 sctx->vertex_elements = NULL;
2703 FREE(state);
2704 }
2705
2706 static void si_set_vertex_buffers(struct pipe_context *ctx,
2707 unsigned start_slot, unsigned count,
2708 const struct pipe_vertex_buffer *buffers)
2709 {
2710 struct si_context *sctx = (struct si_context *)ctx;
2711 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2712 int i;
2713
2714 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2715
2716 if (buffers) {
2717 for (i = 0; i < count; i++) {
2718 const struct pipe_vertex_buffer *src = buffers + i;
2719 struct pipe_vertex_buffer *dsti = dst + i;
2720
2721 pipe_resource_reference(&dsti->buffer, src->buffer);
2722 dsti->buffer_offset = src->buffer_offset;
2723 dsti->stride = src->stride;
2724 }
2725 } else {
2726 for (i = 0; i < count; i++) {
2727 pipe_resource_reference(&dst[i].buffer, NULL);
2728 }
2729 }
2730 sctx->vertex_buffers_dirty = true;
2731 }
2732
2733 static void si_set_index_buffer(struct pipe_context *ctx,
2734 const struct pipe_index_buffer *ib)
2735 {
2736 struct si_context *sctx = (struct si_context *)ctx;
2737
2738 if (ib) {
2739 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2740 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2741 } else {
2742 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2743 }
2744 }
2745
2746 /*
2747 * Misc
2748 */
2749 static void si_set_polygon_stipple(struct pipe_context *ctx,
2750 const struct pipe_poly_stipple *state)
2751 {
2752 }
2753
2754 static void si_texture_barrier(struct pipe_context *ctx)
2755 {
2756 struct si_context *sctx = (struct si_context *)ctx;
2757
2758 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2759 SI_CONTEXT_INV_TC_L2 |
2760 SI_CONTEXT_FLUSH_AND_INV_CB;
2761 }
2762
2763 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2764 {
2765 struct pipe_blend_state blend;
2766
2767 memset(&blend, 0, sizeof(blend));
2768 blend.independent_blend_enable = true;
2769 blend.rt[0].colormask = 0xf;
2770 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2771 }
2772
2773 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2774 bool include_draw_vbo)
2775 {
2776 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2777 }
2778
2779 void si_init_state_functions(struct si_context *sctx)
2780 {
2781 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2782 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2783 si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
2784
2785 sctx->b.b.create_blend_state = si_create_blend_state;
2786 sctx->b.b.bind_blend_state = si_bind_blend_state;
2787 sctx->b.b.delete_blend_state = si_delete_blend_state;
2788 sctx->b.b.set_blend_color = si_set_blend_color;
2789
2790 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2791 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2792 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2793
2794 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2795 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2796 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2797
2798 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2799 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2800 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2801 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2802
2803 sctx->b.b.set_clip_state = si_set_clip_state;
2804 sctx->b.b.set_scissor_states = si_set_scissor_states;
2805 sctx->b.b.set_viewport_states = si_set_viewport_states;
2806 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2807
2808 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2809 sctx->b.b.get_sample_position = cayman_get_sample_position;
2810
2811 sctx->b.b.create_sampler_state = si_create_sampler_state;
2812 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2813 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2814
2815 sctx->b.b.create_sampler_view = si_create_sampler_view;
2816 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2817
2818 sctx->b.b.set_sample_mask = si_set_sample_mask;
2819
2820 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2821 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2822 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2823 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2824 sctx->b.b.set_index_buffer = si_set_index_buffer;
2825
2826 sctx->b.b.texture_barrier = si_texture_barrier;
2827 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2828 sctx->b.b.set_min_samples = si_set_min_samples;
2829
2830 sctx->b.dma_copy = si_dma_copy;
2831 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2832 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2833
2834 sctx->b.b.draw_vbo = si_draw_vbo;
2835 }
2836
2837 static void
2838 si_write_harvested_raster_configs(struct si_context *sctx,
2839 struct si_pm4_state *pm4,
2840 unsigned raster_config)
2841 {
2842 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
2843 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
2844 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2845 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2846 unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
2847 unsigned rb_per_se = num_rb / num_se;
2848 unsigned se0_mask = (1 << rb_per_se) - 1;
2849 unsigned se1_mask = se0_mask << rb_per_se;
2850 unsigned se;
2851
2852 assert(num_se == 1 || num_se == 2);
2853 assert(sh_per_se == 1 || sh_per_se == 2);
2854 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
2855
2856 /* XXX: I can't figure out what the *_XSEL and *_YSEL
2857 * fields are for, so I'm leaving them as their default
2858 * values. */
2859
2860 se0_mask &= rb_mask;
2861 se1_mask &= rb_mask;
2862 if (num_se == 2 && (!se0_mask || !se1_mask)) {
2863 raster_config &= C_028350_SE_MAP;
2864
2865 if (!se0_mask) {
2866 raster_config |=
2867 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
2868 } else {
2869 raster_config |=
2870 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
2871 }
2872 }
2873
2874 for (se = 0; se < num_se; se++) {
2875 unsigned raster_config_se = raster_config;
2876 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
2877 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
2878
2879 pkr0_mask &= rb_mask;
2880 pkr1_mask &= rb_mask;
2881 if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
2882 raster_config_se &= C_028350_PKR_MAP;
2883
2884 if (!pkr0_mask) {
2885 raster_config_se |=
2886 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
2887 } else {
2888 raster_config_se |=
2889 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
2890 }
2891 }
2892
2893 if (rb_per_pkr == 2) {
2894 unsigned rb0_mask = 1 << (se * rb_per_se);
2895 unsigned rb1_mask = rb0_mask << 1;
2896
2897 rb0_mask &= rb_mask;
2898 rb1_mask &= rb_mask;
2899 if (!rb0_mask || !rb1_mask) {
2900 raster_config_se &= C_028350_RB_MAP_PKR0;
2901
2902 if (!rb0_mask) {
2903 raster_config_se |=
2904 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
2905 } else {
2906 raster_config_se |=
2907 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
2908 }
2909 }
2910
2911 if (sh_per_se == 2) {
2912 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
2913 rb1_mask = rb0_mask << 1;
2914 rb0_mask &= rb_mask;
2915 rb1_mask &= rb_mask;
2916 if (!rb0_mask || !rb1_mask) {
2917 raster_config_se &= C_028350_RB_MAP_PKR1;
2918
2919 if (!rb0_mask) {
2920 raster_config_se |=
2921 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
2922 } else {
2923 raster_config_se |=
2924 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
2925 }
2926 }
2927 }
2928 }
2929
2930 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
2931 SE_INDEX(se) | SH_BROADCAST_WRITES |
2932 INSTANCE_BROADCAST_WRITES);
2933 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
2934 }
2935
2936 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
2937 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
2938 INSTANCE_BROADCAST_WRITES);
2939 }
2940
2941 void si_init_config(struct si_context *sctx)
2942 {
2943 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2944
2945 if (pm4 == NULL)
2946 return;
2947
2948 si_cmd_context_control(pm4);
2949
2950 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2951 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2952 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2953 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2954 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2955 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2956 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2957 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2958 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2959 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2960 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2961 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2962
2963 /* FIXME calculate these values somehow ??? */
2964 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
2965 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
2966 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
2967
2968 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2969 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2970 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
2971 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2972
2973 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
2974 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
2975 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
2976 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
2977
2978 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2979 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2980 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2981 if (sctx->b.chip_class < CIK)
2982 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2983 S_008A14_CLIP_VTX_REORDER_ENA(1));
2984
2985 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2986 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2987
2988 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2989
2990 if (sctx->b.chip_class >= CIK) {
2991 switch (sctx->screen->b.family) {
2992 case CHIP_BONAIRE:
2993 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
2994 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
2995 break;
2996 case CHIP_HAWAII:
2997 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
2998 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
2999 break;
3000 case CHIP_KAVERI:
3001 /* XXX todo */
3002 case CHIP_KABINI:
3003 /* XXX todo */
3004 case CHIP_MULLINS:
3005 /* XXX todo */
3006 default:
3007 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3008 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3009 break;
3010 }
3011 } else {
3012 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3013 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
3014 unsigned raster_config;
3015
3016 switch (sctx->screen->b.family) {
3017 case CHIP_TAHITI:
3018 case CHIP_PITCAIRN:
3019 raster_config = 0x2a00126a;
3020 break;
3021 case CHIP_VERDE:
3022 raster_config = 0x0000124a;
3023 break;
3024 case CHIP_OLAND:
3025 raster_config = 0x00000082;
3026 break;
3027 case CHIP_HAINAN:
3028 raster_config = 0x00000000;
3029 break;
3030 default:
3031 fprintf(stderr,
3032 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3033 raster_config = 0x00000000;
3034 break;
3035 }
3036
3037 /* Always use the default config when all backends are enabled
3038 * (or when we failed to determine the enabled backends).
3039 */
3040 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3041 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3042 raster_config);
3043 } else {
3044 si_write_harvested_raster_configs(sctx, pm4, raster_config);
3045 }
3046 }
3047
3048 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3049 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3050 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3051 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3052 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3053 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3054 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3055
3056 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3057 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3058 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3059 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3060 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3061 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3062 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3063 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3064 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3065 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3066 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3067 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3068 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3069 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3070 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3071
3072 /* There is a hang if stencil is used and fast stencil is enabled
3073 * regardless of whether HTILE is depth-only or not.
3074 */
3075 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3076 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3077 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3078 S_02800C_FAST_STENCIL_DISABLE(1));
3079
3080 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3081 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3082 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3083
3084 if (sctx->b.chip_class >= CIK) {
3085 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3086 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3087 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3088 }
3089
3090 sctx->init_config = pm4;
3091 }