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radeonsi: emit_clip_state packets optimization
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_winsys_cs *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
91 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
92
93 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
94 * I think we don't have to do anything between IBs.
95 */
96 if (sctx->screen->dfsm_allowed &&
97 sctx->last_cb_target_mask != cb_target_mask) {
98 sctx->last_cb_target_mask = cb_target_mask;
99
100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
102 }
103
104 if (sctx->chip_class >= VI) {
105 /* DCC MSAA workaround for blending.
106 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
107 * COMBINER_DISABLE, but that would be more complicated.
108 */
109 bool oc_disable = (sctx->chip_class == VI ||
110 sctx->chip_class == GFX9) &&
111 blend &&
112 blend->blend_enable_4bit & cb_target_mask &&
113 sctx->framebuffer.nr_samples >= 2;
114
115 radeon_opt_set_context_reg(
116 sctx, R_028424_CB_DCC_CONTROL,
117 SI_TRACKED_CB_DCC_CONTROL,
118 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
119 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
120 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
121 }
122
123 /* RB+ register settings. */
124 if (sctx->screen->rbplus_allowed) {
125 unsigned spi_shader_col_format =
126 sctx->ps_shader.cso ?
127 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
128 unsigned sx_ps_downconvert = 0;
129 unsigned sx_blend_opt_epsilon = 0;
130 unsigned sx_blend_opt_control = 0;
131
132 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
133 struct r600_surface *surf =
134 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
135 unsigned format, swap, spi_format, colormask;
136 bool has_alpha, has_rgb;
137
138 if (!surf)
139 continue;
140
141 format = G_028C70_FORMAT(surf->cb_color_info);
142 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
143 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
144 colormask = (cb_target_mask >> (i * 4)) & 0xf;
145
146 /* Set if RGB and A are present. */
147 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
148
149 if (format == V_028C70_COLOR_8 ||
150 format == V_028C70_COLOR_16 ||
151 format == V_028C70_COLOR_32)
152 has_rgb = !has_alpha;
153 else
154 has_rgb = true;
155
156 /* Check the colormask and export format. */
157 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
158 has_rgb = false;
159 if (!(colormask & PIPE_MASK_A))
160 has_alpha = false;
161
162 if (spi_format == V_028714_SPI_SHADER_ZERO) {
163 has_rgb = false;
164 has_alpha = false;
165 }
166
167 /* Disable value checking for disabled channels. */
168 if (!has_rgb)
169 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
170 if (!has_alpha)
171 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
172
173 /* Enable down-conversion for 32bpp and smaller formats. */
174 switch (format) {
175 case V_028C70_COLOR_8:
176 case V_028C70_COLOR_8_8:
177 case V_028C70_COLOR_8_8_8_8:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
180 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
182 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
183 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
184 }
185 break;
186
187 case V_028C70_COLOR_5_6_5:
188 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
189 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
190 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
191 }
192 break;
193
194 case V_028C70_COLOR_1_5_5_5:
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
196 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
197 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
198 }
199 break;
200
201 case V_028C70_COLOR_4_4_4_4:
202 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
203 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
204 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
205 }
206 break;
207
208 case V_028C70_COLOR_32:
209 if (swap == V_028C70_SWAP_STD &&
210 spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV &&
213 spi_format == V_028714_SPI_SHADER_32_AR)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
215 break;
216
217 case V_028C70_COLOR_16:
218 case V_028C70_COLOR_16_16:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
224 if (swap == V_028C70_SWAP_STD ||
225 swap == V_028C70_SWAP_STD_REV)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
227 else
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
229 }
230 break;
231
232 case V_028C70_COLOR_10_11_11:
233 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
235 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
236 }
237 break;
238
239 case V_028C70_COLOR_2_10_10_10:
240 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
242 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
243 }
244 break;
245 }
246 }
247
248 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
249 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
250 SI_TRACKED_SX_PS_DOWNCONVERT,
251 sx_ps_downconvert, sx_blend_opt_epsilon,
252 sx_blend_opt_control);
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 PRINT_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 static void si_blend_check_commutativity(struct si_screen *sscreen,
374 struct si_state_blend *blend,
375 enum pipe_blend_func func,
376 enum pipe_blendfactor src,
377 enum pipe_blendfactor dst,
378 unsigned chanmask)
379 {
380 /* Src factor is allowed when it does not depend on Dst */
381 static const uint32_t src_allowed =
382 (1u << PIPE_BLENDFACTOR_ONE) |
383 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
384 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
386 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
387 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
389 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
397
398 if (dst == PIPE_BLENDFACTOR_ONE &&
399 (src_allowed & (1u << src))) {
400 /* Addition is commutative, but floating point addition isn't
401 * associative: subtle changes can be introduced via different
402 * rounding.
403 *
404 * Out-of-order is also non-deterministic, which means that
405 * this breaks OpenGL invariance requirements. So only enable
406 * out-of-order additive blending if explicitly allowed by a
407 * setting.
408 */
409 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
410 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
411 blend->commutative_4bit |= chanmask;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
425 *src_factor = PIPE_BLENDFACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == PIPE_BLEND_SUBTRACT)
430 *func = PIPE_BLEND_REVERSE_SUBTRACT;
431 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
432 *func = PIPE_BLEND_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
439 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
440 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
441 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
442 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
443 }
444
445 static void *si_create_blend_state_mode(struct pipe_context *ctx,
446 const struct pipe_blend_state *state,
447 unsigned mode)
448 {
449 struct si_context *sctx = (struct si_context*)ctx;
450 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
451 struct si_pm4_state *pm4 = &blend->pm4;
452 uint32_t sx_mrt_blend_opt[8] = {0};
453 uint32_t color_control = 0;
454
455 if (!blend)
456 return NULL;
457
458 blend->alpha_to_coverage = state->alpha_to_coverage;
459 blend->alpha_to_one = state->alpha_to_one;
460 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
461 blend->logicop_enable = state->logicop_enable;
462
463 if (state->logicop_enable) {
464 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
465 } else {
466 color_control |= S_028808_ROP3(0xcc);
467 }
468
469 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
472 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
475
476 if (state->alpha_to_coverage)
477 blend->need_src_alpha_4bit |= 0xf;
478
479 blend->cb_target_mask = 0;
480 blend->cb_target_enabled_4bit = 0;
481
482 for (int i = 0; i < 8; i++) {
483 /* state->rt entries > 0 only written if independent blending */
484 const int j = state->independent_blend_enable ? i : 0;
485
486 unsigned eqRGB = state->rt[j].rgb_func;
487 unsigned srcRGB = state->rt[j].rgb_src_factor;
488 unsigned dstRGB = state->rt[j].rgb_dst_factor;
489 unsigned eqA = state->rt[j].alpha_func;
490 unsigned srcA = state->rt[j].alpha_src_factor;
491 unsigned dstA = state->rt[j].alpha_dst_factor;
492
493 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
494 unsigned blend_cntl = 0;
495
496 sx_mrt_blend_opt[i] =
497 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
498 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
499
500 /* Only set dual source blending for MRT0 to avoid a hang. */
501 if (i >= 1 && blend->dual_src_blend) {
502 /* Vulkan does this for dual source blending. */
503 if (i == 1)
504 blend_cntl |= S_028780_ENABLE(1);
505
506 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
507 continue;
508 }
509
510 /* Only addition and subtraction equations are supported with
511 * dual source blending.
512 */
513 if (blend->dual_src_blend &&
514 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
515 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
518 continue;
519 }
520
521 /* cb_render_state will disable unused ones */
522 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
523 if (state->rt[j].colormask)
524 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
525
526 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 si_blend_check_commutativity(sctx->screen, blend,
532 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
533 si_blend_check_commutativity(sctx->screen, blend,
534 eqA, srcA, dstA, 0x8 << (4 * i));
535
536 /* Blending optimizations for RB+.
537 * These transformations don't change the behavior.
538 *
539 * First, get rid of DST in the blend factors:
540 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
541 */
542 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
543 PIPE_BLENDFACTOR_DST_COLOR,
544 PIPE_BLENDFACTOR_SRC_COLOR);
545 si_blend_remove_dst(&eqA, &srcA, &dstA,
546 PIPE_BLENDFACTOR_DST_COLOR,
547 PIPE_BLENDFACTOR_SRC_COLOR);
548 si_blend_remove_dst(&eqA, &srcA, &dstA,
549 PIPE_BLENDFACTOR_DST_ALPHA,
550 PIPE_BLENDFACTOR_SRC_ALPHA);
551
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
554 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
555 srcA_opt = si_translate_blend_opt_factor(srcA, true);
556 dstA_opt = si_translate_blend_opt_factor(dstA, true);
557
558 /* Handle interdependencies. */
559 if (si_blend_factor_uses_dst(srcRGB))
560 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
561 if (si_blend_factor_uses_dst(srcA))
562 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
563
564 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
565 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
566 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
567 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
568 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
569
570 /* Set the final value. */
571 sx_mrt_blend_opt[i] =
572 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
573 S_028760_COLOR_DST_OPT(dstRGB_opt) |
574 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
575 S_028760_ALPHA_SRC_OPT(srcA_opt) |
576 S_028760_ALPHA_DST_OPT(dstA_opt) |
577 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
578
579 /* Set blend state. */
580 blend_cntl |= S_028780_ENABLE(1);
581 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
582 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
583 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
584
585 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
586 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
587 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
588 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
589 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
590 }
591 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
592
593 blend->blend_enable_4bit |= 0xfu << (i * 4);
594
595 /* This is only important for formats without alpha. */
596 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
598 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
599 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
600 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
601 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
602 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
603 }
604
605 if (blend->cb_target_mask) {
606 color_control |= S_028808_MODE(mode);
607 } else {
608 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
609 }
610
611 if (sctx->screen->rbplus_allowed) {
612 /* Disable RB+ blend optimizations for dual source blending.
613 * Vulkan does this.
614 */
615 if (blend->dual_src_blend) {
616 for (int i = 0; i < 8; i++) {
617 sx_mrt_blend_opt[i] =
618 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
620 }
621 }
622
623 for (int i = 0; i < 8; i++)
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
625 sx_mrt_blend_opt[i]);
626
627 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
628 if (blend->dual_src_blend || state->logicop_enable ||
629 mode == V_028808_CB_RESOLVE)
630 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
631 }
632
633 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
634 return blend;
635 }
636
637 static void *si_create_blend_state(struct pipe_context *ctx,
638 const struct pipe_blend_state *state)
639 {
640 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
641 }
642
643 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 struct si_state_blend *old_blend = sctx->queued.named.blend;
647 struct si_state_blend *blend = (struct si_state_blend *)state;
648
649 if (!state)
650 return;
651
652 si_pm4_bind_state(sctx, blend, state);
653
654 if (!old_blend ||
655 old_blend->cb_target_mask != blend->cb_target_mask ||
656 old_blend->dual_src_blend != blend->dual_src_blend ||
657 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
658 sctx->framebuffer.nr_samples >= 2 &&
659 sctx->screen->dcc_msaa_allowed))
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
661
662 if (!old_blend ||
663 old_blend->cb_target_mask != blend->cb_target_mask ||
664 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
665 old_blend->alpha_to_one != blend->alpha_to_one ||
666 old_blend->dual_src_blend != blend->dual_src_blend ||
667 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
668 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
669 sctx->do_update_shaders = true;
670
671 if (sctx->screen->dpbb_allowed &&
672 (!old_blend ||
673 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
676 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
677
678 if (sctx->screen->has_out_of_order_rast &&
679 (!old_blend ||
680 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
681 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
682 old_blend->commutative_4bit != blend->commutative_4bit ||
683 old_blend->logicop_enable != blend->logicop_enable)))
684 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
685 }
686
687 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
691 }
692
693 static void si_set_blend_color(struct pipe_context *ctx,
694 const struct pipe_blend_color *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 static const struct pipe_blend_color zeros;
698
699 sctx->blend_color.state = *state;
700 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
701 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
702 }
703
704 static void si_emit_blend_color(struct si_context *sctx)
705 {
706 struct radeon_winsys_cs *cs = sctx->gfx_cs;
707
708 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
709 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
710 }
711
712 /*
713 * Clipping
714 */
715
716 static void si_set_clip_state(struct pipe_context *ctx,
717 const struct pipe_clip_state *state)
718 {
719 struct si_context *sctx = (struct si_context *)ctx;
720 struct pipe_constant_buffer cb;
721 static const struct pipe_clip_state zeros;
722
723 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
724 return;
725
726 sctx->clip_state.state = *state;
727 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
728 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
729
730 cb.buffer = NULL;
731 cb.user_buffer = state->ucp;
732 cb.buffer_offset = 0;
733 cb.buffer_size = 4*4*8;
734 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
735 pipe_resource_reference(&cb.buffer, NULL);
736 }
737
738 static void si_emit_clip_state(struct si_context *sctx)
739 {
740 struct radeon_winsys_cs *cs = sctx->gfx_cs;
741
742 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
743 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
744 }
745
746 static void si_emit_clip_regs(struct si_context *sctx)
747 {
748 struct si_shader *vs = si_get_vs_state(sctx);
749 struct si_shader_selector *vs_sel = vs->selector;
750 struct tgsi_shader_info *info = &vs_sel->info;
751 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
752 unsigned window_space =
753 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
754 unsigned clipdist_mask = vs_sel->clipdist_mask;
755 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
756 unsigned culldist_mask = vs_sel->culldist_mask;
757 unsigned total_mask;
758
759 if (vs->key.opt.clip_disable) {
760 assert(!info->culldist_writemask);
761 clipdist_mask = 0;
762 culldist_mask = 0;
763 }
764 total_mask = clipdist_mask | culldist_mask;
765
766 /* Clip distances on points have no effect, so need to be implemented
767 * as cull distances. This applies for the clipvertex case as well.
768 *
769 * Setting this for primitives other than points should have no adverse
770 * effects.
771 */
772 clipdist_mask &= rs->clip_plane_enable;
773 culldist_mask |= clipdist_mask;
774
775 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
776 SI_TRACKED_PA_CL_VS_OUT_CNTL,
777 vs_sel->pa_cl_vs_out_cntl |
778 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
779 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
780 clipdist_mask | (culldist_mask << 8));
781 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
782 SI_TRACKED_PA_CL_CLIP_CNTL,
783 rs->pa_cl_clip_cntl |
784 ucp_mask |
785 S_028810_CLIP_DISABLE(window_space));
786 }
787
788 /*
789 * inferred state between framebuffer and rasterizer
790 */
791 static void si_update_poly_offset_state(struct si_context *sctx)
792 {
793 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
794
795 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
796 si_pm4_bind_state(sctx, poly_offset, NULL);
797 return;
798 }
799
800 /* Use the user format, not db_render_format, so that the polygon
801 * offset behaves as expected by applications.
802 */
803 switch (sctx->framebuffer.state.zsbuf->texture->format) {
804 case PIPE_FORMAT_Z16_UNORM:
805 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
806 break;
807 default: /* 24-bit */
808 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
809 break;
810 case PIPE_FORMAT_Z32_FLOAT:
811 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
812 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
813 break;
814 }
815 }
816
817 /*
818 * Rasterizer
819 */
820
821 static uint32_t si_translate_fill(uint32_t func)
822 {
823 switch(func) {
824 case PIPE_POLYGON_MODE_FILL:
825 return V_028814_X_DRAW_TRIANGLES;
826 case PIPE_POLYGON_MODE_LINE:
827 return V_028814_X_DRAW_LINES;
828 case PIPE_POLYGON_MODE_POINT:
829 return V_028814_X_DRAW_POINTS;
830 default:
831 assert(0);
832 return V_028814_X_DRAW_POINTS;
833 }
834 }
835
836 static void *si_create_rs_state(struct pipe_context *ctx,
837 const struct pipe_rasterizer_state *state)
838 {
839 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
840 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
841 struct si_pm4_state *pm4 = &rs->pm4;
842 unsigned tmp, i;
843 float psize_min, psize_max;
844
845 if (!rs) {
846 return NULL;
847 }
848
849 rs->scissor_enable = state->scissor;
850 rs->clip_halfz = state->clip_halfz;
851 rs->two_side = state->light_twoside;
852 rs->multisample_enable = state->multisample;
853 rs->force_persample_interp = state->force_persample_interp;
854 rs->clip_plane_enable = state->clip_plane_enable;
855 rs->line_stipple_enable = state->line_stipple_enable;
856 rs->poly_stipple_enable = state->poly_stipple_enable;
857 rs->line_smooth = state->line_smooth;
858 rs->line_width = state->line_width;
859 rs->poly_smooth = state->poly_smooth;
860 rs->uses_poly_offset = state->offset_point || state->offset_line ||
861 state->offset_tri;
862 rs->clamp_fragment_color = state->clamp_fragment_color;
863 rs->clamp_vertex_color = state->clamp_vertex_color;
864 rs->flatshade = state->flatshade;
865 rs->sprite_coord_enable = state->sprite_coord_enable;
866 rs->rasterizer_discard = state->rasterizer_discard;
867 rs->pa_sc_line_stipple = state->line_stipple_enable ?
868 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
869 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
870 rs->pa_cl_clip_cntl =
871 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
872 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
873 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
874 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
875 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
876
877 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
878 S_0286D4_FLAT_SHADE_ENA(1) |
879 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
880 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
883 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
884 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
885
886 /* point size 12.4 fixed point */
887 tmp = (unsigned)(state->point_size * 8.0);
888 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
889
890 if (state->point_size_per_vertex) {
891 psize_min = util_get_min_point_size(state);
892 psize_max = 8192;
893 } else {
894 /* Force the point size to be as if the vertex output was disabled. */
895 psize_min = state->point_size;
896 psize_max = state->point_size;
897 }
898 rs->max_point_size = psize_max;
899
900 /* Divide by two, because 0.5 = 1 pixel. */
901 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
902 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
903 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
904
905 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
906 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
907 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
908 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
909 S_028A48_MSAA_ENABLE(state->multisample ||
910 state->poly_smooth ||
911 state->line_smooth) |
912 S_028A48_VPORT_SCISSOR_ENABLE(1) |
913 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
914
915 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
916 S_028BE4_PIX_CENTER(state->half_pixel_center) |
917 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
918
919 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
920 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
921 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
922 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
923 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
924 S_028814_FACE(!state->front_ccw) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
928 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
929 state->fill_back != PIPE_POLYGON_MODE_FILL) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
932
933 if (!rs->uses_poly_offset)
934 return rs;
935
936 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
937 if (!rs->pm4_poly_offset) {
938 FREE(rs);
939 return NULL;
940 }
941
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i = 0; i < 3; i++) {
944 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
945 float offset_units = state->offset_units;
946 float offset_scale = state->offset_scale * 16.0f;
947 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
948
949 if (!state->offset_units_unscaled) {
950 switch (i) {
951 case 0: /* 16-bit zbuffer */
952 offset_units *= 4.0f;
953 pa_su_poly_offset_db_fmt_cntl =
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
955 break;
956 case 1: /* 24-bit zbuffer */
957 offset_units *= 2.0f;
958 pa_su_poly_offset_db_fmt_cntl =
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
960 break;
961 case 2: /* 32-bit zbuffer */
962 offset_units *= 1.0f;
963 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
964 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
965 break;
966 }
967 }
968
969 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
970 fui(offset_scale));
971 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
972 fui(offset_units));
973 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
974 fui(offset_scale));
975 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
976 fui(offset_units));
977 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
978 pa_su_poly_offset_db_fmt_cntl);
979 }
980
981 return rs;
982 }
983
984 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
985 {
986 struct si_context *sctx = (struct si_context *)ctx;
987 struct si_state_rasterizer *old_rs =
988 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
989 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
990
991 if (!state)
992 return;
993
994 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
995 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
996
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx->screen->has_msaa_sample_loc_bug &&
999 sctx->framebuffer.nr_samples > 1)
1000 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1001 }
1002
1003 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1004 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1005
1006 si_pm4_bind_state(sctx, rasterizer, rs);
1007 si_update_poly_offset_state(sctx);
1008
1009 if (!old_rs ||
1010 (old_rs->scissor_enable != rs->scissor_enable ||
1011 old_rs->line_width != rs->line_width ||
1012 old_rs->max_point_size != rs->max_point_size)) {
1013 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1014 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1015 }
1016
1017 if (!old_rs ||
1018 old_rs->clip_halfz != rs->clip_halfz) {
1019 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1020 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1021 }
1022
1023 if (!old_rs ||
1024 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1025 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1026 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1027
1028 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1029 rs->line_stipple_enable;
1030
1031 if (!old_rs ||
1032 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1033 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1034 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1035 old_rs->flatshade != rs->flatshade ||
1036 old_rs->two_side != rs->two_side ||
1037 old_rs->multisample_enable != rs->multisample_enable ||
1038 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1039 old_rs->poly_smooth != rs->poly_smooth ||
1040 old_rs->line_smooth != rs->line_smooth ||
1041 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1042 old_rs->force_persample_interp != rs->force_persample_interp)
1043 sctx->do_update_shaders = true;
1044 }
1045
1046 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1047 {
1048 struct si_context *sctx = (struct si_context *)ctx;
1049 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1050
1051 if (sctx->queued.named.rasterizer == state)
1052 si_pm4_bind_state(sctx, poly_offset, NULL);
1053
1054 FREE(rs->pm4_poly_offset);
1055 si_pm4_delete_state(sctx, rasterizer, rs);
1056 }
1057
1058 /*
1059 * infeered state between dsa and stencil ref
1060 */
1061 static void si_emit_stencil_ref(struct si_context *sctx)
1062 {
1063 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1064 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1065 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1066
1067 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1068 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1069 S_028430_STENCILMASK(dsa->valuemask[0]) |
1070 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1071 S_028430_STENCILOPVAL(1));
1072 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1073 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1074 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1075 S_028434_STENCILOPVAL_BF(1));
1076 }
1077
1078 static void si_set_stencil_ref(struct pipe_context *ctx,
1079 const struct pipe_stencil_ref *state)
1080 {
1081 struct si_context *sctx = (struct si_context *)ctx;
1082
1083 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1084 return;
1085
1086 sctx->stencil_ref.state = *state;
1087 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1088 }
1089
1090
1091 /*
1092 * DSA
1093 */
1094
1095 static uint32_t si_translate_stencil_op(int s_op)
1096 {
1097 switch (s_op) {
1098 case PIPE_STENCIL_OP_KEEP:
1099 return V_02842C_STENCIL_KEEP;
1100 case PIPE_STENCIL_OP_ZERO:
1101 return V_02842C_STENCIL_ZERO;
1102 case PIPE_STENCIL_OP_REPLACE:
1103 return V_02842C_STENCIL_REPLACE_TEST;
1104 case PIPE_STENCIL_OP_INCR:
1105 return V_02842C_STENCIL_ADD_CLAMP;
1106 case PIPE_STENCIL_OP_DECR:
1107 return V_02842C_STENCIL_SUB_CLAMP;
1108 case PIPE_STENCIL_OP_INCR_WRAP:
1109 return V_02842C_STENCIL_ADD_WRAP;
1110 case PIPE_STENCIL_OP_DECR_WRAP:
1111 return V_02842C_STENCIL_SUB_WRAP;
1112 case PIPE_STENCIL_OP_INVERT:
1113 return V_02842C_STENCIL_INVERT;
1114 default:
1115 PRINT_ERR("Unknown stencil op %d", s_op);
1116 assert(0);
1117 break;
1118 }
1119 return 0;
1120 }
1121
1122 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1123 {
1124 return s->enabled && s->writemask &&
1125 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1126 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1127 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1128 }
1129
1130 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1131 {
1132 /* REPLACE is normally order invariant, except when the stencil
1133 * reference value is written by the fragment shader. Tracking this
1134 * interaction does not seem worth the effort, so be conservative. */
1135 return op != PIPE_STENCIL_OP_INCR &&
1136 op != PIPE_STENCIL_OP_DECR &&
1137 op != PIPE_STENCIL_OP_REPLACE;
1138 }
1139
1140 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1141 * invariant in the sense that the set of passing fragments as well as the
1142 * final stencil buffer result does not depend on the order of fragments. */
1143 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1144 {
1145 return !state->enabled || !state->writemask ||
1146 /* The following assumes that Z writes are disabled. */
1147 (state->func == PIPE_FUNC_ALWAYS &&
1148 si_order_invariant_stencil_op(state->zpass_op) &&
1149 si_order_invariant_stencil_op(state->zfail_op)) ||
1150 (state->func == PIPE_FUNC_NEVER &&
1151 si_order_invariant_stencil_op(state->fail_op));
1152 }
1153
1154 static void *si_create_dsa_state(struct pipe_context *ctx,
1155 const struct pipe_depth_stencil_alpha_state *state)
1156 {
1157 struct si_context *sctx = (struct si_context *)ctx;
1158 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1159 struct si_pm4_state *pm4 = &dsa->pm4;
1160 unsigned db_depth_control;
1161 uint32_t db_stencil_control = 0;
1162
1163 if (!dsa) {
1164 return NULL;
1165 }
1166
1167 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1168 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1169 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1170 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1171
1172 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1173 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1174 S_028800_ZFUNC(state->depth.func) |
1175 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1176
1177 /* stencil */
1178 if (state->stencil[0].enabled) {
1179 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1180 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1181 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1182 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1183 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1184
1185 if (state->stencil[1].enabled) {
1186 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1187 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1188 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1189 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1190 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1191 }
1192 }
1193
1194 /* alpha */
1195 if (state->alpha.enabled) {
1196 dsa->alpha_func = state->alpha.func;
1197
1198 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1199 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1200 } else {
1201 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1202 }
1203
1204 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1205 if (state->stencil[0].enabled)
1206 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1207 if (state->depth.bounds_test) {
1208 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1209 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1210 }
1211
1212 dsa->depth_enabled = state->depth.enabled;
1213 dsa->depth_write_enabled = state->depth.enabled &&
1214 state->depth.writemask;
1215 dsa->stencil_enabled = state->stencil[0].enabled;
1216 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1217 (si_dsa_writes_stencil(&state->stencil[0]) ||
1218 si_dsa_writes_stencil(&state->stencil[1]));
1219 dsa->db_can_write = dsa->depth_write_enabled ||
1220 dsa->stencil_write_enabled;
1221
1222 bool zfunc_is_ordered =
1223 state->depth.func == PIPE_FUNC_NEVER ||
1224 state->depth.func == PIPE_FUNC_LESS ||
1225 state->depth.func == PIPE_FUNC_LEQUAL ||
1226 state->depth.func == PIPE_FUNC_GREATER ||
1227 state->depth.func == PIPE_FUNC_GEQUAL;
1228
1229 bool nozwrite_and_order_invariant_stencil =
1230 !dsa->db_can_write ||
1231 (!dsa->depth_write_enabled &&
1232 si_order_invariant_stencil_state(&state->stencil[0]) &&
1233 si_order_invariant_stencil_state(&state->stencil[1]));
1234
1235 dsa->order_invariance[1].zs =
1236 nozwrite_and_order_invariant_stencil ||
1237 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1238 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1239
1240 dsa->order_invariance[1].pass_set =
1241 nozwrite_and_order_invariant_stencil ||
1242 (!dsa->stencil_write_enabled &&
1243 (state->depth.func == PIPE_FUNC_ALWAYS ||
1244 state->depth.func == PIPE_FUNC_NEVER));
1245 dsa->order_invariance[0].pass_set =
1246 !dsa->depth_write_enabled ||
1247 (state->depth.func == PIPE_FUNC_ALWAYS ||
1248 state->depth.func == PIPE_FUNC_NEVER);
1249
1250 dsa->order_invariance[1].pass_last =
1251 sctx->screen->assume_no_z_fights &&
1252 !dsa->stencil_write_enabled &&
1253 dsa->depth_write_enabled && zfunc_is_ordered;
1254 dsa->order_invariance[0].pass_last =
1255 sctx->screen->assume_no_z_fights &&
1256 dsa->depth_write_enabled && zfunc_is_ordered;
1257
1258 return dsa;
1259 }
1260
1261 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1262 {
1263 struct si_context *sctx = (struct si_context *)ctx;
1264 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1265 struct si_state_dsa *dsa = state;
1266
1267 if (!state)
1268 return;
1269
1270 si_pm4_bind_state(sctx, dsa, dsa);
1271
1272 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1273 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1274 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1275 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1276 }
1277
1278 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1279 sctx->do_update_shaders = true;
1280
1281 if (sctx->screen->dpbb_allowed &&
1282 (!old_dsa ||
1283 (old_dsa->depth_enabled != dsa->depth_enabled ||
1284 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1285 old_dsa->db_can_write != dsa->db_can_write)))
1286 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1287
1288 if (sctx->screen->has_out_of_order_rast &&
1289 (!old_dsa ||
1290 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1291 sizeof(old_dsa->order_invariance))))
1292 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1293 }
1294
1295 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1296 {
1297 struct si_context *sctx = (struct si_context *)ctx;
1298 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1299 }
1300
1301 static void *si_create_db_flush_dsa(struct si_context *sctx)
1302 {
1303 struct pipe_depth_stencil_alpha_state dsa = {};
1304
1305 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1306 }
1307
1308 /* DB RENDER STATE */
1309
1310 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1311 {
1312 struct si_context *sctx = (struct si_context*)ctx;
1313
1314 /* Pipeline stat & streamout queries. */
1315 if (enable) {
1316 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1317 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1318 } else {
1319 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1320 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1321 }
1322
1323 /* Occlusion queries. */
1324 if (sctx->occlusion_queries_disabled != !enable) {
1325 sctx->occlusion_queries_disabled = !enable;
1326 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1327 }
1328 }
1329
1330 void si_set_occlusion_query_state(struct si_context *sctx,
1331 bool old_perfect_enable)
1332 {
1333 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1334
1335 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1336
1337 if (perfect_enable != old_perfect_enable)
1338 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1339 }
1340
1341 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1342 {
1343 st->saved_compute = sctx->cs_shader_state.program;
1344
1345 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1346 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1347 }
1348
1349 static void si_emit_db_render_state(struct si_context *sctx)
1350 {
1351 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1352 unsigned db_shader_control, db_render_control, db_count_control;
1353
1354 /* DB_RENDER_CONTROL */
1355 if (sctx->dbcb_depth_copy_enabled ||
1356 sctx->dbcb_stencil_copy_enabled) {
1357 db_render_control =
1358 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1359 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1360 S_028000_COPY_CENTROID(1) |
1361 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1362 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1363 db_render_control =
1364 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1365 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1366 } else {
1367 db_render_control =
1368 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1369 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1370 }
1371
1372 /* DB_COUNT_CONTROL (occlusion queries) */
1373 if (sctx->num_occlusion_queries > 0 &&
1374 !sctx->occlusion_queries_disabled) {
1375 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1376
1377 if (sctx->chip_class >= CIK) {
1378 db_count_control =
1379 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1380 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1381 S_028004_ZPASS_ENABLE(1) |
1382 S_028004_SLICE_EVEN_ENABLE(1) |
1383 S_028004_SLICE_ODD_ENABLE(1);
1384 } else {
1385 db_count_control =
1386 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1387 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1388 }
1389 } else {
1390 /* Disable occlusion queries. */
1391 if (sctx->chip_class >= CIK) {
1392 db_count_control = 0;
1393 } else {
1394 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1395 }
1396 }
1397
1398 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1399 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1400 db_count_control);
1401
1402 /* DB_RENDER_OVERRIDE2 */
1403 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1404 SI_TRACKED_DB_RENDER_OVERRIDE2,
1405 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1406 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1407 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1408
1409 db_shader_control = sctx->ps_db_shader_control;
1410
1411 /* Bug workaround for smoothing (overrasterization) on SI. */
1412 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1413 db_shader_control &= C_02880C_Z_ORDER;
1414 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1415 }
1416
1417 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1418 if (!rs || !rs->multisample_enable)
1419 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1420
1421 if (sctx->screen->has_rbplus &&
1422 !sctx->screen->rbplus_allowed)
1423 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1424
1425 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1426 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1427 }
1428
1429 /*
1430 * format translation
1431 */
1432 static uint32_t si_translate_colorformat(enum pipe_format format)
1433 {
1434 const struct util_format_description *desc = util_format_description(format);
1435 if (!desc)
1436 return V_028C70_COLOR_INVALID;
1437
1438 #define HAS_SIZE(x,y,z,w) \
1439 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1440 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1441
1442 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1443 return V_028C70_COLOR_10_11_11;
1444
1445 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1446 return V_028C70_COLOR_INVALID;
1447
1448 /* hw cannot support mixed formats (except depth/stencil, since
1449 * stencil is not written to). */
1450 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1451 return V_028C70_COLOR_INVALID;
1452
1453 switch (desc->nr_channels) {
1454 case 1:
1455 switch (desc->channel[0].size) {
1456 case 8:
1457 return V_028C70_COLOR_8;
1458 case 16:
1459 return V_028C70_COLOR_16;
1460 case 32:
1461 return V_028C70_COLOR_32;
1462 }
1463 break;
1464 case 2:
1465 if (desc->channel[0].size == desc->channel[1].size) {
1466 switch (desc->channel[0].size) {
1467 case 8:
1468 return V_028C70_COLOR_8_8;
1469 case 16:
1470 return V_028C70_COLOR_16_16;
1471 case 32:
1472 return V_028C70_COLOR_32_32;
1473 }
1474 } else if (HAS_SIZE(8,24,0,0)) {
1475 return V_028C70_COLOR_24_8;
1476 } else if (HAS_SIZE(24,8,0,0)) {
1477 return V_028C70_COLOR_8_24;
1478 }
1479 break;
1480 case 3:
1481 if (HAS_SIZE(5,6,5,0)) {
1482 return V_028C70_COLOR_5_6_5;
1483 } else if (HAS_SIZE(32,8,24,0)) {
1484 return V_028C70_COLOR_X24_8_32_FLOAT;
1485 }
1486 break;
1487 case 4:
1488 if (desc->channel[0].size == desc->channel[1].size &&
1489 desc->channel[0].size == desc->channel[2].size &&
1490 desc->channel[0].size == desc->channel[3].size) {
1491 switch (desc->channel[0].size) {
1492 case 4:
1493 return V_028C70_COLOR_4_4_4_4;
1494 case 8:
1495 return V_028C70_COLOR_8_8_8_8;
1496 case 16:
1497 return V_028C70_COLOR_16_16_16_16;
1498 case 32:
1499 return V_028C70_COLOR_32_32_32_32;
1500 }
1501 } else if (HAS_SIZE(5,5,5,1)) {
1502 return V_028C70_COLOR_1_5_5_5;
1503 } else if (HAS_SIZE(1,5,5,5)) {
1504 return V_028C70_COLOR_5_5_5_1;
1505 } else if (HAS_SIZE(10,10,10,2)) {
1506 return V_028C70_COLOR_2_10_10_10;
1507 }
1508 break;
1509 }
1510 return V_028C70_COLOR_INVALID;
1511 }
1512
1513 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1514 {
1515 if (SI_BIG_ENDIAN) {
1516 switch(colorformat) {
1517 /* 8-bit buffers. */
1518 case V_028C70_COLOR_8:
1519 return V_028C70_ENDIAN_NONE;
1520
1521 /* 16-bit buffers. */
1522 case V_028C70_COLOR_5_6_5:
1523 case V_028C70_COLOR_1_5_5_5:
1524 case V_028C70_COLOR_4_4_4_4:
1525 case V_028C70_COLOR_16:
1526 case V_028C70_COLOR_8_8:
1527 return V_028C70_ENDIAN_8IN16;
1528
1529 /* 32-bit buffers. */
1530 case V_028C70_COLOR_8_8_8_8:
1531 case V_028C70_COLOR_2_10_10_10:
1532 case V_028C70_COLOR_8_24:
1533 case V_028C70_COLOR_24_8:
1534 case V_028C70_COLOR_16_16:
1535 return V_028C70_ENDIAN_8IN32;
1536
1537 /* 64-bit buffers. */
1538 case V_028C70_COLOR_16_16_16_16:
1539 return V_028C70_ENDIAN_8IN16;
1540
1541 case V_028C70_COLOR_32_32:
1542 return V_028C70_ENDIAN_8IN32;
1543
1544 /* 128-bit buffers. */
1545 case V_028C70_COLOR_32_32_32_32:
1546 return V_028C70_ENDIAN_8IN32;
1547 default:
1548 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1549 }
1550 } else {
1551 return V_028C70_ENDIAN_NONE;
1552 }
1553 }
1554
1555 static uint32_t si_translate_dbformat(enum pipe_format format)
1556 {
1557 switch (format) {
1558 case PIPE_FORMAT_Z16_UNORM:
1559 return V_028040_Z_16;
1560 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1561 case PIPE_FORMAT_X8Z24_UNORM:
1562 case PIPE_FORMAT_Z24X8_UNORM:
1563 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1564 return V_028040_Z_24; /* deprecated on SI */
1565 case PIPE_FORMAT_Z32_FLOAT:
1566 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1567 return V_028040_Z_32_FLOAT;
1568 default:
1569 return V_028040_Z_INVALID;
1570 }
1571 }
1572
1573 /*
1574 * Texture translation
1575 */
1576
1577 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1578 enum pipe_format format,
1579 const struct util_format_description *desc,
1580 int first_non_void)
1581 {
1582 struct si_screen *sscreen = (struct si_screen*)screen;
1583 bool uniform = true;
1584 int i;
1585
1586 /* Colorspace (return non-RGB formats directly). */
1587 switch (desc->colorspace) {
1588 /* Depth stencil formats */
1589 case UTIL_FORMAT_COLORSPACE_ZS:
1590 switch (format) {
1591 case PIPE_FORMAT_Z16_UNORM:
1592 return V_008F14_IMG_DATA_FORMAT_16;
1593 case PIPE_FORMAT_X24S8_UINT:
1594 case PIPE_FORMAT_S8X24_UINT:
1595 /*
1596 * Implemented as an 8_8_8_8 data format to fix texture
1597 * gathers in stencil sampling. This affects at least
1598 * GL45-CTS.texture_cube_map_array.sampling on VI.
1599 */
1600 if (sscreen->info.chip_class <= VI)
1601 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1602
1603 if (format == PIPE_FORMAT_X24S8_UINT)
1604 return V_008F14_IMG_DATA_FORMAT_8_24;
1605 else
1606 return V_008F14_IMG_DATA_FORMAT_24_8;
1607 case PIPE_FORMAT_Z24X8_UNORM:
1608 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1609 return V_008F14_IMG_DATA_FORMAT_8_24;
1610 case PIPE_FORMAT_X8Z24_UNORM:
1611 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1612 return V_008F14_IMG_DATA_FORMAT_24_8;
1613 case PIPE_FORMAT_S8_UINT:
1614 return V_008F14_IMG_DATA_FORMAT_8;
1615 case PIPE_FORMAT_Z32_FLOAT:
1616 return V_008F14_IMG_DATA_FORMAT_32;
1617 case PIPE_FORMAT_X32_S8X24_UINT:
1618 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1619 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1620 default:
1621 goto out_unknown;
1622 }
1623
1624 case UTIL_FORMAT_COLORSPACE_YUV:
1625 goto out_unknown; /* TODO */
1626
1627 case UTIL_FORMAT_COLORSPACE_SRGB:
1628 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1629 goto out_unknown;
1630 break;
1631
1632 default:
1633 break;
1634 }
1635
1636 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1637 if (!sscreen->info.has_format_bc1_through_bc7)
1638 goto out_unknown;
1639
1640 switch (format) {
1641 case PIPE_FORMAT_RGTC1_SNORM:
1642 case PIPE_FORMAT_LATC1_SNORM:
1643 case PIPE_FORMAT_RGTC1_UNORM:
1644 case PIPE_FORMAT_LATC1_UNORM:
1645 return V_008F14_IMG_DATA_FORMAT_BC4;
1646 case PIPE_FORMAT_RGTC2_SNORM:
1647 case PIPE_FORMAT_LATC2_SNORM:
1648 case PIPE_FORMAT_RGTC2_UNORM:
1649 case PIPE_FORMAT_LATC2_UNORM:
1650 return V_008F14_IMG_DATA_FORMAT_BC5;
1651 default:
1652 goto out_unknown;
1653 }
1654 }
1655
1656 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1657 (sscreen->info.family == CHIP_STONEY ||
1658 sscreen->info.family == CHIP_VEGA10 ||
1659 sscreen->info.family == CHIP_RAVEN)) {
1660 switch (format) {
1661 case PIPE_FORMAT_ETC1_RGB8:
1662 case PIPE_FORMAT_ETC2_RGB8:
1663 case PIPE_FORMAT_ETC2_SRGB8:
1664 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1665 case PIPE_FORMAT_ETC2_RGB8A1:
1666 case PIPE_FORMAT_ETC2_SRGB8A1:
1667 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1668 case PIPE_FORMAT_ETC2_RGBA8:
1669 case PIPE_FORMAT_ETC2_SRGBA8:
1670 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1671 case PIPE_FORMAT_ETC2_R11_UNORM:
1672 case PIPE_FORMAT_ETC2_R11_SNORM:
1673 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1674 case PIPE_FORMAT_ETC2_RG11_UNORM:
1675 case PIPE_FORMAT_ETC2_RG11_SNORM:
1676 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1677 default:
1678 goto out_unknown;
1679 }
1680 }
1681
1682 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1683 if (!sscreen->info.has_format_bc1_through_bc7)
1684 goto out_unknown;
1685
1686 switch (format) {
1687 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1688 case PIPE_FORMAT_BPTC_SRGBA:
1689 return V_008F14_IMG_DATA_FORMAT_BC7;
1690 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1691 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1692 return V_008F14_IMG_DATA_FORMAT_BC6;
1693 default:
1694 goto out_unknown;
1695 }
1696 }
1697
1698 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1699 switch (format) {
1700 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1701 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1702 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1703 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1704 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1705 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1706 default:
1707 goto out_unknown;
1708 }
1709 }
1710
1711 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1712 if (!sscreen->info.has_format_bc1_through_bc7)
1713 goto out_unknown;
1714
1715 switch (format) {
1716 case PIPE_FORMAT_DXT1_RGB:
1717 case PIPE_FORMAT_DXT1_RGBA:
1718 case PIPE_FORMAT_DXT1_SRGB:
1719 case PIPE_FORMAT_DXT1_SRGBA:
1720 return V_008F14_IMG_DATA_FORMAT_BC1;
1721 case PIPE_FORMAT_DXT3_RGBA:
1722 case PIPE_FORMAT_DXT3_SRGBA:
1723 return V_008F14_IMG_DATA_FORMAT_BC2;
1724 case PIPE_FORMAT_DXT5_RGBA:
1725 case PIPE_FORMAT_DXT5_SRGBA:
1726 return V_008F14_IMG_DATA_FORMAT_BC3;
1727 default:
1728 goto out_unknown;
1729 }
1730 }
1731
1732 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1733 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1734 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1735 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1736 }
1737
1738 /* R8G8Bx_SNORM - TODO CxV8U8 */
1739
1740 /* hw cannot support mixed formats (except depth/stencil, since only
1741 * depth is read).*/
1742 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1743 goto out_unknown;
1744
1745 /* See whether the components are of the same size. */
1746 for (i = 1; i < desc->nr_channels; i++) {
1747 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1748 }
1749
1750 /* Non-uniform formats. */
1751 if (!uniform) {
1752 switch(desc->nr_channels) {
1753 case 3:
1754 if (desc->channel[0].size == 5 &&
1755 desc->channel[1].size == 6 &&
1756 desc->channel[2].size == 5) {
1757 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1758 }
1759 goto out_unknown;
1760 case 4:
1761 if (desc->channel[0].size == 5 &&
1762 desc->channel[1].size == 5 &&
1763 desc->channel[2].size == 5 &&
1764 desc->channel[3].size == 1) {
1765 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1766 }
1767 if (desc->channel[0].size == 1 &&
1768 desc->channel[1].size == 5 &&
1769 desc->channel[2].size == 5 &&
1770 desc->channel[3].size == 5) {
1771 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1772 }
1773 if (desc->channel[0].size == 10 &&
1774 desc->channel[1].size == 10 &&
1775 desc->channel[2].size == 10 &&
1776 desc->channel[3].size == 2) {
1777 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1778 }
1779 goto out_unknown;
1780 }
1781 goto out_unknown;
1782 }
1783
1784 if (first_non_void < 0 || first_non_void > 3)
1785 goto out_unknown;
1786
1787 /* uniform formats */
1788 switch (desc->channel[first_non_void].size) {
1789 case 4:
1790 switch (desc->nr_channels) {
1791 #if 0 /* Not supported for render targets */
1792 case 2:
1793 return V_008F14_IMG_DATA_FORMAT_4_4;
1794 #endif
1795 case 4:
1796 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1797 }
1798 break;
1799 case 8:
1800 switch (desc->nr_channels) {
1801 case 1:
1802 return V_008F14_IMG_DATA_FORMAT_8;
1803 case 2:
1804 return V_008F14_IMG_DATA_FORMAT_8_8;
1805 case 4:
1806 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1807 }
1808 break;
1809 case 16:
1810 switch (desc->nr_channels) {
1811 case 1:
1812 return V_008F14_IMG_DATA_FORMAT_16;
1813 case 2:
1814 return V_008F14_IMG_DATA_FORMAT_16_16;
1815 case 4:
1816 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1817 }
1818 break;
1819 case 32:
1820 switch (desc->nr_channels) {
1821 case 1:
1822 return V_008F14_IMG_DATA_FORMAT_32;
1823 case 2:
1824 return V_008F14_IMG_DATA_FORMAT_32_32;
1825 #if 0 /* Not supported for render targets */
1826 case 3:
1827 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1828 #endif
1829 case 4:
1830 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1831 }
1832 }
1833
1834 out_unknown:
1835 return ~0;
1836 }
1837
1838 static unsigned si_tex_wrap(unsigned wrap)
1839 {
1840 switch (wrap) {
1841 default:
1842 case PIPE_TEX_WRAP_REPEAT:
1843 return V_008F30_SQ_TEX_WRAP;
1844 case PIPE_TEX_WRAP_CLAMP:
1845 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1846 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1847 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1848 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1849 return V_008F30_SQ_TEX_CLAMP_BORDER;
1850 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1851 return V_008F30_SQ_TEX_MIRROR;
1852 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1853 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1854 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1855 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1856 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1857 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1858 }
1859 }
1860
1861 static unsigned si_tex_mipfilter(unsigned filter)
1862 {
1863 switch (filter) {
1864 case PIPE_TEX_MIPFILTER_NEAREST:
1865 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1866 case PIPE_TEX_MIPFILTER_LINEAR:
1867 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1868 default:
1869 case PIPE_TEX_MIPFILTER_NONE:
1870 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1871 }
1872 }
1873
1874 static unsigned si_tex_compare(unsigned compare)
1875 {
1876 switch (compare) {
1877 default:
1878 case PIPE_FUNC_NEVER:
1879 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1880 case PIPE_FUNC_LESS:
1881 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1882 case PIPE_FUNC_EQUAL:
1883 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1884 case PIPE_FUNC_LEQUAL:
1885 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1886 case PIPE_FUNC_GREATER:
1887 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1888 case PIPE_FUNC_NOTEQUAL:
1889 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1890 case PIPE_FUNC_GEQUAL:
1891 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1892 case PIPE_FUNC_ALWAYS:
1893 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1894 }
1895 }
1896
1897 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1898 unsigned view_target, unsigned nr_samples)
1899 {
1900 unsigned res_target = rtex->buffer.b.b.target;
1901
1902 if (view_target == PIPE_TEXTURE_CUBE ||
1903 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1904 res_target = view_target;
1905 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1906 else if (res_target == PIPE_TEXTURE_CUBE ||
1907 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1908 res_target = PIPE_TEXTURE_2D_ARRAY;
1909
1910 /* GFX9 allocates 1D textures as 2D. */
1911 if ((res_target == PIPE_TEXTURE_1D ||
1912 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1913 sscreen->info.chip_class >= GFX9 &&
1914 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1915 if (res_target == PIPE_TEXTURE_1D)
1916 res_target = PIPE_TEXTURE_2D;
1917 else
1918 res_target = PIPE_TEXTURE_2D_ARRAY;
1919 }
1920
1921 switch (res_target) {
1922 default:
1923 case PIPE_TEXTURE_1D:
1924 return V_008F1C_SQ_RSRC_IMG_1D;
1925 case PIPE_TEXTURE_1D_ARRAY:
1926 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1927 case PIPE_TEXTURE_2D:
1928 case PIPE_TEXTURE_RECT:
1929 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1930 V_008F1C_SQ_RSRC_IMG_2D;
1931 case PIPE_TEXTURE_2D_ARRAY:
1932 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1933 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1934 case PIPE_TEXTURE_3D:
1935 return V_008F1C_SQ_RSRC_IMG_3D;
1936 case PIPE_TEXTURE_CUBE:
1937 case PIPE_TEXTURE_CUBE_ARRAY:
1938 return V_008F1C_SQ_RSRC_IMG_CUBE;
1939 }
1940 }
1941
1942 /*
1943 * Format support testing
1944 */
1945
1946 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1947 {
1948 const struct util_format_description *desc = util_format_description(format);
1949 if (!desc)
1950 return false;
1951
1952 return si_translate_texformat(screen, format, desc,
1953 util_format_get_first_non_void_channel(format)) != ~0U;
1954 }
1955
1956 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1957 const struct util_format_description *desc,
1958 int first_non_void)
1959 {
1960 int i;
1961
1962 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1963 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1964
1965 assert(first_non_void >= 0);
1966
1967 if (desc->nr_channels == 4 &&
1968 desc->channel[0].size == 10 &&
1969 desc->channel[1].size == 10 &&
1970 desc->channel[2].size == 10 &&
1971 desc->channel[3].size == 2)
1972 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1973
1974 /* See whether the components are of the same size. */
1975 for (i = 0; i < desc->nr_channels; i++) {
1976 if (desc->channel[first_non_void].size != desc->channel[i].size)
1977 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1978 }
1979
1980 switch (desc->channel[first_non_void].size) {
1981 case 8:
1982 switch (desc->nr_channels) {
1983 case 1:
1984 case 3: /* 3 loads */
1985 return V_008F0C_BUF_DATA_FORMAT_8;
1986 case 2:
1987 return V_008F0C_BUF_DATA_FORMAT_8_8;
1988 case 4:
1989 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1990 }
1991 break;
1992 case 16:
1993 switch (desc->nr_channels) {
1994 case 1:
1995 case 3: /* 3 loads */
1996 return V_008F0C_BUF_DATA_FORMAT_16;
1997 case 2:
1998 return V_008F0C_BUF_DATA_FORMAT_16_16;
1999 case 4:
2000 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2001 }
2002 break;
2003 case 32:
2004 switch (desc->nr_channels) {
2005 case 1:
2006 return V_008F0C_BUF_DATA_FORMAT_32;
2007 case 2:
2008 return V_008F0C_BUF_DATA_FORMAT_32_32;
2009 case 3:
2010 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2011 case 4:
2012 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2013 }
2014 break;
2015 case 64:
2016 /* Legacy double formats. */
2017 switch (desc->nr_channels) {
2018 case 1: /* 1 load */
2019 return V_008F0C_BUF_DATA_FORMAT_32_32;
2020 case 2: /* 1 load */
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2022 case 3: /* 3 loads */
2023 return V_008F0C_BUF_DATA_FORMAT_32_32;
2024 case 4: /* 2 loads */
2025 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2026 }
2027 break;
2028 }
2029
2030 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2031 }
2032
2033 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2034 const struct util_format_description *desc,
2035 int first_non_void)
2036 {
2037 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2038 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2039
2040 assert(first_non_void >= 0);
2041
2042 switch (desc->channel[first_non_void].type) {
2043 case UTIL_FORMAT_TYPE_SIGNED:
2044 case UTIL_FORMAT_TYPE_FIXED:
2045 if (desc->channel[first_non_void].size >= 32 ||
2046 desc->channel[first_non_void].pure_integer)
2047 return V_008F0C_BUF_NUM_FORMAT_SINT;
2048 else if (desc->channel[first_non_void].normalized)
2049 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2050 else
2051 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2052 break;
2053 case UTIL_FORMAT_TYPE_UNSIGNED:
2054 if (desc->channel[first_non_void].size >= 32 ||
2055 desc->channel[first_non_void].pure_integer)
2056 return V_008F0C_BUF_NUM_FORMAT_UINT;
2057 else if (desc->channel[first_non_void].normalized)
2058 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2059 else
2060 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2061 break;
2062 case UTIL_FORMAT_TYPE_FLOAT:
2063 default:
2064 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2065 }
2066 }
2067
2068 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2069 enum pipe_format format,
2070 unsigned usage)
2071 {
2072 const struct util_format_description *desc;
2073 int first_non_void;
2074 unsigned data_format;
2075
2076 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2077 PIPE_BIND_SAMPLER_VIEW |
2078 PIPE_BIND_VERTEX_BUFFER)) == 0);
2079
2080 desc = util_format_description(format);
2081 if (!desc)
2082 return 0;
2083
2084 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2085 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2086 * for read-only access (with caveats surrounding bounds checks), but
2087 * obviously fails for write access which we have to implement for
2088 * shader images. Luckily, OpenGL doesn't expect this to be supported
2089 * anyway, and so the only impact is on PBO uploads / downloads, which
2090 * shouldn't be expected to be fast for GL_RGB anyway.
2091 */
2092 if (desc->block.bits == 3 * 8 ||
2093 desc->block.bits == 3 * 16) {
2094 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2095 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2096 if (!usage)
2097 return 0;
2098 }
2099 }
2100
2101 first_non_void = util_format_get_first_non_void_channel(format);
2102 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2103 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2104 return 0;
2105
2106 return usage;
2107 }
2108
2109 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2110 {
2111 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2112 si_translate_colorswap(format, false) != ~0U;
2113 }
2114
2115 static bool si_is_zs_format_supported(enum pipe_format format)
2116 {
2117 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2118 }
2119
2120 static boolean si_is_format_supported(struct pipe_screen *screen,
2121 enum pipe_format format,
2122 enum pipe_texture_target target,
2123 unsigned sample_count,
2124 unsigned usage)
2125 {
2126 struct si_screen *sscreen = (struct si_screen *)screen;
2127 unsigned retval = 0;
2128
2129 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2130 PRINT_ERR("r600: unsupported texture type %d\n", target);
2131 return false;
2132 }
2133
2134 if (!util_format_is_supported(format, usage))
2135 return false;
2136
2137 if (sample_count > 1) {
2138 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2139 return false;
2140
2141 if (usage & PIPE_BIND_SHADER_IMAGE)
2142 return false;
2143
2144 switch (sample_count) {
2145 case 2:
2146 case 4:
2147 case 8:
2148 break;
2149 case 16:
2150 /* Allow resource_copy_region with nr_samples == 16. */
2151 if (sscreen->eqaa_force_coverage_samples == 16 &&
2152 !util_format_is_depth_or_stencil(format))
2153 return true;
2154 if (format == PIPE_FORMAT_NONE)
2155 return true;
2156 else
2157 return false;
2158 default:
2159 return false;
2160 }
2161 }
2162
2163 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2164 PIPE_BIND_SHADER_IMAGE)) {
2165 if (target == PIPE_BUFFER) {
2166 retval |= si_is_vertex_format_supported(
2167 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2168 PIPE_BIND_SHADER_IMAGE));
2169 } else {
2170 if (si_is_sampler_format_supported(screen, format))
2171 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2172 PIPE_BIND_SHADER_IMAGE);
2173 }
2174 }
2175
2176 if ((usage & (PIPE_BIND_RENDER_TARGET |
2177 PIPE_BIND_DISPLAY_TARGET |
2178 PIPE_BIND_SCANOUT |
2179 PIPE_BIND_SHARED |
2180 PIPE_BIND_BLENDABLE)) &&
2181 si_is_colorbuffer_format_supported(format)) {
2182 retval |= usage &
2183 (PIPE_BIND_RENDER_TARGET |
2184 PIPE_BIND_DISPLAY_TARGET |
2185 PIPE_BIND_SCANOUT |
2186 PIPE_BIND_SHARED);
2187 if (!util_format_is_pure_integer(format) &&
2188 !util_format_is_depth_or_stencil(format))
2189 retval |= usage & PIPE_BIND_BLENDABLE;
2190 }
2191
2192 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2193 si_is_zs_format_supported(format)) {
2194 retval |= PIPE_BIND_DEPTH_STENCIL;
2195 }
2196
2197 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2198 retval |= si_is_vertex_format_supported(screen, format,
2199 PIPE_BIND_VERTEX_BUFFER);
2200 }
2201
2202 if ((usage & PIPE_BIND_LINEAR) &&
2203 !util_format_is_compressed(format) &&
2204 !(usage & PIPE_BIND_DEPTH_STENCIL))
2205 retval |= PIPE_BIND_LINEAR;
2206
2207 return retval == usage;
2208 }
2209
2210 /*
2211 * framebuffer handling
2212 */
2213
2214 static void si_choose_spi_color_formats(struct r600_surface *surf,
2215 unsigned format, unsigned swap,
2216 unsigned ntype, bool is_depth)
2217 {
2218 /* Alpha is needed for alpha-to-coverage.
2219 * Blending may be with or without alpha.
2220 */
2221 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2222 unsigned alpha = 0; /* exports alpha, but may not support blending */
2223 unsigned blend = 0; /* supports blending, but may not export alpha */
2224 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2225
2226 /* Choose the SPI color formats. These are required values for RB+.
2227 * Other chips have multiple choices, though they are not necessarily better.
2228 */
2229 switch (format) {
2230 case V_028C70_COLOR_5_6_5:
2231 case V_028C70_COLOR_1_5_5_5:
2232 case V_028C70_COLOR_5_5_5_1:
2233 case V_028C70_COLOR_4_4_4_4:
2234 case V_028C70_COLOR_10_11_11:
2235 case V_028C70_COLOR_11_11_10:
2236 case V_028C70_COLOR_8:
2237 case V_028C70_COLOR_8_8:
2238 case V_028C70_COLOR_8_8_8_8:
2239 case V_028C70_COLOR_10_10_10_2:
2240 case V_028C70_COLOR_2_10_10_10:
2241 if (ntype == V_028C70_NUMBER_UINT)
2242 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2243 else if (ntype == V_028C70_NUMBER_SINT)
2244 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2245 else
2246 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2247 break;
2248
2249 case V_028C70_COLOR_16:
2250 case V_028C70_COLOR_16_16:
2251 case V_028C70_COLOR_16_16_16_16:
2252 if (ntype == V_028C70_NUMBER_UNORM ||
2253 ntype == V_028C70_NUMBER_SNORM) {
2254 /* UNORM16 and SNORM16 don't support blending */
2255 if (ntype == V_028C70_NUMBER_UNORM)
2256 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2257 else
2258 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2259
2260 /* Use 32 bits per channel for blending. */
2261 if (format == V_028C70_COLOR_16) {
2262 if (swap == V_028C70_SWAP_STD) { /* R */
2263 blend = V_028714_SPI_SHADER_32_R;
2264 blend_alpha = V_028714_SPI_SHADER_32_AR;
2265 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2266 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2267 else
2268 assert(0);
2269 } else if (format == V_028C70_COLOR_16_16) {
2270 if (swap == V_028C70_SWAP_STD) { /* RG */
2271 blend = V_028714_SPI_SHADER_32_GR;
2272 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2273 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2274 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2275 else
2276 assert(0);
2277 } else /* 16_16_16_16 */
2278 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2279 } else if (ntype == V_028C70_NUMBER_UINT)
2280 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2281 else if (ntype == V_028C70_NUMBER_SINT)
2282 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2283 else if (ntype == V_028C70_NUMBER_FLOAT)
2284 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2285 else
2286 assert(0);
2287 break;
2288
2289 case V_028C70_COLOR_32:
2290 if (swap == V_028C70_SWAP_STD) { /* R */
2291 blend = normal = V_028714_SPI_SHADER_32_R;
2292 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2293 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2295 else
2296 assert(0);
2297 break;
2298
2299 case V_028C70_COLOR_32_32:
2300 if (swap == V_028C70_SWAP_STD) { /* RG */
2301 blend = normal = V_028714_SPI_SHADER_32_GR;
2302 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2303 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2304 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2305 else
2306 assert(0);
2307 break;
2308
2309 case V_028C70_COLOR_32_32_32_32:
2310 case V_028C70_COLOR_8_24:
2311 case V_028C70_COLOR_24_8:
2312 case V_028C70_COLOR_X24_8_32_FLOAT:
2313 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2314 break;
2315
2316 default:
2317 assert(0);
2318 return;
2319 }
2320
2321 /* The DB->CB copy needs 32_ABGR. */
2322 if (is_depth)
2323 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2324
2325 surf->spi_shader_col_format = normal;
2326 surf->spi_shader_col_format_alpha = alpha;
2327 surf->spi_shader_col_format_blend = blend;
2328 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2329 }
2330
2331 static void si_initialize_color_surface(struct si_context *sctx,
2332 struct r600_surface *surf)
2333 {
2334 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2335 unsigned color_info, color_attrib;
2336 unsigned format, swap, ntype, endian;
2337 const struct util_format_description *desc;
2338 int firstchan;
2339 unsigned blend_clamp = 0, blend_bypass = 0;
2340
2341 desc = util_format_description(surf->base.format);
2342 for (firstchan = 0; firstchan < 4; firstchan++) {
2343 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2344 break;
2345 }
2346 }
2347 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2348 ntype = V_028C70_NUMBER_FLOAT;
2349 } else {
2350 ntype = V_028C70_NUMBER_UNORM;
2351 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2352 ntype = V_028C70_NUMBER_SRGB;
2353 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2354 if (desc->channel[firstchan].pure_integer) {
2355 ntype = V_028C70_NUMBER_SINT;
2356 } else {
2357 assert(desc->channel[firstchan].normalized);
2358 ntype = V_028C70_NUMBER_SNORM;
2359 }
2360 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2361 if (desc->channel[firstchan].pure_integer) {
2362 ntype = V_028C70_NUMBER_UINT;
2363 } else {
2364 assert(desc->channel[firstchan].normalized);
2365 ntype = V_028C70_NUMBER_UNORM;
2366 }
2367 }
2368 }
2369
2370 format = si_translate_colorformat(surf->base.format);
2371 if (format == V_028C70_COLOR_INVALID) {
2372 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2373 }
2374 assert(format != V_028C70_COLOR_INVALID);
2375 swap = si_translate_colorswap(surf->base.format, false);
2376 endian = si_colorformat_endian_swap(format);
2377
2378 /* blend clamp should be set for all NORM/SRGB types */
2379 if (ntype == V_028C70_NUMBER_UNORM ||
2380 ntype == V_028C70_NUMBER_SNORM ||
2381 ntype == V_028C70_NUMBER_SRGB)
2382 blend_clamp = 1;
2383
2384 /* set blend bypass according to docs if SINT/UINT or
2385 8/24 COLOR variants */
2386 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2387 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2388 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2389 blend_clamp = 0;
2390 blend_bypass = 1;
2391 }
2392
2393 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2394 if (format == V_028C70_COLOR_8 ||
2395 format == V_028C70_COLOR_8_8 ||
2396 format == V_028C70_COLOR_8_8_8_8)
2397 surf->color_is_int8 = true;
2398 else if (format == V_028C70_COLOR_10_10_10_2 ||
2399 format == V_028C70_COLOR_2_10_10_10)
2400 surf->color_is_int10 = true;
2401 }
2402
2403 color_info = S_028C70_FORMAT(format) |
2404 S_028C70_COMP_SWAP(swap) |
2405 S_028C70_BLEND_CLAMP(blend_clamp) |
2406 S_028C70_BLEND_BYPASS(blend_bypass) |
2407 S_028C70_SIMPLE_FLOAT(1) |
2408 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2409 ntype != V_028C70_NUMBER_SNORM &&
2410 ntype != V_028C70_NUMBER_SRGB &&
2411 format != V_028C70_COLOR_8_24 &&
2412 format != V_028C70_COLOR_24_8) |
2413 S_028C70_NUMBER_TYPE(ntype) |
2414 S_028C70_ENDIAN(endian);
2415
2416 /* Intensity is implemented as Red, so treat it that way. */
2417 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2418 util_format_is_intensity(surf->base.format));
2419
2420 if (rtex->buffer.b.b.nr_samples > 1) {
2421 unsigned log_samples = util_logbase2(rtex->buffer.b.b.nr_samples);
2422 unsigned log_fragments = util_logbase2(rtex->num_color_samples);
2423
2424 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2425 S_028C74_NUM_FRAGMENTS(log_fragments);
2426
2427 if (rtex->surface.fmask_size) {
2428 color_info |= S_028C70_COMPRESSION(1);
2429 unsigned fmask_bankh = util_logbase2(rtex->surface.u.legacy.fmask.bankh);
2430
2431 if (sctx->chip_class == SI) {
2432 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2433 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2434 }
2435 }
2436 }
2437
2438 if (sctx->chip_class >= VI) {
2439 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2440 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2441
2442 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2443 64 for APU because all of our APUs to date use DIMMs which have
2444 a request granularity size of 64B while all other chips have a
2445 32B request size */
2446 if (!sctx->screen->info.has_dedicated_vram)
2447 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2448
2449 if (rtex->num_color_samples > 1) {
2450 if (rtex->surface.bpe == 1)
2451 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2452 else if (rtex->surface.bpe == 2)
2453 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2454 }
2455
2456 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2457 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2458 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2459 }
2460
2461 /* This must be set for fast clear to work without FMASK. */
2462 if (!rtex->surface.fmask_size && sctx->chip_class == SI) {
2463 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2464 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2465 }
2466
2467 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2468 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2469
2470 if (sctx->chip_class >= GFX9) {
2471 unsigned mip0_depth = util_max_layer(&rtex->buffer.b.b, 0);
2472
2473 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2474 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2475 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2476 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2477 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2478 S_028C68_MAX_MIP(rtex->buffer.b.b.last_level);
2479 }
2480
2481 surf->cb_color_view = color_view;
2482 surf->cb_color_info = color_info;
2483 surf->cb_color_attrib = color_attrib;
2484
2485 /* Determine pixel shader export format */
2486 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2487
2488 surf->color_initialized = true;
2489 }
2490
2491 static void si_init_depth_surface(struct si_context *sctx,
2492 struct r600_surface *surf)
2493 {
2494 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2495 unsigned level = surf->base.u.tex.level;
2496 unsigned format, stencil_format;
2497 uint32_t z_info, s_info;
2498
2499 format = si_translate_dbformat(rtex->db_render_format);
2500 stencil_format = rtex->surface.has_stencil ?
2501 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2502
2503 assert(format != V_028040_Z_INVALID);
2504 if (format == V_028040_Z_INVALID)
2505 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->buffer.b.b.format);
2506
2507 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2508 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2509 surf->db_htile_data_base = 0;
2510 surf->db_htile_surface = 0;
2511
2512 if (sctx->chip_class >= GFX9) {
2513 assert(rtex->surface.u.gfx9.surf_offset == 0);
2514 surf->db_depth_base = rtex->buffer.gpu_address >> 8;
2515 surf->db_stencil_base = (rtex->buffer.gpu_address +
2516 rtex->surface.u.gfx9.stencil_offset) >> 8;
2517 z_info = S_028038_FORMAT(format) |
2518 S_028038_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples)) |
2519 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2520 S_028038_MAXMIP(rtex->buffer.b.b.last_level);
2521 s_info = S_02803C_FORMAT(stencil_format) |
2522 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2523 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2524 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2525 surf->db_depth_view |= S_028008_MIPID(level);
2526 surf->db_depth_size = S_02801C_X_MAX(rtex->buffer.b.b.width0 - 1) |
2527 S_02801C_Y_MAX(rtex->buffer.b.b.height0 - 1);
2528
2529 if (si_htile_enabled(rtex, level)) {
2530 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2531 S_028038_ALLOW_EXPCLEAR(1);
2532
2533 if (rtex->tc_compatible_htile) {
2534 unsigned max_zplanes = 4;
2535
2536 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2537 rtex->buffer.b.b.nr_samples > 1)
2538 max_zplanes = 2;
2539
2540 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2541 S_028038_ITERATE_FLUSH(1);
2542 s_info |= S_02803C_ITERATE_FLUSH(1);
2543 }
2544
2545 if (rtex->surface.has_stencil) {
2546 /* Stencil buffer workaround ported from the SI-CI-VI code.
2547 * See that for explanation.
2548 */
2549 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->buffer.b.b.nr_samples <= 1);
2550 } else {
2551 /* Use all HTILE for depth if there's no stencil. */
2552 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2553 }
2554
2555 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2556 rtex->htile_offset) >> 8;
2557 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2558 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2559 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2560 }
2561 } else {
2562 /* SI-CI-VI */
2563 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2564
2565 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2566
2567 surf->db_depth_base = (rtex->buffer.gpu_address +
2568 rtex->surface.u.legacy.level[level].offset) >> 8;
2569 surf->db_stencil_base = (rtex->buffer.gpu_address +
2570 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2571
2572 z_info = S_028040_FORMAT(format) |
2573 S_028040_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples));
2574 s_info = S_028044_FORMAT(stencil_format);
2575 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2576
2577 if (sctx->chip_class >= CIK) {
2578 struct radeon_info *info = &sctx->screen->info;
2579 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2580 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2581 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2582 unsigned tile_mode = info->si_tile_mode_array[index];
2583 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2584 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2585
2586 surf->db_depth_info |=
2587 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2588 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2589 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2590 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2591 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2592 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2593 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2594 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2595 } else {
2596 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2597 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2598 tile_mode_index = si_tile_mode_index(rtex, level, true);
2599 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2600 }
2601
2602 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2603 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2604 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2605 levelinfo->nblk_y) / 64 - 1);
2606
2607 if (si_htile_enabled(rtex, level)) {
2608 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2609 S_028040_ALLOW_EXPCLEAR(1);
2610
2611 if (rtex->surface.has_stencil) {
2612 /* Workaround: For a not yet understood reason, the
2613 * combination of MSAA, fast stencil clear and stencil
2614 * decompress messes with subsequent stencil buffer
2615 * uses. Problem was reproduced on Verde, Bonaire,
2616 * Tonga, and Carrizo.
2617 *
2618 * Disabling EXPCLEAR works around the problem.
2619 *
2620 * Check piglit's arb_texture_multisample-stencil-clear
2621 * test if you want to try changing this.
2622 */
2623 if (rtex->buffer.b.b.nr_samples <= 1)
2624 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2625 } else if (!rtex->tc_compatible_htile) {
2626 /* Use all of the htile_buffer for depth if there's no stencil.
2627 * This must not be set when TC-compatible HTILE is enabled
2628 * due to a hw bug.
2629 */
2630 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2631 }
2632
2633 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2634 rtex->htile_offset) >> 8;
2635 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2636
2637 if (rtex->tc_compatible_htile) {
2638 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2639
2640 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2641 if (rtex->buffer.b.b.nr_samples <= 1)
2642 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2643 else if (rtex->buffer.b.b.nr_samples <= 4)
2644 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2645 else
2646 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2647 }
2648 }
2649 }
2650
2651 surf->db_z_info = z_info;
2652 surf->db_stencil_info = s_info;
2653
2654 surf->depth_initialized = true;
2655 }
2656
2657 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2658 {
2659 if (sctx->decompression_enabled)
2660 return;
2661
2662 if (sctx->framebuffer.state.zsbuf) {
2663 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2664 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2665
2666 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2667
2668 if (rtex->surface.has_stencil)
2669 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2670 }
2671
2672 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2673 while (compressed_cb_mask) {
2674 unsigned i = u_bit_scan(&compressed_cb_mask);
2675 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2676 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2677
2678 if (rtex->surface.fmask_size)
2679 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2680 if (rtex->dcc_gather_statistics)
2681 rtex->separate_dcc_dirty = true;
2682 }
2683 }
2684
2685 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2686 {
2687 for (int i = 0; i < state->nr_cbufs; ++i) {
2688 struct r600_surface *surf = NULL;
2689 struct r600_texture *rtex;
2690
2691 if (!state->cbufs[i])
2692 continue;
2693 surf = (struct r600_surface*)state->cbufs[i];
2694 rtex = (struct r600_texture*)surf->base.texture;
2695
2696 p_atomic_dec(&rtex->framebuffers_bound);
2697 }
2698 }
2699
2700 static void si_set_framebuffer_state(struct pipe_context *ctx,
2701 const struct pipe_framebuffer_state *state)
2702 {
2703 struct si_context *sctx = (struct si_context *)ctx;
2704 struct pipe_constant_buffer constbuf = {0};
2705 struct r600_surface *surf = NULL;
2706 struct r600_texture *rtex;
2707 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2708 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2709 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2710 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2711 bool old_has_stencil =
2712 old_has_zsbuf &&
2713 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2714 bool unbound = false;
2715 int i;
2716
2717 si_update_fb_dirtiness_after_rendering(sctx);
2718
2719 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2720 if (!sctx->framebuffer.state.cbufs[i])
2721 continue;
2722
2723 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2724 if (rtex->dcc_gather_statistics)
2725 vi_separate_dcc_stop_query(sctx, rtex);
2726 }
2727
2728 /* Disable DCC if the formats are incompatible. */
2729 for (i = 0; i < state->nr_cbufs; i++) {
2730 if (!state->cbufs[i])
2731 continue;
2732
2733 surf = (struct r600_surface*)state->cbufs[i];
2734 rtex = (struct r600_texture*)surf->base.texture;
2735
2736 if (!surf->dcc_incompatible)
2737 continue;
2738
2739 /* Since the DCC decompression calls back into set_framebuffer-
2740 * _state, we need to unbind the framebuffer, so that
2741 * vi_separate_dcc_stop_query isn't called twice with the same
2742 * color buffer.
2743 */
2744 if (!unbound) {
2745 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2746 unbound = true;
2747 }
2748
2749 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2750 if (!si_texture_disable_dcc(sctx, rtex))
2751 si_decompress_dcc(sctx, rtex);
2752
2753 surf->dcc_incompatible = false;
2754 }
2755
2756 /* Only flush TC when changing the framebuffer state, because
2757 * the only client not using TC that can change textures is
2758 * the framebuffer.
2759 *
2760 * Wait for compute shaders because of possible transitions:
2761 * - FB write -> shader read
2762 * - shader write -> FB read
2763 *
2764 * DB caches are flushed on demand (using si_decompress_textures).
2765 *
2766 * When MSAA is enabled, CB and TC caches are flushed on demand
2767 * (after FMASK decompression). Shader write -> FB read transitions
2768 * cannot happen for MSAA textures, because MSAA shader images are
2769 * not supported.
2770 *
2771 * Only flush and wait for CB if there is actually a bound color buffer.
2772 */
2773 if (sctx->framebuffer.uncompressed_cb_mask)
2774 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2775 sctx->framebuffer.CB_has_shader_readable_metadata);
2776
2777 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2778
2779 /* u_blitter doesn't invoke depth decompression when it does multiple
2780 * blits in a row, but the only case when it matters for DB is when
2781 * doing generate_mipmap. So here we flush DB manually between
2782 * individual generate_mipmap blits.
2783 * Note that lower mipmap levels aren't compressed.
2784 */
2785 if (sctx->generate_mipmap_for_depth) {
2786 si_make_DB_shader_coherent(sctx, 1, false,
2787 sctx->framebuffer.DB_has_shader_readable_metadata);
2788 } else if (sctx->chip_class == GFX9) {
2789 /* It appears that DB metadata "leaks" in a sequence of:
2790 * - depth clear
2791 * - DCC decompress for shader image writes (with DB disabled)
2792 * - render with DEPTH_BEFORE_SHADER=1
2793 * Flushing DB metadata works around the problem.
2794 */
2795 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2796 }
2797
2798 /* Take the maximum of the old and new count. If the new count is lower,
2799 * dirtying is needed to disable the unbound colorbuffers.
2800 */
2801 sctx->framebuffer.dirty_cbufs |=
2802 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2803 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2804
2805 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2806 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2807
2808 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2809 sctx->framebuffer.spi_shader_col_format = 0;
2810 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2811 sctx->framebuffer.spi_shader_col_format_blend = 0;
2812 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2813 sctx->framebuffer.color_is_int8 = 0;
2814 sctx->framebuffer.color_is_int10 = 0;
2815
2816 sctx->framebuffer.compressed_cb_mask = 0;
2817 sctx->framebuffer.uncompressed_cb_mask = 0;
2818 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2819 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2820 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2821 sctx->framebuffer.any_dst_linear = false;
2822 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2823 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2824
2825 for (i = 0; i < state->nr_cbufs; i++) {
2826 if (!state->cbufs[i])
2827 continue;
2828
2829 surf = (struct r600_surface*)state->cbufs[i];
2830 rtex = (struct r600_texture*)surf->base.texture;
2831
2832 if (!surf->color_initialized) {
2833 si_initialize_color_surface(sctx, surf);
2834 }
2835
2836 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2837 sctx->framebuffer.spi_shader_col_format |=
2838 surf->spi_shader_col_format << (i * 4);
2839 sctx->framebuffer.spi_shader_col_format_alpha |=
2840 surf->spi_shader_col_format_alpha << (i * 4);
2841 sctx->framebuffer.spi_shader_col_format_blend |=
2842 surf->spi_shader_col_format_blend << (i * 4);
2843 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2844 surf->spi_shader_col_format_blend_alpha << (i * 4);
2845
2846 if (surf->color_is_int8)
2847 sctx->framebuffer.color_is_int8 |= 1 << i;
2848 if (surf->color_is_int10)
2849 sctx->framebuffer.color_is_int10 |= 1 << i;
2850
2851 if (rtex->surface.fmask_size)
2852 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2853 else
2854 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2855
2856 /* Don't update nr_color_samples for non-AA buffers.
2857 * (e.g. destination of MSAA resolve)
2858 */
2859 if (rtex->buffer.b.b.nr_samples >= 2 &&
2860 rtex->num_color_samples < rtex->buffer.b.b.nr_samples) {
2861 sctx->framebuffer.nr_color_samples =
2862 MIN2(sctx->framebuffer.nr_color_samples,
2863 rtex->num_color_samples);
2864 }
2865
2866 if (rtex->surface.is_linear)
2867 sctx->framebuffer.any_dst_linear = true;
2868
2869 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2870 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2871
2872 si_context_add_resource_size(sctx, surf->base.texture);
2873
2874 p_atomic_inc(&rtex->framebuffers_bound);
2875
2876 if (rtex->dcc_gather_statistics) {
2877 /* Dirty tracking must be enabled for DCC usage analysis. */
2878 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2879 vi_separate_dcc_start_query(sctx, rtex);
2880 }
2881 }
2882
2883 struct r600_texture *zstex = NULL;
2884
2885 if (state->zsbuf) {
2886 surf = (struct r600_surface*)state->zsbuf;
2887 zstex = (struct r600_texture*)surf->base.texture;
2888
2889 if (!surf->depth_initialized) {
2890 si_init_depth_surface(sctx, surf);
2891 }
2892
2893 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2894 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2895
2896 si_context_add_resource_size(sctx, surf->base.texture);
2897 }
2898
2899 si_update_ps_colorbuf0_slot(sctx);
2900 si_update_poly_offset_state(sctx);
2901 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2902 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2903
2904 if (sctx->screen->dpbb_allowed)
2905 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2906
2907 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2908 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2909
2910 if (sctx->screen->has_out_of_order_rast &&
2911 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2912 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2913 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2914 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2915
2916 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2917 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2918 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2919
2920 /* Set sample locations as fragment shader constants. */
2921 switch (sctx->framebuffer.nr_samples) {
2922 case 1:
2923 constbuf.user_buffer = sctx->sample_locations_1x;
2924 break;
2925 case 2:
2926 constbuf.user_buffer = sctx->sample_locations_2x;
2927 break;
2928 case 4:
2929 constbuf.user_buffer = sctx->sample_locations_4x;
2930 break;
2931 case 8:
2932 constbuf.user_buffer = sctx->sample_locations_8x;
2933 break;
2934 case 16:
2935 constbuf.user_buffer = sctx->sample_locations_16x;
2936 break;
2937 default:
2938 PRINT_ERR("Requested an invalid number of samples %i.\n",
2939 sctx->framebuffer.nr_samples);
2940 assert(0);
2941 }
2942 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2943 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2944
2945 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2946 }
2947
2948 sctx->do_update_shaders = true;
2949
2950 if (!sctx->decompression_enabled) {
2951 /* Prevent textures decompression when the framebuffer state
2952 * changes come from the decompression passes themselves.
2953 */
2954 sctx->need_check_render_feedback = true;
2955 }
2956 }
2957
2958 static void si_emit_framebuffer_state(struct si_context *sctx)
2959 {
2960 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2961 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2962 unsigned i, nr_cbufs = state->nr_cbufs;
2963 struct r600_texture *tex = NULL;
2964 struct r600_surface *cb = NULL;
2965 unsigned cb_color_info = 0;
2966
2967 /* Colorbuffers. */
2968 for (i = 0; i < nr_cbufs; i++) {
2969 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2970 unsigned cb_color_attrib;
2971
2972 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2973 continue;
2974
2975 cb = (struct r600_surface*)state->cbufs[i];
2976 if (!cb) {
2977 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2978 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2979 continue;
2980 }
2981
2982 tex = (struct r600_texture *)cb->base.texture;
2983 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2984 &tex->buffer, RADEON_USAGE_READWRITE,
2985 tex->buffer.b.b.nr_samples > 1 ?
2986 RADEON_PRIO_COLOR_BUFFER_MSAA :
2987 RADEON_PRIO_COLOR_BUFFER);
2988
2989 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2990 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2991 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2992 RADEON_PRIO_CMASK);
2993 }
2994
2995 if (tex->dcc_separate_buffer)
2996 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2997 tex->dcc_separate_buffer,
2998 RADEON_USAGE_READWRITE,
2999 RADEON_PRIO_DCC);
3000
3001 /* Compute mutable surface parameters. */
3002 cb_color_base = tex->buffer.gpu_address >> 8;
3003 cb_color_fmask = 0;
3004 cb_color_cmask = tex->cmask.base_address_reg;
3005 cb_dcc_base = 0;
3006 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3007 cb_color_attrib = cb->cb_color_attrib;
3008
3009 if (cb->base.u.tex.level > 0)
3010 cb_color_info &= C_028C70_FAST_CLEAR;
3011
3012 if (tex->surface.fmask_size) {
3013 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3014 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3015 }
3016
3017 /* Set up DCC. */
3018 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3019 bool is_msaa_resolve_dst = state->cbufs[0] &&
3020 state->cbufs[0]->texture->nr_samples > 1 &&
3021 state->cbufs[1] == &cb->base &&
3022 state->cbufs[1]->texture->nr_samples <= 1;
3023
3024 if (!is_msaa_resolve_dst)
3025 cb_color_info |= S_028C70_DCC_ENABLE(1);
3026
3027 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3028 tex->dcc_offset) >> 8;
3029 cb_dcc_base |= tex->surface.tile_swizzle;
3030 }
3031
3032 if (sctx->chip_class >= GFX9) {
3033 struct gfx9_surf_meta_flags meta;
3034
3035 if (tex->dcc_offset)
3036 meta = tex->surface.u.gfx9.dcc;
3037 else
3038 meta = tex->surface.u.gfx9.cmask;
3039
3040 /* Set mutable surface parameters. */
3041 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3042 cb_color_base |= tex->surface.tile_swizzle;
3043 if (!tex->surface.fmask_size)
3044 cb_color_fmask = cb_color_base;
3045 if (cb->base.u.tex.level > 0)
3046 cb_color_cmask = cb_color_base;
3047 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3048 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3049 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3050 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3051
3052 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3053 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3054 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3055 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3056 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3057 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3058 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3059 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3060 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3061 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3062 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3063 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3064 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3065 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3066 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3067 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3068
3069 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3070 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3071 } else {
3072 /* Compute mutable surface parameters (SI-CI-VI). */
3073 const struct legacy_surf_level *level_info =
3074 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3075 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3076 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3077
3078 cb_color_base += level_info->offset >> 8;
3079 /* Only macrotiled modes can set tile swizzle. */
3080 if (level_info->mode == RADEON_SURF_MODE_2D)
3081 cb_color_base |= tex->surface.tile_swizzle;
3082
3083 if (!tex->surface.fmask_size)
3084 cb_color_fmask = cb_color_base;
3085 if (cb->base.u.tex.level > 0)
3086 cb_color_cmask = cb_color_base;
3087 if (cb_dcc_base)
3088 cb_dcc_base += level_info->dcc_offset >> 8;
3089
3090 pitch_tile_max = level_info->nblk_x / 8 - 1;
3091 slice_tile_max = level_info->nblk_x *
3092 level_info->nblk_y / 64 - 1;
3093 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3094
3095 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3096 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3097 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3098
3099 if (tex->surface.fmask_size) {
3100 if (sctx->chip_class >= CIK)
3101 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3102 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3103 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3104 } else {
3105 /* This must be set for fast clear to work without FMASK. */
3106 if (sctx->chip_class >= CIK)
3107 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3108 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3109 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3110 }
3111
3112 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3113 sctx->chip_class >= VI ? 14 : 13);
3114 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3115 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3116 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3117 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3118 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3119 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3120 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3121 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3122 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3123 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3124 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3125 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3126 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3127
3128 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3129 radeon_emit(cs, cb_dcc_base);
3130 }
3131 }
3132 for (; i < 8 ; i++)
3133 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3134 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3135
3136 /* ZS buffer. */
3137 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3138 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3139 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3140
3141 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3142 &rtex->buffer, RADEON_USAGE_READWRITE,
3143 zb->base.texture->nr_samples > 1 ?
3144 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3145 RADEON_PRIO_DEPTH_BUFFER);
3146
3147 if (sctx->chip_class >= GFX9) {
3148 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3149 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3150 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3151 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3152
3153 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3154 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3155 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3156 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3157 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3158 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3159 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3160 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3161 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3162 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3163 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3164 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3165
3166 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3167 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3168 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3169 } else {
3170 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3171
3172 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3173 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3174 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3175 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3176 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3177 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3178 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3179 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3180 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3181 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3182 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3183 }
3184
3185 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3186 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3187 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3188
3189 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3190 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3191 } else if (sctx->framebuffer.dirty_zsbuf) {
3192 if (sctx->chip_class >= GFX9)
3193 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3194 else
3195 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3196
3197 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3198 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3199 }
3200
3201 /* Framebuffer dimensions. */
3202 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3203 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3204 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3205
3206 if (sctx->screen->dfsm_allowed) {
3207 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3208 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3209 }
3210
3211 sctx->framebuffer.dirty_cbufs = 0;
3212 sctx->framebuffer.dirty_zsbuf = false;
3213 }
3214
3215 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3216 {
3217 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3218 unsigned nr_samples = sctx->framebuffer.nr_samples;
3219 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3220
3221 /* Smoothing (only possible with nr_samples == 1) uses the same
3222 * sample locations as the MSAA it simulates.
3223 */
3224 if (nr_samples <= 1 && sctx->smoothing_enabled)
3225 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3226
3227 /* On Polaris, the small primitive filter uses the sample locations
3228 * even when MSAA is off, so we need to make sure they're set to 0.
3229 */
3230 if (has_msaa_sample_loc_bug)
3231 nr_samples = MAX2(nr_samples, 1);
3232
3233 if (nr_samples != sctx->sample_locs_num_samples) {
3234 sctx->sample_locs_num_samples = nr_samples;
3235 si_emit_sample_locations(cs, nr_samples);
3236 }
3237
3238 if (sctx->family >= CHIP_POLARIS10) {
3239 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3240 unsigned small_prim_filter_cntl =
3241 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3242 /* line bug */
3243 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3244
3245 /* The alternative of setting sample locations to 0 would
3246 * require a DB flush to avoid Z errors, see
3247 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3248 */
3249 if (has_msaa_sample_loc_bug &&
3250 sctx->framebuffer.nr_samples > 1 &&
3251 rs && !rs->multisample_enable)
3252 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3253
3254 radeon_opt_set_context_reg(sctx,
3255 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3256 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3257 small_prim_filter_cntl);
3258 }
3259 }
3260
3261 static bool si_out_of_order_rasterization(struct si_context *sctx)
3262 {
3263 struct si_state_blend *blend = sctx->queued.named.blend;
3264 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3265
3266 if (!sctx->screen->has_out_of_order_rast)
3267 return false;
3268
3269 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3270
3271 if (blend) {
3272 colormask &= blend->cb_target_enabled_4bit;
3273 } else {
3274 colormask = 0;
3275 }
3276
3277 /* Conservative: No logic op. */
3278 if (colormask && blend->logicop_enable)
3279 return false;
3280
3281 struct si_dsa_order_invariance dsa_order_invariant = {
3282 .zs = true, .pass_set = true, .pass_last = false
3283 };
3284
3285 if (sctx->framebuffer.state.zsbuf) {
3286 struct r600_texture *zstex =
3287 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3288 bool has_stencil = zstex->surface.has_stencil;
3289 dsa_order_invariant = dsa->order_invariance[has_stencil];
3290 if (!dsa_order_invariant.zs)
3291 return false;
3292
3293 /* The set of PS invocations is always order invariant,
3294 * except when early Z/S tests are requested. */
3295 if (sctx->ps_shader.cso &&
3296 sctx->ps_shader.cso->info.writes_memory &&
3297 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3298 !dsa_order_invariant.pass_set)
3299 return false;
3300
3301 if (sctx->num_perfect_occlusion_queries != 0 &&
3302 !dsa_order_invariant.pass_set)
3303 return false;
3304 }
3305
3306 if (!colormask)
3307 return true;
3308
3309 unsigned blendmask = colormask & blend->blend_enable_4bit;
3310
3311 if (blendmask) {
3312 /* Only commutative blending. */
3313 if (blendmask & ~blend->commutative_4bit)
3314 return false;
3315
3316 if (!dsa_order_invariant.pass_set)
3317 return false;
3318 }
3319
3320 if (colormask & ~blendmask) {
3321 if (!dsa_order_invariant.pass_last)
3322 return false;
3323 }
3324
3325 return true;
3326 }
3327
3328 static void si_emit_msaa_config(struct si_context *sctx)
3329 {
3330 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3331 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3332 /* 33% faster rendering to linear color buffers */
3333 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3334 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3335 unsigned sc_mode_cntl_1 =
3336 S_028A4C_WALK_SIZE(dst_is_linear) |
3337 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3338 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3339 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3340 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3341 /* always 1: */
3342 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3343 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3344 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3345 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3346 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3347 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3348 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3349 S_028804_INCOHERENT_EQAA_READS(1) |
3350 S_028804_INTERPOLATE_COMP_Z(1) |
3351 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3352 unsigned coverage_samples, color_samples, z_samples;
3353
3354 /* S: Coverage samples (up to 16x):
3355 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3356 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3357 *
3358 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3359 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3360 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3361 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3362 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3363 * # Z samples).
3364 *
3365 * F: Color samples (up to 8x, must be <= coverage samples):
3366 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3367 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3368 *
3369 * Can be anything between coverage and color samples:
3370 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3371 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3372 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3373 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3374 * # All are currently set the same as coverage samples.
3375 *
3376 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3377 * flag for undefined color samples. A shader-based resolve must handle unknowns
3378 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3379 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3380 * useful. The CB resolve always drops unknowns.
3381 *
3382 * Sensible AA configurations:
3383 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3384 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3385 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3386 * EQAA 8s 8z 8f = 8x MSAA
3387 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3388 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3389 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3390 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3391 * EQAA 4s 4z 4f = 4x MSAA
3392 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3393 * EQAA 2s 2z 2f = 2x MSAA
3394 */
3395 if (sctx->framebuffer.nr_samples > 1) {
3396 coverage_samples = sctx->framebuffer.nr_samples;
3397 color_samples = sctx->framebuffer.nr_color_samples;
3398
3399 if (sctx->framebuffer.state.zsbuf) {
3400 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3401 z_samples = MAX2(1, z_samples);
3402 } else {
3403 z_samples = coverage_samples;
3404 }
3405 } else if (sctx->smoothing_enabled) {
3406 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3407 } else {
3408 coverage_samples = color_samples = z_samples = 1;
3409 }
3410
3411 /* Required by OpenGL line rasterization.
3412 *
3413 * TODO: We should also enable perpendicular endcaps for AA lines,
3414 * but that requires implementing line stippling in the pixel
3415 * shader. SC can only do line stippling with axis-aligned
3416 * endcaps.
3417 */
3418 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3419 unsigned sc_aa_config = 0;
3420
3421 if (coverage_samples > 1) {
3422 /* distance from the pixel center, indexed by log2(nr_samples) */
3423 static unsigned max_dist[] = {
3424 0, /* unused */
3425 4, /* 2x MSAA */
3426 6, /* 4x MSAA */
3427 7, /* 8x MSAA */
3428 8, /* 16x MSAA */
3429 };
3430 unsigned log_samples = util_logbase2(coverage_samples);
3431 unsigned log_z_samples = util_logbase2(z_samples);
3432 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3433 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3434
3435 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3436 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3437 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3438 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3439
3440 if (sctx->framebuffer.nr_samples > 1) {
3441 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3442 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3443 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3444 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3445 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3446 } else if (sctx->smoothing_enabled) {
3447 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3448 }
3449 }
3450
3451 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3452 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3453 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3454 sc_aa_config);
3455 /* R_028804_DB_EQAA */
3456 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3457 db_eqaa);
3458 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3459 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3460 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3461
3462 /* GFX9: Flush DFSM when the AA mode changes. */
3463 if (sctx->screen->dfsm_allowed) {
3464 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3465 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3466 }
3467 }
3468
3469 void si_update_ps_iter_samples(struct si_context *sctx)
3470 {
3471 if (sctx->framebuffer.nr_samples > 1)
3472 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3473 if (sctx->screen->dpbb_allowed)
3474 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3475 }
3476
3477 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3478 {
3479 struct si_context *sctx = (struct si_context *)ctx;
3480
3481 /* The hardware can only do sample shading with 2^n samples. */
3482 min_samples = util_next_power_of_two(min_samples);
3483
3484 if (sctx->ps_iter_samples == min_samples)
3485 return;
3486
3487 sctx->ps_iter_samples = min_samples;
3488 sctx->do_update_shaders = true;
3489
3490 si_update_ps_iter_samples(sctx);
3491 }
3492
3493 /*
3494 * Samplers
3495 */
3496
3497 /**
3498 * Build the sampler view descriptor for a buffer texture.
3499 * @param state 256-bit descriptor; only the high 128 bits are filled in
3500 */
3501 void
3502 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3503 enum pipe_format format,
3504 unsigned offset, unsigned size,
3505 uint32_t *state)
3506 {
3507 const struct util_format_description *desc;
3508 int first_non_void;
3509 unsigned stride;
3510 unsigned num_records;
3511 unsigned num_format, data_format;
3512
3513 desc = util_format_description(format);
3514 first_non_void = util_format_get_first_non_void_channel(format);
3515 stride = desc->block.bits / 8;
3516 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3517 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3518
3519 num_records = size / stride;
3520 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3521
3522 /* The NUM_RECORDS field has a different meaning depending on the chip,
3523 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3524 *
3525 * SI-CIK:
3526 * - If STRIDE == 0, it's in byte units.
3527 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3528 *
3529 * VI:
3530 * - For SMEM and STRIDE == 0, it's in byte units.
3531 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3532 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3533 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3534 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3535 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3536 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3537 * That way the same descriptor can be used by both SMEM and VMEM.
3538 *
3539 * GFX9:
3540 * - For SMEM and STRIDE == 0, it's in byte units.
3541 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3542 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3543 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3544 */
3545 if (screen->info.chip_class >= GFX9)
3546 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3547 * from STRIDE to bytes. This works around it by setting
3548 * NUM_RECORDS to at least the size of one element, so that
3549 * the first element is readable when IDXEN == 0.
3550 *
3551 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3552 * IDXEN is enforced?
3553 */
3554 num_records = num_records ? MAX2(num_records, stride) : 0;
3555 else if (screen->info.chip_class == VI)
3556 num_records *= stride;
3557
3558 state[4] = 0;
3559 state[5] = S_008F04_STRIDE(stride);
3560 state[6] = num_records;
3561 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3562 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3563 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3564 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3565 S_008F0C_NUM_FORMAT(num_format) |
3566 S_008F0C_DATA_FORMAT(data_format);
3567 }
3568
3569 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3570 {
3571 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3572
3573 if (swizzle[3] == PIPE_SWIZZLE_X) {
3574 /* For the pre-defined border color values (white, opaque
3575 * black, transparent black), the only thing that matters is
3576 * that the alpha channel winds up in the correct place
3577 * (because the RGB channels are all the same) so either of
3578 * these enumerations will work.
3579 */
3580 if (swizzle[2] == PIPE_SWIZZLE_Y)
3581 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3582 else
3583 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3584 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3585 if (swizzle[1] == PIPE_SWIZZLE_Y)
3586 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3587 else
3588 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3589 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3590 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3591 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3592 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3593 }
3594
3595 return bc_swizzle;
3596 }
3597
3598 /**
3599 * Build the sampler view descriptor for a texture.
3600 */
3601 void
3602 si_make_texture_descriptor(struct si_screen *screen,
3603 struct r600_texture *tex,
3604 bool sampler,
3605 enum pipe_texture_target target,
3606 enum pipe_format pipe_format,
3607 const unsigned char state_swizzle[4],
3608 unsigned first_level, unsigned last_level,
3609 unsigned first_layer, unsigned last_layer,
3610 unsigned width, unsigned height, unsigned depth,
3611 uint32_t *state,
3612 uint32_t *fmask_state)
3613 {
3614 struct pipe_resource *res = &tex->buffer.b.b;
3615 const struct util_format_description *desc;
3616 unsigned char swizzle[4];
3617 int first_non_void;
3618 unsigned num_format, data_format, type, num_samples;
3619 uint64_t va;
3620
3621 desc = util_format_description(pipe_format);
3622
3623 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3624 MAX2(1, res->nr_samples) : tex->num_color_samples;
3625
3626 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3627 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3628 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3629 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3630
3631 switch (pipe_format) {
3632 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3633 case PIPE_FORMAT_X32_S8X24_UINT:
3634 case PIPE_FORMAT_X8Z24_UNORM:
3635 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3636 break;
3637 case PIPE_FORMAT_X24S8_UINT:
3638 /*
3639 * X24S8 is implemented as an 8_8_8_8 data format, to
3640 * fix texture gathers. This affects at least
3641 * GL45-CTS.texture_cube_map_array.sampling on VI.
3642 */
3643 if (screen->info.chip_class <= VI)
3644 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3645 else
3646 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3647 break;
3648 default:
3649 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3650 }
3651 } else {
3652 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3653 }
3654
3655 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3656
3657 switch (pipe_format) {
3658 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3659 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3660 break;
3661 default:
3662 if (first_non_void < 0) {
3663 if (util_format_is_compressed(pipe_format)) {
3664 switch (pipe_format) {
3665 case PIPE_FORMAT_DXT1_SRGB:
3666 case PIPE_FORMAT_DXT1_SRGBA:
3667 case PIPE_FORMAT_DXT3_SRGBA:
3668 case PIPE_FORMAT_DXT5_SRGBA:
3669 case PIPE_FORMAT_BPTC_SRGBA:
3670 case PIPE_FORMAT_ETC2_SRGB8:
3671 case PIPE_FORMAT_ETC2_SRGB8A1:
3672 case PIPE_FORMAT_ETC2_SRGBA8:
3673 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3674 break;
3675 case PIPE_FORMAT_RGTC1_SNORM:
3676 case PIPE_FORMAT_LATC1_SNORM:
3677 case PIPE_FORMAT_RGTC2_SNORM:
3678 case PIPE_FORMAT_LATC2_SNORM:
3679 case PIPE_FORMAT_ETC2_R11_SNORM:
3680 case PIPE_FORMAT_ETC2_RG11_SNORM:
3681 /* implies float, so use SNORM/UNORM to determine
3682 whether data is signed or not */
3683 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3684 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3685 break;
3686 default:
3687 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3688 break;
3689 }
3690 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3691 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3692 } else {
3693 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3694 }
3695 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3696 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3697 } else {
3698 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3699
3700 switch (desc->channel[first_non_void].type) {
3701 case UTIL_FORMAT_TYPE_FLOAT:
3702 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3703 break;
3704 case UTIL_FORMAT_TYPE_SIGNED:
3705 if (desc->channel[first_non_void].normalized)
3706 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3707 else if (desc->channel[first_non_void].pure_integer)
3708 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3709 else
3710 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3711 break;
3712 case UTIL_FORMAT_TYPE_UNSIGNED:
3713 if (desc->channel[first_non_void].normalized)
3714 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3715 else if (desc->channel[first_non_void].pure_integer)
3716 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3717 else
3718 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3719 }
3720 }
3721 }
3722
3723 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3724 if (data_format == ~0) {
3725 data_format = 0;
3726 }
3727
3728 /* S8 with Z32 HTILE needs a special format. */
3729 if (screen->info.chip_class >= GFX9 &&
3730 pipe_format == PIPE_FORMAT_S8_UINT &&
3731 tex->tc_compatible_htile)
3732 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3733
3734 if (!sampler &&
3735 (res->target == PIPE_TEXTURE_CUBE ||
3736 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3737 (screen->info.chip_class <= VI &&
3738 res->target == PIPE_TEXTURE_3D))) {
3739 /* For the purpose of shader images, treat cube maps and 3D
3740 * textures as 2D arrays. For 3D textures, the address
3741 * calculations for mipmaps are different, so we rely on the
3742 * caller to effectively disable mipmaps.
3743 */
3744 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3745
3746 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3747 } else {
3748 type = si_tex_dim(screen, tex, target, num_samples);
3749 }
3750
3751 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3752 height = 1;
3753 depth = res->array_size;
3754 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3755 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3756 if (sampler || res->target != PIPE_TEXTURE_3D)
3757 depth = res->array_size;
3758 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3759 depth = res->array_size / 6;
3760
3761 state[0] = 0;
3762 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3763 S_008F14_NUM_FORMAT_GFX6(num_format));
3764 state[2] = (S_008F18_WIDTH(width - 1) |
3765 S_008F18_HEIGHT(height - 1) |
3766 S_008F18_PERF_MOD(4));
3767 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3768 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3769 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3770 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3771 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3772 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3773 util_logbase2(num_samples) :
3774 last_level) |
3775 S_008F1C_TYPE(type));
3776 state[4] = 0;
3777 state[5] = S_008F24_BASE_ARRAY(first_layer);
3778 state[6] = 0;
3779 state[7] = 0;
3780
3781 if (screen->info.chip_class >= GFX9) {
3782 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3783
3784 /* Depth is the the last accessible layer on Gfx9.
3785 * The hw doesn't need to know the total number of layers.
3786 */
3787 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3788 state[4] |= S_008F20_DEPTH(depth - 1);
3789 else
3790 state[4] |= S_008F20_DEPTH(last_layer);
3791
3792 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3793 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3794 util_logbase2(num_samples) :
3795 tex->buffer.b.b.last_level);
3796 } else {
3797 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3798 state[4] |= S_008F20_DEPTH(depth - 1);
3799 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3800 }
3801
3802 if (tex->dcc_offset) {
3803 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3804 } else {
3805 /* The last dword is unused by hw. The shader uses it to clear
3806 * bits in the first dword of sampler state.
3807 */
3808 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3809 if (first_level == last_level)
3810 state[7] = C_008F30_MAX_ANISO_RATIO;
3811 else
3812 state[7] = 0xffffffff;
3813 }
3814 }
3815
3816 /* Initialize the sampler view for FMASK. */
3817 if (tex->surface.fmask_size) {
3818 uint32_t data_format, num_format;
3819
3820 va = tex->buffer.gpu_address + tex->fmask_offset;
3821
3822 #define FMASK(s,f) (((unsigned)(s) * 16) + (f))
3823 if (screen->info.chip_class >= GFX9) {
3824 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3825 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3826 case FMASK(2,1):
3827 num_format = V_008F14_IMG_FMASK_8_2_1;
3828 break;
3829 case FMASK(2,2):
3830 num_format = V_008F14_IMG_FMASK_8_2_2;
3831 break;
3832 case FMASK(4,1):
3833 num_format = V_008F14_IMG_FMASK_8_4_1;
3834 break;
3835 case FMASK(4,2):
3836 num_format = V_008F14_IMG_FMASK_8_4_2;
3837 break;
3838 case FMASK(4,4):
3839 num_format = V_008F14_IMG_FMASK_8_4_4;
3840 break;
3841 case FMASK(8,1):
3842 num_format = V_008F14_IMG_FMASK_8_8_1;
3843 break;
3844 case FMASK(8,2):
3845 num_format = V_008F14_IMG_FMASK_16_8_2;
3846 break;
3847 case FMASK(8,4):
3848 num_format = V_008F14_IMG_FMASK_32_8_4;
3849 break;
3850 case FMASK(8,8):
3851 num_format = V_008F14_IMG_FMASK_32_8_8;
3852 break;
3853 case FMASK(16,1):
3854 num_format = V_008F14_IMG_FMASK_16_16_1;
3855 break;
3856 case FMASK(16,2):
3857 num_format = V_008F14_IMG_FMASK_32_16_2;
3858 break;
3859 case FMASK(16,4):
3860 num_format = V_008F14_IMG_FMASK_64_16_4;
3861 break;
3862 case FMASK(16,8):
3863 num_format = V_008F14_IMG_FMASK_64_16_8;
3864 break;
3865 default:
3866 unreachable("invalid nr_samples");
3867 }
3868 } else {
3869 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3870 case FMASK(2,1):
3871 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3872 break;
3873 case FMASK(2,2):
3874 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3875 break;
3876 case FMASK(4,1):
3877 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3878 break;
3879 case FMASK(4,2):
3880 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3881 break;
3882 case FMASK(4,4):
3883 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3884 break;
3885 case FMASK(8,1):
3886 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3887 break;
3888 case FMASK(8,2):
3889 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3890 break;
3891 case FMASK(8,4):
3892 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3893 break;
3894 case FMASK(8,8):
3895 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3896 break;
3897 case FMASK(16,1):
3898 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3899 break;
3900 case FMASK(16,2):
3901 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3902 break;
3903 case FMASK(16,4):
3904 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3905 break;
3906 case FMASK(16,8):
3907 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3908 break;
3909 default:
3910 unreachable("invalid nr_samples");
3911 }
3912 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3913 }
3914 #undef FMASK
3915
3916 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3917 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3918 S_008F14_DATA_FORMAT_GFX6(data_format) |
3919 S_008F14_NUM_FORMAT_GFX6(num_format);
3920 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3921 S_008F18_HEIGHT(height - 1);
3922 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3923 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3924 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3925 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3926 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3927 fmask_state[4] = 0;
3928 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3929 fmask_state[6] = 0;
3930 fmask_state[7] = 0;
3931
3932 if (screen->info.chip_class >= GFX9) {
3933 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3934 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3935 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3936 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3937 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3938 } else {
3939 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3940 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3941 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3942 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3943 }
3944 }
3945 }
3946
3947 /**
3948 * Create a sampler view.
3949 *
3950 * @param ctx context
3951 * @param texture texture
3952 * @param state sampler view template
3953 * @param width0 width0 override (for compressed textures as int)
3954 * @param height0 height0 override (for compressed textures as int)
3955 * @param force_level set the base address to the level (for compressed textures)
3956 */
3957 struct pipe_sampler_view *
3958 si_create_sampler_view_custom(struct pipe_context *ctx,
3959 struct pipe_resource *texture,
3960 const struct pipe_sampler_view *state,
3961 unsigned width0, unsigned height0,
3962 unsigned force_level)
3963 {
3964 struct si_context *sctx = (struct si_context*)ctx;
3965 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3966 struct r600_texture *tmp = (struct r600_texture*)texture;
3967 unsigned base_level, first_level, last_level;
3968 unsigned char state_swizzle[4];
3969 unsigned height, depth, width;
3970 unsigned last_layer = state->u.tex.last_layer;
3971 enum pipe_format pipe_format;
3972 const struct legacy_surf_level *surflevel;
3973
3974 if (!view)
3975 return NULL;
3976
3977 /* initialize base object */
3978 view->base = *state;
3979 view->base.texture = NULL;
3980 view->base.reference.count = 1;
3981 view->base.context = ctx;
3982
3983 assert(texture);
3984 pipe_resource_reference(&view->base.texture, texture);
3985
3986 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3987 state->format == PIPE_FORMAT_S8X24_UINT ||
3988 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3989 state->format == PIPE_FORMAT_S8_UINT)
3990 view->is_stencil_sampler = true;
3991
3992 /* Buffer resource. */
3993 if (texture->target == PIPE_BUFFER) {
3994 si_make_buffer_descriptor(sctx->screen,
3995 r600_resource(texture),
3996 state->format,
3997 state->u.buf.offset,
3998 state->u.buf.size,
3999 view->state);
4000 return &view->base;
4001 }
4002
4003 state_swizzle[0] = state->swizzle_r;
4004 state_swizzle[1] = state->swizzle_g;
4005 state_swizzle[2] = state->swizzle_b;
4006 state_swizzle[3] = state->swizzle_a;
4007
4008 base_level = 0;
4009 first_level = state->u.tex.first_level;
4010 last_level = state->u.tex.last_level;
4011 width = width0;
4012 height = height0;
4013 depth = texture->depth0;
4014
4015 if (sctx->chip_class <= VI && force_level) {
4016 assert(force_level == first_level &&
4017 force_level == last_level);
4018 base_level = force_level;
4019 first_level = 0;
4020 last_level = 0;
4021 width = u_minify(width, force_level);
4022 height = u_minify(height, force_level);
4023 depth = u_minify(depth, force_level);
4024 }
4025
4026 /* This is not needed if state trackers set last_layer correctly. */
4027 if (state->target == PIPE_TEXTURE_1D ||
4028 state->target == PIPE_TEXTURE_2D ||
4029 state->target == PIPE_TEXTURE_RECT ||
4030 state->target == PIPE_TEXTURE_CUBE)
4031 last_layer = state->u.tex.first_layer;
4032
4033 /* Texturing with separate depth and stencil. */
4034 pipe_format = state->format;
4035
4036 /* Depth/stencil texturing sometimes needs separate texture. */
4037 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
4038 if (!tmp->flushed_depth_texture &&
4039 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4040 pipe_resource_reference(&view->base.texture, NULL);
4041 FREE(view);
4042 return NULL;
4043 }
4044
4045 assert(tmp->flushed_depth_texture);
4046
4047 /* Override format for the case where the flushed texture
4048 * contains only Z or only S.
4049 */
4050 if (tmp->flushed_depth_texture->buffer.b.b.format != tmp->buffer.b.b.format)
4051 pipe_format = tmp->flushed_depth_texture->buffer.b.b.format;
4052
4053 tmp = tmp->flushed_depth_texture;
4054 }
4055
4056 surflevel = tmp->surface.u.legacy.level;
4057
4058 if (tmp->db_compatible) {
4059 if (!view->is_stencil_sampler)
4060 pipe_format = tmp->db_render_format;
4061
4062 switch (pipe_format) {
4063 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4064 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4065 break;
4066 case PIPE_FORMAT_X8Z24_UNORM:
4067 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4068 /* Z24 is always stored like this for DB
4069 * compatibility.
4070 */
4071 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4072 break;
4073 case PIPE_FORMAT_X24S8_UINT:
4074 case PIPE_FORMAT_S8X24_UINT:
4075 case PIPE_FORMAT_X32_S8X24_UINT:
4076 pipe_format = PIPE_FORMAT_S8_UINT;
4077 surflevel = tmp->surface.u.legacy.stencil_level;
4078 break;
4079 default:;
4080 }
4081 }
4082
4083 view->dcc_incompatible =
4084 vi_dcc_formats_are_incompatible(texture,
4085 state->u.tex.first_level,
4086 state->format);
4087
4088 si_make_texture_descriptor(sctx->screen, tmp, true,
4089 state->target, pipe_format, state_swizzle,
4090 first_level, last_level,
4091 state->u.tex.first_layer, last_layer,
4092 width, height, depth,
4093 view->state, view->fmask_state);
4094
4095 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4096 view->is_integer =
4097 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4098 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4099 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4100 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4101 view->base_level_info = &surflevel[base_level];
4102 view->base_level = base_level;
4103 view->block_width = util_format_get_blockwidth(pipe_format);
4104 return &view->base;
4105 }
4106
4107 static struct pipe_sampler_view *
4108 si_create_sampler_view(struct pipe_context *ctx,
4109 struct pipe_resource *texture,
4110 const struct pipe_sampler_view *state)
4111 {
4112 return si_create_sampler_view_custom(ctx, texture, state,
4113 texture ? texture->width0 : 0,
4114 texture ? texture->height0 : 0, 0);
4115 }
4116
4117 static void si_sampler_view_destroy(struct pipe_context *ctx,
4118 struct pipe_sampler_view *state)
4119 {
4120 struct si_sampler_view *view = (struct si_sampler_view *)state;
4121
4122 pipe_resource_reference(&state->texture, NULL);
4123 FREE(view);
4124 }
4125
4126 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4127 {
4128 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4129 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4130 (linear_filter &&
4131 (wrap == PIPE_TEX_WRAP_CLAMP ||
4132 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4133 }
4134
4135 static uint32_t si_translate_border_color(struct si_context *sctx,
4136 const struct pipe_sampler_state *state,
4137 const union pipe_color_union *color,
4138 bool is_integer)
4139 {
4140 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4141 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4142
4143 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4144 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4145 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4146 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4147
4148 #define simple_border_types(elt) \
4149 do { \
4150 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4151 color->elt[2] == 0 && color->elt[3] == 0) \
4152 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4153 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4154 color->elt[2] == 0 && color->elt[3] == 1) \
4155 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4156 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4157 color->elt[2] == 1 && color->elt[3] == 1) \
4158 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4159 } while (false)
4160
4161 if (is_integer)
4162 simple_border_types(ui);
4163 else
4164 simple_border_types(f);
4165
4166 #undef simple_border_types
4167
4168 int i;
4169
4170 /* Check if the border has been uploaded already. */
4171 for (i = 0; i < sctx->border_color_count; i++)
4172 if (memcmp(&sctx->border_color_table[i], color,
4173 sizeof(*color)) == 0)
4174 break;
4175
4176 if (i >= SI_MAX_BORDER_COLORS) {
4177 /* Getting 4096 unique border colors is very unlikely. */
4178 fprintf(stderr, "radeonsi: The border color table is full. "
4179 "Any new border colors will be just black. "
4180 "Please file a bug.\n");
4181 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4182 }
4183
4184 if (i == sctx->border_color_count) {
4185 /* Upload a new border color. */
4186 memcpy(&sctx->border_color_table[i], color,
4187 sizeof(*color));
4188 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4189 color, sizeof(*color));
4190 sctx->border_color_count++;
4191 }
4192
4193 return S_008F3C_BORDER_COLOR_PTR(i) |
4194 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4195 }
4196
4197 static inline int S_FIXED(float value, unsigned frac_bits)
4198 {
4199 return value * (1 << frac_bits);
4200 }
4201
4202 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4203 {
4204 if (filter == PIPE_TEX_FILTER_LINEAR)
4205 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4206 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4207 else
4208 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4209 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4210 }
4211
4212 static inline unsigned si_tex_aniso_filter(unsigned filter)
4213 {
4214 if (filter < 2)
4215 return 0;
4216 if (filter < 4)
4217 return 1;
4218 if (filter < 8)
4219 return 2;
4220 if (filter < 16)
4221 return 3;
4222 return 4;
4223 }
4224
4225 static void *si_create_sampler_state(struct pipe_context *ctx,
4226 const struct pipe_sampler_state *state)
4227 {
4228 struct si_context *sctx = (struct si_context *)ctx;
4229 struct si_screen *sscreen = sctx->screen;
4230 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4231 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4232 : state->max_anisotropy;
4233 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4234 union pipe_color_union clamped_border_color;
4235
4236 if (!rstate) {
4237 return NULL;
4238 }
4239
4240 #ifdef DEBUG
4241 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4242 #endif
4243 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4244 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4245 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4246 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4247 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4248 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4249 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4250 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4251 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4252 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4253 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4254 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4255 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4256 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4257 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4258 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4259 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4260 S_008F38_MIP_POINT_PRECLAMP(0) |
4261 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4262 S_008F38_FILTER_PREC_FIX(1) |
4263 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4264 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4265
4266 /* Create sampler resource for integer textures. */
4267 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4268 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4269
4270 /* Create sampler resource for upgraded depth textures. */
4271 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4272
4273 for (unsigned i = 0; i < 4; ++i) {
4274 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4275 * when the border color is 1.0. */
4276 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4277 }
4278
4279 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4280 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4281 else
4282 rstate->upgraded_depth_val[3] =
4283 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4284 S_008F3C_UPGRADED_DEPTH(1);
4285
4286 return rstate;
4287 }
4288
4289 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4290 {
4291 struct si_context *sctx = (struct si_context *)ctx;
4292
4293 if (sctx->sample_mask == (uint16_t)sample_mask)
4294 return;
4295
4296 sctx->sample_mask = sample_mask;
4297 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4298 }
4299
4300 static void si_emit_sample_mask(struct si_context *sctx)
4301 {
4302 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4303 unsigned mask = sctx->sample_mask;
4304
4305 /* Needed for line and polygon smoothing as well as for the Polaris
4306 * small primitive filter. We expect the state tracker to take care of
4307 * this for us.
4308 */
4309 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4310 (mask & 1 && sctx->blitter->running));
4311
4312 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4313 radeon_emit(cs, mask | (mask << 16));
4314 radeon_emit(cs, mask | (mask << 16));
4315 }
4316
4317 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4318 {
4319 #ifdef DEBUG
4320 struct si_sampler_state *s = state;
4321
4322 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4323 s->magic = 0;
4324 #endif
4325 free(state);
4326 }
4327
4328 /*
4329 * Vertex elements & buffers
4330 */
4331
4332 static void *si_create_vertex_elements(struct pipe_context *ctx,
4333 unsigned count,
4334 const struct pipe_vertex_element *elements)
4335 {
4336 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4337 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4338 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4339 int i;
4340
4341 assert(count <= SI_MAX_ATTRIBS);
4342 if (!v)
4343 return NULL;
4344
4345 v->count = count;
4346 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4347
4348 for (i = 0; i < count; ++i) {
4349 const struct util_format_description *desc;
4350 const struct util_format_channel_description *channel;
4351 unsigned data_format, num_format;
4352 int first_non_void;
4353 unsigned vbo_index = elements[i].vertex_buffer_index;
4354 unsigned char swizzle[4];
4355
4356 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4357 FREE(v);
4358 return NULL;
4359 }
4360
4361 if (elements[i].instance_divisor) {
4362 v->uses_instance_divisors = true;
4363 v->instance_divisors[i] = elements[i].instance_divisor;
4364
4365 if (v->instance_divisors[i] == 1)
4366 v->instance_divisor_is_one |= 1u << i;
4367 else
4368 v->instance_divisor_is_fetched |= 1u << i;
4369 }
4370
4371 if (!used[vbo_index]) {
4372 v->first_vb_use_mask |= 1 << i;
4373 used[vbo_index] = true;
4374 }
4375
4376 desc = util_format_description(elements[i].src_format);
4377 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4378 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4379 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4380 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4381 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4382
4383 v->format_size[i] = desc->block.bits / 8;
4384 v->src_offset[i] = elements[i].src_offset;
4385 v->vertex_buffer_index[i] = vbo_index;
4386
4387 /* The hardware always treats the 2-bit alpha channel as
4388 * unsigned, so a shader workaround is needed. The affected
4389 * chips are VI and older except Stoney (GFX8.1).
4390 */
4391 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4392 sscreen->info.chip_class <= VI &&
4393 sscreen->info.family != CHIP_STONEY) {
4394 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4395 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4396 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4397 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4398 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4399 /* This isn't actually used in OpenGL. */
4400 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4401 }
4402 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4403 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4404 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4405 else
4406 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4407 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4408 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4409 if (channel->normalized) {
4410 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4411 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4412 else
4413 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4414 } else {
4415 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4416 }
4417 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4418 if (channel->normalized) {
4419 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4420 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4421 else
4422 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4423 } else {
4424 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4425 }
4426 }
4427 } else if (channel && channel->size == 64 &&
4428 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4429 switch (desc->nr_channels) {
4430 case 1:
4431 case 2:
4432 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4433 swizzle[0] = PIPE_SWIZZLE_X;
4434 swizzle[1] = PIPE_SWIZZLE_Y;
4435 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4436 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4437 break;
4438 case 3:
4439 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4440 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4441 swizzle[1] = PIPE_SWIZZLE_Y;
4442 swizzle[2] = PIPE_SWIZZLE_0;
4443 swizzle[3] = PIPE_SWIZZLE_0;
4444 break;
4445 case 4:
4446 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4447 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4448 swizzle[1] = PIPE_SWIZZLE_Y;
4449 swizzle[2] = PIPE_SWIZZLE_Z;
4450 swizzle[3] = PIPE_SWIZZLE_W;
4451 break;
4452 default:
4453 assert(0);
4454 }
4455 } else if (channel && desc->nr_channels == 3) {
4456 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4457
4458 if (channel->size == 8) {
4459 if (channel->pure_integer)
4460 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4461 else
4462 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4463 } else if (channel->size == 16) {
4464 if (channel->pure_integer)
4465 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4466 else
4467 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4468 }
4469 }
4470
4471 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4472 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4473 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4474 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4475 S_008F0C_NUM_FORMAT(num_format) |
4476 S_008F0C_DATA_FORMAT(data_format);
4477 }
4478 return v;
4479 }
4480
4481 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4482 {
4483 struct si_context *sctx = (struct si_context *)ctx;
4484 struct si_vertex_elements *old = sctx->vertex_elements;
4485 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4486
4487 sctx->vertex_elements = v;
4488 sctx->vertex_buffers_dirty = true;
4489
4490 if (v &&
4491 (!old ||
4492 old->count != v->count ||
4493 old->uses_instance_divisors != v->uses_instance_divisors ||
4494 v->uses_instance_divisors || /* we don't check which divisors changed */
4495 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4496 sctx->do_update_shaders = true;
4497
4498 if (v && v->instance_divisor_is_fetched) {
4499 struct pipe_constant_buffer cb;
4500
4501 cb.buffer = NULL;
4502 cb.user_buffer = v->instance_divisors;
4503 cb.buffer_offset = 0;
4504 cb.buffer_size = sizeof(uint32_t) * v->count;
4505 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4506 }
4507 }
4508
4509 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4510 {
4511 struct si_context *sctx = (struct si_context *)ctx;
4512
4513 if (sctx->vertex_elements == state)
4514 sctx->vertex_elements = NULL;
4515 FREE(state);
4516 }
4517
4518 static void si_set_vertex_buffers(struct pipe_context *ctx,
4519 unsigned start_slot, unsigned count,
4520 const struct pipe_vertex_buffer *buffers)
4521 {
4522 struct si_context *sctx = (struct si_context *)ctx;
4523 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4524 int i;
4525
4526 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4527
4528 if (buffers) {
4529 for (i = 0; i < count; i++) {
4530 const struct pipe_vertex_buffer *src = buffers + i;
4531 struct pipe_vertex_buffer *dsti = dst + i;
4532 struct pipe_resource *buf = src->buffer.resource;
4533
4534 pipe_resource_reference(&dsti->buffer.resource, buf);
4535 dsti->buffer_offset = src->buffer_offset;
4536 dsti->stride = src->stride;
4537 si_context_add_resource_size(sctx, buf);
4538 if (buf)
4539 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4540 }
4541 } else {
4542 for (i = 0; i < count; i++) {
4543 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4544 }
4545 }
4546 sctx->vertex_buffers_dirty = true;
4547 }
4548
4549 /*
4550 * Misc
4551 */
4552
4553 static void si_set_tess_state(struct pipe_context *ctx,
4554 const float default_outer_level[4],
4555 const float default_inner_level[2])
4556 {
4557 struct si_context *sctx = (struct si_context *)ctx;
4558 struct pipe_constant_buffer cb;
4559 float array[8];
4560
4561 memcpy(array, default_outer_level, sizeof(float) * 4);
4562 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4563
4564 cb.buffer = NULL;
4565 cb.user_buffer = NULL;
4566 cb.buffer_size = sizeof(array);
4567
4568 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4569 (void*)array, sizeof(array),
4570 &cb.buffer_offset);
4571
4572 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4573 pipe_resource_reference(&cb.buffer, NULL);
4574 }
4575
4576 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4577 {
4578 struct si_context *sctx = (struct si_context *)ctx;
4579
4580 si_update_fb_dirtiness_after_rendering(sctx);
4581
4582 /* Multisample surfaces are flushed in si_decompress_textures. */
4583 if (sctx->framebuffer.uncompressed_cb_mask)
4584 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4585 sctx->framebuffer.CB_has_shader_readable_metadata);
4586 }
4587
4588 /* This only ensures coherency for shader image/buffer stores. */
4589 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4590 {
4591 struct si_context *sctx = (struct si_context *)ctx;
4592
4593 /* Subsequent commands must wait for all shader invocations to
4594 * complete. */
4595 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4596 SI_CONTEXT_CS_PARTIAL_FLUSH;
4597
4598 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4599 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4600 SI_CONTEXT_INV_VMEM_L1;
4601
4602 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4603 PIPE_BARRIER_SHADER_BUFFER |
4604 PIPE_BARRIER_TEXTURE |
4605 PIPE_BARRIER_IMAGE |
4606 PIPE_BARRIER_STREAMOUT_BUFFER |
4607 PIPE_BARRIER_GLOBAL_BUFFER)) {
4608 /* As far as I can tell, L1 contents are written back to L2
4609 * automatically at end of shader, but the contents of other
4610 * L1 caches might still be stale. */
4611 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4612 }
4613
4614 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4615 /* Indices are read through TC L2 since VI.
4616 * L1 isn't used.
4617 */
4618 if (sctx->screen->info.chip_class <= CIK)
4619 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4620 }
4621
4622 /* MSAA color, any depth and any stencil are flushed in
4623 * si_decompress_textures when needed.
4624 */
4625 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4626 sctx->framebuffer.uncompressed_cb_mask) {
4627 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4628
4629 if (sctx->chip_class <= VI)
4630 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4631 }
4632
4633 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4634 if (sctx->screen->info.chip_class <= VI &&
4635 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4636 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4637 }
4638
4639 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4640 {
4641 struct pipe_blend_state blend;
4642
4643 memset(&blend, 0, sizeof(blend));
4644 blend.independent_blend_enable = true;
4645 blend.rt[0].colormask = 0xf;
4646 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4647 }
4648
4649 static void si_init_config(struct si_context *sctx);
4650
4651 void si_init_state_functions(struct si_context *sctx)
4652 {
4653 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4654 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4655 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4656 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4657 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4658 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4659 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4660 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4661 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4662 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4663 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4664
4665 sctx->b.create_blend_state = si_create_blend_state;
4666 sctx->b.bind_blend_state = si_bind_blend_state;
4667 sctx->b.delete_blend_state = si_delete_blend_state;
4668 sctx->b.set_blend_color = si_set_blend_color;
4669
4670 sctx->b.create_rasterizer_state = si_create_rs_state;
4671 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4672 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4673
4674 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4675 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4676 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4677
4678 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4679 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4680 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4681 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4682 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4683
4684 sctx->b.set_clip_state = si_set_clip_state;
4685 sctx->b.set_stencil_ref = si_set_stencil_ref;
4686
4687 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4688
4689 sctx->b.create_sampler_state = si_create_sampler_state;
4690 sctx->b.delete_sampler_state = si_delete_sampler_state;
4691
4692 sctx->b.create_sampler_view = si_create_sampler_view;
4693 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4694
4695 sctx->b.set_sample_mask = si_set_sample_mask;
4696
4697 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4698 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4699 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4700 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4701
4702 sctx->b.texture_barrier = si_texture_barrier;
4703 sctx->b.memory_barrier = si_memory_barrier;
4704 sctx->b.set_min_samples = si_set_min_samples;
4705 sctx->b.set_tess_state = si_set_tess_state;
4706
4707 sctx->b.set_active_query_state = si_set_active_query_state;
4708
4709 sctx->b.draw_vbo = si_draw_vbo;
4710
4711 si_init_config(sctx);
4712 }
4713
4714 void si_init_screen_state_functions(struct si_screen *sscreen)
4715 {
4716 sscreen->b.is_format_supported = si_is_format_supported;
4717 }
4718
4719 static void si_set_grbm_gfx_index(struct si_context *sctx,
4720 struct si_pm4_state *pm4, unsigned value)
4721 {
4722 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4723 R_00802C_GRBM_GFX_INDEX;
4724 si_pm4_set_reg(pm4, reg, value);
4725 }
4726
4727 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4728 struct si_pm4_state *pm4, unsigned se)
4729 {
4730 assert(se == ~0 || se < sctx->screen->info.max_se);
4731 si_set_grbm_gfx_index(sctx, pm4,
4732 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4733 S_030800_SE_INDEX(se)) |
4734 S_030800_SH_BROADCAST_WRITES(1) |
4735 S_030800_INSTANCE_BROADCAST_WRITES(1));
4736 }
4737
4738 static void
4739 si_write_harvested_raster_configs(struct si_context *sctx,
4740 struct si_pm4_state *pm4,
4741 unsigned raster_config,
4742 unsigned raster_config_1)
4743 {
4744 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4745 unsigned raster_config_se[4];
4746 unsigned se;
4747
4748 ac_get_harvested_configs(&sctx->screen->info,
4749 raster_config,
4750 &raster_config_1,
4751 raster_config_se);
4752
4753 for (se = 0; se < num_se; se++) {
4754 si_set_grbm_gfx_index_se(sctx, pm4, se);
4755 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4756 }
4757 si_set_grbm_gfx_index(sctx, pm4, ~0);
4758
4759 if (sctx->chip_class >= CIK) {
4760 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4761 }
4762 }
4763
4764 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4765 {
4766 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4767 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4768 unsigned raster_config, raster_config_1;
4769
4770 ac_get_raster_config(&sctx->screen->info,
4771 &raster_config,
4772 &raster_config_1);
4773
4774 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4775 /* Always use the default config when all backends are enabled
4776 * (or when we failed to determine the enabled backends).
4777 */
4778 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4779 raster_config);
4780 if (sctx->chip_class >= CIK)
4781 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4782 raster_config_1);
4783 } else {
4784 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4785 }
4786 }
4787
4788 static void si_init_config(struct si_context *sctx)
4789 {
4790 struct si_screen *sscreen = sctx->screen;
4791 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4792 bool has_clear_state = sscreen->has_clear_state;
4793 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4794
4795 /* Only SI can disable CLEAR_STATE for now. */
4796 assert(has_clear_state || sscreen->info.chip_class == SI);
4797
4798 if (!pm4)
4799 return;
4800
4801 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4802 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4803 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4804 si_pm4_cmd_end(pm4, false);
4805
4806 if (has_clear_state) {
4807 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4808 si_pm4_cmd_add(pm4, 0);
4809 si_pm4_cmd_end(pm4, false);
4810 }
4811
4812 if (sctx->chip_class <= VI)
4813 si_set_raster_config(sctx, pm4);
4814
4815 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4816 if (!has_clear_state)
4817 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4818
4819 /* FIXME calculate these values somehow ??? */
4820 if (sctx->chip_class <= VI) {
4821 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4822 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4823 }
4824
4825 if (!has_clear_state) {
4826 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4827 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4828 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4829 }
4830
4831 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4832 if (!has_clear_state)
4833 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4834 if (sctx->chip_class < CIK)
4835 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4836 S_008A14_CLIP_VTX_REORDER_ENA(1));
4837
4838 if (!has_clear_state)
4839 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4840
4841 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4842 * I don't know why. Deduced by trial and error.
4843 */
4844 if (sctx->chip_class <= CIK) {
4845 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4846 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4847 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4848 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4849 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4850 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4851 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4852 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4853 }
4854
4855 if (!has_clear_state) {
4856 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4857 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4858 S_028230_ER_TRI(0xA) |
4859 S_028230_ER_POINT(0xA) |
4860 S_028230_ER_RECT(0xA) |
4861 /* Required by DX10_DIAMOND_TEST_ENA: */
4862 S_028230_ER_LINE_LR(0x1A) |
4863 S_028230_ER_LINE_RL(0x26) |
4864 S_028230_ER_LINE_TB(0xA) |
4865 S_028230_ER_LINE_BT(0xA));
4866 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4867 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4868 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4869 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4870 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4871 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4872 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4873 }
4874
4875 if (sctx->chip_class >= GFX9) {
4876 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4877 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4878 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4879 } else {
4880 /* These registers, when written, also overwrite the CLEAR_STATE
4881 * context, so we can't rely on CLEAR_STATE setting them.
4882 * It would be an issue if there was another UMD changing them.
4883 */
4884 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4885 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4886 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4887 }
4888
4889 if (sctx->chip_class >= CIK) {
4890 if (sctx->chip_class >= GFX9) {
4891 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4892 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4893 } else {
4894 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4895 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4896 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4897 S_00B41C_WAVE_LIMIT(0x3F));
4898 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4899 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4900
4901 /* If this is 0, Bonaire can hang even if GS isn't being used.
4902 * Other chips are unaffected. These are suboptimal values,
4903 * but we don't use on-chip GS.
4904 */
4905 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4906 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4907 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4908 }
4909 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4910 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4911
4912 /* Compute LATE_ALLOC_VS.LIMIT. */
4913 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4914 (sscreen->info.max_se *
4915 sscreen->info.max_sh_per_se);
4916 unsigned late_alloc_limit; /* The limit is per SH. */
4917
4918 if (sctx->family == CHIP_KABINI) {
4919 late_alloc_limit = 0; /* Potential hang on Kabini. */
4920 } else if (num_cu_per_sh <= 4) {
4921 /* Too few available compute units per SH. Disallowing
4922 * VS to run on one CU could hurt us more than late VS
4923 * allocation would help.
4924 *
4925 * 2 is the highest safe number that allows us to keep
4926 * all CUs enabled.
4927 */
4928 late_alloc_limit = 2;
4929 } else {
4930 /* This is a good initial value, allowing 1 late_alloc
4931 * wave per SIMD on num_cu - 2.
4932 */
4933 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4934
4935 /* The limit is 0-based, so 0 means 1. */
4936 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4937 late_alloc_limit -= 1;
4938 }
4939
4940 /* VS can't execute on one CU if the limit is > 2. */
4941 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4942 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4943 S_00B118_WAVE_LIMIT(0x3F));
4944 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4945 S_00B11C_LIMIT(late_alloc_limit));
4946 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4947 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4948 }
4949
4950 if (sctx->chip_class >= VI) {
4951 unsigned vgt_tess_distribution;
4952
4953 vgt_tess_distribution =
4954 S_028B50_ACCUM_ISOLINE(32) |
4955 S_028B50_ACCUM_TRI(11) |
4956 S_028B50_ACCUM_QUAD(11) |
4957 S_028B50_DONUT_SPLIT(16);
4958
4959 /* Testing with Unigine Heaven extreme tesselation yielded best results
4960 * with TRAP_SPLIT = 3.
4961 */
4962 if (sctx->family == CHIP_FIJI ||
4963 sctx->family >= CHIP_POLARIS10)
4964 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4965
4966 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4967 } else if (!has_clear_state) {
4968 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4969 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4970 }
4971
4972 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4973 if (sctx->chip_class >= CIK) {
4974 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4975 S_028084_ADDRESS(border_color_va >> 40));
4976 }
4977 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4978 RADEON_PRIO_BORDER_COLORS);
4979
4980 if (sctx->chip_class >= GFX9) {
4981 unsigned num_se = sscreen->info.max_se;
4982 unsigned pc_lines = 0;
4983
4984 switch (sctx->family) {
4985 case CHIP_VEGA10:
4986 case CHIP_VEGA12:
4987 pc_lines = 4096;
4988 break;
4989 case CHIP_RAVEN:
4990 pc_lines = 1024;
4991 break;
4992 default:
4993 assert(0);
4994 }
4995
4996 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4997 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4998 S_028C48_MAX_PRIM_PER_BATCH(1023));
4999 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5000 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5001 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5002 }
5003
5004 si_pm4_upload_indirect_buffer(sctx, pm4);
5005 sctx->init_config = pm4;
5006 }