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radeonsi: ignore PIPE_BIND_LINEAR in si_is_format_supported v2
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.info.r600_num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.num_render_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case UTIL_FORMAT_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case UTIL_FORMAT_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case UTIL_FORMAT_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case UTIL_FORMAT_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case UTIL_FORMAT_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
243 * is that:
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
248 *
249 * Another reason is to avoid a hang with dual source blending.
250 */
251 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
252 {
253 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
254 struct si_state_blend *blend = sctx->queued.named.blend;
255 uint32_t cb_target_mask = 0, i;
256
257 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
258 if (sctx->framebuffer.state.cbufs[i])
259 cb_target_mask |= 0xf << (4*i);
260
261 if (blend)
262 cb_target_mask &= blend->cb_target_mask;
263
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
267 *
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
269 */
270 if (blend && blend->dual_src_blend &&
271 sctx->ps_shader.cso &&
272 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
273 cb_target_mask = 0;
274
275 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
276
277 /* STONEY-specific register settings. */
278 if (sctx->b.family == CHIP_STONEY) {
279 unsigned spi_shader_col_format =
280 sctx->ps_shader.cso ?
281 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
282 unsigned sx_ps_downconvert = 0;
283 unsigned sx_blend_opt_epsilon = 0;
284 unsigned sx_blend_opt_control = 0;
285
286 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
287 struct r600_surface *surf =
288 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
289 unsigned format, swap, spi_format, colormask;
290 bool has_alpha, has_rgb;
291
292 if (!surf)
293 continue;
294
295 format = G_028C70_FORMAT(surf->cb_color_info);
296 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
297 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
298 colormask = (cb_target_mask >> (i * 4)) & 0xf;
299
300 /* Set if RGB and A are present. */
301 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
302
303 if (format == V_028C70_COLOR_8 ||
304 format == V_028C70_COLOR_16 ||
305 format == V_028C70_COLOR_32)
306 has_rgb = !has_alpha;
307 else
308 has_rgb = true;
309
310 /* Check the colormask and export format. */
311 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
312 has_rgb = false;
313 if (!(colormask & PIPE_MASK_A))
314 has_alpha = false;
315
316 if (spi_format == V_028714_SPI_SHADER_ZERO) {
317 has_rgb = false;
318 has_alpha = false;
319 }
320
321 /* Disable value checking for disabled channels. */
322 if (!has_rgb)
323 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
324 if (!has_alpha)
325 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
326
327 /* Enable down-conversion for 32bpp and smaller formats. */
328 switch (format) {
329 case V_028C70_COLOR_8:
330 case V_028C70_COLOR_8_8:
331 case V_028C70_COLOR_8_8_8_8:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
335 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
336 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
337 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
338 }
339 break;
340
341 case V_028C70_COLOR_5_6_5:
342 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
343 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
344 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
345 }
346 break;
347
348 case V_028C70_COLOR_1_5_5_5:
349 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
350 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
351 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
352 }
353 break;
354
355 case V_028C70_COLOR_4_4_4_4:
356 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
357 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
358 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
359 }
360 break;
361
362 case V_028C70_COLOR_32:
363 if (swap == V_0280A0_SWAP_STD &&
364 spi_format == V_028714_SPI_SHADER_32_R)
365 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
366 else if (swap == V_0280A0_SWAP_ALT_REV &&
367 spi_format == V_028714_SPI_SHADER_32_AR)
368 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
369 break;
370
371 case V_028C70_COLOR_16:
372 case V_028C70_COLOR_16_16:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
377 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
378 if (swap == V_0280A0_SWAP_STD ||
379 swap == V_0280A0_SWAP_STD_REV)
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
381 else
382 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
383 }
384 break;
385
386 case V_028C70_COLOR_10_11_11:
387 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
388 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
389 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
390 }
391 break;
392
393 case V_028C70_COLOR_2_10_10_10:
394 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
395 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
396 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
397 }
398 break;
399 }
400 }
401
402 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
403 sx_ps_downconvert = 0;
404 sx_blend_opt_epsilon = 0;
405 sx_blend_opt_control = 0;
406 }
407
408 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
409 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
412 }
413 }
414
415 /*
416 * Blender functions
417 */
418
419 static uint32_t si_translate_blend_function(int blend_func)
420 {
421 switch (blend_func) {
422 case PIPE_BLEND_ADD:
423 return V_028780_COMB_DST_PLUS_SRC;
424 case PIPE_BLEND_SUBTRACT:
425 return V_028780_COMB_SRC_MINUS_DST;
426 case PIPE_BLEND_REVERSE_SUBTRACT:
427 return V_028780_COMB_DST_MINUS_SRC;
428 case PIPE_BLEND_MIN:
429 return V_028780_COMB_MIN_DST_SRC;
430 case PIPE_BLEND_MAX:
431 return V_028780_COMB_MAX_DST_SRC;
432 default:
433 R600_ERR("Unknown blend function %d\n", blend_func);
434 assert(0);
435 break;
436 }
437 return 0;
438 }
439
440 static uint32_t si_translate_blend_factor(int blend_fact)
441 {
442 switch (blend_fact) {
443 case PIPE_BLENDFACTOR_ONE:
444 return V_028780_BLEND_ONE;
445 case PIPE_BLENDFACTOR_SRC_COLOR:
446 return V_028780_BLEND_SRC_COLOR;
447 case PIPE_BLENDFACTOR_SRC_ALPHA:
448 return V_028780_BLEND_SRC_ALPHA;
449 case PIPE_BLENDFACTOR_DST_ALPHA:
450 return V_028780_BLEND_DST_ALPHA;
451 case PIPE_BLENDFACTOR_DST_COLOR:
452 return V_028780_BLEND_DST_COLOR;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE;
455 case PIPE_BLENDFACTOR_CONST_COLOR:
456 return V_028780_BLEND_CONSTANT_COLOR;
457 case PIPE_BLENDFACTOR_CONST_ALPHA:
458 return V_028780_BLEND_CONSTANT_ALPHA;
459 case PIPE_BLENDFACTOR_ZERO:
460 return V_028780_BLEND_ZERO;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
473 case PIPE_BLENDFACTOR_SRC1_COLOR:
474 return V_028780_BLEND_SRC1_COLOR;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA:
476 return V_028780_BLEND_SRC1_ALPHA;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
478 return V_028780_BLEND_INV_SRC1_COLOR;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
480 return V_028780_BLEND_INV_SRC1_ALPHA;
481 default:
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
483 assert(0);
484 break;
485 }
486 return 0;
487 }
488
489 static uint32_t si_translate_blend_opt_function(int blend_func)
490 {
491 switch (blend_func) {
492 case PIPE_BLEND_ADD:
493 return V_028760_OPT_COMB_ADD;
494 case PIPE_BLEND_SUBTRACT:
495 return V_028760_OPT_COMB_SUBTRACT;
496 case PIPE_BLEND_REVERSE_SUBTRACT:
497 return V_028760_OPT_COMB_REVSUBTRACT;
498 case PIPE_BLEND_MIN:
499 return V_028760_OPT_COMB_MIN;
500 case PIPE_BLEND_MAX:
501 return V_028760_OPT_COMB_MAX;
502 default:
503 return V_028760_OPT_COMB_BLEND_DISABLED;
504 }
505 }
506
507 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
508 {
509 switch (blend_fact) {
510 case PIPE_BLENDFACTOR_ZERO:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
512 case PIPE_BLENDFACTOR_ONE:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
514 case PIPE_BLENDFACTOR_SRC_COLOR:
515 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
518 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
520 case PIPE_BLENDFACTOR_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
525 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
527 default:
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
529 }
530 }
531
532 /**
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 */
536 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
537 unsigned *dst_factor, unsigned expected_dst,
538 unsigned replacement_src)
539 {
540 if (*src_factor == expected_dst &&
541 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
542 *src_factor = PIPE_BLENDFACTOR_ZERO;
543 *dst_factor = replacement_src;
544
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func == PIPE_BLEND_SUBTRACT)
547 *func = PIPE_BLEND_REVERSE_SUBTRACT;
548 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
549 *func = PIPE_BLEND_SUBTRACT;
550 }
551 }
552
553 static bool si_blend_factor_uses_dst(unsigned factor)
554 {
555 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
556 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
559 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
560 }
561
562 static void *si_create_blend_state_mode(struct pipe_context *ctx,
563 const struct pipe_blend_state *state,
564 unsigned mode)
565 {
566 struct si_context *sctx = (struct si_context*)ctx;
567 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
568 struct si_pm4_state *pm4 = &blend->pm4;
569 uint32_t sx_mrt_blend_opt[8] = {0};
570 uint32_t color_control = 0;
571
572 if (!blend)
573 return NULL;
574
575 blend->alpha_to_coverage = state->alpha_to_coverage;
576 blend->alpha_to_one = state->alpha_to_one;
577 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
578
579 if (state->logicop_enable) {
580 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
581 } else {
582 color_control |= S_028808_ROP3(0xcc);
583 }
584
585 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
591
592 if (state->alpha_to_coverage)
593 blend->need_src_alpha_4bit |= 0xf;
594
595 blend->cb_target_mask = 0;
596 for (int i = 0; i < 8; i++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j = state->independent_blend_enable ? i : 0;
599
600 unsigned eqRGB = state->rt[j].rgb_func;
601 unsigned srcRGB = state->rt[j].rgb_src_factor;
602 unsigned dstRGB = state->rt[j].rgb_dst_factor;
603 unsigned eqA = state->rt[j].alpha_func;
604 unsigned srcA = state->rt[j].alpha_src_factor;
605 unsigned dstA = state->rt[j].alpha_dst_factor;
606
607 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
608 unsigned blend_cntl = 0;
609
610 sx_mrt_blend_opt[i] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
613
614 if (!state->rt[j].colormask)
615 continue;
616
617 /* cb_render_state will disable unused ones */
618 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
619
620 if (!state->rt[j].blend_enable) {
621 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 continue;
623 }
624
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
627 *
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
630 */
631 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
632 PIPE_BLENDFACTOR_DST_COLOR,
633 PIPE_BLENDFACTOR_SRC_COLOR);
634 si_blend_remove_dst(&eqA, &srcA, &dstA,
635 PIPE_BLENDFACTOR_DST_COLOR,
636 PIPE_BLENDFACTOR_SRC_COLOR);
637 si_blend_remove_dst(&eqA, &srcA, &dstA,
638 PIPE_BLENDFACTOR_DST_ALPHA,
639 PIPE_BLENDFACTOR_SRC_ALPHA);
640
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
643 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
644 srcA_opt = si_translate_blend_opt_factor(srcA, true);
645 dstA_opt = si_translate_blend_opt_factor(dstA, true);
646
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650 if (si_blend_factor_uses_dst(srcA))
651 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
652
653 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
654 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
656 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
657 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
658
659 /* Set the final value. */
660 sx_mrt_blend_opt[i] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt) |
665 S_028760_ALPHA_DST_OPT(dstA_opt) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
667
668 /* Set blend state. */
669 blend_cntl |= S_028780_ENABLE(1);
670 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
671 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
672 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
673
674 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
675 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
677 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
678 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
679 }
680 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
681
682 blend->blend_enable_4bit |= 0xf << (i * 4);
683
684 /* This is only important for formats without alpha. */
685 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
687 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
689 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
690 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
691 blend->need_src_alpha_4bit |= 0xf << (i * 4);
692 }
693
694 if (blend->cb_target_mask) {
695 color_control |= S_028808_MODE(mode);
696 } else {
697 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
698 }
699
700 if (sctx->b.family == CHIP_STONEY) {
701 for (int i = 0; i < 8; i++)
702 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
703 sx_mrt_blend_opt[i]);
704
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend->dual_src_blend || state->logicop_enable ||
707 mode == V_028808_CB_RESOLVE)
708 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
709 }
710
711 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
712 return blend;
713 }
714
715 static void *si_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
719 }
720
721 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
725 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
726 }
727
728 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
729 {
730 struct si_context *sctx = (struct si_context *)ctx;
731 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
732 }
733
734 static void si_set_blend_color(struct pipe_context *ctx,
735 const struct pipe_blend_color *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738
739 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->blend_color.state = *state;
743 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
744 }
745
746 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
747 {
748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
749
750 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
751 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
752 }
753
754 /*
755 * Clipping, scissors and viewport
756 */
757
758 static void si_set_clip_state(struct pipe_context *ctx,
759 const struct pipe_clip_state *state)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_constant_buffer cb;
763
764 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
765 return;
766
767 sctx->clip_state.state = *state;
768 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
769
770 cb.buffer = NULL;
771 cb.user_buffer = state->ucp;
772 cb.buffer_offset = 0;
773 cb.buffer_size = 4*4*8;
774 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
775 pipe_resource_reference(&cb.buffer, NULL);
776 }
777
778 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
779 {
780 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
781
782 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
783 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
784 }
785
786 #define SIX_BITS 0x3F
787
788 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
789 {
790 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
791 struct tgsi_shader_info *info = si_get_vs_info(sctx);
792 unsigned window_space =
793 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
794 unsigned clipdist_mask =
795 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
796
797 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
798 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
799 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
800 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
801 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
802 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
803 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
804 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
805 info->writes_edgeflag ||
806 info->writes_layer ||
807 info->writes_viewport_index) |
808 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
809 (sctx->queued.named.rasterizer->clip_plane_enable &
810 clipdist_mask));
811 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
812 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
813 (clipdist_mask ? 0 :
814 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
815 S_028810_CLIP_DISABLE(window_space));
816
817 /* reuse needs to be set off if we write oViewport */
818 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
819 S_028AB4_REUSE_OFF(info->writes_viewport_index));
820 }
821
822 static void si_set_scissor_states(struct pipe_context *ctx,
823 unsigned start_slot,
824 unsigned num_scissors,
825 const struct pipe_scissor_state *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828 int i;
829
830 for (i = 0; i < num_scissors; i++)
831 sctx->scissors.states[start_slot + i] = state[i];
832
833 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
834 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
835 }
836
837 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
838 {
839 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
840 struct pipe_scissor_state *states = sctx->scissors.states;
841 unsigned mask = sctx->scissors.dirty_mask;
842
843 /* The simple case: Only 1 viewport is active. */
844 if (mask & 1 &&
845 !si_get_vs_info(sctx)->writes_viewport_index) {
846 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
847 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
848 S_028250_TL_Y(states[0].miny) |
849 S_028250_WINDOW_OFFSET_DISABLE(1));
850 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
851 S_028254_BR_Y(states[0].maxy));
852 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
853 return;
854 }
855
856 while (mask) {
857 int start, count, i;
858
859 u_bit_scan_consecutive_range(&mask, &start, &count);
860
861 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
862 start * 4 * 2, count * 2);
863 for (i = start; i < start+count; i++) {
864 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
865 S_028250_TL_Y(states[i].miny) |
866 S_028250_WINDOW_OFFSET_DISABLE(1));
867 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
868 S_028254_BR_Y(states[i].maxy));
869 }
870 }
871 sctx->scissors.dirty_mask = 0;
872 }
873
874 static void si_set_viewport_states(struct pipe_context *ctx,
875 unsigned start_slot,
876 unsigned num_viewports,
877 const struct pipe_viewport_state *state)
878 {
879 struct si_context *sctx = (struct si_context *)ctx;
880 int i;
881
882 for (i = 0; i < num_viewports; i++)
883 sctx->viewports.states[start_slot + i] = state[i];
884
885 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
886 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
887 }
888
889 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
890 {
891 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
892 struct pipe_viewport_state *states = sctx->viewports.states;
893 unsigned mask = sctx->viewports.dirty_mask;
894
895 /* The simple case: Only 1 viewport is active. */
896 if (mask & 1 &&
897 !si_get_vs_info(sctx)->writes_viewport_index) {
898 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
899 radeon_emit(cs, fui(states[0].scale[0]));
900 radeon_emit(cs, fui(states[0].translate[0]));
901 radeon_emit(cs, fui(states[0].scale[1]));
902 radeon_emit(cs, fui(states[0].translate[1]));
903 radeon_emit(cs, fui(states[0].scale[2]));
904 radeon_emit(cs, fui(states[0].translate[2]));
905 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
906 return;
907 }
908
909 while (mask) {
910 int start, count, i;
911
912 u_bit_scan_consecutive_range(&mask, &start, &count);
913
914 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
915 start * 4 * 6, count * 6);
916 for (i = start; i < start+count; i++) {
917 radeon_emit(cs, fui(states[i].scale[0]));
918 radeon_emit(cs, fui(states[i].translate[0]));
919 radeon_emit(cs, fui(states[i].scale[1]));
920 radeon_emit(cs, fui(states[i].translate[1]));
921 radeon_emit(cs, fui(states[i].scale[2]));
922 radeon_emit(cs, fui(states[i].translate[2]));
923 }
924 }
925 sctx->viewports.dirty_mask = 0;
926 }
927
928 /*
929 * inferred state between framebuffer and rasterizer
930 */
931 static void si_update_poly_offset_state(struct si_context *sctx)
932 {
933 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
934
935 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
936 return;
937
938 switch (sctx->framebuffer.state.zsbuf->texture->format) {
939 case PIPE_FORMAT_Z16_UNORM:
940 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
941 break;
942 default: /* 24-bit */
943 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
944 break;
945 case PIPE_FORMAT_Z32_FLOAT:
946 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
947 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
948 break;
949 }
950 }
951
952 /*
953 * Rasterizer
954 */
955
956 static uint32_t si_translate_fill(uint32_t func)
957 {
958 switch(func) {
959 case PIPE_POLYGON_MODE_FILL:
960 return V_028814_X_DRAW_TRIANGLES;
961 case PIPE_POLYGON_MODE_LINE:
962 return V_028814_X_DRAW_LINES;
963 case PIPE_POLYGON_MODE_POINT:
964 return V_028814_X_DRAW_POINTS;
965 default:
966 assert(0);
967 return V_028814_X_DRAW_POINTS;
968 }
969 }
970
971 static void *si_create_rs_state(struct pipe_context *ctx,
972 const struct pipe_rasterizer_state *state)
973 {
974 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
975 struct si_pm4_state *pm4 = &rs->pm4;
976 unsigned tmp, i;
977 float psize_min, psize_max;
978
979 if (!rs) {
980 return NULL;
981 }
982
983 rs->two_side = state->light_twoside;
984 rs->multisample_enable = state->multisample;
985 rs->force_persample_interp = state->force_persample_interp;
986 rs->clip_plane_enable = state->clip_plane_enable;
987 rs->line_stipple_enable = state->line_stipple_enable;
988 rs->poly_stipple_enable = state->poly_stipple_enable;
989 rs->line_smooth = state->line_smooth;
990 rs->poly_smooth = state->poly_smooth;
991 rs->uses_poly_offset = state->offset_point || state->offset_line ||
992 state->offset_tri;
993 rs->clamp_fragment_color = state->clamp_fragment_color;
994 rs->flatshade = state->flatshade;
995 rs->sprite_coord_enable = state->sprite_coord_enable;
996 rs->rasterizer_discard = state->rasterizer_discard;
997 rs->pa_sc_line_stipple = state->line_stipple_enable ?
998 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
999 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1000 rs->pa_cl_clip_cntl =
1001 S_028810_PS_UCP_MODE(3) |
1002 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1003 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1004 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1005 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1006 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1007
1008 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
1009 S_0286D4_FLAT_SHADE_ENA(1) |
1010 S_0286D4_PNT_SPRITE_ENA(1) |
1011 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1012 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1013 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1014 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1015 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1016
1017 /* point size 12.4 fixed point */
1018 tmp = (unsigned)(state->point_size * 8.0);
1019 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1020
1021 if (state->point_size_per_vertex) {
1022 psize_min = util_get_min_point_size(state);
1023 psize_max = 8192;
1024 } else {
1025 /* Force the point size to be as if the vertex output was disabled. */
1026 psize_min = state->point_size;
1027 psize_max = state->point_size;
1028 }
1029 /* Divide by two, because 0.5 = 1 pixel. */
1030 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1031 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
1032 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
1033
1034 tmp = (unsigned)state->line_width * 8;
1035 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
1036 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
1037 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1038 S_028A48_MSAA_ENABLE(state->multisample ||
1039 state->poly_smooth ||
1040 state->line_smooth) |
1041 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
1042
1043 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
1044 S_028BE4_PIX_CENTER(state->half_pixel_center) |
1045 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
1046
1047 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1048 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1049 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1050 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1051 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1052 S_028814_FACE(!state->front_ccw) |
1053 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1054 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1055 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1056 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
1057 state->fill_back != PIPE_POLYGON_MODE_FILL) |
1058 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1059 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
1060 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
1061 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
1062
1063 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1064 for (i = 0; i < 3; i++) {
1065 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1066 float offset_units = state->offset_units;
1067 float offset_scale = state->offset_scale * 16.0f;
1068
1069 switch (i) {
1070 case 0: /* 16-bit zbuffer */
1071 offset_units *= 4.0f;
1072 break;
1073 case 1: /* 24-bit zbuffer */
1074 offset_units *= 2.0f;
1075 break;
1076 case 2: /* 32-bit zbuffer */
1077 offset_units *= 1.0f;
1078 break;
1079 }
1080
1081 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1082 fui(offset_scale));
1083 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1084 fui(offset_units));
1085 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1086 fui(offset_scale));
1087 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1088 fui(offset_units));
1089 }
1090
1091 return rs;
1092 }
1093
1094 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1095 {
1096 struct si_context *sctx = (struct si_context *)ctx;
1097 struct si_state_rasterizer *old_rs =
1098 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1099 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1100
1101 if (!state)
1102 return;
1103
1104 if (sctx->framebuffer.nr_samples > 1 &&
1105 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1106 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1107
1108 si_pm4_bind_state(sctx, rasterizer, rs);
1109 si_update_poly_offset_state(sctx);
1110
1111 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1112 }
1113
1114 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1115 {
1116 struct si_context *sctx = (struct si_context *)ctx;
1117
1118 if (sctx->queued.named.rasterizer == state)
1119 si_pm4_bind_state(sctx, poly_offset, NULL);
1120 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1121 }
1122
1123 /*
1124 * infeered state between dsa and stencil ref
1125 */
1126 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1127 {
1128 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1129 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1130 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1131
1132 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1133 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1134 S_028430_STENCILMASK(dsa->valuemask[0]) |
1135 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1136 S_028430_STENCILOPVAL(1));
1137 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1138 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1139 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1140 S_028434_STENCILOPVAL_BF(1));
1141 }
1142
1143 static void si_set_stencil_ref(struct pipe_context *ctx,
1144 const struct pipe_stencil_ref *state)
1145 {
1146 struct si_context *sctx = (struct si_context *)ctx;
1147
1148 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1149 return;
1150
1151 sctx->stencil_ref.state = *state;
1152 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1153 }
1154
1155
1156 /*
1157 * DSA
1158 */
1159
1160 static uint32_t si_translate_stencil_op(int s_op)
1161 {
1162 switch (s_op) {
1163 case PIPE_STENCIL_OP_KEEP:
1164 return V_02842C_STENCIL_KEEP;
1165 case PIPE_STENCIL_OP_ZERO:
1166 return V_02842C_STENCIL_ZERO;
1167 case PIPE_STENCIL_OP_REPLACE:
1168 return V_02842C_STENCIL_REPLACE_TEST;
1169 case PIPE_STENCIL_OP_INCR:
1170 return V_02842C_STENCIL_ADD_CLAMP;
1171 case PIPE_STENCIL_OP_DECR:
1172 return V_02842C_STENCIL_SUB_CLAMP;
1173 case PIPE_STENCIL_OP_INCR_WRAP:
1174 return V_02842C_STENCIL_ADD_WRAP;
1175 case PIPE_STENCIL_OP_DECR_WRAP:
1176 return V_02842C_STENCIL_SUB_WRAP;
1177 case PIPE_STENCIL_OP_INVERT:
1178 return V_02842C_STENCIL_INVERT;
1179 default:
1180 R600_ERR("Unknown stencil op %d", s_op);
1181 assert(0);
1182 break;
1183 }
1184 return 0;
1185 }
1186
1187 static void *si_create_dsa_state(struct pipe_context *ctx,
1188 const struct pipe_depth_stencil_alpha_state *state)
1189 {
1190 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1191 struct si_pm4_state *pm4 = &dsa->pm4;
1192 unsigned db_depth_control;
1193 uint32_t db_stencil_control = 0;
1194
1195 if (!dsa) {
1196 return NULL;
1197 }
1198
1199 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1200 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1201 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1202 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1203
1204 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1205 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1206 S_028800_ZFUNC(state->depth.func) |
1207 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1208
1209 /* stencil */
1210 if (state->stencil[0].enabled) {
1211 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1212 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1213 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1214 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1215 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1216
1217 if (state->stencil[1].enabled) {
1218 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1219 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1220 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1221 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1222 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1223 }
1224 }
1225
1226 /* alpha */
1227 if (state->alpha.enabled) {
1228 dsa->alpha_func = state->alpha.func;
1229
1230 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1231 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1232 } else {
1233 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1234 }
1235
1236 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1237 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1238 if (state->depth.bounds_test) {
1239 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1240 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1241 }
1242
1243 return dsa;
1244 }
1245
1246 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1247 {
1248 struct si_context *sctx = (struct si_context *)ctx;
1249 struct si_state_dsa *dsa = state;
1250
1251 if (!state)
1252 return;
1253
1254 si_pm4_bind_state(sctx, dsa, dsa);
1255
1256 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1257 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1258 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1259 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1260 }
1261 }
1262
1263 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1264 {
1265 struct si_context *sctx = (struct si_context *)ctx;
1266 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1267 }
1268
1269 static void *si_create_db_flush_dsa(struct si_context *sctx)
1270 {
1271 struct pipe_depth_stencil_alpha_state dsa = {};
1272
1273 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1274 }
1275
1276 /* DB RENDER STATE */
1277
1278 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1279 {
1280 struct si_context *sctx = (struct si_context*)ctx;
1281
1282 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1283 }
1284
1285 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1286 {
1287 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1288 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1289 unsigned db_shader_control;
1290
1291 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1292
1293 /* DB_RENDER_CONTROL */
1294 if (sctx->dbcb_depth_copy_enabled ||
1295 sctx->dbcb_stencil_copy_enabled) {
1296 radeon_emit(cs,
1297 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1298 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1299 S_028000_COPY_CENTROID(1) |
1300 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1301 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1302 radeon_emit(cs,
1303 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1304 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1305 } else {
1306 radeon_emit(cs,
1307 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1308 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1309 }
1310
1311 /* DB_COUNT_CONTROL (occlusion queries) */
1312 if (sctx->b.num_occlusion_queries > 0) {
1313 if (sctx->b.chip_class >= CIK) {
1314 radeon_emit(cs,
1315 S_028004_PERFECT_ZPASS_COUNTS(1) |
1316 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1317 S_028004_ZPASS_ENABLE(1) |
1318 S_028004_SLICE_EVEN_ENABLE(1) |
1319 S_028004_SLICE_ODD_ENABLE(1));
1320 } else {
1321 radeon_emit(cs,
1322 S_028004_PERFECT_ZPASS_COUNTS(1) |
1323 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1324 }
1325 } else {
1326 /* Disable occlusion queries. */
1327 if (sctx->b.chip_class >= CIK) {
1328 radeon_emit(cs, 0);
1329 } else {
1330 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1331 }
1332 }
1333
1334 /* DB_RENDER_OVERRIDE2 */
1335 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1336 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1337 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1338
1339 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1340 sctx->ps_db_shader_control;
1341
1342 /* Bug workaround for smoothing (overrasterization) on SI. */
1343 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1344 db_shader_control &= C_02880C_Z_ORDER;
1345 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1346 }
1347
1348 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1349 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1350 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1351
1352 if (sctx->b.family == CHIP_STONEY &&
1353 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1354 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1355
1356 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1357 db_shader_control);
1358 }
1359
1360 /*
1361 * format translation
1362 */
1363 static uint32_t si_translate_colorformat(enum pipe_format format)
1364 {
1365 const struct util_format_description *desc = util_format_description(format);
1366
1367 #define HAS_SIZE(x,y,z,w) \
1368 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1369 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1370
1371 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1372 return V_028C70_COLOR_10_11_11;
1373
1374 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1375 return V_028C70_COLOR_INVALID;
1376
1377 switch (desc->nr_channels) {
1378 case 1:
1379 switch (desc->channel[0].size) {
1380 case 8:
1381 return V_028C70_COLOR_8;
1382 case 16:
1383 return V_028C70_COLOR_16;
1384 case 32:
1385 return V_028C70_COLOR_32;
1386 }
1387 break;
1388 case 2:
1389 if (desc->channel[0].size == desc->channel[1].size) {
1390 switch (desc->channel[0].size) {
1391 case 8:
1392 return V_028C70_COLOR_8_8;
1393 case 16:
1394 return V_028C70_COLOR_16_16;
1395 case 32:
1396 return V_028C70_COLOR_32_32;
1397 }
1398 } else if (HAS_SIZE(8,24,0,0)) {
1399 return V_028C70_COLOR_24_8;
1400 } else if (HAS_SIZE(24,8,0,0)) {
1401 return V_028C70_COLOR_8_24;
1402 }
1403 break;
1404 case 3:
1405 if (HAS_SIZE(5,6,5,0)) {
1406 return V_028C70_COLOR_5_6_5;
1407 } else if (HAS_SIZE(32,8,24,0)) {
1408 return V_028C70_COLOR_X24_8_32_FLOAT;
1409 }
1410 break;
1411 case 4:
1412 if (desc->channel[0].size == desc->channel[1].size &&
1413 desc->channel[0].size == desc->channel[2].size &&
1414 desc->channel[0].size == desc->channel[3].size) {
1415 switch (desc->channel[0].size) {
1416 case 4:
1417 return V_028C70_COLOR_4_4_4_4;
1418 case 8:
1419 return V_028C70_COLOR_8_8_8_8;
1420 case 16:
1421 return V_028C70_COLOR_16_16_16_16;
1422 case 32:
1423 return V_028C70_COLOR_32_32_32_32;
1424 }
1425 } else if (HAS_SIZE(5,5,5,1)) {
1426 return V_028C70_COLOR_1_5_5_5;
1427 } else if (HAS_SIZE(10,10,10,2)) {
1428 return V_028C70_COLOR_2_10_10_10;
1429 }
1430 break;
1431 }
1432 return V_028C70_COLOR_INVALID;
1433 }
1434
1435 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1436 {
1437 if (SI_BIG_ENDIAN) {
1438 switch(colorformat) {
1439 /* 8-bit buffers. */
1440 case V_028C70_COLOR_8:
1441 return V_028C70_ENDIAN_NONE;
1442
1443 /* 16-bit buffers. */
1444 case V_028C70_COLOR_5_6_5:
1445 case V_028C70_COLOR_1_5_5_5:
1446 case V_028C70_COLOR_4_4_4_4:
1447 case V_028C70_COLOR_16:
1448 case V_028C70_COLOR_8_8:
1449 return V_028C70_ENDIAN_8IN16;
1450
1451 /* 32-bit buffers. */
1452 case V_028C70_COLOR_8_8_8_8:
1453 case V_028C70_COLOR_2_10_10_10:
1454 case V_028C70_COLOR_8_24:
1455 case V_028C70_COLOR_24_8:
1456 case V_028C70_COLOR_16_16:
1457 return V_028C70_ENDIAN_8IN32;
1458
1459 /* 64-bit buffers. */
1460 case V_028C70_COLOR_16_16_16_16:
1461 return V_028C70_ENDIAN_8IN16;
1462
1463 case V_028C70_COLOR_32_32:
1464 return V_028C70_ENDIAN_8IN32;
1465
1466 /* 128-bit buffers. */
1467 case V_028C70_COLOR_32_32_32_32:
1468 return V_028C70_ENDIAN_8IN32;
1469 default:
1470 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1471 }
1472 } else {
1473 return V_028C70_ENDIAN_NONE;
1474 }
1475 }
1476
1477 static uint32_t si_translate_dbformat(enum pipe_format format)
1478 {
1479 switch (format) {
1480 case PIPE_FORMAT_Z16_UNORM:
1481 return V_028040_Z_16;
1482 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1483 case PIPE_FORMAT_X8Z24_UNORM:
1484 case PIPE_FORMAT_Z24X8_UNORM:
1485 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1486 return V_028040_Z_24; /* deprecated on SI */
1487 case PIPE_FORMAT_Z32_FLOAT:
1488 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1489 return V_028040_Z_32_FLOAT;
1490 default:
1491 return V_028040_Z_INVALID;
1492 }
1493 }
1494
1495 /*
1496 * Texture translation
1497 */
1498
1499 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1500 enum pipe_format format,
1501 const struct util_format_description *desc,
1502 int first_non_void)
1503 {
1504 struct si_screen *sscreen = (struct si_screen*)screen;
1505 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1506 sscreen->b.info.drm_minor >= 31) ||
1507 sscreen->b.info.drm_major == 3;
1508 boolean uniform = TRUE;
1509 int i;
1510
1511 /* Colorspace (return non-RGB formats directly). */
1512 switch (desc->colorspace) {
1513 /* Depth stencil formats */
1514 case UTIL_FORMAT_COLORSPACE_ZS:
1515 switch (format) {
1516 case PIPE_FORMAT_Z16_UNORM:
1517 return V_008F14_IMG_DATA_FORMAT_16;
1518 case PIPE_FORMAT_X24S8_UINT:
1519 case PIPE_FORMAT_Z24X8_UNORM:
1520 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1521 return V_008F14_IMG_DATA_FORMAT_8_24;
1522 case PIPE_FORMAT_X8Z24_UNORM:
1523 case PIPE_FORMAT_S8X24_UINT:
1524 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1525 return V_008F14_IMG_DATA_FORMAT_24_8;
1526 case PIPE_FORMAT_S8_UINT:
1527 return V_008F14_IMG_DATA_FORMAT_8;
1528 case PIPE_FORMAT_Z32_FLOAT:
1529 return V_008F14_IMG_DATA_FORMAT_32;
1530 case PIPE_FORMAT_X32_S8X24_UINT:
1531 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1532 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1533 default:
1534 goto out_unknown;
1535 }
1536
1537 case UTIL_FORMAT_COLORSPACE_YUV:
1538 goto out_unknown; /* TODO */
1539
1540 case UTIL_FORMAT_COLORSPACE_SRGB:
1541 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1542 goto out_unknown;
1543 break;
1544
1545 default:
1546 break;
1547 }
1548
1549 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1550 if (!enable_compressed_formats)
1551 goto out_unknown;
1552
1553 switch (format) {
1554 case PIPE_FORMAT_RGTC1_SNORM:
1555 case PIPE_FORMAT_LATC1_SNORM:
1556 case PIPE_FORMAT_RGTC1_UNORM:
1557 case PIPE_FORMAT_LATC1_UNORM:
1558 return V_008F14_IMG_DATA_FORMAT_BC4;
1559 case PIPE_FORMAT_RGTC2_SNORM:
1560 case PIPE_FORMAT_LATC2_SNORM:
1561 case PIPE_FORMAT_RGTC2_UNORM:
1562 case PIPE_FORMAT_LATC2_UNORM:
1563 return V_008F14_IMG_DATA_FORMAT_BC5;
1564 default:
1565 goto out_unknown;
1566 }
1567 }
1568
1569 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1570 sscreen->b.family >= CHIP_STONEY) {
1571 switch (format) {
1572 case PIPE_FORMAT_ETC1_RGB8:
1573 case PIPE_FORMAT_ETC2_RGB8:
1574 case PIPE_FORMAT_ETC2_SRGB8:
1575 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1576 case PIPE_FORMAT_ETC2_RGB8A1:
1577 case PIPE_FORMAT_ETC2_SRGB8A1:
1578 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1579 case PIPE_FORMAT_ETC2_RGBA8:
1580 case PIPE_FORMAT_ETC2_SRGBA8:
1581 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1582 case PIPE_FORMAT_ETC2_R11_UNORM:
1583 case PIPE_FORMAT_ETC2_R11_SNORM:
1584 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1585 case PIPE_FORMAT_ETC2_RG11_UNORM:
1586 case PIPE_FORMAT_ETC2_RG11_SNORM:
1587 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1588 default:
1589 goto out_unknown;
1590 }
1591 }
1592
1593 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1594 if (!enable_compressed_formats)
1595 goto out_unknown;
1596
1597 switch (format) {
1598 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1599 case PIPE_FORMAT_BPTC_SRGBA:
1600 return V_008F14_IMG_DATA_FORMAT_BC7;
1601 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1602 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1603 return V_008F14_IMG_DATA_FORMAT_BC6;
1604 default:
1605 goto out_unknown;
1606 }
1607 }
1608
1609 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1610 switch (format) {
1611 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1612 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1613 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1614 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1615 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1616 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1617 default:
1618 goto out_unknown;
1619 }
1620 }
1621
1622 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1623 if (!enable_compressed_formats)
1624 goto out_unknown;
1625
1626 if (!util_format_s3tc_enabled) {
1627 goto out_unknown;
1628 }
1629
1630 switch (format) {
1631 case PIPE_FORMAT_DXT1_RGB:
1632 case PIPE_FORMAT_DXT1_RGBA:
1633 case PIPE_FORMAT_DXT1_SRGB:
1634 case PIPE_FORMAT_DXT1_SRGBA:
1635 return V_008F14_IMG_DATA_FORMAT_BC1;
1636 case PIPE_FORMAT_DXT3_RGBA:
1637 case PIPE_FORMAT_DXT3_SRGBA:
1638 return V_008F14_IMG_DATA_FORMAT_BC2;
1639 case PIPE_FORMAT_DXT5_RGBA:
1640 case PIPE_FORMAT_DXT5_SRGBA:
1641 return V_008F14_IMG_DATA_FORMAT_BC3;
1642 default:
1643 goto out_unknown;
1644 }
1645 }
1646
1647 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1648 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1649 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1650 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1651 }
1652
1653 /* R8G8Bx_SNORM - TODO CxV8U8 */
1654
1655 /* See whether the components are of the same size. */
1656 for (i = 1; i < desc->nr_channels; i++) {
1657 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1658 }
1659
1660 /* Non-uniform formats. */
1661 if (!uniform) {
1662 switch(desc->nr_channels) {
1663 case 3:
1664 if (desc->channel[0].size == 5 &&
1665 desc->channel[1].size == 6 &&
1666 desc->channel[2].size == 5) {
1667 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1668 }
1669 goto out_unknown;
1670 case 4:
1671 if (desc->channel[0].size == 5 &&
1672 desc->channel[1].size == 5 &&
1673 desc->channel[2].size == 5 &&
1674 desc->channel[3].size == 1) {
1675 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1676 }
1677 if (desc->channel[0].size == 10 &&
1678 desc->channel[1].size == 10 &&
1679 desc->channel[2].size == 10 &&
1680 desc->channel[3].size == 2) {
1681 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1682 }
1683 goto out_unknown;
1684 }
1685 goto out_unknown;
1686 }
1687
1688 if (first_non_void < 0 || first_non_void > 3)
1689 goto out_unknown;
1690
1691 /* uniform formats */
1692 switch (desc->channel[first_non_void].size) {
1693 case 4:
1694 switch (desc->nr_channels) {
1695 #if 0 /* Not supported for render targets */
1696 case 2:
1697 return V_008F14_IMG_DATA_FORMAT_4_4;
1698 #endif
1699 case 4:
1700 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1701 }
1702 break;
1703 case 8:
1704 switch (desc->nr_channels) {
1705 case 1:
1706 return V_008F14_IMG_DATA_FORMAT_8;
1707 case 2:
1708 return V_008F14_IMG_DATA_FORMAT_8_8;
1709 case 4:
1710 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1711 }
1712 break;
1713 case 16:
1714 switch (desc->nr_channels) {
1715 case 1:
1716 return V_008F14_IMG_DATA_FORMAT_16;
1717 case 2:
1718 return V_008F14_IMG_DATA_FORMAT_16_16;
1719 case 4:
1720 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1721 }
1722 break;
1723 case 32:
1724 switch (desc->nr_channels) {
1725 case 1:
1726 return V_008F14_IMG_DATA_FORMAT_32;
1727 case 2:
1728 return V_008F14_IMG_DATA_FORMAT_32_32;
1729 #if 0 /* Not supported for render targets */
1730 case 3:
1731 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1732 #endif
1733 case 4:
1734 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1735 }
1736 }
1737
1738 out_unknown:
1739 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1740 return ~0;
1741 }
1742
1743 static unsigned si_tex_wrap(unsigned wrap)
1744 {
1745 switch (wrap) {
1746 default:
1747 case PIPE_TEX_WRAP_REPEAT:
1748 return V_008F30_SQ_TEX_WRAP;
1749 case PIPE_TEX_WRAP_CLAMP:
1750 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1751 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1752 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1753 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1754 return V_008F30_SQ_TEX_CLAMP_BORDER;
1755 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1756 return V_008F30_SQ_TEX_MIRROR;
1757 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1758 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1759 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1760 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1761 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1762 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1763 }
1764 }
1765
1766 static unsigned si_tex_filter(unsigned filter)
1767 {
1768 switch (filter) {
1769 default:
1770 case PIPE_TEX_FILTER_NEAREST:
1771 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1772 case PIPE_TEX_FILTER_LINEAR:
1773 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1774 }
1775 }
1776
1777 static unsigned si_tex_mipfilter(unsigned filter)
1778 {
1779 switch (filter) {
1780 case PIPE_TEX_MIPFILTER_NEAREST:
1781 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1782 case PIPE_TEX_MIPFILTER_LINEAR:
1783 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1784 default:
1785 case PIPE_TEX_MIPFILTER_NONE:
1786 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1787 }
1788 }
1789
1790 static unsigned si_tex_compare(unsigned compare)
1791 {
1792 switch (compare) {
1793 default:
1794 case PIPE_FUNC_NEVER:
1795 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1796 case PIPE_FUNC_LESS:
1797 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1798 case PIPE_FUNC_EQUAL:
1799 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1800 case PIPE_FUNC_LEQUAL:
1801 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1802 case PIPE_FUNC_GREATER:
1803 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1804 case PIPE_FUNC_NOTEQUAL:
1805 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1806 case PIPE_FUNC_GEQUAL:
1807 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1808 case PIPE_FUNC_ALWAYS:
1809 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1810 }
1811 }
1812
1813 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1814 unsigned nr_samples)
1815 {
1816 if (view_target == PIPE_TEXTURE_CUBE ||
1817 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1818 res_target = view_target;
1819
1820 switch (res_target) {
1821 default:
1822 case PIPE_TEXTURE_1D:
1823 return V_008F1C_SQ_RSRC_IMG_1D;
1824 case PIPE_TEXTURE_1D_ARRAY:
1825 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1826 case PIPE_TEXTURE_2D:
1827 case PIPE_TEXTURE_RECT:
1828 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1829 V_008F1C_SQ_RSRC_IMG_2D;
1830 case PIPE_TEXTURE_2D_ARRAY:
1831 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1832 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1833 case PIPE_TEXTURE_3D:
1834 return V_008F1C_SQ_RSRC_IMG_3D;
1835 case PIPE_TEXTURE_CUBE:
1836 case PIPE_TEXTURE_CUBE_ARRAY:
1837 return V_008F1C_SQ_RSRC_IMG_CUBE;
1838 }
1839 }
1840
1841 /*
1842 * Format support testing
1843 */
1844
1845 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1846 {
1847 return si_translate_texformat(screen, format, util_format_description(format),
1848 util_format_get_first_non_void_channel(format)) != ~0U;
1849 }
1850
1851 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1852 const struct util_format_description *desc,
1853 int first_non_void)
1854 {
1855 unsigned type = desc->channel[first_non_void].type;
1856 int i;
1857
1858 if (type == UTIL_FORMAT_TYPE_FIXED)
1859 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1860
1861 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1862 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1863
1864 if (desc->nr_channels == 4 &&
1865 desc->channel[0].size == 10 &&
1866 desc->channel[1].size == 10 &&
1867 desc->channel[2].size == 10 &&
1868 desc->channel[3].size == 2)
1869 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1870
1871 /* See whether the components are of the same size. */
1872 for (i = 0; i < desc->nr_channels; i++) {
1873 if (desc->channel[first_non_void].size != desc->channel[i].size)
1874 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1875 }
1876
1877 switch (desc->channel[first_non_void].size) {
1878 case 8:
1879 switch (desc->nr_channels) {
1880 case 1:
1881 return V_008F0C_BUF_DATA_FORMAT_8;
1882 case 2:
1883 return V_008F0C_BUF_DATA_FORMAT_8_8;
1884 case 3:
1885 case 4:
1886 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1887 }
1888 break;
1889 case 16:
1890 switch (desc->nr_channels) {
1891 case 1:
1892 return V_008F0C_BUF_DATA_FORMAT_16;
1893 case 2:
1894 return V_008F0C_BUF_DATA_FORMAT_16_16;
1895 case 3:
1896 case 4:
1897 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1898 }
1899 break;
1900 case 32:
1901 /* From the Southern Islands ISA documentation about MTBUF:
1902 * 'Memory reads of data in memory that is 32 or 64 bits do not
1903 * undergo any format conversion.'
1904 */
1905 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1906 !desc->channel[first_non_void].pure_integer)
1907 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1908
1909 switch (desc->nr_channels) {
1910 case 1:
1911 return V_008F0C_BUF_DATA_FORMAT_32;
1912 case 2:
1913 return V_008F0C_BUF_DATA_FORMAT_32_32;
1914 case 3:
1915 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1916 case 4:
1917 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1918 }
1919 break;
1920 }
1921
1922 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1923 }
1924
1925 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1926 const struct util_format_description *desc,
1927 int first_non_void)
1928 {
1929 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1930 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1931
1932 switch (desc->channel[first_non_void].type) {
1933 case UTIL_FORMAT_TYPE_SIGNED:
1934 if (desc->channel[first_non_void].normalized)
1935 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1936 else if (desc->channel[first_non_void].pure_integer)
1937 return V_008F0C_BUF_NUM_FORMAT_SINT;
1938 else
1939 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1940 break;
1941 case UTIL_FORMAT_TYPE_UNSIGNED:
1942 if (desc->channel[first_non_void].normalized)
1943 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1944 else if (desc->channel[first_non_void].pure_integer)
1945 return V_008F0C_BUF_NUM_FORMAT_UINT;
1946 else
1947 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1948 break;
1949 case UTIL_FORMAT_TYPE_FLOAT:
1950 default:
1951 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1952 }
1953 }
1954
1955 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1956 {
1957 const struct util_format_description *desc;
1958 int first_non_void;
1959 unsigned data_format;
1960
1961 desc = util_format_description(format);
1962 first_non_void = util_format_get_first_non_void_channel(format);
1963 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1964 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1965 }
1966
1967 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1968 {
1969 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1970 r600_translate_colorswap(format) != ~0U;
1971 }
1972
1973 static bool si_is_zs_format_supported(enum pipe_format format)
1974 {
1975 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1976 }
1977
1978 boolean si_is_format_supported(struct pipe_screen *screen,
1979 enum pipe_format format,
1980 enum pipe_texture_target target,
1981 unsigned sample_count,
1982 unsigned usage)
1983 {
1984 unsigned retval = 0;
1985
1986 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1987 R600_ERR("r600: unsupported texture type %d\n", target);
1988 return FALSE;
1989 }
1990
1991 if (!util_format_is_supported(format, usage))
1992 return FALSE;
1993
1994 if (sample_count > 1) {
1995 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1996 return FALSE;
1997
1998 switch (sample_count) {
1999 case 2:
2000 case 4:
2001 case 8:
2002 break;
2003 default:
2004 return FALSE;
2005 }
2006 }
2007
2008 if (usage & PIPE_BIND_SAMPLER_VIEW) {
2009 if (target == PIPE_BUFFER) {
2010 if (si_is_vertex_format_supported(screen, format))
2011 retval |= PIPE_BIND_SAMPLER_VIEW;
2012 } else {
2013 if (si_is_sampler_format_supported(screen, format))
2014 retval |= PIPE_BIND_SAMPLER_VIEW;
2015 }
2016 }
2017
2018 if ((usage & (PIPE_BIND_RENDER_TARGET |
2019 PIPE_BIND_DISPLAY_TARGET |
2020 PIPE_BIND_SCANOUT |
2021 PIPE_BIND_SHARED |
2022 PIPE_BIND_BLENDABLE)) &&
2023 si_is_colorbuffer_format_supported(format)) {
2024 retval |= usage &
2025 (PIPE_BIND_RENDER_TARGET |
2026 PIPE_BIND_DISPLAY_TARGET |
2027 PIPE_BIND_SCANOUT |
2028 PIPE_BIND_SHARED);
2029 if (!util_format_is_pure_integer(format) &&
2030 !util_format_is_depth_or_stencil(format))
2031 retval |= usage & PIPE_BIND_BLENDABLE;
2032 }
2033
2034 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2035 si_is_zs_format_supported(format)) {
2036 retval |= PIPE_BIND_DEPTH_STENCIL;
2037 }
2038
2039 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
2040 si_is_vertex_format_supported(screen, format)) {
2041 retval |= PIPE_BIND_VERTEX_BUFFER;
2042 }
2043
2044 if (usage & PIPE_BIND_TRANSFER_READ)
2045 retval |= PIPE_BIND_TRANSFER_READ;
2046 if (usage & PIPE_BIND_TRANSFER_WRITE)
2047 retval |= PIPE_BIND_TRANSFER_WRITE;
2048
2049 if ((usage & PIPE_BIND_LINEAR) &&
2050 !util_format_is_compressed(format) &&
2051 !(usage & PIPE_BIND_DEPTH_STENCIL))
2052 retval |= PIPE_BIND_LINEAR;
2053
2054 return retval == usage;
2055 }
2056
2057 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
2058 {
2059 unsigned tile_mode_index = 0;
2060
2061 if (stencil) {
2062 tile_mode_index = rtex->surface.stencil_tiling_index[level];
2063 } else {
2064 tile_mode_index = rtex->surface.tiling_index[level];
2065 }
2066 return tile_mode_index;
2067 }
2068
2069 /*
2070 * framebuffer handling
2071 */
2072
2073 static void si_choose_spi_color_formats(struct r600_surface *surf,
2074 unsigned format, unsigned swap,
2075 unsigned ntype, bool is_depth)
2076 {
2077 /* Alpha is needed for alpha-to-coverage.
2078 * Blending may be with or without alpha.
2079 */
2080 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2081 unsigned alpha = 0; /* exports alpha, but may not support blending */
2082 unsigned blend = 0; /* supports blending, but may not export alpha */
2083 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2084
2085 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2086 * Other chips have multiple choices, though they are not necessarily better.
2087 */
2088 switch (format) {
2089 case V_028C70_COLOR_5_6_5:
2090 case V_028C70_COLOR_1_5_5_5:
2091 case V_028C70_COLOR_5_5_5_1:
2092 case V_028C70_COLOR_4_4_4_4:
2093 case V_028C70_COLOR_10_11_11:
2094 case V_028C70_COLOR_11_11_10:
2095 case V_028C70_COLOR_8:
2096 case V_028C70_COLOR_8_8:
2097 case V_028C70_COLOR_8_8_8_8:
2098 case V_028C70_COLOR_10_10_10_2:
2099 case V_028C70_COLOR_2_10_10_10:
2100 if (ntype == V_028C70_NUMBER_UINT)
2101 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2102 else if (ntype == V_028C70_NUMBER_SINT)
2103 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2104 else
2105 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2106 break;
2107
2108 case V_028C70_COLOR_16:
2109 case V_028C70_COLOR_16_16:
2110 case V_028C70_COLOR_16_16_16_16:
2111 if (ntype == V_028C70_NUMBER_UNORM ||
2112 ntype == V_028C70_NUMBER_SNORM) {
2113 /* UNORM16 and SNORM16 don't support blending */
2114 if (ntype == V_028C70_NUMBER_UNORM)
2115 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2116 else
2117 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2118
2119 /* Use 32 bits per channel for blending. */
2120 if (format == V_028C70_COLOR_16) {
2121 if (swap == V_028C70_SWAP_STD) { /* R */
2122 blend = V_028714_SPI_SHADER_32_R;
2123 blend_alpha = V_028714_SPI_SHADER_32_AR;
2124 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2125 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2126 else
2127 assert(0);
2128 } else if (format == V_028C70_COLOR_16_16) {
2129 if (swap == V_028C70_SWAP_STD) { /* RG */
2130 blend = V_028714_SPI_SHADER_32_GR;
2131 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2132 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2133 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2134 else
2135 assert(0);
2136 } else /* 16_16_16_16 */
2137 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2138 } else if (ntype == V_028C70_NUMBER_UINT)
2139 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2140 else if (ntype == V_028C70_NUMBER_SINT)
2141 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2142 else if (ntype == V_028C70_NUMBER_FLOAT)
2143 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2144 else
2145 assert(0);
2146 break;
2147
2148 case V_028C70_COLOR_32:
2149 if (swap == V_028C70_SWAP_STD) { /* R */
2150 blend = normal = V_028714_SPI_SHADER_32_R;
2151 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2152 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2153 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2154 else
2155 assert(0);
2156 break;
2157
2158 case V_028C70_COLOR_32_32:
2159 if (swap == V_028C70_SWAP_STD) { /* RG */
2160 blend = normal = V_028714_SPI_SHADER_32_GR;
2161 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2162 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2163 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2164 else
2165 assert(0);
2166 break;
2167
2168 case V_028C70_COLOR_32_32_32_32:
2169 case V_028C70_COLOR_8_24:
2170 case V_028C70_COLOR_24_8:
2171 case V_028C70_COLOR_X24_8_32_FLOAT:
2172 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2173 break;
2174
2175 default:
2176 assert(0);
2177 return;
2178 }
2179
2180 /* The DB->CB copy needs 32_ABGR. */
2181 if (is_depth)
2182 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2183
2184 surf->spi_shader_col_format = normal;
2185 surf->spi_shader_col_format_alpha = alpha;
2186 surf->spi_shader_col_format_blend = blend;
2187 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2188 }
2189
2190 static void si_initialize_color_surface(struct si_context *sctx,
2191 struct r600_surface *surf)
2192 {
2193 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2194 unsigned level = surf->base.u.tex.level;
2195 uint64_t offset = rtex->surface.level[level].offset;
2196 unsigned pitch, slice;
2197 unsigned color_info, color_attrib, color_pitch, color_view;
2198 unsigned tile_mode_index;
2199 unsigned format, swap, ntype, endian;
2200 const struct util_format_description *desc;
2201 int i;
2202 unsigned blend_clamp = 0, blend_bypass = 0;
2203
2204 /* Layered rendering doesn't work with LINEAR_GENERAL.
2205 * (LINEAR_ALIGNED and others work) */
2206 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2207 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2208 offset += rtex->surface.level[level].slice_size *
2209 surf->base.u.tex.first_layer;
2210 color_view = 0;
2211 } else {
2212 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2213 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2214 }
2215
2216 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2217 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2218 if (slice) {
2219 slice = slice - 1;
2220 }
2221
2222 tile_mode_index = si_tile_mode_index(rtex, level, false);
2223
2224 desc = util_format_description(surf->base.format);
2225 for (i = 0; i < 4; i++) {
2226 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2227 break;
2228 }
2229 }
2230 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2231 ntype = V_028C70_NUMBER_FLOAT;
2232 } else {
2233 ntype = V_028C70_NUMBER_UNORM;
2234 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2235 ntype = V_028C70_NUMBER_SRGB;
2236 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2237 if (desc->channel[i].pure_integer) {
2238 ntype = V_028C70_NUMBER_SINT;
2239 } else {
2240 assert(desc->channel[i].normalized);
2241 ntype = V_028C70_NUMBER_SNORM;
2242 }
2243 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2244 if (desc->channel[i].pure_integer) {
2245 ntype = V_028C70_NUMBER_UINT;
2246 } else {
2247 assert(desc->channel[i].normalized);
2248 ntype = V_028C70_NUMBER_UNORM;
2249 }
2250 }
2251 }
2252
2253 format = si_translate_colorformat(surf->base.format);
2254 if (format == V_028C70_COLOR_INVALID) {
2255 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2256 }
2257 assert(format != V_028C70_COLOR_INVALID);
2258 swap = r600_translate_colorswap(surf->base.format);
2259 endian = si_colorformat_endian_swap(format);
2260
2261 /* blend clamp should be set for all NORM/SRGB types */
2262 if (ntype == V_028C70_NUMBER_UNORM ||
2263 ntype == V_028C70_NUMBER_SNORM ||
2264 ntype == V_028C70_NUMBER_SRGB)
2265 blend_clamp = 1;
2266
2267 /* set blend bypass according to docs if SINT/UINT or
2268 8/24 COLOR variants */
2269 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2270 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2271 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2272 blend_clamp = 0;
2273 blend_bypass = 1;
2274 }
2275
2276 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2277 (format == V_028C70_COLOR_8 ||
2278 format == V_028C70_COLOR_8_8 ||
2279 format == V_028C70_COLOR_8_8_8_8))
2280 surf->color_is_int8 = true;
2281
2282 color_info = S_028C70_FORMAT(format) |
2283 S_028C70_COMP_SWAP(swap) |
2284 S_028C70_BLEND_CLAMP(blend_clamp) |
2285 S_028C70_BLEND_BYPASS(blend_bypass) |
2286 S_028C70_NUMBER_TYPE(ntype) |
2287 S_028C70_ENDIAN(endian);
2288
2289 color_pitch = S_028C64_TILE_MAX(pitch);
2290
2291 /* Intensity is implemented as Red, so treat it that way. */
2292 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2293 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1 ||
2294 util_format_is_intensity(surf->base.format));
2295
2296 if (rtex->resource.b.b.nr_samples > 1) {
2297 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2298
2299 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2300 S_028C74_NUM_FRAGMENTS(log_samples);
2301
2302 if (rtex->fmask.size) {
2303 color_info |= S_028C70_COMPRESSION(1);
2304 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2305
2306 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2307
2308 if (sctx->b.chip_class == SI) {
2309 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2310 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2311 }
2312 if (sctx->b.chip_class >= CIK) {
2313 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2314 }
2315 }
2316 }
2317
2318 offset += rtex->resource.gpu_address;
2319
2320 surf->cb_color_base = offset >> 8;
2321 surf->cb_color_pitch = color_pitch;
2322 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2323 surf->cb_color_view = color_view;
2324 surf->cb_color_info = color_info;
2325 surf->cb_color_attrib = color_attrib;
2326
2327 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2328 unsigned max_uncompressed_block_size = 2;
2329
2330 if (rtex->surface.nsamples > 1) {
2331 if (rtex->surface.bpe == 1)
2332 max_uncompressed_block_size = 0;
2333 else if (rtex->surface.bpe == 2)
2334 max_uncompressed_block_size = 1;
2335 }
2336
2337 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2338 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2339 surf->cb_dcc_base = (rtex->resource.gpu_address +
2340 rtex->dcc_offset +
2341 rtex->surface.level[level].dcc_offset) >> 8;
2342 }
2343
2344 if (rtex->fmask.size) {
2345 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2346 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2347 } else {
2348 /* This must be set for fast clear to work without FMASK. */
2349 surf->cb_color_fmask = surf->cb_color_base;
2350 surf->cb_color_fmask_slice = surf->cb_color_slice;
2351 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2352
2353 if (sctx->b.chip_class == SI) {
2354 unsigned bankh = util_logbase2(rtex->surface.bankh);
2355 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2356 }
2357
2358 if (sctx->b.chip_class >= CIK) {
2359 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2360 }
2361 }
2362
2363 /* Determine pixel shader export format */
2364 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2365
2366 surf->color_initialized = true;
2367 }
2368
2369 static void si_init_depth_surface(struct si_context *sctx,
2370 struct r600_surface *surf)
2371 {
2372 struct si_screen *sscreen = sctx->screen;
2373 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2374 unsigned level = surf->base.u.tex.level;
2375 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2376 unsigned format, tile_mode_index, array_mode;
2377 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2378 uint32_t z_info, s_info, db_depth_info;
2379 uint64_t z_offs, s_offs;
2380 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2381
2382 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2383 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2384 case PIPE_FORMAT_X8Z24_UNORM:
2385 case PIPE_FORMAT_Z24X8_UNORM:
2386 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2387 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2388 break;
2389 case PIPE_FORMAT_Z32_FLOAT:
2390 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2391 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2392 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2393 break;
2394 case PIPE_FORMAT_Z16_UNORM:
2395 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2396 break;
2397 default:
2398 assert(0);
2399 }
2400
2401 format = si_translate_dbformat(rtex->resource.b.b.format);
2402
2403 if (format == V_028040_Z_INVALID) {
2404 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2405 }
2406 assert(format != V_028040_Z_INVALID);
2407
2408 s_offs = z_offs = rtex->resource.gpu_address;
2409 z_offs += rtex->surface.level[level].offset;
2410 s_offs += rtex->surface.stencil_level[level].offset;
2411
2412 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2413
2414 z_info = S_028040_FORMAT(format);
2415 if (rtex->resource.b.b.nr_samples > 1) {
2416 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2417 }
2418
2419 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2420 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2421 else
2422 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2423
2424 if (sctx->b.chip_class >= CIK) {
2425 switch (rtex->surface.level[level].mode) {
2426 case RADEON_SURF_MODE_2D:
2427 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2428 break;
2429 case RADEON_SURF_MODE_1D:
2430 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2431 case RADEON_SURF_MODE_LINEAR:
2432 default:
2433 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2434 break;
2435 }
2436 tile_split = rtex->surface.tile_split;
2437 stile_split = rtex->surface.stencil_tile_split;
2438 macro_aspect = rtex->surface.mtilea;
2439 bankw = rtex->surface.bankw;
2440 bankh = rtex->surface.bankh;
2441 tile_split = cik_tile_split(tile_split);
2442 stile_split = cik_tile_split(stile_split);
2443 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2444 bankw = cik_bank_wh(bankw);
2445 bankh = cik_bank_wh(bankh);
2446 nbanks = si_num_banks(sscreen, rtex);
2447 tile_mode_index = si_tile_mode_index(rtex, level, false);
2448 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2449
2450 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2451 S_02803C_PIPE_CONFIG(pipe_config) |
2452 S_02803C_BANK_WIDTH(bankw) |
2453 S_02803C_BANK_HEIGHT(bankh) |
2454 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2455 S_02803C_NUM_BANKS(nbanks);
2456 z_info |= S_028040_TILE_SPLIT(tile_split);
2457 s_info |= S_028044_TILE_SPLIT(stile_split);
2458 } else {
2459 tile_mode_index = si_tile_mode_index(rtex, level, false);
2460 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2461 tile_mode_index = si_tile_mode_index(rtex, level, true);
2462 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2463 }
2464
2465 /* HiZ aka depth buffer htile */
2466 /* use htile only for first level */
2467 if (rtex->htile_buffer && !level) {
2468 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2469 S_028040_ALLOW_EXPCLEAR(1);
2470
2471 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2472 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2473 else
2474 /* Use all of the htile_buffer for depth if there's no stencil. */
2475 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2476
2477 uint64_t va = rtex->htile_buffer->gpu_address;
2478 db_htile_data_base = va >> 8;
2479 db_htile_surface = S_028ABC_FULL_CACHE(1);
2480 } else {
2481 db_htile_data_base = 0;
2482 db_htile_surface = 0;
2483 }
2484
2485 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2486
2487 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2488 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2489 surf->db_htile_data_base = db_htile_data_base;
2490 surf->db_depth_info = db_depth_info;
2491 surf->db_z_info = z_info;
2492 surf->db_stencil_info = s_info;
2493 surf->db_depth_base = z_offs >> 8;
2494 surf->db_stencil_base = s_offs >> 8;
2495 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2496 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2497 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2498 levelinfo->nblk_y) / 64 - 1);
2499 surf->db_htile_surface = db_htile_surface;
2500 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2501
2502 surf->depth_initialized = true;
2503 }
2504
2505 static void si_set_framebuffer_state(struct pipe_context *ctx,
2506 const struct pipe_framebuffer_state *state)
2507 {
2508 struct si_context *sctx = (struct si_context *)ctx;
2509 struct pipe_constant_buffer constbuf = {0};
2510 struct r600_surface *surf = NULL;
2511 struct r600_texture *rtex;
2512 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2513 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2514 int i;
2515
2516 /* Only flush TC when changing the framebuffer state, because
2517 * the only client not using TC that can change textures is
2518 * the framebuffer.
2519 *
2520 * Flush all CB and DB caches here because all buffers can be used
2521 * for write by both TC (with shader image stores) and CB/DB.
2522 */
2523 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2524 SI_CONTEXT_INV_GLOBAL_L2 |
2525 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2526
2527 /* Take the maximum of the old and new count. If the new count is lower,
2528 * dirtying is needed to disable the unbound colorbuffers.
2529 */
2530 sctx->framebuffer.dirty_cbufs |=
2531 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2532 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2533
2534 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2535
2536 sctx->framebuffer.spi_shader_col_format = 0;
2537 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2538 sctx->framebuffer.spi_shader_col_format_blend = 0;
2539 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2540 sctx->framebuffer.color_is_int8 = 0;
2541
2542 sctx->framebuffer.compressed_cb_mask = 0;
2543 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2544 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2545 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2546 util_format_is_pure_integer(state->cbufs[0]->format);
2547
2548 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2549 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2550
2551 for (i = 0; i < state->nr_cbufs; i++) {
2552 if (!state->cbufs[i])
2553 continue;
2554
2555 surf = (struct r600_surface*)state->cbufs[i];
2556 rtex = (struct r600_texture*)surf->base.texture;
2557
2558 if (!surf->color_initialized) {
2559 si_initialize_color_surface(sctx, surf);
2560 }
2561
2562 sctx->framebuffer.spi_shader_col_format |=
2563 surf->spi_shader_col_format << (i * 4);
2564 sctx->framebuffer.spi_shader_col_format_alpha |=
2565 surf->spi_shader_col_format_alpha << (i * 4);
2566 sctx->framebuffer.spi_shader_col_format_blend |=
2567 surf->spi_shader_col_format_blend << (i * 4);
2568 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2569 surf->spi_shader_col_format_blend_alpha << (i * 4);
2570
2571 if (surf->color_is_int8)
2572 sctx->framebuffer.color_is_int8 |= 1 << i;
2573
2574 if (rtex->fmask.size && rtex->cmask.size) {
2575 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2576 }
2577 r600_context_add_resource_size(ctx, surf->base.texture);
2578 }
2579 /* Set the second SPI format for possible dual-src blending. */
2580 if (i == 1 && surf) {
2581 sctx->framebuffer.spi_shader_col_format |=
2582 surf->spi_shader_col_format << (i * 4);
2583 sctx->framebuffer.spi_shader_col_format_alpha |=
2584 surf->spi_shader_col_format_alpha << (i * 4);
2585 sctx->framebuffer.spi_shader_col_format_blend |=
2586 surf->spi_shader_col_format_blend << (i * 4);
2587 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2588 surf->spi_shader_col_format_blend_alpha << (i * 4);
2589 }
2590
2591 if (state->zsbuf) {
2592 surf = (struct r600_surface*)state->zsbuf;
2593
2594 if (!surf->depth_initialized) {
2595 si_init_depth_surface(sctx, surf);
2596 }
2597 r600_context_add_resource_size(ctx, surf->base.texture);
2598 }
2599
2600 si_update_poly_offset_state(sctx);
2601 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2602 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2603
2604 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2605 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2606 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2607
2608 /* Set sample locations as fragment shader constants. */
2609 switch (sctx->framebuffer.nr_samples) {
2610 case 1:
2611 constbuf.user_buffer = sctx->b.sample_locations_1x;
2612 break;
2613 case 2:
2614 constbuf.user_buffer = sctx->b.sample_locations_2x;
2615 break;
2616 case 4:
2617 constbuf.user_buffer = sctx->b.sample_locations_4x;
2618 break;
2619 case 8:
2620 constbuf.user_buffer = sctx->b.sample_locations_8x;
2621 break;
2622 case 16:
2623 constbuf.user_buffer = sctx->b.sample_locations_16x;
2624 break;
2625 default:
2626 assert(0);
2627 }
2628 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2629 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2630 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2631
2632 /* Smoothing (only possible with nr_samples == 1) uses the same
2633 * sample locations as the MSAA it simulates.
2634 *
2635 * Therefore, don't update the sample locations when
2636 * transitioning from no AA to smoothing-equivalent AA, and
2637 * vice versa.
2638 */
2639 if ((sctx->framebuffer.nr_samples != 1 ||
2640 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2641 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2642 old_nr_samples != 1))
2643 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2644 }
2645 }
2646
2647 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2648 {
2649 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2650 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2651 unsigned i, nr_cbufs = state->nr_cbufs;
2652 struct r600_texture *tex = NULL;
2653 struct r600_surface *cb = NULL;
2654
2655 /* Colorbuffers. */
2656 for (i = 0; i < nr_cbufs; i++) {
2657 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2658 continue;
2659
2660 cb = (struct r600_surface*)state->cbufs[i];
2661 if (!cb) {
2662 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2663 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2664 continue;
2665 }
2666
2667 tex = (struct r600_texture *)cb->base.texture;
2668 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2669 &tex->resource, RADEON_USAGE_READWRITE,
2670 tex->surface.nsamples > 1 ?
2671 RADEON_PRIO_COLOR_BUFFER_MSAA :
2672 RADEON_PRIO_COLOR_BUFFER);
2673
2674 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2675 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2676 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2677 RADEON_PRIO_CMASK);
2678 }
2679
2680 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2681 sctx->b.chip_class >= VI ? 14 : 13);
2682 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2683 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2684 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2685 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2686 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2687 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2688 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2689 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2690 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2691 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2692 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2693 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2694 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2695
2696 if (sctx->b.chip_class >= VI)
2697 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2698 }
2699 /* set CB_COLOR1_INFO for possible dual-src blending */
2700 if (i == 1 && state->cbufs[0] &&
2701 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2702 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2703 cb->cb_color_info | tex->cb_color_info);
2704 i++;
2705 }
2706 for (; i < 8 ; i++)
2707 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2708 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2709
2710 /* ZS buffer. */
2711 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2712 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2713 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2714
2715 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2716 &rtex->resource, RADEON_USAGE_READWRITE,
2717 zb->base.texture->nr_samples > 1 ?
2718 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2719 RADEON_PRIO_DEPTH_BUFFER);
2720
2721 if (zb->db_htile_data_base) {
2722 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2723 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2724 RADEON_PRIO_HTILE);
2725 }
2726
2727 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2728 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2729
2730 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2731 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2732 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2733 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2734 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2735 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2736 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2737 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2738 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2739 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2740 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2741
2742 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2743 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2744 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2745
2746 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2747 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2748 zb->pa_su_poly_offset_db_fmt_cntl);
2749 } else if (sctx->framebuffer.dirty_zsbuf) {
2750 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2751 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2752 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2753 }
2754
2755 /* Framebuffer dimensions. */
2756 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2757 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2758 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2759
2760 sctx->framebuffer.dirty_cbufs = 0;
2761 sctx->framebuffer.dirty_zsbuf = false;
2762 }
2763
2764 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2765 struct r600_atom *atom)
2766 {
2767 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2768 unsigned nr_samples = sctx->framebuffer.nr_samples;
2769
2770 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2771 SI_NUM_SMOOTH_AA_SAMPLES);
2772 }
2773
2774 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2775 {
2776 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2777
2778 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2779 sctx->ps_iter_samples,
2780 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2781 }
2782
2783
2784 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2785 {
2786 struct si_context *sctx = (struct si_context *)ctx;
2787
2788 if (sctx->ps_iter_samples == min_samples)
2789 return;
2790
2791 sctx->ps_iter_samples = min_samples;
2792
2793 if (sctx->framebuffer.nr_samples > 1)
2794 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2795 }
2796
2797 /*
2798 * Samplers
2799 */
2800
2801 /**
2802 * Build the sampler view descriptor for a buffer texture.
2803 * @param state 256-bit descriptor; only the high 128 bits are filled in
2804 */
2805 void
2806 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2807 enum pipe_format format,
2808 unsigned first_element, unsigned last_element,
2809 uint32_t *state)
2810 {
2811 const struct util_format_description *desc;
2812 int first_non_void;
2813 uint64_t va;
2814 unsigned stride;
2815 unsigned num_records;
2816 unsigned num_format, data_format;
2817
2818 desc = util_format_description(format);
2819 first_non_void = util_format_get_first_non_void_channel(format);
2820 stride = desc->block.bits / 8;
2821 va = buf->gpu_address + first_element * stride;
2822 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2823 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2824
2825 num_records = last_element + 1 - first_element;
2826 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2827
2828 if (screen->b.chip_class >= VI)
2829 num_records *= stride;
2830
2831 state[4] = va;
2832 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2833 S_008F04_STRIDE(stride);
2834 state[6] = num_records;
2835 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2836 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2837 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2838 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2839 S_008F0C_NUM_FORMAT(num_format) |
2840 S_008F0C_DATA_FORMAT(data_format);
2841 }
2842
2843 /**
2844 * Build the sampler view descriptor for a texture.
2845 */
2846 void
2847 si_make_texture_descriptor(struct si_screen *screen,
2848 struct r600_texture *tex,
2849 bool sampler,
2850 enum pipe_texture_target target,
2851 enum pipe_format pipe_format,
2852 const unsigned char state_swizzle[4],
2853 unsigned base_level, unsigned first_level, unsigned last_level,
2854 unsigned first_layer, unsigned last_layer,
2855 unsigned width, unsigned height, unsigned depth,
2856 uint32_t *state,
2857 uint32_t *fmask_state)
2858 {
2859 struct pipe_resource *res = &tex->resource.b.b;
2860 const struct radeon_surf_level *surflevel = tex->surface.level;
2861 const struct util_format_description *desc;
2862 unsigned char swizzle[4];
2863 int first_non_void;
2864 unsigned num_format, data_format, type;
2865 uint32_t pitch;
2866 uint64_t va;
2867
2868 /* Texturing with separate depth and stencil. */
2869 if (tex->is_depth && !tex->is_flushing_texture) {
2870 switch (pipe_format) {
2871 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2872 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2873 break;
2874 case PIPE_FORMAT_X8Z24_UNORM:
2875 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2876 /* Z24 is always stored like this. */
2877 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2878 break;
2879 case PIPE_FORMAT_X24S8_UINT:
2880 case PIPE_FORMAT_S8X24_UINT:
2881 case PIPE_FORMAT_X32_S8X24_UINT:
2882 pipe_format = PIPE_FORMAT_S8_UINT;
2883 surflevel = tex->surface.stencil_level;
2884 break;
2885 default:;
2886 }
2887 }
2888
2889 desc = util_format_description(pipe_format);
2890
2891 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2892 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2893 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2894
2895 switch (pipe_format) {
2896 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2897 case PIPE_FORMAT_X24S8_UINT:
2898 case PIPE_FORMAT_X32_S8X24_UINT:
2899 case PIPE_FORMAT_X8Z24_UNORM:
2900 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2901 break;
2902 default:
2903 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2904 }
2905 } else {
2906 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2907 }
2908
2909 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2910
2911 switch (pipe_format) {
2912 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2913 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2914 break;
2915 default:
2916 if (first_non_void < 0) {
2917 if (util_format_is_compressed(pipe_format)) {
2918 switch (pipe_format) {
2919 case PIPE_FORMAT_DXT1_SRGB:
2920 case PIPE_FORMAT_DXT1_SRGBA:
2921 case PIPE_FORMAT_DXT3_SRGBA:
2922 case PIPE_FORMAT_DXT5_SRGBA:
2923 case PIPE_FORMAT_BPTC_SRGBA:
2924 case PIPE_FORMAT_ETC2_SRGB8:
2925 case PIPE_FORMAT_ETC2_SRGB8A1:
2926 case PIPE_FORMAT_ETC2_SRGBA8:
2927 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2928 break;
2929 case PIPE_FORMAT_RGTC1_SNORM:
2930 case PIPE_FORMAT_LATC1_SNORM:
2931 case PIPE_FORMAT_RGTC2_SNORM:
2932 case PIPE_FORMAT_LATC2_SNORM:
2933 case PIPE_FORMAT_ETC2_R11_SNORM:
2934 case PIPE_FORMAT_ETC2_RG11_SNORM:
2935 /* implies float, so use SNORM/UNORM to determine
2936 whether data is signed or not */
2937 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2938 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2939 break;
2940 default:
2941 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2942 break;
2943 }
2944 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2945 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2946 } else {
2947 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2948 }
2949 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2950 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2951 } else {
2952 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2953
2954 switch (desc->channel[first_non_void].type) {
2955 case UTIL_FORMAT_TYPE_FLOAT:
2956 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2957 break;
2958 case UTIL_FORMAT_TYPE_SIGNED:
2959 if (desc->channel[first_non_void].normalized)
2960 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2961 else if (desc->channel[first_non_void].pure_integer)
2962 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2963 else
2964 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2965 break;
2966 case UTIL_FORMAT_TYPE_UNSIGNED:
2967 if (desc->channel[first_non_void].normalized)
2968 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2969 else if (desc->channel[first_non_void].pure_integer)
2970 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2971 else
2972 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2973 }
2974 }
2975 }
2976
2977 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2978 if (data_format == ~0) {
2979 data_format = 0;
2980 }
2981
2982 if (!sampler &&
2983 (res->target == PIPE_TEXTURE_CUBE ||
2984 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2985 res->target == PIPE_TEXTURE_3D)) {
2986 /* For the purpose of shader images, treat cube maps and 3D
2987 * textures as 2D arrays. For 3D textures, the address
2988 * calculations for mipmaps are different, so we rely on the
2989 * caller to effectively disable mipmaps.
2990 */
2991 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2992
2993 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2994 } else {
2995 type = si_tex_dim(res->target, target, res->nr_samples);
2996 }
2997
2998 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2999 height = 1;
3000 depth = res->array_size;
3001 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3002 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3003 if (sampler || res->target != PIPE_TEXTURE_3D)
3004 depth = res->array_size;
3005 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3006 depth = res->array_size / 6;
3007
3008 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
3009 va = tex->resource.gpu_address + surflevel[base_level].offset;
3010
3011 state[0] = va >> 8;
3012 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
3013 S_008F14_DATA_FORMAT(data_format) |
3014 S_008F14_NUM_FORMAT(num_format));
3015 state[2] = (S_008F18_WIDTH(width - 1) |
3016 S_008F18_HEIGHT(height - 1));
3017 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3018 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3019 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3020 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3021 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3022 0 : first_level) |
3023 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3024 util_logbase2(res->nr_samples) :
3025 last_level) |
3026 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
3027 S_008F1C_POW2_PAD(res->last_level > 0) |
3028 S_008F1C_TYPE(type));
3029 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
3030 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
3031 S_008F24_LAST_ARRAY(last_layer));
3032
3033 if (tex->dcc_offset) {
3034 unsigned swap = r600_translate_colorswap(pipe_format);
3035
3036 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3037 state[7] = (tex->resource.gpu_address +
3038 tex->dcc_offset +
3039 surflevel[base_level].dcc_offset) >> 8;
3040 } else {
3041 state[6] = 0;
3042 state[7] = 0;
3043 }
3044
3045 /* Initialize the sampler view for FMASK. */
3046 if (tex->fmask.size) {
3047 uint32_t fmask_format;
3048
3049 va = tex->resource.gpu_address + tex->fmask.offset;
3050
3051 switch (res->nr_samples) {
3052 case 2:
3053 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3054 break;
3055 case 4:
3056 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3057 break;
3058 case 8:
3059 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3060 break;
3061 default:
3062 assert(0);
3063 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3064 }
3065
3066 fmask_state[0] = va >> 8;
3067 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3068 S_008F14_DATA_FORMAT(fmask_format) |
3069 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3070 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3071 S_008F18_HEIGHT(height - 1);
3072 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3073 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3074 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3075 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3076 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3077 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3078 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3079 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3080 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3081 S_008F24_LAST_ARRAY(last_layer);
3082 fmask_state[6] = 0;
3083 fmask_state[7] = 0;
3084 }
3085 }
3086
3087 /**
3088 * Create a sampler view.
3089 *
3090 * @param ctx context
3091 * @param texture texture
3092 * @param state sampler view template
3093 * @param width0 width0 override (for compressed textures as int)
3094 * @param height0 height0 override (for compressed textures as int)
3095 * @param force_level set the base address to the level (for compressed textures)
3096 */
3097 struct pipe_sampler_view *
3098 si_create_sampler_view_custom(struct pipe_context *ctx,
3099 struct pipe_resource *texture,
3100 const struct pipe_sampler_view *state,
3101 unsigned width0, unsigned height0,
3102 unsigned force_level)
3103 {
3104 struct si_context *sctx = (struct si_context*)ctx;
3105 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3106 struct r600_texture *tmp = (struct r600_texture*)texture;
3107 unsigned base_level, first_level, last_level;
3108 unsigned char state_swizzle[4];
3109 unsigned height, depth, width;
3110 unsigned last_layer = state->u.tex.last_layer;
3111
3112 if (!view)
3113 return NULL;
3114
3115 /* initialize base object */
3116 view->base = *state;
3117 view->base.texture = NULL;
3118 view->base.reference.count = 1;
3119 view->base.context = ctx;
3120
3121 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3122 if (!texture) {
3123 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3124 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3125 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3126 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3127 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3128 return &view->base;
3129 }
3130
3131 pipe_resource_reference(&view->base.texture, texture);
3132
3133 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3134 state->format == PIPE_FORMAT_S8X24_UINT ||
3135 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3136 state->format == PIPE_FORMAT_S8_UINT)
3137 view->is_stencil_sampler = true;
3138
3139 /* Buffer resource. */
3140 if (texture->target == PIPE_BUFFER) {
3141 si_make_buffer_descriptor(sctx->screen,
3142 (struct r600_resource *)texture,
3143 state->format,
3144 state->u.buf.first_element,
3145 state->u.buf.last_element,
3146 view->state);
3147
3148 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3149 return &view->base;
3150 }
3151
3152 state_swizzle[0] = state->swizzle_r;
3153 state_swizzle[1] = state->swizzle_g;
3154 state_swizzle[2] = state->swizzle_b;
3155 state_swizzle[3] = state->swizzle_a;
3156
3157 base_level = 0;
3158 first_level = state->u.tex.first_level;
3159 last_level = state->u.tex.last_level;
3160 width = width0;
3161 height = height0;
3162 depth = texture->depth0;
3163
3164 if (force_level) {
3165 assert(force_level == first_level &&
3166 force_level == last_level);
3167 base_level = force_level;
3168 first_level = 0;
3169 last_level = 0;
3170 width = u_minify(width, force_level);
3171 height = u_minify(height, force_level);
3172 depth = u_minify(depth, force_level);
3173 }
3174
3175 /* This is not needed if state trackers set last_layer correctly. */
3176 if (state->target == PIPE_TEXTURE_1D ||
3177 state->target == PIPE_TEXTURE_2D ||
3178 state->target == PIPE_TEXTURE_RECT ||
3179 state->target == PIPE_TEXTURE_CUBE)
3180 last_layer = state->u.tex.first_layer;
3181
3182 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3183 state->format, state_swizzle,
3184 base_level, first_level, last_level,
3185 state->u.tex.first_layer, last_layer,
3186 width, height, depth,
3187 view->state, view->fmask_state);
3188
3189 return &view->base;
3190 }
3191
3192 static struct pipe_sampler_view *
3193 si_create_sampler_view(struct pipe_context *ctx,
3194 struct pipe_resource *texture,
3195 const struct pipe_sampler_view *state)
3196 {
3197 return si_create_sampler_view_custom(ctx, texture, state,
3198 texture ? texture->width0 : 0,
3199 texture ? texture->height0 : 0, 0);
3200 }
3201
3202 static void si_sampler_view_destroy(struct pipe_context *ctx,
3203 struct pipe_sampler_view *state)
3204 {
3205 struct si_sampler_view *view = (struct si_sampler_view *)state;
3206
3207 if (state->texture && state->texture->target == PIPE_BUFFER)
3208 LIST_DELINIT(&view->list);
3209
3210 pipe_resource_reference(&state->texture, NULL);
3211 FREE(view);
3212 }
3213
3214 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3215 {
3216 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3217 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3218 (linear_filter &&
3219 (wrap == PIPE_TEX_WRAP_CLAMP ||
3220 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3221 }
3222
3223 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3224 {
3225 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3226 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3227
3228 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3229 state->border_color.ui[2] || state->border_color.ui[3]) &&
3230 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3231 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3232 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3233 }
3234
3235 static void *si_create_sampler_state(struct pipe_context *ctx,
3236 const struct pipe_sampler_state *state)
3237 {
3238 struct si_context *sctx = (struct si_context *)ctx;
3239 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3240 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
3241 unsigned border_color_type, border_color_index = 0;
3242
3243 if (!rstate) {
3244 return NULL;
3245 }
3246
3247 if (!sampler_state_needs_border_color(state))
3248 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3249 else if (state->border_color.f[0] == 0 &&
3250 state->border_color.f[1] == 0 &&
3251 state->border_color.f[2] == 0 &&
3252 state->border_color.f[3] == 0)
3253 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3254 else if (state->border_color.f[0] == 0 &&
3255 state->border_color.f[1] == 0 &&
3256 state->border_color.f[2] == 0 &&
3257 state->border_color.f[3] == 1)
3258 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3259 else if (state->border_color.f[0] == 1 &&
3260 state->border_color.f[1] == 1 &&
3261 state->border_color.f[2] == 1 &&
3262 state->border_color.f[3] == 1)
3263 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3264 else {
3265 int i;
3266
3267 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3268
3269 /* Check if the border has been uploaded already. */
3270 for (i = 0; i < sctx->border_color_count; i++)
3271 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3272 sizeof(state->border_color)) == 0)
3273 break;
3274
3275 if (i >= SI_MAX_BORDER_COLORS) {
3276 /* Getting 4096 unique border colors is very unlikely. */
3277 fprintf(stderr, "radeonsi: The border color table is full. "
3278 "Any new border colors will be just black. "
3279 "Please file a bug.\n");
3280 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3281 } else {
3282 if (i == sctx->border_color_count) {
3283 /* Upload a new border color. */
3284 memcpy(&sctx->border_color_table[i], &state->border_color,
3285 sizeof(state->border_color));
3286 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3287 &state->border_color,
3288 sizeof(state->border_color));
3289 sctx->border_color_count++;
3290 }
3291
3292 border_color_index = i;
3293 }
3294 }
3295
3296 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3297 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3298 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3299 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
3300 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3301 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3302 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
3303 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3304 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3305 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3306 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
3307 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
3308 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
3309 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3310 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3311 return rstate;
3312 }
3313
3314 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3315 {
3316 struct si_context *sctx = (struct si_context *)ctx;
3317
3318 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3319 return;
3320
3321 sctx->sample_mask.sample_mask = sample_mask;
3322 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3323 }
3324
3325 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3326 {
3327 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3328 unsigned mask = sctx->sample_mask.sample_mask;
3329
3330 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3331 radeon_emit(cs, mask | (mask << 16));
3332 radeon_emit(cs, mask | (mask << 16));
3333 }
3334
3335 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3336 {
3337 free(state);
3338 }
3339
3340 /*
3341 * Vertex elements & buffers
3342 */
3343
3344 static void *si_create_vertex_elements(struct pipe_context *ctx,
3345 unsigned count,
3346 const struct pipe_vertex_element *elements)
3347 {
3348 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3349 int i;
3350
3351 assert(count < SI_MAX_ATTRIBS);
3352 if (!v)
3353 return NULL;
3354
3355 v->count = count;
3356 for (i = 0; i < count; ++i) {
3357 const struct util_format_description *desc;
3358 unsigned data_format, num_format;
3359 int first_non_void;
3360
3361 desc = util_format_description(elements[i].src_format);
3362 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3363 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3364 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3365
3366 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3367 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3368 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3369 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3370 S_008F0C_NUM_FORMAT(num_format) |
3371 S_008F0C_DATA_FORMAT(data_format);
3372 v->format_size[i] = desc->block.bits / 8;
3373 }
3374 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3375
3376 return v;
3377 }
3378
3379 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3380 {
3381 struct si_context *sctx = (struct si_context *)ctx;
3382 struct si_vertex_element *v = (struct si_vertex_element*)state;
3383
3384 sctx->vertex_elements = v;
3385 sctx->vertex_buffers_dirty = true;
3386 }
3387
3388 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3389 {
3390 struct si_context *sctx = (struct si_context *)ctx;
3391
3392 if (sctx->vertex_elements == state)
3393 sctx->vertex_elements = NULL;
3394 FREE(state);
3395 }
3396
3397 static void si_set_vertex_buffers(struct pipe_context *ctx,
3398 unsigned start_slot, unsigned count,
3399 const struct pipe_vertex_buffer *buffers)
3400 {
3401 struct si_context *sctx = (struct si_context *)ctx;
3402 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3403 int i;
3404
3405 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3406
3407 if (buffers) {
3408 for (i = 0; i < count; i++) {
3409 const struct pipe_vertex_buffer *src = buffers + i;
3410 struct pipe_vertex_buffer *dsti = dst + i;
3411
3412 pipe_resource_reference(&dsti->buffer, src->buffer);
3413 dsti->buffer_offset = src->buffer_offset;
3414 dsti->stride = src->stride;
3415 r600_context_add_resource_size(ctx, src->buffer);
3416 }
3417 } else {
3418 for (i = 0; i < count; i++) {
3419 pipe_resource_reference(&dst[i].buffer, NULL);
3420 }
3421 }
3422 sctx->vertex_buffers_dirty = true;
3423 }
3424
3425 static void si_set_index_buffer(struct pipe_context *ctx,
3426 const struct pipe_index_buffer *ib)
3427 {
3428 struct si_context *sctx = (struct si_context *)ctx;
3429
3430 if (ib) {
3431 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3432 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3433 r600_context_add_resource_size(ctx, ib->buffer);
3434 } else {
3435 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3436 }
3437 }
3438
3439 /*
3440 * Misc
3441 */
3442 static void si_set_polygon_stipple(struct pipe_context *ctx,
3443 const struct pipe_poly_stipple *state)
3444 {
3445 struct si_context *sctx = (struct si_context *)ctx;
3446 struct pipe_resource *tex;
3447 struct pipe_sampler_view *view;
3448 bool is_zero = true;
3449 bool is_one = true;
3450 int i;
3451
3452 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3453 * the resource is NULL/invalid. Take advantage of this fact and skip
3454 * texture allocation if the stipple pattern is constant.
3455 *
3456 * This is an optimization for the common case when stippling isn't
3457 * used but set_polygon_stipple is still called by st/mesa.
3458 */
3459 for (i = 0; i < Elements(state->stipple); i++) {
3460 is_zero = is_zero && state->stipple[i] == 0;
3461 is_one = is_one && state->stipple[i] == 0xffffffff;
3462 }
3463
3464 if (is_zero || is_one) {
3465 struct pipe_sampler_view templ = {{0}};
3466
3467 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3468 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3469 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3470 /* The pattern should be inverted in the texture. */
3471 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3472
3473 view = ctx->create_sampler_view(ctx, NULL, &templ);
3474 } else {
3475 /* Create a new texture. */
3476 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3477 if (!tex)
3478 return;
3479
3480 view = util_pstipple_create_sampler_view(ctx, tex);
3481 pipe_resource_reference(&tex, NULL);
3482 }
3483
3484 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3485 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3486 pipe_sampler_view_reference(&view, NULL);
3487
3488 /* Bind the sampler state if needed. */
3489 if (!sctx->pstipple_sampler_state) {
3490 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3491 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3492 SI_POLY_STIPPLE_SAMPLER, 1,
3493 &sctx->pstipple_sampler_state);
3494 }
3495 }
3496
3497 static void si_set_tess_state(struct pipe_context *ctx,
3498 const float default_outer_level[4],
3499 const float default_inner_level[2])
3500 {
3501 struct si_context *sctx = (struct si_context *)ctx;
3502 struct pipe_constant_buffer cb;
3503 float array[8];
3504
3505 memcpy(array, default_outer_level, sizeof(float) * 4);
3506 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3507
3508 cb.buffer = NULL;
3509 cb.user_buffer = NULL;
3510 cb.buffer_size = sizeof(array);
3511
3512 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3513 (void*)array, sizeof(array),
3514 &cb.buffer_offset);
3515
3516 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3517 SI_DRIVER_STATE_CONST_BUF, &cb);
3518 pipe_resource_reference(&cb.buffer, NULL);
3519 }
3520
3521 static void si_texture_barrier(struct pipe_context *ctx)
3522 {
3523 struct si_context *sctx = (struct si_context *)ctx;
3524
3525 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3526 SI_CONTEXT_INV_GLOBAL_L2 |
3527 SI_CONTEXT_FLUSH_AND_INV_CB;
3528 }
3529
3530 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3531 {
3532 struct si_context *sctx = (struct si_context *)ctx;
3533
3534 /* Subsequent commands must wait for all shader invocations to
3535 * complete. */
3536 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
3537
3538 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3539 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3540 SI_CONTEXT_INV_VMEM_L1;
3541
3542 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3543 PIPE_BARRIER_SHADER_BUFFER |
3544 PIPE_BARRIER_TEXTURE |
3545 PIPE_BARRIER_IMAGE |
3546 PIPE_BARRIER_STREAMOUT_BUFFER)) {
3547 /* As far as I can tell, L1 contents are written back to L2
3548 * automatically at end of shader, but the contents of other
3549 * L1 caches might still be stale. */
3550 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3551 }
3552
3553 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3554 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3555
3556 /* Indices are read through TC L2 since VI. */
3557 if (sctx->screen->b.chip_class <= CIK)
3558 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3559 }
3560
3561 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3562 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3563
3564 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3565 PIPE_BARRIER_FRAMEBUFFER |
3566 PIPE_BARRIER_INDIRECT_BUFFER)) {
3567 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3568 *
3569 * We need to make sure that TC L1 & L2 are written back to
3570 * memory, because neither CPU accesses nor CB fetches consider
3571 * TC, but there's no need to invalidate any TC cache lines. */
3572 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3573 }
3574 }
3575
3576 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3577 {
3578 struct pipe_blend_state blend;
3579
3580 memset(&blend, 0, sizeof(blend));
3581 blend.independent_blend_enable = true;
3582 blend.rt[0].colormask = 0xf;
3583 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3584 }
3585
3586 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3587 bool include_draw_vbo)
3588 {
3589 si_need_cs_space((struct si_context*)ctx);
3590 }
3591
3592 static void si_init_config(struct si_context *sctx);
3593
3594 void si_init_state_functions(struct si_context *sctx)
3595 {
3596 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3597 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3598 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3599
3600 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3601 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3602 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3603 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3604 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3605 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3606 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3607 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3608 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3609 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3610 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3611 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3612 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3613
3614 sctx->b.b.create_blend_state = si_create_blend_state;
3615 sctx->b.b.bind_blend_state = si_bind_blend_state;
3616 sctx->b.b.delete_blend_state = si_delete_blend_state;
3617 sctx->b.b.set_blend_color = si_set_blend_color;
3618
3619 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3620 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3621 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3622
3623 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3624 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3625 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3626
3627 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3628 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3629 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3630 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3631 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3632
3633 sctx->b.b.set_clip_state = si_set_clip_state;
3634 sctx->b.b.set_scissor_states = si_set_scissor_states;
3635 sctx->b.b.set_viewport_states = si_set_viewport_states;
3636 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3637
3638 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3639 sctx->b.b.get_sample_position = cayman_get_sample_position;
3640
3641 sctx->b.b.create_sampler_state = si_create_sampler_state;
3642 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3643
3644 sctx->b.b.create_sampler_view = si_create_sampler_view;
3645 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3646
3647 sctx->b.b.set_sample_mask = si_set_sample_mask;
3648
3649 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3650 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3651 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3652 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3653 sctx->b.b.set_index_buffer = si_set_index_buffer;
3654
3655 sctx->b.b.texture_barrier = si_texture_barrier;
3656 sctx->b.b.memory_barrier = si_memory_barrier;
3657 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3658 sctx->b.b.set_min_samples = si_set_min_samples;
3659 sctx->b.b.set_tess_state = si_set_tess_state;
3660
3661 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3662 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3663
3664 sctx->b.b.draw_vbo = si_draw_vbo;
3665
3666 if (sctx->b.chip_class >= CIK) {
3667 sctx->b.dma_copy = cik_sdma_copy;
3668 } else {
3669 sctx->b.dma_copy = si_dma_copy;
3670 }
3671
3672 si_init_config(sctx);
3673 }
3674
3675 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3676 struct r600_texture *rtex,
3677 struct radeon_bo_metadata *md)
3678 {
3679 struct si_screen *sscreen = (struct si_screen*)rscreen;
3680 struct pipe_resource *res = &rtex->resource.b.b;
3681 static const unsigned char swizzle[] = {
3682 PIPE_SWIZZLE_RED,
3683 PIPE_SWIZZLE_GREEN,
3684 PIPE_SWIZZLE_BLUE,
3685 PIPE_SWIZZLE_ALPHA
3686 };
3687 uint32_t desc[8], i;
3688 bool is_array = util_resource_is_array_texture(res);
3689
3690 /* DRM 2.x.x doesn't support this. */
3691 if (rscreen->info.drm_major != 3)
3692 return;
3693
3694 assert(rtex->fmask.size == 0);
3695
3696 /* Metadata image format format version 1:
3697 * [0] = 1 (metadata format identifier)
3698 * [1] = (VENDOR_ID << 16) | PCI_ID
3699 * [2:9] = image descriptor for the whole resource
3700 * [2] is always 0, because the base address is cleared
3701 * [9] is the DCC offset bits [39:8] from the beginning of
3702 * the buffer
3703 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3704 */
3705
3706 md->metadata[0] = 1; /* metadata image format version 1 */
3707
3708 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3709 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3710
3711 si_make_texture_descriptor(sscreen, rtex, true,
3712 res->target, res->format,
3713 swizzle, 0, 0, res->last_level, 0,
3714 is_array ? res->array_size - 1 : 0,
3715 res->width0, res->height0, res->depth0,
3716 desc, NULL);
3717
3718 /* Clear the base address and set the relative DCC offset. */
3719 desc[0] = 0;
3720 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3721 desc[7] = rtex->dcc_offset >> 8;
3722
3723 /* Dwords [2:9] contain the image descriptor. */
3724 memcpy(&md->metadata[2], desc, sizeof(desc));
3725
3726 /* Dwords [10:..] contain the mipmap level offsets. */
3727 for (i = 0; i <= res->last_level; i++)
3728 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3729
3730 md->size_metadata = (11 + res->last_level) * 4;
3731 }
3732
3733 void si_init_screen_state_functions(struct si_screen *sscreen)
3734 {
3735 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3736 }
3737
3738 static void
3739 si_write_harvested_raster_configs(struct si_context *sctx,
3740 struct si_pm4_state *pm4,
3741 unsigned raster_config,
3742 unsigned raster_config_1)
3743 {
3744 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3745 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3746 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3747 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3748 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3749 unsigned rb_per_se = num_rb / num_se;
3750 unsigned se_mask[4];
3751 unsigned se;
3752
3753 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3754 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3755 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3756 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3757
3758 assert(num_se == 1 || num_se == 2 || num_se == 4);
3759 assert(sh_per_se == 1 || sh_per_se == 2);
3760 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3761
3762 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3763 * fields are for, so I'm leaving them as their default
3764 * values. */
3765
3766 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3767 (!se_mask[2] && !se_mask[3]))) {
3768 raster_config_1 &= C_028354_SE_PAIR_MAP;
3769
3770 if (!se_mask[0] && !se_mask[1]) {
3771 raster_config_1 |=
3772 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3773 } else {
3774 raster_config_1 |=
3775 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3776 }
3777 }
3778
3779 for (se = 0; se < num_se; se++) {
3780 unsigned raster_config_se = raster_config;
3781 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3782 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3783 int idx = (se / 2) * 2;
3784
3785 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3786 raster_config_se &= C_028350_SE_MAP;
3787
3788 if (!se_mask[idx]) {
3789 raster_config_se |=
3790 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3791 } else {
3792 raster_config_se |=
3793 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3794 }
3795 }
3796
3797 pkr0_mask &= rb_mask;
3798 pkr1_mask &= rb_mask;
3799 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3800 raster_config_se &= C_028350_PKR_MAP;
3801
3802 if (!pkr0_mask) {
3803 raster_config_se |=
3804 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3805 } else {
3806 raster_config_se |=
3807 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3808 }
3809 }
3810
3811 if (rb_per_se >= 2) {
3812 unsigned rb0_mask = 1 << (se * rb_per_se);
3813 unsigned rb1_mask = rb0_mask << 1;
3814
3815 rb0_mask &= rb_mask;
3816 rb1_mask &= rb_mask;
3817 if (!rb0_mask || !rb1_mask) {
3818 raster_config_se &= C_028350_RB_MAP_PKR0;
3819
3820 if (!rb0_mask) {
3821 raster_config_se |=
3822 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3823 } else {
3824 raster_config_se |=
3825 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3826 }
3827 }
3828
3829 if (rb_per_se > 2) {
3830 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3831 rb1_mask = rb0_mask << 1;
3832 rb0_mask &= rb_mask;
3833 rb1_mask &= rb_mask;
3834 if (!rb0_mask || !rb1_mask) {
3835 raster_config_se &= C_028350_RB_MAP_PKR1;
3836
3837 if (!rb0_mask) {
3838 raster_config_se |=
3839 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3840 } else {
3841 raster_config_se |=
3842 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3843 }
3844 }
3845 }
3846 }
3847
3848 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3849 if (sctx->b.chip_class < CIK)
3850 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3851 SE_INDEX(se) | SH_BROADCAST_WRITES |
3852 INSTANCE_BROADCAST_WRITES);
3853 else
3854 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3855 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3856 S_030800_INSTANCE_BROADCAST_WRITES(1));
3857 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3858 if (sctx->b.chip_class >= CIK)
3859 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3860 }
3861
3862 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3863 if (sctx->b.chip_class < CIK)
3864 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3865 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3866 INSTANCE_BROADCAST_WRITES);
3867 else
3868 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3869 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3870 S_030800_INSTANCE_BROADCAST_WRITES(1));
3871 }
3872
3873 static void si_init_config(struct si_context *sctx)
3874 {
3875 struct si_screen *sscreen = sctx->screen;
3876 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3877 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3878 unsigned raster_config, raster_config_1;
3879 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3880 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3881 int i;
3882
3883 if (!pm4)
3884 return;
3885
3886 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3887 si_pm4_cmd_add(pm4, 0x80000000);
3888 si_pm4_cmd_add(pm4, 0x80000000);
3889 si_pm4_cmd_end(pm4, false);
3890
3891 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3892 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3893
3894 /* FIXME calculate these values somehow ??? */
3895 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3896 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3897 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3898
3899 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3900 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3901
3902 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3903 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3904 if (sctx->b.chip_class < CIK)
3905 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3906 S_008A14_CLIP_VTX_REORDER_ENA(1));
3907
3908 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3909 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3910
3911 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3912
3913 for (i = 0; i < 16; i++) {
3914 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3915 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3916 }
3917
3918 switch (sctx->screen->b.family) {
3919 case CHIP_TAHITI:
3920 case CHIP_PITCAIRN:
3921 raster_config = 0x2a00126a;
3922 raster_config_1 = 0x00000000;
3923 break;
3924 case CHIP_VERDE:
3925 raster_config = 0x0000124a;
3926 raster_config_1 = 0x00000000;
3927 break;
3928 case CHIP_OLAND:
3929 raster_config = 0x00000082;
3930 raster_config_1 = 0x00000000;
3931 break;
3932 case CHIP_HAINAN:
3933 raster_config = 0x00000000;
3934 raster_config_1 = 0x00000000;
3935 break;
3936 case CHIP_BONAIRE:
3937 raster_config = 0x16000012;
3938 raster_config_1 = 0x00000000;
3939 break;
3940 case CHIP_HAWAII:
3941 raster_config = 0x3a00161a;
3942 raster_config_1 = 0x0000002e;
3943 break;
3944 case CHIP_FIJI:
3945 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3946 /* old kernels with old tiling config */
3947 raster_config = 0x16000012;
3948 raster_config_1 = 0x0000002a;
3949 } else {
3950 raster_config = 0x3a00161a;
3951 raster_config_1 = 0x0000002e;
3952 }
3953 break;
3954 case CHIP_POLARIS10:
3955 raster_config = 0x16000012;
3956 raster_config_1 = 0x0000002a;
3957 break;
3958 case CHIP_POLARIS11:
3959 raster_config = 0x16000012;
3960 raster_config_1 = 0x00000000;
3961 break;
3962 case CHIP_TONGA:
3963 raster_config = 0x16000012;
3964 raster_config_1 = 0x0000002a;
3965 break;
3966 case CHIP_ICELAND:
3967 raster_config = 0x00000002;
3968 raster_config_1 = 0x00000000;
3969 break;
3970 case CHIP_CARRIZO:
3971 raster_config = 0x00000002;
3972 raster_config_1 = 0x00000000;
3973 break;
3974 case CHIP_KAVERI:
3975 /* KV should be 0x00000002, but that causes problems with radeon */
3976 raster_config = 0x00000000; /* 0x00000002 */
3977 raster_config_1 = 0x00000000;
3978 break;
3979 case CHIP_KABINI:
3980 case CHIP_MULLINS:
3981 case CHIP_STONEY:
3982 raster_config = 0x00000000;
3983 raster_config_1 = 0x00000000;
3984 break;
3985 default:
3986 fprintf(stderr,
3987 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3988 raster_config = 0x00000000;
3989 raster_config_1 = 0x00000000;
3990 break;
3991 }
3992
3993 /* Always use the default config when all backends are enabled
3994 * (or when we failed to determine the enabled backends).
3995 */
3996 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3997 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3998 raster_config);
3999 if (sctx->b.chip_class >= CIK)
4000 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4001 raster_config_1);
4002 } else {
4003 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4004 }
4005
4006 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4007 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4008 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4009 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4010 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4011 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4012 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4013
4014 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4015 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
4016 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4017 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4018 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4019 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
4020 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
4021 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
4022 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
4023 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4024 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4025 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4026 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
4027 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
4028 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
4029
4030 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4031 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4032 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4033
4034 if (sctx->b.chip_class >= CIK) {
4035 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4036 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4037 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4038
4039 if (sscreen->b.info.num_good_compute_units /
4040 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4041 /* Too few available compute units per SH. Disallowing
4042 * VS to run on CU0 could hurt us more than late VS
4043 * allocation would help.
4044 *
4045 * LATE_ALLOC_VS = 2 is the highest safe number.
4046 */
4047 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4048 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4049 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4050 } else {
4051 /* Set LATE_ALLOC_VS == 31. It should be less than
4052 * the number of scratch waves. Limitations:
4053 * - VS can't execute on CU0.
4054 * - If HS writes outputs to LDS, LS can't execute on CU0.
4055 */
4056 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
4057 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4058 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4059 }
4060
4061 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4062 }
4063
4064 if (sctx->b.chip_class >= VI) {
4065 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4066 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4067 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4068 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4069 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4070 }
4071
4072 if (sctx->b.family == CHIP_STONEY)
4073 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4074
4075 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4076 if (sctx->b.chip_class >= CIK)
4077 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4078 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4079 RADEON_PRIO_BORDER_COLORS);
4080
4081 si_pm4_upload_indirect_buffer(sctx, pm4);
4082 sctx->init_config = pm4;
4083 }