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radeon: implement pipe_context::bind_sampler_states()
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528
529 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
530 state->fill_back != PIPE_POLYGON_MODE_FILL);
531
532 if (state->flatshade_first)
533 prov_vtx = 0;
534
535 rs->flatshade = state->flatshade;
536 rs->sprite_coord_enable = state->sprite_coord_enable;
537 rs->pa_sc_line_stipple = state->line_stipple_enable ?
538 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
539 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
540 rs->pa_su_sc_mode_cntl =
541 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
542 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
543 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
548 S_028814_POLY_MODE(polygon_dual_mode) |
549 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
551 rs->pa_cl_clip_cntl =
552 S_028810_PS_UCP_MODE(3) |
553 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
554 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
555 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
556 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
557
558 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
559
560 /* offset */
561 rs->offset_units = state->offset_units;
562 rs->offset_scale = state->offset_scale * 12.0f;
563
564 tmp = S_0286D4_FLAT_SHADE_ENA(1);
565 if (state->sprite_coord_enable) {
566 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
567 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
568 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
569 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
570 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
571 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
572 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
573 }
574 }
575 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
576
577 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
578 /* point size 12.4 fixed point */
579 tmp = (unsigned)(state->point_size * 8.0);
580 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
581
582 if (state->point_size_per_vertex) {
583 psize_min = util_get_min_point_size(state);
584 psize_max = 8192;
585 } else {
586 /* Force the point size to be as if the vertex output was disabled. */
587 psize_min = state->point_size;
588 psize_max = state->point_size;
589 }
590 /* Divide by two, because 0.5 = 1 pixel. */
591 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
592 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
593 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
594
595 tmp = (unsigned)state->line_width * 8;
596 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
597 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
598 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
599 S_028A48_MSAA_ENABLE(state->multisample));
600
601 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
602 S_028BE4_PIX_CENTER(state->half_pixel_center) |
603 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
604 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
605 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
608
609 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
610 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
611
612 return rs;
613 }
614
615 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
616 {
617 struct r600_context *rctx = (struct r600_context *)ctx;
618 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
619
620 if (state == NULL)
621 return;
622
623 // TODO
624 rctx->sprite_coord_enable = rs->sprite_coord_enable;
625 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
626 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
627
628 si_pm4_bind_state(rctx, rasterizer, rs);
629 si_update_fb_rs_state(rctx);
630 }
631
632 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
633 {
634 struct r600_context *rctx = (struct r600_context *)ctx;
635 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
636 }
637
638 /*
639 * infeered state between dsa and stencil ref
640 */
641 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
642 {
643 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
644 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
645 struct si_state_dsa *dsa = rctx->queued.named.dsa;
646
647 if (pm4 == NULL)
648 return;
649
650 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
651 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
652 S_028430_STENCILMASK(dsa->valuemask[0]) |
653 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
654 S_028430_STENCILOPVAL(1));
655 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
656 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
657 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
658 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
659 S_028434_STENCILOPVAL_BF(1));
660
661 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
662 }
663
664 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
665 const struct pipe_stencil_ref *state)
666 {
667 struct r600_context *rctx = (struct r600_context *)ctx;
668 rctx->stencil_ref = *state;
669 si_update_dsa_stencil_ref(rctx);
670 }
671
672
673 /*
674 * DSA
675 */
676
677 static uint32_t si_translate_stencil_op(int s_op)
678 {
679 switch (s_op) {
680 case PIPE_STENCIL_OP_KEEP:
681 return V_02842C_STENCIL_KEEP;
682 case PIPE_STENCIL_OP_ZERO:
683 return V_02842C_STENCIL_ZERO;
684 case PIPE_STENCIL_OP_REPLACE:
685 return V_02842C_STENCIL_REPLACE_TEST;
686 case PIPE_STENCIL_OP_INCR:
687 return V_02842C_STENCIL_ADD_CLAMP;
688 case PIPE_STENCIL_OP_DECR:
689 return V_02842C_STENCIL_SUB_CLAMP;
690 case PIPE_STENCIL_OP_INCR_WRAP:
691 return V_02842C_STENCIL_ADD_WRAP;
692 case PIPE_STENCIL_OP_DECR_WRAP:
693 return V_02842C_STENCIL_SUB_WRAP;
694 case PIPE_STENCIL_OP_INVERT:
695 return V_02842C_STENCIL_INVERT;
696 default:
697 R600_ERR("Unknown stencil op %d", s_op);
698 assert(0);
699 break;
700 }
701 return 0;
702 }
703
704 static void *si_create_dsa_state(struct pipe_context *ctx,
705 const struct pipe_depth_stencil_alpha_state *state)
706 {
707 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
708 struct si_pm4_state *pm4 = &dsa->pm4;
709 unsigned db_depth_control;
710 unsigned db_render_override, db_render_control;
711 uint32_t db_stencil_control = 0;
712
713 if (dsa == NULL) {
714 return NULL;
715 }
716
717 dsa->valuemask[0] = state->stencil[0].valuemask;
718 dsa->valuemask[1] = state->stencil[1].valuemask;
719 dsa->writemask[0] = state->stencil[0].writemask;
720 dsa->writemask[1] = state->stencil[1].writemask;
721
722 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
723 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
724 S_028800_ZFUNC(state->depth.func);
725
726 /* stencil */
727 if (state->stencil[0].enabled) {
728 db_depth_control |= S_028800_STENCIL_ENABLE(1);
729 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
730 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
731 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
732 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
733
734 if (state->stencil[1].enabled) {
735 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
736 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
737 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
738 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
739 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
740 }
741 }
742
743 /* alpha */
744 if (state->alpha.enabled) {
745 dsa->alpha_func = state->alpha.func;
746 dsa->alpha_ref = state->alpha.ref_value;
747 } else {
748 dsa->alpha_func = PIPE_FUNC_ALWAYS;
749 }
750
751 /* misc */
752 db_render_control = 0;
753 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
754 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
755 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
756 /* TODO db_render_override depends on query */
757 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
758 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
759 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
760 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
761 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
762 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
763 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
764 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
765 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
766 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
767 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
768 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
769 dsa->db_render_override = db_render_override;
770
771 return dsa;
772 }
773
774 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
775 {
776 struct r600_context *rctx = (struct r600_context *)ctx;
777 struct si_state_dsa *dsa = state;
778
779 if (state == NULL)
780 return;
781
782 si_pm4_bind_state(rctx, dsa, dsa);
783 si_update_dsa_stencil_ref(rctx);
784 }
785
786 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
787 {
788 struct r600_context *rctx = (struct r600_context *)ctx;
789 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
790 }
791
792 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
793 bool copy_stencil, int sample)
794 {
795 struct pipe_depth_stencil_alpha_state dsa;
796 struct si_state_dsa *state;
797
798 memset(&dsa, 0, sizeof(dsa));
799
800 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
801 if (copy_depth || copy_stencil) {
802 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
803 S_028000_DEPTH_COPY(copy_depth) |
804 S_028000_STENCIL_COPY(copy_stencil) |
805 S_028000_COPY_CENTROID(1) |
806 S_028000_COPY_SAMPLE(sample));
807 } else {
808 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
809 S_028000_DEPTH_COMPRESS_DISABLE(1) |
810 S_028000_STENCIL_COMPRESS_DISABLE(1));
811 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
812 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
813 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
814 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
815 S_02800C_DISABLE_TILE_RATE_TILES(1));
816 }
817
818 return state;
819 }
820
821 /*
822 * format translation
823 */
824 static uint32_t si_translate_colorformat(enum pipe_format format)
825 {
826 const struct util_format_description *desc = util_format_description(format);
827
828 #define HAS_SIZE(x,y,z,w) \
829 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
830 desc->channel[2].size == (z) && desc->channel[3].size == (w))
831
832 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
833 return V_028C70_COLOR_10_11_11;
834
835 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
836 return V_028C70_COLOR_INVALID;
837
838 switch (desc->nr_channels) {
839 case 1:
840 switch (desc->channel[0].size) {
841 case 8:
842 return V_028C70_COLOR_8;
843 case 16:
844 return V_028C70_COLOR_16;
845 case 32:
846 return V_028C70_COLOR_32;
847 }
848 break;
849 case 2:
850 if (desc->channel[0].size == desc->channel[1].size) {
851 switch (desc->channel[0].size) {
852 case 8:
853 return V_028C70_COLOR_8_8;
854 case 16:
855 return V_028C70_COLOR_16_16;
856 case 32:
857 return V_028C70_COLOR_32_32;
858 }
859 } else if (HAS_SIZE(8,24,0,0)) {
860 return V_028C70_COLOR_24_8;
861 } else if (HAS_SIZE(24,8,0,0)) {
862 return V_028C70_COLOR_8_24;
863 }
864 break;
865 case 3:
866 if (HAS_SIZE(5,6,5,0)) {
867 return V_028C70_COLOR_5_6_5;
868 } else if (HAS_SIZE(32,8,24,0)) {
869 return V_028C70_COLOR_X24_8_32_FLOAT;
870 }
871 break;
872 case 4:
873 if (desc->channel[0].size == desc->channel[1].size &&
874 desc->channel[0].size == desc->channel[2].size &&
875 desc->channel[0].size == desc->channel[3].size) {
876 switch (desc->channel[0].size) {
877 case 4:
878 return V_028C70_COLOR_4_4_4_4;
879 case 8:
880 return V_028C70_COLOR_8_8_8_8;
881 case 16:
882 return V_028C70_COLOR_16_16_16_16;
883 case 32:
884 return V_028C70_COLOR_32_32_32_32;
885 }
886 } else if (HAS_SIZE(5,5,5,1)) {
887 return V_028C70_COLOR_1_5_5_5;
888 } else if (HAS_SIZE(10,10,10,2)) {
889 return V_028C70_COLOR_2_10_10_10;
890 }
891 break;
892 }
893 return V_028C70_COLOR_INVALID;
894 }
895
896 static uint32_t si_translate_colorswap(enum pipe_format format)
897 {
898 const struct util_format_description *desc = util_format_description(format);
899
900 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
901
902 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
903 return V_028C70_SWAP_STD;
904
905 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
906 return ~0;
907
908 switch (desc->nr_channels) {
909 case 1:
910 if (HAS_SWIZZLE(0,X))
911 return V_028C70_SWAP_STD; /* X___ */
912 else if (HAS_SWIZZLE(3,X))
913 return V_028C70_SWAP_ALT_REV; /* ___X */
914 break;
915 case 2:
916 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
917 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
918 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
919 return V_028C70_SWAP_STD; /* XY__ */
920 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
921 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
922 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
923 return V_028C70_SWAP_STD_REV; /* YX__ */
924 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
925 return V_028C70_SWAP_ALT; /* X__Y */
926 break;
927 case 3:
928 if (HAS_SWIZZLE(0,X))
929 return V_028C70_SWAP_STD; /* XYZ */
930 else if (HAS_SWIZZLE(0,Z))
931 return V_028C70_SWAP_STD_REV; /* ZYX */
932 break;
933 case 4:
934 /* check the middle channels, the 1st and 4th channel can be NONE */
935 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
936 return V_028C70_SWAP_STD; /* XYZW */
937 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
938 return V_028C70_SWAP_STD_REV; /* WZYX */
939 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
940 return V_028C70_SWAP_ALT; /* ZYXW */
941 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
942 return V_028C70_SWAP_ALT_REV; /* WXYZ */
943 break;
944 }
945 return ~0U;
946 }
947
948 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
949 {
950 if (R600_BIG_ENDIAN) {
951 switch(colorformat) {
952 /* 8-bit buffers. */
953 case V_028C70_COLOR_8:
954 return V_028C70_ENDIAN_NONE;
955
956 /* 16-bit buffers. */
957 case V_028C70_COLOR_5_6_5:
958 case V_028C70_COLOR_1_5_5_5:
959 case V_028C70_COLOR_4_4_4_4:
960 case V_028C70_COLOR_16:
961 case V_028C70_COLOR_8_8:
962 return V_028C70_ENDIAN_8IN16;
963
964 /* 32-bit buffers. */
965 case V_028C70_COLOR_8_8_8_8:
966 case V_028C70_COLOR_2_10_10_10:
967 case V_028C70_COLOR_8_24:
968 case V_028C70_COLOR_24_8:
969 case V_028C70_COLOR_16_16:
970 return V_028C70_ENDIAN_8IN32;
971
972 /* 64-bit buffers. */
973 case V_028C70_COLOR_16_16_16_16:
974 return V_028C70_ENDIAN_8IN16;
975
976 case V_028C70_COLOR_32_32:
977 return V_028C70_ENDIAN_8IN32;
978
979 /* 128-bit buffers. */
980 case V_028C70_COLOR_32_32_32_32:
981 return V_028C70_ENDIAN_8IN32;
982 default:
983 return V_028C70_ENDIAN_NONE; /* Unsupported. */
984 }
985 } else {
986 return V_028C70_ENDIAN_NONE;
987 }
988 }
989
990 /* Returns the size in bits of the widest component of a CB format */
991 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
992 {
993 switch(colorformat) {
994 case V_028C70_COLOR_4_4_4_4:
995 return 4;
996
997 case V_028C70_COLOR_1_5_5_5:
998 case V_028C70_COLOR_5_5_5_1:
999 return 5;
1000
1001 case V_028C70_COLOR_5_6_5:
1002 return 6;
1003
1004 case V_028C70_COLOR_8:
1005 case V_028C70_COLOR_8_8:
1006 case V_028C70_COLOR_8_8_8_8:
1007 return 8;
1008
1009 case V_028C70_COLOR_10_10_10_2:
1010 case V_028C70_COLOR_2_10_10_10:
1011 return 10;
1012
1013 case V_028C70_COLOR_10_11_11:
1014 case V_028C70_COLOR_11_11_10:
1015 return 11;
1016
1017 case V_028C70_COLOR_16:
1018 case V_028C70_COLOR_16_16:
1019 case V_028C70_COLOR_16_16_16_16:
1020 return 16;
1021
1022 case V_028C70_COLOR_8_24:
1023 case V_028C70_COLOR_24_8:
1024 return 24;
1025
1026 case V_028C70_COLOR_32:
1027 case V_028C70_COLOR_32_32:
1028 case V_028C70_COLOR_32_32_32_32:
1029 case V_028C70_COLOR_X24_8_32_FLOAT:
1030 return 32;
1031 }
1032
1033 assert(!"Unknown maximum component size");
1034 return 0;
1035 }
1036
1037 static uint32_t si_translate_dbformat(enum pipe_format format)
1038 {
1039 switch (format) {
1040 case PIPE_FORMAT_Z16_UNORM:
1041 return V_028040_Z_16;
1042 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1043 case PIPE_FORMAT_X8Z24_UNORM:
1044 case PIPE_FORMAT_Z24X8_UNORM:
1045 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1046 return V_028040_Z_24; /* deprecated on SI */
1047 case PIPE_FORMAT_Z32_FLOAT:
1048 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1049 return V_028040_Z_32_FLOAT;
1050 default:
1051 return V_028040_Z_INVALID;
1052 }
1053 }
1054
1055 /*
1056 * Texture translation
1057 */
1058
1059 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1060 enum pipe_format format,
1061 const struct util_format_description *desc,
1062 int first_non_void)
1063 {
1064 struct r600_screen *rscreen = (struct r600_screen*)screen;
1065 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1066 boolean uniform = TRUE;
1067 int i;
1068
1069 /* Colorspace (return non-RGB formats directly). */
1070 switch (desc->colorspace) {
1071 /* Depth stencil formats */
1072 case UTIL_FORMAT_COLORSPACE_ZS:
1073 switch (format) {
1074 case PIPE_FORMAT_Z16_UNORM:
1075 return V_008F14_IMG_DATA_FORMAT_16;
1076 case PIPE_FORMAT_X24S8_UINT:
1077 case PIPE_FORMAT_Z24X8_UNORM:
1078 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1079 return V_008F14_IMG_DATA_FORMAT_8_24;
1080 case PIPE_FORMAT_X8Z24_UNORM:
1081 case PIPE_FORMAT_S8X24_UINT:
1082 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1083 return V_008F14_IMG_DATA_FORMAT_24_8;
1084 case PIPE_FORMAT_S8_UINT:
1085 return V_008F14_IMG_DATA_FORMAT_8;
1086 case PIPE_FORMAT_Z32_FLOAT:
1087 return V_008F14_IMG_DATA_FORMAT_32;
1088 case PIPE_FORMAT_X32_S8X24_UINT:
1089 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1090 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1091 default:
1092 goto out_unknown;
1093 }
1094
1095 case UTIL_FORMAT_COLORSPACE_YUV:
1096 goto out_unknown; /* TODO */
1097
1098 case UTIL_FORMAT_COLORSPACE_SRGB:
1099 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1100 goto out_unknown;
1101 break;
1102
1103 default:
1104 break;
1105 }
1106
1107 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1108 if (!enable_s3tc)
1109 goto out_unknown;
1110
1111 switch (format) {
1112 case PIPE_FORMAT_RGTC1_SNORM:
1113 case PIPE_FORMAT_LATC1_SNORM:
1114 case PIPE_FORMAT_RGTC1_UNORM:
1115 case PIPE_FORMAT_LATC1_UNORM:
1116 return V_008F14_IMG_DATA_FORMAT_BC4;
1117 case PIPE_FORMAT_RGTC2_SNORM:
1118 case PIPE_FORMAT_LATC2_SNORM:
1119 case PIPE_FORMAT_RGTC2_UNORM:
1120 case PIPE_FORMAT_LATC2_UNORM:
1121 return V_008F14_IMG_DATA_FORMAT_BC5;
1122 default:
1123 goto out_unknown;
1124 }
1125 }
1126
1127 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1128
1129 if (!enable_s3tc)
1130 goto out_unknown;
1131
1132 if (!util_format_s3tc_enabled) {
1133 goto out_unknown;
1134 }
1135
1136 switch (format) {
1137 case PIPE_FORMAT_DXT1_RGB:
1138 case PIPE_FORMAT_DXT1_RGBA:
1139 case PIPE_FORMAT_DXT1_SRGB:
1140 case PIPE_FORMAT_DXT1_SRGBA:
1141 return V_008F14_IMG_DATA_FORMAT_BC1;
1142 case PIPE_FORMAT_DXT3_RGBA:
1143 case PIPE_FORMAT_DXT3_SRGBA:
1144 return V_008F14_IMG_DATA_FORMAT_BC2;
1145 case PIPE_FORMAT_DXT5_RGBA:
1146 case PIPE_FORMAT_DXT5_SRGBA:
1147 return V_008F14_IMG_DATA_FORMAT_BC3;
1148 default:
1149 goto out_unknown;
1150 }
1151 }
1152
1153 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1154 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1155 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1156 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1157 }
1158
1159 /* R8G8Bx_SNORM - TODO CxV8U8 */
1160
1161 /* See whether the components are of the same size. */
1162 for (i = 1; i < desc->nr_channels; i++) {
1163 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1164 }
1165
1166 /* Non-uniform formats. */
1167 if (!uniform) {
1168 switch(desc->nr_channels) {
1169 case 3:
1170 if (desc->channel[0].size == 5 &&
1171 desc->channel[1].size == 6 &&
1172 desc->channel[2].size == 5) {
1173 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1174 }
1175 goto out_unknown;
1176 case 4:
1177 if (desc->channel[0].size == 5 &&
1178 desc->channel[1].size == 5 &&
1179 desc->channel[2].size == 5 &&
1180 desc->channel[3].size == 1) {
1181 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1182 }
1183 if (desc->channel[0].size == 10 &&
1184 desc->channel[1].size == 10 &&
1185 desc->channel[2].size == 10 &&
1186 desc->channel[3].size == 2) {
1187 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1188 }
1189 goto out_unknown;
1190 }
1191 goto out_unknown;
1192 }
1193
1194 if (first_non_void < 0 || first_non_void > 3)
1195 goto out_unknown;
1196
1197 /* uniform formats */
1198 switch (desc->channel[first_non_void].size) {
1199 case 4:
1200 switch (desc->nr_channels) {
1201 #if 0 /* Not supported for render targets */
1202 case 2:
1203 return V_008F14_IMG_DATA_FORMAT_4_4;
1204 #endif
1205 case 4:
1206 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1207 }
1208 break;
1209 case 8:
1210 switch (desc->nr_channels) {
1211 case 1:
1212 return V_008F14_IMG_DATA_FORMAT_8;
1213 case 2:
1214 return V_008F14_IMG_DATA_FORMAT_8_8;
1215 case 4:
1216 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1217 }
1218 break;
1219 case 16:
1220 switch (desc->nr_channels) {
1221 case 1:
1222 return V_008F14_IMG_DATA_FORMAT_16;
1223 case 2:
1224 return V_008F14_IMG_DATA_FORMAT_16_16;
1225 case 4:
1226 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1227 }
1228 break;
1229 case 32:
1230 switch (desc->nr_channels) {
1231 case 1:
1232 return V_008F14_IMG_DATA_FORMAT_32;
1233 case 2:
1234 return V_008F14_IMG_DATA_FORMAT_32_32;
1235 #if 0 /* Not supported for render targets */
1236 case 3:
1237 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1238 #endif
1239 case 4:
1240 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1241 }
1242 }
1243
1244 out_unknown:
1245 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1246 return ~0;
1247 }
1248
1249 static unsigned si_tex_wrap(unsigned wrap)
1250 {
1251 switch (wrap) {
1252 default:
1253 case PIPE_TEX_WRAP_REPEAT:
1254 return V_008F30_SQ_TEX_WRAP;
1255 case PIPE_TEX_WRAP_CLAMP:
1256 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1257 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1258 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1259 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1260 return V_008F30_SQ_TEX_CLAMP_BORDER;
1261 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1262 return V_008F30_SQ_TEX_MIRROR;
1263 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1264 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1265 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1266 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1267 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1268 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1269 }
1270 }
1271
1272 static unsigned si_tex_filter(unsigned filter)
1273 {
1274 switch (filter) {
1275 default:
1276 case PIPE_TEX_FILTER_NEAREST:
1277 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1278 case PIPE_TEX_FILTER_LINEAR:
1279 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1280 }
1281 }
1282
1283 static unsigned si_tex_mipfilter(unsigned filter)
1284 {
1285 switch (filter) {
1286 case PIPE_TEX_MIPFILTER_NEAREST:
1287 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1288 case PIPE_TEX_MIPFILTER_LINEAR:
1289 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1290 default:
1291 case PIPE_TEX_MIPFILTER_NONE:
1292 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1293 }
1294 }
1295
1296 static unsigned si_tex_compare(unsigned compare)
1297 {
1298 switch (compare) {
1299 default:
1300 case PIPE_FUNC_NEVER:
1301 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1302 case PIPE_FUNC_LESS:
1303 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1304 case PIPE_FUNC_EQUAL:
1305 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1306 case PIPE_FUNC_LEQUAL:
1307 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1308 case PIPE_FUNC_GREATER:
1309 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1310 case PIPE_FUNC_NOTEQUAL:
1311 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1312 case PIPE_FUNC_GEQUAL:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1314 case PIPE_FUNC_ALWAYS:
1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1316 }
1317 }
1318
1319 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1320 {
1321 switch (dim) {
1322 default:
1323 case PIPE_TEXTURE_1D:
1324 return V_008F1C_SQ_RSRC_IMG_1D;
1325 case PIPE_TEXTURE_1D_ARRAY:
1326 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1327 case PIPE_TEXTURE_2D:
1328 case PIPE_TEXTURE_RECT:
1329 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1330 V_008F1C_SQ_RSRC_IMG_2D;
1331 case PIPE_TEXTURE_2D_ARRAY:
1332 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1333 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1334 case PIPE_TEXTURE_3D:
1335 return V_008F1C_SQ_RSRC_IMG_3D;
1336 case PIPE_TEXTURE_CUBE:
1337 return V_008F1C_SQ_RSRC_IMG_CUBE;
1338 }
1339 }
1340
1341 /*
1342 * Format support testing
1343 */
1344
1345 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1346 {
1347 return si_translate_texformat(screen, format, util_format_description(format),
1348 util_format_get_first_non_void_channel(format)) != ~0U;
1349 }
1350
1351 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1352 enum pipe_format format,
1353 const struct util_format_description *desc,
1354 int first_non_void)
1355 {
1356 unsigned type = desc->channel[first_non_void].type;
1357 int i;
1358
1359 if (type == UTIL_FORMAT_TYPE_FIXED)
1360 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1361
1362 /* See whether the components are of the same size. */
1363 for (i = 0; i < desc->nr_channels; i++) {
1364 if (desc->channel[first_non_void].size != desc->channel[i].size)
1365 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1366 }
1367
1368 switch (desc->channel[first_non_void].size) {
1369 case 8:
1370 switch (desc->nr_channels) {
1371 case 1:
1372 return V_008F0C_BUF_DATA_FORMAT_8;
1373 case 2:
1374 return V_008F0C_BUF_DATA_FORMAT_8_8;
1375 case 3:
1376 case 4:
1377 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1378 }
1379 break;
1380 case 16:
1381 switch (desc->nr_channels) {
1382 case 1:
1383 return V_008F0C_BUF_DATA_FORMAT_16;
1384 case 2:
1385 return V_008F0C_BUF_DATA_FORMAT_16_16;
1386 case 3:
1387 case 4:
1388 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1389 }
1390 break;
1391 case 32:
1392 /* From the Southern Islands ISA documentation about MTBUF:
1393 * 'Memory reads of data in memory that is 32 or 64 bits do not
1394 * undergo any format conversion.'
1395 */
1396 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1397 !desc->channel[first_non_void].pure_integer)
1398 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1399
1400 switch (desc->nr_channels) {
1401 case 1:
1402 return V_008F0C_BUF_DATA_FORMAT_32;
1403 case 2:
1404 return V_008F0C_BUF_DATA_FORMAT_32_32;
1405 case 3:
1406 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1407 case 4:
1408 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1409 }
1410 break;
1411 }
1412
1413 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1414 }
1415
1416 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1417 {
1418 const struct util_format_description *desc;
1419 int first_non_void;
1420 unsigned data_format;
1421
1422 desc = util_format_description(format);
1423 first_non_void = util_format_get_first_non_void_channel(format);
1424 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1425 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1426 }
1427
1428 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1429 {
1430 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1431 si_translate_colorswap(format) != ~0U;
1432 }
1433
1434 static bool si_is_zs_format_supported(enum pipe_format format)
1435 {
1436 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1437 }
1438
1439 boolean si_is_format_supported(struct pipe_screen *screen,
1440 enum pipe_format format,
1441 enum pipe_texture_target target,
1442 unsigned sample_count,
1443 unsigned usage)
1444 {
1445 struct r600_screen *rscreen = (struct r600_screen *)screen;
1446 unsigned retval = 0;
1447
1448 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1449 R600_ERR("r600: unsupported texture type %d\n", target);
1450 return FALSE;
1451 }
1452
1453 if (!util_format_is_supported(format, usage))
1454 return FALSE;
1455
1456 if (sample_count > 1) {
1457 if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI)
1458 return FALSE;
1459
1460 switch (sample_count) {
1461 case 2:
1462 case 4:
1463 case 8:
1464 break;
1465 default:
1466 return FALSE;
1467 }
1468 }
1469
1470 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1471 si_is_sampler_format_supported(screen, format)) {
1472 retval |= PIPE_BIND_SAMPLER_VIEW;
1473 }
1474
1475 if ((usage & (PIPE_BIND_RENDER_TARGET |
1476 PIPE_BIND_DISPLAY_TARGET |
1477 PIPE_BIND_SCANOUT |
1478 PIPE_BIND_SHARED)) &&
1479 si_is_colorbuffer_format_supported(format)) {
1480 retval |= usage &
1481 (PIPE_BIND_RENDER_TARGET |
1482 PIPE_BIND_DISPLAY_TARGET |
1483 PIPE_BIND_SCANOUT |
1484 PIPE_BIND_SHARED);
1485 }
1486
1487 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1488 si_is_zs_format_supported(format)) {
1489 retval |= PIPE_BIND_DEPTH_STENCIL;
1490 }
1491
1492 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1493 si_is_vertex_format_supported(screen, format)) {
1494 retval |= PIPE_BIND_VERTEX_BUFFER;
1495 }
1496
1497 if (usage & PIPE_BIND_TRANSFER_READ)
1498 retval |= PIPE_BIND_TRANSFER_READ;
1499 if (usage & PIPE_BIND_TRANSFER_WRITE)
1500 retval |= PIPE_BIND_TRANSFER_WRITE;
1501
1502 return retval == usage;
1503 }
1504
1505 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1506 {
1507 unsigned tile_mode_index = 0;
1508
1509 if (stencil) {
1510 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1511 } else {
1512 tile_mode_index = rtex->surface.tiling_index[level];
1513 }
1514 return tile_mode_index;
1515 }
1516
1517 /*
1518 * framebuffer handling
1519 */
1520
1521 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1522 const struct pipe_framebuffer_state *state, int cb)
1523 {
1524 struct r600_texture *rtex;
1525 struct r600_surface *surf;
1526 unsigned level = state->cbufs[cb]->u.tex.level;
1527 unsigned pitch, slice;
1528 unsigned color_info, color_attrib;
1529 unsigned tile_mode_index;
1530 unsigned format, swap, ntype, endian;
1531 uint64_t offset;
1532 const struct util_format_description *desc;
1533 int i;
1534 unsigned blend_clamp = 0, blend_bypass = 0;
1535 unsigned max_comp_size;
1536
1537 surf = (struct r600_surface *)state->cbufs[cb];
1538 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1539
1540 offset = rtex->surface.level[level].offset;
1541 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1542 offset += rtex->surface.level[level].slice_size *
1543 state->cbufs[cb]->u.tex.first_layer;
1544 }
1545 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1546 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1547 if (slice) {
1548 slice = slice - 1;
1549 }
1550
1551 tile_mode_index = si_tile_mode_index(rtex, level, false);
1552
1553 desc = util_format_description(surf->base.format);
1554 for (i = 0; i < 4; i++) {
1555 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1556 break;
1557 }
1558 }
1559 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1560 ntype = V_028C70_NUMBER_FLOAT;
1561 } else {
1562 ntype = V_028C70_NUMBER_UNORM;
1563 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1564 ntype = V_028C70_NUMBER_SRGB;
1565 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1566 if (desc->channel[i].pure_integer) {
1567 ntype = V_028C70_NUMBER_SINT;
1568 } else {
1569 assert(desc->channel[i].normalized);
1570 ntype = V_028C70_NUMBER_SNORM;
1571 }
1572 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1573 if (desc->channel[i].pure_integer) {
1574 ntype = V_028C70_NUMBER_UINT;
1575 } else {
1576 assert(desc->channel[i].normalized);
1577 ntype = V_028C70_NUMBER_UNORM;
1578 }
1579 }
1580 }
1581
1582 format = si_translate_colorformat(surf->base.format);
1583 if (format == V_028C70_COLOR_INVALID) {
1584 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1585 }
1586 assert(format != V_028C70_COLOR_INVALID);
1587 swap = si_translate_colorswap(surf->base.format);
1588 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1589 endian = V_028C70_ENDIAN_NONE;
1590 } else {
1591 endian = si_colorformat_endian_swap(format);
1592 }
1593
1594 /* blend clamp should be set for all NORM/SRGB types */
1595 if (ntype == V_028C70_NUMBER_UNORM ||
1596 ntype == V_028C70_NUMBER_SNORM ||
1597 ntype == V_028C70_NUMBER_SRGB)
1598 blend_clamp = 1;
1599
1600 /* set blend bypass according to docs if SINT/UINT or
1601 8/24 COLOR variants */
1602 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1603 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1604 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1605 blend_clamp = 0;
1606 blend_bypass = 1;
1607 }
1608
1609 color_info = S_028C70_FORMAT(format) |
1610 S_028C70_COMP_SWAP(swap) |
1611 S_028C70_BLEND_CLAMP(blend_clamp) |
1612 S_028C70_BLEND_BYPASS(blend_bypass) |
1613 S_028C70_NUMBER_TYPE(ntype) |
1614 S_028C70_ENDIAN(endian);
1615
1616 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1617 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1618
1619 if (rtex->resource.b.b.nr_samples > 1) {
1620 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1621
1622 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1623 S_028C74_NUM_FRAGMENTS(log_samples);
1624
1625 if (rtex->fmask.size) {
1626 color_info |= S_028C70_COMPRESSION(1);
1627 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1628
1629 /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */
1630 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) |
1631 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1632 }
1633 }
1634
1635 if (rtex->cmask.size) {
1636 color_info |= S_028C70_FAST_CLEAR(1);
1637 }
1638
1639 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1640 offset >>= 8;
1641
1642 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1643 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1644 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1645 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1646 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1647
1648 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1649 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1650 } else {
1651 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1652 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1653 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1654 }
1655 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1656 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1657
1658 if (rtex->cmask.size) {
1659 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1660 offset + (rtex->cmask.offset >> 8));
1661 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1662 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1663 }
1664 if (rtex->fmask.size) {
1665 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1666 offset + (rtex->fmask.offset >> 8));
1667 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1668 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1669 }
1670
1671 /* set CB_COLOR1_INFO for possible dual-src blending */
1672 if (state->nr_cbufs == 1) {
1673 assert(cb == 0);
1674 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1675 }
1676
1677 /* Determine pixel shader export format */
1678 max_comp_size = si_colorformat_max_comp_size(format);
1679 if (ntype == V_028C70_NUMBER_SRGB ||
1680 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1681 max_comp_size <= 10) ||
1682 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1683 rctx->export_16bpc |= 1 << cb;
1684 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1685 if (state->nr_cbufs == 1)
1686 rctx->export_16bpc |= 1 << 1;
1687 }
1688 }
1689
1690 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1691 const struct pipe_framebuffer_state *state)
1692 {
1693 struct r600_screen *rscreen = rctx->screen;
1694 struct r600_texture *rtex;
1695 struct r600_surface *surf;
1696 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1697 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1698 uint32_t z_info, s_info, db_depth_info;
1699 uint64_t z_offs, s_offs;
1700
1701 if (state->zsbuf == NULL) {
1702 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1703 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1704 return;
1705 }
1706
1707 surf = (struct r600_surface *)state->zsbuf;
1708 level = surf->base.u.tex.level;
1709 rtex = (struct r600_texture*)surf->base.texture;
1710
1711 format = si_translate_dbformat(rtex->resource.b.b.format);
1712
1713 if (format == V_028040_Z_INVALID) {
1714 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1715 }
1716 assert(format != V_028040_Z_INVALID);
1717
1718 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1719 z_offs += rtex->surface.level[level].offset;
1720 s_offs += rtex->surface.stencil_level[level].offset;
1721
1722 z_offs >>= 8;
1723 s_offs >>= 8;
1724
1725 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1726 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1727 if (slice) {
1728 slice = slice - 1;
1729 }
1730
1731 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1732
1733 z_info = S_028040_FORMAT(format);
1734 if (rtex->resource.b.b.nr_samples > 1) {
1735 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1736 }
1737
1738 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1739 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1740 else
1741 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1742
1743 if (rctx->b.chip_class >= CIK) {
1744 switch (rtex->surface.level[level].mode) {
1745 case RADEON_SURF_MODE_2D:
1746 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1747 break;
1748 case RADEON_SURF_MODE_1D:
1749 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1750 case RADEON_SURF_MODE_LINEAR:
1751 default:
1752 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1753 break;
1754 }
1755 tile_split = rtex->surface.tile_split;
1756 stile_split = rtex->surface.stencil_tile_split;
1757 macro_aspect = rtex->surface.mtilea;
1758 bankw = rtex->surface.bankw;
1759 bankh = rtex->surface.bankh;
1760 tile_split = cik_tile_split(tile_split);
1761 stile_split = cik_tile_split(stile_split);
1762 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1763 bankw = cik_bank_wh(bankw);
1764 bankh = cik_bank_wh(bankh);
1765 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1766 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1767 rscreen->b.info.r600_num_backends);
1768
1769 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1770 S_02803C_PIPE_CONFIG(pipe_config) |
1771 S_02803C_BANK_WIDTH(bankw) |
1772 S_02803C_BANK_HEIGHT(bankh) |
1773 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1774 S_02803C_NUM_BANKS(nbanks);
1775 z_info |= S_028040_TILE_SPLIT(tile_split);
1776 s_info |= S_028044_TILE_SPLIT(stile_split);
1777 } else {
1778 tile_mode_index = si_tile_mode_index(rtex, level, false);
1779 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1780 tile_mode_index = si_tile_mode_index(rtex, level, true);
1781 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1782 }
1783
1784 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1785 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1786 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1787
1788 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1789 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1790 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1791
1792 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1793 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1794 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1795 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1796 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1797
1798 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1799 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1800 }
1801
1802 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1803 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1804 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1805 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1806 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1807
1808 /* 2xMSAA
1809 * There are two locations (-4, 4), (4, -4). */
1810 static uint32_t sample_locs_2x[] = {
1811 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1812 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1813 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1814 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1815 };
1816 static unsigned max_dist_2x = 4;
1817 /* 4xMSAA
1818 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1819 static uint32_t sample_locs_4x[] = {
1820 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1821 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1822 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1823 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1824 };
1825 static unsigned max_dist_4x = 6;
1826 /* Cayman/SI 8xMSAA */
1827 static uint32_t cm_sample_locs_8x[] = {
1828 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1829 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1830 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1831 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1832 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1833 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1834 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1835 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1836 };
1837 static unsigned cm_max_dist_8x = 8;
1838 /* Cayman/SI 16xMSAA */
1839 static uint32_t cm_sample_locs_16x[] = {
1840 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1841 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1842 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1843 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1844 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1845 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1846 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1847 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1848 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1849 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1850 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1851 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1852 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1853 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1854 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1855 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1856 };
1857 static unsigned cm_max_dist_16x = 8;
1858
1859 static void si_get_sample_position(struct pipe_context *ctx,
1860 unsigned sample_count,
1861 unsigned sample_index,
1862 float *out_value)
1863 {
1864 int offset, index;
1865 struct {
1866 int idx:4;
1867 } val;
1868 switch (sample_count) {
1869 case 1:
1870 default:
1871 out_value[0] = out_value[1] = 0.5;
1872 break;
1873 case 2:
1874 offset = 4 * (sample_index * 2);
1875 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1876 out_value[0] = (float)(val.idx + 8) / 16.0f;
1877 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1878 out_value[1] = (float)(val.idx + 8) / 16.0f;
1879 break;
1880 case 4:
1881 offset = 4 * (sample_index * 2);
1882 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1883 out_value[0] = (float)(val.idx + 8) / 16.0f;
1884 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1885 out_value[1] = (float)(val.idx + 8) / 16.0f;
1886 break;
1887 case 8:
1888 offset = 4 * (sample_index % 4 * 2);
1889 index = (sample_index / 4) * 4;
1890 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1891 out_value[0] = (float)(val.idx + 8) / 16.0f;
1892 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1893 out_value[1] = (float)(val.idx + 8) / 16.0f;
1894 break;
1895 case 16:
1896 offset = 4 * (sample_index % 4 * 2);
1897 index = (sample_index / 4) * 4;
1898 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1899 out_value[0] = (float)(val.idx + 8) / 16.0f;
1900 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1901 out_value[1] = (float)(val.idx + 8) / 16.0f;
1902 break;
1903 }
1904 }
1905
1906 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1907 {
1908 unsigned max_dist = 0;
1909
1910 switch (nr_samples) {
1911 default:
1912 nr_samples = 0;
1913 break;
1914 case 2:
1915 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1916 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1917 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1918 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1919 max_dist = max_dist_2x;
1920 break;
1921 case 4:
1922 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1923 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1924 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1925 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1926 max_dist = max_dist_4x;
1927 break;
1928 case 8:
1929 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1930 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1931 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1932 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1933 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1934 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1935 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1936 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1937 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1938 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1939 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1940 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
1941 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
1942 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
1943 max_dist = cm_max_dist_8x;
1944 break;
1945 case 16:
1946 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
1947 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
1948 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
1949 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
1950 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
1951 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
1952 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
1953 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
1954 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
1955 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
1956 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
1957 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
1958 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
1959 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
1960 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
1961 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
1962 max_dist = cm_max_dist_16x;
1963 break;
1964 }
1965
1966 if (nr_samples > 1) {
1967 unsigned log_samples = util_logbase2(nr_samples);
1968
1969 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
1970 S_028BDC_LAST_PIXEL(1) |
1971 S_028BDC_EXPAND_LINE_WIDTH(1));
1972 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
1973 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1974 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1975 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
1976
1977 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
1978 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1979 S_028804_PS_ITER_SAMPLES(log_samples) |
1980 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1981 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1982 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1983 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1984 } else {
1985 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
1986 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
1987
1988 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
1989 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1990 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1991 }
1992 }
1993
1994 static void si_set_framebuffer_state(struct pipe_context *ctx,
1995 const struct pipe_framebuffer_state *state)
1996 {
1997 struct r600_context *rctx = (struct r600_context *)ctx;
1998 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
1999 uint32_t tl, br;
2000 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2001
2002 if (pm4 == NULL)
2003 return;
2004
2005 if (rctx->framebuffer.nr_cbufs) {
2006 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2007 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2008 }
2009 if (rctx->framebuffer.zsbuf) {
2010 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2011 }
2012
2013 util_copy_framebuffer_state(&rctx->framebuffer, state);
2014
2015 /* build states */
2016 rctx->export_16bpc = 0;
2017 rctx->fb_compressed_cb_mask = 0;
2018 for (i = 0; i < state->nr_cbufs; i++) {
2019 struct r600_texture *rtex =
2020 (struct r600_texture*)state->cbufs[i]->texture;
2021
2022 si_cb(rctx, pm4, state, i);
2023
2024 if (rtex->fmask.size || rtex->cmask.size) {
2025 rctx->fb_compressed_cb_mask |= 1 << i;
2026 }
2027 }
2028 for (; i < 8; i++) {
2029 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2030 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2031 }
2032
2033 assert(!(rctx->export_16bpc & ~0xff));
2034 si_db(rctx, pm4, state);
2035
2036 tl_x = 0;
2037 tl_y = 0;
2038 br_x = state->width;
2039 br_y = state->height;
2040
2041 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2042 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2043
2044 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2045 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2046 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2047 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2048 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2049 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2050 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2051 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2052 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2053 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2054
2055 if (state->nr_cbufs)
2056 nr_samples = state->cbufs[0]->texture->nr_samples;
2057 else if (state->zsbuf)
2058 nr_samples = state->zsbuf->texture->nr_samples;
2059 else
2060 nr_samples = 0;
2061
2062 si_set_msaa_state(rctx, pm4, nr_samples);
2063 rctx->fb_log_samples = util_logbase2(nr_samples);
2064 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2065 util_format_is_pure_integer(state->cbufs[0]->format);
2066
2067 si_pm4_set_state(rctx, framebuffer, pm4);
2068 si_update_fb_rs_state(rctx);
2069 si_update_fb_blend_state(rctx);
2070 }
2071
2072 /*
2073 * shaders
2074 */
2075
2076 /* Compute the key for the hw shader variant */
2077 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2078 struct si_pipe_shader_selector *sel,
2079 union si_shader_key *key)
2080 {
2081 struct r600_context *rctx = (struct r600_context *)ctx;
2082 memset(key, 0, sizeof(*key));
2083
2084 if (sel->type == PIPE_SHADER_VERTEX) {
2085 unsigned i;
2086 if (!rctx->vertex_elements)
2087 return;
2088
2089 for (i = 0; i < rctx->vertex_elements->count; ++i)
2090 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2091
2092 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2093 key->vs.ucps_enabled |= 0x2;
2094 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2095 key->vs.ucps_enabled |= 0x1;
2096 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2097 if (sel->fs_write_all)
2098 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2099 key->ps.export_16bpc = rctx->export_16bpc;
2100
2101 if (rctx->queued.named.rasterizer) {
2102 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2103 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2104
2105 if (rctx->queued.named.blend) {
2106 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2107 rctx->queued.named.rasterizer->multisample_enable &&
2108 !rctx->fb_cb0_is_integer;
2109 }
2110 }
2111 if (rctx->queued.named.dsa) {
2112 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2113
2114 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2115 if (rctx->framebuffer.nr_cbufs &&
2116 rctx->framebuffer.cbufs[0] &&
2117 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2118 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2119
2120 if (key->ps.alpha_func != PIPE_FUNC_ALWAYS &&
2121 key->ps.alpha_func != PIPE_FUNC_NEVER)
2122 key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
2123 } else {
2124 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2125 }
2126 }
2127 }
2128
2129 /* Select the hw shader variant depending on the current state.
2130 * (*dirty) is set to 1 if current variant was changed */
2131 int si_shader_select(struct pipe_context *ctx,
2132 struct si_pipe_shader_selector *sel,
2133 unsigned *dirty)
2134 {
2135 union si_shader_key key;
2136 struct si_pipe_shader * shader = NULL;
2137 int r;
2138
2139 si_shader_selector_key(ctx, sel, &key);
2140
2141 /* Check if we don't need to change anything.
2142 * This path is also used for most shaders that don't need multiple
2143 * variants, it will cost just a computation of the key and this
2144 * test. */
2145 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2146 return 0;
2147 }
2148
2149 /* lookup if we have other variants in the list */
2150 if (sel->num_shaders > 1) {
2151 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2152
2153 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2154 p = c;
2155 c = c->next_variant;
2156 }
2157
2158 if (c) {
2159 p->next_variant = c->next_variant;
2160 shader = c;
2161 }
2162 }
2163
2164 if (unlikely(!shader)) {
2165 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2166 shader->selector = sel;
2167 shader->key = key;
2168
2169 r = si_pipe_shader_create(ctx, shader);
2170 if (unlikely(r)) {
2171 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2172 sel->type, r);
2173 sel->current = NULL;
2174 FREE(shader);
2175 return r;
2176 }
2177
2178 /* We don't know the value of fs_write_all property until we built
2179 * at least one variant, so we may need to recompute the key (include
2180 * rctx->framebuffer.nr_cbufs) after building first variant. */
2181 if (sel->type == PIPE_SHADER_FRAGMENT &&
2182 sel->num_shaders == 0 &&
2183 shader->shader.fs_write_all) {
2184 sel->fs_write_all = 1;
2185 si_shader_selector_key(ctx, sel, &shader->key);
2186 }
2187
2188 sel->num_shaders++;
2189 }
2190
2191 if (dirty)
2192 *dirty = 1;
2193
2194 shader->next_variant = sel->current;
2195 sel->current = shader;
2196
2197 return 0;
2198 }
2199
2200 static void *si_create_shader_state(struct pipe_context *ctx,
2201 const struct pipe_shader_state *state,
2202 unsigned pipe_shader_type)
2203 {
2204 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2205 int r;
2206
2207 sel->type = pipe_shader_type;
2208 sel->tokens = tgsi_dup_tokens(state->tokens);
2209 sel->so = state->stream_output;
2210
2211 r = si_shader_select(ctx, sel, NULL);
2212 if (r) {
2213 free(sel);
2214 return NULL;
2215 }
2216
2217 return sel;
2218 }
2219
2220 static void *si_create_fs_state(struct pipe_context *ctx,
2221 const struct pipe_shader_state *state)
2222 {
2223 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2224 }
2225
2226 static void *si_create_vs_state(struct pipe_context *ctx,
2227 const struct pipe_shader_state *state)
2228 {
2229 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2230 }
2231
2232 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2233 {
2234 struct r600_context *rctx = (struct r600_context *)ctx;
2235 struct si_pipe_shader_selector *sel = state;
2236
2237 if (rctx->vs_shader == sel)
2238 return;
2239
2240 rctx->vs_shader = sel;
2241
2242 if (sel && sel->current) {
2243 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2244 rctx->b.streamout.stride_in_dw = sel->so.stride;
2245 } else {
2246 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2247 }
2248
2249 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2250 }
2251
2252 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2253 {
2254 struct r600_context *rctx = (struct r600_context *)ctx;
2255 struct si_pipe_shader_selector *sel = state;
2256
2257 if (rctx->ps_shader == sel)
2258 return;
2259
2260 rctx->ps_shader = sel;
2261
2262 if (sel && sel->current)
2263 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2264 else
2265 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2266
2267 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2268 }
2269
2270 static void si_delete_shader_selector(struct pipe_context *ctx,
2271 struct si_pipe_shader_selector *sel)
2272 {
2273 struct r600_context *rctx = (struct r600_context *)ctx;
2274 struct si_pipe_shader *p = sel->current, *c;
2275
2276 while (p) {
2277 c = p->next_variant;
2278 si_pm4_delete_state(rctx, vs, p->pm4);
2279 si_pipe_shader_destroy(ctx, p);
2280 free(p);
2281 p = c;
2282 }
2283
2284 free(sel->tokens);
2285 free(sel);
2286 }
2287
2288 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2289 {
2290 struct r600_context *rctx = (struct r600_context *)ctx;
2291 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2292
2293 if (rctx->vs_shader == sel) {
2294 rctx->vs_shader = NULL;
2295 }
2296
2297 si_delete_shader_selector(ctx, sel);
2298 }
2299
2300 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2301 {
2302 struct r600_context *rctx = (struct r600_context *)ctx;
2303 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2304
2305 if (rctx->ps_shader == sel) {
2306 rctx->ps_shader = NULL;
2307 }
2308
2309 si_delete_shader_selector(ctx, sel);
2310 }
2311
2312 /*
2313 * Samplers
2314 */
2315
2316 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2317 struct pipe_resource *texture,
2318 const struct pipe_sampler_view *state)
2319 {
2320 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2321 struct r600_texture *tmp = (struct r600_texture*)texture;
2322 const struct util_format_description *desc;
2323 unsigned format, num_format;
2324 uint32_t pitch = 0;
2325 unsigned char state_swizzle[4], swizzle[4];
2326 unsigned height, depth, width;
2327 enum pipe_format pipe_format = state->format;
2328 struct radeon_surface_level *surflevel;
2329 int first_non_void;
2330 uint64_t va;
2331
2332 if (view == NULL)
2333 return NULL;
2334
2335 /* initialize base object */
2336 view->base = *state;
2337 view->base.texture = NULL;
2338 pipe_reference(NULL, &texture->reference);
2339 view->base.texture = texture;
2340 view->base.reference.count = 1;
2341 view->base.context = ctx;
2342
2343 state_swizzle[0] = state->swizzle_r;
2344 state_swizzle[1] = state->swizzle_g;
2345 state_swizzle[2] = state->swizzle_b;
2346 state_swizzle[3] = state->swizzle_a;
2347
2348 surflevel = tmp->surface.level;
2349
2350 /* Texturing with separate depth and stencil. */
2351 if (tmp->is_depth && !tmp->is_flushing_texture) {
2352 switch (pipe_format) {
2353 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2354 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2355 break;
2356 case PIPE_FORMAT_X8Z24_UNORM:
2357 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2358 /* Z24 is always stored like this. */
2359 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2360 break;
2361 case PIPE_FORMAT_X24S8_UINT:
2362 case PIPE_FORMAT_S8X24_UINT:
2363 case PIPE_FORMAT_X32_S8X24_UINT:
2364 pipe_format = PIPE_FORMAT_S8_UINT;
2365 surflevel = tmp->surface.stencil_level;
2366 break;
2367 default:;
2368 }
2369 }
2370
2371 desc = util_format_description(pipe_format);
2372
2373 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2374 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2375 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2376
2377 switch (pipe_format) {
2378 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2379 case PIPE_FORMAT_X24S8_UINT:
2380 case PIPE_FORMAT_X32_S8X24_UINT:
2381 case PIPE_FORMAT_X8Z24_UNORM:
2382 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2383 break;
2384 default:
2385 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2386 }
2387 } else {
2388 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2389 }
2390
2391 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2392
2393 switch (pipe_format) {
2394 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2395 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2396 break;
2397 default:
2398 if (first_non_void < 0) {
2399 if (util_format_is_compressed(pipe_format)) {
2400 switch (pipe_format) {
2401 case PIPE_FORMAT_DXT1_SRGB:
2402 case PIPE_FORMAT_DXT1_SRGBA:
2403 case PIPE_FORMAT_DXT3_SRGBA:
2404 case PIPE_FORMAT_DXT5_SRGBA:
2405 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2406 break;
2407 case PIPE_FORMAT_RGTC1_SNORM:
2408 case PIPE_FORMAT_LATC1_SNORM:
2409 case PIPE_FORMAT_RGTC2_SNORM:
2410 case PIPE_FORMAT_LATC2_SNORM:
2411 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2412 break;
2413 default:
2414 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2415 break;
2416 }
2417 } else {
2418 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2419 }
2420 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2421 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2422 } else {
2423 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2424
2425 switch (desc->channel[first_non_void].type) {
2426 case UTIL_FORMAT_TYPE_FLOAT:
2427 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2428 break;
2429 case UTIL_FORMAT_TYPE_SIGNED:
2430 if (desc->channel[first_non_void].normalized)
2431 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2432 else if (desc->channel[first_non_void].pure_integer)
2433 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2434 else
2435 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2436 break;
2437 case UTIL_FORMAT_TYPE_UNSIGNED:
2438 if (desc->channel[first_non_void].normalized)
2439 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2440 else if (desc->channel[first_non_void].pure_integer)
2441 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2442 else
2443 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2444 }
2445 }
2446 }
2447
2448 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2449 if (format == ~0) {
2450 format = 0;
2451 }
2452
2453 view->resource = &tmp->resource;
2454
2455 /* not supported any more */
2456 //endian = si_colorformat_endian_swap(format);
2457
2458 width = surflevel[0].npix_x;
2459 height = surflevel[0].npix_y;
2460 depth = surflevel[0].npix_z;
2461 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2462
2463 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2464 height = 1;
2465 depth = texture->array_size;
2466 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2467 depth = texture->array_size;
2468 }
2469
2470 va = r600_resource_va(ctx->screen, texture);
2471 va += surflevel[0].offset;
2472 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2473 view->state[0] = va >> 8;
2474 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2475 S_008F14_DATA_FORMAT(format) |
2476 S_008F14_NUM_FORMAT(num_format));
2477 view->state[2] = (S_008F18_WIDTH(width - 1) |
2478 S_008F18_HEIGHT(height - 1));
2479 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2480 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2481 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2482 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2483 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2484 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2485 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2486 util_logbase2(texture->nr_samples) :
2487 state->u.tex.last_level - tmp->mipmap_shift) |
2488 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2489 S_008F1C_POW2_PAD(texture->last_level > 0) |
2490 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2491 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2492 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2493 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2494 view->state[6] = 0;
2495 view->state[7] = 0;
2496
2497 /* Initialize the sampler view for FMASK. */
2498 if (tmp->fmask.size) {
2499 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2500 uint32_t fmask_format;
2501
2502 switch (texture->nr_samples) {
2503 case 2:
2504 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2505 break;
2506 case 4:
2507 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2508 break;
2509 case 8:
2510 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2511 break;
2512 default:
2513 assert(0);
2514 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2515 }
2516
2517 view->fmask_state[0] = va >> 8;
2518 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2519 S_008F14_DATA_FORMAT(fmask_format) |
2520 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2521 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2522 S_008F18_HEIGHT(height - 1);
2523 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2524 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2525 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2526 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2527 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2528 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2529 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2530 S_008F20_PITCH(tmp->fmask.pitch - 1);
2531 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2532 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2533 view->fmask_state[6] = 0;
2534 view->fmask_state[7] = 0;
2535 }
2536
2537 return &view->base;
2538 }
2539
2540 static void si_sampler_view_destroy(struct pipe_context *ctx,
2541 struct pipe_sampler_view *state)
2542 {
2543 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2544
2545 pipe_resource_reference(&state->texture, NULL);
2546 FREE(resource);
2547 }
2548
2549 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2550 {
2551 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2552 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2553 (linear_filter &&
2554 (wrap == PIPE_TEX_WRAP_CLAMP ||
2555 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2556 }
2557
2558 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2559 {
2560 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2561 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2562
2563 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2564 state->border_color.ui[2] || state->border_color.ui[3]) &&
2565 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2566 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2567 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2568 }
2569
2570 static void *si_create_sampler_state(struct pipe_context *ctx,
2571 const struct pipe_sampler_state *state)
2572 {
2573 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2574 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2575 unsigned border_color_type;
2576
2577 if (rstate == NULL) {
2578 return NULL;
2579 }
2580
2581 if (sampler_state_needs_border_color(state))
2582 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2583 else
2584 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2585
2586 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2587 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2588 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2589 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2590 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2591 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2592 aniso_flag_offset << 16 | /* XXX */
2593 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2594 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2595 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2596 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2597 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2598 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2599 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2600 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2601
2602 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2603 memcpy(rstate->border_color, state->border_color.ui,
2604 sizeof(rstate->border_color));
2605 }
2606
2607 return rstate;
2608 }
2609
2610 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2611 * the si_set_sampler_view calls. LTO might help too. */
2612 static void si_set_sampler_views(struct r600_context *rctx,
2613 unsigned shader, unsigned count,
2614 struct pipe_sampler_view **views)
2615 {
2616 struct r600_textures_info *samplers = &rctx->samplers[shader];
2617 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2618 int i;
2619
2620 for (i = 0; i < count; i++) {
2621 if (views[i]) {
2622 struct r600_texture *rtex =
2623 (struct r600_texture*)views[i]->texture;
2624
2625 if (rtex->is_depth && !rtex->is_flushing_texture) {
2626 samplers->depth_texture_mask |= 1 << i;
2627 } else {
2628 samplers->depth_texture_mask &= ~(1 << i);
2629 }
2630 if (rtex->cmask.size || rtex->fmask.size) {
2631 samplers->compressed_colortex_mask |= 1 << i;
2632 } else {
2633 samplers->compressed_colortex_mask &= ~(1 << i);
2634 }
2635
2636 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2637
2638 if (rtex->fmask.size) {
2639 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2640 views[i], rviews[i]->fmask_state);
2641 } else {
2642 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2643 NULL, NULL);
2644 }
2645 } else {
2646 samplers->depth_texture_mask &= ~(1 << i);
2647 samplers->compressed_colortex_mask &= ~(1 << i);
2648 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2649 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2650 NULL, NULL);
2651 }
2652 }
2653 for (; i < samplers->n_views; i++) {
2654 samplers->depth_texture_mask &= ~(1 << i);
2655 samplers->compressed_colortex_mask &= ~(1 << i);
2656 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2657 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2658 NULL, NULL);
2659 }
2660
2661 samplers->n_views = count;
2662 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2663 }
2664
2665 static void si_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
2666 struct pipe_sampler_view **views)
2667 {
2668 struct r600_context *rctx = (struct r600_context *)ctx;
2669
2670 si_set_sampler_views(rctx, PIPE_SHADER_VERTEX, count, views);
2671 }
2672
2673 static void si_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
2674 struct pipe_sampler_view **views)
2675 {
2676 struct r600_context *rctx = (struct r600_context *)ctx;
2677
2678 si_set_sampler_views(rctx, PIPE_SHADER_FRAGMENT, count, views);
2679 }
2680
2681 static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx, unsigned count,
2682 void **states,
2683 struct r600_textures_info *samplers,
2684 unsigned user_data_reg)
2685 {
2686 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2687 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2688 uint32_t *border_color_table = NULL;
2689 int i, j;
2690
2691 if (!count)
2692 goto out;
2693
2694 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2695
2696 si_pm4_sh_data_begin(pm4);
2697 for (i = 0; i < count; i++) {
2698 if (rstates[i] &&
2699 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2700 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2701 if (!rctx->border_color_table ||
2702 ((rctx->border_color_offset + count - i) &
2703 C_008F3C_BORDER_COLOR_PTR)) {
2704 r600_resource_reference(&rctx->border_color_table, NULL);
2705 rctx->border_color_offset = 0;
2706
2707 rctx->border_color_table =
2708 r600_resource_create_custom(&rctx->screen->b.b,
2709 PIPE_USAGE_STAGING,
2710 4096 * 4 * 4);
2711 }
2712
2713 if (!border_color_table) {
2714 border_color_table =
2715 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2716 rctx->b.rings.gfx.cs,
2717 PIPE_TRANSFER_WRITE |
2718 PIPE_TRANSFER_UNSYNCHRONIZED);
2719 }
2720
2721 for (j = 0; j < 4; j++) {
2722 border_color_table[4 * rctx->border_color_offset + j] =
2723 util_le32_to_cpu(rstates[i]->border_color[j]);
2724 }
2725
2726 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2727 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2728 }
2729
2730 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2731 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2732 }
2733 }
2734 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2735
2736 if (border_color_table) {
2737 uint64_t va_offset =
2738 r600_resource_va(&rctx->screen->b.b,
2739 (void*)rctx->border_color_table);
2740
2741 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2742 if (rctx->b.chip_class >= CIK)
2743 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2744 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2745 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2746 }
2747
2748 memcpy(samplers->samplers, states, sizeof(void*) * count);
2749
2750 out:
2751 samplers->n_samplers = count;
2752 return pm4;
2753 }
2754
2755 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2756 {
2757 struct r600_context *rctx = (struct r600_context *)ctx;
2758 struct si_pm4_state *pm4;
2759
2760 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2761 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2762 si_pm4_set_state(rctx, vs_sampler, pm4);
2763 }
2764
2765 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2766 {
2767 struct r600_context *rctx = (struct r600_context *)ctx;
2768 struct si_pm4_state *pm4;
2769
2770 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2771 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2772 si_pm4_set_state(rctx, ps_sampler, pm4);
2773 }
2774
2775
2776 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2777 unsigned start, unsigned count,
2778 void **states)
2779 {
2780 assert(start == 0);
2781
2782 switch (shader) {
2783 case PIPE_SHADER_VERTEX:
2784 si_bind_vs_sampler_states(ctx, count, states);
2785 break;
2786 case PIPE_SHADER_FRAGMENT:
2787 si_bind_ps_sampler_states(ctx, count, states);
2788 break;
2789 default:
2790 ;
2791 }
2792 }
2793
2794
2795
2796 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2797 {
2798 struct r600_context *rctx = (struct r600_context *)ctx;
2799 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2800 uint16_t mask = sample_mask;
2801
2802 if (pm4 == NULL)
2803 return;
2804
2805 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2806 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2807
2808 si_pm4_set_state(rctx, sample_mask, pm4);
2809 }
2810
2811 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2812 {
2813 free(state);
2814 }
2815
2816 /*
2817 * Vertex elements & buffers
2818 */
2819
2820 static void *si_create_vertex_elements(struct pipe_context *ctx,
2821 unsigned count,
2822 const struct pipe_vertex_element *elements)
2823 {
2824 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2825 int i;
2826
2827 assert(count < PIPE_MAX_ATTRIBS);
2828 if (!v)
2829 return NULL;
2830
2831 v->count = count;
2832 for (i = 0; i < count; ++i) {
2833 const struct util_format_description *desc;
2834 unsigned data_format, num_format;
2835 int first_non_void;
2836
2837 desc = util_format_description(elements[i].src_format);
2838 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2839 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2840 desc, first_non_void);
2841
2842 switch (desc->channel[first_non_void].type) {
2843 case UTIL_FORMAT_TYPE_FIXED:
2844 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2845 break;
2846 case UTIL_FORMAT_TYPE_SIGNED:
2847 if (desc->channel[first_non_void].normalized)
2848 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2849 else if (desc->channel[first_non_void].pure_integer)
2850 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
2851 else
2852 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
2853 break;
2854 case UTIL_FORMAT_TYPE_UNSIGNED:
2855 if (desc->channel[first_non_void].normalized)
2856 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2857 else if (desc->channel[first_non_void].pure_integer)
2858 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
2859 else
2860 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
2861 break;
2862 case UTIL_FORMAT_TYPE_FLOAT:
2863 default:
2864 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2865 }
2866
2867 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2868 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2869 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2870 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2871 S_008F0C_NUM_FORMAT(num_format) |
2872 S_008F0C_DATA_FORMAT(data_format);
2873 }
2874 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2875
2876 return v;
2877 }
2878
2879 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2880 {
2881 struct r600_context *rctx = (struct r600_context *)ctx;
2882 struct si_vertex_element *v = (struct si_vertex_element*)state;
2883
2884 rctx->vertex_elements = v;
2885 }
2886
2887 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2888 {
2889 struct r600_context *rctx = (struct r600_context *)ctx;
2890
2891 if (rctx->vertex_elements == state)
2892 rctx->vertex_elements = NULL;
2893 FREE(state);
2894 }
2895
2896 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2897 const struct pipe_vertex_buffer *buffers)
2898 {
2899 struct r600_context *rctx = (struct r600_context *)ctx;
2900
2901 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2902 }
2903
2904 static void si_set_index_buffer(struct pipe_context *ctx,
2905 const struct pipe_index_buffer *ib)
2906 {
2907 struct r600_context *rctx = (struct r600_context *)ctx;
2908
2909 if (ib) {
2910 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2911 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2912 } else {
2913 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2914 }
2915 }
2916
2917 /*
2918 * Misc
2919 */
2920 static void si_set_polygon_stipple(struct pipe_context *ctx,
2921 const struct pipe_poly_stipple *state)
2922 {
2923 }
2924
2925 static void si_texture_barrier(struct pipe_context *ctx)
2926 {
2927 struct r600_context *rctx = (struct r600_context *)ctx;
2928
2929 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2930 R600_CONTEXT_FLUSH_AND_INV_CB;
2931 }
2932
2933 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2934 {
2935 struct pipe_blend_state blend;
2936
2937 memset(&blend, 0, sizeof(blend));
2938 blend.independent_blend_enable = true;
2939 blend.rt[0].colormask = 0xf;
2940 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2941 }
2942
2943 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2944 struct pipe_resource *texture,
2945 const struct pipe_surface *surf_tmpl)
2946 {
2947 struct r600_texture *rtex = (struct r600_texture*)texture;
2948 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2949 unsigned level = surf_tmpl->u.tex.level;
2950
2951 if (surface == NULL)
2952 return NULL;
2953
2954 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2955 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2956 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
2957
2958 pipe_reference_init(&surface->base.reference, 1);
2959 pipe_resource_reference(&surface->base.texture, texture);
2960 surface->base.context = pipe;
2961 surface->base.format = surf_tmpl->format;
2962 surface->base.width = rtex->surface.level[level].npix_x;
2963 surface->base.height = rtex->surface.level[level].npix_y;
2964 surface->base.texture = texture;
2965 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
2966 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
2967 surface->base.u.tex.level = level;
2968
2969 return &surface->base;
2970 }
2971
2972 static void r600_surface_destroy(struct pipe_context *pipe,
2973 struct pipe_surface *surface)
2974 {
2975 pipe_resource_reference(&surface->texture, NULL);
2976 FREE(surface);
2977 }
2978
2979 static boolean si_dma_copy(struct pipe_context *ctx,
2980 struct pipe_resource *dst,
2981 unsigned dst_level,
2982 unsigned dst_x, unsigned dst_y, unsigned dst_z,
2983 struct pipe_resource *src,
2984 unsigned src_level,
2985 const struct pipe_box *src_box)
2986 {
2987 /* XXX implement this or share evergreen_dma_blit with r600g */
2988 return FALSE;
2989 }
2990
2991 void si_init_state_functions(struct r600_context *rctx)
2992 {
2993 int i;
2994
2995 rctx->b.b.create_blend_state = si_create_blend_state;
2996 rctx->b.b.bind_blend_state = si_bind_blend_state;
2997 rctx->b.b.delete_blend_state = si_delete_blend_state;
2998 rctx->b.b.set_blend_color = si_set_blend_color;
2999
3000 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3001 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3002 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3003
3004 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3005 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3006 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3007
3008 for (i = 0; i < 8; i++) {
3009 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3010 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3011 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3012 }
3013 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3014 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3015 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3016
3017 rctx->b.b.set_clip_state = si_set_clip_state;
3018 rctx->b.b.set_scissor_states = si_set_scissor_states;
3019 rctx->b.b.set_viewport_states = si_set_viewport_states;
3020 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3021
3022 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3023 rctx->b.b.get_sample_position = si_get_sample_position;
3024
3025 rctx->b.b.create_vs_state = si_create_vs_state;
3026 rctx->b.b.create_fs_state = si_create_fs_state;
3027 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3028 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3029 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3030 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3031
3032 rctx->b.b.create_sampler_state = si_create_sampler_state;
3033 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3034 rctx->b.b.bind_vertex_sampler_states = si_bind_vs_sampler_states;
3035 rctx->b.b.bind_fragment_sampler_states = si_bind_ps_sampler_states;
3036 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3037
3038 rctx->b.b.create_sampler_view = si_create_sampler_view;
3039 rctx->b.b.set_vertex_sampler_views = si_set_vs_sampler_views;
3040 rctx->b.b.set_fragment_sampler_views = si_set_ps_sampler_views;
3041 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3042
3043 rctx->b.b.set_sample_mask = si_set_sample_mask;
3044
3045 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3046 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3047 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3048 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3049 rctx->b.b.set_index_buffer = si_set_index_buffer;
3050
3051 rctx->b.b.texture_barrier = si_texture_barrier;
3052 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3053 rctx->b.b.create_surface = r600_create_surface;
3054 rctx->b.b.surface_destroy = r600_surface_destroy;
3055 rctx->b.dma_copy = si_dma_copy;
3056
3057 rctx->b.b.draw_vbo = si_draw_vbo;
3058 }
3059
3060 void si_init_config(struct r600_context *rctx)
3061 {
3062 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3063
3064 if (pm4 == NULL)
3065 return;
3066
3067 si_cmd_context_control(pm4);
3068
3069 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3070
3071 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3072 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3073 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3074 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3075 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3076 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3077 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3078 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3079 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3080 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3081 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3082 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3083 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3084 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3085 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3086 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3087 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3088 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3089 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3090 S_028AA8_SWITCH_ON_EOP(1) |
3091 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3092 S_028AA8_PRIMGROUP_SIZE(63));
3093 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3094 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3095 if (rctx->b.chip_class < CIK)
3096 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3097 S_008A14_CLIP_VTX_REORDER_ENA(1));
3098
3099 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3100 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3101 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3102
3103 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3104
3105 if (rctx->b.chip_class >= CIK) {
3106 switch (rctx->screen->b.family) {
3107 case CHIP_BONAIRE:
3108 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3109 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3110 break;
3111 case CHIP_KAVERI:
3112 /* XXX todo */
3113 case CHIP_KABINI:
3114 /* XXX todo */
3115 default:
3116 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3117 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3118 break;
3119 }
3120 } else {
3121 switch (rctx->screen->b.family) {
3122 case CHIP_TAHITI:
3123 case CHIP_PITCAIRN:
3124 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3125 break;
3126 case CHIP_VERDE:
3127 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3128 break;
3129 case CHIP_OLAND:
3130 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3131 break;
3132 case CHIP_HAINAN:
3133 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3134 break;
3135 default:
3136 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3137 break;
3138 }
3139 }
3140
3141 si_pm4_set_state(rctx, init, pm4);
3142 }