2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "radeonsi_pipe.h"
35 #include "radeonsi_shader.h"
40 * inferred framebuffer and blender state
42 static void si_update_fb_blend_state(struct r600_context
*rctx
)
44 struct si_pm4_state
*pm4
;
45 struct si_state_blend
*blend
= rctx
->queued
.named
.blend
;
51 pm4
= CALLOC_STRUCT(si_pm4_state
);
55 mask
= (1ULL << ((unsigned)rctx
->framebuffer
.nr_cbufs
* 4)) - 1;
56 mask
&= blend
->cb_target_mask
;
57 si_pm4_set_reg(pm4
, R_028238_CB_TARGET_MASK
, mask
);
59 si_pm4_set_state(rctx
, fb_blend
, pm4
);
66 static uint32_t si_translate_blend_function(int blend_func
)
70 return V_028780_COMB_DST_PLUS_SRC
;
71 case PIPE_BLEND_SUBTRACT
:
72 return V_028780_COMB_SRC_MINUS_DST
;
73 case PIPE_BLEND_REVERSE_SUBTRACT
:
74 return V_028780_COMB_DST_MINUS_SRC
;
76 return V_028780_COMB_MIN_DST_SRC
;
78 return V_028780_COMB_MAX_DST_SRC
;
80 R600_ERR("Unknown blend function %d\n", blend_func
);
87 static uint32_t si_translate_blend_factor(int blend_fact
)
90 case PIPE_BLENDFACTOR_ONE
:
91 return V_028780_BLEND_ONE
;
92 case PIPE_BLENDFACTOR_SRC_COLOR
:
93 return V_028780_BLEND_SRC_COLOR
;
94 case PIPE_BLENDFACTOR_SRC_ALPHA
:
95 return V_028780_BLEND_SRC_ALPHA
;
96 case PIPE_BLENDFACTOR_DST_ALPHA
:
97 return V_028780_BLEND_DST_ALPHA
;
98 case PIPE_BLENDFACTOR_DST_COLOR
:
99 return V_028780_BLEND_DST_COLOR
;
100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
101 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
102 case PIPE_BLENDFACTOR_CONST_COLOR
:
103 return V_028780_BLEND_CONSTANT_COLOR
;
104 case PIPE_BLENDFACTOR_CONST_ALPHA
:
105 return V_028780_BLEND_CONSTANT_ALPHA
;
106 case PIPE_BLENDFACTOR_ZERO
:
107 return V_028780_BLEND_ZERO
;
108 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
112 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
114 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
115 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
116 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
120 case PIPE_BLENDFACTOR_SRC1_COLOR
:
121 return V_028780_BLEND_SRC1_COLOR
;
122 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
123 return V_028780_BLEND_SRC1_ALPHA
;
124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
125 return V_028780_BLEND_INV_SRC1_COLOR
;
126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
127 return V_028780_BLEND_INV_SRC1_ALPHA
;
129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
136 static void *si_create_blend_state(struct pipe_context
*ctx
,
137 const struct pipe_blend_state
*state
)
139 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
140 struct si_pm4_state
*pm4
= &blend
->pm4
;
142 uint32_t color_control
;
147 color_control
= S_028808_MODE(V_028808_CB_NORMAL
);
148 if (state
->logicop_enable
) {
149 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
151 color_control
|= S_028808_ROP3(0xcc);
153 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
155 si_pm4_set_reg(pm4
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, ~0);
156 si_pm4_set_reg(pm4
, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, ~0);
158 blend
->cb_target_mask
= 0;
159 for (int i
= 0; i
< 8; i
++) {
160 /* state->rt entries > 0 only written if independent blending */
161 const int j
= state
->independent_blend_enable
? i
: 0;
163 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
164 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
165 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
166 unsigned eqA
= state
->rt
[j
].alpha_func
;
167 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
168 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
170 unsigned blend_cntl
= 0;
172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
173 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
175 if (!state
->rt
[j
].blend_enable
) {
176 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
180 blend_cntl
|= S_028780_ENABLE(1);
181 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
182 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
183 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
185 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
186 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
187 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
188 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
189 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
191 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
197 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
199 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
200 si_pm4_bind_state(rctx
, blend
, (struct si_state_blend
*)state
);
201 si_update_fb_blend_state(rctx
);
204 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
206 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
207 si_pm4_delete_state(rctx
, blend
, (struct si_state_blend
*)state
);
210 static void si_set_blend_color(struct pipe_context
*ctx
,
211 const struct pipe_blend_color
*state
)
213 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
214 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
219 si_pm4_set_reg(pm4
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
220 si_pm4_set_reg(pm4
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
221 si_pm4_set_reg(pm4
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
222 si_pm4_set_reg(pm4
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
224 si_pm4_set_state(rctx
, blend_color
, pm4
);
228 * Clipping, scissors and viewport
231 static void si_set_clip_state(struct pipe_context
*ctx
,
232 const struct pipe_clip_state
*state
)
234 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
235 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
240 for (int i
= 0; i
< 6; i
++) {
241 si_pm4_set_reg(pm4
, R_0285BC_PA_CL_UCP_0_X
+ i
* 16,
242 fui(state
->ucp
[i
][0]));
243 si_pm4_set_reg(pm4
, R_0285C0_PA_CL_UCP_0_Y
+ i
* 16,
244 fui(state
->ucp
[i
][1]));
245 si_pm4_set_reg(pm4
, R_0285C4_PA_CL_UCP_0_Z
+ i
* 16,
246 fui(state
->ucp
[i
][2]));
247 si_pm4_set_reg(pm4
, R_0285C8_PA_CL_UCP_0_W
+ i
* 16,
248 fui(state
->ucp
[i
][3]));
251 si_pm4_set_state(rctx
, clip
, pm4
);
254 static void si_set_scissor_state(struct pipe_context
*ctx
,
255 const struct pipe_scissor_state
*state
)
257 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
258 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
264 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
265 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
266 si_pm4_set_reg(pm4
, R_028210_PA_SC_CLIPRECT_0_TL
, tl
);
267 si_pm4_set_reg(pm4
, R_028214_PA_SC_CLIPRECT_0_BR
, br
);
268 si_pm4_set_reg(pm4
, R_028218_PA_SC_CLIPRECT_1_TL
, tl
);
269 si_pm4_set_reg(pm4
, R_02821C_PA_SC_CLIPRECT_1_BR
, br
);
270 si_pm4_set_reg(pm4
, R_028220_PA_SC_CLIPRECT_2_TL
, tl
);
271 si_pm4_set_reg(pm4
, R_028224_PA_SC_CLIPRECT_2_BR
, br
);
272 si_pm4_set_reg(pm4
, R_028228_PA_SC_CLIPRECT_3_TL
, tl
);
273 si_pm4_set_reg(pm4
, R_02822C_PA_SC_CLIPRECT_3_BR
, br
);
275 si_pm4_set_state(rctx
, scissor
, pm4
);
278 static void si_set_viewport_state(struct pipe_context
*ctx
,
279 const struct pipe_viewport_state
*state
)
281 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
282 struct si_state_viewport
*viewport
= CALLOC_STRUCT(si_state_viewport
);
283 struct si_pm4_state
*pm4
= &viewport
->pm4
;
285 if (viewport
== NULL
)
288 viewport
->viewport
= *state
;
289 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000);
290 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000);
291 si_pm4_set_reg(pm4
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
292 si_pm4_set_reg(pm4
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
293 si_pm4_set_reg(pm4
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
294 si_pm4_set_reg(pm4
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
295 si_pm4_set_reg(pm4
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
296 si_pm4_set_reg(pm4
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
297 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
299 si_pm4_set_state(rctx
, viewport
, viewport
);
303 * inferred state between framebuffer and rasterizer
305 static void si_update_fb_rs_state(struct r600_context
*rctx
)
307 struct si_state_rasterizer
*rs
= rctx
->queued
.named
.rasterizer
;
308 struct si_pm4_state
*pm4
;
309 unsigned offset_db_fmt_cntl
= 0, depth
;
312 if (!rs
|| !rctx
->framebuffer
.zsbuf
)
315 offset_units
= rctx
->queued
.named
.rasterizer
->offset_units
;
316 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
317 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
318 case PIPE_FORMAT_X8Z24_UNORM
:
319 case PIPE_FORMAT_Z24X8_UNORM
:
320 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
322 offset_units
*= 2.0f
;
324 case PIPE_FORMAT_Z32_FLOAT
:
325 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
327 offset_units
*= 1.0f
;
328 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
330 case PIPE_FORMAT_Z16_UNORM
:
332 offset_units
*= 4.0f
;
338 pm4
= CALLOC_STRUCT(si_pm4_state
);
339 /* FIXME some of those reg can be computed with cso */
340 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
341 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
342 fui(rctx
->queued
.named
.rasterizer
->offset_scale
));
343 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
344 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
345 fui(rctx
->queued
.named
.rasterizer
->offset_scale
));
346 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
347 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, offset_db_fmt_cntl
);
349 si_pm4_set_state(rctx
, fb_rs
, pm4
);
356 static uint32_t si_translate_fill(uint32_t func
)
359 case PIPE_POLYGON_MODE_FILL
:
360 return V_028814_X_DRAW_TRIANGLES
;
361 case PIPE_POLYGON_MODE_LINE
:
362 return V_028814_X_DRAW_LINES
;
363 case PIPE_POLYGON_MODE_POINT
:
364 return V_028814_X_DRAW_POINTS
;
367 return V_028814_X_DRAW_POINTS
;
371 static void *si_create_rs_state(struct pipe_context
*ctx
,
372 const struct pipe_rasterizer_state
*state
)
374 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
375 struct si_pm4_state
*pm4
= &rs
->pm4
;
377 unsigned prov_vtx
= 1, polygon_dual_mode
;
379 float psize_min
, psize_max
;
385 rs
->two_side
= state
->light_twoside
;
387 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
388 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
390 if (state
->flatshade_first
)
393 rs
->flatshade
= state
->flatshade
;
394 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
395 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
396 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
397 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
398 rs
->pa_su_sc_mode_cntl
=
399 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
400 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
401 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
402 S_028814_FACE(!state
->front_ccw
) |
403 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
404 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
405 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
406 S_028814_POLY_MODE(polygon_dual_mode
) |
407 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
408 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
));
409 rs
->pa_cl_clip_cntl
=
410 S_028810_PS_UCP_MODE(3) |
411 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
412 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
413 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
414 rs
->pa_cl_vs_out_cntl
=
415 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
416 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
);
418 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
421 rs
->offset_units
= state
->offset_units
;
422 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
424 /* XXX: Flat shading hangs the GPU */
425 tmp
= S_0286D4_FLAT_SHADE_ENA(0);
426 if (state
->sprite_coord_enable
) {
427 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
428 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
429 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
430 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
431 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
);
432 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
433 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
436 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
438 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000);
439 /* point size 12.4 fixed point */
440 tmp
= (unsigned)(state
->point_size
* 8.0);
441 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
443 if (state
->point_size_per_vertex
) {
444 psize_min
= util_get_min_point_size(state
);
447 /* Force the point size to be as if the vertex output was disabled. */
448 psize_min
= state
->point_size
;
449 psize_max
= state
->point_size
;
451 /* Divide by two, because 0.5 = 1 pixel. */
452 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
453 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
454 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
456 tmp
= (unsigned)state
->line_width
* 8;
457 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
458 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
459 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
));
461 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
, 0x00000400);
462 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
463 S_028BE4_PIX_CENTER(state
->gl_rasterization_rules
));
464 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000);
465 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000);
466 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000);
467 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000);
469 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
470 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
);
475 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
477 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
478 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
484 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
485 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
486 rctx
->pa_su_sc_mode_cntl
= rs
->pa_su_sc_mode_cntl
;
487 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
488 rctx
->pa_cl_vs_out_cntl
= rs
->pa_cl_vs_out_cntl
;
490 si_pm4_bind_state(rctx
, rasterizer
, rs
);
491 si_update_fb_rs_state(rctx
);
494 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
496 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
497 si_pm4_delete_state(rctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
501 * infeered state between dsa and stencil ref
503 static void si_update_dsa_stencil_ref(struct r600_context
*rctx
)
505 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
506 struct pipe_stencil_ref
*ref
= &rctx
->stencil_ref
;
507 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
512 si_pm4_set_reg(pm4
, R_028430_DB_STENCILREFMASK
,
513 S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
514 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
515 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
516 S_028430_STENCILOPVAL(1));
517 si_pm4_set_reg(pm4
, R_028434_DB_STENCILREFMASK_BF
,
518 S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
519 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
520 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
521 S_028434_STENCILOPVAL_BF(1));
523 si_pm4_set_state(rctx
, dsa_stencil_ref
, pm4
);
526 static void si_set_pipe_stencil_ref(struct pipe_context
*ctx
,
527 const struct pipe_stencil_ref
*state
)
529 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
530 rctx
->stencil_ref
= *state
;
531 si_update_dsa_stencil_ref(rctx
);
539 static uint32_t si_translate_stencil_op(int s_op
)
542 case PIPE_STENCIL_OP_KEEP
:
543 return V_02842C_STENCIL_KEEP
;
544 case PIPE_STENCIL_OP_ZERO
:
545 return V_02842C_STENCIL_ZERO
;
546 case PIPE_STENCIL_OP_REPLACE
:
547 return V_02842C_STENCIL_REPLACE_TEST
;
548 case PIPE_STENCIL_OP_INCR
:
549 return V_02842C_STENCIL_ADD_CLAMP
;
550 case PIPE_STENCIL_OP_DECR
:
551 return V_02842C_STENCIL_SUB_CLAMP
;
552 case PIPE_STENCIL_OP_INCR_WRAP
:
553 return V_02842C_STENCIL_ADD_WRAP
;
554 case PIPE_STENCIL_OP_DECR_WRAP
:
555 return V_02842C_STENCIL_SUB_WRAP
;
556 case PIPE_STENCIL_OP_INVERT
:
557 return V_02842C_STENCIL_INVERT
;
559 R600_ERR("Unknown stencil op %d", s_op
);
566 static void *si_create_dsa_state(struct pipe_context
*ctx
,
567 const struct pipe_depth_stencil_alpha_state
*state
)
569 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
570 struct si_pm4_state
*pm4
= &dsa
->pm4
;
571 unsigned db_depth_control
;
572 unsigned db_render_override
, db_render_control
;
573 uint32_t db_stencil_control
= 0;
579 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
580 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
581 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
582 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
584 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
585 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
586 S_028800_ZFUNC(state
->depth
.func
);
589 if (state
->stencil
[0].enabled
) {
590 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
591 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
592 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
593 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
594 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
596 if (state
->stencil
[1].enabled
) {
597 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
598 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
599 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
600 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
601 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
606 if (state
->alpha
.enabled
) {
607 dsa
->alpha_func
= state
->alpha
.func
;
608 dsa
->alpha_ref
= state
->alpha
.ref_value
;
610 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
614 db_render_control
= 0;
615 db_render_override
= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
616 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
617 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
618 /* TODO db_render_override depends on query */
619 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, 0x00000000);
620 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, 0x00000000);
621 si_pm4_set_reg(pm4
, R_028028_DB_STENCIL_CLEAR
, 0x00000000);
622 si_pm4_set_reg(pm4
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000);
623 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
624 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
625 si_pm4_set_reg(pm4
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
626 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
627 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
628 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
629 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
630 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
631 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
, 0x0000AA00);
632 dsa
->db_render_override
= db_render_override
;
637 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
639 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
640 struct si_state_dsa
*dsa
= state
;
645 si_pm4_bind_state(rctx
, dsa
, dsa
);
646 si_update_dsa_stencil_ref(rctx
);
649 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
651 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
652 si_pm4_delete_state(rctx
, dsa
, (struct si_state_dsa
*)state
);
655 static void *si_create_db_flush_dsa(struct r600_context
*rctx
, bool copy_depth
,
658 struct pipe_depth_stencil_alpha_state dsa
;
659 struct si_state_dsa
*state
;
661 memset(&dsa
, 0, sizeof(dsa
));
663 state
= rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
664 if (copy_depth
|| copy_stencil
) {
665 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
666 S_028000_DEPTH_COPY(copy_depth
) |
667 S_028000_STENCIL_COPY(copy_stencil
) |
668 S_028000_COPY_CENTROID(1));
670 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
671 S_028000_DEPTH_COMPRESS_DISABLE(1) |
672 S_028000_STENCIL_COMPRESS_DISABLE(1));
673 si_pm4_set_reg(&state
->pm4
, R_02800C_DB_RENDER_OVERRIDE
,
674 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
675 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
676 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
) |
677 S_02800C_DISABLE_TILE_RATE_TILES(1));
686 static uint32_t si_translate_colorformat(enum pipe_format format
)
690 case PIPE_FORMAT_A8_UNORM
:
691 case PIPE_FORMAT_A8_SNORM
:
692 case PIPE_FORMAT_A8_UINT
:
693 case PIPE_FORMAT_A8_SINT
:
694 case PIPE_FORMAT_I8_UNORM
:
695 case PIPE_FORMAT_I8_SNORM
:
696 case PIPE_FORMAT_I8_UINT
:
697 case PIPE_FORMAT_I8_SINT
:
698 case PIPE_FORMAT_L8_UNORM
:
699 case PIPE_FORMAT_L8_SNORM
:
700 case PIPE_FORMAT_L8_UINT
:
701 case PIPE_FORMAT_L8_SINT
:
702 case PIPE_FORMAT_L8_SRGB
:
703 case PIPE_FORMAT_R8_UNORM
:
704 case PIPE_FORMAT_R8_SNORM
:
705 case PIPE_FORMAT_R8_UINT
:
706 case PIPE_FORMAT_R8_SINT
:
707 return V_028C70_COLOR_8
;
709 /* 16-bit buffers. */
710 case PIPE_FORMAT_B5G6R5_UNORM
:
711 return V_028C70_COLOR_5_6_5
;
713 case PIPE_FORMAT_B5G5R5A1_UNORM
:
714 case PIPE_FORMAT_B5G5R5X1_UNORM
:
715 return V_028C70_COLOR_1_5_5_5
;
717 case PIPE_FORMAT_B4G4R4A4_UNORM
:
718 case PIPE_FORMAT_B4G4R4X4_UNORM
:
719 return V_028C70_COLOR_4_4_4_4
;
721 case PIPE_FORMAT_L8A8_UNORM
:
722 case PIPE_FORMAT_L8A8_SNORM
:
723 case PIPE_FORMAT_L8A8_UINT
:
724 case PIPE_FORMAT_L8A8_SINT
:
725 case PIPE_FORMAT_R8G8_SNORM
:
726 case PIPE_FORMAT_R8G8_UNORM
:
727 case PIPE_FORMAT_R8G8_UINT
:
728 case PIPE_FORMAT_R8G8_SINT
:
729 return V_028C70_COLOR_8_8
;
731 case PIPE_FORMAT_Z16_UNORM
:
732 case PIPE_FORMAT_R16_UNORM
:
733 case PIPE_FORMAT_R16_SNORM
:
734 case PIPE_FORMAT_R16_UINT
:
735 case PIPE_FORMAT_R16_SINT
:
736 case PIPE_FORMAT_R16_FLOAT
:
737 case PIPE_FORMAT_L16_UNORM
:
738 case PIPE_FORMAT_L16_SNORM
:
739 case PIPE_FORMAT_L16_FLOAT
:
740 case PIPE_FORMAT_I16_UNORM
:
741 case PIPE_FORMAT_I16_SNORM
:
742 case PIPE_FORMAT_I16_FLOAT
:
743 case PIPE_FORMAT_A16_UNORM
:
744 case PIPE_FORMAT_A16_SNORM
:
745 case PIPE_FORMAT_A16_FLOAT
:
746 return V_028C70_COLOR_16
;
748 /* 32-bit buffers. */
749 case PIPE_FORMAT_A8B8G8R8_SRGB
:
750 case PIPE_FORMAT_A8B8G8R8_UNORM
:
751 case PIPE_FORMAT_A8R8G8B8_UNORM
:
752 case PIPE_FORMAT_B8G8R8A8_SRGB
:
753 case PIPE_FORMAT_B8G8R8A8_UNORM
:
754 case PIPE_FORMAT_B8G8R8X8_UNORM
:
755 case PIPE_FORMAT_R8G8B8A8_SNORM
:
756 case PIPE_FORMAT_R8G8B8A8_UNORM
:
757 case PIPE_FORMAT_R8G8B8X8_UNORM
:
758 case PIPE_FORMAT_R8G8B8X8_SNORM
:
759 case PIPE_FORMAT_R8G8B8X8_SRGB
:
760 case PIPE_FORMAT_R8G8B8X8_UINT
:
761 case PIPE_FORMAT_R8G8B8X8_SINT
:
762 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
763 case PIPE_FORMAT_X8B8G8R8_UNORM
:
764 case PIPE_FORMAT_X8R8G8B8_UNORM
:
765 case PIPE_FORMAT_R8G8B8_UNORM
:
766 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
767 case PIPE_FORMAT_R8G8B8A8_USCALED
:
768 case PIPE_FORMAT_R8G8B8A8_SINT
:
769 case PIPE_FORMAT_R8G8B8A8_UINT
:
770 return V_028C70_COLOR_8_8_8_8
;
772 case PIPE_FORMAT_R10G10B10A2_UNORM
:
773 case PIPE_FORMAT_R10G10B10X2_SNORM
:
774 case PIPE_FORMAT_B10G10R10A2_UNORM
:
775 case PIPE_FORMAT_B10G10R10A2_UINT
:
776 case PIPE_FORMAT_B10G10R10X2_UNORM
:
777 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
778 return V_028C70_COLOR_2_10_10_10
;
780 case PIPE_FORMAT_Z24X8_UNORM
:
781 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
782 return V_028C70_COLOR_8_24
;
784 case PIPE_FORMAT_S8X24_UINT
:
785 case PIPE_FORMAT_X8Z24_UNORM
:
786 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
787 return V_028C70_COLOR_24_8
;
789 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
790 return V_028C70_COLOR_X24_8_32_FLOAT
;
792 case PIPE_FORMAT_I32_FLOAT
:
793 case PIPE_FORMAT_L32_FLOAT
:
794 case PIPE_FORMAT_R32_FLOAT
:
795 case PIPE_FORMAT_A32_FLOAT
:
796 case PIPE_FORMAT_Z32_FLOAT
:
797 return V_028C70_COLOR_32
;
799 case PIPE_FORMAT_L16A16_UNORM
:
800 case PIPE_FORMAT_L16A16_SNORM
:
801 case PIPE_FORMAT_L16A16_FLOAT
:
802 case PIPE_FORMAT_R16G16_SSCALED
:
803 case PIPE_FORMAT_R16G16_UNORM
:
804 case PIPE_FORMAT_R16G16_SNORM
:
805 case PIPE_FORMAT_R16G16_UINT
:
806 case PIPE_FORMAT_R16G16_SINT
:
807 case PIPE_FORMAT_R16G16_FLOAT
:
808 return V_028C70_COLOR_16_16
;
810 case PIPE_FORMAT_R11G11B10_FLOAT
:
811 return V_028C70_COLOR_10_11_11
;
813 /* 64-bit buffers. */
814 case PIPE_FORMAT_R16G16B16A16_UINT
:
815 case PIPE_FORMAT_R16G16B16A16_SINT
:
816 case PIPE_FORMAT_R16G16B16A16_USCALED
:
817 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
818 case PIPE_FORMAT_R16G16B16A16_UNORM
:
819 case PIPE_FORMAT_R16G16B16A16_SNORM
:
820 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
821 case PIPE_FORMAT_R16G16B16X16_UNORM
:
822 case PIPE_FORMAT_R16G16B16X16_SNORM
:
823 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
824 case PIPE_FORMAT_R16G16B16X16_UINT
:
825 case PIPE_FORMAT_R16G16B16X16_SINT
:
826 return V_028C70_COLOR_16_16_16_16
;
828 case PIPE_FORMAT_L32A32_FLOAT
:
829 case PIPE_FORMAT_L32A32_UINT
:
830 case PIPE_FORMAT_L32A32_SINT
:
831 case PIPE_FORMAT_R32G32_FLOAT
:
832 case PIPE_FORMAT_R32G32_USCALED
:
833 case PIPE_FORMAT_R32G32_SSCALED
:
834 case PIPE_FORMAT_R32G32_SINT
:
835 case PIPE_FORMAT_R32G32_UINT
:
836 return V_028C70_COLOR_32_32
;
838 /* 128-bit buffers. */
839 case PIPE_FORMAT_R32G32B32A32_SNORM
:
840 case PIPE_FORMAT_R32G32B32A32_UNORM
:
841 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
842 case PIPE_FORMAT_R32G32B32A32_USCALED
:
843 case PIPE_FORMAT_R32G32B32A32_SINT
:
844 case PIPE_FORMAT_R32G32B32A32_UINT
:
845 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
846 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
847 case PIPE_FORMAT_R32G32B32X32_UINT
:
848 case PIPE_FORMAT_R32G32B32X32_SINT
:
849 return V_028C70_COLOR_32_32_32_32
;
852 case PIPE_FORMAT_UYVY
:
853 case PIPE_FORMAT_YUYV
:
854 /* 96-bit buffers. */
855 case PIPE_FORMAT_R32G32B32_FLOAT
:
857 case PIPE_FORMAT_L4A4_UNORM
:
858 case PIPE_FORMAT_R4A4_UNORM
:
859 case PIPE_FORMAT_A4R4_UNORM
:
861 return V_028C70_COLOR_INVALID
; /* Unsupported. */
865 static uint32_t si_translate_colorswap(enum pipe_format format
)
869 case PIPE_FORMAT_L4A4_UNORM
:
870 case PIPE_FORMAT_A4R4_UNORM
:
871 return V_028C70_SWAP_ALT
;
873 case PIPE_FORMAT_A8_UNORM
:
874 case PIPE_FORMAT_A8_SNORM
:
875 case PIPE_FORMAT_A8_UINT
:
876 case PIPE_FORMAT_A8_SINT
:
877 case PIPE_FORMAT_R4A4_UNORM
:
878 return V_028C70_SWAP_ALT_REV
;
879 case PIPE_FORMAT_I8_UNORM
:
880 case PIPE_FORMAT_I8_SNORM
:
881 case PIPE_FORMAT_L8_UNORM
:
882 case PIPE_FORMAT_L8_SNORM
:
883 case PIPE_FORMAT_I8_UINT
:
884 case PIPE_FORMAT_I8_SINT
:
885 case PIPE_FORMAT_L8_UINT
:
886 case PIPE_FORMAT_L8_SINT
:
887 case PIPE_FORMAT_L8_SRGB
:
888 case PIPE_FORMAT_R8_UNORM
:
889 case PIPE_FORMAT_R8_SNORM
:
890 case PIPE_FORMAT_R8_UINT
:
891 case PIPE_FORMAT_R8_SINT
:
892 return V_028C70_SWAP_STD
;
894 /* 16-bit buffers. */
895 case PIPE_FORMAT_B5G6R5_UNORM
:
896 return V_028C70_SWAP_STD_REV
;
898 case PIPE_FORMAT_B5G5R5A1_UNORM
:
899 case PIPE_FORMAT_B5G5R5X1_UNORM
:
900 return V_028C70_SWAP_ALT
;
902 case PIPE_FORMAT_B4G4R4A4_UNORM
:
903 case PIPE_FORMAT_B4G4R4X4_UNORM
:
904 return V_028C70_SWAP_ALT
;
906 case PIPE_FORMAT_Z16_UNORM
:
907 return V_028C70_SWAP_STD
;
909 case PIPE_FORMAT_L8A8_UNORM
:
910 case PIPE_FORMAT_L8A8_SNORM
:
911 case PIPE_FORMAT_L8A8_UINT
:
912 case PIPE_FORMAT_L8A8_SINT
:
913 return V_028C70_SWAP_ALT
;
914 case PIPE_FORMAT_R8G8_SNORM
:
915 case PIPE_FORMAT_R8G8_UNORM
:
916 case PIPE_FORMAT_R8G8_UINT
:
917 case PIPE_FORMAT_R8G8_SINT
:
918 return V_028C70_SWAP_STD
;
920 case PIPE_FORMAT_I16_UNORM
:
921 case PIPE_FORMAT_I16_SNORM
:
922 case PIPE_FORMAT_I16_FLOAT
:
923 case PIPE_FORMAT_L16_UNORM
:
924 case PIPE_FORMAT_L16_SNORM
:
925 case PIPE_FORMAT_L16_FLOAT
:
926 case PIPE_FORMAT_R16_UNORM
:
927 case PIPE_FORMAT_R16_SNORM
:
928 case PIPE_FORMAT_R16_UINT
:
929 case PIPE_FORMAT_R16_SINT
:
930 case PIPE_FORMAT_R16_FLOAT
:
931 return V_028C70_SWAP_STD
;
933 case PIPE_FORMAT_A16_UNORM
:
934 case PIPE_FORMAT_A16_SNORM
:
935 case PIPE_FORMAT_A16_FLOAT
:
936 return V_028C70_SWAP_ALT_REV
;
938 /* 32-bit buffers. */
939 case PIPE_FORMAT_A8B8G8R8_SRGB
:
940 return V_028C70_SWAP_STD_REV
;
941 case PIPE_FORMAT_B8G8R8A8_SRGB
:
942 return V_028C70_SWAP_ALT
;
944 case PIPE_FORMAT_B8G8R8A8_UNORM
:
945 case PIPE_FORMAT_B8G8R8X8_UNORM
:
946 return V_028C70_SWAP_ALT
;
948 case PIPE_FORMAT_A8R8G8B8_UNORM
:
949 case PIPE_FORMAT_X8R8G8B8_UNORM
:
950 return V_028C70_SWAP_ALT_REV
;
951 case PIPE_FORMAT_R8G8B8A8_SNORM
:
952 case PIPE_FORMAT_R8G8B8A8_UNORM
:
953 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
954 case PIPE_FORMAT_R8G8B8A8_USCALED
:
955 case PIPE_FORMAT_R8G8B8A8_SINT
:
956 case PIPE_FORMAT_R8G8B8A8_UINT
:
957 case PIPE_FORMAT_R8G8B8X8_UNORM
:
958 case PIPE_FORMAT_R8G8B8X8_SNORM
:
959 case PIPE_FORMAT_R8G8B8X8_SRGB
:
960 case PIPE_FORMAT_R8G8B8X8_UINT
:
961 case PIPE_FORMAT_R8G8B8X8_SINT
:
962 return V_028C70_SWAP_STD
;
964 case PIPE_FORMAT_A8B8G8R8_UNORM
:
965 case PIPE_FORMAT_X8B8G8R8_UNORM
:
966 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
967 return V_028C70_SWAP_STD_REV
;
969 case PIPE_FORMAT_Z24X8_UNORM
:
970 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
971 return V_028C70_SWAP_STD
;
973 case PIPE_FORMAT_S8X24_UINT
:
974 case PIPE_FORMAT_X8Z24_UNORM
:
975 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
976 return V_028C70_SWAP_STD_REV
;
978 case PIPE_FORMAT_R10G10B10A2_UNORM
:
979 case PIPE_FORMAT_R10G10B10X2_SNORM
:
980 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
981 return V_028C70_SWAP_STD
;
983 case PIPE_FORMAT_B10G10R10A2_UNORM
:
984 case PIPE_FORMAT_B10G10R10A2_UINT
:
985 case PIPE_FORMAT_B10G10R10X2_UNORM
:
986 return V_028C70_SWAP_ALT
;
988 case PIPE_FORMAT_R11G11B10_FLOAT
:
989 case PIPE_FORMAT_I32_FLOAT
:
990 case PIPE_FORMAT_L32_FLOAT
:
991 case PIPE_FORMAT_R32_FLOAT
:
992 case PIPE_FORMAT_R32_UINT
:
993 case PIPE_FORMAT_R32_SINT
:
994 case PIPE_FORMAT_Z32_FLOAT
:
995 case PIPE_FORMAT_R16G16_FLOAT
:
996 case PIPE_FORMAT_R16G16_UNORM
:
997 case PIPE_FORMAT_R16G16_SNORM
:
998 case PIPE_FORMAT_R16G16_UINT
:
999 case PIPE_FORMAT_R16G16_SINT
:
1000 return V_028C70_SWAP_STD
;
1002 case PIPE_FORMAT_L16A16_UNORM
:
1003 case PIPE_FORMAT_L16A16_SNORM
:
1004 case PIPE_FORMAT_L16A16_FLOAT
:
1005 return V_028C70_SWAP_ALT
;
1007 case PIPE_FORMAT_A32_FLOAT
:
1008 return V_028C70_SWAP_ALT_REV
;
1010 /* 64-bit buffers. */
1011 case PIPE_FORMAT_R32G32_FLOAT
:
1012 case PIPE_FORMAT_R32G32_UINT
:
1013 case PIPE_FORMAT_R32G32_SINT
:
1014 case PIPE_FORMAT_R16G16B16A16_UNORM
:
1015 case PIPE_FORMAT_R16G16B16A16_SNORM
:
1016 case PIPE_FORMAT_R16G16B16A16_USCALED
:
1017 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
1018 case PIPE_FORMAT_R16G16B16A16_UINT
:
1019 case PIPE_FORMAT_R16G16B16A16_SINT
:
1020 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
1021 case PIPE_FORMAT_R16G16B16X16_UNORM
:
1022 case PIPE_FORMAT_R16G16B16X16_SNORM
:
1023 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
1024 case PIPE_FORMAT_R16G16B16X16_UINT
:
1025 case PIPE_FORMAT_R16G16B16X16_SINT
:
1026 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1027 return V_028C70_SWAP_STD
;
1029 case PIPE_FORMAT_L32A32_FLOAT
:
1030 case PIPE_FORMAT_L32A32_UINT
:
1031 case PIPE_FORMAT_L32A32_SINT
:
1032 return V_028C70_SWAP_ALT
;
1034 /* 128-bit buffers. */
1035 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
1036 case PIPE_FORMAT_R32G32B32A32_SNORM
:
1037 case PIPE_FORMAT_R32G32B32A32_UNORM
:
1038 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
1039 case PIPE_FORMAT_R32G32B32A32_USCALED
:
1040 case PIPE_FORMAT_R32G32B32A32_SINT
:
1041 case PIPE_FORMAT_R32G32B32A32_UINT
:
1042 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
1043 case PIPE_FORMAT_R32G32B32X32_UINT
:
1044 case PIPE_FORMAT_R32G32B32X32_SINT
:
1045 return V_028C70_SWAP_STD
;
1047 R600_ERR("unsupported colorswap format %d\n", format
);
1053 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1055 if (R600_BIG_ENDIAN
) {
1056 switch(colorformat
) {
1057 /* 8-bit buffers. */
1058 case V_028C70_COLOR_8
:
1059 return V_028C70_ENDIAN_NONE
;
1061 /* 16-bit buffers. */
1062 case V_028C70_COLOR_5_6_5
:
1063 case V_028C70_COLOR_1_5_5_5
:
1064 case V_028C70_COLOR_4_4_4_4
:
1065 case V_028C70_COLOR_16
:
1066 case V_028C70_COLOR_8_8
:
1067 return V_028C70_ENDIAN_8IN16
;
1069 /* 32-bit buffers. */
1070 case V_028C70_COLOR_8_8_8_8
:
1071 case V_028C70_COLOR_2_10_10_10
:
1072 case V_028C70_COLOR_8_24
:
1073 case V_028C70_COLOR_24_8
:
1074 case V_028C70_COLOR_16_16
:
1075 return V_028C70_ENDIAN_8IN32
;
1077 /* 64-bit buffers. */
1078 case V_028C70_COLOR_16_16_16_16
:
1079 return V_028C70_ENDIAN_8IN16
;
1081 case V_028C70_COLOR_32_32
:
1082 return V_028C70_ENDIAN_8IN32
;
1084 /* 128-bit buffers. */
1085 case V_028C70_COLOR_32_32_32_32
:
1086 return V_028C70_ENDIAN_8IN32
;
1088 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1091 return V_028C70_ENDIAN_NONE
;
1095 /* Returns the size in bits of the widest component of a CB format */
1096 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
1098 switch(colorformat
) {
1099 case V_028C70_COLOR_4_4_4_4
:
1102 case V_028C70_COLOR_1_5_5_5
:
1103 case V_028C70_COLOR_5_5_5_1
:
1106 case V_028C70_COLOR_5_6_5
:
1109 case V_028C70_COLOR_8
:
1110 case V_028C70_COLOR_8_8
:
1111 case V_028C70_COLOR_8_8_8_8
:
1114 case V_028C70_COLOR_10_10_10_2
:
1115 case V_028C70_COLOR_2_10_10_10
:
1118 case V_028C70_COLOR_10_11_11
:
1119 case V_028C70_COLOR_11_11_10
:
1122 case V_028C70_COLOR_16
:
1123 case V_028C70_COLOR_16_16
:
1124 case V_028C70_COLOR_16_16_16_16
:
1127 case V_028C70_COLOR_8_24
:
1128 case V_028C70_COLOR_24_8
:
1131 case V_028C70_COLOR_32
:
1132 case V_028C70_COLOR_32_32
:
1133 case V_028C70_COLOR_32_32_32_32
:
1134 case V_028C70_COLOR_X24_8_32_FLOAT
:
1138 assert(!"Unknown maximum component size");
1142 static uint32_t si_translate_dbformat(enum pipe_format format
)
1145 case PIPE_FORMAT_Z16_UNORM
:
1146 return V_028040_Z_16
;
1147 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1148 case PIPE_FORMAT_X8Z24_UNORM
:
1149 case PIPE_FORMAT_Z24X8_UNORM
:
1150 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1151 return V_028040_Z_24
; /* deprecated on SI */
1152 case PIPE_FORMAT_Z32_FLOAT
:
1153 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1154 return V_028040_Z_32_FLOAT
;
1156 return V_028040_Z_INVALID
;
1161 * Texture translation
1164 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1165 enum pipe_format format
,
1166 const struct util_format_description
*desc
,
1169 boolean uniform
= TRUE
;
1172 /* Colorspace (return non-RGB formats directly). */
1173 switch (desc
->colorspace
) {
1174 /* Depth stencil formats */
1175 case UTIL_FORMAT_COLORSPACE_ZS
:
1177 case PIPE_FORMAT_Z16_UNORM
:
1178 return V_008F14_IMG_DATA_FORMAT_16
;
1179 case PIPE_FORMAT_X24S8_UINT
:
1180 case PIPE_FORMAT_Z24X8_UNORM
:
1181 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1182 return V_008F14_IMG_DATA_FORMAT_8_24
;
1183 case PIPE_FORMAT_X8Z24_UNORM
:
1184 case PIPE_FORMAT_X32_S8X24_UINT
:
1185 case PIPE_FORMAT_S8X24_UINT
:
1186 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1187 return V_008F14_IMG_DATA_FORMAT_24_8
;
1188 case PIPE_FORMAT_S8_UINT
:
1189 return V_008F14_IMG_DATA_FORMAT_8
;
1190 case PIPE_FORMAT_Z32_FLOAT
:
1191 return V_008F14_IMG_DATA_FORMAT_32
;
1192 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1193 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1198 case UTIL_FORMAT_COLORSPACE_YUV
:
1199 goto out_unknown
; /* TODO */
1201 case UTIL_FORMAT_COLORSPACE_SRGB
:
1202 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1210 /* TODO compressed formats */
1212 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1213 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1214 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1215 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1218 /* R8G8Bx_SNORM - TODO CxV8U8 */
1220 /* See whether the components are of the same size. */
1221 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1222 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1225 /* Non-uniform formats. */
1227 switch(desc
->nr_channels
) {
1229 if (desc
->channel
[0].size
== 5 &&
1230 desc
->channel
[1].size
== 6 &&
1231 desc
->channel
[2].size
== 5) {
1232 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1236 if (desc
->channel
[0].size
== 5 &&
1237 desc
->channel
[1].size
== 5 &&
1238 desc
->channel
[2].size
== 5 &&
1239 desc
->channel
[3].size
== 1) {
1240 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1242 if (desc
->channel
[0].size
== 10 &&
1243 desc
->channel
[1].size
== 10 &&
1244 desc
->channel
[2].size
== 10 &&
1245 desc
->channel
[3].size
== 2) {
1246 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1253 if (first_non_void
< 0 || first_non_void
> 3)
1256 /* uniform formats */
1257 switch (desc
->channel
[first_non_void
].size
) {
1259 switch (desc
->nr_channels
) {
1260 #if 0 /* Not supported for render targets */
1262 return V_008F14_IMG_DATA_FORMAT_4_4
;
1265 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1269 switch (desc
->nr_channels
) {
1271 return V_008F14_IMG_DATA_FORMAT_8
;
1273 return V_008F14_IMG_DATA_FORMAT_8_8
;
1275 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1279 switch (desc
->nr_channels
) {
1281 return V_008F14_IMG_DATA_FORMAT_16
;
1283 return V_008F14_IMG_DATA_FORMAT_16_16
;
1285 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1289 switch (desc
->nr_channels
) {
1291 return V_008F14_IMG_DATA_FORMAT_32
;
1293 return V_008F14_IMG_DATA_FORMAT_32_32
;
1294 #if 0 /* Not supported for render targets */
1296 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1299 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1304 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1308 static unsigned si_tex_wrap(unsigned wrap
)
1312 case PIPE_TEX_WRAP_REPEAT
:
1313 return V_008F30_SQ_TEX_WRAP
;
1314 case PIPE_TEX_WRAP_CLAMP
:
1315 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1316 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1317 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1318 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1319 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1320 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1321 return V_008F30_SQ_TEX_MIRROR
;
1322 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1323 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1324 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1325 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1326 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1327 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1331 static unsigned si_tex_filter(unsigned filter
)
1335 case PIPE_TEX_FILTER_NEAREST
:
1336 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1337 case PIPE_TEX_FILTER_LINEAR
:
1338 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1342 static unsigned si_tex_mipfilter(unsigned filter
)
1345 case PIPE_TEX_MIPFILTER_NEAREST
:
1346 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1347 case PIPE_TEX_MIPFILTER_LINEAR
:
1348 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1350 case PIPE_TEX_MIPFILTER_NONE
:
1351 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1355 static unsigned si_tex_compare(unsigned compare
)
1359 case PIPE_FUNC_NEVER
:
1360 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1361 case PIPE_FUNC_LESS
:
1362 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1363 case PIPE_FUNC_EQUAL
:
1364 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1365 case PIPE_FUNC_LEQUAL
:
1366 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1367 case PIPE_FUNC_GREATER
:
1368 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1369 case PIPE_FUNC_NOTEQUAL
:
1370 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1371 case PIPE_FUNC_GEQUAL
:
1372 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1373 case PIPE_FUNC_ALWAYS
:
1374 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1378 static unsigned si_tex_dim(unsigned dim
)
1382 case PIPE_TEXTURE_1D
:
1383 return V_008F1C_SQ_RSRC_IMG_1D
;
1384 case PIPE_TEXTURE_1D_ARRAY
:
1385 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1386 case PIPE_TEXTURE_2D
:
1387 case PIPE_TEXTURE_RECT
:
1388 return V_008F1C_SQ_RSRC_IMG_2D
;
1389 case PIPE_TEXTURE_2D_ARRAY
:
1390 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1391 case PIPE_TEXTURE_3D
:
1392 return V_008F1C_SQ_RSRC_IMG_3D
;
1393 case PIPE_TEXTURE_CUBE
:
1394 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1399 * Format support testing
1402 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1404 return si_translate_texformat(screen
, format
, util_format_description(format
),
1405 util_format_get_first_non_void_channel(format
)) != ~0U;
1408 static uint32_t si_translate_vertexformat(struct pipe_screen
*screen
,
1409 enum pipe_format format
,
1410 const struct util_format_description
*desc
,
1413 unsigned type
= desc
->channel
[first_non_void
].type
;
1416 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1417 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1419 /* See whether the components are of the same size. */
1420 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1421 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1422 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1425 switch (desc
->channel
[first_non_void
].size
) {
1427 switch (desc
->nr_channels
) {
1429 return V_008F0C_BUF_DATA_FORMAT_8
;
1431 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1434 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1438 switch (desc
->nr_channels
) {
1440 return V_008F0C_BUF_DATA_FORMAT_16
;
1442 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1445 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1449 if (type
!= UTIL_FORMAT_TYPE_FLOAT
)
1450 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1452 switch (desc
->nr_channels
) {
1454 return V_008F0C_BUF_DATA_FORMAT_32
;
1456 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1458 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1460 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1465 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1468 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1470 const struct util_format_description
*desc
;
1472 unsigned data_format
;
1474 desc
= util_format_description(format
);
1475 first_non_void
= util_format_get_first_non_void_channel(format
);
1476 data_format
= si_translate_vertexformat(screen
, format
, desc
, first_non_void
);
1477 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1480 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1482 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1483 si_translate_colorswap(format
) != ~0U;
1486 static bool si_is_zs_format_supported(enum pipe_format format
)
1488 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1491 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1492 enum pipe_format format
,
1493 enum pipe_texture_target target
,
1494 unsigned sample_count
,
1497 unsigned retval
= 0;
1499 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1500 R600_ERR("r600: unsupported texture type %d\n", target
);
1504 if (!util_format_is_supported(format
, usage
))
1508 if (sample_count
> 1)
1511 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
1512 si_is_sampler_format_supported(screen
, format
)) {
1513 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1516 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1517 PIPE_BIND_DISPLAY_TARGET
|
1519 PIPE_BIND_SHARED
)) &&
1520 si_is_colorbuffer_format_supported(format
)) {
1522 (PIPE_BIND_RENDER_TARGET
|
1523 PIPE_BIND_DISPLAY_TARGET
|
1528 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1529 si_is_zs_format_supported(format
)) {
1530 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1533 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1534 si_is_vertex_format_supported(screen
, format
)) {
1535 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1538 if (usage
& PIPE_BIND_TRANSFER_READ
)
1539 retval
|= PIPE_BIND_TRANSFER_READ
;
1540 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1541 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1543 return retval
== usage
;
1546 static unsigned si_tile_mode_index(struct r600_resource_texture
*rtex
, unsigned level
)
1548 if (util_format_is_depth_or_stencil(rtex
->real_format
)) {
1549 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_1D
) {
1551 } else if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_2D
) {
1552 switch (rtex
->real_format
) {
1553 case PIPE_FORMAT_Z16_UNORM
:
1555 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1556 case PIPE_FORMAT_X8Z24_UNORM
:
1557 case PIPE_FORMAT_Z24X8_UNORM
:
1558 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1559 case PIPE_FORMAT_Z32_FLOAT
:
1560 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1568 switch (rtex
->surface
.level
[level
].mode
) {
1570 assert(!"Invalid surface mode");
1572 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1574 case RADEON_SURF_MODE_1D
:
1575 if (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)
1579 case RADEON_SURF_MODE_2D
:
1580 if (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) {
1581 switch (util_format_get_blocksize(rtex
->real_format
)) {
1587 assert(!"Invalid block size");
1593 switch (util_format_get_blocksize(rtex
->real_format
)) {
1610 * framebuffer handling
1613 static void si_cb(struct r600_context
*rctx
, struct si_pm4_state
*pm4
,
1614 const struct pipe_framebuffer_state
*state
, int cb
)
1616 struct r600_resource_texture
*rtex
;
1617 struct r600_surface
*surf
;
1618 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1619 unsigned pitch
, slice
;
1620 unsigned color_info
;
1621 unsigned tile_mode_index
;
1622 unsigned format
, swap
, ntype
, endian
;
1624 const struct util_format_description
*desc
;
1626 unsigned blend_clamp
= 0, blend_bypass
= 0;
1627 unsigned max_comp_size
;
1629 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1630 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1632 offset
= rtex
->surface
.level
[level
].offset
;
1633 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1634 offset
+= rtex
->surface
.level
[level
].slice_size
*
1635 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1637 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1638 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1643 tile_mode_index
= si_tile_mode_index(rtex
, level
);
1645 desc
= util_format_description(surf
->base
.format
);
1646 for (i
= 0; i
< 4; i
++) {
1647 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1651 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1652 ntype
= V_028C70_NUMBER_FLOAT
;
1654 ntype
= V_028C70_NUMBER_UNORM
;
1655 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1656 ntype
= V_028C70_NUMBER_SRGB
;
1657 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1658 if (desc
->channel
[i
].pure_integer
) {
1659 ntype
= V_028C70_NUMBER_SINT
;
1661 assert(desc
->channel
[i
].normalized
);
1662 ntype
= V_028C70_NUMBER_SNORM
;
1664 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1665 if (desc
->channel
[i
].pure_integer
) {
1666 ntype
= V_028C70_NUMBER_UINT
;
1668 assert(desc
->channel
[i
].normalized
);
1669 ntype
= V_028C70_NUMBER_UNORM
;
1674 format
= si_translate_colorformat(surf
->base
.format
);
1675 if (format
== V_028C70_COLOR_INVALID
) {
1676 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
1678 assert(format
!= V_028C70_COLOR_INVALID
);
1679 swap
= si_translate_colorswap(surf
->base
.format
);
1680 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1681 endian
= V_028C70_ENDIAN_NONE
;
1683 endian
= si_colorformat_endian_swap(format
);
1686 /* blend clamp should be set for all NORM/SRGB types */
1687 if (ntype
== V_028C70_NUMBER_UNORM
||
1688 ntype
== V_028C70_NUMBER_SNORM
||
1689 ntype
== V_028C70_NUMBER_SRGB
)
1692 /* set blend bypass according to docs if SINT/UINT or
1693 8/24 COLOR variants */
1694 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1695 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1696 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1701 color_info
= S_028C70_FORMAT(format
) |
1702 S_028C70_COMP_SWAP(swap
) |
1703 S_028C70_BLEND_CLAMP(blend_clamp
) |
1704 S_028C70_BLEND_BYPASS(blend_bypass
) |
1705 S_028C70_NUMBER_TYPE(ntype
) |
1706 S_028C70_ENDIAN(endian
);
1708 offset
+= r600_resource_va(rctx
->context
.screen
, state
->cbufs
[cb
]->texture
);
1711 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1712 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1713 si_pm4_set_reg(pm4
, R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C, offset
);
1714 si_pm4_set_reg(pm4
, R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C, S_028C64_TILE_MAX(pitch
));
1715 si_pm4_set_reg(pm4
, R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C, S_028C68_TILE_MAX(slice
));
1717 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1718 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C, 0x00000000);
1720 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C,
1721 S_028C6C_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1722 S_028C6C_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
));
1724 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C, color_info
);
1725 si_pm4_set_reg(pm4
, R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C,
1726 S_028C74_TILE_MODE_INDEX(tile_mode_index
));
1728 /* Determine pixel shader export format */
1729 max_comp_size
= si_colorformat_max_comp_size(format
);
1730 if (ntype
== V_028C70_NUMBER_SRGB
||
1731 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
1732 max_comp_size
<= 10) ||
1733 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
1734 rctx
->export_16bpc
|= 1 << cb
;
1738 static void si_db(struct r600_context
*rctx
, struct si_pm4_state
*pm4
,
1739 const struct pipe_framebuffer_state
*state
)
1741 struct r600_resource_texture
*rtex
;
1742 struct r600_surface
*surf
;
1743 unsigned level
, pitch
, slice
, format
, tile_mode_index
;
1744 uint32_t z_info
, s_info
;
1745 uint64_t z_offs
, s_offs
;
1747 if (state
->zsbuf
== NULL
) {
1748 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, S_028040_FORMAT(V_028040_Z_INVALID
));
1749 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, S_028044_FORMAT(V_028044_STENCIL_INVALID
));
1753 surf
= (struct r600_surface
*)state
->zsbuf
;
1754 level
= surf
->base
.u
.tex
.level
;
1755 rtex
= (struct r600_resource_texture
*)surf
->base
.texture
;
1757 format
= si_translate_dbformat(rtex
->real_format
);
1759 if (format
== V_028040_Z_INVALID
) {
1760 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->real_format
);
1762 assert(format
!= V_028040_Z_INVALID
);
1764 s_offs
= z_offs
= r600_resource_va(rctx
->context
.screen
, surf
->base
.texture
);
1765 z_offs
+= rtex
->surface
.level
[level
].offset
;
1766 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
1771 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1772 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1777 z_info
= S_028040_FORMAT(format
);
1778 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1779 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
1781 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
1783 tile_mode_index
= si_tile_mode_index(rtex
, level
);
1784 if (tile_mode_index
< 4 || tile_mode_index
> 7) {
1785 R600_ERR("Invalid DB tiling mode %d!\n",
1786 rtex
->surface
.level
[level
].mode
);
1787 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, S_028040_FORMAT(V_028040_Z_INVALID
));
1788 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, S_028044_FORMAT(V_028044_STENCIL_INVALID
));
1791 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
1792 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
1794 si_pm4_set_reg(pm4
, R_028008_DB_DEPTH_VIEW
,
1795 S_028008_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1796 S_028008_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
));
1798 si_pm4_set_reg(pm4
, R_02803C_DB_DEPTH_INFO
, S_02803C_ADDR5_SWIZZLE_MASK(1));
1799 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, z_info
);
1800 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, s_info
);
1802 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1803 si_pm4_set_reg(pm4
, R_028048_DB_Z_READ_BASE
, z_offs
);
1804 si_pm4_set_reg(pm4
, R_02804C_DB_STENCIL_READ_BASE
, s_offs
);
1805 si_pm4_set_reg(pm4
, R_028050_DB_Z_WRITE_BASE
, z_offs
);
1806 si_pm4_set_reg(pm4
, R_028054_DB_STENCIL_WRITE_BASE
, s_offs
);
1808 si_pm4_set_reg(pm4
, R_028058_DB_DEPTH_SIZE
, S_028058_PITCH_TILE_MAX(pitch
));
1809 si_pm4_set_reg(pm4
, R_02805C_DB_DEPTH_SLICE
, S_02805C_SLICE_TILE_MAX(slice
));
1812 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
1813 const struct pipe_framebuffer_state
*state
)
1815 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1816 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
1817 uint32_t shader_mask
, tl
, br
;
1818 int tl_x
, tl_y
, br_x
, br_y
;
1823 si_pm4_inval_fb_cache(pm4
, state
->nr_cbufs
);
1826 si_pm4_inval_zsbuf_cache(pm4
);
1828 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
1831 rctx
->export_16bpc
= 0;
1832 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1833 si_cb(rctx
, pm4
, state
, i
);
1835 assert(!(rctx
->export_16bpc
& ~0xff));
1836 si_db(rctx
, pm4
, state
);
1839 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1840 shader_mask
|= 0xf << (i
* 4);
1844 br_x
= state
->width
;
1845 br_y
= state
->height
;
1847 tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
1848 br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
1850 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
);
1851 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
);
1852 si_pm4_set_reg(pm4
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
1853 si_pm4_set_reg(pm4
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
1854 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
);
1855 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
);
1856 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
);
1857 si_pm4_set_reg(pm4
, R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
);
1858 si_pm4_set_reg(pm4
, R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000);
1859 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
1860 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, shader_mask
);
1861 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
, 0x00000000);
1863 si_pm4_set_state(rctx
, framebuffer
, pm4
);
1864 si_update_fb_rs_state(rctx
);
1865 si_update_fb_blend_state(rctx
);
1872 /* Compute the key for the hw shader variant */
1873 static INLINE
struct si_shader_key
si_shader_selector_key(struct pipe_context
*ctx
,
1874 struct si_pipe_shader_selector
*sel
)
1876 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1877 struct si_shader_key key
;
1878 memset(&key
, 0, sizeof(key
));
1880 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
1881 if (sel
->fs_write_all
)
1882 key
.nr_cbufs
= rctx
->framebuffer
.nr_cbufs
;
1883 key
.export_16bpc
= rctx
->export_16bpc
;
1884 if (rctx
->queued
.named
.rasterizer
) {
1885 key
.color_two_side
= rctx
->queued
.named
.rasterizer
->two_side
;
1886 /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
1888 if (rctx
->queued
.named
.dsa
) {
1889 key
.alpha_func
= rctx
->queued
.named
.dsa
->alpha_func
;
1890 key
.alpha_ref
= rctx
->queued
.named
.dsa
->alpha_ref
;
1892 key
.alpha_func
= PIPE_FUNC_ALWAYS
;
1899 /* Select the hw shader variant depending on the current state.
1900 * (*dirty) is set to 1 if current variant was changed */
1901 int si_shader_select(struct pipe_context
*ctx
,
1902 struct si_pipe_shader_selector
*sel
,
1905 struct si_shader_key key
;
1906 struct si_pipe_shader
* shader
= NULL
;
1909 key
= si_shader_selector_key(ctx
, sel
);
1911 /* Check if we don't need to change anything.
1912 * This path is also used for most shaders that don't need multiple
1913 * variants, it will cost just a computation of the key and this
1915 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
1919 /* lookup if we have other variants in the list */
1920 if (sel
->num_shaders
> 1) {
1921 struct si_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
1923 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
1925 c
= c
->next_variant
;
1929 p
->next_variant
= c
->next_variant
;
1934 if (unlikely(!shader
)) {
1935 shader
= CALLOC(1, sizeof(struct si_pipe_shader
));
1936 shader
->selector
= sel
;
1938 r
= si_pipe_shader_create(ctx
, shader
, key
);
1940 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1942 sel
->current
= NULL
;
1946 /* We don't know the value of fs_write_all property until we built
1947 * at least one variant, so we may need to recompute the key (include
1948 * rctx->framebuffer.nr_cbufs) after building first variant. */
1949 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
1950 sel
->num_shaders
== 0 &&
1951 shader
->shader
.fs_write_all
) {
1952 sel
->fs_write_all
= 1;
1953 key
= si_shader_selector_key(ctx
, sel
);
1963 shader
->next_variant
= sel
->current
;
1964 sel
->current
= shader
;
1969 static void *si_create_shader_state(struct pipe_context
*ctx
,
1970 const struct pipe_shader_state
*state
,
1971 unsigned pipe_shader_type
)
1973 struct si_pipe_shader_selector
*sel
= CALLOC_STRUCT(si_pipe_shader_selector
);
1976 sel
->type
= pipe_shader_type
;
1977 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1978 sel
->so
= state
->stream_output
;
1980 r
= si_shader_select(ctx
, sel
, NULL
);
1989 static void *si_create_fs_state(struct pipe_context
*ctx
,
1990 const struct pipe_shader_state
*state
)
1992 return si_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
1995 static void *si_create_vs_state(struct pipe_context
*ctx
,
1996 const struct pipe_shader_state
*state
)
1998 return si_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
2001 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2003 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2004 struct si_pipe_shader_selector
*sel
= state
;
2006 if (rctx
->vs_shader
== sel
)
2009 rctx
->vs_shader
= sel
;
2011 if (sel
&& sel
->current
)
2012 si_pm4_bind_state(rctx
, vs
, sel
->current
->pm4
);
2014 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
2017 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2019 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2020 struct si_pipe_shader_selector
*sel
= state
;
2022 if (rctx
->ps_shader
== sel
)
2025 rctx
->ps_shader
= sel
;
2027 if (sel
&& sel
->current
)
2028 si_pm4_bind_state(rctx
, ps
, sel
->current
->pm4
);
2030 si_pm4_bind_state(rctx
, ps
, rctx
->dummy_pixel_shader
->pm4
);
2033 static void si_delete_shader_selector(struct pipe_context
*ctx
,
2034 struct si_pipe_shader_selector
*sel
)
2036 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2037 struct si_pipe_shader
*p
= sel
->current
, *c
;
2040 c
= p
->next_variant
;
2041 si_pm4_delete_state(rctx
, vs
, p
->pm4
);
2042 si_pipe_shader_destroy(ctx
, p
);
2051 static void si_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
2053 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2054 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2056 if (rctx
->vs_shader
== sel
) {
2057 rctx
->vs_shader
= NULL
;
2060 si_delete_shader_selector(ctx
, sel
);
2063 static void si_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
2065 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2066 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2068 if (rctx
->ps_shader
== sel
) {
2069 rctx
->ps_shader
= NULL
;
2072 si_delete_shader_selector(ctx
, sel
);
2079 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
2080 struct pipe_resource
*texture
,
2081 const struct pipe_sampler_view
*state
)
2083 struct si_pipe_sampler_view
*view
= CALLOC_STRUCT(si_pipe_sampler_view
);
2084 struct r600_resource_texture
*tmp
= (struct r600_resource_texture
*)texture
;
2085 const struct util_format_description
*desc
;
2086 unsigned format
, num_format
;
2088 unsigned char state_swizzle
[4], swizzle
[4];
2089 unsigned height
, depth
, width
;
2090 enum pipe_format pipe_format
= state
->format
;
2091 struct radeon_surface_level
*surflevel
;
2098 /* initialize base object */
2099 view
->base
= *state
;
2100 view
->base
.texture
= NULL
;
2101 pipe_reference(NULL
, &texture
->reference
);
2102 view
->base
.texture
= texture
;
2103 view
->base
.reference
.count
= 1;
2104 view
->base
.context
= ctx
;
2106 state_swizzle
[0] = state
->swizzle_r
;
2107 state_swizzle
[1] = state
->swizzle_g
;
2108 state_swizzle
[2] = state
->swizzle_b
;
2109 state_swizzle
[3] = state
->swizzle_a
;
2111 surflevel
= tmp
->surface
.level
;
2113 /* Texturing with separate depth and stencil. */
2114 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
2115 switch (pipe_format
) {
2116 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2117 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2119 case PIPE_FORMAT_X8Z24_UNORM
:
2120 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2121 /* Z24 is always stored like this. */
2122 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2124 case PIPE_FORMAT_X24S8_UINT
:
2125 case PIPE_FORMAT_S8X24_UINT
:
2126 case PIPE_FORMAT_X32_S8X24_UINT
:
2127 pipe_format
= PIPE_FORMAT_S8_UINT
;
2128 surflevel
= tmp
->surface
.stencil_level
;
2134 desc
= util_format_description(pipe_format
);
2136 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2137 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2138 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2140 switch (pipe_format
) {
2141 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2142 case PIPE_FORMAT_X24S8_UINT
:
2143 case PIPE_FORMAT_X32_S8X24_UINT
:
2144 case PIPE_FORMAT_X8Z24_UNORM
:
2145 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2148 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2151 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2154 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2156 switch (pipe_format
) {
2157 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2158 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2161 if (first_non_void
< 0) {
2162 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2163 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2164 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2166 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2168 switch (desc
->channel
[first_non_void
].type
) {
2169 case UTIL_FORMAT_TYPE_FLOAT
:
2170 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2172 case UTIL_FORMAT_TYPE_SIGNED
:
2173 if (desc
->channel
[first_non_void
].normalized
)
2174 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2175 else if (desc
->channel
[first_non_void
].pure_integer
)
2176 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2178 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2180 case UTIL_FORMAT_TYPE_UNSIGNED
:
2181 if (desc
->channel
[first_non_void
].normalized
)
2182 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2183 else if (desc
->channel
[first_non_void
].pure_integer
)
2184 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2186 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2191 format
= si_translate_texformat(ctx
->screen
, pipe_format
, desc
, first_non_void
);
2196 view
->resource
= &tmp
->resource
;
2198 /* not supported any more */
2199 //endian = si_colorformat_endian_swap(format);
2201 width
= surflevel
[0].npix_x
;
2202 height
= surflevel
[0].npix_y
;
2203 depth
= surflevel
[0].npix_z
;
2204 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
2206 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2208 depth
= texture
->array_size
;
2209 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2210 depth
= texture
->array_size
;
2213 va
= r600_resource_va(ctx
->screen
, texture
);
2214 va
+= surflevel
[0].offset
;
2215 view
->state
[0] = va
>> 8;
2216 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2217 S_008F14_DATA_FORMAT(format
) |
2218 S_008F14_NUM_FORMAT(num_format
));
2219 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2220 S_008F18_HEIGHT(height
- 1));
2221 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2222 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2223 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2224 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2225 S_008F1C_BASE_LEVEL(state
->u
.tex
.first_level
) |
2226 S_008F1C_LAST_LEVEL(state
->u
.tex
.last_level
) |
2227 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp
, 0)) |
2228 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2229 S_008F1C_TYPE(si_tex_dim(texture
->target
)));
2230 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2231 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2232 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
));
2239 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2240 struct pipe_sampler_view
*state
)
2242 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
2244 pipe_resource_reference(&state
->texture
, NULL
);
2248 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2249 const struct pipe_sampler_state
*state
)
2251 struct si_pipe_sampler_state
*rstate
= CALLOC_STRUCT(si_pipe_sampler_state
);
2252 union util_color uc
;
2253 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2254 unsigned border_color_type
;
2256 if (rstate
== NULL
) {
2260 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_A8R8G8B8_UNORM
, &uc
);
2263 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
2266 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2269 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
2271 default: /* Use border color pointer */
2272 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2275 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2276 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2277 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2278 (state
->max_anisotropy
& 0x7) << 9 | /* XXX */
2279 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2280 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2281 aniso_flag_offset
<< 16 | /* XXX */
2282 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2283 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2284 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2285 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2286 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
)) |
2287 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
)) |
2288 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2289 rstate
->val
[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2291 if (border_color_type
== V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2292 memcpy(rstate
->border_color
, state
->border_color
.f
,
2293 sizeof(rstate
->border_color
));
2299 static struct si_pm4_state
*si_set_sampler_view(struct r600_context
*rctx
,
2301 struct pipe_sampler_view
**views
,
2302 struct r600_textures_info
*samplers
,
2303 unsigned user_data_reg
)
2305 struct si_pipe_sampler_view
**resource
= (struct si_pipe_sampler_view
**)views
;
2306 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2312 si_pm4_inval_texture_cache(pm4
);
2314 si_pm4_sh_data_begin(pm4
);
2315 for (i
= 0; i
< count
; i
++) {
2316 pipe_sampler_view_reference(
2317 (struct pipe_sampler_view
**)&samplers
->views
[i
],
2321 struct r600_resource_texture
*rtex
=
2322 (struct r600_resource_texture
*)views
[i
]->texture
;
2324 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
2325 samplers
->depth_texture_mask
|= 1 << i
;
2327 samplers
->depth_texture_mask
&= ~(1 << i
);
2330 si_pm4_add_bo(pm4
, resource
[i
]->resource
, RADEON_USAGE_READ
);
2332 samplers
->depth_texture_mask
&= ~(1 << i
);
2335 for (j
= 0; j
< Elements(resource
[i
]->state
); ++j
) {
2336 si_pm4_sh_data_add(pm4
, resource
[i
] ? resource
[i
]->state
[j
] : 0);
2340 for (i
= count
; i
< NUM_TEX_UNITS
; i
++) {
2341 if (samplers
->views
[i
])
2342 pipe_sampler_view_reference((struct pipe_sampler_view
**)&samplers
->views
[i
], NULL
);
2345 si_pm4_sh_data_end(pm4
, user_data_reg
, SI_SGPR_RESOURCE
);
2348 rctx
->ps_samplers
.n_views
= count
;
2352 static void si_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
2353 struct pipe_sampler_view
**views
)
2355 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2356 struct si_pm4_state
*pm4
;
2358 pm4
= si_set_sampler_view(rctx
, count
, views
, &rctx
->vs_samplers
,
2359 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2360 si_pm4_set_state(rctx
, vs_sampler_views
, pm4
);
2363 static void si_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
2364 struct pipe_sampler_view
**views
)
2366 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2367 struct si_pm4_state
*pm4
;
2369 pm4
= si_set_sampler_view(rctx
, count
, views
, &rctx
->ps_samplers
,
2370 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2371 si_pm4_set_state(rctx
, ps_sampler_views
, pm4
);
2374 static struct si_pm4_state
*si_bind_sampler(struct r600_context
*rctx
, unsigned count
,
2376 struct r600_textures_info
*samplers
,
2377 unsigned user_data_reg
)
2379 struct si_pipe_sampler_state
**rstates
= (struct si_pipe_sampler_state
**)states
;
2380 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2381 uint32_t *border_color_table
= NULL
;
2387 si_pm4_inval_texture_cache(pm4
);
2389 si_pm4_sh_data_begin(pm4
);
2390 for (i
= 0; i
< count
; i
++) {
2392 G_008F3C_BORDER_COLOR_TYPE(rstates
[i
]->val
[3]) ==
2393 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2394 if (!rctx
->border_color_table
||
2395 ((rctx
->border_color_offset
+ count
- i
) &
2396 C_008F3C_BORDER_COLOR_PTR
)) {
2397 si_resource_reference(&rctx
->border_color_table
, NULL
);
2398 rctx
->border_color_offset
= 0;
2400 rctx
->border_color_table
=
2401 si_resource_create_custom(&rctx
->screen
->screen
,
2406 if (!border_color_table
) {
2407 border_color_table
=
2408 rctx
->ws
->buffer_map(rctx
->border_color_table
->cs_buf
,
2410 PIPE_TRANSFER_WRITE
|
2411 PIPE_TRANSFER_UNSYNCHRONIZED
);
2414 for (j
= 0; j
< 4; j
++) {
2415 union fi border_color
;
2417 border_color
.f
= rstates
[i
]->border_color
[j
];
2418 border_color_table
[4 * rctx
->border_color_offset
+ j
] =
2419 util_le32_to_cpu(border_color
.i
);
2422 rstates
[i
]->val
[3] &= C_008F3C_BORDER_COLOR_PTR
;
2423 rstates
[i
]->val
[3] |= S_008F3C_BORDER_COLOR_PTR(rctx
->border_color_offset
++);
2426 for (j
= 0; j
< Elements(rstates
[i
]->val
); ++j
) {
2427 si_pm4_sh_data_add(pm4
, rstates
[i
] ? rstates
[i
]->val
[j
] : 0);
2430 si_pm4_sh_data_end(pm4
, user_data_reg
, SI_SGPR_SAMPLER
);
2432 if (border_color_table
) {
2433 uint64_t va_offset
=
2434 r600_resource_va(&rctx
->screen
->screen
,
2435 (void*)rctx
->border_color_table
);
2437 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, va_offset
>> 8);
2438 rctx
->ws
->buffer_unmap(rctx
->border_color_table
->cs_buf
);
2439 si_pm4_add_bo(pm4
, rctx
->border_color_table
, RADEON_USAGE_READ
);
2442 memcpy(samplers
->samplers
, states
, sizeof(void*) * count
);
2445 samplers
->n_samplers
= count
;
2449 static void si_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
2451 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2452 struct si_pm4_state
*pm4
;
2454 pm4
= si_bind_sampler(rctx
, count
, states
, &rctx
->vs_samplers
,
2455 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2456 si_pm4_set_state(rctx
, vs_sampler
, pm4
);
2459 static void si_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
2461 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2462 struct si_pm4_state
*pm4
;
2464 pm4
= si_bind_sampler(rctx
, count
, states
, &rctx
->ps_samplers
,
2465 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2466 si_pm4_set_state(rctx
, ps_sampler
, pm4
);
2469 static void si_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
2473 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
2481 static void si_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
2482 struct pipe_constant_buffer
*cb
)
2484 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2485 struct si_resource
*rbuffer
= cb
? si_resource(cb
->buffer
) : NULL
;
2486 struct si_pm4_state
*pm4
;
2488 uint32_t reg
, offset
;
2490 /* Note that the state tracker can unbind constant buffers by
2491 * passing NULL here.
2496 pm4
= CALLOC_STRUCT(si_pm4_state
);
2497 si_pm4_inval_shader_cache(pm4
);
2499 if (cb
->user_buffer
)
2500 r600_upload_const_buffer(rctx
, &rbuffer
, cb
->user_buffer
, cb
->buffer_size
, &offset
);
2503 va_offset
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
2504 va_offset
+= offset
;
2506 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
2509 case PIPE_SHADER_VERTEX
:
2510 reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
+ SI_SGPR_CONST
* 4;
2511 si_pm4_set_reg(pm4
, reg
, va_offset
);
2512 si_pm4_set_reg(pm4
, reg
+ 4, va_offset
>> 32);
2513 si_pm4_set_state(rctx
, vs_const
, pm4
);
2516 case PIPE_SHADER_FRAGMENT
:
2517 reg
= R_00B030_SPI_SHADER_USER_DATA_PS_0
+ SI_SGPR_CONST
* 4;
2518 si_pm4_set_reg(pm4
, reg
, va_offset
);
2519 si_pm4_set_reg(pm4
, reg
+ 4, va_offset
>> 32);
2520 si_pm4_set_state(rctx
, ps_const
, pm4
);
2524 R600_ERR("unsupported %d\n", shader
);
2527 if (cb
->buffer
!= &rbuffer
->b
.b
)
2528 si_resource_reference(&rbuffer
, NULL
);
2532 * Vertex elements & buffers
2535 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
2537 const struct pipe_vertex_element
*elements
)
2539 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
2542 assert(count
< PIPE_MAX_ATTRIBS
);
2547 for (i
= 0; i
< count
; ++i
) {
2548 const struct util_format_description
*desc
;
2549 unsigned data_format
, num_format
;
2552 desc
= util_format_description(elements
[i
].src_format
);
2553 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
2554 data_format
= si_translate_vertexformat(ctx
->screen
, elements
[i
].src_format
,
2555 desc
, first_non_void
);
2557 switch (desc
->channel
[first_non_void
].type
) {
2558 case UTIL_FORMAT_TYPE_FIXED
:
2559 num_format
= V_008F0C_BUF_NUM_FORMAT_USCALED
; /* XXX */
2561 case UTIL_FORMAT_TYPE_SIGNED
:
2562 if (desc
->channel
[first_non_void
].normalized
)
2563 num_format
= V_008F0C_BUF_NUM_FORMAT_SNORM
;
2564 else if (desc
->channel
[first_non_void
].pure_integer
)
2565 num_format
= V_008F0C_BUF_NUM_FORMAT_SINT
;
2567 num_format
= V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2569 case UTIL_FORMAT_TYPE_UNSIGNED
:
2570 if (desc
->channel
[first_non_void
].normalized
)
2571 num_format
= V_008F0C_BUF_NUM_FORMAT_UNORM
;
2572 else if (desc
->channel
[first_non_void
].pure_integer
)
2573 num_format
= V_008F0C_BUF_NUM_FORMAT_UINT
;
2575 num_format
= V_008F0C_BUF_NUM_FORMAT_USCALED
;
2577 case UTIL_FORMAT_TYPE_FLOAT
:
2579 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2582 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2583 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2584 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2585 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2586 S_008F0C_NUM_FORMAT(num_format
) |
2587 S_008F0C_DATA_FORMAT(data_format
);
2589 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
2594 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
2596 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2597 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
2599 rctx
->vertex_elements
= v
;
2602 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
2604 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2606 if (rctx
->vertex_elements
== state
)
2607 rctx
->vertex_elements
= NULL
;
2611 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
2612 const struct pipe_vertex_buffer
*buffers
)
2614 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2616 util_set_vertex_buffers_count(rctx
->vertex_buffer
, &rctx
->nr_vertex_buffers
, buffers
, start_slot
, count
);
2619 static void si_set_index_buffer(struct pipe_context
*ctx
,
2620 const struct pipe_index_buffer
*ib
)
2622 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2625 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
2626 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
2628 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
2635 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
2636 const struct pipe_poly_stipple
*state
)
2640 static void si_texture_barrier(struct pipe_context
*ctx
)
2642 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2643 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2645 si_pm4_inval_texture_cache(pm4
);
2646 si_pm4_inval_fb_cache(pm4
, rctx
->framebuffer
.nr_cbufs
);
2647 si_pm4_set_state(rctx
, texture_barrier
, pm4
);
2650 void si_init_state_functions(struct r600_context
*rctx
)
2652 rctx
->context
.create_blend_state
= si_create_blend_state
;
2653 rctx
->context
.bind_blend_state
= si_bind_blend_state
;
2654 rctx
->context
.delete_blend_state
= si_delete_blend_state
;
2655 rctx
->context
.set_blend_color
= si_set_blend_color
;
2657 rctx
->context
.create_rasterizer_state
= si_create_rs_state
;
2658 rctx
->context
.bind_rasterizer_state
= si_bind_rs_state
;
2659 rctx
->context
.delete_rasterizer_state
= si_delete_rs_state
;
2661 rctx
->context
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
2662 rctx
->context
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
2663 rctx
->context
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
2664 rctx
->custom_dsa_flush_depth_stencil
= si_create_db_flush_dsa(rctx
, true, true);
2665 rctx
->custom_dsa_flush_depth
= si_create_db_flush_dsa(rctx
, true, false);
2666 rctx
->custom_dsa_flush_stencil
= si_create_db_flush_dsa(rctx
, false, true);
2667 rctx
->custom_dsa_flush_inplace
= si_create_db_flush_dsa(rctx
, false, false);
2669 rctx
->context
.set_clip_state
= si_set_clip_state
;
2670 rctx
->context
.set_scissor_state
= si_set_scissor_state
;
2671 rctx
->context
.set_viewport_state
= si_set_viewport_state
;
2672 rctx
->context
.set_stencil_ref
= si_set_pipe_stencil_ref
;
2674 rctx
->context
.set_framebuffer_state
= si_set_framebuffer_state
;
2676 rctx
->context
.create_vs_state
= si_create_vs_state
;
2677 rctx
->context
.create_fs_state
= si_create_fs_state
;
2678 rctx
->context
.bind_vs_state
= si_bind_vs_shader
;
2679 rctx
->context
.bind_fs_state
= si_bind_ps_shader
;
2680 rctx
->context
.delete_vs_state
= si_delete_vs_shader
;
2681 rctx
->context
.delete_fs_state
= si_delete_ps_shader
;
2683 rctx
->context
.create_sampler_state
= si_create_sampler_state
;
2684 rctx
->context
.bind_vertex_sampler_states
= si_bind_vs_sampler
;
2685 rctx
->context
.bind_fragment_sampler_states
= si_bind_ps_sampler
;
2686 rctx
->context
.delete_sampler_state
= si_delete_sampler_state
;
2688 rctx
->context
.create_sampler_view
= si_create_sampler_view
;
2689 rctx
->context
.set_vertex_sampler_views
= si_set_vs_sampler_view
;
2690 rctx
->context
.set_fragment_sampler_views
= si_set_ps_sampler_view
;
2691 rctx
->context
.sampler_view_destroy
= si_sampler_view_destroy
;
2693 rctx
->context
.set_sample_mask
= si_set_sample_mask
;
2695 rctx
->context
.set_constant_buffer
= si_set_constant_buffer
;
2697 rctx
->context
.create_vertex_elements_state
= si_create_vertex_elements
;
2698 rctx
->context
.bind_vertex_elements_state
= si_bind_vertex_elements
;
2699 rctx
->context
.delete_vertex_elements_state
= si_delete_vertex_element
;
2700 rctx
->context
.set_vertex_buffers
= si_set_vertex_buffers
;
2701 rctx
->context
.set_index_buffer
= si_set_index_buffer
;
2703 rctx
->context
.create_stream_output_target
= si_create_so_target
;
2704 rctx
->context
.stream_output_target_destroy
= si_so_target_destroy
;
2705 rctx
->context
.set_stream_output_targets
= si_set_so_targets
;
2707 rctx
->context
.texture_barrier
= si_texture_barrier
;
2708 rctx
->context
.set_polygon_stipple
= si_set_polygon_stipple
;
2710 rctx
->context
.draw_vbo
= si_draw_vbo
;
2713 void si_init_config(struct r600_context
*rctx
)
2715 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2717 si_cmd_context_control(pm4
);
2719 si_pm4_set_reg(pm4
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0);
2721 si_pm4_set_reg(pm4
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0);
2722 si_pm4_set_reg(pm4
, R_028A14_VGT_HOS_CNTL
, 0x0);
2723 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0);
2724 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0);
2725 si_pm4_set_reg(pm4
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0);
2726 si_pm4_set_reg(pm4
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0);
2727 si_pm4_set_reg(pm4
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0);
2728 si_pm4_set_reg(pm4
, R_028A2C_VGT_GROUP_DECR
, 0x0);
2729 si_pm4_set_reg(pm4
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0);
2730 si_pm4_set_reg(pm4
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0);
2731 si_pm4_set_reg(pm4
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0);
2732 si_pm4_set_reg(pm4
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0);
2733 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, 0x0);
2734 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0x0);
2735 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
2736 si_pm4_set_reg(pm4
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0);
2737 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
2738 si_pm4_set_reg(pm4
, R_028AA8_IA_MULTI_VGT_PARAM
,
2739 S_028AA8_SWITCH_ON_EOP(1) |
2740 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2741 S_028AA8_PRIMGROUP_SIZE(63));
2742 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0x00000000);
2743 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
2744 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
2745 S_008A14_CLIP_VTX_REORDER_ENA(1));
2747 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
2748 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
2749 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
2751 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
, 0x110000);
2753 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
2755 switch (rctx
->screen
->family
) {
2758 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x2a00126a);
2761 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x0000124a);
2764 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000082);
2767 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
2771 si_pm4_set_state(rctx
, init
, pm4
);