2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
30 #include "radeon/r600_cs.h"
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
38 /* Initialize an external atom (owned by ../radeon). */
40 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
41 struct r600_atom
**list_elem
)
43 atom
->id
= list_elem
- sctx
->atoms
.array
+ 1;
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
49 struct r600_atom
**list_elem
,
50 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
52 atom
->emit
= (void*)emit_func
;
53 atom
->id
= list_elem
- sctx
->atoms
.array
+ 1; /* index+1 in the atom array */
57 unsigned si_array_mode(unsigned mode
)
60 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
61 return V_009910_ARRAY_LINEAR_ALIGNED
;
62 case RADEON_SURF_MODE_1D
:
63 return V_009910_ARRAY_1D_TILED_THIN1
;
64 case RADEON_SURF_MODE_2D
:
65 return V_009910_ARRAY_2D_TILED_THIN1
;
67 case RADEON_SURF_MODE_LINEAR
:
68 return V_009910_ARRAY_LINEAR_GENERAL
;
72 uint32_t si_num_banks(struct si_screen
*sscreen
, struct r600_texture
*tex
)
74 if (sscreen
->b
.chip_class
>= CIK
&&
75 sscreen
->b
.info
.cik_macrotile_mode_array_valid
) {
76 unsigned index
, tileb
;
78 tileb
= 8 * 8 * tex
->surface
.bpe
;
79 tileb
= MIN2(tex
->surface
.tile_split
, tileb
);
81 for (index
= 0; tileb
> 64; index
++) {
86 return (sscreen
->b
.info
.cik_macrotile_mode_array
[index
] >> 6) & 0x3;
89 if (sscreen
->b
.chip_class
== SI
&&
90 sscreen
->b
.info
.si_tile_mode_array_valid
) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index
= tex
->surface
.tiling_index
[0];
94 assert(tile_mode_index
< 32);
96 return G_009910_NUM_BANKS(sscreen
->b
.info
.si_tile_mode_array
[tile_mode_index
]);
100 switch (sscreen
->b
.tiling_info
.num_banks
) {
102 return V_02803C_ADDR_SURF_2_BANK
;
104 return V_02803C_ADDR_SURF_4_BANK
;
107 return V_02803C_ADDR_SURF_8_BANK
;
109 return V_02803C_ADDR_SURF_16_BANK
;
113 unsigned cik_tile_split(unsigned tile_split
)
115 switch (tile_split
) {
117 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_64B
;
120 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_128B
;
123 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_256B
;
126 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_512B
;
130 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_1KB
;
133 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_2KB
;
136 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_4KB
;
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
)
144 switch (macro_tile_aspect
) {
147 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_1
;
150 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_2
;
153 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_4
;
156 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_8
;
159 return macro_tile_aspect
;
162 unsigned cik_bank_wh(unsigned bankwh
)
167 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_1
;
170 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_2
;
173 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_4
;
176 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_8
;
182 unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
)
184 if (sscreen
->b
.info
.si_tile_mode_array_valid
) {
185 uint32_t gb_tile_mode
= sscreen
->b
.info
.si_tile_mode_array
[tile_mode
];
187 return G_009910_PIPE_CONFIG(gb_tile_mode
);
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen
->b
.info
.r600_num_tile_pipes
) {
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16
;
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16
;
199 if (sscreen
->b
.info
.r600_num_backends
== 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16
;
202 return V_02803C_X_ADDR_SURF_P4_8X16
;
204 return V_02803C_ADDR_SURF_P2
;
208 static unsigned si_map_swizzle(unsigned swizzle
)
211 case UTIL_FORMAT_SWIZZLE_Y
:
212 return V_008F0C_SQ_SEL_Y
;
213 case UTIL_FORMAT_SWIZZLE_Z
:
214 return V_008F0C_SQ_SEL_Z
;
215 case UTIL_FORMAT_SWIZZLE_W
:
216 return V_008F0C_SQ_SEL_W
;
217 case UTIL_FORMAT_SWIZZLE_0
:
218 return V_008F0C_SQ_SEL_0
;
219 case UTIL_FORMAT_SWIZZLE_1
:
220 return V_008F0C_SQ_SEL_1
;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X
;
226 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
228 return value
* (1 << frac_bits
);
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x
)
235 x
>= 4096 ? 0xffff : x
* 16;
239 * Inferred framebuffer and blender state.
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
247 * Another reason is to avoid a hang with dual source blending.
249 static void si_emit_cb_target_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
251 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
252 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
253 uint32_t mask
= 0, i
;
255 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++)
256 if (sctx
->framebuffer
.state
.cbufs
[i
])
257 mask
|= 0xf << (4*i
);
260 mask
&= blend
->cb_target_mask
;
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
268 if (blend
&& blend
->dual_src_blend
&&
269 sctx
->ps_shader
.cso
&&
270 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
273 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, mask
);
280 static uint32_t si_translate_blend_function(int blend_func
)
282 switch (blend_func
) {
284 return V_028780_COMB_DST_PLUS_SRC
;
285 case PIPE_BLEND_SUBTRACT
:
286 return V_028780_COMB_SRC_MINUS_DST
;
287 case PIPE_BLEND_REVERSE_SUBTRACT
:
288 return V_028780_COMB_DST_MINUS_SRC
;
290 return V_028780_COMB_MIN_DST_SRC
;
292 return V_028780_COMB_MAX_DST_SRC
;
294 R600_ERR("Unknown blend function %d\n", blend_func
);
301 static uint32_t si_translate_blend_factor(int blend_fact
)
303 switch (blend_fact
) {
304 case PIPE_BLENDFACTOR_ONE
:
305 return V_028780_BLEND_ONE
;
306 case PIPE_BLENDFACTOR_SRC_COLOR
:
307 return V_028780_BLEND_SRC_COLOR
;
308 case PIPE_BLENDFACTOR_SRC_ALPHA
:
309 return V_028780_BLEND_SRC_ALPHA
;
310 case PIPE_BLENDFACTOR_DST_ALPHA
:
311 return V_028780_BLEND_DST_ALPHA
;
312 case PIPE_BLENDFACTOR_DST_COLOR
:
313 return V_028780_BLEND_DST_COLOR
;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
316 case PIPE_BLENDFACTOR_CONST_COLOR
:
317 return V_028780_BLEND_CONSTANT_COLOR
;
318 case PIPE_BLENDFACTOR_CONST_ALPHA
:
319 return V_028780_BLEND_CONSTANT_ALPHA
;
320 case PIPE_BLENDFACTOR_ZERO
:
321 return V_028780_BLEND_ZERO
;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
334 case PIPE_BLENDFACTOR_SRC1_COLOR
:
335 return V_028780_BLEND_SRC1_COLOR
;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
337 return V_028780_BLEND_SRC1_ALPHA
;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
339 return V_028780_BLEND_INV_SRC1_COLOR
;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
341 return V_028780_BLEND_INV_SRC1_ALPHA
;
343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
350 static uint32_t si_translate_blend_opt_function(int blend_func
)
352 switch (blend_func
) {
354 return V_028760_OPT_COMB_ADD
;
355 case PIPE_BLEND_SUBTRACT
:
356 return V_028760_OPT_COMB_SUBTRACT
;
357 case PIPE_BLEND_REVERSE_SUBTRACT
:
358 return V_028760_OPT_COMB_REVSUBTRACT
;
360 return V_028760_OPT_COMB_MIN
;
362 return V_028760_OPT_COMB_MAX
;
364 return V_028760_OPT_COMB_BLEND_DISABLED
;
368 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
370 switch (blend_fact
) {
371 case PIPE_BLENDFACTOR_ZERO
:
372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
373 case PIPE_BLENDFACTOR_ONE
:
374 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
375 case PIPE_BLENDFACTOR_SRC_COLOR
:
376 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
377 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
378 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
379 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
380 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
381 case PIPE_BLENDFACTOR_SRC_ALPHA
:
382 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
383 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
384 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
385 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
386 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
387 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
393 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
394 const struct pipe_blend_state
*state
,
397 struct si_context
*sctx
= (struct si_context
*)ctx
;
398 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
399 struct si_pm4_state
*pm4
= &blend
->pm4
;
401 uint32_t color_control
= 0;
406 blend
->alpha_to_one
= state
->alpha_to_one
;
407 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
409 if (state
->logicop_enable
) {
410 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
412 color_control
|= S_028808_ROP3(0xcc);
415 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
416 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
417 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
418 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
419 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
420 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
422 blend
->cb_target_mask
= 0;
423 for (int i
= 0; i
< 8; i
++) {
424 /* state->rt entries > 0 only written if independent blending */
425 const int j
= state
->independent_blend_enable
? i
: 0;
427 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
428 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
429 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
430 unsigned eqA
= state
->rt
[j
].alpha_func
;
431 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
432 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
434 unsigned blend_cntl
= 0;
436 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
437 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
439 if (!state
->rt
[j
].blend_enable
) {
440 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
444 blend_cntl
|= S_028780_ENABLE(1);
445 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
446 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
447 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
449 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
450 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
451 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
452 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
453 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
455 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
458 if (blend
->cb_target_mask
) {
459 color_control
|= S_028808_MODE(mode
);
461 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
464 if (sctx
->b
.family
== CHIP_STONEY
) {
465 uint32_t sx_blend_opt_control
= 0;
467 for (int i
= 0; i
< 8; i
++) {
468 const int j
= state
->independent_blend_enable
? i
: 0;
470 /* TODO: We can also set this if the surface doesn't contain RGB. */
471 if (!state
->rt
[j
].blend_enable
||
472 !(state
->rt
[j
].colormask
& (PIPE_MASK_R
| PIPE_MASK_G
| PIPE_MASK_B
)))
473 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (4 * i
);
475 /* TODO: We can also set this if the surface doesn't contain alpha. */
476 if (!state
->rt
[j
].blend_enable
||
477 !(state
->rt
[j
].colormask
& PIPE_MASK_A
))
478 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (4 * i
);
480 if (!state
->rt
[j
].blend_enable
) {
481 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
482 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
483 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
));
487 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
488 S_028760_COLOR_SRC_OPT(si_translate_blend_opt_factor(state
->rt
[j
].rgb_src_factor
, false)) |
489 S_028760_COLOR_DST_OPT(si_translate_blend_opt_factor(state
->rt
[j
].rgb_dst_factor
, false)) |
490 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(state
->rt
[j
].rgb_func
)) |
491 S_028760_ALPHA_SRC_OPT(si_translate_blend_opt_factor(state
->rt
[j
].alpha_src_factor
, true)) |
492 S_028760_ALPHA_DST_OPT(si_translate_blend_opt_factor(state
->rt
[j
].alpha_dst_factor
, true)) |
493 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(state
->rt
[j
].alpha_func
)));
496 si_pm4_set_reg(pm4
, R_02875C_SX_BLEND_OPT_CONTROL
, sx_blend_opt_control
);
498 /* RB+ doesn't work with dual source blending */
499 if (blend
->dual_src_blend
)
500 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
503 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
507 static void *si_create_blend_state(struct pipe_context
*ctx
,
508 const struct pipe_blend_state
*state
)
510 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
513 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
515 struct si_context
*sctx
= (struct si_context
*)ctx
;
516 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
517 si_mark_atom_dirty(sctx
, &sctx
->cb_target_mask
);
520 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
522 struct si_context
*sctx
= (struct si_context
*)ctx
;
523 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
526 static void si_set_blend_color(struct pipe_context
*ctx
,
527 const struct pipe_blend_color
*state
)
529 struct si_context
*sctx
= (struct si_context
*)ctx
;
531 if (memcmp(&sctx
->blend_color
.state
, state
, sizeof(*state
)) == 0)
534 sctx
->blend_color
.state
= *state
;
535 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
538 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
540 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
542 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
543 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
547 * Clipping, scissors and viewport
550 static void si_set_clip_state(struct pipe_context
*ctx
,
551 const struct pipe_clip_state
*state
)
553 struct si_context
*sctx
= (struct si_context
*)ctx
;
554 struct pipe_constant_buffer cb
;
556 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
559 sctx
->clip_state
.state
= *state
;
560 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
563 cb
.user_buffer
= state
->ucp
;
564 cb
.buffer_offset
= 0;
565 cb
.buffer_size
= 4*4*8;
566 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, SI_DRIVER_STATE_CONST_BUF
, &cb
);
567 pipe_resource_reference(&cb
.buffer
, NULL
);
570 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
572 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
574 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
575 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
578 #define SIX_BITS 0x3F
580 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
582 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
583 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
584 unsigned window_space
=
585 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
586 unsigned clipdist_mask
=
587 info
->writes_clipvertex
? SIX_BITS
: info
->clipdist_writemask
;
589 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
590 S_02881C_USE_VTX_POINT_SIZE(info
->writes_psize
) |
591 S_02881C_USE_VTX_EDGE_FLAG(info
->writes_edgeflag
) |
592 S_02881C_USE_VTX_RENDER_TARGET_INDX(info
->writes_layer
) |
593 S_02881C_USE_VTX_VIEWPORT_INDX(info
->writes_viewport_index
) |
594 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask
& 0x0F) != 0) |
595 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask
& 0xF0) != 0) |
596 S_02881C_VS_OUT_MISC_VEC_ENA(info
->writes_psize
||
597 info
->writes_edgeflag
||
598 info
->writes_layer
||
599 info
->writes_viewport_index
) |
600 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
601 (sctx
->queued
.named
.rasterizer
->clip_plane_enable
&
603 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
604 sctx
->queued
.named
.rasterizer
->pa_cl_clip_cntl
|
606 sctx
->queued
.named
.rasterizer
->clip_plane_enable
& SIX_BITS
) |
607 S_028810_CLIP_DISABLE(window_space
));
609 /* reuse needs to be set off if we write oViewport */
610 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
611 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
614 static void si_set_scissor_states(struct pipe_context
*ctx
,
616 unsigned num_scissors
,
617 const struct pipe_scissor_state
*state
)
619 struct si_context
*sctx
= (struct si_context
*)ctx
;
622 for (i
= 0; i
< num_scissors
; i
++)
623 sctx
->scissors
.states
[start_slot
+ i
] = state
[i
];
625 sctx
->scissors
.dirty_mask
|= ((1 << num_scissors
) - 1) << start_slot
;
626 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
629 static void si_emit_scissors(struct si_context
*sctx
, struct r600_atom
*atom
)
631 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
632 struct pipe_scissor_state
*states
= sctx
->scissors
.states
;
633 unsigned mask
= sctx
->scissors
.dirty_mask
;
635 /* The simple case: Only 1 viewport is active. */
637 !si_get_vs_info(sctx
)->writes_viewport_index
) {
638 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
639 radeon_emit(cs
, S_028250_TL_X(states
[0].minx
) |
640 S_028250_TL_Y(states
[0].miny
) |
641 S_028250_WINDOW_OFFSET_DISABLE(1));
642 radeon_emit(cs
, S_028254_BR_X(states
[0].maxx
) |
643 S_028254_BR_Y(states
[0].maxy
));
644 sctx
->scissors
.dirty_mask
&= ~1; /* clear one bit */
651 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
653 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+
654 start
* 4 * 2, count
* 2);
655 for (i
= start
; i
< start
+count
; i
++) {
656 radeon_emit(cs
, S_028250_TL_X(states
[i
].minx
) |
657 S_028250_TL_Y(states
[i
].miny
) |
658 S_028250_WINDOW_OFFSET_DISABLE(1));
659 radeon_emit(cs
, S_028254_BR_X(states
[i
].maxx
) |
660 S_028254_BR_Y(states
[i
].maxy
));
663 sctx
->scissors
.dirty_mask
= 0;
666 static void si_set_viewport_states(struct pipe_context
*ctx
,
668 unsigned num_viewports
,
669 const struct pipe_viewport_state
*state
)
671 struct si_context
*sctx
= (struct si_context
*)ctx
;
674 for (i
= 0; i
< num_viewports
; i
++)
675 sctx
->viewports
.states
[start_slot
+ i
] = state
[i
];
677 sctx
->viewports
.dirty_mask
|= ((1 << num_viewports
) - 1) << start_slot
;
678 si_mark_atom_dirty(sctx
, &sctx
->viewports
.atom
);
681 static void si_emit_viewports(struct si_context
*sctx
, struct r600_atom
*atom
)
683 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
684 struct pipe_viewport_state
*states
= sctx
->viewports
.states
;
685 unsigned mask
= sctx
->viewports
.dirty_mask
;
687 /* The simple case: Only 1 viewport is active. */
689 !si_get_vs_info(sctx
)->writes_viewport_index
) {
690 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
, 6);
691 radeon_emit(cs
, fui(states
[0].scale
[0]));
692 radeon_emit(cs
, fui(states
[0].translate
[0]));
693 radeon_emit(cs
, fui(states
[0].scale
[1]));
694 radeon_emit(cs
, fui(states
[0].translate
[1]));
695 radeon_emit(cs
, fui(states
[0].scale
[2]));
696 radeon_emit(cs
, fui(states
[0].translate
[2]));
697 sctx
->viewports
.dirty_mask
&= ~1; /* clear one bit */
704 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
706 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
707 start
* 4 * 6, count
* 6);
708 for (i
= start
; i
< start
+count
; i
++) {
709 radeon_emit(cs
, fui(states
[i
].scale
[0]));
710 radeon_emit(cs
, fui(states
[i
].translate
[0]));
711 radeon_emit(cs
, fui(states
[i
].scale
[1]));
712 radeon_emit(cs
, fui(states
[i
].translate
[1]));
713 radeon_emit(cs
, fui(states
[i
].scale
[2]));
714 radeon_emit(cs
, fui(states
[i
].translate
[2]));
717 sctx
->viewports
.dirty_mask
= 0;
721 * inferred state between framebuffer and rasterizer
723 static void si_update_poly_offset_state(struct si_context
*sctx
)
725 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
727 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
)
730 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
731 case PIPE_FORMAT_Z16_UNORM
:
732 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
734 default: /* 24-bit */
735 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
737 case PIPE_FORMAT_Z32_FLOAT
:
738 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
739 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
748 static uint32_t si_translate_fill(uint32_t func
)
751 case PIPE_POLYGON_MODE_FILL
:
752 return V_028814_X_DRAW_TRIANGLES
;
753 case PIPE_POLYGON_MODE_LINE
:
754 return V_028814_X_DRAW_LINES
;
755 case PIPE_POLYGON_MODE_POINT
:
756 return V_028814_X_DRAW_POINTS
;
759 return V_028814_X_DRAW_POINTS
;
763 static void *si_create_rs_state(struct pipe_context
*ctx
,
764 const struct pipe_rasterizer_state
*state
)
766 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
767 struct si_pm4_state
*pm4
= &rs
->pm4
;
769 float psize_min
, psize_max
;
775 rs
->two_side
= state
->light_twoside
;
776 rs
->multisample_enable
= state
->multisample
;
777 rs
->force_persample_interp
= state
->force_persample_interp
;
778 rs
->clip_plane_enable
= state
->clip_plane_enable
;
779 rs
->line_stipple_enable
= state
->line_stipple_enable
;
780 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
781 rs
->line_smooth
= state
->line_smooth
;
782 rs
->poly_smooth
= state
->poly_smooth
;
783 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
785 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
786 rs
->flatshade
= state
->flatshade
;
787 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
788 rs
->rasterizer_discard
= state
->rasterizer_discard
;
789 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
790 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
791 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
792 rs
->pa_cl_clip_cntl
=
793 S_028810_PS_UCP_MODE(3) |
794 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
795 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
796 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
797 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
798 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
800 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
801 S_0286D4_FLAT_SHADE_ENA(1) |
802 S_0286D4_PNT_SPRITE_ENA(1) |
803 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
804 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
805 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
806 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
807 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
809 /* point size 12.4 fixed point */
810 tmp
= (unsigned)(state
->point_size
* 8.0);
811 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
813 if (state
->point_size_per_vertex
) {
814 psize_min
= util_get_min_point_size(state
);
817 /* Force the point size to be as if the vertex output was disabled. */
818 psize_min
= state
->point_size
;
819 psize_max
= state
->point_size
;
821 /* Divide by two, because 0.5 = 1 pixel. */
822 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
823 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
824 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
826 tmp
= (unsigned)state
->line_width
* 8;
827 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
828 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
829 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
830 S_028A48_MSAA_ENABLE(state
->multisample
||
831 state
->poly_smooth
||
832 state
->line_smooth
) |
833 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
));
835 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
836 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
837 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
839 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
840 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
841 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
842 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
843 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
844 S_028814_FACE(!state
->front_ccw
) |
845 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
846 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
847 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
848 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
849 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
850 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
851 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
852 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+
853 SI_SGPR_VS_STATE_BITS
* 4, state
->clamp_vertex_color
);
855 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
856 for (i
= 0; i
< 3; i
++) {
857 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
858 float offset_units
= state
->offset_units
;
859 float offset_scale
= state
->offset_scale
* 16.0f
;
862 case 0: /* 16-bit zbuffer */
863 offset_units
*= 4.0f
;
865 case 1: /* 24-bit zbuffer */
866 offset_units
*= 2.0f
;
868 case 2: /* 32-bit zbuffer */
869 offset_units
*= 1.0f
;
873 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
875 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
877 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
879 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
886 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
888 struct si_context
*sctx
= (struct si_context
*)ctx
;
889 struct si_state_rasterizer
*old_rs
=
890 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
891 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
896 if (sctx
->framebuffer
.nr_samples
> 1 &&
897 (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
))
898 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
900 si_pm4_bind_state(sctx
, rasterizer
, rs
);
901 si_update_poly_offset_state(sctx
);
903 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
906 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
908 struct si_context
*sctx
= (struct si_context
*)ctx
;
910 if (sctx
->queued
.named
.rasterizer
== state
)
911 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
912 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
916 * infeered state between dsa and stencil ref
918 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
920 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
921 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
922 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
924 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
925 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
926 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
927 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
928 S_028430_STENCILOPVAL(1));
929 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
930 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
931 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
932 S_028434_STENCILOPVAL_BF(1));
935 static void si_set_stencil_ref(struct pipe_context
*ctx
,
936 const struct pipe_stencil_ref
*state
)
938 struct si_context
*sctx
= (struct si_context
*)ctx
;
940 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
943 sctx
->stencil_ref
.state
= *state
;
944 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
952 static uint32_t si_translate_stencil_op(int s_op
)
955 case PIPE_STENCIL_OP_KEEP
:
956 return V_02842C_STENCIL_KEEP
;
957 case PIPE_STENCIL_OP_ZERO
:
958 return V_02842C_STENCIL_ZERO
;
959 case PIPE_STENCIL_OP_REPLACE
:
960 return V_02842C_STENCIL_REPLACE_TEST
;
961 case PIPE_STENCIL_OP_INCR
:
962 return V_02842C_STENCIL_ADD_CLAMP
;
963 case PIPE_STENCIL_OP_DECR
:
964 return V_02842C_STENCIL_SUB_CLAMP
;
965 case PIPE_STENCIL_OP_INCR_WRAP
:
966 return V_02842C_STENCIL_ADD_WRAP
;
967 case PIPE_STENCIL_OP_DECR_WRAP
:
968 return V_02842C_STENCIL_SUB_WRAP
;
969 case PIPE_STENCIL_OP_INVERT
:
970 return V_02842C_STENCIL_INVERT
;
972 R600_ERR("Unknown stencil op %d", s_op
);
979 static void *si_create_dsa_state(struct pipe_context
*ctx
,
980 const struct pipe_depth_stencil_alpha_state
*state
)
982 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
983 struct si_pm4_state
*pm4
= &dsa
->pm4
;
984 unsigned db_depth_control
;
985 uint32_t db_stencil_control
= 0;
991 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
992 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
993 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
994 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
996 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
997 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
998 S_028800_ZFUNC(state
->depth
.func
) |
999 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1002 if (state
->stencil
[0].enabled
) {
1003 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1004 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1005 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1006 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1007 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1009 if (state
->stencil
[1].enabled
) {
1010 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1011 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1012 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1013 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1014 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1019 if (state
->alpha
.enabled
) {
1020 dsa
->alpha_func
= state
->alpha
.func
;
1022 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1023 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1025 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1028 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1029 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1030 if (state
->depth
.bounds_test
) {
1031 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1032 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1038 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1040 struct si_context
*sctx
= (struct si_context
*)ctx
;
1041 struct si_state_dsa
*dsa
= state
;
1046 si_pm4_bind_state(sctx
, dsa
, dsa
);
1048 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1049 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1050 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1051 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1055 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1057 struct si_context
*sctx
= (struct si_context
*)ctx
;
1058 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1061 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1063 struct pipe_depth_stencil_alpha_state dsa
= {};
1065 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1068 /* DB RENDER STATE */
1070 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
1072 struct si_context
*sctx
= (struct si_context
*)ctx
;
1074 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1077 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1079 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1080 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1081 unsigned db_shader_control
;
1083 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1085 /* DB_RENDER_CONTROL */
1086 if (sctx
->dbcb_depth_copy_enabled
||
1087 sctx
->dbcb_stencil_copy_enabled
) {
1089 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1090 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1091 S_028000_COPY_CENTROID(1) |
1092 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1093 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1095 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1096 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1099 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1100 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1103 /* DB_COUNT_CONTROL (occlusion queries) */
1104 if (sctx
->b
.num_occlusion_queries
> 0) {
1105 if (sctx
->b
.chip_class
>= CIK
) {
1107 S_028004_PERFECT_ZPASS_COUNTS(1) |
1108 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1109 S_028004_ZPASS_ENABLE(1) |
1110 S_028004_SLICE_EVEN_ENABLE(1) |
1111 S_028004_SLICE_ODD_ENABLE(1));
1114 S_028004_PERFECT_ZPASS_COUNTS(1) |
1115 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1118 /* Disable occlusion queries. */
1119 if (sctx
->b
.chip_class
>= CIK
) {
1122 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1126 /* DB_RENDER_OVERRIDE2 */
1127 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1128 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1129 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
));
1131 db_shader_control
= S_02880C_ALPHA_TO_MASK_DISABLE(sctx
->framebuffer
.cb0_is_integer
) |
1132 sctx
->ps_db_shader_control
;
1134 /* Bug workaround for smoothing (overrasterization) on SI. */
1135 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
)
1136 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1138 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
1140 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1141 if (sctx
->framebuffer
.nr_samples
<= 1 || (rs
&& !rs
->multisample_enable
))
1142 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1144 if (sctx
->b
.family
== CHIP_STONEY
&&
1145 sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
)
1146 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1148 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1153 * format translation
1155 static uint32_t si_translate_colorformat(enum pipe_format format
)
1157 const struct util_format_description
*desc
= util_format_description(format
);
1159 #define HAS_SIZE(x,y,z,w) \
1160 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1161 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1163 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1164 return V_028C70_COLOR_10_11_11
;
1166 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1167 return V_028C70_COLOR_INVALID
;
1169 switch (desc
->nr_channels
) {
1171 switch (desc
->channel
[0].size
) {
1173 return V_028C70_COLOR_8
;
1175 return V_028C70_COLOR_16
;
1177 return V_028C70_COLOR_32
;
1181 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1182 switch (desc
->channel
[0].size
) {
1184 return V_028C70_COLOR_8_8
;
1186 return V_028C70_COLOR_16_16
;
1188 return V_028C70_COLOR_32_32
;
1190 } else if (HAS_SIZE(8,24,0,0)) {
1191 return V_028C70_COLOR_24_8
;
1192 } else if (HAS_SIZE(24,8,0,0)) {
1193 return V_028C70_COLOR_8_24
;
1197 if (HAS_SIZE(5,6,5,0)) {
1198 return V_028C70_COLOR_5_6_5
;
1199 } else if (HAS_SIZE(32,8,24,0)) {
1200 return V_028C70_COLOR_X24_8_32_FLOAT
;
1204 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1205 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1206 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1207 switch (desc
->channel
[0].size
) {
1209 return V_028C70_COLOR_4_4_4_4
;
1211 return V_028C70_COLOR_8_8_8_8
;
1213 return V_028C70_COLOR_16_16_16_16
;
1215 return V_028C70_COLOR_32_32_32_32
;
1217 } else if (HAS_SIZE(5,5,5,1)) {
1218 return V_028C70_COLOR_1_5_5_5
;
1219 } else if (HAS_SIZE(10,10,10,2)) {
1220 return V_028C70_COLOR_2_10_10_10
;
1224 return V_028C70_COLOR_INVALID
;
1227 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1229 if (SI_BIG_ENDIAN
) {
1230 switch(colorformat
) {
1231 /* 8-bit buffers. */
1232 case V_028C70_COLOR_8
:
1233 return V_028C70_ENDIAN_NONE
;
1235 /* 16-bit buffers. */
1236 case V_028C70_COLOR_5_6_5
:
1237 case V_028C70_COLOR_1_5_5_5
:
1238 case V_028C70_COLOR_4_4_4_4
:
1239 case V_028C70_COLOR_16
:
1240 case V_028C70_COLOR_8_8
:
1241 return V_028C70_ENDIAN_8IN16
;
1243 /* 32-bit buffers. */
1244 case V_028C70_COLOR_8_8_8_8
:
1245 case V_028C70_COLOR_2_10_10_10
:
1246 case V_028C70_COLOR_8_24
:
1247 case V_028C70_COLOR_24_8
:
1248 case V_028C70_COLOR_16_16
:
1249 return V_028C70_ENDIAN_8IN32
;
1251 /* 64-bit buffers. */
1252 case V_028C70_COLOR_16_16_16_16
:
1253 return V_028C70_ENDIAN_8IN16
;
1255 case V_028C70_COLOR_32_32
:
1256 return V_028C70_ENDIAN_8IN32
;
1258 /* 128-bit buffers. */
1259 case V_028C70_COLOR_32_32_32_32
:
1260 return V_028C70_ENDIAN_8IN32
;
1262 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1265 return V_028C70_ENDIAN_NONE
;
1269 /* Returns the size in bits of the widest component of a CB format */
1270 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
1272 switch(colorformat
) {
1273 case V_028C70_COLOR_4_4_4_4
:
1276 case V_028C70_COLOR_1_5_5_5
:
1277 case V_028C70_COLOR_5_5_5_1
:
1280 case V_028C70_COLOR_5_6_5
:
1283 case V_028C70_COLOR_8
:
1284 case V_028C70_COLOR_8_8
:
1285 case V_028C70_COLOR_8_8_8_8
:
1288 case V_028C70_COLOR_10_10_10_2
:
1289 case V_028C70_COLOR_2_10_10_10
:
1292 case V_028C70_COLOR_10_11_11
:
1293 case V_028C70_COLOR_11_11_10
:
1296 case V_028C70_COLOR_16
:
1297 case V_028C70_COLOR_16_16
:
1298 case V_028C70_COLOR_16_16_16_16
:
1301 case V_028C70_COLOR_8_24
:
1302 case V_028C70_COLOR_24_8
:
1305 case V_028C70_COLOR_32
:
1306 case V_028C70_COLOR_32_32
:
1307 case V_028C70_COLOR_32_32_32_32
:
1308 case V_028C70_COLOR_X24_8_32_FLOAT
:
1312 assert(!"Unknown maximum component size");
1316 static uint32_t si_translate_dbformat(enum pipe_format format
)
1319 case PIPE_FORMAT_Z16_UNORM
:
1320 return V_028040_Z_16
;
1321 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1322 case PIPE_FORMAT_X8Z24_UNORM
:
1323 case PIPE_FORMAT_Z24X8_UNORM
:
1324 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1325 return V_028040_Z_24
; /* deprecated on SI */
1326 case PIPE_FORMAT_Z32_FLOAT
:
1327 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1328 return V_028040_Z_32_FLOAT
;
1330 return V_028040_Z_INVALID
;
1335 * Texture translation
1338 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1339 enum pipe_format format
,
1340 const struct util_format_description
*desc
,
1343 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1344 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1345 sscreen
->b
.info
.drm_minor
>= 31) ||
1346 sscreen
->b
.info
.drm_major
== 3;
1347 boolean uniform
= TRUE
;
1350 /* Colorspace (return non-RGB formats directly). */
1351 switch (desc
->colorspace
) {
1352 /* Depth stencil formats */
1353 case UTIL_FORMAT_COLORSPACE_ZS
:
1355 case PIPE_FORMAT_Z16_UNORM
:
1356 return V_008F14_IMG_DATA_FORMAT_16
;
1357 case PIPE_FORMAT_X24S8_UINT
:
1358 case PIPE_FORMAT_Z24X8_UNORM
:
1359 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1360 return V_008F14_IMG_DATA_FORMAT_8_24
;
1361 case PIPE_FORMAT_X8Z24_UNORM
:
1362 case PIPE_FORMAT_S8X24_UINT
:
1363 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1364 return V_008F14_IMG_DATA_FORMAT_24_8
;
1365 case PIPE_FORMAT_S8_UINT
:
1366 return V_008F14_IMG_DATA_FORMAT_8
;
1367 case PIPE_FORMAT_Z32_FLOAT
:
1368 return V_008F14_IMG_DATA_FORMAT_32
;
1369 case PIPE_FORMAT_X32_S8X24_UINT
:
1370 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1371 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1376 case UTIL_FORMAT_COLORSPACE_YUV
:
1377 goto out_unknown
; /* TODO */
1379 case UTIL_FORMAT_COLORSPACE_SRGB
:
1380 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1388 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1389 if (!enable_compressed_formats
)
1393 case PIPE_FORMAT_RGTC1_SNORM
:
1394 case PIPE_FORMAT_LATC1_SNORM
:
1395 case PIPE_FORMAT_RGTC1_UNORM
:
1396 case PIPE_FORMAT_LATC1_UNORM
:
1397 return V_008F14_IMG_DATA_FORMAT_BC4
;
1398 case PIPE_FORMAT_RGTC2_SNORM
:
1399 case PIPE_FORMAT_LATC2_SNORM
:
1400 case PIPE_FORMAT_RGTC2_UNORM
:
1401 case PIPE_FORMAT_LATC2_UNORM
:
1402 return V_008F14_IMG_DATA_FORMAT_BC5
;
1408 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1409 if (!enable_compressed_formats
)
1413 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1414 case PIPE_FORMAT_BPTC_SRGBA
:
1415 return V_008F14_IMG_DATA_FORMAT_BC7
;
1416 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1417 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1418 return V_008F14_IMG_DATA_FORMAT_BC6
;
1424 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1426 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1427 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1428 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1429 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1430 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1431 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1437 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1438 if (!enable_compressed_formats
)
1441 if (!util_format_s3tc_enabled
) {
1446 case PIPE_FORMAT_DXT1_RGB
:
1447 case PIPE_FORMAT_DXT1_RGBA
:
1448 case PIPE_FORMAT_DXT1_SRGB
:
1449 case PIPE_FORMAT_DXT1_SRGBA
:
1450 return V_008F14_IMG_DATA_FORMAT_BC1
;
1451 case PIPE_FORMAT_DXT3_RGBA
:
1452 case PIPE_FORMAT_DXT3_SRGBA
:
1453 return V_008F14_IMG_DATA_FORMAT_BC2
;
1454 case PIPE_FORMAT_DXT5_RGBA
:
1455 case PIPE_FORMAT_DXT5_SRGBA
:
1456 return V_008F14_IMG_DATA_FORMAT_BC3
;
1462 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1463 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1464 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1465 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1468 /* R8G8Bx_SNORM - TODO CxV8U8 */
1470 /* See whether the components are of the same size. */
1471 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1472 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1475 /* Non-uniform formats. */
1477 switch(desc
->nr_channels
) {
1479 if (desc
->channel
[0].size
== 5 &&
1480 desc
->channel
[1].size
== 6 &&
1481 desc
->channel
[2].size
== 5) {
1482 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1486 if (desc
->channel
[0].size
== 5 &&
1487 desc
->channel
[1].size
== 5 &&
1488 desc
->channel
[2].size
== 5 &&
1489 desc
->channel
[3].size
== 1) {
1490 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1492 if (desc
->channel
[0].size
== 10 &&
1493 desc
->channel
[1].size
== 10 &&
1494 desc
->channel
[2].size
== 10 &&
1495 desc
->channel
[3].size
== 2) {
1496 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1503 if (first_non_void
< 0 || first_non_void
> 3)
1506 /* uniform formats */
1507 switch (desc
->channel
[first_non_void
].size
) {
1509 switch (desc
->nr_channels
) {
1510 #if 0 /* Not supported for render targets */
1512 return V_008F14_IMG_DATA_FORMAT_4_4
;
1515 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1519 switch (desc
->nr_channels
) {
1521 return V_008F14_IMG_DATA_FORMAT_8
;
1523 return V_008F14_IMG_DATA_FORMAT_8_8
;
1525 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1529 switch (desc
->nr_channels
) {
1531 return V_008F14_IMG_DATA_FORMAT_16
;
1533 return V_008F14_IMG_DATA_FORMAT_16_16
;
1535 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1539 switch (desc
->nr_channels
) {
1541 return V_008F14_IMG_DATA_FORMAT_32
;
1543 return V_008F14_IMG_DATA_FORMAT_32_32
;
1544 #if 0 /* Not supported for render targets */
1546 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1549 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1554 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1558 static unsigned si_tex_wrap(unsigned wrap
)
1562 case PIPE_TEX_WRAP_REPEAT
:
1563 return V_008F30_SQ_TEX_WRAP
;
1564 case PIPE_TEX_WRAP_CLAMP
:
1565 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1566 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1567 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1568 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1569 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1570 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1571 return V_008F30_SQ_TEX_MIRROR
;
1572 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1573 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1574 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1575 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1576 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1577 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1581 static unsigned si_tex_filter(unsigned filter
)
1585 case PIPE_TEX_FILTER_NEAREST
:
1586 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1587 case PIPE_TEX_FILTER_LINEAR
:
1588 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1592 static unsigned si_tex_mipfilter(unsigned filter
)
1595 case PIPE_TEX_MIPFILTER_NEAREST
:
1596 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1597 case PIPE_TEX_MIPFILTER_LINEAR
:
1598 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1600 case PIPE_TEX_MIPFILTER_NONE
:
1601 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1605 static unsigned si_tex_compare(unsigned compare
)
1609 case PIPE_FUNC_NEVER
:
1610 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1611 case PIPE_FUNC_LESS
:
1612 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1613 case PIPE_FUNC_EQUAL
:
1614 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1615 case PIPE_FUNC_LEQUAL
:
1616 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1617 case PIPE_FUNC_GREATER
:
1618 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1619 case PIPE_FUNC_NOTEQUAL
:
1620 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1621 case PIPE_FUNC_GEQUAL
:
1622 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1623 case PIPE_FUNC_ALWAYS
:
1624 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1628 static unsigned si_tex_dim(unsigned res_target
, unsigned view_target
,
1629 unsigned nr_samples
)
1631 if (view_target
== PIPE_TEXTURE_CUBE
||
1632 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1633 res_target
= view_target
;
1635 switch (res_target
) {
1637 case PIPE_TEXTURE_1D
:
1638 return V_008F1C_SQ_RSRC_IMG_1D
;
1639 case PIPE_TEXTURE_1D_ARRAY
:
1640 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1641 case PIPE_TEXTURE_2D
:
1642 case PIPE_TEXTURE_RECT
:
1643 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1644 V_008F1C_SQ_RSRC_IMG_2D
;
1645 case PIPE_TEXTURE_2D_ARRAY
:
1646 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1647 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1648 case PIPE_TEXTURE_3D
:
1649 return V_008F1C_SQ_RSRC_IMG_3D
;
1650 case PIPE_TEXTURE_CUBE
:
1651 case PIPE_TEXTURE_CUBE_ARRAY
:
1652 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1657 * Format support testing
1660 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1662 return si_translate_texformat(screen
, format
, util_format_description(format
),
1663 util_format_get_first_non_void_channel(format
)) != ~0U;
1666 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1667 const struct util_format_description
*desc
,
1670 unsigned type
= desc
->channel
[first_non_void
].type
;
1673 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1674 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1676 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1677 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1679 if (desc
->nr_channels
== 4 &&
1680 desc
->channel
[0].size
== 10 &&
1681 desc
->channel
[1].size
== 10 &&
1682 desc
->channel
[2].size
== 10 &&
1683 desc
->channel
[3].size
== 2)
1684 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1686 /* See whether the components are of the same size. */
1687 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1688 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1689 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1692 switch (desc
->channel
[first_non_void
].size
) {
1694 switch (desc
->nr_channels
) {
1696 return V_008F0C_BUF_DATA_FORMAT_8
;
1698 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1701 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1705 switch (desc
->nr_channels
) {
1707 return V_008F0C_BUF_DATA_FORMAT_16
;
1709 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1712 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1716 /* From the Southern Islands ISA documentation about MTBUF:
1717 * 'Memory reads of data in memory that is 32 or 64 bits do not
1718 * undergo any format conversion.'
1720 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1721 !desc
->channel
[first_non_void
].pure_integer
)
1722 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1724 switch (desc
->nr_channels
) {
1726 return V_008F0C_BUF_DATA_FORMAT_32
;
1728 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1730 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1732 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1737 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1740 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1741 const struct util_format_description
*desc
,
1744 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1745 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1747 switch (desc
->channel
[first_non_void
].type
) {
1748 case UTIL_FORMAT_TYPE_SIGNED
:
1749 if (desc
->channel
[first_non_void
].normalized
)
1750 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1751 else if (desc
->channel
[first_non_void
].pure_integer
)
1752 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1754 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1756 case UTIL_FORMAT_TYPE_UNSIGNED
:
1757 if (desc
->channel
[first_non_void
].normalized
)
1758 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1759 else if (desc
->channel
[first_non_void
].pure_integer
)
1760 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1762 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1764 case UTIL_FORMAT_TYPE_FLOAT
:
1766 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1770 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1772 const struct util_format_description
*desc
;
1774 unsigned data_format
;
1776 desc
= util_format_description(format
);
1777 first_non_void
= util_format_get_first_non_void_channel(format
);
1778 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1779 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1782 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1784 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1785 r600_translate_colorswap(format
) != ~0U;
1788 static bool si_is_zs_format_supported(enum pipe_format format
)
1790 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1793 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1794 enum pipe_format format
,
1795 enum pipe_texture_target target
,
1796 unsigned sample_count
,
1799 unsigned retval
= 0;
1801 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1802 R600_ERR("r600: unsupported texture type %d\n", target
);
1806 if (!util_format_is_supported(format
, usage
))
1809 if (sample_count
> 1) {
1810 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1813 switch (sample_count
) {
1823 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
1824 if (target
== PIPE_BUFFER
) {
1825 if (si_is_vertex_format_supported(screen
, format
))
1826 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1828 if (si_is_sampler_format_supported(screen
, format
))
1829 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1833 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1834 PIPE_BIND_DISPLAY_TARGET
|
1837 PIPE_BIND_BLENDABLE
)) &&
1838 si_is_colorbuffer_format_supported(format
)) {
1840 (PIPE_BIND_RENDER_TARGET
|
1841 PIPE_BIND_DISPLAY_TARGET
|
1844 if (!util_format_is_pure_integer(format
) &&
1845 !util_format_is_depth_or_stencil(format
))
1846 retval
|= usage
& PIPE_BIND_BLENDABLE
;
1849 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1850 si_is_zs_format_supported(format
)) {
1851 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1854 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1855 si_is_vertex_format_supported(screen
, format
)) {
1856 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1859 if (usage
& PIPE_BIND_TRANSFER_READ
)
1860 retval
|= PIPE_BIND_TRANSFER_READ
;
1861 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1862 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1864 return retval
== usage
;
1867 unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1869 unsigned tile_mode_index
= 0;
1872 tile_mode_index
= rtex
->surface
.stencil_tiling_index
[level
];
1874 tile_mode_index
= rtex
->surface
.tiling_index
[level
];
1876 return tile_mode_index
;
1880 * framebuffer handling
1883 static void si_initialize_color_surface(struct si_context
*sctx
,
1884 struct r600_surface
*surf
)
1886 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1887 unsigned level
= surf
->base
.u
.tex
.level
;
1888 uint64_t offset
= rtex
->surface
.level
[level
].offset
;
1889 unsigned pitch
, slice
;
1890 unsigned color_info
, color_attrib
, color_pitch
, color_view
;
1891 unsigned tile_mode_index
;
1892 unsigned format
, swap
, ntype
, endian
;
1893 const struct util_format_description
*desc
;
1895 unsigned blend_clamp
= 0, blend_bypass
= 0;
1896 unsigned max_comp_size
;
1898 /* Layered rendering doesn't work with LINEAR_GENERAL.
1899 * (LINEAR_ALIGNED and others work) */
1900 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
1901 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
1902 offset
+= rtex
->surface
.level
[level
].slice_size
*
1903 surf
->base
.u
.tex
.first_layer
;
1906 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1907 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1910 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1911 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1916 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1918 desc
= util_format_description(surf
->base
.format
);
1919 for (i
= 0; i
< 4; i
++) {
1920 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1924 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1925 ntype
= V_028C70_NUMBER_FLOAT
;
1927 ntype
= V_028C70_NUMBER_UNORM
;
1928 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1929 ntype
= V_028C70_NUMBER_SRGB
;
1930 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1931 if (desc
->channel
[i
].pure_integer
) {
1932 ntype
= V_028C70_NUMBER_SINT
;
1934 assert(desc
->channel
[i
].normalized
);
1935 ntype
= V_028C70_NUMBER_SNORM
;
1937 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1938 if (desc
->channel
[i
].pure_integer
) {
1939 ntype
= V_028C70_NUMBER_UINT
;
1941 assert(desc
->channel
[i
].normalized
);
1942 ntype
= V_028C70_NUMBER_UNORM
;
1947 format
= si_translate_colorformat(surf
->base
.format
);
1948 if (format
== V_028C70_COLOR_INVALID
) {
1949 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
1951 assert(format
!= V_028C70_COLOR_INVALID
);
1952 swap
= r600_translate_colorswap(surf
->base
.format
);
1953 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1954 endian
= V_028C70_ENDIAN_NONE
;
1956 endian
= si_colorformat_endian_swap(format
);
1959 /* blend clamp should be set for all NORM/SRGB types */
1960 if (ntype
== V_028C70_NUMBER_UNORM
||
1961 ntype
== V_028C70_NUMBER_SNORM
||
1962 ntype
== V_028C70_NUMBER_SRGB
)
1965 /* set blend bypass according to docs if SINT/UINT or
1966 8/24 COLOR variants */
1967 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1968 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1969 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1974 color_info
= S_028C70_FORMAT(format
) |
1975 S_028C70_COMP_SWAP(swap
) |
1976 S_028C70_BLEND_CLAMP(blend_clamp
) |
1977 S_028C70_BLEND_BYPASS(blend_bypass
) |
1978 S_028C70_NUMBER_TYPE(ntype
) |
1979 S_028C70_ENDIAN(endian
);
1981 color_pitch
= S_028C64_TILE_MAX(pitch
);
1983 color_attrib
= S_028C74_TILE_MODE_INDEX(tile_mode_index
) |
1984 S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == UTIL_FORMAT_SWIZZLE_1
);
1986 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1987 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1989 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1990 S_028C74_NUM_FRAGMENTS(log_samples
);
1992 if (rtex
->fmask
.size
) {
1993 color_info
|= S_028C70_COMPRESSION(1);
1994 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
1996 color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(rtex
->fmask
.tile_mode_index
);
1998 if (sctx
->b
.chip_class
== SI
) {
1999 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2000 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2002 if (sctx
->b
.chip_class
>= CIK
) {
2003 color_pitch
|= S_028C64_FMASK_TILE_MAX(rtex
->fmask
.pitch_in_pixels
/ 8 - 1);
2008 offset
+= rtex
->resource
.gpu_address
;
2010 surf
->cb_color_base
= offset
>> 8;
2011 surf
->cb_color_pitch
= color_pitch
;
2012 surf
->cb_color_slice
= S_028C68_TILE_MAX(slice
);
2013 surf
->cb_color_view
= color_view
;
2014 surf
->cb_color_info
= color_info
;
2015 surf
->cb_color_attrib
= color_attrib
;
2017 if (sctx
->b
.chip_class
>= VI
&& rtex
->dcc_buffer
) {
2018 unsigned max_uncompressed_block_size
= 2;
2019 uint64_t dcc_offset
= rtex
->surface
.level
[level
].dcc_offset
;
2021 if (rtex
->surface
.nsamples
> 1) {
2022 if (rtex
->surface
.bpe
== 1)
2023 max_uncompressed_block_size
= 0;
2024 else if (rtex
->surface
.bpe
== 2)
2025 max_uncompressed_block_size
= 1;
2028 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2029 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2030 surf
->cb_dcc_base
= (rtex
->dcc_buffer
->gpu_address
+ dcc_offset
) >> 8;
2033 if (rtex
->fmask
.size
) {
2034 surf
->cb_color_fmask
= (offset
+ rtex
->fmask
.offset
) >> 8;
2035 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
2037 /* This must be set for fast clear to work without FMASK. */
2038 surf
->cb_color_fmask
= surf
->cb_color_base
;
2039 surf
->cb_color_fmask_slice
= surf
->cb_color_slice
;
2040 surf
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2042 if (sctx
->b
.chip_class
== SI
) {
2043 unsigned bankh
= util_logbase2(rtex
->surface
.bankh
);
2044 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2047 if (sctx
->b
.chip_class
>= CIK
) {
2048 surf
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch
);
2052 /* Determine pixel shader export format */
2053 max_comp_size
= si_colorformat_max_comp_size(format
);
2054 if (ntype
== V_028C70_NUMBER_SRGB
||
2055 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
2056 max_comp_size
<= 10) ||
2057 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
2058 surf
->export_16bpc
= true;
2061 if (sctx
->b
.family
== CHIP_STONEY
&&
2062 !(sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
)) {
2063 switch (desc
->channel
[0].size
) {
2065 if (desc
->nr_channels
== 1) {
2066 if (swap
== V_0280A0_SWAP_STD
)
2067 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
2068 else if (swap
== V_0280A0_SWAP_ALT_REV
)
2069 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_A
;
2073 /* For 1-channel formats, use the superset thereof. */
2074 if (desc
->nr_channels
<= 2) {
2075 if (swap
== V_0280A0_SWAP_STD
||
2076 swap
== V_0280A0_SWAP_STD_REV
)
2077 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_16_16_GR
;
2079 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_16_16_AR
;
2083 if (desc
->nr_channels
== 3) {
2084 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_10_11_11
;
2085 surf
->sx_blend_opt_epsilon
= V_028758_11BIT_FORMAT
;
2089 if (desc
->nr_channels
== 4) {
2090 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_2_10_10_10
;
2091 surf
->sx_blend_opt_epsilon
= V_028758_10BIT_FORMAT
;
2095 /* For 1 and 2-channel formats, use the superset thereof. */
2096 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_8_8_8_8
;
2097 surf
->sx_blend_opt_epsilon
= V_028758_8BIT_FORMAT
;
2100 if (desc
->nr_channels
== 3) {
2101 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_5_6_5
;
2102 surf
->sx_blend_opt_epsilon
= V_028758_6BIT_FORMAT
;
2103 } else if (desc
->nr_channels
== 4) {
2104 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_1_5_5_5
;
2105 surf
->sx_blend_opt_epsilon
= V_028758_5BIT_FORMAT
;
2109 /* For 1 nad 2-channel formats, use the superset thereof. */
2110 surf
->sx_ps_downconvert
= V_028754_SX_RT_EXPORT_4_4_4_4
;
2111 surf
->sx_blend_opt_epsilon
= V_028758_4BIT_FORMAT
;
2116 surf
->color_initialized
= true;
2119 static void si_init_depth_surface(struct si_context
*sctx
,
2120 struct r600_surface
*surf
)
2122 struct si_screen
*sscreen
= sctx
->screen
;
2123 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2124 unsigned level
= surf
->base
.u
.tex
.level
;
2125 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
2126 unsigned format
, tile_mode_index
, array_mode
;
2127 unsigned macro_aspect
, tile_split
, stile_split
, bankh
, bankw
, nbanks
, pipe_config
;
2128 uint32_t z_info
, s_info
, db_depth_info
;
2129 uint64_t z_offs
, s_offs
;
2130 uint32_t db_htile_data_base
, db_htile_surface
, pa_su_poly_offset_db_fmt_cntl
= 0;
2132 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
2133 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2134 case PIPE_FORMAT_X8Z24_UNORM
:
2135 case PIPE_FORMAT_Z24X8_UNORM
:
2136 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2137 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2139 case PIPE_FORMAT_Z32_FLOAT
:
2140 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2141 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2142 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2144 case PIPE_FORMAT_Z16_UNORM
:
2145 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2151 format
= si_translate_dbformat(rtex
->resource
.b
.b
.format
);
2153 if (format
== V_028040_Z_INVALID
) {
2154 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2156 assert(format
!= V_028040_Z_INVALID
);
2158 s_offs
= z_offs
= rtex
->resource
.gpu_address
;
2159 z_offs
+= rtex
->surface
.level
[level
].offset
;
2160 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
2162 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2164 z_info
= S_028040_FORMAT(format
);
2165 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2166 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2169 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2170 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2172 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2174 if (sctx
->b
.chip_class
>= CIK
) {
2175 switch (rtex
->surface
.level
[level
].mode
) {
2176 case RADEON_SURF_MODE_2D
:
2177 array_mode
= V_02803C_ARRAY_2D_TILED_THIN1
;
2179 case RADEON_SURF_MODE_1D
:
2180 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
2181 case RADEON_SURF_MODE_LINEAR
:
2183 array_mode
= V_02803C_ARRAY_1D_TILED_THIN1
;
2186 tile_split
= rtex
->surface
.tile_split
;
2187 stile_split
= rtex
->surface
.stencil_tile_split
;
2188 macro_aspect
= rtex
->surface
.mtilea
;
2189 bankw
= rtex
->surface
.bankw
;
2190 bankh
= rtex
->surface
.bankh
;
2191 tile_split
= cik_tile_split(tile_split
);
2192 stile_split
= cik_tile_split(stile_split
);
2193 macro_aspect
= cik_macro_tile_aspect(macro_aspect
);
2194 bankw
= cik_bank_wh(bankw
);
2195 bankh
= cik_bank_wh(bankh
);
2196 nbanks
= si_num_banks(sscreen
, rtex
);
2197 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2198 pipe_config
= cik_db_pipe_config(sscreen
, tile_mode_index
);
2200 db_depth_info
|= S_02803C_ARRAY_MODE(array_mode
) |
2201 S_02803C_PIPE_CONFIG(pipe_config
) |
2202 S_02803C_BANK_WIDTH(bankw
) |
2203 S_02803C_BANK_HEIGHT(bankh
) |
2204 S_02803C_MACRO_TILE_ASPECT(macro_aspect
) |
2205 S_02803C_NUM_BANKS(nbanks
);
2206 z_info
|= S_028040_TILE_SPLIT(tile_split
);
2207 s_info
|= S_028044_TILE_SPLIT(stile_split
);
2209 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2210 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2211 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2212 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2215 /* HiZ aka depth buffer htile */
2216 /* use htile only for first level */
2217 if (rtex
->htile_buffer
&& !level
) {
2218 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2219 S_028040_ALLOW_EXPCLEAR(1);
2221 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2222 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2224 /* Use all of the htile_buffer for depth if there's no stencil. */
2225 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2227 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
2228 db_htile_data_base
= va
>> 8;
2229 db_htile_surface
= S_028ABC_FULL_CACHE(1);
2231 db_htile_data_base
= 0;
2232 db_htile_surface
= 0;
2235 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2237 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2238 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2239 surf
->db_htile_data_base
= db_htile_data_base
;
2240 surf
->db_depth_info
= db_depth_info
;
2241 surf
->db_z_info
= z_info
;
2242 surf
->db_stencil_info
= s_info
;
2243 surf
->db_depth_base
= z_offs
>> 8;
2244 surf
->db_stencil_base
= s_offs
>> 8;
2245 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2246 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2247 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2248 levelinfo
->nblk_y
) / 64 - 1);
2249 surf
->db_htile_surface
= db_htile_surface
;
2250 surf
->pa_su_poly_offset_db_fmt_cntl
= pa_su_poly_offset_db_fmt_cntl
;
2252 surf
->depth_initialized
= true;
2255 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2256 const struct pipe_framebuffer_state
*state
)
2258 struct si_context
*sctx
= (struct si_context
*)ctx
;
2259 struct pipe_constant_buffer constbuf
= {0};
2260 struct r600_surface
*surf
= NULL
;
2261 struct r600_texture
*rtex
;
2262 bool old_cb0_is_integer
= sctx
->framebuffer
.cb0_is_integer
;
2263 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2266 /* Only flush TC when changing the framebuffer state, because
2267 * the only client not using TC that can change textures is
2270 * Flush all CB and DB caches here because all buffers can be used
2271 * for write by both TC (with shader image stores) and CB/DB.
2273 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2274 SI_CONTEXT_INV_GLOBAL_L2
|
2275 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
;
2277 /* Take the maximum of the old and new count. If the new count is lower,
2278 * dirtying is needed to disable the unbound colorbuffers.
2280 sctx
->framebuffer
.dirty_cbufs
|=
2281 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2282 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2284 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2286 sctx
->framebuffer
.export_16bpc
= 0;
2287 sctx
->framebuffer
.compressed_cb_mask
= 0;
2288 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2289 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2290 sctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
2291 util_format_is_pure_integer(state
->cbufs
[0]->format
);
2293 if (sctx
->framebuffer
.cb0_is_integer
!= old_cb0_is_integer
)
2294 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2296 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2297 if (!state
->cbufs
[i
])
2300 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2301 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2303 if (!surf
->color_initialized
) {
2304 si_initialize_color_surface(sctx
, surf
);
2307 if (surf
->export_16bpc
) {
2308 sctx
->framebuffer
.export_16bpc
|= 1 << i
;
2311 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
2312 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2314 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2316 /* Set the 16BPC export for possible dual-src blending. */
2317 if (i
== 1 && surf
&& surf
->export_16bpc
) {
2318 sctx
->framebuffer
.export_16bpc
|= 1 << 1;
2321 assert(!(sctx
->framebuffer
.export_16bpc
& ~0xff));
2324 surf
= (struct r600_surface
*)state
->zsbuf
;
2326 if (!surf
->depth_initialized
) {
2327 si_init_depth_surface(sctx
, surf
);
2329 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2332 si_update_poly_offset_state(sctx
);
2333 si_mark_atom_dirty(sctx
, &sctx
->cb_target_mask
);
2334 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2336 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2337 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2338 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2340 /* Set sample locations as fragment shader constants. */
2341 switch (sctx
->framebuffer
.nr_samples
) {
2343 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2346 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2349 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2352 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2355 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2360 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2361 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_FRAGMENT
,
2362 SI_DRIVER_STATE_CONST_BUF
, &constbuf
);
2364 /* Smoothing (only possible with nr_samples == 1) uses the same
2365 * sample locations as the MSAA it simulates.
2367 * Therefore, don't update the sample locations when
2368 * transitioning from no AA to smoothing-equivalent AA, and
2371 if ((sctx
->framebuffer
.nr_samples
!= 1 ||
2372 old_nr_samples
!= SI_NUM_SMOOTH_AA_SAMPLES
) &&
2373 (sctx
->framebuffer
.nr_samples
!= SI_NUM_SMOOTH_AA_SAMPLES
||
2374 old_nr_samples
!= 1))
2375 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
);
2379 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2381 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2382 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2383 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2384 struct r600_texture
*tex
= NULL
;
2385 struct r600_surface
*cb
= NULL
;
2386 uint32_t sx_ps_downconvert
= 0;
2387 uint32_t sx_blend_opt_epsilon
= 0;
2390 for (i
= 0; i
< nr_cbufs
; i
++) {
2391 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2394 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2396 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2397 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2401 tex
= (struct r600_texture
*)cb
->base
.texture
;
2402 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2403 &tex
->resource
, RADEON_USAGE_READWRITE
,
2404 tex
->surface
.nsamples
> 1 ?
2405 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2406 RADEON_PRIO_COLOR_BUFFER
);
2408 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2409 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2410 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2414 if (tex
->dcc_buffer
&& tex
->dcc_buffer
!= &tex
->resource
) {
2415 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2416 tex
->dcc_buffer
, RADEON_USAGE_READWRITE
,
2420 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2421 sctx
->b
.chip_class
>= VI
? 14 : 13);
2422 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2423 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2424 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2425 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2426 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2427 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2428 radeon_emit(cs
, cb
->cb_dcc_control
); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2429 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
2430 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2431 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2432 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2433 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2434 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2436 if (sctx
->b
.chip_class
>= VI
)
2437 radeon_emit(cs
, cb
->cb_dcc_base
); /* R_028C94_CB_COLOR0_DCC_BASE */
2439 sx_ps_downconvert
|= cb
->sx_ps_downconvert
<< (4 * i
);
2440 sx_blend_opt_epsilon
|= cb
->sx_blend_opt_epsilon
<< (4 * i
);
2442 /* set CB_COLOR1_INFO for possible dual-src blending */
2443 if (i
== 1 && state
->cbufs
[0] &&
2444 sctx
->framebuffer
.dirty_cbufs
& (1 << 0)) {
2445 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
2446 cb
->cb_color_info
| tex
->cb_color_info
);
2447 sx_ps_downconvert
|= cb
->sx_ps_downconvert
<< (4 * i
);
2448 sx_blend_opt_epsilon
|= cb
->sx_blend_opt_epsilon
<< (4 * i
);
2452 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
2453 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2455 if (sctx
->b
.family
== CHIP_STONEY
) {
2456 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 2);
2457 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
2458 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
2462 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
2463 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2464 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2466 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2467 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2468 zb
->base
.texture
->nr_samples
> 1 ?
2469 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2470 RADEON_PRIO_DEPTH_BUFFER
);
2472 if (zb
->db_htile_data_base
) {
2473 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2474 rtex
->htile_buffer
, RADEON_USAGE_READWRITE
,
2478 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2479 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2481 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2482 radeon_emit(cs
, zb
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
2483 radeon_emit(cs
, zb
->db_z_info
| /* R_028040_DB_Z_INFO */
2484 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2485 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2486 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2487 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2488 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2489 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2490 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2491 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2493 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
2494 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
2495 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
2497 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2498 radeon_set_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2499 zb
->pa_su_poly_offset_db_fmt_cntl
);
2500 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
2501 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2502 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2503 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2506 /* Framebuffer dimensions. */
2507 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2508 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2509 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2511 sctx
->framebuffer
.dirty_cbufs
= 0;
2512 sctx
->framebuffer
.dirty_zsbuf
= false;
2515 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
2516 struct r600_atom
*atom
)
2518 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2519 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2521 cayman_emit_msaa_sample_locs(cs
, nr_samples
> 1 ? nr_samples
:
2522 SI_NUM_SMOOTH_AA_SAMPLES
);
2525 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
2527 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2529 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2530 sctx
->ps_iter_samples
,
2531 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0);
2535 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
2537 struct si_context
*sctx
= (struct si_context
*)ctx
;
2539 if (sctx
->ps_iter_samples
== min_samples
)
2542 sctx
->ps_iter_samples
= min_samples
;
2544 if (sctx
->framebuffer
.nr_samples
> 1)
2545 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2553 * Create a sampler view.
2555 * @param ctx context
2556 * @param texture texture
2557 * @param state sampler view template
2558 * @param width0 width0 override (for compressed textures as int)
2559 * @param height0 height0 override (for compressed textures as int)
2560 * @param force_level set the base address to the level (for compressed textures)
2562 struct pipe_sampler_view
*
2563 si_create_sampler_view_custom(struct pipe_context
*ctx
,
2564 struct pipe_resource
*texture
,
2565 const struct pipe_sampler_view
*state
,
2566 unsigned width0
, unsigned height0
,
2567 unsigned force_level
)
2569 struct si_context
*sctx
= (struct si_context
*)ctx
;
2570 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
2571 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
2572 const struct util_format_description
*desc
;
2573 unsigned format
, num_format
, base_level
, first_level
, last_level
;
2575 unsigned char state_swizzle
[4], swizzle
[4];
2576 unsigned height
, depth
, width
;
2577 enum pipe_format pipe_format
= state
->format
;
2578 struct radeon_surf_level
*surflevel
;
2581 unsigned last_layer
= state
->u
.tex
.last_layer
;
2586 /* initialize base object */
2587 view
->base
= *state
;
2588 view
->base
.texture
= NULL
;
2589 view
->base
.reference
.count
= 1;
2590 view
->base
.context
= ctx
;
2592 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2594 view
->state
[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state
->swizzle_r
)) |
2595 S_008F1C_DST_SEL_Y(si_map_swizzle(state
->swizzle_g
)) |
2596 S_008F1C_DST_SEL_Z(si_map_swizzle(state
->swizzle_b
)) |
2597 S_008F1C_DST_SEL_W(si_map_swizzle(state
->swizzle_a
)) |
2598 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
);
2602 pipe_resource_reference(&view
->base
.texture
, texture
);
2603 view
->resource
= &tmp
->resource
;
2605 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
2606 state
->format
== PIPE_FORMAT_S8X24_UINT
||
2607 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
2608 state
->format
== PIPE_FORMAT_S8_UINT
)
2609 view
->is_stencil_sampler
= true;
2611 /* Buffer resource. */
2612 if (texture
->target
== PIPE_BUFFER
) {
2613 unsigned stride
, num_records
;
2615 desc
= util_format_description(state
->format
);
2616 first_non_void
= util_format_get_first_non_void_channel(state
->format
);
2617 stride
= desc
->block
.bits
/ 8;
2618 va
= tmp
->resource
.gpu_address
+ state
->u
.buf
.first_element
*stride
;
2619 format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2620 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2622 num_records
= state
->u
.buf
.last_element
+ 1 - state
->u
.buf
.first_element
;
2623 num_records
= MIN2(num_records
, texture
->width0
/ stride
);
2625 if (sctx
->b
.chip_class
>= VI
)
2626 num_records
*= stride
;
2628 view
->state
[4] = va
;
2629 view
->state
[5] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
2630 S_008F04_STRIDE(stride
);
2631 view
->state
[6] = num_records
;
2632 view
->state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2633 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2634 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2635 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2636 S_008F0C_NUM_FORMAT(num_format
) |
2637 S_008F0C_DATA_FORMAT(format
);
2639 LIST_ADDTAIL(&view
->list
, &sctx
->b
.texture_buffers
);
2643 state_swizzle
[0] = state
->swizzle_r
;
2644 state_swizzle
[1] = state
->swizzle_g
;
2645 state_swizzle
[2] = state
->swizzle_b
;
2646 state_swizzle
[3] = state
->swizzle_a
;
2648 surflevel
= tmp
->surface
.level
;
2650 /* Texturing with separate depth and stencil. */
2651 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
2652 switch (pipe_format
) {
2653 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2654 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2656 case PIPE_FORMAT_X8Z24_UNORM
:
2657 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2658 /* Z24 is always stored like this. */
2659 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2661 case PIPE_FORMAT_X24S8_UINT
:
2662 case PIPE_FORMAT_S8X24_UINT
:
2663 case PIPE_FORMAT_X32_S8X24_UINT
:
2664 pipe_format
= PIPE_FORMAT_S8_UINT
;
2665 surflevel
= tmp
->surface
.stencil_level
;
2671 desc
= util_format_description(pipe_format
);
2673 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2674 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2675 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2677 switch (pipe_format
) {
2678 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2679 case PIPE_FORMAT_X24S8_UINT
:
2680 case PIPE_FORMAT_X32_S8X24_UINT
:
2681 case PIPE_FORMAT_X8Z24_UNORM
:
2682 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2685 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2688 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2691 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2693 switch (pipe_format
) {
2694 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2695 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2698 if (first_non_void
< 0) {
2699 if (util_format_is_compressed(pipe_format
)) {
2700 switch (pipe_format
) {
2701 case PIPE_FORMAT_DXT1_SRGB
:
2702 case PIPE_FORMAT_DXT1_SRGBA
:
2703 case PIPE_FORMAT_DXT3_SRGBA
:
2704 case PIPE_FORMAT_DXT5_SRGBA
:
2705 case PIPE_FORMAT_BPTC_SRGBA
:
2706 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2708 case PIPE_FORMAT_RGTC1_SNORM
:
2709 case PIPE_FORMAT_LATC1_SNORM
:
2710 case PIPE_FORMAT_RGTC2_SNORM
:
2711 case PIPE_FORMAT_LATC2_SNORM
:
2712 /* implies float, so use SNORM/UNORM to determine
2713 whether data is signed or not */
2714 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2715 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2718 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2721 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2722 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2724 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2726 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2727 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2729 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2731 switch (desc
->channel
[first_non_void
].type
) {
2732 case UTIL_FORMAT_TYPE_FLOAT
:
2733 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2735 case UTIL_FORMAT_TYPE_SIGNED
:
2736 if (desc
->channel
[first_non_void
].normalized
)
2737 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2738 else if (desc
->channel
[first_non_void
].pure_integer
)
2739 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2741 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2743 case UTIL_FORMAT_TYPE_UNSIGNED
:
2744 if (desc
->channel
[first_non_void
].normalized
)
2745 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2746 else if (desc
->channel
[first_non_void
].pure_integer
)
2747 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2749 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2754 format
= si_translate_texformat(ctx
->screen
, pipe_format
, desc
, first_non_void
);
2760 first_level
= state
->u
.tex
.first_level
;
2761 last_level
= state
->u
.tex
.last_level
;
2764 depth
= texture
->depth0
;
2767 assert(force_level
== first_level
&&
2768 force_level
== last_level
);
2769 base_level
= force_level
;
2772 width
= u_minify(width
, force_level
);
2773 height
= u_minify(height
, force_level
);
2774 depth
= u_minify(depth
, force_level
);
2777 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
2779 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2781 depth
= texture
->array_size
;
2782 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2783 depth
= texture
->array_size
;
2784 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
2785 depth
= texture
->array_size
/ 6;
2787 /* This is not needed if state trackers set last_layer correctly. */
2788 if (state
->target
== PIPE_TEXTURE_1D
||
2789 state
->target
== PIPE_TEXTURE_2D
||
2790 state
->target
== PIPE_TEXTURE_RECT
||
2791 state
->target
== PIPE_TEXTURE_CUBE
)
2792 last_layer
= state
->u
.tex
.first_layer
;
2794 va
= tmp
->resource
.gpu_address
+ surflevel
[base_level
].offset
;
2796 view
->state
[0] = va
>> 8;
2797 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2798 S_008F14_DATA_FORMAT(format
) |
2799 S_008F14_NUM_FORMAT(num_format
));
2800 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2801 S_008F18_HEIGHT(height
- 1));
2802 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2803 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2804 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2805 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2806 S_008F1C_BASE_LEVEL(texture
->nr_samples
> 1 ?
2808 S_008F1C_LAST_LEVEL(texture
->nr_samples
> 1 ?
2809 util_logbase2(texture
->nr_samples
) :
2811 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp
, base_level
, false)) |
2812 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2813 S_008F1C_TYPE(si_tex_dim(texture
->target
, state
->target
,
2814 texture
->nr_samples
)));
2815 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2816 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2817 S_008F24_LAST_ARRAY(last_layer
));
2819 if (tmp
->dcc_buffer
) {
2820 uint64_t dcc_offset
= surflevel
[base_level
].dcc_offset
;
2821 unsigned swap
= r600_translate_colorswap(pipe_format
);
2823 view
->state
[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
2824 view
->state
[7] = (tmp
->dcc_buffer
->gpu_address
+ dcc_offset
) >> 8;
2825 view
->dcc_buffer
= tmp
->dcc_buffer
;
2831 /* Initialize the sampler view for FMASK. */
2832 if (tmp
->fmask
.size
) {
2833 uint64_t va
= tmp
->resource
.gpu_address
+ tmp
->fmask
.offset
;
2834 uint32_t fmask_format
;
2836 switch (texture
->nr_samples
) {
2838 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2841 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2844 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2848 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2851 view
->fmask_state
[0] = va
>> 8;
2852 view
->fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2853 S_008F14_DATA_FORMAT(fmask_format
) |
2854 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2855 view
->fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2856 S_008F18_HEIGHT(height
- 1);
2857 view
->fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2858 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
2859 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
2860 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
2861 S_008F1C_TILING_INDEX(tmp
->fmask
.tile_mode_index
) |
2862 S_008F1C_TYPE(si_tex_dim(texture
->target
,
2864 view
->fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
2865 S_008F20_PITCH(tmp
->fmask
.pitch_in_pixels
- 1);
2866 view
->fmask_state
[5] = S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2867 S_008F24_LAST_ARRAY(last_layer
);
2868 view
->fmask_state
[6] = 0;
2869 view
->fmask_state
[7] = 0;
2875 static struct pipe_sampler_view
*
2876 si_create_sampler_view(struct pipe_context
*ctx
,
2877 struct pipe_resource
*texture
,
2878 const struct pipe_sampler_view
*state
)
2880 return si_create_sampler_view_custom(ctx
, texture
, state
,
2881 texture
? texture
->width0
: 0,
2882 texture
? texture
->height0
: 0, 0);
2885 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2886 struct pipe_sampler_view
*state
)
2888 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
2890 if (view
->resource
&& view
->resource
->b
.b
.target
== PIPE_BUFFER
)
2891 LIST_DELINIT(&view
->list
);
2893 pipe_resource_reference(&state
->texture
, NULL
);
2897 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2899 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2900 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2902 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2903 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2906 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2908 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2909 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2911 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2912 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2913 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2914 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2915 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2918 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2919 const struct pipe_sampler_state
*state
)
2921 struct si_context
*sctx
= (struct si_context
*)ctx
;
2922 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
2923 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2924 unsigned border_color_type
, border_color_index
= 0;
2930 if (!sampler_state_needs_border_color(state
))
2931 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2932 else if (state
->border_color
.f
[0] == 0 &&
2933 state
->border_color
.f
[1] == 0 &&
2934 state
->border_color
.f
[2] == 0 &&
2935 state
->border_color
.f
[3] == 0)
2936 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2937 else if (state
->border_color
.f
[0] == 0 &&
2938 state
->border_color
.f
[1] == 0 &&
2939 state
->border_color
.f
[2] == 0 &&
2940 state
->border_color
.f
[3] == 1)
2941 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
2942 else if (state
->border_color
.f
[0] == 1 &&
2943 state
->border_color
.f
[1] == 1 &&
2944 state
->border_color
.f
[2] == 1 &&
2945 state
->border_color
.f
[3] == 1)
2946 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
2950 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2952 /* Check if the border has been uploaded already. */
2953 for (i
= 0; i
< sctx
->border_color_count
; i
++)
2954 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
2955 sizeof(state
->border_color
)) == 0)
2958 if (i
>= SI_MAX_BORDER_COLORS
) {
2959 /* Getting 4096 unique border colors is very unlikely. */
2960 fprintf(stderr
, "radeonsi: The border color table is full. "
2961 "Any new border colors will be just black. "
2962 "Please file a bug.\n");
2963 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2965 if (i
== sctx
->border_color_count
) {
2966 /* Upload a new border color. */
2967 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
2968 sizeof(state
->border_color
));
2969 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
2970 &state
->border_color
,
2971 sizeof(state
->border_color
));
2972 sctx
->border_color_count
++;
2975 border_color_index
= i
;
2979 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2980 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2981 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2982 r600_tex_aniso_filter(state
->max_anisotropy
) << 9 |
2983 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2984 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2985 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2986 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2987 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2988 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2989 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
2990 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
2991 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2992 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
2993 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2997 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2999 struct si_context
*sctx
= (struct si_context
*)ctx
;
3001 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
3004 sctx
->sample_mask
.sample_mask
= sample_mask
;
3005 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
3008 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
3010 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3011 unsigned mask
= sctx
->sample_mask
.sample_mask
;
3013 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3014 radeon_emit(cs
, mask
| (mask
<< 16));
3015 radeon_emit(cs
, mask
| (mask
<< 16));
3018 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3024 * Vertex elements & buffers
3027 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3029 const struct pipe_vertex_element
*elements
)
3031 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
3034 assert(count
< SI_MAX_ATTRIBS
);
3039 for (i
= 0; i
< count
; ++i
) {
3040 const struct util_format_description
*desc
;
3041 unsigned data_format
, num_format
;
3044 desc
= util_format_description(elements
[i
].src_format
);
3045 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3046 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3047 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3049 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3050 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3051 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3052 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3053 S_008F0C_NUM_FORMAT(num_format
) |
3054 S_008F0C_DATA_FORMAT(data_format
);
3055 v
->format_size
[i
] = desc
->block
.bits
/ 8;
3057 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3062 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3064 struct si_context
*sctx
= (struct si_context
*)ctx
;
3065 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3067 sctx
->vertex_elements
= v
;
3068 sctx
->vertex_buffers_dirty
= true;
3071 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3073 struct si_context
*sctx
= (struct si_context
*)ctx
;
3075 if (sctx
->vertex_elements
== state
)
3076 sctx
->vertex_elements
= NULL
;
3080 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
3081 unsigned start_slot
, unsigned count
,
3082 const struct pipe_vertex_buffer
*buffers
)
3084 struct si_context
*sctx
= (struct si_context
*)ctx
;
3085 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
3088 assert(start_slot
+ count
<= Elements(sctx
->vertex_buffer
));
3091 for (i
= 0; i
< count
; i
++) {
3092 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
3093 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
3095 pipe_resource_reference(&dsti
->buffer
, src
->buffer
);
3096 dsti
->buffer_offset
= src
->buffer_offset
;
3097 dsti
->stride
= src
->stride
;
3098 r600_context_add_resource_size(ctx
, src
->buffer
);
3101 for (i
= 0; i
< count
; i
++) {
3102 pipe_resource_reference(&dst
[i
].buffer
, NULL
);
3105 sctx
->vertex_buffers_dirty
= true;
3108 static void si_set_index_buffer(struct pipe_context
*ctx
,
3109 const struct pipe_index_buffer
*ib
)
3111 struct si_context
*sctx
= (struct si_context
*)ctx
;
3114 pipe_resource_reference(&sctx
->index_buffer
.buffer
, ib
->buffer
);
3115 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3116 r600_context_add_resource_size(ctx
, ib
->buffer
);
3118 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3125 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
3126 const struct pipe_poly_stipple
*state
)
3128 struct si_context
*sctx
= (struct si_context
*)ctx
;
3129 struct pipe_resource
*tex
;
3130 struct pipe_sampler_view
*view
;
3131 bool is_zero
= true;
3135 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3136 * the resource is NULL/invalid. Take advantage of this fact and skip
3137 * texture allocation if the stipple pattern is constant.
3139 * This is an optimization for the common case when stippling isn't
3140 * used but set_polygon_stipple is still called by st/mesa.
3142 for (i
= 0; i
< Elements(state
->stipple
); i
++) {
3143 is_zero
= is_zero
&& state
->stipple
[i
] == 0;
3144 is_one
= is_one
&& state
->stipple
[i
] == 0xffffffff;
3147 if (is_zero
|| is_one
) {
3148 struct pipe_sampler_view templ
= {{0}};
3150 templ
.swizzle_r
= PIPE_SWIZZLE_ZERO
;
3151 templ
.swizzle_g
= PIPE_SWIZZLE_ZERO
;
3152 templ
.swizzle_b
= PIPE_SWIZZLE_ZERO
;
3153 /* The pattern should be inverted in the texture. */
3154 templ
.swizzle_a
= is_zero
? PIPE_SWIZZLE_ONE
: PIPE_SWIZZLE_ZERO
;
3156 view
= ctx
->create_sampler_view(ctx
, NULL
, &templ
);
3158 /* Create a new texture. */
3159 tex
= util_pstipple_create_stipple_texture(ctx
, state
->stipple
);
3163 view
= util_pstipple_create_sampler_view(ctx
, tex
);
3164 pipe_resource_reference(&tex
, NULL
);
3167 ctx
->set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
,
3168 SI_POLY_STIPPLE_SAMPLER
, 1, &view
);
3169 pipe_sampler_view_reference(&view
, NULL
);
3171 /* Bind the sampler state if needed. */
3172 if (!sctx
->pstipple_sampler_state
) {
3173 sctx
->pstipple_sampler_state
= util_pstipple_create_sampler(ctx
);
3174 ctx
->bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
,
3175 SI_POLY_STIPPLE_SAMPLER
, 1,
3176 &sctx
->pstipple_sampler_state
);
3180 static void si_set_tess_state(struct pipe_context
*ctx
,
3181 const float default_outer_level
[4],
3182 const float default_inner_level
[2])
3184 struct si_context
*sctx
= (struct si_context
*)ctx
;
3185 struct pipe_constant_buffer cb
;
3188 memcpy(array
, default_outer_level
, sizeof(float) * 4);
3189 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
3192 cb
.user_buffer
= NULL
;
3193 cb
.buffer_size
= sizeof(array
);
3195 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
3196 (void*)array
, sizeof(array
),
3199 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_TESS_CTRL
,
3200 SI_DRIVER_STATE_CONST_BUF
, &cb
);
3201 pipe_resource_reference(&cb
.buffer
, NULL
);
3204 static void si_texture_barrier(struct pipe_context
*ctx
)
3206 struct si_context
*sctx
= (struct si_context
*)ctx
;
3208 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
3209 SI_CONTEXT_INV_GLOBAL_L2
|
3210 SI_CONTEXT_FLUSH_AND_INV_CB
;
3213 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3215 struct pipe_blend_state blend
;
3217 memset(&blend
, 0, sizeof(blend
));
3218 blend
.independent_blend_enable
= true;
3219 blend
.rt
[0].colormask
= 0xf;
3220 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3223 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3224 bool include_draw_vbo
)
3226 si_need_cs_space((struct si_context
*)ctx
);
3229 static void si_init_config(struct si_context
*sctx
);
3231 void si_init_state_functions(struct si_context
*sctx
)
3233 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
3234 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
3235 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
3237 si_init_atom(sctx
, &sctx
->cache_flush
, &sctx
->atoms
.s
.cache_flush
, si_emit_cache_flush
);
3238 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
3239 si_init_atom(sctx
, &sctx
->msaa_sample_locs
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
3240 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
3241 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
3242 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
3243 si_init_atom(sctx
, &sctx
->cb_target_mask
, &sctx
->atoms
.s
.cb_target_mask
, si_emit_cb_target_mask
);
3244 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
3245 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
3246 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
3247 si_init_atom(sctx
, &sctx
->scissors
.atom
, &sctx
->atoms
.s
.scissors
, si_emit_scissors
);
3248 si_init_atom(sctx
, &sctx
->viewports
.atom
, &sctx
->atoms
.s
.viewports
, si_emit_viewports
);
3249 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
3251 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3252 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3253 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3254 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3256 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3257 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3258 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3260 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3261 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3262 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3264 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
3265 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3266 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3267 sctx
->custom_blend_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
3269 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3270 sctx
->b
.b
.set_scissor_states
= si_set_scissor_states
;
3271 sctx
->b
.b
.set_viewport_states
= si_set_viewport_states
;
3272 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
3274 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3275 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3277 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3278 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3280 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3281 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3283 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3285 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3286 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3287 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3288 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3289 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3291 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3292 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
3293 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
3294 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
3296 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3297 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3299 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3301 if (sctx
->b
.chip_class
>= CIK
) {
3302 sctx
->b
.dma_copy
= cik_sdma_copy
;
3304 sctx
->b
.dma_copy
= si_dma_copy
;
3307 si_init_config(sctx
);
3311 si_write_harvested_raster_configs(struct si_context
*sctx
,
3312 struct si_pm4_state
*pm4
,
3313 unsigned raster_config
,
3314 unsigned raster_config_1
)
3316 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
3317 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
3318 unsigned rb_mask
= sctx
->screen
->b
.info
.si_backend_enabled_mask
;
3319 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.r600_num_backends
, 16);
3320 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
3321 unsigned rb_per_se
= num_rb
/ num_se
;
3322 unsigned se_mask
[4];
3325 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
3326 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
3327 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
3328 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
3330 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
3331 assert(sh_per_se
== 1 || sh_per_se
== 2);
3332 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
3334 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3335 * fields are for, so I'm leaving them as their default
3338 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
3339 (!se_mask
[2] && !se_mask
[3]))) {
3340 raster_config_1
&= C_028354_SE_PAIR_MAP
;
3342 if (!se_mask
[0] && !se_mask
[1]) {
3344 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
3347 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
3351 for (se
= 0; se
< num_se
; se
++) {
3352 unsigned raster_config_se
= raster_config
;
3353 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
3354 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
3355 int idx
= (se
/ 2) * 2;
3357 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
3358 raster_config_se
&= C_028350_SE_MAP
;
3360 if (!se_mask
[idx
]) {
3362 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
3365 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
3369 pkr0_mask
&= rb_mask
;
3370 pkr1_mask
&= rb_mask
;
3371 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
3372 raster_config_se
&= C_028350_PKR_MAP
;
3376 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
3379 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
3383 if (rb_per_se
>= 2) {
3384 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
3385 unsigned rb1_mask
= rb0_mask
<< 1;
3387 rb0_mask
&= rb_mask
;
3388 rb1_mask
&= rb_mask
;
3389 if (!rb0_mask
|| !rb1_mask
) {
3390 raster_config_se
&= C_028350_RB_MAP_PKR0
;
3394 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
3397 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
3401 if (rb_per_se
> 2) {
3402 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
3403 rb1_mask
= rb0_mask
<< 1;
3404 rb0_mask
&= rb_mask
;
3405 rb1_mask
&= rb_mask
;
3406 if (!rb0_mask
|| !rb1_mask
) {
3407 raster_config_se
&= C_028350_RB_MAP_PKR1
;
3411 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
3414 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
3420 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3421 if (sctx
->b
.chip_class
< CIK
)
3422 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3423 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
3424 INSTANCE_BROADCAST_WRITES
);
3426 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3427 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
3428 S_030800_INSTANCE_BROADCAST_WRITES(1));
3429 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
3430 if (sctx
->b
.chip_class
>= CIK
)
3431 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
3434 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3435 if (sctx
->b
.chip_class
< CIK
)
3436 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3437 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
3438 INSTANCE_BROADCAST_WRITES
);
3440 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3441 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3442 S_030800_INSTANCE_BROADCAST_WRITES(1));
3445 static void si_init_config(struct si_context
*sctx
)
3447 struct si_screen
*sscreen
= sctx
->screen
;
3448 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.r600_num_backends
, 16);
3449 unsigned rb_mask
= sctx
->screen
->b
.info
.si_backend_enabled_mask
;
3450 unsigned raster_config
, raster_config_1
;
3451 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
3452 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3458 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
3459 si_pm4_cmd_add(pm4
, 0x80000000);
3460 si_pm4_cmd_add(pm4
, 0x80000000);
3461 si_pm4_cmd_end(pm4
, false);
3463 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
3464 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
3466 /* FIXME calculate these values somehow ??? */
3467 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
3468 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3469 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3471 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3472 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3474 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3475 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3476 if (sctx
->b
.chip_class
< CIK
)
3477 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3478 S_008A14_CLIP_VTX_REORDER_ENA(1));
3480 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3481 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3483 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3485 for (i
= 0; i
< 16; i
++) {
3486 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
3487 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
3490 switch (sctx
->screen
->b
.family
) {
3493 raster_config
= 0x2a00126a;
3494 raster_config_1
= 0x00000000;
3497 raster_config
= 0x0000124a;
3498 raster_config_1
= 0x00000000;
3501 raster_config
= 0x00000082;
3502 raster_config_1
= 0x00000000;
3505 raster_config
= 0x00000000;
3506 raster_config_1
= 0x00000000;
3509 raster_config
= 0x16000012;
3510 raster_config_1
= 0x00000000;
3513 raster_config
= 0x3a00161a;
3514 raster_config_1
= 0x0000002e;
3517 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
3518 /* old kernels with old tiling config */
3519 raster_config
= 0x16000012;
3520 raster_config_1
= 0x0000002a;
3522 raster_config
= 0x3a00161a;
3523 raster_config_1
= 0x0000002e;
3527 raster_config
= 0x16000012;
3528 raster_config_1
= 0x0000002a;
3531 raster_config
= 0x00000002;
3532 raster_config_1
= 0x00000000;
3535 raster_config
= 0x00000002;
3536 raster_config_1
= 0x00000000;
3539 /* KV should be 0x00000002, but that causes problems with radeon */
3540 raster_config
= 0x00000000; /* 0x00000002 */
3541 raster_config_1
= 0x00000000;
3546 raster_config
= 0x00000000;
3547 raster_config_1
= 0x00000000;
3551 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3552 raster_config
= 0x00000000;
3553 raster_config_1
= 0x00000000;
3557 /* Always use the default config when all backends are enabled
3558 * (or when we failed to determine the enabled backends).
3560 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
3561 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
3563 if (sctx
->b
.chip_class
>= CIK
)
3564 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
3567 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
3570 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
3571 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
3572 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
3573 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3574 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
3575 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
3576 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3578 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3579 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3580 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3581 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3582 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
3583 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, fui(1.0));
3584 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, fui(1.0));
3585 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, fui(1.0));
3586 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, fui(1.0));
3587 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
3588 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
3589 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
3590 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
3591 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3592 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
3594 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
3595 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
3596 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
3598 if (sctx
->b
.chip_class
>= CIK
) {
3599 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xfffc));
3600 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
3601 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xfffe));
3602 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
3603 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
3604 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(0));
3605 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
3608 if (sctx
->b
.chip_class
>= VI
) {
3609 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
3610 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3611 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3612 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
3613 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
3616 if (sctx
->b
.family
== CHIP_STONEY
)
3617 si_pm4_set_reg(pm4
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
3619 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
3620 if (sctx
->b
.chip_class
>= CIK
)
3621 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
3622 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
3623 RADEON_PRIO_BORDER_COLORS
);
3625 si_pm4_upload_indirect_buffer(sctx
, pm4
);
3626 sctx
->init_config
= pm4
;