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radeonsi: move clip plane constant buffer to RW buffers
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.info.r600_num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.num_render_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case UTIL_FORMAT_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case UTIL_FORMAT_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case UTIL_FORMAT_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case UTIL_FORMAT_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case UTIL_FORMAT_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
243 * is that:
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
248 *
249 * Another reason is to avoid a hang with dual source blending.
250 */
251 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
252 {
253 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
254 struct si_state_blend *blend = sctx->queued.named.blend;
255 uint32_t cb_target_mask = 0, i;
256
257 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
258 if (sctx->framebuffer.state.cbufs[i])
259 cb_target_mask |= 0xf << (4*i);
260
261 if (blend)
262 cb_target_mask &= blend->cb_target_mask;
263
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
267 *
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
269 */
270 if (blend && blend->dual_src_blend &&
271 sctx->ps_shader.cso &&
272 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
273 cb_target_mask = 0;
274
275 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
276
277 /* STONEY-specific register settings. */
278 if (sctx->b.family == CHIP_STONEY) {
279 unsigned spi_shader_col_format =
280 sctx->ps_shader.cso ?
281 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
282 unsigned sx_ps_downconvert = 0;
283 unsigned sx_blend_opt_epsilon = 0;
284 unsigned sx_blend_opt_control = 0;
285
286 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
287 struct r600_surface *surf =
288 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
289 unsigned format, swap, spi_format, colormask;
290 bool has_alpha, has_rgb;
291
292 if (!surf)
293 continue;
294
295 format = G_028C70_FORMAT(surf->cb_color_info);
296 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
297 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
298 colormask = (cb_target_mask >> (i * 4)) & 0xf;
299
300 /* Set if RGB and A are present. */
301 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
302
303 if (format == V_028C70_COLOR_8 ||
304 format == V_028C70_COLOR_16 ||
305 format == V_028C70_COLOR_32)
306 has_rgb = !has_alpha;
307 else
308 has_rgb = true;
309
310 /* Check the colormask and export format. */
311 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
312 has_rgb = false;
313 if (!(colormask & PIPE_MASK_A))
314 has_alpha = false;
315
316 if (spi_format == V_028714_SPI_SHADER_ZERO) {
317 has_rgb = false;
318 has_alpha = false;
319 }
320
321 /* Disable value checking for disabled channels. */
322 if (!has_rgb)
323 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
324 if (!has_alpha)
325 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
326
327 /* Enable down-conversion for 32bpp and smaller formats. */
328 switch (format) {
329 case V_028C70_COLOR_8:
330 case V_028C70_COLOR_8_8:
331 case V_028C70_COLOR_8_8_8_8:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
335 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
336 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
337 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
338 }
339 break;
340
341 case V_028C70_COLOR_5_6_5:
342 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
343 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
344 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
345 }
346 break;
347
348 case V_028C70_COLOR_1_5_5_5:
349 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
350 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
351 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
352 }
353 break;
354
355 case V_028C70_COLOR_4_4_4_4:
356 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
357 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
358 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
359 }
360 break;
361
362 case V_028C70_COLOR_32:
363 if (swap == V_0280A0_SWAP_STD &&
364 spi_format == V_028714_SPI_SHADER_32_R)
365 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
366 else if (swap == V_0280A0_SWAP_ALT_REV &&
367 spi_format == V_028714_SPI_SHADER_32_AR)
368 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
369 break;
370
371 case V_028C70_COLOR_16:
372 case V_028C70_COLOR_16_16:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
377 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
378 if (swap == V_0280A0_SWAP_STD ||
379 swap == V_0280A0_SWAP_STD_REV)
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
381 else
382 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
383 }
384 break;
385
386 case V_028C70_COLOR_10_11_11:
387 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
388 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
389 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
390 }
391 break;
392
393 case V_028C70_COLOR_2_10_10_10:
394 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
395 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
396 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
397 }
398 break;
399 }
400 }
401
402 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
403 sx_ps_downconvert = 0;
404 sx_blend_opt_epsilon = 0;
405 sx_blend_opt_control = 0;
406 }
407
408 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
409 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
412 }
413 }
414
415 /*
416 * Blender functions
417 */
418
419 static uint32_t si_translate_blend_function(int blend_func)
420 {
421 switch (blend_func) {
422 case PIPE_BLEND_ADD:
423 return V_028780_COMB_DST_PLUS_SRC;
424 case PIPE_BLEND_SUBTRACT:
425 return V_028780_COMB_SRC_MINUS_DST;
426 case PIPE_BLEND_REVERSE_SUBTRACT:
427 return V_028780_COMB_DST_MINUS_SRC;
428 case PIPE_BLEND_MIN:
429 return V_028780_COMB_MIN_DST_SRC;
430 case PIPE_BLEND_MAX:
431 return V_028780_COMB_MAX_DST_SRC;
432 default:
433 R600_ERR("Unknown blend function %d\n", blend_func);
434 assert(0);
435 break;
436 }
437 return 0;
438 }
439
440 static uint32_t si_translate_blend_factor(int blend_fact)
441 {
442 switch (blend_fact) {
443 case PIPE_BLENDFACTOR_ONE:
444 return V_028780_BLEND_ONE;
445 case PIPE_BLENDFACTOR_SRC_COLOR:
446 return V_028780_BLEND_SRC_COLOR;
447 case PIPE_BLENDFACTOR_SRC_ALPHA:
448 return V_028780_BLEND_SRC_ALPHA;
449 case PIPE_BLENDFACTOR_DST_ALPHA:
450 return V_028780_BLEND_DST_ALPHA;
451 case PIPE_BLENDFACTOR_DST_COLOR:
452 return V_028780_BLEND_DST_COLOR;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE;
455 case PIPE_BLENDFACTOR_CONST_COLOR:
456 return V_028780_BLEND_CONSTANT_COLOR;
457 case PIPE_BLENDFACTOR_CONST_ALPHA:
458 return V_028780_BLEND_CONSTANT_ALPHA;
459 case PIPE_BLENDFACTOR_ZERO:
460 return V_028780_BLEND_ZERO;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
473 case PIPE_BLENDFACTOR_SRC1_COLOR:
474 return V_028780_BLEND_SRC1_COLOR;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA:
476 return V_028780_BLEND_SRC1_ALPHA;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
478 return V_028780_BLEND_INV_SRC1_COLOR;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
480 return V_028780_BLEND_INV_SRC1_ALPHA;
481 default:
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
483 assert(0);
484 break;
485 }
486 return 0;
487 }
488
489 static uint32_t si_translate_blend_opt_function(int blend_func)
490 {
491 switch (blend_func) {
492 case PIPE_BLEND_ADD:
493 return V_028760_OPT_COMB_ADD;
494 case PIPE_BLEND_SUBTRACT:
495 return V_028760_OPT_COMB_SUBTRACT;
496 case PIPE_BLEND_REVERSE_SUBTRACT:
497 return V_028760_OPT_COMB_REVSUBTRACT;
498 case PIPE_BLEND_MIN:
499 return V_028760_OPT_COMB_MIN;
500 case PIPE_BLEND_MAX:
501 return V_028760_OPT_COMB_MAX;
502 default:
503 return V_028760_OPT_COMB_BLEND_DISABLED;
504 }
505 }
506
507 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
508 {
509 switch (blend_fact) {
510 case PIPE_BLENDFACTOR_ZERO:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
512 case PIPE_BLENDFACTOR_ONE:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
514 case PIPE_BLENDFACTOR_SRC_COLOR:
515 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
518 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
520 case PIPE_BLENDFACTOR_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
525 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
527 default:
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
529 }
530 }
531
532 /**
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 */
536 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
537 unsigned *dst_factor, unsigned expected_dst,
538 unsigned replacement_src)
539 {
540 if (*src_factor == expected_dst &&
541 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
542 *src_factor = PIPE_BLENDFACTOR_ZERO;
543 *dst_factor = replacement_src;
544
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func == PIPE_BLEND_SUBTRACT)
547 *func = PIPE_BLEND_REVERSE_SUBTRACT;
548 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
549 *func = PIPE_BLEND_SUBTRACT;
550 }
551 }
552
553 static bool si_blend_factor_uses_dst(unsigned factor)
554 {
555 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
556 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
559 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
560 }
561
562 static void *si_create_blend_state_mode(struct pipe_context *ctx,
563 const struct pipe_blend_state *state,
564 unsigned mode)
565 {
566 struct si_context *sctx = (struct si_context*)ctx;
567 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
568 struct si_pm4_state *pm4 = &blend->pm4;
569 uint32_t sx_mrt_blend_opt[8] = {0};
570 uint32_t color_control = 0;
571
572 if (!blend)
573 return NULL;
574
575 blend->alpha_to_coverage = state->alpha_to_coverage;
576 blend->alpha_to_one = state->alpha_to_one;
577 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
578
579 if (state->logicop_enable) {
580 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
581 } else {
582 color_control |= S_028808_ROP3(0xcc);
583 }
584
585 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
591
592 if (state->alpha_to_coverage)
593 blend->need_src_alpha_4bit |= 0xf;
594
595 blend->cb_target_mask = 0;
596 for (int i = 0; i < 8; i++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j = state->independent_blend_enable ? i : 0;
599
600 unsigned eqRGB = state->rt[j].rgb_func;
601 unsigned srcRGB = state->rt[j].rgb_src_factor;
602 unsigned dstRGB = state->rt[j].rgb_dst_factor;
603 unsigned eqA = state->rt[j].alpha_func;
604 unsigned srcA = state->rt[j].alpha_src_factor;
605 unsigned dstA = state->rt[j].alpha_dst_factor;
606
607 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
608 unsigned blend_cntl = 0;
609
610 sx_mrt_blend_opt[i] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
613
614 if (!state->rt[j].colormask)
615 continue;
616
617 /* cb_render_state will disable unused ones */
618 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
619
620 if (!state->rt[j].blend_enable) {
621 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 continue;
623 }
624
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
627 *
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
630 */
631 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
632 PIPE_BLENDFACTOR_DST_COLOR,
633 PIPE_BLENDFACTOR_SRC_COLOR);
634 si_blend_remove_dst(&eqA, &srcA, &dstA,
635 PIPE_BLENDFACTOR_DST_COLOR,
636 PIPE_BLENDFACTOR_SRC_COLOR);
637 si_blend_remove_dst(&eqA, &srcA, &dstA,
638 PIPE_BLENDFACTOR_DST_ALPHA,
639 PIPE_BLENDFACTOR_SRC_ALPHA);
640
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
643 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
644 srcA_opt = si_translate_blend_opt_factor(srcA, true);
645 dstA_opt = si_translate_blend_opt_factor(dstA, true);
646
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650 if (si_blend_factor_uses_dst(srcA))
651 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
652
653 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
654 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
656 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
657 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
658
659 /* Set the final value. */
660 sx_mrt_blend_opt[i] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt) |
665 S_028760_ALPHA_DST_OPT(dstA_opt) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
667
668 /* Set blend state. */
669 blend_cntl |= S_028780_ENABLE(1);
670 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
671 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
672 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
673
674 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
675 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
677 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
678 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
679 }
680 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
681
682 blend->blend_enable_4bit |= 0xf << (i * 4);
683
684 /* This is only important for formats without alpha. */
685 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
687 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
689 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
690 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
691 blend->need_src_alpha_4bit |= 0xf << (i * 4);
692 }
693
694 if (blend->cb_target_mask) {
695 color_control |= S_028808_MODE(mode);
696 } else {
697 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
698 }
699
700 if (sctx->b.family == CHIP_STONEY) {
701 for (int i = 0; i < 8; i++)
702 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
703 sx_mrt_blend_opt[i]);
704
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend->dual_src_blend || state->logicop_enable ||
707 mode == V_028808_CB_RESOLVE)
708 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
709 }
710
711 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
712 return blend;
713 }
714
715 static void *si_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
719 }
720
721 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
725 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
726 }
727
728 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
729 {
730 struct si_context *sctx = (struct si_context *)ctx;
731 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
732 }
733
734 static void si_set_blend_color(struct pipe_context *ctx,
735 const struct pipe_blend_color *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738
739 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->blend_color.state = *state;
743 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
744 }
745
746 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
747 {
748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
749
750 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
751 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
752 }
753
754 /*
755 * Clipping
756 */
757
758 static void si_set_clip_state(struct pipe_context *ctx,
759 const struct pipe_clip_state *state)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_constant_buffer cb;
763
764 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
765 return;
766
767 sctx->clip_state.state = *state;
768 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
769
770 cb.buffer = NULL;
771 cb.user_buffer = state->ucp;
772 cb.buffer_offset = 0;
773 cb.buffer_size = 4*4*8;
774 si_set_constant_buffer(sctx, &sctx->rw_buffers,
775 SI_VS_CONST_CLIP_PLANES, &cb);
776 pipe_resource_reference(&cb.buffer, NULL);
777 }
778
779 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
780 {
781 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
782
783 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
784 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
785 }
786
787 #define SIX_BITS 0x3F
788
789 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
790 {
791 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
792 struct tgsi_shader_info *info = si_get_vs_info(sctx);
793 unsigned window_space =
794 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
795 unsigned clipdist_mask =
796 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
797
798 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
799 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
800 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
801 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
802 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
803 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
804 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
805 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
806 info->writes_edgeflag ||
807 info->writes_layer ||
808 info->writes_viewport_index) |
809 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
810 (sctx->queued.named.rasterizer->clip_plane_enable &
811 clipdist_mask));
812 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
813 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
814 (clipdist_mask ? 0 :
815 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
816 S_028810_CLIP_DISABLE(window_space));
817
818 /* reuse needs to be set off if we write oViewport */
819 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
820 S_028AB4_REUSE_OFF(info->writes_viewport_index));
821 }
822
823 /*
824 * inferred state between framebuffer and rasterizer
825 */
826 static void si_update_poly_offset_state(struct si_context *sctx)
827 {
828 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
829
830 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
831 return;
832
833 switch (sctx->framebuffer.state.zsbuf->texture->format) {
834 case PIPE_FORMAT_Z16_UNORM:
835 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
836 break;
837 default: /* 24-bit */
838 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
839 break;
840 case PIPE_FORMAT_Z32_FLOAT:
841 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
842 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
843 break;
844 }
845 }
846
847 /*
848 * Rasterizer
849 */
850
851 static uint32_t si_translate_fill(uint32_t func)
852 {
853 switch(func) {
854 case PIPE_POLYGON_MODE_FILL:
855 return V_028814_X_DRAW_TRIANGLES;
856 case PIPE_POLYGON_MODE_LINE:
857 return V_028814_X_DRAW_LINES;
858 case PIPE_POLYGON_MODE_POINT:
859 return V_028814_X_DRAW_POINTS;
860 default:
861 assert(0);
862 return V_028814_X_DRAW_POINTS;
863 }
864 }
865
866 static void *si_create_rs_state(struct pipe_context *ctx,
867 const struct pipe_rasterizer_state *state)
868 {
869 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
870 struct si_pm4_state *pm4 = &rs->pm4;
871 unsigned tmp, i;
872 float psize_min, psize_max;
873
874 if (!rs) {
875 return NULL;
876 }
877
878 rs->scissor_enable = state->scissor;
879 rs->two_side = state->light_twoside;
880 rs->multisample_enable = state->multisample;
881 rs->force_persample_interp = state->force_persample_interp;
882 rs->clip_plane_enable = state->clip_plane_enable;
883 rs->line_stipple_enable = state->line_stipple_enable;
884 rs->poly_stipple_enable = state->poly_stipple_enable;
885 rs->line_smooth = state->line_smooth;
886 rs->poly_smooth = state->poly_smooth;
887 rs->uses_poly_offset = state->offset_point || state->offset_line ||
888 state->offset_tri;
889 rs->clamp_fragment_color = state->clamp_fragment_color;
890 rs->flatshade = state->flatshade;
891 rs->sprite_coord_enable = state->sprite_coord_enable;
892 rs->rasterizer_discard = state->rasterizer_discard;
893 rs->pa_sc_line_stipple = state->line_stipple_enable ?
894 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
895 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
896 rs->pa_cl_clip_cntl =
897 S_028810_PS_UCP_MODE(3) |
898 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
899 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
900 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
901 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
902 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
903
904 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
905 S_0286D4_FLAT_SHADE_ENA(1) |
906 S_0286D4_PNT_SPRITE_ENA(1) |
907 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
908 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
909 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
910 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
911 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
912
913 /* point size 12.4 fixed point */
914 tmp = (unsigned)(state->point_size * 8.0);
915 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
916
917 if (state->point_size_per_vertex) {
918 psize_min = util_get_min_point_size(state);
919 psize_max = 8192;
920 } else {
921 /* Force the point size to be as if the vertex output was disabled. */
922 psize_min = state->point_size;
923 psize_max = state->point_size;
924 }
925 /* Divide by two, because 0.5 = 1 pixel. */
926 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
927 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
928 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
929
930 tmp = (unsigned)state->line_width * 8;
931 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
932 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
933 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
934 S_028A48_MSAA_ENABLE(state->multisample ||
935 state->poly_smooth ||
936 state->line_smooth) |
937 S_028A48_VPORT_SCISSOR_ENABLE(1));
938
939 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
940 S_028BE4_PIX_CENTER(state->half_pixel_center) |
941 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
942
943 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
944 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
945 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
946 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
947 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
948 S_028814_FACE(!state->front_ccw) |
949 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
950 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
951 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
952 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
953 state->fill_back != PIPE_POLYGON_MODE_FILL) |
954 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
955 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
956 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
957 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
958
959 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
960 for (i = 0; i < 3; i++) {
961 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
962 float offset_units = state->offset_units;
963 float offset_scale = state->offset_scale * 16.0f;
964
965 switch (i) {
966 case 0: /* 16-bit zbuffer */
967 offset_units *= 4.0f;
968 break;
969 case 1: /* 24-bit zbuffer */
970 offset_units *= 2.0f;
971 break;
972 case 2: /* 32-bit zbuffer */
973 offset_units *= 1.0f;
974 break;
975 }
976
977 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
978 fui(offset_scale));
979 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
980 fui(offset_units));
981 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
982 fui(offset_scale));
983 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
984 fui(offset_units));
985 }
986
987 return rs;
988 }
989
990 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
991 {
992 struct si_context *sctx = (struct si_context *)ctx;
993 struct si_state_rasterizer *old_rs =
994 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
995 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
996
997 if (!state)
998 return;
999
1000 if (sctx->framebuffer.nr_samples > 1 &&
1001 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1002 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1003
1004 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
1005
1006 si_pm4_bind_state(sctx, rasterizer, rs);
1007 si_update_poly_offset_state(sctx);
1008
1009 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1010 }
1011
1012 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct si_context *sctx = (struct si_context *)ctx;
1015
1016 if (sctx->queued.named.rasterizer == state)
1017 si_pm4_bind_state(sctx, poly_offset, NULL);
1018 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1019 }
1020
1021 /*
1022 * infeered state between dsa and stencil ref
1023 */
1024 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1025 {
1026 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1027 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1028 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1029
1030 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1031 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1032 S_028430_STENCILMASK(dsa->valuemask[0]) |
1033 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1034 S_028430_STENCILOPVAL(1));
1035 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1036 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1037 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1038 S_028434_STENCILOPVAL_BF(1));
1039 }
1040
1041 static void si_set_stencil_ref(struct pipe_context *ctx,
1042 const struct pipe_stencil_ref *state)
1043 {
1044 struct si_context *sctx = (struct si_context *)ctx;
1045
1046 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1047 return;
1048
1049 sctx->stencil_ref.state = *state;
1050 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1051 }
1052
1053
1054 /*
1055 * DSA
1056 */
1057
1058 static uint32_t si_translate_stencil_op(int s_op)
1059 {
1060 switch (s_op) {
1061 case PIPE_STENCIL_OP_KEEP:
1062 return V_02842C_STENCIL_KEEP;
1063 case PIPE_STENCIL_OP_ZERO:
1064 return V_02842C_STENCIL_ZERO;
1065 case PIPE_STENCIL_OP_REPLACE:
1066 return V_02842C_STENCIL_REPLACE_TEST;
1067 case PIPE_STENCIL_OP_INCR:
1068 return V_02842C_STENCIL_ADD_CLAMP;
1069 case PIPE_STENCIL_OP_DECR:
1070 return V_02842C_STENCIL_SUB_CLAMP;
1071 case PIPE_STENCIL_OP_INCR_WRAP:
1072 return V_02842C_STENCIL_ADD_WRAP;
1073 case PIPE_STENCIL_OP_DECR_WRAP:
1074 return V_02842C_STENCIL_SUB_WRAP;
1075 case PIPE_STENCIL_OP_INVERT:
1076 return V_02842C_STENCIL_INVERT;
1077 default:
1078 R600_ERR("Unknown stencil op %d", s_op);
1079 assert(0);
1080 break;
1081 }
1082 return 0;
1083 }
1084
1085 static void *si_create_dsa_state(struct pipe_context *ctx,
1086 const struct pipe_depth_stencil_alpha_state *state)
1087 {
1088 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1089 struct si_pm4_state *pm4 = &dsa->pm4;
1090 unsigned db_depth_control;
1091 uint32_t db_stencil_control = 0;
1092
1093 if (!dsa) {
1094 return NULL;
1095 }
1096
1097 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1098 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1099 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1100 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1101
1102 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1103 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1104 S_028800_ZFUNC(state->depth.func) |
1105 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1106
1107 /* stencil */
1108 if (state->stencil[0].enabled) {
1109 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1110 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1111 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1112 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1113 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1114
1115 if (state->stencil[1].enabled) {
1116 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1117 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1118 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1119 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1120 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1121 }
1122 }
1123
1124 /* alpha */
1125 if (state->alpha.enabled) {
1126 dsa->alpha_func = state->alpha.func;
1127
1128 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1129 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1130 } else {
1131 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1132 }
1133
1134 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1135 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1136 if (state->depth.bounds_test) {
1137 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1138 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1139 }
1140
1141 return dsa;
1142 }
1143
1144 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1145 {
1146 struct si_context *sctx = (struct si_context *)ctx;
1147 struct si_state_dsa *dsa = state;
1148
1149 if (!state)
1150 return;
1151
1152 si_pm4_bind_state(sctx, dsa, dsa);
1153
1154 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1155 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1156 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1157 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1158 }
1159 }
1160
1161 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1162 {
1163 struct si_context *sctx = (struct si_context *)ctx;
1164 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1165 }
1166
1167 static void *si_create_db_flush_dsa(struct si_context *sctx)
1168 {
1169 struct pipe_depth_stencil_alpha_state dsa = {};
1170
1171 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1172 }
1173
1174 /* DB RENDER STATE */
1175
1176 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1177 {
1178 struct si_context *sctx = (struct si_context*)ctx;
1179
1180 /* Pipeline stat & streamout queries. */
1181 if (enable) {
1182 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1183 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1184 } else {
1185 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1186 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1187 }
1188
1189 /* Occlusion queries. */
1190 if (sctx->occlusion_queries_disabled != !enable) {
1191 sctx->occlusion_queries_disabled = !enable;
1192 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1193 }
1194 }
1195
1196 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1197 {
1198 struct si_context *sctx = (struct si_context*)ctx;
1199
1200 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1201 }
1202
1203 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1204 {
1205 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1206 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1207 unsigned db_shader_control;
1208
1209 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1210
1211 /* DB_RENDER_CONTROL */
1212 if (sctx->dbcb_depth_copy_enabled ||
1213 sctx->dbcb_stencil_copy_enabled) {
1214 radeon_emit(cs,
1215 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1216 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1217 S_028000_COPY_CENTROID(1) |
1218 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1219 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1220 radeon_emit(cs,
1221 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1222 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1223 } else {
1224 radeon_emit(cs,
1225 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1226 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1227 }
1228
1229 /* DB_COUNT_CONTROL (occlusion queries) */
1230 if (sctx->b.num_occlusion_queries > 0 &&
1231 !sctx->occlusion_queries_disabled) {
1232 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1233
1234 if (sctx->b.chip_class >= CIK) {
1235 radeon_emit(cs,
1236 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1237 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1238 S_028004_ZPASS_ENABLE(1) |
1239 S_028004_SLICE_EVEN_ENABLE(1) |
1240 S_028004_SLICE_ODD_ENABLE(1));
1241 } else {
1242 radeon_emit(cs,
1243 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1244 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1245 }
1246 } else {
1247 /* Disable occlusion queries. */
1248 if (sctx->b.chip_class >= CIK) {
1249 radeon_emit(cs, 0);
1250 } else {
1251 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1252 }
1253 }
1254
1255 /* DB_RENDER_OVERRIDE2 */
1256 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1257 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1258 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1259
1260 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1261 sctx->ps_db_shader_control;
1262
1263 /* Bug workaround for smoothing (overrasterization) on SI. */
1264 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1265 db_shader_control &= C_02880C_Z_ORDER;
1266 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1267 }
1268
1269 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1270 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1271 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1272
1273 if (sctx->b.family == CHIP_STONEY &&
1274 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1275 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1276
1277 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1278 db_shader_control);
1279 }
1280
1281 /*
1282 * format translation
1283 */
1284 static uint32_t si_translate_colorformat(enum pipe_format format)
1285 {
1286 const struct util_format_description *desc = util_format_description(format);
1287
1288 #define HAS_SIZE(x,y,z,w) \
1289 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1290 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1291
1292 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1293 return V_028C70_COLOR_10_11_11;
1294
1295 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1296 return V_028C70_COLOR_INVALID;
1297
1298 switch (desc->nr_channels) {
1299 case 1:
1300 switch (desc->channel[0].size) {
1301 case 8:
1302 return V_028C70_COLOR_8;
1303 case 16:
1304 return V_028C70_COLOR_16;
1305 case 32:
1306 return V_028C70_COLOR_32;
1307 }
1308 break;
1309 case 2:
1310 if (desc->channel[0].size == desc->channel[1].size) {
1311 switch (desc->channel[0].size) {
1312 case 8:
1313 return V_028C70_COLOR_8_8;
1314 case 16:
1315 return V_028C70_COLOR_16_16;
1316 case 32:
1317 return V_028C70_COLOR_32_32;
1318 }
1319 } else if (HAS_SIZE(8,24,0,0)) {
1320 return V_028C70_COLOR_24_8;
1321 } else if (HAS_SIZE(24,8,0,0)) {
1322 return V_028C70_COLOR_8_24;
1323 }
1324 break;
1325 case 3:
1326 if (HAS_SIZE(5,6,5,0)) {
1327 return V_028C70_COLOR_5_6_5;
1328 } else if (HAS_SIZE(32,8,24,0)) {
1329 return V_028C70_COLOR_X24_8_32_FLOAT;
1330 }
1331 break;
1332 case 4:
1333 if (desc->channel[0].size == desc->channel[1].size &&
1334 desc->channel[0].size == desc->channel[2].size &&
1335 desc->channel[0].size == desc->channel[3].size) {
1336 switch (desc->channel[0].size) {
1337 case 4:
1338 return V_028C70_COLOR_4_4_4_4;
1339 case 8:
1340 return V_028C70_COLOR_8_8_8_8;
1341 case 16:
1342 return V_028C70_COLOR_16_16_16_16;
1343 case 32:
1344 return V_028C70_COLOR_32_32_32_32;
1345 }
1346 } else if (HAS_SIZE(5,5,5,1)) {
1347 return V_028C70_COLOR_1_5_5_5;
1348 } else if (HAS_SIZE(10,10,10,2)) {
1349 return V_028C70_COLOR_2_10_10_10;
1350 }
1351 break;
1352 }
1353 return V_028C70_COLOR_INVALID;
1354 }
1355
1356 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1357 {
1358 if (SI_BIG_ENDIAN) {
1359 switch(colorformat) {
1360 /* 8-bit buffers. */
1361 case V_028C70_COLOR_8:
1362 return V_028C70_ENDIAN_NONE;
1363
1364 /* 16-bit buffers. */
1365 case V_028C70_COLOR_5_6_5:
1366 case V_028C70_COLOR_1_5_5_5:
1367 case V_028C70_COLOR_4_4_4_4:
1368 case V_028C70_COLOR_16:
1369 case V_028C70_COLOR_8_8:
1370 return V_028C70_ENDIAN_8IN16;
1371
1372 /* 32-bit buffers. */
1373 case V_028C70_COLOR_8_8_8_8:
1374 case V_028C70_COLOR_2_10_10_10:
1375 case V_028C70_COLOR_8_24:
1376 case V_028C70_COLOR_24_8:
1377 case V_028C70_COLOR_16_16:
1378 return V_028C70_ENDIAN_8IN32;
1379
1380 /* 64-bit buffers. */
1381 case V_028C70_COLOR_16_16_16_16:
1382 return V_028C70_ENDIAN_8IN16;
1383
1384 case V_028C70_COLOR_32_32:
1385 return V_028C70_ENDIAN_8IN32;
1386
1387 /* 128-bit buffers. */
1388 case V_028C70_COLOR_32_32_32_32:
1389 return V_028C70_ENDIAN_8IN32;
1390 default:
1391 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1392 }
1393 } else {
1394 return V_028C70_ENDIAN_NONE;
1395 }
1396 }
1397
1398 static uint32_t si_translate_dbformat(enum pipe_format format)
1399 {
1400 switch (format) {
1401 case PIPE_FORMAT_Z16_UNORM:
1402 return V_028040_Z_16;
1403 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1404 case PIPE_FORMAT_X8Z24_UNORM:
1405 case PIPE_FORMAT_Z24X8_UNORM:
1406 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1407 return V_028040_Z_24; /* deprecated on SI */
1408 case PIPE_FORMAT_Z32_FLOAT:
1409 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1410 return V_028040_Z_32_FLOAT;
1411 default:
1412 return V_028040_Z_INVALID;
1413 }
1414 }
1415
1416 /*
1417 * Texture translation
1418 */
1419
1420 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1421 enum pipe_format format,
1422 const struct util_format_description *desc,
1423 int first_non_void)
1424 {
1425 struct si_screen *sscreen = (struct si_screen*)screen;
1426 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1427 sscreen->b.info.drm_minor >= 31) ||
1428 sscreen->b.info.drm_major == 3;
1429 boolean uniform = TRUE;
1430 int i;
1431
1432 /* Colorspace (return non-RGB formats directly). */
1433 switch (desc->colorspace) {
1434 /* Depth stencil formats */
1435 case UTIL_FORMAT_COLORSPACE_ZS:
1436 switch (format) {
1437 case PIPE_FORMAT_Z16_UNORM:
1438 return V_008F14_IMG_DATA_FORMAT_16;
1439 case PIPE_FORMAT_X24S8_UINT:
1440 case PIPE_FORMAT_Z24X8_UNORM:
1441 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1442 return V_008F14_IMG_DATA_FORMAT_8_24;
1443 case PIPE_FORMAT_X8Z24_UNORM:
1444 case PIPE_FORMAT_S8X24_UINT:
1445 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1446 return V_008F14_IMG_DATA_FORMAT_24_8;
1447 case PIPE_FORMAT_S8_UINT:
1448 return V_008F14_IMG_DATA_FORMAT_8;
1449 case PIPE_FORMAT_Z32_FLOAT:
1450 return V_008F14_IMG_DATA_FORMAT_32;
1451 case PIPE_FORMAT_X32_S8X24_UINT:
1452 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1453 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1454 default:
1455 goto out_unknown;
1456 }
1457
1458 case UTIL_FORMAT_COLORSPACE_YUV:
1459 goto out_unknown; /* TODO */
1460
1461 case UTIL_FORMAT_COLORSPACE_SRGB:
1462 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1463 goto out_unknown;
1464 break;
1465
1466 default:
1467 break;
1468 }
1469
1470 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1471 if (!enable_compressed_formats)
1472 goto out_unknown;
1473
1474 switch (format) {
1475 case PIPE_FORMAT_RGTC1_SNORM:
1476 case PIPE_FORMAT_LATC1_SNORM:
1477 case PIPE_FORMAT_RGTC1_UNORM:
1478 case PIPE_FORMAT_LATC1_UNORM:
1479 return V_008F14_IMG_DATA_FORMAT_BC4;
1480 case PIPE_FORMAT_RGTC2_SNORM:
1481 case PIPE_FORMAT_LATC2_SNORM:
1482 case PIPE_FORMAT_RGTC2_UNORM:
1483 case PIPE_FORMAT_LATC2_UNORM:
1484 return V_008F14_IMG_DATA_FORMAT_BC5;
1485 default:
1486 goto out_unknown;
1487 }
1488 }
1489
1490 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1491 sscreen->b.family == CHIP_STONEY) {
1492 switch (format) {
1493 case PIPE_FORMAT_ETC1_RGB8:
1494 case PIPE_FORMAT_ETC2_RGB8:
1495 case PIPE_FORMAT_ETC2_SRGB8:
1496 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1497 case PIPE_FORMAT_ETC2_RGB8A1:
1498 case PIPE_FORMAT_ETC2_SRGB8A1:
1499 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1500 case PIPE_FORMAT_ETC2_RGBA8:
1501 case PIPE_FORMAT_ETC2_SRGBA8:
1502 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1503 case PIPE_FORMAT_ETC2_R11_UNORM:
1504 case PIPE_FORMAT_ETC2_R11_SNORM:
1505 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1506 case PIPE_FORMAT_ETC2_RG11_UNORM:
1507 case PIPE_FORMAT_ETC2_RG11_SNORM:
1508 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1509 default:
1510 goto out_unknown;
1511 }
1512 }
1513
1514 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1515 if (!enable_compressed_formats)
1516 goto out_unknown;
1517
1518 switch (format) {
1519 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1520 case PIPE_FORMAT_BPTC_SRGBA:
1521 return V_008F14_IMG_DATA_FORMAT_BC7;
1522 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1523 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1524 return V_008F14_IMG_DATA_FORMAT_BC6;
1525 default:
1526 goto out_unknown;
1527 }
1528 }
1529
1530 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1531 switch (format) {
1532 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1533 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1534 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1535 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1536 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1537 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1538 default:
1539 goto out_unknown;
1540 }
1541 }
1542
1543 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1544 if (!enable_compressed_formats)
1545 goto out_unknown;
1546
1547 if (!util_format_s3tc_enabled) {
1548 goto out_unknown;
1549 }
1550
1551 switch (format) {
1552 case PIPE_FORMAT_DXT1_RGB:
1553 case PIPE_FORMAT_DXT1_RGBA:
1554 case PIPE_FORMAT_DXT1_SRGB:
1555 case PIPE_FORMAT_DXT1_SRGBA:
1556 return V_008F14_IMG_DATA_FORMAT_BC1;
1557 case PIPE_FORMAT_DXT3_RGBA:
1558 case PIPE_FORMAT_DXT3_SRGBA:
1559 return V_008F14_IMG_DATA_FORMAT_BC2;
1560 case PIPE_FORMAT_DXT5_RGBA:
1561 case PIPE_FORMAT_DXT5_SRGBA:
1562 return V_008F14_IMG_DATA_FORMAT_BC3;
1563 default:
1564 goto out_unknown;
1565 }
1566 }
1567
1568 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1569 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1570 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1571 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1572 }
1573
1574 /* R8G8Bx_SNORM - TODO CxV8U8 */
1575
1576 /* See whether the components are of the same size. */
1577 for (i = 1; i < desc->nr_channels; i++) {
1578 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1579 }
1580
1581 /* Non-uniform formats. */
1582 if (!uniform) {
1583 switch(desc->nr_channels) {
1584 case 3:
1585 if (desc->channel[0].size == 5 &&
1586 desc->channel[1].size == 6 &&
1587 desc->channel[2].size == 5) {
1588 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1589 }
1590 goto out_unknown;
1591 case 4:
1592 if (desc->channel[0].size == 5 &&
1593 desc->channel[1].size == 5 &&
1594 desc->channel[2].size == 5 &&
1595 desc->channel[3].size == 1) {
1596 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1597 }
1598 if (desc->channel[0].size == 10 &&
1599 desc->channel[1].size == 10 &&
1600 desc->channel[2].size == 10 &&
1601 desc->channel[3].size == 2) {
1602 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1603 }
1604 goto out_unknown;
1605 }
1606 goto out_unknown;
1607 }
1608
1609 if (first_non_void < 0 || first_non_void > 3)
1610 goto out_unknown;
1611
1612 /* uniform formats */
1613 switch (desc->channel[first_non_void].size) {
1614 case 4:
1615 switch (desc->nr_channels) {
1616 #if 0 /* Not supported for render targets */
1617 case 2:
1618 return V_008F14_IMG_DATA_FORMAT_4_4;
1619 #endif
1620 case 4:
1621 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1622 }
1623 break;
1624 case 8:
1625 switch (desc->nr_channels) {
1626 case 1:
1627 return V_008F14_IMG_DATA_FORMAT_8;
1628 case 2:
1629 return V_008F14_IMG_DATA_FORMAT_8_8;
1630 case 4:
1631 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1632 }
1633 break;
1634 case 16:
1635 switch (desc->nr_channels) {
1636 case 1:
1637 return V_008F14_IMG_DATA_FORMAT_16;
1638 case 2:
1639 return V_008F14_IMG_DATA_FORMAT_16_16;
1640 case 4:
1641 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1642 }
1643 break;
1644 case 32:
1645 switch (desc->nr_channels) {
1646 case 1:
1647 return V_008F14_IMG_DATA_FORMAT_32;
1648 case 2:
1649 return V_008F14_IMG_DATA_FORMAT_32_32;
1650 #if 0 /* Not supported for render targets */
1651 case 3:
1652 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1653 #endif
1654 case 4:
1655 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1656 }
1657 }
1658
1659 out_unknown:
1660 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1661 return ~0;
1662 }
1663
1664 static unsigned si_tex_wrap(unsigned wrap)
1665 {
1666 switch (wrap) {
1667 default:
1668 case PIPE_TEX_WRAP_REPEAT:
1669 return V_008F30_SQ_TEX_WRAP;
1670 case PIPE_TEX_WRAP_CLAMP:
1671 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1672 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1673 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1674 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1675 return V_008F30_SQ_TEX_CLAMP_BORDER;
1676 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1677 return V_008F30_SQ_TEX_MIRROR;
1678 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1679 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1680 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1681 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1682 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1683 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1684 }
1685 }
1686
1687 static unsigned si_tex_mipfilter(unsigned filter)
1688 {
1689 switch (filter) {
1690 case PIPE_TEX_MIPFILTER_NEAREST:
1691 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1692 case PIPE_TEX_MIPFILTER_LINEAR:
1693 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1694 default:
1695 case PIPE_TEX_MIPFILTER_NONE:
1696 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1697 }
1698 }
1699
1700 static unsigned si_tex_compare(unsigned compare)
1701 {
1702 switch (compare) {
1703 default:
1704 case PIPE_FUNC_NEVER:
1705 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1706 case PIPE_FUNC_LESS:
1707 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1708 case PIPE_FUNC_EQUAL:
1709 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1710 case PIPE_FUNC_LEQUAL:
1711 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1712 case PIPE_FUNC_GREATER:
1713 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1714 case PIPE_FUNC_NOTEQUAL:
1715 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1716 case PIPE_FUNC_GEQUAL:
1717 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1718 case PIPE_FUNC_ALWAYS:
1719 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1720 }
1721 }
1722
1723 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1724 unsigned nr_samples)
1725 {
1726 if (view_target == PIPE_TEXTURE_CUBE ||
1727 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1728 res_target = view_target;
1729
1730 switch (res_target) {
1731 default:
1732 case PIPE_TEXTURE_1D:
1733 return V_008F1C_SQ_RSRC_IMG_1D;
1734 case PIPE_TEXTURE_1D_ARRAY:
1735 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1736 case PIPE_TEXTURE_2D:
1737 case PIPE_TEXTURE_RECT:
1738 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1739 V_008F1C_SQ_RSRC_IMG_2D;
1740 case PIPE_TEXTURE_2D_ARRAY:
1741 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1742 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1743 case PIPE_TEXTURE_3D:
1744 return V_008F1C_SQ_RSRC_IMG_3D;
1745 case PIPE_TEXTURE_CUBE:
1746 case PIPE_TEXTURE_CUBE_ARRAY:
1747 return V_008F1C_SQ_RSRC_IMG_CUBE;
1748 }
1749 }
1750
1751 /*
1752 * Format support testing
1753 */
1754
1755 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1756 {
1757 return si_translate_texformat(screen, format, util_format_description(format),
1758 util_format_get_first_non_void_channel(format)) != ~0U;
1759 }
1760
1761 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1762 const struct util_format_description *desc,
1763 int first_non_void)
1764 {
1765 unsigned type = desc->channel[first_non_void].type;
1766 int i;
1767
1768 if (type == UTIL_FORMAT_TYPE_FIXED)
1769 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1770
1771 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1772 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1773
1774 if (desc->nr_channels == 4 &&
1775 desc->channel[0].size == 10 &&
1776 desc->channel[1].size == 10 &&
1777 desc->channel[2].size == 10 &&
1778 desc->channel[3].size == 2)
1779 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1780
1781 /* See whether the components are of the same size. */
1782 for (i = 0; i < desc->nr_channels; i++) {
1783 if (desc->channel[first_non_void].size != desc->channel[i].size)
1784 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1785 }
1786
1787 switch (desc->channel[first_non_void].size) {
1788 case 8:
1789 switch (desc->nr_channels) {
1790 case 1:
1791 return V_008F0C_BUF_DATA_FORMAT_8;
1792 case 2:
1793 return V_008F0C_BUF_DATA_FORMAT_8_8;
1794 case 3:
1795 case 4:
1796 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1797 }
1798 break;
1799 case 16:
1800 switch (desc->nr_channels) {
1801 case 1:
1802 return V_008F0C_BUF_DATA_FORMAT_16;
1803 case 2:
1804 return V_008F0C_BUF_DATA_FORMAT_16_16;
1805 case 3:
1806 case 4:
1807 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1808 }
1809 break;
1810 case 32:
1811 /* From the Southern Islands ISA documentation about MTBUF:
1812 * 'Memory reads of data in memory that is 32 or 64 bits do not
1813 * undergo any format conversion.'
1814 */
1815 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1816 !desc->channel[first_non_void].pure_integer)
1817 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1818
1819 switch (desc->nr_channels) {
1820 case 1:
1821 return V_008F0C_BUF_DATA_FORMAT_32;
1822 case 2:
1823 return V_008F0C_BUF_DATA_FORMAT_32_32;
1824 case 3:
1825 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1826 case 4:
1827 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1828 }
1829 break;
1830 }
1831
1832 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1833 }
1834
1835 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1836 const struct util_format_description *desc,
1837 int first_non_void)
1838 {
1839 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1840 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1841
1842 switch (desc->channel[first_non_void].type) {
1843 case UTIL_FORMAT_TYPE_SIGNED:
1844 if (desc->channel[first_non_void].normalized)
1845 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1846 else if (desc->channel[first_non_void].pure_integer)
1847 return V_008F0C_BUF_NUM_FORMAT_SINT;
1848 else
1849 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1850 break;
1851 case UTIL_FORMAT_TYPE_UNSIGNED:
1852 if (desc->channel[first_non_void].normalized)
1853 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1854 else if (desc->channel[first_non_void].pure_integer)
1855 return V_008F0C_BUF_NUM_FORMAT_UINT;
1856 else
1857 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1858 break;
1859 case UTIL_FORMAT_TYPE_FLOAT:
1860 default:
1861 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1862 }
1863 }
1864
1865 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1866 {
1867 const struct util_format_description *desc;
1868 int first_non_void;
1869 unsigned data_format;
1870
1871 desc = util_format_description(format);
1872 first_non_void = util_format_get_first_non_void_channel(format);
1873 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1874 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1875 }
1876
1877 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1878 {
1879 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1880 r600_translate_colorswap(format) != ~0U;
1881 }
1882
1883 static bool si_is_zs_format_supported(enum pipe_format format)
1884 {
1885 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1886 }
1887
1888 boolean si_is_format_supported(struct pipe_screen *screen,
1889 enum pipe_format format,
1890 enum pipe_texture_target target,
1891 unsigned sample_count,
1892 unsigned usage)
1893 {
1894 unsigned retval = 0;
1895
1896 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1897 R600_ERR("r600: unsupported texture type %d\n", target);
1898 return FALSE;
1899 }
1900
1901 if (!util_format_is_supported(format, usage))
1902 return FALSE;
1903
1904 if (sample_count > 1) {
1905 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1906 return FALSE;
1907
1908 switch (sample_count) {
1909 case 2:
1910 case 4:
1911 case 8:
1912 break;
1913 case 16:
1914 if (format == PIPE_FORMAT_NONE)
1915 return TRUE;
1916 else
1917 return FALSE;
1918 default:
1919 return FALSE;
1920 }
1921 }
1922
1923 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1924 if (target == PIPE_BUFFER) {
1925 if (si_is_vertex_format_supported(screen, format))
1926 retval |= PIPE_BIND_SAMPLER_VIEW;
1927 } else {
1928 if (si_is_sampler_format_supported(screen, format))
1929 retval |= PIPE_BIND_SAMPLER_VIEW;
1930 }
1931 }
1932
1933 if ((usage & (PIPE_BIND_RENDER_TARGET |
1934 PIPE_BIND_DISPLAY_TARGET |
1935 PIPE_BIND_SCANOUT |
1936 PIPE_BIND_SHARED |
1937 PIPE_BIND_BLENDABLE)) &&
1938 si_is_colorbuffer_format_supported(format)) {
1939 retval |= usage &
1940 (PIPE_BIND_RENDER_TARGET |
1941 PIPE_BIND_DISPLAY_TARGET |
1942 PIPE_BIND_SCANOUT |
1943 PIPE_BIND_SHARED);
1944 if (!util_format_is_pure_integer(format) &&
1945 !util_format_is_depth_or_stencil(format))
1946 retval |= usage & PIPE_BIND_BLENDABLE;
1947 }
1948
1949 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1950 si_is_zs_format_supported(format)) {
1951 retval |= PIPE_BIND_DEPTH_STENCIL;
1952 }
1953
1954 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1955 si_is_vertex_format_supported(screen, format)) {
1956 retval |= PIPE_BIND_VERTEX_BUFFER;
1957 }
1958
1959 if (usage & PIPE_BIND_TRANSFER_READ)
1960 retval |= PIPE_BIND_TRANSFER_READ;
1961 if (usage & PIPE_BIND_TRANSFER_WRITE)
1962 retval |= PIPE_BIND_TRANSFER_WRITE;
1963
1964 if ((usage & PIPE_BIND_LINEAR) &&
1965 !util_format_is_compressed(format) &&
1966 !(usage & PIPE_BIND_DEPTH_STENCIL))
1967 retval |= PIPE_BIND_LINEAR;
1968
1969 return retval == usage;
1970 }
1971
1972 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1973 {
1974 unsigned tile_mode_index = 0;
1975
1976 if (stencil) {
1977 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1978 } else {
1979 tile_mode_index = rtex->surface.tiling_index[level];
1980 }
1981 return tile_mode_index;
1982 }
1983
1984 /*
1985 * framebuffer handling
1986 */
1987
1988 static void si_choose_spi_color_formats(struct r600_surface *surf,
1989 unsigned format, unsigned swap,
1990 unsigned ntype, bool is_depth)
1991 {
1992 /* Alpha is needed for alpha-to-coverage.
1993 * Blending may be with or without alpha.
1994 */
1995 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1996 unsigned alpha = 0; /* exports alpha, but may not support blending */
1997 unsigned blend = 0; /* supports blending, but may not export alpha */
1998 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1999
2000 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2001 * Other chips have multiple choices, though they are not necessarily better.
2002 */
2003 switch (format) {
2004 case V_028C70_COLOR_5_6_5:
2005 case V_028C70_COLOR_1_5_5_5:
2006 case V_028C70_COLOR_5_5_5_1:
2007 case V_028C70_COLOR_4_4_4_4:
2008 case V_028C70_COLOR_10_11_11:
2009 case V_028C70_COLOR_11_11_10:
2010 case V_028C70_COLOR_8:
2011 case V_028C70_COLOR_8_8:
2012 case V_028C70_COLOR_8_8_8_8:
2013 case V_028C70_COLOR_10_10_10_2:
2014 case V_028C70_COLOR_2_10_10_10:
2015 if (ntype == V_028C70_NUMBER_UINT)
2016 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2017 else if (ntype == V_028C70_NUMBER_SINT)
2018 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2019 else
2020 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2021 break;
2022
2023 case V_028C70_COLOR_16:
2024 case V_028C70_COLOR_16_16:
2025 case V_028C70_COLOR_16_16_16_16:
2026 if (ntype == V_028C70_NUMBER_UNORM ||
2027 ntype == V_028C70_NUMBER_SNORM) {
2028 /* UNORM16 and SNORM16 don't support blending */
2029 if (ntype == V_028C70_NUMBER_UNORM)
2030 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2031 else
2032 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2033
2034 /* Use 32 bits per channel for blending. */
2035 if (format == V_028C70_COLOR_16) {
2036 if (swap == V_028C70_SWAP_STD) { /* R */
2037 blend = V_028714_SPI_SHADER_32_R;
2038 blend_alpha = V_028714_SPI_SHADER_32_AR;
2039 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2040 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2041 else
2042 assert(0);
2043 } else if (format == V_028C70_COLOR_16_16) {
2044 if (swap == V_028C70_SWAP_STD) { /* RG */
2045 blend = V_028714_SPI_SHADER_32_GR;
2046 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2047 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2048 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2049 else
2050 assert(0);
2051 } else /* 16_16_16_16 */
2052 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2053 } else if (ntype == V_028C70_NUMBER_UINT)
2054 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2055 else if (ntype == V_028C70_NUMBER_SINT)
2056 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2057 else if (ntype == V_028C70_NUMBER_FLOAT)
2058 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2059 else
2060 assert(0);
2061 break;
2062
2063 case V_028C70_COLOR_32:
2064 if (swap == V_028C70_SWAP_STD) { /* R */
2065 blend = normal = V_028714_SPI_SHADER_32_R;
2066 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2067 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2068 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2069 else
2070 assert(0);
2071 break;
2072
2073 case V_028C70_COLOR_32_32:
2074 if (swap == V_028C70_SWAP_STD) { /* RG */
2075 blend = normal = V_028714_SPI_SHADER_32_GR;
2076 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2077 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2078 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2079 else
2080 assert(0);
2081 break;
2082
2083 case V_028C70_COLOR_32_32_32_32:
2084 case V_028C70_COLOR_8_24:
2085 case V_028C70_COLOR_24_8:
2086 case V_028C70_COLOR_X24_8_32_FLOAT:
2087 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2088 break;
2089
2090 default:
2091 assert(0);
2092 return;
2093 }
2094
2095 /* The DB->CB copy needs 32_ABGR. */
2096 if (is_depth)
2097 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2098
2099 surf->spi_shader_col_format = normal;
2100 surf->spi_shader_col_format_alpha = alpha;
2101 surf->spi_shader_col_format_blend = blend;
2102 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2103 }
2104
2105 static void si_initialize_color_surface(struct si_context *sctx,
2106 struct r600_surface *surf)
2107 {
2108 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2109 unsigned level = surf->base.u.tex.level;
2110 uint64_t offset = rtex->surface.level[level].offset;
2111 unsigned pitch, slice;
2112 unsigned color_info, color_attrib, color_pitch, color_view;
2113 unsigned tile_mode_index;
2114 unsigned format, swap, ntype, endian;
2115 const struct util_format_description *desc;
2116 int i;
2117 unsigned blend_clamp = 0, blend_bypass = 0;
2118
2119 /* Layered rendering doesn't work with LINEAR_GENERAL.
2120 * (LINEAR_ALIGNED and others work) */
2121 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2122 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2123 offset += rtex->surface.level[level].slice_size *
2124 surf->base.u.tex.first_layer;
2125 color_view = 0;
2126 } else {
2127 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2128 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2129 }
2130
2131 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2132 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2133 if (slice) {
2134 slice = slice - 1;
2135 }
2136
2137 tile_mode_index = si_tile_mode_index(rtex, level, false);
2138
2139 desc = util_format_description(surf->base.format);
2140 for (i = 0; i < 4; i++) {
2141 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2142 break;
2143 }
2144 }
2145 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2146 ntype = V_028C70_NUMBER_FLOAT;
2147 } else {
2148 ntype = V_028C70_NUMBER_UNORM;
2149 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2150 ntype = V_028C70_NUMBER_SRGB;
2151 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2152 if (desc->channel[i].pure_integer) {
2153 ntype = V_028C70_NUMBER_SINT;
2154 } else {
2155 assert(desc->channel[i].normalized);
2156 ntype = V_028C70_NUMBER_SNORM;
2157 }
2158 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2159 if (desc->channel[i].pure_integer) {
2160 ntype = V_028C70_NUMBER_UINT;
2161 } else {
2162 assert(desc->channel[i].normalized);
2163 ntype = V_028C70_NUMBER_UNORM;
2164 }
2165 }
2166 }
2167
2168 format = si_translate_colorformat(surf->base.format);
2169 if (format == V_028C70_COLOR_INVALID) {
2170 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2171 }
2172 assert(format != V_028C70_COLOR_INVALID);
2173 swap = r600_translate_colorswap(surf->base.format);
2174 endian = si_colorformat_endian_swap(format);
2175
2176 /* blend clamp should be set for all NORM/SRGB types */
2177 if (ntype == V_028C70_NUMBER_UNORM ||
2178 ntype == V_028C70_NUMBER_SNORM ||
2179 ntype == V_028C70_NUMBER_SRGB)
2180 blend_clamp = 1;
2181
2182 /* set blend bypass according to docs if SINT/UINT or
2183 8/24 COLOR variants */
2184 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2185 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2186 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2187 blend_clamp = 0;
2188 blend_bypass = 1;
2189 }
2190
2191 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2192 (format == V_028C70_COLOR_8 ||
2193 format == V_028C70_COLOR_8_8 ||
2194 format == V_028C70_COLOR_8_8_8_8))
2195 surf->color_is_int8 = true;
2196
2197 color_info = S_028C70_FORMAT(format) |
2198 S_028C70_COMP_SWAP(swap) |
2199 S_028C70_BLEND_CLAMP(blend_clamp) |
2200 S_028C70_BLEND_BYPASS(blend_bypass) |
2201 S_028C70_NUMBER_TYPE(ntype) |
2202 S_028C70_ENDIAN(endian);
2203
2204 color_pitch = S_028C64_TILE_MAX(pitch);
2205
2206 /* Intensity is implemented as Red, so treat it that way. */
2207 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2208 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1 ||
2209 util_format_is_intensity(surf->base.format));
2210
2211 if (rtex->resource.b.b.nr_samples > 1) {
2212 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2213
2214 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2215 S_028C74_NUM_FRAGMENTS(log_samples);
2216
2217 if (rtex->fmask.size) {
2218 color_info |= S_028C70_COMPRESSION(1);
2219 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2220
2221 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2222
2223 if (sctx->b.chip_class == SI) {
2224 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2225 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2226 }
2227 if (sctx->b.chip_class >= CIK) {
2228 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2229 }
2230 }
2231 }
2232
2233 offset += rtex->resource.gpu_address;
2234
2235 surf->cb_color_base = offset >> 8;
2236 surf->cb_color_pitch = color_pitch;
2237 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2238 surf->cb_color_view = color_view;
2239 surf->cb_color_info = color_info;
2240 surf->cb_color_attrib = color_attrib;
2241
2242 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2243 unsigned max_uncompressed_block_size = 2;
2244
2245 if (rtex->surface.nsamples > 1) {
2246 if (rtex->surface.bpe == 1)
2247 max_uncompressed_block_size = 0;
2248 else if (rtex->surface.bpe == 2)
2249 max_uncompressed_block_size = 1;
2250 }
2251
2252 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2253 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2254 surf->cb_dcc_base = (rtex->resource.gpu_address +
2255 rtex->dcc_offset +
2256 rtex->surface.level[level].dcc_offset) >> 8;
2257 }
2258
2259 if (rtex->fmask.size) {
2260 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2261 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2262 } else {
2263 /* This must be set for fast clear to work without FMASK. */
2264 surf->cb_color_fmask = surf->cb_color_base;
2265 surf->cb_color_fmask_slice = surf->cb_color_slice;
2266 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2267
2268 if (sctx->b.chip_class == SI) {
2269 unsigned bankh = util_logbase2(rtex->surface.bankh);
2270 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2271 }
2272
2273 if (sctx->b.chip_class >= CIK) {
2274 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2275 }
2276 }
2277
2278 /* Determine pixel shader export format */
2279 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2280
2281 surf->color_initialized = true;
2282 }
2283
2284 static void si_init_depth_surface(struct si_context *sctx,
2285 struct r600_surface *surf)
2286 {
2287 struct si_screen *sscreen = sctx->screen;
2288 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2289 unsigned level = surf->base.u.tex.level;
2290 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2291 unsigned format, tile_mode_index, array_mode;
2292 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2293 uint32_t z_info, s_info, db_depth_info;
2294 uint64_t z_offs, s_offs;
2295 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2296
2297 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2298 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2299 case PIPE_FORMAT_X8Z24_UNORM:
2300 case PIPE_FORMAT_Z24X8_UNORM:
2301 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2302 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2303 break;
2304 case PIPE_FORMAT_Z32_FLOAT:
2305 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2306 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2307 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2308 break;
2309 case PIPE_FORMAT_Z16_UNORM:
2310 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2311 break;
2312 default:
2313 assert(0);
2314 }
2315
2316 format = si_translate_dbformat(rtex->resource.b.b.format);
2317
2318 if (format == V_028040_Z_INVALID) {
2319 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2320 }
2321 assert(format != V_028040_Z_INVALID);
2322
2323 s_offs = z_offs = rtex->resource.gpu_address;
2324 z_offs += rtex->surface.level[level].offset;
2325 s_offs += rtex->surface.stencil_level[level].offset;
2326
2327 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2328
2329 z_info = S_028040_FORMAT(format);
2330 if (rtex->resource.b.b.nr_samples > 1) {
2331 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2332 }
2333
2334 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2335 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2336 else
2337 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2338
2339 if (sctx->b.chip_class >= CIK) {
2340 switch (rtex->surface.level[level].mode) {
2341 case RADEON_SURF_MODE_2D:
2342 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2343 break;
2344 case RADEON_SURF_MODE_1D:
2345 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2346 case RADEON_SURF_MODE_LINEAR:
2347 default:
2348 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2349 break;
2350 }
2351 tile_split = rtex->surface.tile_split;
2352 stile_split = rtex->surface.stencil_tile_split;
2353 macro_aspect = rtex->surface.mtilea;
2354 bankw = rtex->surface.bankw;
2355 bankh = rtex->surface.bankh;
2356 tile_split = cik_tile_split(tile_split);
2357 stile_split = cik_tile_split(stile_split);
2358 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2359 bankw = cik_bank_wh(bankw);
2360 bankh = cik_bank_wh(bankh);
2361 nbanks = si_num_banks(sscreen, rtex);
2362 tile_mode_index = si_tile_mode_index(rtex, level, false);
2363 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2364
2365 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2366 S_02803C_PIPE_CONFIG(pipe_config) |
2367 S_02803C_BANK_WIDTH(bankw) |
2368 S_02803C_BANK_HEIGHT(bankh) |
2369 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2370 S_02803C_NUM_BANKS(nbanks);
2371 z_info |= S_028040_TILE_SPLIT(tile_split);
2372 s_info |= S_028044_TILE_SPLIT(stile_split);
2373 } else {
2374 tile_mode_index = si_tile_mode_index(rtex, level, false);
2375 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2376 tile_mode_index = si_tile_mode_index(rtex, level, true);
2377 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2378 }
2379
2380 /* HiZ aka depth buffer htile */
2381 /* use htile only for first level */
2382 if (rtex->htile_buffer && !level) {
2383 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2384 S_028040_ALLOW_EXPCLEAR(1);
2385
2386 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2387 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2388 else
2389 /* Use all of the htile_buffer for depth if there's no stencil. */
2390 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2391
2392 uint64_t va = rtex->htile_buffer->gpu_address;
2393 db_htile_data_base = va >> 8;
2394 db_htile_surface = S_028ABC_FULL_CACHE(1);
2395 } else {
2396 db_htile_data_base = 0;
2397 db_htile_surface = 0;
2398 }
2399
2400 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2401
2402 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2403 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2404 surf->db_htile_data_base = db_htile_data_base;
2405 surf->db_depth_info = db_depth_info;
2406 surf->db_z_info = z_info;
2407 surf->db_stencil_info = s_info;
2408 surf->db_depth_base = z_offs >> 8;
2409 surf->db_stencil_base = s_offs >> 8;
2410 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2411 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2412 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2413 levelinfo->nblk_y) / 64 - 1);
2414 surf->db_htile_surface = db_htile_surface;
2415 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2416
2417 surf->depth_initialized = true;
2418 }
2419
2420 static void si_set_framebuffer_state(struct pipe_context *ctx,
2421 const struct pipe_framebuffer_state *state)
2422 {
2423 struct si_context *sctx = (struct si_context *)ctx;
2424 struct pipe_constant_buffer constbuf = {0};
2425 struct r600_surface *surf = NULL;
2426 struct r600_texture *rtex;
2427 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2428 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2429 int i;
2430
2431 /* Only flush TC when changing the framebuffer state, because
2432 * the only client not using TC that can change textures is
2433 * the framebuffer.
2434 *
2435 * Flush all CB and DB caches here because all buffers can be used
2436 * for write by both TC (with shader image stores) and CB/DB.
2437 */
2438 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2439 SI_CONTEXT_INV_GLOBAL_L2 |
2440 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2441 SI_CONTEXT_CS_PARTIAL_FLUSH;
2442
2443 /* Take the maximum of the old and new count. If the new count is lower,
2444 * dirtying is needed to disable the unbound colorbuffers.
2445 */
2446 sctx->framebuffer.dirty_cbufs |=
2447 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2448 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2449
2450 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2451
2452 sctx->framebuffer.spi_shader_col_format = 0;
2453 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2454 sctx->framebuffer.spi_shader_col_format_blend = 0;
2455 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2456 sctx->framebuffer.color_is_int8 = 0;
2457
2458 sctx->framebuffer.compressed_cb_mask = 0;
2459 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2460 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2461 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2462 util_format_is_pure_integer(state->cbufs[0]->format);
2463
2464 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2465 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2466
2467 for (i = 0; i < state->nr_cbufs; i++) {
2468 if (!state->cbufs[i])
2469 continue;
2470
2471 surf = (struct r600_surface*)state->cbufs[i];
2472 rtex = (struct r600_texture*)surf->base.texture;
2473
2474 if (!surf->color_initialized) {
2475 si_initialize_color_surface(sctx, surf);
2476 }
2477
2478 sctx->framebuffer.spi_shader_col_format |=
2479 surf->spi_shader_col_format << (i * 4);
2480 sctx->framebuffer.spi_shader_col_format_alpha |=
2481 surf->spi_shader_col_format_alpha << (i * 4);
2482 sctx->framebuffer.spi_shader_col_format_blend |=
2483 surf->spi_shader_col_format_blend << (i * 4);
2484 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2485 surf->spi_shader_col_format_blend_alpha << (i * 4);
2486
2487 if (surf->color_is_int8)
2488 sctx->framebuffer.color_is_int8 |= 1 << i;
2489
2490 if (rtex->fmask.size && rtex->cmask.size) {
2491 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2492 }
2493 r600_context_add_resource_size(ctx, surf->base.texture);
2494 }
2495 /* Set the second SPI format for possible dual-src blending. */
2496 if (i == 1 && surf) {
2497 sctx->framebuffer.spi_shader_col_format |=
2498 surf->spi_shader_col_format << (i * 4);
2499 sctx->framebuffer.spi_shader_col_format_alpha |=
2500 surf->spi_shader_col_format_alpha << (i * 4);
2501 sctx->framebuffer.spi_shader_col_format_blend |=
2502 surf->spi_shader_col_format_blend << (i * 4);
2503 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2504 surf->spi_shader_col_format_blend_alpha << (i * 4);
2505 }
2506
2507 if (state->zsbuf) {
2508 surf = (struct r600_surface*)state->zsbuf;
2509
2510 if (!surf->depth_initialized) {
2511 si_init_depth_surface(sctx, surf);
2512 }
2513 r600_context_add_resource_size(ctx, surf->base.texture);
2514 }
2515
2516 si_update_poly_offset_state(sctx);
2517 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2518 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2519
2520 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2521 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2522 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2523
2524 /* Set sample locations as fragment shader constants. */
2525 switch (sctx->framebuffer.nr_samples) {
2526 case 1:
2527 constbuf.user_buffer = sctx->b.sample_locations_1x;
2528 break;
2529 case 2:
2530 constbuf.user_buffer = sctx->b.sample_locations_2x;
2531 break;
2532 case 4:
2533 constbuf.user_buffer = sctx->b.sample_locations_4x;
2534 break;
2535 case 8:
2536 constbuf.user_buffer = sctx->b.sample_locations_8x;
2537 break;
2538 case 16:
2539 constbuf.user_buffer = sctx->b.sample_locations_16x;
2540 break;
2541 default:
2542 R600_ERR("Requested an invalid number of samples %i.\n",
2543 sctx->framebuffer.nr_samples);
2544 assert(0);
2545 }
2546 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2547 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2548 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2549
2550 /* Smoothing (only possible with nr_samples == 1) uses the same
2551 * sample locations as the MSAA it simulates.
2552 *
2553 * Therefore, don't update the sample locations when
2554 * transitioning from no AA to smoothing-equivalent AA, and
2555 * vice versa.
2556 */
2557 if ((sctx->framebuffer.nr_samples != 1 ||
2558 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2559 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2560 old_nr_samples != 1))
2561 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2562 }
2563 }
2564
2565 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2566 {
2567 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2568 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2569 unsigned i, nr_cbufs = state->nr_cbufs;
2570 struct r600_texture *tex = NULL;
2571 struct r600_surface *cb = NULL;
2572
2573 /* Colorbuffers. */
2574 for (i = 0; i < nr_cbufs; i++) {
2575 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2576 continue;
2577
2578 cb = (struct r600_surface*)state->cbufs[i];
2579 if (!cb) {
2580 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2581 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2582 continue;
2583 }
2584
2585 tex = (struct r600_texture *)cb->base.texture;
2586 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2587 &tex->resource, RADEON_USAGE_READWRITE,
2588 tex->surface.nsamples > 1 ?
2589 RADEON_PRIO_COLOR_BUFFER_MSAA :
2590 RADEON_PRIO_COLOR_BUFFER);
2591
2592 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2593 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2594 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2595 RADEON_PRIO_CMASK);
2596 }
2597
2598 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2599 sctx->b.chip_class >= VI ? 14 : 13);
2600 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2601 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2602 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2603 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2604 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2605 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2606 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2607 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2608 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2609 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2610 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2611 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2612 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2613
2614 if (sctx->b.chip_class >= VI)
2615 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2616 }
2617 /* set CB_COLOR1_INFO for possible dual-src blending */
2618 if (i == 1 && state->cbufs[0] &&
2619 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2620 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2621 cb->cb_color_info | tex->cb_color_info);
2622 i++;
2623 }
2624 for (; i < 8 ; i++)
2625 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2626 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2627
2628 /* ZS buffer. */
2629 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2630 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2631 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2632
2633 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2634 &rtex->resource, RADEON_USAGE_READWRITE,
2635 zb->base.texture->nr_samples > 1 ?
2636 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2637 RADEON_PRIO_DEPTH_BUFFER);
2638
2639 if (zb->db_htile_data_base) {
2640 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2641 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2642 RADEON_PRIO_HTILE);
2643 }
2644
2645 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2646 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2647
2648 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2649 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2650 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2651 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2652 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2653 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2654 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2655 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2656 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2657 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2658 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2659
2660 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2661 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2662 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2663
2664 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2665 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2666 zb->pa_su_poly_offset_db_fmt_cntl);
2667 } else if (sctx->framebuffer.dirty_zsbuf) {
2668 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2669 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2670 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2671 }
2672
2673 /* Framebuffer dimensions. */
2674 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2675 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2676 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2677
2678 sctx->framebuffer.dirty_cbufs = 0;
2679 sctx->framebuffer.dirty_zsbuf = false;
2680 }
2681
2682 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2683 struct r600_atom *atom)
2684 {
2685 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2686 unsigned nr_samples = sctx->framebuffer.nr_samples;
2687
2688 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2689 SI_NUM_SMOOTH_AA_SAMPLES);
2690 }
2691
2692 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2693 {
2694 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2695
2696 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2697 sctx->ps_iter_samples,
2698 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2699 }
2700
2701
2702 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2703 {
2704 struct si_context *sctx = (struct si_context *)ctx;
2705
2706 if (sctx->ps_iter_samples == min_samples)
2707 return;
2708
2709 sctx->ps_iter_samples = min_samples;
2710
2711 if (sctx->framebuffer.nr_samples > 1)
2712 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2713 }
2714
2715 /*
2716 * Samplers
2717 */
2718
2719 /**
2720 * Build the sampler view descriptor for a buffer texture.
2721 * @param state 256-bit descriptor; only the high 128 bits are filled in
2722 */
2723 void
2724 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2725 enum pipe_format format,
2726 unsigned first_element, unsigned last_element,
2727 uint32_t *state)
2728 {
2729 const struct util_format_description *desc;
2730 int first_non_void;
2731 uint64_t va;
2732 unsigned stride;
2733 unsigned num_records;
2734 unsigned num_format, data_format;
2735
2736 desc = util_format_description(format);
2737 first_non_void = util_format_get_first_non_void_channel(format);
2738 stride = desc->block.bits / 8;
2739 va = buf->gpu_address + first_element * stride;
2740 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2741 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2742
2743 num_records = last_element + 1 - first_element;
2744 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2745
2746 if (screen->b.chip_class >= VI)
2747 num_records *= stride;
2748
2749 state[4] = va;
2750 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2751 S_008F04_STRIDE(stride);
2752 state[6] = num_records;
2753 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2754 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2755 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2756 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2757 S_008F0C_NUM_FORMAT(num_format) |
2758 S_008F0C_DATA_FORMAT(data_format);
2759 }
2760
2761 /**
2762 * Build the sampler view descriptor for a texture.
2763 */
2764 void
2765 si_make_texture_descriptor(struct si_screen *screen,
2766 struct r600_texture *tex,
2767 bool sampler,
2768 enum pipe_texture_target target,
2769 enum pipe_format pipe_format,
2770 const unsigned char state_swizzle[4],
2771 unsigned base_level, unsigned first_level, unsigned last_level,
2772 unsigned first_layer, unsigned last_layer,
2773 unsigned width, unsigned height, unsigned depth,
2774 uint32_t *state,
2775 uint32_t *fmask_state)
2776 {
2777 struct pipe_resource *res = &tex->resource.b.b;
2778 const struct radeon_surf_level *surflevel = tex->surface.level;
2779 const struct util_format_description *desc;
2780 unsigned char swizzle[4];
2781 int first_non_void;
2782 unsigned num_format, data_format, type;
2783 uint32_t pitch;
2784 uint64_t va;
2785
2786 /* Texturing with separate depth and stencil. */
2787 if (tex->is_depth && !tex->is_flushing_texture) {
2788 switch (pipe_format) {
2789 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2790 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2791 break;
2792 case PIPE_FORMAT_X8Z24_UNORM:
2793 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2794 /* Z24 is always stored like this. */
2795 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2796 break;
2797 case PIPE_FORMAT_X24S8_UINT:
2798 case PIPE_FORMAT_S8X24_UINT:
2799 case PIPE_FORMAT_X32_S8X24_UINT:
2800 pipe_format = PIPE_FORMAT_S8_UINT;
2801 surflevel = tex->surface.stencil_level;
2802 break;
2803 default:;
2804 }
2805 }
2806
2807 desc = util_format_description(pipe_format);
2808
2809 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2810 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2811 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2812
2813 switch (pipe_format) {
2814 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2815 case PIPE_FORMAT_X24S8_UINT:
2816 case PIPE_FORMAT_X32_S8X24_UINT:
2817 case PIPE_FORMAT_X8Z24_UNORM:
2818 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2819 break;
2820 default:
2821 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2822 }
2823 } else {
2824 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2825 }
2826
2827 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2828
2829 switch (pipe_format) {
2830 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2831 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2832 break;
2833 default:
2834 if (first_non_void < 0) {
2835 if (util_format_is_compressed(pipe_format)) {
2836 switch (pipe_format) {
2837 case PIPE_FORMAT_DXT1_SRGB:
2838 case PIPE_FORMAT_DXT1_SRGBA:
2839 case PIPE_FORMAT_DXT3_SRGBA:
2840 case PIPE_FORMAT_DXT5_SRGBA:
2841 case PIPE_FORMAT_BPTC_SRGBA:
2842 case PIPE_FORMAT_ETC2_SRGB8:
2843 case PIPE_FORMAT_ETC2_SRGB8A1:
2844 case PIPE_FORMAT_ETC2_SRGBA8:
2845 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2846 break;
2847 case PIPE_FORMAT_RGTC1_SNORM:
2848 case PIPE_FORMAT_LATC1_SNORM:
2849 case PIPE_FORMAT_RGTC2_SNORM:
2850 case PIPE_FORMAT_LATC2_SNORM:
2851 case PIPE_FORMAT_ETC2_R11_SNORM:
2852 case PIPE_FORMAT_ETC2_RG11_SNORM:
2853 /* implies float, so use SNORM/UNORM to determine
2854 whether data is signed or not */
2855 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2856 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2857 break;
2858 default:
2859 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2860 break;
2861 }
2862 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2863 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2864 } else {
2865 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2866 }
2867 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2868 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2869 } else {
2870 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2871
2872 switch (desc->channel[first_non_void].type) {
2873 case UTIL_FORMAT_TYPE_FLOAT:
2874 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2875 break;
2876 case UTIL_FORMAT_TYPE_SIGNED:
2877 if (desc->channel[first_non_void].normalized)
2878 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2879 else if (desc->channel[first_non_void].pure_integer)
2880 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2881 else
2882 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2883 break;
2884 case UTIL_FORMAT_TYPE_UNSIGNED:
2885 if (desc->channel[first_non_void].normalized)
2886 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2887 else if (desc->channel[first_non_void].pure_integer)
2888 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2889 else
2890 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2891 }
2892 }
2893 }
2894
2895 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2896 if (data_format == ~0) {
2897 data_format = 0;
2898 }
2899
2900 if (!sampler &&
2901 (res->target == PIPE_TEXTURE_CUBE ||
2902 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2903 res->target == PIPE_TEXTURE_3D)) {
2904 /* For the purpose of shader images, treat cube maps and 3D
2905 * textures as 2D arrays. For 3D textures, the address
2906 * calculations for mipmaps are different, so we rely on the
2907 * caller to effectively disable mipmaps.
2908 */
2909 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2910
2911 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2912 } else {
2913 type = si_tex_dim(res->target, target, res->nr_samples);
2914 }
2915
2916 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2917 height = 1;
2918 depth = res->array_size;
2919 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2920 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2921 if (sampler || res->target != PIPE_TEXTURE_3D)
2922 depth = res->array_size;
2923 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2924 depth = res->array_size / 6;
2925
2926 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2927 va = tex->resource.gpu_address + surflevel[base_level].offset;
2928
2929 state[0] = va >> 8;
2930 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2931 S_008F14_DATA_FORMAT(data_format) |
2932 S_008F14_NUM_FORMAT(num_format));
2933 state[2] = (S_008F18_WIDTH(width - 1) |
2934 S_008F18_HEIGHT(height - 1));
2935 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2936 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2937 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2938 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2939 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2940 0 : first_level) |
2941 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2942 util_logbase2(res->nr_samples) :
2943 last_level) |
2944 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
2945 S_008F1C_POW2_PAD(res->last_level > 0) |
2946 S_008F1C_TYPE(type));
2947 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2948 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2949 S_008F24_LAST_ARRAY(last_layer));
2950
2951 if (tex->dcc_offset) {
2952 unsigned swap = r600_translate_colorswap(pipe_format);
2953
2954 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2955 state[7] = (tex->resource.gpu_address +
2956 tex->dcc_offset +
2957 surflevel[base_level].dcc_offset) >> 8;
2958 } else {
2959 state[6] = 0;
2960 state[7] = 0;
2961
2962 /* The last dword is unused by hw. The shader uses it to clear
2963 * bits in the first dword of sampler state.
2964 */
2965 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2966 if (first_level == last_level)
2967 state[7] = C_008F30_MAX_ANISO_RATIO;
2968 else
2969 state[7] = 0xffffffff;
2970 }
2971 }
2972
2973 /* Initialize the sampler view for FMASK. */
2974 if (tex->fmask.size) {
2975 uint32_t fmask_format;
2976
2977 va = tex->resource.gpu_address + tex->fmask.offset;
2978
2979 switch (res->nr_samples) {
2980 case 2:
2981 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2982 break;
2983 case 4:
2984 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2985 break;
2986 case 8:
2987 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2988 break;
2989 default:
2990 assert(0);
2991 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2992 }
2993
2994 fmask_state[0] = va >> 8;
2995 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2996 S_008F14_DATA_FORMAT(fmask_format) |
2997 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2998 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2999 S_008F18_HEIGHT(height - 1);
3000 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3001 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3002 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3003 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3004 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3005 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3006 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3007 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3008 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3009 S_008F24_LAST_ARRAY(last_layer);
3010 fmask_state[6] = 0;
3011 fmask_state[7] = 0;
3012 }
3013 }
3014
3015 /**
3016 * Create a sampler view.
3017 *
3018 * @param ctx context
3019 * @param texture texture
3020 * @param state sampler view template
3021 * @param width0 width0 override (for compressed textures as int)
3022 * @param height0 height0 override (for compressed textures as int)
3023 * @param force_level set the base address to the level (for compressed textures)
3024 */
3025 struct pipe_sampler_view *
3026 si_create_sampler_view_custom(struct pipe_context *ctx,
3027 struct pipe_resource *texture,
3028 const struct pipe_sampler_view *state,
3029 unsigned width0, unsigned height0,
3030 unsigned force_level)
3031 {
3032 struct si_context *sctx = (struct si_context*)ctx;
3033 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3034 struct r600_texture *tmp = (struct r600_texture*)texture;
3035 unsigned base_level, first_level, last_level;
3036 unsigned char state_swizzle[4];
3037 unsigned height, depth, width;
3038 unsigned last_layer = state->u.tex.last_layer;
3039
3040 if (!view)
3041 return NULL;
3042
3043 /* initialize base object */
3044 view->base = *state;
3045 view->base.texture = NULL;
3046 view->base.reference.count = 1;
3047 view->base.context = ctx;
3048
3049 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3050 if (!texture) {
3051 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3052 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3053 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3054 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3055 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3056 return &view->base;
3057 }
3058
3059 pipe_resource_reference(&view->base.texture, texture);
3060
3061 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3062 state->format == PIPE_FORMAT_S8X24_UINT ||
3063 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3064 state->format == PIPE_FORMAT_S8_UINT)
3065 view->is_stencil_sampler = true;
3066
3067 /* Buffer resource. */
3068 if (texture->target == PIPE_BUFFER) {
3069 si_make_buffer_descriptor(sctx->screen,
3070 (struct r600_resource *)texture,
3071 state->format,
3072 state->u.buf.first_element,
3073 state->u.buf.last_element,
3074 view->state);
3075
3076 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3077 return &view->base;
3078 }
3079
3080 state_swizzle[0] = state->swizzle_r;
3081 state_swizzle[1] = state->swizzle_g;
3082 state_swizzle[2] = state->swizzle_b;
3083 state_swizzle[3] = state->swizzle_a;
3084
3085 base_level = 0;
3086 first_level = state->u.tex.first_level;
3087 last_level = state->u.tex.last_level;
3088 width = width0;
3089 height = height0;
3090 depth = texture->depth0;
3091
3092 if (force_level) {
3093 assert(force_level == first_level &&
3094 force_level == last_level);
3095 base_level = force_level;
3096 first_level = 0;
3097 last_level = 0;
3098 width = u_minify(width, force_level);
3099 height = u_minify(height, force_level);
3100 depth = u_minify(depth, force_level);
3101 }
3102
3103 /* This is not needed if state trackers set last_layer correctly. */
3104 if (state->target == PIPE_TEXTURE_1D ||
3105 state->target == PIPE_TEXTURE_2D ||
3106 state->target == PIPE_TEXTURE_RECT ||
3107 state->target == PIPE_TEXTURE_CUBE)
3108 last_layer = state->u.tex.first_layer;
3109
3110 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3111 state->format, state_swizzle,
3112 base_level, first_level, last_level,
3113 state->u.tex.first_layer, last_layer,
3114 width, height, depth,
3115 view->state, view->fmask_state);
3116
3117 return &view->base;
3118 }
3119
3120 static struct pipe_sampler_view *
3121 si_create_sampler_view(struct pipe_context *ctx,
3122 struct pipe_resource *texture,
3123 const struct pipe_sampler_view *state)
3124 {
3125 return si_create_sampler_view_custom(ctx, texture, state,
3126 texture ? texture->width0 : 0,
3127 texture ? texture->height0 : 0, 0);
3128 }
3129
3130 static void si_sampler_view_destroy(struct pipe_context *ctx,
3131 struct pipe_sampler_view *state)
3132 {
3133 struct si_sampler_view *view = (struct si_sampler_view *)state;
3134
3135 if (state->texture && state->texture->target == PIPE_BUFFER)
3136 LIST_DELINIT(&view->list);
3137
3138 pipe_resource_reference(&state->texture, NULL);
3139 FREE(view);
3140 }
3141
3142 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3143 {
3144 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3145 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3146 (linear_filter &&
3147 (wrap == PIPE_TEX_WRAP_CLAMP ||
3148 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3149 }
3150
3151 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3152 {
3153 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3154 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3155
3156 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3157 state->border_color.ui[2] || state->border_color.ui[3]) &&
3158 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3159 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3160 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3161 }
3162
3163 static void *si_create_sampler_state(struct pipe_context *ctx,
3164 const struct pipe_sampler_state *state)
3165 {
3166 struct si_context *sctx = (struct si_context *)ctx;
3167 struct r600_common_screen *rscreen = sctx->b.screen;
3168 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3169 unsigned border_color_type, border_color_index = 0;
3170 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3171 : state->max_anisotropy;
3172 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3173
3174 if (!rstate) {
3175 return NULL;
3176 }
3177
3178 if (!sampler_state_needs_border_color(state))
3179 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3180 else if (state->border_color.f[0] == 0 &&
3181 state->border_color.f[1] == 0 &&
3182 state->border_color.f[2] == 0 &&
3183 state->border_color.f[3] == 0)
3184 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3185 else if (state->border_color.f[0] == 0 &&
3186 state->border_color.f[1] == 0 &&
3187 state->border_color.f[2] == 0 &&
3188 state->border_color.f[3] == 1)
3189 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3190 else if (state->border_color.f[0] == 1 &&
3191 state->border_color.f[1] == 1 &&
3192 state->border_color.f[2] == 1 &&
3193 state->border_color.f[3] == 1)
3194 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3195 else {
3196 int i;
3197
3198 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3199
3200 /* Check if the border has been uploaded already. */
3201 for (i = 0; i < sctx->border_color_count; i++)
3202 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3203 sizeof(state->border_color)) == 0)
3204 break;
3205
3206 if (i >= SI_MAX_BORDER_COLORS) {
3207 /* Getting 4096 unique border colors is very unlikely. */
3208 fprintf(stderr, "radeonsi: The border color table is full. "
3209 "Any new border colors will be just black. "
3210 "Please file a bug.\n");
3211 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3212 } else {
3213 if (i == sctx->border_color_count) {
3214 /* Upload a new border color. */
3215 memcpy(&sctx->border_color_table[i], &state->border_color,
3216 sizeof(state->border_color));
3217 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3218 &state->border_color,
3219 sizeof(state->border_color));
3220 sctx->border_color_count++;
3221 }
3222
3223 border_color_index = i;
3224 }
3225 }
3226
3227 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3228 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3229 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3230 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3231 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3232 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3233 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3234 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3235 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3236 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3237 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3238 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3239 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3240 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3241 S_008F38_MIP_POINT_PRECLAMP(1) |
3242 S_008F38_DISABLE_LSB_CEIL(1) |
3243 S_008F38_FILTER_PREC_FIX(1) |
3244 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3245 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3246 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3247 return rstate;
3248 }
3249
3250 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3251 {
3252 struct si_context *sctx = (struct si_context *)ctx;
3253
3254 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3255 return;
3256
3257 sctx->sample_mask.sample_mask = sample_mask;
3258 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3259 }
3260
3261 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3262 {
3263 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3264 unsigned mask = sctx->sample_mask.sample_mask;
3265
3266 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3267 radeon_emit(cs, mask | (mask << 16));
3268 radeon_emit(cs, mask | (mask << 16));
3269 }
3270
3271 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3272 {
3273 free(state);
3274 }
3275
3276 /*
3277 * Vertex elements & buffers
3278 */
3279
3280 static void *si_create_vertex_elements(struct pipe_context *ctx,
3281 unsigned count,
3282 const struct pipe_vertex_element *elements)
3283 {
3284 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3285 int i;
3286
3287 assert(count <= SI_MAX_ATTRIBS);
3288 if (!v)
3289 return NULL;
3290
3291 v->count = count;
3292 for (i = 0; i < count; ++i) {
3293 const struct util_format_description *desc;
3294 unsigned data_format, num_format;
3295 int first_non_void;
3296
3297 desc = util_format_description(elements[i].src_format);
3298 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3299 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3300 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3301
3302 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3303 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3304 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3305 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3306 S_008F0C_NUM_FORMAT(num_format) |
3307 S_008F0C_DATA_FORMAT(data_format);
3308 v->format_size[i] = desc->block.bits / 8;
3309 }
3310 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3311
3312 return v;
3313 }
3314
3315 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3316 {
3317 struct si_context *sctx = (struct si_context *)ctx;
3318 struct si_vertex_element *v = (struct si_vertex_element*)state;
3319
3320 sctx->vertex_elements = v;
3321 sctx->vertex_buffers_dirty = true;
3322 }
3323
3324 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3325 {
3326 struct si_context *sctx = (struct si_context *)ctx;
3327
3328 if (sctx->vertex_elements == state)
3329 sctx->vertex_elements = NULL;
3330 FREE(state);
3331 }
3332
3333 static void si_set_vertex_buffers(struct pipe_context *ctx,
3334 unsigned start_slot, unsigned count,
3335 const struct pipe_vertex_buffer *buffers)
3336 {
3337 struct si_context *sctx = (struct si_context *)ctx;
3338 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3339 int i;
3340
3341 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3342
3343 if (buffers) {
3344 for (i = 0; i < count; i++) {
3345 const struct pipe_vertex_buffer *src = buffers + i;
3346 struct pipe_vertex_buffer *dsti = dst + i;
3347
3348 pipe_resource_reference(&dsti->buffer, src->buffer);
3349 dsti->buffer_offset = src->buffer_offset;
3350 dsti->stride = src->stride;
3351 r600_context_add_resource_size(ctx, src->buffer);
3352 }
3353 } else {
3354 for (i = 0; i < count; i++) {
3355 pipe_resource_reference(&dst[i].buffer, NULL);
3356 }
3357 }
3358 sctx->vertex_buffers_dirty = true;
3359 }
3360
3361 static void si_set_index_buffer(struct pipe_context *ctx,
3362 const struct pipe_index_buffer *ib)
3363 {
3364 struct si_context *sctx = (struct si_context *)ctx;
3365
3366 if (ib) {
3367 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3368 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3369 r600_context_add_resource_size(ctx, ib->buffer);
3370 } else {
3371 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3372 }
3373 }
3374
3375 /*
3376 * Misc
3377 */
3378
3379 static void si_set_tess_state(struct pipe_context *ctx,
3380 const float default_outer_level[4],
3381 const float default_inner_level[2])
3382 {
3383 struct si_context *sctx = (struct si_context *)ctx;
3384 struct pipe_constant_buffer cb;
3385 float array[8];
3386
3387 memcpy(array, default_outer_level, sizeof(float) * 4);
3388 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3389
3390 cb.buffer = NULL;
3391 cb.user_buffer = NULL;
3392 cb.buffer_size = sizeof(array);
3393
3394 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3395 (void*)array, sizeof(array),
3396 &cb.buffer_offset);
3397
3398 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3399 SI_DRIVER_STATE_CONST_BUF, &cb);
3400 pipe_resource_reference(&cb.buffer, NULL);
3401 }
3402
3403 static void si_texture_barrier(struct pipe_context *ctx)
3404 {
3405 struct si_context *sctx = (struct si_context *)ctx;
3406
3407 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3408 SI_CONTEXT_INV_GLOBAL_L2 |
3409 SI_CONTEXT_FLUSH_AND_INV_CB |
3410 SI_CONTEXT_CS_PARTIAL_FLUSH;
3411 }
3412
3413 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3414 {
3415 struct si_context *sctx = (struct si_context *)ctx;
3416
3417 /* Subsequent commands must wait for all shader invocations to
3418 * complete. */
3419 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3420 SI_CONTEXT_CS_PARTIAL_FLUSH;
3421
3422 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3423 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3424 SI_CONTEXT_INV_VMEM_L1;
3425
3426 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3427 PIPE_BARRIER_SHADER_BUFFER |
3428 PIPE_BARRIER_TEXTURE |
3429 PIPE_BARRIER_IMAGE |
3430 PIPE_BARRIER_STREAMOUT_BUFFER |
3431 PIPE_BARRIER_GLOBAL_BUFFER)) {
3432 /* As far as I can tell, L1 contents are written back to L2
3433 * automatically at end of shader, but the contents of other
3434 * L1 caches might still be stale. */
3435 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3436 }
3437
3438 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3439 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3440
3441 /* Indices are read through TC L2 since VI. */
3442 if (sctx->screen->b.chip_class <= CIK)
3443 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3444 }
3445
3446 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3447 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3448
3449 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3450 PIPE_BARRIER_FRAMEBUFFER |
3451 PIPE_BARRIER_INDIRECT_BUFFER)) {
3452 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3453 *
3454 * We need to make sure that TC L1 & L2 are written back to
3455 * memory, because neither CPU accesses nor CB fetches consider
3456 * TC, but there's no need to invalidate any TC cache lines. */
3457 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3458 }
3459 }
3460
3461 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3462 {
3463 struct pipe_blend_state blend;
3464
3465 memset(&blend, 0, sizeof(blend));
3466 blend.independent_blend_enable = true;
3467 blend.rt[0].colormask = 0xf;
3468 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3469 }
3470
3471 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3472 bool include_draw_vbo)
3473 {
3474 si_need_cs_space((struct si_context*)ctx);
3475 }
3476
3477 static void si_init_config(struct si_context *sctx);
3478
3479 void si_init_state_functions(struct si_context *sctx)
3480 {
3481 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3482 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3483 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3484 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3485 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3486
3487 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3488 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3489 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3490 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3491 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3492 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3493 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3494 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3495 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3496 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3497 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3498
3499 sctx->b.b.create_blend_state = si_create_blend_state;
3500 sctx->b.b.bind_blend_state = si_bind_blend_state;
3501 sctx->b.b.delete_blend_state = si_delete_blend_state;
3502 sctx->b.b.set_blend_color = si_set_blend_color;
3503
3504 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3505 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3506 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3507
3508 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3509 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3510 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3511
3512 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3513 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3514 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3515 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3516 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3517
3518 sctx->b.b.set_clip_state = si_set_clip_state;
3519 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3520
3521 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3522 sctx->b.b.get_sample_position = cayman_get_sample_position;
3523
3524 sctx->b.b.create_sampler_state = si_create_sampler_state;
3525 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3526
3527 sctx->b.b.create_sampler_view = si_create_sampler_view;
3528 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3529
3530 sctx->b.b.set_sample_mask = si_set_sample_mask;
3531
3532 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3533 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3534 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3535 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3536 sctx->b.b.set_index_buffer = si_set_index_buffer;
3537
3538 sctx->b.b.texture_barrier = si_texture_barrier;
3539 sctx->b.b.memory_barrier = si_memory_barrier;
3540 sctx->b.b.set_min_samples = si_set_min_samples;
3541 sctx->b.b.set_tess_state = si_set_tess_state;
3542
3543 sctx->b.b.set_active_query_state = si_set_active_query_state;
3544 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3545 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3546
3547 sctx->b.b.draw_vbo = si_draw_vbo;
3548
3549 if (sctx->b.chip_class >= CIK) {
3550 sctx->b.dma_copy = cik_sdma_copy;
3551 } else {
3552 sctx->b.dma_copy = si_dma_copy;
3553 }
3554
3555 si_init_config(sctx);
3556 }
3557
3558 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3559 struct r600_texture *rtex,
3560 struct radeon_bo_metadata *md)
3561 {
3562 struct si_screen *sscreen = (struct si_screen*)rscreen;
3563 struct pipe_resource *res = &rtex->resource.b.b;
3564 static const unsigned char swizzle[] = {
3565 PIPE_SWIZZLE_RED,
3566 PIPE_SWIZZLE_GREEN,
3567 PIPE_SWIZZLE_BLUE,
3568 PIPE_SWIZZLE_ALPHA
3569 };
3570 uint32_t desc[8], i;
3571 bool is_array = util_resource_is_array_texture(res);
3572
3573 /* DRM 2.x.x doesn't support this. */
3574 if (rscreen->info.drm_major != 3)
3575 return;
3576
3577 assert(rtex->fmask.size == 0);
3578
3579 /* Metadata image format format version 1:
3580 * [0] = 1 (metadata format identifier)
3581 * [1] = (VENDOR_ID << 16) | PCI_ID
3582 * [2:9] = image descriptor for the whole resource
3583 * [2] is always 0, because the base address is cleared
3584 * [9] is the DCC offset bits [39:8] from the beginning of
3585 * the buffer
3586 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3587 */
3588
3589 md->metadata[0] = 1; /* metadata image format version 1 */
3590
3591 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3592 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3593
3594 si_make_texture_descriptor(sscreen, rtex, true,
3595 res->target, res->format,
3596 swizzle, 0, 0, res->last_level, 0,
3597 is_array ? res->array_size - 1 : 0,
3598 res->width0, res->height0, res->depth0,
3599 desc, NULL);
3600
3601 /* Clear the base address and set the relative DCC offset. */
3602 desc[0] = 0;
3603 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3604 desc[7] = rtex->dcc_offset >> 8;
3605
3606 /* Dwords [2:9] contain the image descriptor. */
3607 memcpy(&md->metadata[2], desc, sizeof(desc));
3608
3609 /* Dwords [10:..] contain the mipmap level offsets. */
3610 for (i = 0; i <= res->last_level; i++)
3611 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3612
3613 md->size_metadata = (11 + res->last_level) * 4;
3614 }
3615
3616 void si_init_screen_state_functions(struct si_screen *sscreen)
3617 {
3618 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3619 }
3620
3621 static void
3622 si_write_harvested_raster_configs(struct si_context *sctx,
3623 struct si_pm4_state *pm4,
3624 unsigned raster_config,
3625 unsigned raster_config_1)
3626 {
3627 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3628 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3629 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3630 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3631 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3632 unsigned rb_per_se = num_rb / num_se;
3633 unsigned se_mask[4];
3634 unsigned se;
3635
3636 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3637 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3638 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3639 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3640
3641 assert(num_se == 1 || num_se == 2 || num_se == 4);
3642 assert(sh_per_se == 1 || sh_per_se == 2);
3643 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3644
3645 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3646 * fields are for, so I'm leaving them as their default
3647 * values. */
3648
3649 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3650 (!se_mask[2] && !se_mask[3]))) {
3651 raster_config_1 &= C_028354_SE_PAIR_MAP;
3652
3653 if (!se_mask[0] && !se_mask[1]) {
3654 raster_config_1 |=
3655 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3656 } else {
3657 raster_config_1 |=
3658 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3659 }
3660 }
3661
3662 for (se = 0; se < num_se; se++) {
3663 unsigned raster_config_se = raster_config;
3664 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3665 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3666 int idx = (se / 2) * 2;
3667
3668 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3669 raster_config_se &= C_028350_SE_MAP;
3670
3671 if (!se_mask[idx]) {
3672 raster_config_se |=
3673 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3674 } else {
3675 raster_config_se |=
3676 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3677 }
3678 }
3679
3680 pkr0_mask &= rb_mask;
3681 pkr1_mask &= rb_mask;
3682 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3683 raster_config_se &= C_028350_PKR_MAP;
3684
3685 if (!pkr0_mask) {
3686 raster_config_se |=
3687 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3688 } else {
3689 raster_config_se |=
3690 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3691 }
3692 }
3693
3694 if (rb_per_se >= 2) {
3695 unsigned rb0_mask = 1 << (se * rb_per_se);
3696 unsigned rb1_mask = rb0_mask << 1;
3697
3698 rb0_mask &= rb_mask;
3699 rb1_mask &= rb_mask;
3700 if (!rb0_mask || !rb1_mask) {
3701 raster_config_se &= C_028350_RB_MAP_PKR0;
3702
3703 if (!rb0_mask) {
3704 raster_config_se |=
3705 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3706 } else {
3707 raster_config_se |=
3708 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3709 }
3710 }
3711
3712 if (rb_per_se > 2) {
3713 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3714 rb1_mask = rb0_mask << 1;
3715 rb0_mask &= rb_mask;
3716 rb1_mask &= rb_mask;
3717 if (!rb0_mask || !rb1_mask) {
3718 raster_config_se &= C_028350_RB_MAP_PKR1;
3719
3720 if (!rb0_mask) {
3721 raster_config_se |=
3722 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3723 } else {
3724 raster_config_se |=
3725 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3726 }
3727 }
3728 }
3729 }
3730
3731 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3732 if (sctx->b.chip_class < CIK)
3733 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3734 SE_INDEX(se) | SH_BROADCAST_WRITES |
3735 INSTANCE_BROADCAST_WRITES);
3736 else
3737 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3738 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3739 S_030800_INSTANCE_BROADCAST_WRITES(1));
3740 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3741 if (sctx->b.chip_class >= CIK)
3742 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3743 }
3744
3745 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3746 if (sctx->b.chip_class < CIK)
3747 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3748 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3749 INSTANCE_BROADCAST_WRITES);
3750 else
3751 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3752 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3753 S_030800_INSTANCE_BROADCAST_WRITES(1));
3754 }
3755
3756 static void si_init_config(struct si_context *sctx)
3757 {
3758 struct si_screen *sscreen = sctx->screen;
3759 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3760 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3761 unsigned raster_config, raster_config_1;
3762 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3763 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3764 int i;
3765
3766 if (!pm4)
3767 return;
3768
3769 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3770 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3771 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3772 si_pm4_cmd_end(pm4, false);
3773
3774 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3775 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3776
3777 /* FIXME calculate these values somehow ??? */
3778 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3779 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3780 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3781
3782 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3783 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3784
3785 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3786 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3787 if (sctx->b.chip_class < CIK)
3788 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3789 S_008A14_CLIP_VTX_REORDER_ENA(1));
3790
3791 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3792 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3793
3794 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3795
3796 for (i = 0; i < 16; i++) {
3797 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3798 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3799 }
3800
3801 switch (sctx->screen->b.family) {
3802 case CHIP_TAHITI:
3803 case CHIP_PITCAIRN:
3804 raster_config = 0x2a00126a;
3805 raster_config_1 = 0x00000000;
3806 break;
3807 case CHIP_VERDE:
3808 raster_config = 0x0000124a;
3809 raster_config_1 = 0x00000000;
3810 break;
3811 case CHIP_OLAND:
3812 raster_config = 0x00000082;
3813 raster_config_1 = 0x00000000;
3814 break;
3815 case CHIP_HAINAN:
3816 raster_config = 0x00000000;
3817 raster_config_1 = 0x00000000;
3818 break;
3819 case CHIP_BONAIRE:
3820 raster_config = 0x16000012;
3821 raster_config_1 = 0x00000000;
3822 break;
3823 case CHIP_HAWAII:
3824 raster_config = 0x3a00161a;
3825 raster_config_1 = 0x0000002e;
3826 break;
3827 case CHIP_FIJI:
3828 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3829 /* old kernels with old tiling config */
3830 raster_config = 0x16000012;
3831 raster_config_1 = 0x0000002a;
3832 } else {
3833 raster_config = 0x3a00161a;
3834 raster_config_1 = 0x0000002e;
3835 }
3836 break;
3837 case CHIP_POLARIS10:
3838 raster_config = 0x16000012;
3839 raster_config_1 = 0x0000002a;
3840 break;
3841 case CHIP_POLARIS11:
3842 raster_config = 0x16000012;
3843 raster_config_1 = 0x00000000;
3844 break;
3845 case CHIP_TONGA:
3846 raster_config = 0x16000012;
3847 raster_config_1 = 0x0000002a;
3848 break;
3849 case CHIP_ICELAND:
3850 raster_config = 0x00000002;
3851 raster_config_1 = 0x00000000;
3852 break;
3853 case CHIP_CARRIZO:
3854 raster_config = 0x00000002;
3855 raster_config_1 = 0x00000000;
3856 break;
3857 case CHIP_KAVERI:
3858 /* KV should be 0x00000002, but that causes problems with radeon */
3859 raster_config = 0x00000000; /* 0x00000002 */
3860 raster_config_1 = 0x00000000;
3861 break;
3862 case CHIP_KABINI:
3863 case CHIP_MULLINS:
3864 case CHIP_STONEY:
3865 raster_config = 0x00000000;
3866 raster_config_1 = 0x00000000;
3867 break;
3868 default:
3869 fprintf(stderr,
3870 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3871 raster_config = 0x00000000;
3872 raster_config_1 = 0x00000000;
3873 break;
3874 }
3875
3876 /* Always use the default config when all backends are enabled
3877 * (or when we failed to determine the enabled backends).
3878 */
3879 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3880 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3881 raster_config);
3882 if (sctx->b.chip_class >= CIK)
3883 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3884 raster_config_1);
3885 } else {
3886 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3887 }
3888
3889 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3890 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3891 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3892 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3893 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3894 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3895 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3896
3897 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3898 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3899 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3900 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3901 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3902 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3903 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3904 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3905 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3906 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3907 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3908
3909 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3910 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3911 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3912
3913 if (sctx->b.chip_class >= CIK) {
3914 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3915 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3916 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3917
3918 if (sscreen->b.info.num_good_compute_units /
3919 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3920 /* Too few available compute units per SH. Disallowing
3921 * VS to run on CU0 could hurt us more than late VS
3922 * allocation would help.
3923 *
3924 * LATE_ALLOC_VS = 2 is the highest safe number.
3925 */
3926 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3927 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3928 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3929 } else {
3930 /* Set LATE_ALLOC_VS == 31. It should be less than
3931 * the number of scratch waves. Limitations:
3932 * - VS can't execute on CU0.
3933 * - If HS writes outputs to LDS, LS can't execute on CU0.
3934 */
3935 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3936 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3937 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3938 }
3939
3940 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3941 }
3942
3943 if (sctx->b.chip_class >= VI) {
3944 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3945 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3946 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3947 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3948 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3949 }
3950
3951 if (sctx->b.family == CHIP_STONEY)
3952 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3953
3954 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3955 if (sctx->b.chip_class >= CIK)
3956 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3957 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3958 RADEON_PRIO_BORDER_COLORS);
3959
3960 si_pm4_upload_indirect_buffer(sctx, pm4);
3961 sctx->init_config = pm4;
3962 }