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radeonsi: don't set VGT_VTX_CNT_EN twice in init_config
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state),
51 unsigned num_dw)
52 {
53 atom->emit = (void*)emit_func;
54 atom->num_dw = num_dw;
55 atom->dirty = false;
56 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
57 *list_elem = atom;
58 }
59
60 unsigned si_array_mode(unsigned mode)
61 {
62 switch (mode) {
63 case RADEON_SURF_MODE_LINEAR_ALIGNED:
64 return V_009910_ARRAY_LINEAR_ALIGNED;
65 case RADEON_SURF_MODE_1D:
66 return V_009910_ARRAY_1D_TILED_THIN1;
67 case RADEON_SURF_MODE_2D:
68 return V_009910_ARRAY_2D_TILED_THIN1;
69 default:
70 case RADEON_SURF_MODE_LINEAR:
71 return V_009910_ARRAY_LINEAR_GENERAL;
72 }
73 }
74
75 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
76 {
77 if (sscreen->b.chip_class >= CIK &&
78 sscreen->b.info.cik_macrotile_mode_array_valid) {
79 unsigned index, tileb;
80
81 tileb = 8 * 8 * tex->surface.bpe;
82 tileb = MIN2(tex->surface.tile_split, tileb);
83
84 for (index = 0; tileb > 64; index++) {
85 tileb >>= 1;
86 }
87 assert(index < 16);
88
89 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
90 }
91
92 if (sscreen->b.chip_class == SI &&
93 sscreen->b.info.si_tile_mode_array_valid) {
94 /* Don't use stencil_tiling_index, because num_banks is always
95 * read from the depth mode. */
96 unsigned tile_mode_index = tex->surface.tiling_index[0];
97 assert(tile_mode_index < 32);
98
99 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
100 }
101
102 /* The old way. */
103 switch (sscreen->b.tiling_info.num_banks) {
104 case 2:
105 return V_02803C_ADDR_SURF_2_BANK;
106 case 4:
107 return V_02803C_ADDR_SURF_4_BANK;
108 case 8:
109 default:
110 return V_02803C_ADDR_SURF_8_BANK;
111 case 16:
112 return V_02803C_ADDR_SURF_16_BANK;
113 }
114 }
115
116 unsigned cik_tile_split(unsigned tile_split)
117 {
118 switch (tile_split) {
119 case 64:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
121 break;
122 case 128:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
124 break;
125 case 256:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
127 break;
128 case 512:
129 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
130 break;
131 default:
132 case 1024:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
134 break;
135 case 2048:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
137 break;
138 case 4096:
139 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
140 break;
141 }
142 return tile_split;
143 }
144
145 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
146 {
147 switch (macro_tile_aspect) {
148 default:
149 case 1:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
151 break;
152 case 2:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
154 break;
155 case 4:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
157 break;
158 case 8:
159 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
160 break;
161 }
162 return macro_tile_aspect;
163 }
164
165 unsigned cik_bank_wh(unsigned bankwh)
166 {
167 switch (bankwh) {
168 default:
169 case 1:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
171 break;
172 case 2:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
174 break;
175 case 4:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
177 break;
178 case 8:
179 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
180 break;
181 }
182 return bankwh;
183 }
184
185 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
186 {
187 if (sscreen->b.info.si_tile_mode_array_valid) {
188 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
189
190 return G_009910_PIPE_CONFIG(gb_tile_mode);
191 }
192
193 /* This is probably broken for a lot of chips, but it's only used
194 * if the kernel cannot return the tile mode array for CIK. */
195 switch (sscreen->b.info.r600_num_tile_pipes) {
196 case 16:
197 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
198 case 8:
199 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
200 case 4:
201 default:
202 if (sscreen->b.info.r600_num_backends == 4)
203 return V_02803C_X_ADDR_SURF_P4_16X16;
204 else
205 return V_02803C_X_ADDR_SURF_P4_8X16;
206 case 2:
207 return V_02803C_ADDR_SURF_P2;
208 }
209 }
210
211 static unsigned si_map_swizzle(unsigned swizzle)
212 {
213 switch (swizzle) {
214 case UTIL_FORMAT_SWIZZLE_Y:
215 return V_008F0C_SQ_SEL_Y;
216 case UTIL_FORMAT_SWIZZLE_Z:
217 return V_008F0C_SQ_SEL_Z;
218 case UTIL_FORMAT_SWIZZLE_W:
219 return V_008F0C_SQ_SEL_W;
220 case UTIL_FORMAT_SWIZZLE_0:
221 return V_008F0C_SQ_SEL_0;
222 case UTIL_FORMAT_SWIZZLE_1:
223 return V_008F0C_SQ_SEL_1;
224 default: /* UTIL_FORMAT_SWIZZLE_X */
225 return V_008F0C_SQ_SEL_X;
226 }
227 }
228
229 static uint32_t S_FIXED(float value, uint32_t frac_bits)
230 {
231 return value * (1 << frac_bits);
232 }
233
234 /* 12.4 fixed-point */
235 static unsigned si_pack_float_12p4(float x)
236 {
237 return x <= 0 ? 0 :
238 x >= 4096 ? 0xffff : x * 16;
239 }
240
241 /*
242 * Inferred framebuffer and blender state.
243 *
244 * One of the reasons this must be derived from the framebuffer state is that:
245 * - The blend state mask is 0xf most of the time.
246 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
247 * so COLOR1 is enabled pretty much all the time.
248 * So CB_TARGET_MASK is the only register that can disable COLOR1.
249 *
250 * Another reason is to avoid a hang with dual source blending.
251 */
252 void si_update_fb_blend_state(struct si_context *sctx)
253 {
254 struct si_pm4_state *pm4;
255 struct si_state_blend *blend = sctx->queued.named.blend;
256 uint32_t mask = 0, i;
257
258 if (blend == NULL)
259 return;
260
261 pm4 = CALLOC_STRUCT(si_pm4_state);
262 if (pm4 == NULL)
263 return;
264
265 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
266 if (sctx->framebuffer.state.cbufs[i])
267 mask |= 0xf << (4*i);
268 mask &= blend->cb_target_mask;
269
270 /* Avoid a hang that happens when dual source blending is enabled
271 * but there is not enough color outputs. This is undefined behavior,
272 * so disable color writes completely.
273 *
274 * Reproducible with Unigine Heaven 4.0 and drirc missing.
275 */
276 if (blend->dual_src_blend &&
277 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
278 mask = 0;
279
280 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
281 si_pm4_set_state(sctx, fb_blend, pm4);
282 }
283
284 /*
285 * Blender functions
286 */
287
288 static uint32_t si_translate_blend_function(int blend_func)
289 {
290 switch (blend_func) {
291 case PIPE_BLEND_ADD:
292 return V_028780_COMB_DST_PLUS_SRC;
293 case PIPE_BLEND_SUBTRACT:
294 return V_028780_COMB_SRC_MINUS_DST;
295 case PIPE_BLEND_REVERSE_SUBTRACT:
296 return V_028780_COMB_DST_MINUS_SRC;
297 case PIPE_BLEND_MIN:
298 return V_028780_COMB_MIN_DST_SRC;
299 case PIPE_BLEND_MAX:
300 return V_028780_COMB_MAX_DST_SRC;
301 default:
302 R600_ERR("Unknown blend function %d\n", blend_func);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
309 static uint32_t si_translate_blend_factor(int blend_fact)
310 {
311 switch (blend_fact) {
312 case PIPE_BLENDFACTOR_ONE:
313 return V_028780_BLEND_ONE;
314 case PIPE_BLENDFACTOR_SRC_COLOR:
315 return V_028780_BLEND_SRC_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA:
317 return V_028780_BLEND_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_DST_ALPHA:
319 return V_028780_BLEND_DST_ALPHA;
320 case PIPE_BLENDFACTOR_DST_COLOR:
321 return V_028780_BLEND_DST_COLOR;
322 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case PIPE_BLENDFACTOR_CONST_COLOR:
325 return V_028780_BLEND_CONSTANT_COLOR;
326 case PIPE_BLENDFACTOR_CONST_ALPHA:
327 return V_028780_BLEND_CONSTANT_ALPHA;
328 case PIPE_BLENDFACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
331 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
334 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
336 case PIPE_BLENDFACTOR_INV_DST_COLOR:
337 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
338 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
340 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
342 case PIPE_BLENDFACTOR_SRC1_COLOR:
343 return V_028780_BLEND_SRC1_COLOR;
344 case PIPE_BLENDFACTOR_SRC1_ALPHA:
345 return V_028780_BLEND_SRC1_ALPHA;
346 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
347 return V_028780_BLEND_INV_SRC1_COLOR;
348 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
349 return V_028780_BLEND_INV_SRC1_ALPHA;
350 default:
351 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
352 assert(0);
353 break;
354 }
355 return 0;
356 }
357
358 static void *si_create_blend_state_mode(struct pipe_context *ctx,
359 const struct pipe_blend_state *state,
360 unsigned mode)
361 {
362 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
363 struct si_pm4_state *pm4 = &blend->pm4;
364
365 uint32_t color_control = 0;
366
367 if (blend == NULL)
368 return NULL;
369
370 blend->alpha_to_one = state->alpha_to_one;
371 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
372
373 if (state->logicop_enable) {
374 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
375 } else {
376 color_control |= S_028808_ROP3(0xcc);
377 }
378
379 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
380 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
381 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
382 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
383 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
384 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
385
386 blend->cb_target_mask = 0;
387 for (int i = 0; i < 8; i++) {
388 /* state->rt entries > 0 only written if independent blending */
389 const int j = state->independent_blend_enable ? i : 0;
390
391 unsigned eqRGB = state->rt[j].rgb_func;
392 unsigned srcRGB = state->rt[j].rgb_src_factor;
393 unsigned dstRGB = state->rt[j].rgb_dst_factor;
394 unsigned eqA = state->rt[j].alpha_func;
395 unsigned srcA = state->rt[j].alpha_src_factor;
396 unsigned dstA = state->rt[j].alpha_dst_factor;
397
398 unsigned blend_cntl = 0;
399
400 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
401 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
402
403 if (!state->rt[j].blend_enable) {
404 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
405 continue;
406 }
407
408 blend_cntl |= S_028780_ENABLE(1);
409 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
410 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
411 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
412
413 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
414 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
415 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
416 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
417 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
418 }
419 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
420 }
421
422 if (blend->cb_target_mask) {
423 color_control |= S_028808_MODE(mode);
424 } else {
425 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
426 }
427 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
428
429 return blend;
430 }
431
432 static void *si_create_blend_state(struct pipe_context *ctx,
433 const struct pipe_blend_state *state)
434 {
435 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
436 }
437
438 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
439 {
440 struct si_context *sctx = (struct si_context *)ctx;
441 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
442 si_update_fb_blend_state(sctx);
443 }
444
445 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
446 {
447 struct si_context *sctx = (struct si_context *)ctx;
448 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
449 }
450
451 static void si_set_blend_color(struct pipe_context *ctx,
452 const struct pipe_blend_color *state)
453 {
454 struct si_context *sctx = (struct si_context *)ctx;
455
456 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
457 return;
458
459 sctx->blend_color.state = *state;
460 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
461 }
462
463 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
464 {
465 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
466
467 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
468 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
469 }
470
471 /*
472 * Clipping, scissors and viewport
473 */
474
475 static void si_set_clip_state(struct pipe_context *ctx,
476 const struct pipe_clip_state *state)
477 {
478 struct si_context *sctx = (struct si_context *)ctx;
479 struct pipe_constant_buffer cb;
480
481 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
482 return;
483
484 sctx->clip_state.state = *state;
485 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
486
487 cb.buffer = NULL;
488 cb.user_buffer = state->ucp;
489 cb.buffer_offset = 0;
490 cb.buffer_size = 4*4*8;
491 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
492 pipe_resource_reference(&cb.buffer, NULL);
493 }
494
495 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
496 {
497 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
498
499 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
500 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
501 }
502
503 #define SIX_BITS 0x3F
504
505 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
506 {
507 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
508 struct tgsi_shader_info *info = si_get_vs_info(sctx);
509 unsigned window_space =
510 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
511 unsigned clipdist_mask =
512 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
513
514 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
515 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
516 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
517 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
518 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
519 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
520 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
521 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
522 info->writes_edgeflag ||
523 info->writes_layer ||
524 info->writes_viewport_index) |
525 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
526 (sctx->queued.named.rasterizer->clip_plane_enable &
527 clipdist_mask));
528 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
529 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
530 (clipdist_mask ? 0 :
531 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
532 S_028810_CLIP_DISABLE(window_space));
533 }
534
535 static void si_set_scissor_states(struct pipe_context *ctx,
536 unsigned start_slot,
537 unsigned num_scissors,
538 const struct pipe_scissor_state *state)
539 {
540 struct si_context *sctx = (struct si_context *)ctx;
541 int i;
542
543 for (i = 0; i < num_scissors; i++)
544 sctx->scissors.states[start_slot + i] = state[i];
545
546 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
547 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
548 }
549
550 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
551 {
552 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
553 struct pipe_scissor_state *states = sctx->scissors.states;
554 unsigned mask = sctx->scissors.dirty_mask;
555
556 /* The simple case: Only 1 viewport is active. */
557 if (mask & 1 &&
558 !si_get_vs_info(sctx)->writes_viewport_index) {
559 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
560 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
561 S_028250_TL_Y(states[0].miny) |
562 S_028250_WINDOW_OFFSET_DISABLE(1));
563 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
564 S_028254_BR_Y(states[0].maxy));
565 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
566 return;
567 }
568
569 while (mask) {
570 int start, count, i;
571
572 u_bit_scan_consecutive_range(&mask, &start, &count);
573
574 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
575 start * 4 * 2, count * 2);
576 for (i = start; i < start+count; i++) {
577 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
578 S_028250_TL_Y(states[i].miny) |
579 S_028250_WINDOW_OFFSET_DISABLE(1));
580 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
581 S_028254_BR_Y(states[i].maxy));
582 }
583 }
584 sctx->scissors.dirty_mask = 0;
585 }
586
587 static void si_set_viewport_states(struct pipe_context *ctx,
588 unsigned start_slot,
589 unsigned num_viewports,
590 const struct pipe_viewport_state *state)
591 {
592 struct si_context *sctx = (struct si_context *)ctx;
593 int i;
594
595 for (i = 0; i < num_viewports; i++)
596 sctx->viewports.states[start_slot + i] = state[i];
597
598 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
599 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
600 }
601
602 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
603 {
604 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
605 struct pipe_viewport_state *states = sctx->viewports.states;
606 unsigned mask = sctx->viewports.dirty_mask;
607
608 /* The simple case: Only 1 viewport is active. */
609 if (mask & 1 &&
610 !si_get_vs_info(sctx)->writes_viewport_index) {
611 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
612 radeon_emit(cs, fui(states[0].scale[0]));
613 radeon_emit(cs, fui(states[0].translate[0]));
614 radeon_emit(cs, fui(states[0].scale[1]));
615 radeon_emit(cs, fui(states[0].translate[1]));
616 radeon_emit(cs, fui(states[0].scale[2]));
617 radeon_emit(cs, fui(states[0].translate[2]));
618 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
619 return;
620 }
621
622 while (mask) {
623 int start, count, i;
624
625 u_bit_scan_consecutive_range(&mask, &start, &count);
626
627 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
628 start * 4 * 6, count * 6);
629 for (i = start; i < start+count; i++) {
630 radeon_emit(cs, fui(states[i].scale[0]));
631 radeon_emit(cs, fui(states[i].translate[0]));
632 radeon_emit(cs, fui(states[i].scale[1]));
633 radeon_emit(cs, fui(states[i].translate[1]));
634 radeon_emit(cs, fui(states[i].scale[2]));
635 radeon_emit(cs, fui(states[i].translate[2]));
636 }
637 }
638 sctx->viewports.dirty_mask = 0;
639 }
640
641 /*
642 * inferred state between framebuffer and rasterizer
643 */
644 static void si_update_fb_rs_state(struct si_context *sctx)
645 {
646 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
647 struct si_pm4_state *pm4;
648 float offset_units;
649
650 if (!rs || !sctx->framebuffer.state.zsbuf)
651 return;
652
653 offset_units = sctx->queued.named.rasterizer->offset_units;
654 switch (sctx->framebuffer.state.zsbuf->texture->format) {
655 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
656 case PIPE_FORMAT_X8Z24_UNORM:
657 case PIPE_FORMAT_Z24X8_UNORM:
658 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
659 offset_units *= 2.0f;
660 break;
661 case PIPE_FORMAT_Z32_FLOAT:
662 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
663 offset_units *= 1.0f;
664 break;
665 case PIPE_FORMAT_Z16_UNORM:
666 offset_units *= 4.0f;
667 break;
668 default:
669 return;
670 }
671
672 pm4 = CALLOC_STRUCT(si_pm4_state);
673
674 if (pm4 == NULL)
675 return;
676
677 /* FIXME some of those reg can be computed with cso */
678 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
679 fui(sctx->queued.named.rasterizer->offset_scale));
680 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
681 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
682 fui(sctx->queued.named.rasterizer->offset_scale));
683 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
684
685 si_pm4_set_state(sctx, fb_rs, pm4);
686 }
687
688 /*
689 * Rasterizer
690 */
691
692 static uint32_t si_translate_fill(uint32_t func)
693 {
694 switch(func) {
695 case PIPE_POLYGON_MODE_FILL:
696 return V_028814_X_DRAW_TRIANGLES;
697 case PIPE_POLYGON_MODE_LINE:
698 return V_028814_X_DRAW_LINES;
699 case PIPE_POLYGON_MODE_POINT:
700 return V_028814_X_DRAW_POINTS;
701 default:
702 assert(0);
703 return V_028814_X_DRAW_POINTS;
704 }
705 }
706
707 static void *si_create_rs_state(struct pipe_context *ctx,
708 const struct pipe_rasterizer_state *state)
709 {
710 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
711 struct si_pm4_state *pm4 = &rs->pm4;
712 unsigned tmp;
713 float psize_min, psize_max;
714
715 if (rs == NULL) {
716 return NULL;
717 }
718
719 rs->two_side = state->light_twoside;
720 rs->multisample_enable = state->multisample;
721 rs->clip_plane_enable = state->clip_plane_enable;
722 rs->line_stipple_enable = state->line_stipple_enable;
723 rs->poly_stipple_enable = state->poly_stipple_enable;
724 rs->line_smooth = state->line_smooth;
725 rs->poly_smooth = state->poly_smooth;
726
727 rs->flatshade = state->flatshade;
728 rs->sprite_coord_enable = state->sprite_coord_enable;
729 rs->pa_sc_line_stipple = state->line_stipple_enable ?
730 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
731 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
732 rs->pa_cl_clip_cntl =
733 S_028810_PS_UCP_MODE(3) |
734 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
735 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
736 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
737 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
738 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
739
740 /* offset */
741 rs->offset_units = state->offset_units;
742 rs->offset_scale = state->offset_scale * 16.0f;
743
744 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
745 S_0286D4_FLAT_SHADE_ENA(1) |
746 S_0286D4_PNT_SPRITE_ENA(1) |
747 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
748 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
749 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
750 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
751 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
752
753 /* point size 12.4 fixed point */
754 tmp = (unsigned)(state->point_size * 8.0);
755 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
756
757 if (state->point_size_per_vertex) {
758 psize_min = util_get_min_point_size(state);
759 psize_max = 8192;
760 } else {
761 /* Force the point size to be as if the vertex output was disabled. */
762 psize_min = state->point_size;
763 psize_max = state->point_size;
764 }
765 /* Divide by two, because 0.5 = 1 pixel. */
766 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
767 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
768 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
769
770 tmp = (unsigned)state->line_width * 8;
771 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
772 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
773 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
774 S_028A48_MSAA_ENABLE(state->multisample ||
775 state->poly_smooth ||
776 state->line_smooth) |
777 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
778
779 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
780 S_028BE4_PIX_CENTER(state->half_pixel_center) |
781 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
782
783 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
784 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
785 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
786 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
787 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
788 S_028814_FACE(!state->front_ccw) |
789 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
790 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
791 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
792 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
793 state->fill_back != PIPE_POLYGON_MODE_FILL) |
794 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
795 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
796 return rs;
797 }
798
799 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
800 {
801 struct si_context *sctx = (struct si_context *)ctx;
802 struct si_state_rasterizer *old_rs =
803 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
804 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
805
806 if (state == NULL)
807 return;
808
809 if (sctx->framebuffer.nr_samples > 1 &&
810 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
811 si_mark_atom_dirty(sctx, &sctx->db_render_state);
812
813 si_pm4_bind_state(sctx, rasterizer, rs);
814 si_update_fb_rs_state(sctx);
815
816 si_mark_atom_dirty(sctx, &sctx->clip_regs);
817 }
818
819 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
820 {
821 struct si_context *sctx = (struct si_context *)ctx;
822 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
823 }
824
825 /*
826 * infeered state between dsa and stencil ref
827 */
828 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
829 {
830 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
831 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
832 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
833
834 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
835 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
836 S_028430_STENCILMASK(dsa->valuemask[0]) |
837 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
838 S_028430_STENCILOPVAL(1));
839 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
840 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
841 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
842 S_028434_STENCILOPVAL_BF(1));
843 }
844
845 static void si_set_stencil_ref(struct pipe_context *ctx,
846 const struct pipe_stencil_ref *state)
847 {
848 struct si_context *sctx = (struct si_context *)ctx;
849
850 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
851 return;
852
853 sctx->stencil_ref.state = *state;
854 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
855 }
856
857
858 /*
859 * DSA
860 */
861
862 static uint32_t si_translate_stencil_op(int s_op)
863 {
864 switch (s_op) {
865 case PIPE_STENCIL_OP_KEEP:
866 return V_02842C_STENCIL_KEEP;
867 case PIPE_STENCIL_OP_ZERO:
868 return V_02842C_STENCIL_ZERO;
869 case PIPE_STENCIL_OP_REPLACE:
870 return V_02842C_STENCIL_REPLACE_TEST;
871 case PIPE_STENCIL_OP_INCR:
872 return V_02842C_STENCIL_ADD_CLAMP;
873 case PIPE_STENCIL_OP_DECR:
874 return V_02842C_STENCIL_SUB_CLAMP;
875 case PIPE_STENCIL_OP_INCR_WRAP:
876 return V_02842C_STENCIL_ADD_WRAP;
877 case PIPE_STENCIL_OP_DECR_WRAP:
878 return V_02842C_STENCIL_SUB_WRAP;
879 case PIPE_STENCIL_OP_INVERT:
880 return V_02842C_STENCIL_INVERT;
881 default:
882 R600_ERR("Unknown stencil op %d", s_op);
883 assert(0);
884 break;
885 }
886 return 0;
887 }
888
889 static void *si_create_dsa_state(struct pipe_context *ctx,
890 const struct pipe_depth_stencil_alpha_state *state)
891 {
892 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
893 struct si_pm4_state *pm4 = &dsa->pm4;
894 unsigned db_depth_control;
895 uint32_t db_stencil_control = 0;
896
897 if (dsa == NULL) {
898 return NULL;
899 }
900
901 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
902 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
903 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
904 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
905
906 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
907 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
908 S_028800_ZFUNC(state->depth.func) |
909 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
910
911 /* stencil */
912 if (state->stencil[0].enabled) {
913 db_depth_control |= S_028800_STENCIL_ENABLE(1);
914 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
915 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
916 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
917 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
918
919 if (state->stencil[1].enabled) {
920 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
921 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
922 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
923 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
924 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
925 }
926 }
927
928 /* alpha */
929 if (state->alpha.enabled) {
930 dsa->alpha_func = state->alpha.func;
931
932 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
933 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
934 } else {
935 dsa->alpha_func = PIPE_FUNC_ALWAYS;
936 }
937
938 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
939 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
940 if (state->depth.bounds_test) {
941 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
942 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
943 }
944
945 return dsa;
946 }
947
948 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
949 {
950 struct si_context *sctx = (struct si_context *)ctx;
951 struct si_state_dsa *dsa = state;
952
953 if (state == NULL)
954 return;
955
956 si_pm4_bind_state(sctx, dsa, dsa);
957
958 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
959 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
960 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
961 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
962 }
963 }
964
965 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
966 {
967 struct si_context *sctx = (struct si_context *)ctx;
968 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
969 }
970
971 static void *si_create_db_flush_dsa(struct si_context *sctx)
972 {
973 struct pipe_depth_stencil_alpha_state dsa = {};
974
975 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
976 }
977
978 /* DB RENDER STATE */
979
980 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
981 {
982 struct si_context *sctx = (struct si_context*)ctx;
983
984 si_mark_atom_dirty(sctx, &sctx->db_render_state);
985 }
986
987 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
988 {
989 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
990 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
991 unsigned db_shader_control;
992
993 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
994
995 /* DB_RENDER_CONTROL */
996 if (sctx->dbcb_depth_copy_enabled ||
997 sctx->dbcb_stencil_copy_enabled) {
998 radeon_emit(cs,
999 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1000 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1001 S_028000_COPY_CENTROID(1) |
1002 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1003 } else if (sctx->db_inplace_flush_enabled) {
1004 radeon_emit(cs,
1005 S_028000_DEPTH_COMPRESS_DISABLE(1) |
1006 S_028000_STENCIL_COMPRESS_DISABLE(1));
1007 } else if (sctx->db_depth_clear) {
1008 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1009 } else {
1010 radeon_emit(cs, 0);
1011 }
1012
1013 /* DB_COUNT_CONTROL (occlusion queries) */
1014 if (sctx->b.num_occlusion_queries > 0) {
1015 if (sctx->b.chip_class >= CIK) {
1016 radeon_emit(cs,
1017 S_028004_PERFECT_ZPASS_COUNTS(1) |
1018 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1019 S_028004_ZPASS_ENABLE(1) |
1020 S_028004_SLICE_EVEN_ENABLE(1) |
1021 S_028004_SLICE_ODD_ENABLE(1));
1022 } else {
1023 radeon_emit(cs,
1024 S_028004_PERFECT_ZPASS_COUNTS(1) |
1025 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1026 }
1027 } else {
1028 /* Disable occlusion queries. */
1029 if (sctx->b.chip_class >= CIK) {
1030 radeon_emit(cs, 0);
1031 } else {
1032 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1033 }
1034 }
1035
1036 /* DB_RENDER_OVERRIDE2 */
1037 if (sctx->db_depth_disable_expclear) {
1038 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1039 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1040 } else {
1041 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1042 }
1043
1044 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1045 sctx->ps_db_shader_control;
1046
1047 /* Bug workaround for smoothing (overrasterization) on SI. */
1048 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1049 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1050 else
1051 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1052
1053 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1054 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1055 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1056
1057 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1058 db_shader_control);
1059 }
1060
1061 /*
1062 * format translation
1063 */
1064 static uint32_t si_translate_colorformat(enum pipe_format format)
1065 {
1066 const struct util_format_description *desc = util_format_description(format);
1067
1068 #define HAS_SIZE(x,y,z,w) \
1069 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1070 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1071
1072 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1073 return V_028C70_COLOR_10_11_11;
1074
1075 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1076 return V_028C70_COLOR_INVALID;
1077
1078 switch (desc->nr_channels) {
1079 case 1:
1080 switch (desc->channel[0].size) {
1081 case 8:
1082 return V_028C70_COLOR_8;
1083 case 16:
1084 return V_028C70_COLOR_16;
1085 case 32:
1086 return V_028C70_COLOR_32;
1087 }
1088 break;
1089 case 2:
1090 if (desc->channel[0].size == desc->channel[1].size) {
1091 switch (desc->channel[0].size) {
1092 case 8:
1093 return V_028C70_COLOR_8_8;
1094 case 16:
1095 return V_028C70_COLOR_16_16;
1096 case 32:
1097 return V_028C70_COLOR_32_32;
1098 }
1099 } else if (HAS_SIZE(8,24,0,0)) {
1100 return V_028C70_COLOR_24_8;
1101 } else if (HAS_SIZE(24,8,0,0)) {
1102 return V_028C70_COLOR_8_24;
1103 }
1104 break;
1105 case 3:
1106 if (HAS_SIZE(5,6,5,0)) {
1107 return V_028C70_COLOR_5_6_5;
1108 } else if (HAS_SIZE(32,8,24,0)) {
1109 return V_028C70_COLOR_X24_8_32_FLOAT;
1110 }
1111 break;
1112 case 4:
1113 if (desc->channel[0].size == desc->channel[1].size &&
1114 desc->channel[0].size == desc->channel[2].size &&
1115 desc->channel[0].size == desc->channel[3].size) {
1116 switch (desc->channel[0].size) {
1117 case 4:
1118 return V_028C70_COLOR_4_4_4_4;
1119 case 8:
1120 return V_028C70_COLOR_8_8_8_8;
1121 case 16:
1122 return V_028C70_COLOR_16_16_16_16;
1123 case 32:
1124 return V_028C70_COLOR_32_32_32_32;
1125 }
1126 } else if (HAS_SIZE(5,5,5,1)) {
1127 return V_028C70_COLOR_1_5_5_5;
1128 } else if (HAS_SIZE(10,10,10,2)) {
1129 return V_028C70_COLOR_2_10_10_10;
1130 }
1131 break;
1132 }
1133 return V_028C70_COLOR_INVALID;
1134 }
1135
1136 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1137 {
1138 if (SI_BIG_ENDIAN) {
1139 switch(colorformat) {
1140 /* 8-bit buffers. */
1141 case V_028C70_COLOR_8:
1142 return V_028C70_ENDIAN_NONE;
1143
1144 /* 16-bit buffers. */
1145 case V_028C70_COLOR_5_6_5:
1146 case V_028C70_COLOR_1_5_5_5:
1147 case V_028C70_COLOR_4_4_4_4:
1148 case V_028C70_COLOR_16:
1149 case V_028C70_COLOR_8_8:
1150 return V_028C70_ENDIAN_8IN16;
1151
1152 /* 32-bit buffers. */
1153 case V_028C70_COLOR_8_8_8_8:
1154 case V_028C70_COLOR_2_10_10_10:
1155 case V_028C70_COLOR_8_24:
1156 case V_028C70_COLOR_24_8:
1157 case V_028C70_COLOR_16_16:
1158 return V_028C70_ENDIAN_8IN32;
1159
1160 /* 64-bit buffers. */
1161 case V_028C70_COLOR_16_16_16_16:
1162 return V_028C70_ENDIAN_8IN16;
1163
1164 case V_028C70_COLOR_32_32:
1165 return V_028C70_ENDIAN_8IN32;
1166
1167 /* 128-bit buffers. */
1168 case V_028C70_COLOR_32_32_32_32:
1169 return V_028C70_ENDIAN_8IN32;
1170 default:
1171 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1172 }
1173 } else {
1174 return V_028C70_ENDIAN_NONE;
1175 }
1176 }
1177
1178 /* Returns the size in bits of the widest component of a CB format */
1179 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1180 {
1181 switch(colorformat) {
1182 case V_028C70_COLOR_4_4_4_4:
1183 return 4;
1184
1185 case V_028C70_COLOR_1_5_5_5:
1186 case V_028C70_COLOR_5_5_5_1:
1187 return 5;
1188
1189 case V_028C70_COLOR_5_6_5:
1190 return 6;
1191
1192 case V_028C70_COLOR_8:
1193 case V_028C70_COLOR_8_8:
1194 case V_028C70_COLOR_8_8_8_8:
1195 return 8;
1196
1197 case V_028C70_COLOR_10_10_10_2:
1198 case V_028C70_COLOR_2_10_10_10:
1199 return 10;
1200
1201 case V_028C70_COLOR_10_11_11:
1202 case V_028C70_COLOR_11_11_10:
1203 return 11;
1204
1205 case V_028C70_COLOR_16:
1206 case V_028C70_COLOR_16_16:
1207 case V_028C70_COLOR_16_16_16_16:
1208 return 16;
1209
1210 case V_028C70_COLOR_8_24:
1211 case V_028C70_COLOR_24_8:
1212 return 24;
1213
1214 case V_028C70_COLOR_32:
1215 case V_028C70_COLOR_32_32:
1216 case V_028C70_COLOR_32_32_32_32:
1217 case V_028C70_COLOR_X24_8_32_FLOAT:
1218 return 32;
1219 }
1220
1221 assert(!"Unknown maximum component size");
1222 return 0;
1223 }
1224
1225 static uint32_t si_translate_dbformat(enum pipe_format format)
1226 {
1227 switch (format) {
1228 case PIPE_FORMAT_Z16_UNORM:
1229 return V_028040_Z_16;
1230 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1231 case PIPE_FORMAT_X8Z24_UNORM:
1232 case PIPE_FORMAT_Z24X8_UNORM:
1233 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1234 return V_028040_Z_24; /* deprecated on SI */
1235 case PIPE_FORMAT_Z32_FLOAT:
1236 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1237 return V_028040_Z_32_FLOAT;
1238 default:
1239 return V_028040_Z_INVALID;
1240 }
1241 }
1242
1243 /*
1244 * Texture translation
1245 */
1246
1247 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1248 enum pipe_format format,
1249 const struct util_format_description *desc,
1250 int first_non_void)
1251 {
1252 struct si_screen *sscreen = (struct si_screen*)screen;
1253 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1254 sscreen->b.info.drm_minor >= 31) ||
1255 sscreen->b.info.drm_major == 3;
1256 boolean uniform = TRUE;
1257 int i;
1258
1259 /* Colorspace (return non-RGB formats directly). */
1260 switch (desc->colorspace) {
1261 /* Depth stencil formats */
1262 case UTIL_FORMAT_COLORSPACE_ZS:
1263 switch (format) {
1264 case PIPE_FORMAT_Z16_UNORM:
1265 return V_008F14_IMG_DATA_FORMAT_16;
1266 case PIPE_FORMAT_X24S8_UINT:
1267 case PIPE_FORMAT_Z24X8_UNORM:
1268 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1269 return V_008F14_IMG_DATA_FORMAT_8_24;
1270 case PIPE_FORMAT_X8Z24_UNORM:
1271 case PIPE_FORMAT_S8X24_UINT:
1272 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1273 return V_008F14_IMG_DATA_FORMAT_24_8;
1274 case PIPE_FORMAT_S8_UINT:
1275 return V_008F14_IMG_DATA_FORMAT_8;
1276 case PIPE_FORMAT_Z32_FLOAT:
1277 return V_008F14_IMG_DATA_FORMAT_32;
1278 case PIPE_FORMAT_X32_S8X24_UINT:
1279 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1280 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1281 default:
1282 goto out_unknown;
1283 }
1284
1285 case UTIL_FORMAT_COLORSPACE_YUV:
1286 goto out_unknown; /* TODO */
1287
1288 case UTIL_FORMAT_COLORSPACE_SRGB:
1289 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1290 goto out_unknown;
1291 break;
1292
1293 default:
1294 break;
1295 }
1296
1297 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1298 if (!enable_compressed_formats)
1299 goto out_unknown;
1300
1301 switch (format) {
1302 case PIPE_FORMAT_RGTC1_SNORM:
1303 case PIPE_FORMAT_LATC1_SNORM:
1304 case PIPE_FORMAT_RGTC1_UNORM:
1305 case PIPE_FORMAT_LATC1_UNORM:
1306 return V_008F14_IMG_DATA_FORMAT_BC4;
1307 case PIPE_FORMAT_RGTC2_SNORM:
1308 case PIPE_FORMAT_LATC2_SNORM:
1309 case PIPE_FORMAT_RGTC2_UNORM:
1310 case PIPE_FORMAT_LATC2_UNORM:
1311 return V_008F14_IMG_DATA_FORMAT_BC5;
1312 default:
1313 goto out_unknown;
1314 }
1315 }
1316
1317 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1318 if (!enable_compressed_formats)
1319 goto out_unknown;
1320
1321 switch (format) {
1322 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1323 case PIPE_FORMAT_BPTC_SRGBA:
1324 return V_008F14_IMG_DATA_FORMAT_BC7;
1325 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1326 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1327 return V_008F14_IMG_DATA_FORMAT_BC6;
1328 default:
1329 goto out_unknown;
1330 }
1331 }
1332
1333 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1334 switch (format) {
1335 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1336 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1337 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1338 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1339 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1340 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1341 default:
1342 goto out_unknown;
1343 }
1344 }
1345
1346 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1347 if (!enable_compressed_formats)
1348 goto out_unknown;
1349
1350 if (!util_format_s3tc_enabled) {
1351 goto out_unknown;
1352 }
1353
1354 switch (format) {
1355 case PIPE_FORMAT_DXT1_RGB:
1356 case PIPE_FORMAT_DXT1_RGBA:
1357 case PIPE_FORMAT_DXT1_SRGB:
1358 case PIPE_FORMAT_DXT1_SRGBA:
1359 return V_008F14_IMG_DATA_FORMAT_BC1;
1360 case PIPE_FORMAT_DXT3_RGBA:
1361 case PIPE_FORMAT_DXT3_SRGBA:
1362 return V_008F14_IMG_DATA_FORMAT_BC2;
1363 case PIPE_FORMAT_DXT5_RGBA:
1364 case PIPE_FORMAT_DXT5_SRGBA:
1365 return V_008F14_IMG_DATA_FORMAT_BC3;
1366 default:
1367 goto out_unknown;
1368 }
1369 }
1370
1371 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1372 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1373 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1374 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1375 }
1376
1377 /* R8G8Bx_SNORM - TODO CxV8U8 */
1378
1379 /* See whether the components are of the same size. */
1380 for (i = 1; i < desc->nr_channels; i++) {
1381 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1382 }
1383
1384 /* Non-uniform formats. */
1385 if (!uniform) {
1386 switch(desc->nr_channels) {
1387 case 3:
1388 if (desc->channel[0].size == 5 &&
1389 desc->channel[1].size == 6 &&
1390 desc->channel[2].size == 5) {
1391 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1392 }
1393 goto out_unknown;
1394 case 4:
1395 if (desc->channel[0].size == 5 &&
1396 desc->channel[1].size == 5 &&
1397 desc->channel[2].size == 5 &&
1398 desc->channel[3].size == 1) {
1399 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1400 }
1401 if (desc->channel[0].size == 10 &&
1402 desc->channel[1].size == 10 &&
1403 desc->channel[2].size == 10 &&
1404 desc->channel[3].size == 2) {
1405 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1406 }
1407 goto out_unknown;
1408 }
1409 goto out_unknown;
1410 }
1411
1412 if (first_non_void < 0 || first_non_void > 3)
1413 goto out_unknown;
1414
1415 /* uniform formats */
1416 switch (desc->channel[first_non_void].size) {
1417 case 4:
1418 switch (desc->nr_channels) {
1419 #if 0 /* Not supported for render targets */
1420 case 2:
1421 return V_008F14_IMG_DATA_FORMAT_4_4;
1422 #endif
1423 case 4:
1424 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1425 }
1426 break;
1427 case 8:
1428 switch (desc->nr_channels) {
1429 case 1:
1430 return V_008F14_IMG_DATA_FORMAT_8;
1431 case 2:
1432 return V_008F14_IMG_DATA_FORMAT_8_8;
1433 case 4:
1434 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1435 }
1436 break;
1437 case 16:
1438 switch (desc->nr_channels) {
1439 case 1:
1440 return V_008F14_IMG_DATA_FORMAT_16;
1441 case 2:
1442 return V_008F14_IMG_DATA_FORMAT_16_16;
1443 case 4:
1444 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1445 }
1446 break;
1447 case 32:
1448 switch (desc->nr_channels) {
1449 case 1:
1450 return V_008F14_IMG_DATA_FORMAT_32;
1451 case 2:
1452 return V_008F14_IMG_DATA_FORMAT_32_32;
1453 #if 0 /* Not supported for render targets */
1454 case 3:
1455 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1456 #endif
1457 case 4:
1458 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1459 }
1460 }
1461
1462 out_unknown:
1463 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1464 return ~0;
1465 }
1466
1467 static unsigned si_tex_wrap(unsigned wrap)
1468 {
1469 switch (wrap) {
1470 default:
1471 case PIPE_TEX_WRAP_REPEAT:
1472 return V_008F30_SQ_TEX_WRAP;
1473 case PIPE_TEX_WRAP_CLAMP:
1474 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1475 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1476 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1477 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1478 return V_008F30_SQ_TEX_CLAMP_BORDER;
1479 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1480 return V_008F30_SQ_TEX_MIRROR;
1481 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1482 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1483 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1484 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1485 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1486 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1487 }
1488 }
1489
1490 static unsigned si_tex_filter(unsigned filter)
1491 {
1492 switch (filter) {
1493 default:
1494 case PIPE_TEX_FILTER_NEAREST:
1495 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1496 case PIPE_TEX_FILTER_LINEAR:
1497 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1498 }
1499 }
1500
1501 static unsigned si_tex_mipfilter(unsigned filter)
1502 {
1503 switch (filter) {
1504 case PIPE_TEX_MIPFILTER_NEAREST:
1505 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1506 case PIPE_TEX_MIPFILTER_LINEAR:
1507 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1508 default:
1509 case PIPE_TEX_MIPFILTER_NONE:
1510 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1511 }
1512 }
1513
1514 static unsigned si_tex_compare(unsigned compare)
1515 {
1516 switch (compare) {
1517 default:
1518 case PIPE_FUNC_NEVER:
1519 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1520 case PIPE_FUNC_LESS:
1521 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1522 case PIPE_FUNC_EQUAL:
1523 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1524 case PIPE_FUNC_LEQUAL:
1525 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1526 case PIPE_FUNC_GREATER:
1527 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1528 case PIPE_FUNC_NOTEQUAL:
1529 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1530 case PIPE_FUNC_GEQUAL:
1531 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1532 case PIPE_FUNC_ALWAYS:
1533 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1534 }
1535 }
1536
1537 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1538 {
1539 switch (dim) {
1540 default:
1541 case PIPE_TEXTURE_1D:
1542 return V_008F1C_SQ_RSRC_IMG_1D;
1543 case PIPE_TEXTURE_1D_ARRAY:
1544 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1545 case PIPE_TEXTURE_2D:
1546 case PIPE_TEXTURE_RECT:
1547 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1548 V_008F1C_SQ_RSRC_IMG_2D;
1549 case PIPE_TEXTURE_2D_ARRAY:
1550 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1551 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1552 case PIPE_TEXTURE_3D:
1553 return V_008F1C_SQ_RSRC_IMG_3D;
1554 case PIPE_TEXTURE_CUBE:
1555 case PIPE_TEXTURE_CUBE_ARRAY:
1556 return V_008F1C_SQ_RSRC_IMG_CUBE;
1557 }
1558 }
1559
1560 /*
1561 * Format support testing
1562 */
1563
1564 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1565 {
1566 return si_translate_texformat(screen, format, util_format_description(format),
1567 util_format_get_first_non_void_channel(format)) != ~0U;
1568 }
1569
1570 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1571 const struct util_format_description *desc,
1572 int first_non_void)
1573 {
1574 unsigned type = desc->channel[first_non_void].type;
1575 int i;
1576
1577 if (type == UTIL_FORMAT_TYPE_FIXED)
1578 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1579
1580 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1581 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1582
1583 if (desc->nr_channels == 4 &&
1584 desc->channel[0].size == 10 &&
1585 desc->channel[1].size == 10 &&
1586 desc->channel[2].size == 10 &&
1587 desc->channel[3].size == 2)
1588 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1589
1590 /* See whether the components are of the same size. */
1591 for (i = 0; i < desc->nr_channels; i++) {
1592 if (desc->channel[first_non_void].size != desc->channel[i].size)
1593 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1594 }
1595
1596 switch (desc->channel[first_non_void].size) {
1597 case 8:
1598 switch (desc->nr_channels) {
1599 case 1:
1600 return V_008F0C_BUF_DATA_FORMAT_8;
1601 case 2:
1602 return V_008F0C_BUF_DATA_FORMAT_8_8;
1603 case 3:
1604 case 4:
1605 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1606 }
1607 break;
1608 case 16:
1609 switch (desc->nr_channels) {
1610 case 1:
1611 return V_008F0C_BUF_DATA_FORMAT_16;
1612 case 2:
1613 return V_008F0C_BUF_DATA_FORMAT_16_16;
1614 case 3:
1615 case 4:
1616 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1617 }
1618 break;
1619 case 32:
1620 /* From the Southern Islands ISA documentation about MTBUF:
1621 * 'Memory reads of data in memory that is 32 or 64 bits do not
1622 * undergo any format conversion.'
1623 */
1624 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1625 !desc->channel[first_non_void].pure_integer)
1626 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1627
1628 switch (desc->nr_channels) {
1629 case 1:
1630 return V_008F0C_BUF_DATA_FORMAT_32;
1631 case 2:
1632 return V_008F0C_BUF_DATA_FORMAT_32_32;
1633 case 3:
1634 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1635 case 4:
1636 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1637 }
1638 break;
1639 }
1640
1641 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1642 }
1643
1644 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1645 const struct util_format_description *desc,
1646 int first_non_void)
1647 {
1648 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1649 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1650
1651 switch (desc->channel[first_non_void].type) {
1652 case UTIL_FORMAT_TYPE_SIGNED:
1653 if (desc->channel[first_non_void].normalized)
1654 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1655 else if (desc->channel[first_non_void].pure_integer)
1656 return V_008F0C_BUF_NUM_FORMAT_SINT;
1657 else
1658 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1659 break;
1660 case UTIL_FORMAT_TYPE_UNSIGNED:
1661 if (desc->channel[first_non_void].normalized)
1662 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1663 else if (desc->channel[first_non_void].pure_integer)
1664 return V_008F0C_BUF_NUM_FORMAT_UINT;
1665 else
1666 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1667 break;
1668 case UTIL_FORMAT_TYPE_FLOAT:
1669 default:
1670 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1671 }
1672 }
1673
1674 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1675 {
1676 const struct util_format_description *desc;
1677 int first_non_void;
1678 unsigned data_format;
1679
1680 desc = util_format_description(format);
1681 first_non_void = util_format_get_first_non_void_channel(format);
1682 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1683 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1684 }
1685
1686 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1687 {
1688 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1689 r600_translate_colorswap(format) != ~0U;
1690 }
1691
1692 static bool si_is_zs_format_supported(enum pipe_format format)
1693 {
1694 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1695 }
1696
1697 boolean si_is_format_supported(struct pipe_screen *screen,
1698 enum pipe_format format,
1699 enum pipe_texture_target target,
1700 unsigned sample_count,
1701 unsigned usage)
1702 {
1703 unsigned retval = 0;
1704
1705 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1706 R600_ERR("r600: unsupported texture type %d\n", target);
1707 return FALSE;
1708 }
1709
1710 if (!util_format_is_supported(format, usage))
1711 return FALSE;
1712
1713 if (sample_count > 1) {
1714 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1715 return FALSE;
1716
1717 switch (sample_count) {
1718 case 2:
1719 case 4:
1720 case 8:
1721 break;
1722 default:
1723 return FALSE;
1724 }
1725 }
1726
1727 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1728 if (target == PIPE_BUFFER) {
1729 if (si_is_vertex_format_supported(screen, format))
1730 retval |= PIPE_BIND_SAMPLER_VIEW;
1731 } else {
1732 if (si_is_sampler_format_supported(screen, format))
1733 retval |= PIPE_BIND_SAMPLER_VIEW;
1734 }
1735 }
1736
1737 if ((usage & (PIPE_BIND_RENDER_TARGET |
1738 PIPE_BIND_DISPLAY_TARGET |
1739 PIPE_BIND_SCANOUT |
1740 PIPE_BIND_SHARED |
1741 PIPE_BIND_BLENDABLE)) &&
1742 si_is_colorbuffer_format_supported(format)) {
1743 retval |= usage &
1744 (PIPE_BIND_RENDER_TARGET |
1745 PIPE_BIND_DISPLAY_TARGET |
1746 PIPE_BIND_SCANOUT |
1747 PIPE_BIND_SHARED);
1748 if (!util_format_is_pure_integer(format) &&
1749 !util_format_is_depth_or_stencil(format))
1750 retval |= usage & PIPE_BIND_BLENDABLE;
1751 }
1752
1753 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1754 si_is_zs_format_supported(format)) {
1755 retval |= PIPE_BIND_DEPTH_STENCIL;
1756 }
1757
1758 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1759 si_is_vertex_format_supported(screen, format)) {
1760 retval |= PIPE_BIND_VERTEX_BUFFER;
1761 }
1762
1763 if (usage & PIPE_BIND_TRANSFER_READ)
1764 retval |= PIPE_BIND_TRANSFER_READ;
1765 if (usage & PIPE_BIND_TRANSFER_WRITE)
1766 retval |= PIPE_BIND_TRANSFER_WRITE;
1767
1768 return retval == usage;
1769 }
1770
1771 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1772 {
1773 unsigned tile_mode_index = 0;
1774
1775 if (stencil) {
1776 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1777 } else {
1778 tile_mode_index = rtex->surface.tiling_index[level];
1779 }
1780 return tile_mode_index;
1781 }
1782
1783 /*
1784 * framebuffer handling
1785 */
1786
1787 static void si_initialize_color_surface(struct si_context *sctx,
1788 struct r600_surface *surf)
1789 {
1790 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1791 unsigned level = surf->base.u.tex.level;
1792 uint64_t offset = rtex->surface.level[level].offset;
1793 unsigned pitch, slice;
1794 unsigned color_info, color_attrib, color_pitch, color_view;
1795 unsigned tile_mode_index;
1796 unsigned format, swap, ntype, endian;
1797 const struct util_format_description *desc;
1798 int i;
1799 unsigned blend_clamp = 0, blend_bypass = 0;
1800 unsigned max_comp_size;
1801
1802 /* Layered rendering doesn't work with LINEAR_GENERAL.
1803 * (LINEAR_ALIGNED and others work) */
1804 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1805 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1806 offset += rtex->surface.level[level].slice_size *
1807 surf->base.u.tex.first_layer;
1808 color_view = 0;
1809 } else {
1810 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1811 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1812 }
1813
1814 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1815 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1816 if (slice) {
1817 slice = slice - 1;
1818 }
1819
1820 tile_mode_index = si_tile_mode_index(rtex, level, false);
1821
1822 desc = util_format_description(surf->base.format);
1823 for (i = 0; i < 4; i++) {
1824 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1825 break;
1826 }
1827 }
1828 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1829 ntype = V_028C70_NUMBER_FLOAT;
1830 } else {
1831 ntype = V_028C70_NUMBER_UNORM;
1832 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1833 ntype = V_028C70_NUMBER_SRGB;
1834 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1835 if (desc->channel[i].pure_integer) {
1836 ntype = V_028C70_NUMBER_SINT;
1837 } else {
1838 assert(desc->channel[i].normalized);
1839 ntype = V_028C70_NUMBER_SNORM;
1840 }
1841 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1842 if (desc->channel[i].pure_integer) {
1843 ntype = V_028C70_NUMBER_UINT;
1844 } else {
1845 assert(desc->channel[i].normalized);
1846 ntype = V_028C70_NUMBER_UNORM;
1847 }
1848 }
1849 }
1850
1851 format = si_translate_colorformat(surf->base.format);
1852 if (format == V_028C70_COLOR_INVALID) {
1853 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1854 }
1855 assert(format != V_028C70_COLOR_INVALID);
1856 swap = r600_translate_colorswap(surf->base.format);
1857 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1858 endian = V_028C70_ENDIAN_NONE;
1859 } else {
1860 endian = si_colorformat_endian_swap(format);
1861 }
1862
1863 /* blend clamp should be set for all NORM/SRGB types */
1864 if (ntype == V_028C70_NUMBER_UNORM ||
1865 ntype == V_028C70_NUMBER_SNORM ||
1866 ntype == V_028C70_NUMBER_SRGB)
1867 blend_clamp = 1;
1868
1869 /* set blend bypass according to docs if SINT/UINT or
1870 8/24 COLOR variants */
1871 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1872 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1873 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1874 blend_clamp = 0;
1875 blend_bypass = 1;
1876 }
1877
1878 color_info = S_028C70_FORMAT(format) |
1879 S_028C70_COMP_SWAP(swap) |
1880 S_028C70_BLEND_CLAMP(blend_clamp) |
1881 S_028C70_BLEND_BYPASS(blend_bypass) |
1882 S_028C70_NUMBER_TYPE(ntype) |
1883 S_028C70_ENDIAN(endian);
1884
1885 color_pitch = S_028C64_TILE_MAX(pitch);
1886
1887 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1888 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1889
1890 if (rtex->resource.b.b.nr_samples > 1) {
1891 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1892
1893 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1894 S_028C74_NUM_FRAGMENTS(log_samples);
1895
1896 if (rtex->fmask.size) {
1897 color_info |= S_028C70_COMPRESSION(1);
1898 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1899
1900 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1901
1902 if (sctx->b.chip_class == SI) {
1903 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1904 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1905 }
1906 if (sctx->b.chip_class >= CIK) {
1907 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1908 }
1909 }
1910 }
1911
1912 offset += rtex->resource.gpu_address;
1913
1914 surf->cb_color_base = offset >> 8;
1915 surf->cb_color_pitch = color_pitch;
1916 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1917 surf->cb_color_view = color_view;
1918 surf->cb_color_info = color_info;
1919 surf->cb_color_attrib = color_attrib;
1920
1921 if (sctx->b.chip_class >= VI)
1922 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1923
1924 if (rtex->fmask.size) {
1925 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1926 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1927 } else {
1928 /* This must be set for fast clear to work without FMASK. */
1929 surf->cb_color_fmask = surf->cb_color_base;
1930 surf->cb_color_fmask_slice = surf->cb_color_slice;
1931 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1932
1933 if (sctx->b.chip_class == SI) {
1934 unsigned bankh = util_logbase2(rtex->surface.bankh);
1935 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1936 }
1937
1938 if (sctx->b.chip_class >= CIK) {
1939 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1940 }
1941 }
1942
1943 /* Determine pixel shader export format */
1944 max_comp_size = si_colorformat_max_comp_size(format);
1945 if (ntype == V_028C70_NUMBER_SRGB ||
1946 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1947 max_comp_size <= 10) ||
1948 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1949 surf->export_16bpc = true;
1950 }
1951
1952 surf->color_initialized = true;
1953 }
1954
1955 static void si_init_depth_surface(struct si_context *sctx,
1956 struct r600_surface *surf)
1957 {
1958 struct si_screen *sscreen = sctx->screen;
1959 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1960 unsigned level = surf->base.u.tex.level;
1961 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1962 unsigned format, tile_mode_index, array_mode;
1963 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1964 uint32_t z_info, s_info, db_depth_info;
1965 uint64_t z_offs, s_offs;
1966 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1967
1968 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1969 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1970 case PIPE_FORMAT_X8Z24_UNORM:
1971 case PIPE_FORMAT_Z24X8_UNORM:
1972 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1973 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1974 break;
1975 case PIPE_FORMAT_Z32_FLOAT:
1976 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1977 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1978 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1979 break;
1980 case PIPE_FORMAT_Z16_UNORM:
1981 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1982 break;
1983 default:
1984 assert(0);
1985 }
1986
1987 format = si_translate_dbformat(rtex->resource.b.b.format);
1988
1989 if (format == V_028040_Z_INVALID) {
1990 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1991 }
1992 assert(format != V_028040_Z_INVALID);
1993
1994 s_offs = z_offs = rtex->resource.gpu_address;
1995 z_offs += rtex->surface.level[level].offset;
1996 s_offs += rtex->surface.stencil_level[level].offset;
1997
1998 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1999
2000 z_info = S_028040_FORMAT(format);
2001 if (rtex->resource.b.b.nr_samples > 1) {
2002 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2003 }
2004
2005 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2006 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2007 else
2008 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2009
2010 if (sctx->b.chip_class >= CIK) {
2011 switch (rtex->surface.level[level].mode) {
2012 case RADEON_SURF_MODE_2D:
2013 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2014 break;
2015 case RADEON_SURF_MODE_1D:
2016 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2017 case RADEON_SURF_MODE_LINEAR:
2018 default:
2019 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2020 break;
2021 }
2022 tile_split = rtex->surface.tile_split;
2023 stile_split = rtex->surface.stencil_tile_split;
2024 macro_aspect = rtex->surface.mtilea;
2025 bankw = rtex->surface.bankw;
2026 bankh = rtex->surface.bankh;
2027 tile_split = cik_tile_split(tile_split);
2028 stile_split = cik_tile_split(stile_split);
2029 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2030 bankw = cik_bank_wh(bankw);
2031 bankh = cik_bank_wh(bankh);
2032 nbanks = si_num_banks(sscreen, rtex);
2033 tile_mode_index = si_tile_mode_index(rtex, level, false);
2034 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2035
2036 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2037 S_02803C_PIPE_CONFIG(pipe_config) |
2038 S_02803C_BANK_WIDTH(bankw) |
2039 S_02803C_BANK_HEIGHT(bankh) |
2040 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2041 S_02803C_NUM_BANKS(nbanks);
2042 z_info |= S_028040_TILE_SPLIT(tile_split);
2043 s_info |= S_028044_TILE_SPLIT(stile_split);
2044 } else {
2045 tile_mode_index = si_tile_mode_index(rtex, level, false);
2046 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2047 tile_mode_index = si_tile_mode_index(rtex, level, true);
2048 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2049 }
2050
2051 /* HiZ aka depth buffer htile */
2052 /* use htile only for first level */
2053 if (rtex->htile_buffer && !level) {
2054 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2055 S_028040_ALLOW_EXPCLEAR(1);
2056
2057 /* Use all of the htile_buffer for depth, because we don't
2058 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2059 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2060
2061 uint64_t va = rtex->htile_buffer->gpu_address;
2062 db_htile_data_base = va >> 8;
2063 db_htile_surface = S_028ABC_FULL_CACHE(1);
2064 } else {
2065 db_htile_data_base = 0;
2066 db_htile_surface = 0;
2067 }
2068
2069 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2070
2071 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2072 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2073 surf->db_htile_data_base = db_htile_data_base;
2074 surf->db_depth_info = db_depth_info;
2075 surf->db_z_info = z_info;
2076 surf->db_stencil_info = s_info;
2077 surf->db_depth_base = z_offs >> 8;
2078 surf->db_stencil_base = s_offs >> 8;
2079 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2080 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2081 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2082 levelinfo->nblk_y) / 64 - 1);
2083 surf->db_htile_surface = db_htile_surface;
2084 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2085
2086 surf->depth_initialized = true;
2087 }
2088
2089 static void si_set_framebuffer_state(struct pipe_context *ctx,
2090 const struct pipe_framebuffer_state *state)
2091 {
2092 struct si_context *sctx = (struct si_context *)ctx;
2093 struct pipe_constant_buffer constbuf = {0};
2094 struct r600_surface *surf = NULL;
2095 struct r600_texture *rtex;
2096 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2097 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2098 int i;
2099
2100 /* Only flush TC when changing the framebuffer state, because
2101 * the only client not using TC that can change textures is
2102 * the framebuffer.
2103 *
2104 * Flush all CB and DB caches here because all buffers can be used
2105 * for write by both TC (with shader image stores) and CB/DB.
2106 */
2107 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2108 SI_CONTEXT_INV_TC_L2 |
2109 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2110
2111 /* Take the maximum of the old and new count. If the new count is lower,
2112 * dirtying is needed to disable the unbound colorbuffers.
2113 */
2114 sctx->framebuffer.dirty_cbufs |=
2115 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2116 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2117
2118 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2119
2120 sctx->framebuffer.export_16bpc = 0;
2121 sctx->framebuffer.compressed_cb_mask = 0;
2122 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2123 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2124 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2125 util_format_is_pure_integer(state->cbufs[0]->format);
2126
2127 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2128 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2129
2130 for (i = 0; i < state->nr_cbufs; i++) {
2131 if (!state->cbufs[i])
2132 continue;
2133
2134 surf = (struct r600_surface*)state->cbufs[i];
2135 rtex = (struct r600_texture*)surf->base.texture;
2136
2137 if (!surf->color_initialized) {
2138 si_initialize_color_surface(sctx, surf);
2139 }
2140
2141 if (surf->export_16bpc) {
2142 sctx->framebuffer.export_16bpc |= 1 << i;
2143 }
2144
2145 if (rtex->fmask.size && rtex->cmask.size) {
2146 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2147 }
2148 r600_context_add_resource_size(ctx, surf->base.texture);
2149 }
2150 /* Set the 16BPC export for possible dual-src blending. */
2151 if (i == 1 && surf && surf->export_16bpc) {
2152 sctx->framebuffer.export_16bpc |= 1 << 1;
2153 }
2154
2155 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2156
2157 if (state->zsbuf) {
2158 surf = (struct r600_surface*)state->zsbuf;
2159
2160 if (!surf->depth_initialized) {
2161 si_init_depth_surface(sctx, surf);
2162 }
2163 r600_context_add_resource_size(ctx, surf->base.texture);
2164 }
2165
2166 si_update_fb_rs_state(sctx);
2167 si_update_fb_blend_state(sctx);
2168
2169 sctx->framebuffer.atom.num_dw = state->nr_cbufs*16 + (8 - state->nr_cbufs)*3;
2170 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2171 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2172 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2173 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2174
2175 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2176 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2177 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2178
2179 /* Set sample locations as fragment shader constants. */
2180 switch (sctx->framebuffer.nr_samples) {
2181 case 1:
2182 constbuf.user_buffer = sctx->b.sample_locations_1x;
2183 break;
2184 case 2:
2185 constbuf.user_buffer = sctx->b.sample_locations_2x;
2186 break;
2187 case 4:
2188 constbuf.user_buffer = sctx->b.sample_locations_4x;
2189 break;
2190 case 8:
2191 constbuf.user_buffer = sctx->b.sample_locations_8x;
2192 break;
2193 case 16:
2194 constbuf.user_buffer = sctx->b.sample_locations_16x;
2195 break;
2196 default:
2197 assert(0);
2198 }
2199 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2200 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2201 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2202
2203 /* Smoothing (only possible with nr_samples == 1) uses the same
2204 * sample locations as the MSAA it simulates.
2205 *
2206 * Therefore, don't update the sample locations when
2207 * transitioning from no AA to smoothing-equivalent AA, and
2208 * vice versa.
2209 */
2210 if ((sctx->framebuffer.nr_samples != 1 ||
2211 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2212 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2213 old_nr_samples != 1))
2214 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2215 }
2216 }
2217
2218 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2219 {
2220 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2221 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2222 unsigned i, nr_cbufs = state->nr_cbufs;
2223 struct r600_texture *tex = NULL;
2224 struct r600_surface *cb = NULL;
2225
2226 /* Colorbuffers. */
2227 for (i = 0; i < nr_cbufs; i++) {
2228 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2229 continue;
2230
2231 cb = (struct r600_surface*)state->cbufs[i];
2232 if (!cb) {
2233 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2234 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2235 continue;
2236 }
2237
2238 tex = (struct r600_texture *)cb->base.texture;
2239 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2240 &tex->resource, RADEON_USAGE_READWRITE,
2241 tex->surface.nsamples > 1 ?
2242 RADEON_PRIO_COLOR_BUFFER_MSAA :
2243 RADEON_PRIO_COLOR_BUFFER);
2244
2245 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2246 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2247 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2248 RADEON_PRIO_COLOR_META);
2249 }
2250
2251 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2252 sctx->b.chip_class >= VI ? 14 : 13);
2253 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2254 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2255 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2256 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2257 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2258 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2259 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2260 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2261 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2262 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2263 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2264 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2265 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2266
2267 if (sctx->b.chip_class >= VI)
2268 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2269 }
2270 /* set CB_COLOR1_INFO for possible dual-src blending */
2271 if (i == 1 && state->cbufs[0] &&
2272 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2273 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2274 cb->cb_color_info | tex->cb_color_info);
2275 i++;
2276 }
2277 for (; i < 8 ; i++)
2278 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2279 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2280
2281 /* ZS buffer. */
2282 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2283 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2284 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2285
2286 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2287 &rtex->resource, RADEON_USAGE_READWRITE,
2288 zb->base.texture->nr_samples > 1 ?
2289 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2290 RADEON_PRIO_DEPTH_BUFFER);
2291
2292 if (zb->db_htile_data_base) {
2293 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2294 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2295 RADEON_PRIO_DEPTH_META);
2296 }
2297
2298 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2299 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2300
2301 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2302 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2303 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2304 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2305 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2306 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2307 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2308 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2309 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2310 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2311 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2312
2313 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2314 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2315 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2316 zb->pa_su_poly_offset_db_fmt_cntl);
2317 } else if (sctx->framebuffer.dirty_zsbuf) {
2318 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2319 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2320 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2321 }
2322
2323 /* Framebuffer dimensions. */
2324 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2325 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2326 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2327
2328 sctx->framebuffer.dirty_cbufs = 0;
2329 sctx->framebuffer.dirty_zsbuf = false;
2330 }
2331
2332 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2333 struct r600_atom *atom)
2334 {
2335 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2336 unsigned nr_samples = sctx->framebuffer.nr_samples;
2337
2338 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2339 SI_NUM_SMOOTH_AA_SAMPLES);
2340 }
2341
2342 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2343 {
2344 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2345
2346 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2347 sctx->ps_iter_samples,
2348 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2349 }
2350
2351
2352 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2353 {
2354 struct si_context *sctx = (struct si_context *)ctx;
2355
2356 if (sctx->ps_iter_samples == min_samples)
2357 return;
2358
2359 sctx->ps_iter_samples = min_samples;
2360
2361 if (sctx->framebuffer.nr_samples > 1)
2362 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2363 }
2364
2365 /*
2366 * Samplers
2367 */
2368
2369 /**
2370 * Create a sampler view.
2371 *
2372 * @param ctx context
2373 * @param texture texture
2374 * @param state sampler view template
2375 * @param width0 width0 override (for compressed textures as int)
2376 * @param height0 height0 override (for compressed textures as int)
2377 * @param force_level set the base address to the level (for compressed textures)
2378 */
2379 struct pipe_sampler_view *
2380 si_create_sampler_view_custom(struct pipe_context *ctx,
2381 struct pipe_resource *texture,
2382 const struct pipe_sampler_view *state,
2383 unsigned width0, unsigned height0,
2384 unsigned force_level)
2385 {
2386 struct si_context *sctx = (struct si_context*)ctx;
2387 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2388 struct r600_texture *tmp = (struct r600_texture*)texture;
2389 const struct util_format_description *desc;
2390 unsigned format, num_format, base_level, first_level, last_level;
2391 uint32_t pitch = 0;
2392 unsigned char state_swizzle[4], swizzle[4];
2393 unsigned height, depth, width;
2394 enum pipe_format pipe_format = state->format;
2395 struct radeon_surf_level *surflevel;
2396 int first_non_void;
2397 uint64_t va;
2398
2399 if (view == NULL)
2400 return NULL;
2401
2402 /* initialize base object */
2403 view->base = *state;
2404 view->base.texture = NULL;
2405 view->base.reference.count = 1;
2406 view->base.context = ctx;
2407
2408 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2409 if (!texture) {
2410 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2411 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2412 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2413 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2414 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2415 return &view->base;
2416 }
2417
2418 pipe_resource_reference(&view->base.texture, texture);
2419 view->resource = &tmp->resource;
2420
2421 /* Buffer resource. */
2422 if (texture->target == PIPE_BUFFER) {
2423 unsigned stride, num_records;
2424
2425 desc = util_format_description(state->format);
2426 first_non_void = util_format_get_first_non_void_channel(state->format);
2427 stride = desc->block.bits / 8;
2428 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2429 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2430 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2431
2432 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2433 num_records = MIN2(num_records, texture->width0 / stride);
2434
2435 if (sctx->b.chip_class >= VI)
2436 num_records *= stride;
2437
2438 view->state[4] = va;
2439 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2440 S_008F04_STRIDE(stride);
2441 view->state[6] = num_records;
2442 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2443 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2444 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2445 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2446 S_008F0C_NUM_FORMAT(num_format) |
2447 S_008F0C_DATA_FORMAT(format);
2448
2449 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2450 return &view->base;
2451 }
2452
2453 state_swizzle[0] = state->swizzle_r;
2454 state_swizzle[1] = state->swizzle_g;
2455 state_swizzle[2] = state->swizzle_b;
2456 state_swizzle[3] = state->swizzle_a;
2457
2458 surflevel = tmp->surface.level;
2459
2460 /* Texturing with separate depth and stencil. */
2461 if (tmp->is_depth && !tmp->is_flushing_texture) {
2462 switch (pipe_format) {
2463 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2464 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2465 break;
2466 case PIPE_FORMAT_X8Z24_UNORM:
2467 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2468 /* Z24 is always stored like this. */
2469 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2470 break;
2471 case PIPE_FORMAT_X24S8_UINT:
2472 case PIPE_FORMAT_S8X24_UINT:
2473 case PIPE_FORMAT_X32_S8X24_UINT:
2474 pipe_format = PIPE_FORMAT_S8_UINT;
2475 surflevel = tmp->surface.stencil_level;
2476 break;
2477 default:;
2478 }
2479 }
2480
2481 desc = util_format_description(pipe_format);
2482
2483 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2484 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2485 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2486
2487 switch (pipe_format) {
2488 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2489 case PIPE_FORMAT_X24S8_UINT:
2490 case PIPE_FORMAT_X32_S8X24_UINT:
2491 case PIPE_FORMAT_X8Z24_UNORM:
2492 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2493 break;
2494 default:
2495 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2496 }
2497 } else {
2498 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2499 }
2500
2501 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2502
2503 switch (pipe_format) {
2504 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2505 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2506 break;
2507 default:
2508 if (first_non_void < 0) {
2509 if (util_format_is_compressed(pipe_format)) {
2510 switch (pipe_format) {
2511 case PIPE_FORMAT_DXT1_SRGB:
2512 case PIPE_FORMAT_DXT1_SRGBA:
2513 case PIPE_FORMAT_DXT3_SRGBA:
2514 case PIPE_FORMAT_DXT5_SRGBA:
2515 case PIPE_FORMAT_BPTC_SRGBA:
2516 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2517 break;
2518 case PIPE_FORMAT_RGTC1_SNORM:
2519 case PIPE_FORMAT_LATC1_SNORM:
2520 case PIPE_FORMAT_RGTC2_SNORM:
2521 case PIPE_FORMAT_LATC2_SNORM:
2522 /* implies float, so use SNORM/UNORM to determine
2523 whether data is signed or not */
2524 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2525 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2526 break;
2527 default:
2528 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2529 break;
2530 }
2531 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2532 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2533 } else {
2534 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2535 }
2536 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2537 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2538 } else {
2539 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2540
2541 switch (desc->channel[first_non_void].type) {
2542 case UTIL_FORMAT_TYPE_FLOAT:
2543 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2544 break;
2545 case UTIL_FORMAT_TYPE_SIGNED:
2546 if (desc->channel[first_non_void].normalized)
2547 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2548 else if (desc->channel[first_non_void].pure_integer)
2549 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2550 else
2551 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2552 break;
2553 case UTIL_FORMAT_TYPE_UNSIGNED:
2554 if (desc->channel[first_non_void].normalized)
2555 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2556 else if (desc->channel[first_non_void].pure_integer)
2557 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2558 else
2559 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2560 }
2561 }
2562 }
2563
2564 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2565 if (format == ~0) {
2566 format = 0;
2567 }
2568
2569 base_level = 0;
2570 first_level = state->u.tex.first_level;
2571 last_level = state->u.tex.last_level;
2572 width = width0;
2573 height = height0;
2574 depth = texture->depth0;
2575
2576 if (force_level) {
2577 assert(force_level == first_level &&
2578 force_level == last_level);
2579 base_level = force_level;
2580 first_level = 0;
2581 last_level = 0;
2582 width = u_minify(width, force_level);
2583 height = u_minify(height, force_level);
2584 depth = u_minify(depth, force_level);
2585 }
2586
2587 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2588
2589 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2590 height = 1;
2591 depth = texture->array_size;
2592 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2593 depth = texture->array_size;
2594 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2595 depth = texture->array_size / 6;
2596
2597 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2598
2599 view->state[0] = va >> 8;
2600 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2601 S_008F14_DATA_FORMAT(format) |
2602 S_008F14_NUM_FORMAT(num_format));
2603 view->state[2] = (S_008F18_WIDTH(width - 1) |
2604 S_008F18_HEIGHT(height - 1));
2605 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2606 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2607 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2608 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2609 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2610 0 : first_level) |
2611 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2612 util_logbase2(texture->nr_samples) :
2613 last_level) |
2614 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2615 S_008F1C_POW2_PAD(texture->last_level > 0) |
2616 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2617 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2618 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2619 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2620 view->state[6] = 0;
2621 view->state[7] = 0;
2622
2623 /* Initialize the sampler view for FMASK. */
2624 if (tmp->fmask.size) {
2625 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2626 uint32_t fmask_format;
2627
2628 switch (texture->nr_samples) {
2629 case 2:
2630 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2631 break;
2632 case 4:
2633 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2634 break;
2635 case 8:
2636 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2637 break;
2638 default:
2639 assert(0);
2640 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2641 }
2642
2643 view->fmask_state[0] = va >> 8;
2644 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2645 S_008F14_DATA_FORMAT(fmask_format) |
2646 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2647 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2648 S_008F18_HEIGHT(height - 1);
2649 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2650 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2651 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2652 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2653 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2654 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2655 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2656 S_008F20_PITCH(tmp->fmask.pitch - 1);
2657 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2658 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2659 view->fmask_state[6] = 0;
2660 view->fmask_state[7] = 0;
2661 }
2662
2663 return &view->base;
2664 }
2665
2666 static struct pipe_sampler_view *
2667 si_create_sampler_view(struct pipe_context *ctx,
2668 struct pipe_resource *texture,
2669 const struct pipe_sampler_view *state)
2670 {
2671 return si_create_sampler_view_custom(ctx, texture, state,
2672 texture ? texture->width0 : 0,
2673 texture ? texture->height0 : 0, 0);
2674 }
2675
2676 static void si_sampler_view_destroy(struct pipe_context *ctx,
2677 struct pipe_sampler_view *state)
2678 {
2679 struct si_sampler_view *view = (struct si_sampler_view *)state;
2680
2681 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2682 LIST_DELINIT(&view->list);
2683
2684 pipe_resource_reference(&state->texture, NULL);
2685 FREE(view);
2686 }
2687
2688 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2689 {
2690 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2691 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2692 (linear_filter &&
2693 (wrap == PIPE_TEX_WRAP_CLAMP ||
2694 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2695 }
2696
2697 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2698 {
2699 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2700 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2701
2702 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2703 state->border_color.ui[2] || state->border_color.ui[3]) &&
2704 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2705 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2706 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2707 }
2708
2709 static void *si_create_sampler_state(struct pipe_context *ctx,
2710 const struct pipe_sampler_state *state)
2711 {
2712 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2713 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2714 unsigned border_color_type;
2715
2716 if (rstate == NULL) {
2717 return NULL;
2718 }
2719
2720 if (sampler_state_needs_border_color(state))
2721 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2722 else
2723 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2724
2725 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2726 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2727 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2728 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2729 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2730 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2731 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2732 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2733 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2734 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2735 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2736 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2737 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2738 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2739
2740 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2741 memcpy(rstate->border_color, state->border_color.ui,
2742 sizeof(rstate->border_color));
2743 }
2744
2745 return rstate;
2746 }
2747
2748 /* Upload border colors and update the pointers in resource descriptors.
2749 * There can only be 4096 border colors per context.
2750 *
2751 * XXX: This is broken if the buffer gets reallocated.
2752 */
2753 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2754 void **states)
2755 {
2756 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2757 uint32_t *border_color_table = NULL;
2758 int i, j;
2759
2760 for (i = 0; i < count; i++) {
2761 if (rstates[i] &&
2762 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2763 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2764 if (!sctx->border_color_table ||
2765 ((sctx->border_color_offset + count - i) &
2766 C_008F3C_BORDER_COLOR_PTR)) {
2767 r600_resource_reference(&sctx->border_color_table, NULL);
2768 sctx->border_color_offset = 0;
2769
2770 sctx->border_color_table =
2771 si_resource_create_custom(&sctx->screen->b.b,
2772 PIPE_USAGE_DYNAMIC,
2773 4096 * 4 * 4);
2774 }
2775
2776 if (!border_color_table) {
2777 border_color_table =
2778 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2779 sctx->b.rings.gfx.cs,
2780 PIPE_TRANSFER_WRITE |
2781 PIPE_TRANSFER_UNSYNCHRONIZED);
2782 }
2783
2784 for (j = 0; j < 4; j++) {
2785 border_color_table[4 * sctx->border_color_offset + j] =
2786 util_le32_to_cpu(rstates[i]->border_color[j]);
2787 }
2788
2789 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2790 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2791 }
2792 }
2793
2794 if (border_color_table) {
2795 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2796
2797 uint64_t va_offset = sctx->border_color_table->gpu_address;
2798
2799 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2800 if (sctx->b.chip_class >= CIK)
2801 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2802 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2803 RADEON_PRIO_SHADER_DATA);
2804 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2805 }
2806 }
2807
2808 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2809 unsigned start, unsigned count,
2810 void **states)
2811 {
2812 struct si_context *sctx = (struct si_context *)ctx;
2813
2814 if (!count || shader >= SI_NUM_SHADERS)
2815 return;
2816
2817 si_set_border_colors(sctx, count, states);
2818 si_set_sampler_descriptors(sctx, shader, start, count, states);
2819 }
2820
2821 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2822 {
2823 struct si_context *sctx = (struct si_context *)ctx;
2824
2825 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2826 return;
2827
2828 sctx->sample_mask.sample_mask = sample_mask;
2829 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2830 }
2831
2832 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2833 {
2834 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2835 unsigned mask = sctx->sample_mask.sample_mask;
2836
2837 r600_write_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2838 radeon_emit(cs, mask | (mask << 16));
2839 radeon_emit(cs, mask | (mask << 16));
2840 }
2841
2842 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2843 {
2844 free(state);
2845 }
2846
2847 /*
2848 * Vertex elements & buffers
2849 */
2850
2851 static void *si_create_vertex_elements(struct pipe_context *ctx,
2852 unsigned count,
2853 const struct pipe_vertex_element *elements)
2854 {
2855 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2856 int i;
2857
2858 assert(count < SI_MAX_ATTRIBS);
2859 if (!v)
2860 return NULL;
2861
2862 v->count = count;
2863 for (i = 0; i < count; ++i) {
2864 const struct util_format_description *desc;
2865 unsigned data_format, num_format;
2866 int first_non_void;
2867
2868 desc = util_format_description(elements[i].src_format);
2869 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2870 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2871 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2872
2873 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2874 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2875 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2876 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2877 S_008F0C_NUM_FORMAT(num_format) |
2878 S_008F0C_DATA_FORMAT(data_format);
2879 v->format_size[i] = desc->block.bits / 8;
2880 }
2881 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2882
2883 return v;
2884 }
2885
2886 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2887 {
2888 struct si_context *sctx = (struct si_context *)ctx;
2889 struct si_vertex_element *v = (struct si_vertex_element*)state;
2890
2891 sctx->vertex_elements = v;
2892 sctx->vertex_buffers_dirty = true;
2893 }
2894
2895 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2896 {
2897 struct si_context *sctx = (struct si_context *)ctx;
2898
2899 if (sctx->vertex_elements == state)
2900 sctx->vertex_elements = NULL;
2901 FREE(state);
2902 }
2903
2904 static void si_set_vertex_buffers(struct pipe_context *ctx,
2905 unsigned start_slot, unsigned count,
2906 const struct pipe_vertex_buffer *buffers)
2907 {
2908 struct si_context *sctx = (struct si_context *)ctx;
2909 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2910 int i;
2911
2912 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2913
2914 if (buffers) {
2915 for (i = 0; i < count; i++) {
2916 const struct pipe_vertex_buffer *src = buffers + i;
2917 struct pipe_vertex_buffer *dsti = dst + i;
2918
2919 pipe_resource_reference(&dsti->buffer, src->buffer);
2920 dsti->buffer_offset = src->buffer_offset;
2921 dsti->stride = src->stride;
2922 r600_context_add_resource_size(ctx, src->buffer);
2923 }
2924 } else {
2925 for (i = 0; i < count; i++) {
2926 pipe_resource_reference(&dst[i].buffer, NULL);
2927 }
2928 }
2929 sctx->vertex_buffers_dirty = true;
2930 }
2931
2932 static void si_set_index_buffer(struct pipe_context *ctx,
2933 const struct pipe_index_buffer *ib)
2934 {
2935 struct si_context *sctx = (struct si_context *)ctx;
2936
2937 if (ib) {
2938 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2939 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2940 r600_context_add_resource_size(ctx, ib->buffer);
2941 } else {
2942 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2943 }
2944 }
2945
2946 /*
2947 * Misc
2948 */
2949 static void si_set_polygon_stipple(struct pipe_context *ctx,
2950 const struct pipe_poly_stipple *state)
2951 {
2952 struct si_context *sctx = (struct si_context *)ctx;
2953 struct pipe_resource *tex;
2954 struct pipe_sampler_view *view;
2955 bool is_zero = true;
2956 bool is_one = true;
2957 int i;
2958
2959 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2960 * the resource is NULL/invalid. Take advantage of this fact and skip
2961 * texture allocation if the stipple pattern is constant.
2962 *
2963 * This is an optimization for the common case when stippling isn't
2964 * used but set_polygon_stipple is still called by st/mesa.
2965 */
2966 for (i = 0; i < Elements(state->stipple); i++) {
2967 is_zero = is_zero && state->stipple[i] == 0;
2968 is_one = is_one && state->stipple[i] == 0xffffffff;
2969 }
2970
2971 if (is_zero || is_one) {
2972 struct pipe_sampler_view templ = {{0}};
2973
2974 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2975 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2976 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2977 /* The pattern should be inverted in the texture. */
2978 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2979
2980 view = ctx->create_sampler_view(ctx, NULL, &templ);
2981 } else {
2982 /* Create a new texture. */
2983 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2984 if (!tex)
2985 return;
2986
2987 view = util_pstipple_create_sampler_view(ctx, tex);
2988 pipe_resource_reference(&tex, NULL);
2989 }
2990
2991 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2992 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2993 pipe_sampler_view_reference(&view, NULL);
2994
2995 /* Bind the sampler state if needed. */
2996 if (!sctx->pstipple_sampler_state) {
2997 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2998 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2999 SI_POLY_STIPPLE_SAMPLER, 1,
3000 &sctx->pstipple_sampler_state);
3001 }
3002 }
3003
3004 static void si_set_tess_state(struct pipe_context *ctx,
3005 const float default_outer_level[4],
3006 const float default_inner_level[2])
3007 {
3008 struct si_context *sctx = (struct si_context *)ctx;
3009 struct pipe_constant_buffer cb;
3010 float array[8];
3011
3012 memcpy(array, default_outer_level, sizeof(float) * 4);
3013 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3014
3015 cb.buffer = NULL;
3016 cb.user_buffer = NULL;
3017 cb.buffer_size = sizeof(array);
3018
3019 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3020 (void*)array, sizeof(array),
3021 &cb.buffer_offset);
3022
3023 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3024 SI_DRIVER_STATE_CONST_BUF, &cb);
3025 pipe_resource_reference(&cb.buffer, NULL);
3026 }
3027
3028 static void si_texture_barrier(struct pipe_context *ctx)
3029 {
3030 struct si_context *sctx = (struct si_context *)ctx;
3031
3032 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3033 SI_CONTEXT_INV_TC_L2 |
3034 SI_CONTEXT_FLUSH_AND_INV_CB;
3035 }
3036
3037 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3038 {
3039 struct pipe_blend_state blend;
3040
3041 memset(&blend, 0, sizeof(blend));
3042 blend.independent_blend_enable = true;
3043 blend.rt[0].colormask = 0xf;
3044 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3045 }
3046
3047 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3048 bool include_draw_vbo)
3049 {
3050 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3051 }
3052
3053 static void si_init_config(struct si_context *sctx);
3054
3055 void si_init_state_functions(struct si_context *sctx)
3056 {
3057 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3058 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3059
3060 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush, 24);
3061 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
3062 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs, 18);
3063 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
3064 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config, 10);
3065 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask, 4);
3066 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color, 6);
3067 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
3068 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state, 2+6*4);
3069 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors, 16*4);
3070 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports, 16*8);
3071 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref, 4);
3072
3073 sctx->b.b.create_blend_state = si_create_blend_state;
3074 sctx->b.b.bind_blend_state = si_bind_blend_state;
3075 sctx->b.b.delete_blend_state = si_delete_blend_state;
3076 sctx->b.b.set_blend_color = si_set_blend_color;
3077
3078 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3079 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3080 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3081
3082 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3083 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3084 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3085
3086 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3087 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3088 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3089 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3090
3091 sctx->b.b.set_clip_state = si_set_clip_state;
3092 sctx->b.b.set_scissor_states = si_set_scissor_states;
3093 sctx->b.b.set_viewport_states = si_set_viewport_states;
3094 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3095
3096 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3097 sctx->b.b.get_sample_position = cayman_get_sample_position;
3098
3099 sctx->b.b.create_sampler_state = si_create_sampler_state;
3100 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3101 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3102
3103 sctx->b.b.create_sampler_view = si_create_sampler_view;
3104 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3105
3106 sctx->b.b.set_sample_mask = si_set_sample_mask;
3107
3108 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3109 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3110 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3111 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3112 sctx->b.b.set_index_buffer = si_set_index_buffer;
3113
3114 sctx->b.b.texture_barrier = si_texture_barrier;
3115 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3116 sctx->b.b.set_min_samples = si_set_min_samples;
3117 sctx->b.b.set_tess_state = si_set_tess_state;
3118
3119 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3120 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3121
3122 sctx->b.b.draw_vbo = si_draw_vbo;
3123
3124 if (sctx->b.chip_class >= CIK) {
3125 sctx->b.dma_copy = cik_sdma_copy;
3126 } else {
3127 sctx->b.dma_copy = si_dma_copy;
3128 }
3129
3130 si_init_config(sctx);
3131 }
3132
3133 static void
3134 si_write_harvested_raster_configs(struct si_context *sctx,
3135 struct si_pm4_state *pm4,
3136 unsigned raster_config,
3137 unsigned raster_config_1)
3138 {
3139 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3140 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3141 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3142 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3143 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3144 unsigned rb_per_se = num_rb / num_se;
3145 unsigned se_mask[4];
3146 unsigned se;
3147
3148 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3149 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3150 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3151 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3152
3153 assert(num_se == 1 || num_se == 2 || num_se == 4);
3154 assert(sh_per_se == 1 || sh_per_se == 2);
3155 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3156
3157 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3158 * fields are for, so I'm leaving them as their default
3159 * values. */
3160
3161 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3162 (!se_mask[2] && !se_mask[3]))) {
3163 raster_config_1 &= C_028354_SE_PAIR_MAP;
3164
3165 if (!se_mask[0] && !se_mask[1]) {
3166 raster_config_1 |=
3167 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3168 } else {
3169 raster_config_1 |=
3170 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3171 }
3172 }
3173
3174 for (se = 0; se < num_se; se++) {
3175 unsigned raster_config_se = raster_config;
3176 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3177 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3178 int idx = (se / 2) * 2;
3179
3180 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3181 raster_config_se &= C_028350_SE_MAP;
3182
3183 if (!se_mask[idx]) {
3184 raster_config_se |=
3185 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3186 } else {
3187 raster_config_se |=
3188 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3189 }
3190 }
3191
3192 pkr0_mask &= rb_mask;
3193 pkr1_mask &= rb_mask;
3194 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3195 raster_config_se &= C_028350_PKR_MAP;
3196
3197 if (!pkr0_mask) {
3198 raster_config_se |=
3199 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3200 } else {
3201 raster_config_se |=
3202 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3203 }
3204 }
3205
3206 if (rb_per_se >= 2) {
3207 unsigned rb0_mask = 1 << (se * rb_per_se);
3208 unsigned rb1_mask = rb0_mask << 1;
3209
3210 rb0_mask &= rb_mask;
3211 rb1_mask &= rb_mask;
3212 if (!rb0_mask || !rb1_mask) {
3213 raster_config_se &= C_028350_RB_MAP_PKR0;
3214
3215 if (!rb0_mask) {
3216 raster_config_se |=
3217 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3218 } else {
3219 raster_config_se |=
3220 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3221 }
3222 }
3223
3224 if (rb_per_se > 2) {
3225 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3226 rb1_mask = rb0_mask << 1;
3227 rb0_mask &= rb_mask;
3228 rb1_mask &= rb_mask;
3229 if (!rb0_mask || !rb1_mask) {
3230 raster_config_se &= C_028350_RB_MAP_PKR1;
3231
3232 if (!rb0_mask) {
3233 raster_config_se |=
3234 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3235 } else {
3236 raster_config_se |=
3237 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3238 }
3239 }
3240 }
3241 }
3242
3243 /* GRBM_GFX_INDEX is privileged on VI */
3244 if (sctx->b.chip_class <= CIK)
3245 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3246 SE_INDEX(se) | SH_BROADCAST_WRITES |
3247 INSTANCE_BROADCAST_WRITES);
3248 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3249 if (sctx->b.chip_class >= CIK)
3250 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3251 }
3252
3253 /* GRBM_GFX_INDEX is privileged on VI */
3254 if (sctx->b.chip_class <= CIK)
3255 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3256 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3257 INSTANCE_BROADCAST_WRITES);
3258 }
3259
3260 static void si_init_config(struct si_context *sctx)
3261 {
3262 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3263 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3264 unsigned raster_config, raster_config_1;
3265 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3266 int i;
3267
3268 if (pm4 == NULL)
3269 return;
3270
3271 si_cmd_context_control(pm4);
3272
3273 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3274 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3275
3276 /* FIXME calculate these values somehow ??? */
3277 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3278 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3279 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3280
3281 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3282 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3283
3284 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3285 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3286 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3287 if (sctx->b.chip_class < CIK)
3288 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3289 S_008A14_CLIP_VTX_REORDER_ENA(1));
3290
3291 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3292 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3293
3294 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3295
3296 for (i = 0; i < 16; i++) {
3297 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3298 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3299 }
3300
3301 switch (sctx->screen->b.family) {
3302 case CHIP_TAHITI:
3303 case CHIP_PITCAIRN:
3304 raster_config = 0x2a00126a;
3305 raster_config_1 = 0x00000000;
3306 break;
3307 case CHIP_VERDE:
3308 raster_config = 0x0000124a;
3309 raster_config_1 = 0x00000000;
3310 break;
3311 case CHIP_OLAND:
3312 raster_config = 0x00000082;
3313 raster_config_1 = 0x00000000;
3314 break;
3315 case CHIP_HAINAN:
3316 raster_config = 0x00000000;
3317 raster_config_1 = 0x00000000;
3318 break;
3319 case CHIP_BONAIRE:
3320 raster_config = 0x16000012;
3321 raster_config_1 = 0x00000000;
3322 break;
3323 case CHIP_HAWAII:
3324 raster_config = 0x3a00161a;
3325 raster_config_1 = 0x0000002e;
3326 break;
3327 case CHIP_FIJI:
3328 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3329 raster_config = 0x16000012; /* 0x3a00161a */
3330 raster_config_1 = 0x0000002a; /* 0x0000002e */
3331 break;
3332 case CHIP_TONGA:
3333 raster_config = 0x16000012;
3334 raster_config_1 = 0x0000002a;
3335 break;
3336 case CHIP_ICELAND:
3337 raster_config = 0x00000002;
3338 raster_config_1 = 0x00000000;
3339 break;
3340 case CHIP_CARRIZO:
3341 raster_config = 0x00000002;
3342 raster_config_1 = 0x00000000;
3343 break;
3344 case CHIP_KAVERI:
3345 /* KV should be 0x00000002, but that causes problems with radeon */
3346 raster_config = 0x00000000; /* 0x00000002 */
3347 raster_config_1 = 0x00000000;
3348 break;
3349 case CHIP_KABINI:
3350 case CHIP_MULLINS:
3351 raster_config = 0x00000000;
3352 raster_config_1 = 0x00000000;
3353 break;
3354 default:
3355 fprintf(stderr,
3356 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3357 raster_config = 0x00000000;
3358 raster_config_1 = 0x00000000;
3359 break;
3360 }
3361
3362 /* Always use the default config when all backends are enabled
3363 * (or when we failed to determine the enabled backends).
3364 */
3365 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3366 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3367 raster_config);
3368 if (sctx->b.chip_class >= CIK)
3369 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3370 raster_config_1);
3371 } else {
3372 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3373 }
3374
3375 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3376 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3377 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3378 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3379 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3380 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3381 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3382
3383 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3384 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3385 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3386 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3387 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3388 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3389 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3390 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3391 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3392 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3393 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3394 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3395 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3396
3397 /* There is a hang if stencil is used and fast stencil is enabled
3398 * regardless of whether HTILE is depth-only or not.
3399 */
3400 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3401 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3402 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3403 S_02800C_FAST_STENCIL_DISABLE(1));
3404
3405 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3406 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3407 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3408
3409 if (sctx->b.chip_class >= CIK) {
3410 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3411 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3412 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3413 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3414 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3415 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3416 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3417 }
3418
3419 if (sctx->b.chip_class >= VI) {
3420 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3421 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3422 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3423 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3424 }
3425
3426 sctx->init_config = pm4;
3427 }