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radeonsi: add drirc option "radeonsi_assume_no_z_fights"
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x)
79 {
80 return x <= 0 ? 0 :
81 x >= 4096 ? 0xffff : x * 16;
82 }
83
84 /*
85 * Inferred framebuffer and blender state.
86 *
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
89 */
90 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
91 {
92 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
93 struct si_state_blend *blend = sctx->queued.named.blend;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
97 unsigned i;
98
99 if (blend)
100 cb_target_mask &= blend->cb_target_mask;
101
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
105 *
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
107 */
108 if (blend && blend->dual_src_blend &&
109 sctx->ps_shader.cso &&
110 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
111 cb_target_mask = 0;
112
113 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
114
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
117 */
118 if (sctx->screen->dfsm_allowed &&
119 sctx->last_cb_target_mask != cb_target_mask) {
120 sctx->last_cb_target_mask = cb_target_mask;
121
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->b.rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx->screen->b.has_rbplus) {
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 }
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 R600_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 /**
381 * Get rid of DST in the blend factors by commuting the operands:
382 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
383 */
384 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
385 unsigned *dst_factor, unsigned expected_dst,
386 unsigned replacement_src)
387 {
388 if (*src_factor == expected_dst &&
389 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
390 *src_factor = PIPE_BLENDFACTOR_ZERO;
391 *dst_factor = replacement_src;
392
393 /* Commuting the operands requires reversing subtractions. */
394 if (*func == PIPE_BLEND_SUBTRACT)
395 *func = PIPE_BLEND_REVERSE_SUBTRACT;
396 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
397 *func = PIPE_BLEND_SUBTRACT;
398 }
399 }
400
401 static bool si_blend_factor_uses_dst(unsigned factor)
402 {
403 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
404 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
405 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
406 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
407 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
408 }
409
410 static void *si_create_blend_state_mode(struct pipe_context *ctx,
411 const struct pipe_blend_state *state,
412 unsigned mode)
413 {
414 struct si_context *sctx = (struct si_context*)ctx;
415 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
416 struct si_pm4_state *pm4 = &blend->pm4;
417 uint32_t sx_mrt_blend_opt[8] = {0};
418 uint32_t color_control = 0;
419
420 if (!blend)
421 return NULL;
422
423 blend->alpha_to_coverage = state->alpha_to_coverage;
424 blend->alpha_to_one = state->alpha_to_one;
425 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
426 blend->logicop_enable = state->logicop_enable;
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 blend->cb_target_enabled_4bit = 0;
446
447 for (int i = 0; i < 8; i++) {
448 /* state->rt entries > 0 only written if independent blending */
449 const int j = state->independent_blend_enable ? i : 0;
450
451 unsigned eqRGB = state->rt[j].rgb_func;
452 unsigned srcRGB = state->rt[j].rgb_src_factor;
453 unsigned dstRGB = state->rt[j].rgb_dst_factor;
454 unsigned eqA = state->rt[j].alpha_func;
455 unsigned srcA = state->rt[j].alpha_src_factor;
456 unsigned dstA = state->rt[j].alpha_dst_factor;
457
458 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
459 unsigned blend_cntl = 0;
460
461 sx_mrt_blend_opt[i] =
462 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
463 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
464
465 /* Only set dual source blending for MRT0 to avoid a hang. */
466 if (i >= 1 && blend->dual_src_blend) {
467 /* Vulkan does this for dual source blending. */
468 if (i == 1)
469 blend_cntl |= S_028780_ENABLE(1);
470
471 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
472 continue;
473 }
474
475 /* Only addition and subtraction equations are supported with
476 * dual source blending.
477 */
478 if (blend->dual_src_blend &&
479 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
480 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
481 assert(!"Unsupported equation for dual source blending");
482 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
483 continue;
484 }
485
486 /* cb_render_state will disable unused ones */
487 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
488 if (state->rt[j].colormask)
489 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 struct si_state_blend *old_blend = sctx->queued.named.blend;
607 struct si_state_blend *blend = (struct si_state_blend *)state;
608
609 if (!state)
610 return;
611
612 if (!old_blend ||
613 old_blend->cb_target_mask != blend->cb_target_mask ||
614 old_blend->dual_src_blend != blend->dual_src_blend)
615 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
616
617 si_pm4_bind_state(sctx, blend, state);
618
619 if (!old_blend ||
620 old_blend->cb_target_mask != blend->cb_target_mask ||
621 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
622 old_blend->alpha_to_one != blend->alpha_to_one ||
623 old_blend->dual_src_blend != blend->dual_src_blend ||
624 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
625 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
626 sctx->do_update_shaders = true;
627
628 if (sctx->screen->dpbb_allowed &&
629 (!old_blend ||
630 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
631 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
632 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
633 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
634
635 if (sctx->screen->has_out_of_order_rast &&
636 (!old_blend ||
637 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
638 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
639 old_blend->logicop_enable != blend->logicop_enable)))
640 si_mark_atom_dirty(sctx, &sctx->msaa_config);
641 }
642
643 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
647 }
648
649 static void si_set_blend_color(struct pipe_context *ctx,
650 const struct pipe_blend_color *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 static const struct pipe_blend_color zeros;
654
655 sctx->blend_color.state = *state;
656 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
657 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
658 }
659
660 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
661 {
662 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
663
664 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
665 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
666 }
667
668 /*
669 * Clipping
670 */
671
672 static void si_set_clip_state(struct pipe_context *ctx,
673 const struct pipe_clip_state *state)
674 {
675 struct si_context *sctx = (struct si_context *)ctx;
676 struct pipe_constant_buffer cb;
677 static const struct pipe_clip_state zeros;
678
679 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
680 return;
681
682 sctx->clip_state.state = *state;
683 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
684 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
685
686 cb.buffer = NULL;
687 cb.user_buffer = state->ucp;
688 cb.buffer_offset = 0;
689 cb.buffer_size = 4*4*8;
690 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
691 pipe_resource_reference(&cb.buffer, NULL);
692 }
693
694 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
695 {
696 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
697
698 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
699 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
700 }
701
702 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
703 {
704 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
705 struct si_shader *vs = si_get_vs_state(sctx);
706 struct si_shader_selector *vs_sel = vs->selector;
707 struct tgsi_shader_info *info = &vs_sel->info;
708 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
709 unsigned window_space =
710 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
711 unsigned clipdist_mask = vs_sel->clipdist_mask;
712 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
713 unsigned culldist_mask = vs_sel->culldist_mask;
714 unsigned total_mask;
715
716 if (vs->key.opt.clip_disable) {
717 assert(!info->culldist_writemask);
718 clipdist_mask = 0;
719 culldist_mask = 0;
720 }
721 total_mask = clipdist_mask | culldist_mask;
722
723 /* Clip distances on points have no effect, so need to be implemented
724 * as cull distances. This applies for the clipvertex case as well.
725 *
726 * Setting this for primitives other than points should have no adverse
727 * effects.
728 */
729 clipdist_mask &= rs->clip_plane_enable;
730 culldist_mask |= clipdist_mask;
731
732 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
733 vs_sel->pa_cl_vs_out_cntl |
734 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
735 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
736 clipdist_mask | (culldist_mask << 8));
737 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
738 rs->pa_cl_clip_cntl |
739 ucp_mask |
740 S_028810_CLIP_DISABLE(window_space));
741 }
742
743 /*
744 * inferred state between framebuffer and rasterizer
745 */
746 static void si_update_poly_offset_state(struct si_context *sctx)
747 {
748 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
749
750 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
751 si_pm4_bind_state(sctx, poly_offset, NULL);
752 return;
753 }
754
755 /* Use the user format, not db_render_format, so that the polygon
756 * offset behaves as expected by applications.
757 */
758 switch (sctx->framebuffer.state.zsbuf->texture->format) {
759 case PIPE_FORMAT_Z16_UNORM:
760 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
761 break;
762 default: /* 24-bit */
763 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
764 break;
765 case PIPE_FORMAT_Z32_FLOAT:
766 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
767 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
768 break;
769 }
770 }
771
772 /*
773 * Rasterizer
774 */
775
776 static uint32_t si_translate_fill(uint32_t func)
777 {
778 switch(func) {
779 case PIPE_POLYGON_MODE_FILL:
780 return V_028814_X_DRAW_TRIANGLES;
781 case PIPE_POLYGON_MODE_LINE:
782 return V_028814_X_DRAW_LINES;
783 case PIPE_POLYGON_MODE_POINT:
784 return V_028814_X_DRAW_POINTS;
785 default:
786 assert(0);
787 return V_028814_X_DRAW_POINTS;
788 }
789 }
790
791 static void *si_create_rs_state(struct pipe_context *ctx,
792 const struct pipe_rasterizer_state *state)
793 {
794 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
795 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
796 struct si_pm4_state *pm4 = &rs->pm4;
797 unsigned tmp, i;
798 float psize_min, psize_max;
799
800 if (!rs) {
801 return NULL;
802 }
803
804 rs->scissor_enable = state->scissor;
805 rs->clip_halfz = state->clip_halfz;
806 rs->two_side = state->light_twoside;
807 rs->multisample_enable = state->multisample;
808 rs->force_persample_interp = state->force_persample_interp;
809 rs->clip_plane_enable = state->clip_plane_enable;
810 rs->line_stipple_enable = state->line_stipple_enable;
811 rs->poly_stipple_enable = state->poly_stipple_enable;
812 rs->line_smooth = state->line_smooth;
813 rs->poly_smooth = state->poly_smooth;
814 rs->uses_poly_offset = state->offset_point || state->offset_line ||
815 state->offset_tri;
816 rs->clamp_fragment_color = state->clamp_fragment_color;
817 rs->clamp_vertex_color = state->clamp_vertex_color;
818 rs->flatshade = state->flatshade;
819 rs->sprite_coord_enable = state->sprite_coord_enable;
820 rs->rasterizer_discard = state->rasterizer_discard;
821 rs->pa_sc_line_stipple = state->line_stipple_enable ?
822 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
823 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
824 rs->pa_cl_clip_cntl =
825 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
826 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
827 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
828 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
829 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
830
831 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
832 S_0286D4_FLAT_SHADE_ENA(1) |
833 S_0286D4_PNT_SPRITE_ENA(1) |
834 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
835 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
836 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
837 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
838 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
839
840 /* point size 12.4 fixed point */
841 tmp = (unsigned)(state->point_size * 8.0);
842 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
843
844 if (state->point_size_per_vertex) {
845 psize_min = util_get_min_point_size(state);
846 psize_max = 8192;
847 } else {
848 /* Force the point size to be as if the vertex output was disabled. */
849 psize_min = state->point_size;
850 psize_max = state->point_size;
851 }
852 /* Divide by two, because 0.5 = 1 pixel. */
853 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
854 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
855 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
856
857 tmp = (unsigned)state->line_width * 8;
858 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
859 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
860 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
861 S_028A48_MSAA_ENABLE(state->multisample ||
862 state->poly_smooth ||
863 state->line_smooth) |
864 S_028A48_VPORT_SCISSOR_ENABLE(1) |
865 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
866
867 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
868 S_028BE4_PIX_CENTER(state->half_pixel_center) |
869 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
870
871 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
872 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
873 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
874 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
875 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
876 S_028814_FACE(!state->front_ccw) |
877 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
878 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
879 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
880 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
881 state->fill_back != PIPE_POLYGON_MODE_FILL) |
882 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
883 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
884
885 if (!rs->uses_poly_offset)
886 return rs;
887
888 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
889 if (!rs->pm4_poly_offset) {
890 FREE(rs);
891 return NULL;
892 }
893
894 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
895 for (i = 0; i < 3; i++) {
896 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
897 float offset_units = state->offset_units;
898 float offset_scale = state->offset_scale * 16.0f;
899 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
900
901 if (!state->offset_units_unscaled) {
902 switch (i) {
903 case 0: /* 16-bit zbuffer */
904 offset_units *= 4.0f;
905 pa_su_poly_offset_db_fmt_cntl =
906 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
907 break;
908 case 1: /* 24-bit zbuffer */
909 offset_units *= 2.0f;
910 pa_su_poly_offset_db_fmt_cntl =
911 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
912 break;
913 case 2: /* 32-bit zbuffer */
914 offset_units *= 1.0f;
915 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
916 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
917 break;
918 }
919 }
920
921 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
922 fui(offset_scale));
923 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
924 fui(offset_units));
925 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
926 fui(offset_scale));
927 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
928 fui(offset_units));
929 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
930 pa_su_poly_offset_db_fmt_cntl);
931 }
932
933 return rs;
934 }
935
936 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
937 {
938 struct si_context *sctx = (struct si_context *)ctx;
939 struct si_state_rasterizer *old_rs =
940 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
941 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
942
943 if (!state)
944 return;
945
946 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
947 si_mark_atom_dirty(sctx, &sctx->db_render_state);
948
949 /* Update the small primitive filter workaround if necessary. */
950 if (sctx->screen->has_msaa_sample_loc_bug &&
951 sctx->framebuffer.nr_samples > 1)
952 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
953 }
954
955 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
956 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
957
958 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
959
960 si_pm4_bind_state(sctx, rasterizer, rs);
961 si_update_poly_offset_state(sctx);
962
963 if (!old_rs ||
964 old_rs->clip_plane_enable != rs->clip_plane_enable ||
965 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
966 si_mark_atom_dirty(sctx, &sctx->clip_regs);
967
968 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
969 rs->line_stipple_enable;
970
971 if (!old_rs ||
972 old_rs->clip_plane_enable != rs->clip_plane_enable ||
973 old_rs->rasterizer_discard != rs->rasterizer_discard ||
974 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
975 old_rs->flatshade != rs->flatshade ||
976 old_rs->two_side != rs->two_side ||
977 old_rs->multisample_enable != rs->multisample_enable ||
978 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
979 old_rs->poly_smooth != rs->poly_smooth ||
980 old_rs->line_smooth != rs->line_smooth ||
981 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
982 old_rs->force_persample_interp != rs->force_persample_interp)
983 sctx->do_update_shaders = true;
984 }
985
986 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
987 {
988 struct si_context *sctx = (struct si_context *)ctx;
989 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
990
991 if (sctx->queued.named.rasterizer == state)
992 si_pm4_bind_state(sctx, poly_offset, NULL);
993
994 FREE(rs->pm4_poly_offset);
995 si_pm4_delete_state(sctx, rasterizer, rs);
996 }
997
998 /*
999 * infeered state between dsa and stencil ref
1000 */
1001 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1002 {
1003 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1004 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1005 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1006
1007 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1008 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1009 S_028430_STENCILMASK(dsa->valuemask[0]) |
1010 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1011 S_028430_STENCILOPVAL(1));
1012 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1013 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1014 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1015 S_028434_STENCILOPVAL_BF(1));
1016 }
1017
1018 static void si_set_stencil_ref(struct pipe_context *ctx,
1019 const struct pipe_stencil_ref *state)
1020 {
1021 struct si_context *sctx = (struct si_context *)ctx;
1022
1023 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1024 return;
1025
1026 sctx->stencil_ref.state = *state;
1027 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1028 }
1029
1030
1031 /*
1032 * DSA
1033 */
1034
1035 static uint32_t si_translate_stencil_op(int s_op)
1036 {
1037 switch (s_op) {
1038 case PIPE_STENCIL_OP_KEEP:
1039 return V_02842C_STENCIL_KEEP;
1040 case PIPE_STENCIL_OP_ZERO:
1041 return V_02842C_STENCIL_ZERO;
1042 case PIPE_STENCIL_OP_REPLACE:
1043 return V_02842C_STENCIL_REPLACE_TEST;
1044 case PIPE_STENCIL_OP_INCR:
1045 return V_02842C_STENCIL_ADD_CLAMP;
1046 case PIPE_STENCIL_OP_DECR:
1047 return V_02842C_STENCIL_SUB_CLAMP;
1048 case PIPE_STENCIL_OP_INCR_WRAP:
1049 return V_02842C_STENCIL_ADD_WRAP;
1050 case PIPE_STENCIL_OP_DECR_WRAP:
1051 return V_02842C_STENCIL_SUB_WRAP;
1052 case PIPE_STENCIL_OP_INVERT:
1053 return V_02842C_STENCIL_INVERT;
1054 default:
1055 R600_ERR("Unknown stencil op %d", s_op);
1056 assert(0);
1057 break;
1058 }
1059 return 0;
1060 }
1061
1062 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1063 {
1064 return s->enabled && s->writemask &&
1065 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1066 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1067 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1068 }
1069
1070 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1071 {
1072 /* REPLACE is normally order invariant, except when the stencil
1073 * reference value is written by the fragment shader. Tracking this
1074 * interaction does not seem worth the effort, so be conservative. */
1075 return op != PIPE_STENCIL_OP_INCR &&
1076 op != PIPE_STENCIL_OP_DECR &&
1077 op != PIPE_STENCIL_OP_REPLACE;
1078 }
1079
1080 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1081 * invariant in the sense that the set of passing fragments as well as the
1082 * final stencil buffer result does not depend on the order of fragments. */
1083 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1084 {
1085 return !state->enabled || !state->writemask ||
1086 /* The following assumes that Z writes are disabled. */
1087 (state->func == PIPE_FUNC_ALWAYS &&
1088 si_order_invariant_stencil_op(state->zpass_op) &&
1089 si_order_invariant_stencil_op(state->zfail_op)) ||
1090 (state->func == PIPE_FUNC_NEVER &&
1091 si_order_invariant_stencil_op(state->fail_op));
1092 }
1093
1094 static void *si_create_dsa_state(struct pipe_context *ctx,
1095 const struct pipe_depth_stencil_alpha_state *state)
1096 {
1097 struct si_context *sctx = (struct si_context *)ctx;
1098 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1099 struct si_pm4_state *pm4 = &dsa->pm4;
1100 unsigned db_depth_control;
1101 uint32_t db_stencil_control = 0;
1102
1103 if (!dsa) {
1104 return NULL;
1105 }
1106
1107 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1108 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1109 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1110 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1111
1112 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1113 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1114 S_028800_ZFUNC(state->depth.func) |
1115 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1116
1117 /* stencil */
1118 if (state->stencil[0].enabled) {
1119 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1120 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1121 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1122 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1123 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1124
1125 if (state->stencil[1].enabled) {
1126 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1127 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1128 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1129 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1130 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1131 }
1132 }
1133
1134 /* alpha */
1135 if (state->alpha.enabled) {
1136 dsa->alpha_func = state->alpha.func;
1137
1138 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1139 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1140 } else {
1141 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1142 }
1143
1144 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1145 if (state->stencil[0].enabled)
1146 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1147 if (state->depth.bounds_test) {
1148 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1149 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1150 }
1151
1152 dsa->depth_enabled = state->depth.enabled;
1153 dsa->depth_write_enabled = state->depth.enabled &&
1154 state->depth.writemask;
1155 dsa->stencil_enabled = state->stencil[0].enabled;
1156 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1157 (si_dsa_writes_stencil(&state->stencil[0]) ||
1158 si_dsa_writes_stencil(&state->stencil[1]));
1159 dsa->db_can_write = dsa->depth_write_enabled ||
1160 dsa->stencil_write_enabled;
1161
1162 bool zfunc_is_ordered =
1163 state->depth.func == PIPE_FUNC_NEVER ||
1164 state->depth.func == PIPE_FUNC_LESS ||
1165 state->depth.func == PIPE_FUNC_LEQUAL ||
1166 state->depth.func == PIPE_FUNC_GREATER ||
1167 state->depth.func == PIPE_FUNC_GEQUAL;
1168
1169 bool nozwrite_and_order_invariant_stencil =
1170 !dsa->db_can_write ||
1171 (!dsa->depth_write_enabled &&
1172 si_order_invariant_stencil_state(&state->stencil[0]) &&
1173 si_order_invariant_stencil_state(&state->stencil[1]));
1174
1175 dsa->order_invariance[1].zs =
1176 nozwrite_and_order_invariant_stencil ||
1177 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1178 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1179
1180 dsa->order_invariance[1].pass_set =
1181 nozwrite_and_order_invariant_stencil ||
1182 (!dsa->stencil_write_enabled &&
1183 (state->depth.func == PIPE_FUNC_ALWAYS ||
1184 state->depth.func == PIPE_FUNC_NEVER));
1185 dsa->order_invariance[0].pass_set =
1186 !dsa->depth_write_enabled ||
1187 (state->depth.func == PIPE_FUNC_ALWAYS ||
1188 state->depth.func == PIPE_FUNC_NEVER);
1189
1190 dsa->order_invariance[1].pass_last =
1191 sctx->screen->assume_no_z_fights &&
1192 !dsa->stencil_write_enabled &&
1193 dsa->depth_write_enabled && zfunc_is_ordered;
1194 dsa->order_invariance[0].pass_last =
1195 sctx->screen->assume_no_z_fights &&
1196 dsa->depth_write_enabled && zfunc_is_ordered;
1197
1198 return dsa;
1199 }
1200
1201 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1202 {
1203 struct si_context *sctx = (struct si_context *)ctx;
1204 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1205 struct si_state_dsa *dsa = state;
1206
1207 if (!state)
1208 return;
1209
1210 si_pm4_bind_state(sctx, dsa, dsa);
1211
1212 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1213 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1214 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1215 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1216 }
1217
1218 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1219 sctx->do_update_shaders = true;
1220
1221 if (sctx->screen->dpbb_allowed &&
1222 (!old_dsa ||
1223 (old_dsa->depth_enabled != dsa->depth_enabled ||
1224 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1225 old_dsa->db_can_write != dsa->db_can_write)))
1226 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1227
1228 if (sctx->screen->has_out_of_order_rast &&
1229 (!old_dsa ||
1230 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1231 sizeof(old_dsa->order_invariance))))
1232 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1233 }
1234
1235 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1236 {
1237 struct si_context *sctx = (struct si_context *)ctx;
1238 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1239 }
1240
1241 static void *si_create_db_flush_dsa(struct si_context *sctx)
1242 {
1243 struct pipe_depth_stencil_alpha_state dsa = {};
1244
1245 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1246 }
1247
1248 /* DB RENDER STATE */
1249
1250 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1251 {
1252 struct si_context *sctx = (struct si_context*)ctx;
1253
1254 /* Pipeline stat & streamout queries. */
1255 if (enable) {
1256 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1257 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1258 } else {
1259 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1260 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1261 }
1262
1263 /* Occlusion queries. */
1264 if (sctx->occlusion_queries_disabled != !enable) {
1265 sctx->occlusion_queries_disabled = !enable;
1266 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1267 }
1268 }
1269
1270 static void si_set_occlusion_query_state(struct pipe_context *ctx,
1271 bool old_enable,
1272 bool old_perfect_enable)
1273 {
1274 struct si_context *sctx = (struct si_context*)ctx;
1275
1276 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1277
1278 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
1279
1280 if (perfect_enable != old_perfect_enable)
1281 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1282 }
1283
1284 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1285 {
1286 struct si_context *sctx = (struct si_context*)ctx;
1287
1288 st->saved_compute = sctx->cs_shader_state.program;
1289
1290 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1291 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1292 }
1293
1294 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1295 {
1296 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1297 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1298 unsigned db_shader_control;
1299
1300 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1301
1302 /* DB_RENDER_CONTROL */
1303 if (sctx->dbcb_depth_copy_enabled ||
1304 sctx->dbcb_stencil_copy_enabled) {
1305 radeon_emit(cs,
1306 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1307 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1308 S_028000_COPY_CENTROID(1) |
1309 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1310 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1311 radeon_emit(cs,
1312 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1313 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1314 } else {
1315 radeon_emit(cs,
1316 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1317 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1318 }
1319
1320 /* DB_COUNT_CONTROL (occlusion queries) */
1321 if (sctx->b.num_occlusion_queries > 0 &&
1322 !sctx->occlusion_queries_disabled) {
1323 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1324
1325 if (sctx->b.chip_class >= CIK) {
1326 radeon_emit(cs,
1327 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1328 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1329 S_028004_ZPASS_ENABLE(1) |
1330 S_028004_SLICE_EVEN_ENABLE(1) |
1331 S_028004_SLICE_ODD_ENABLE(1));
1332 } else {
1333 radeon_emit(cs,
1334 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1335 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1336 }
1337 } else {
1338 /* Disable occlusion queries. */
1339 if (sctx->b.chip_class >= CIK) {
1340 radeon_emit(cs, 0);
1341 } else {
1342 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1343 }
1344 }
1345
1346 /* DB_RENDER_OVERRIDE2 */
1347 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1348 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1349 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1350 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1351
1352 db_shader_control = sctx->ps_db_shader_control;
1353
1354 /* Bug workaround for smoothing (overrasterization) on SI. */
1355 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1356 db_shader_control &= C_02880C_Z_ORDER;
1357 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1358 }
1359
1360 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1361 if (!rs || !rs->multisample_enable)
1362 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1363
1364 if (sctx->screen->b.has_rbplus &&
1365 !sctx->screen->b.rbplus_allowed)
1366 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1367
1368 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1369 db_shader_control);
1370 }
1371
1372 /*
1373 * format translation
1374 */
1375 static uint32_t si_translate_colorformat(enum pipe_format format)
1376 {
1377 const struct util_format_description *desc = util_format_description(format);
1378 if (!desc)
1379 return V_028C70_COLOR_INVALID;
1380
1381 #define HAS_SIZE(x,y,z,w) \
1382 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1383 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1384
1385 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1386 return V_028C70_COLOR_10_11_11;
1387
1388 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1389 return V_028C70_COLOR_INVALID;
1390
1391 /* hw cannot support mixed formats (except depth/stencil, since
1392 * stencil is not written to). */
1393 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1394 return V_028C70_COLOR_INVALID;
1395
1396 switch (desc->nr_channels) {
1397 case 1:
1398 switch (desc->channel[0].size) {
1399 case 8:
1400 return V_028C70_COLOR_8;
1401 case 16:
1402 return V_028C70_COLOR_16;
1403 case 32:
1404 return V_028C70_COLOR_32;
1405 }
1406 break;
1407 case 2:
1408 if (desc->channel[0].size == desc->channel[1].size) {
1409 switch (desc->channel[0].size) {
1410 case 8:
1411 return V_028C70_COLOR_8_8;
1412 case 16:
1413 return V_028C70_COLOR_16_16;
1414 case 32:
1415 return V_028C70_COLOR_32_32;
1416 }
1417 } else if (HAS_SIZE(8,24,0,0)) {
1418 return V_028C70_COLOR_24_8;
1419 } else if (HAS_SIZE(24,8,0,0)) {
1420 return V_028C70_COLOR_8_24;
1421 }
1422 break;
1423 case 3:
1424 if (HAS_SIZE(5,6,5,0)) {
1425 return V_028C70_COLOR_5_6_5;
1426 } else if (HAS_SIZE(32,8,24,0)) {
1427 return V_028C70_COLOR_X24_8_32_FLOAT;
1428 }
1429 break;
1430 case 4:
1431 if (desc->channel[0].size == desc->channel[1].size &&
1432 desc->channel[0].size == desc->channel[2].size &&
1433 desc->channel[0].size == desc->channel[3].size) {
1434 switch (desc->channel[0].size) {
1435 case 4:
1436 return V_028C70_COLOR_4_4_4_4;
1437 case 8:
1438 return V_028C70_COLOR_8_8_8_8;
1439 case 16:
1440 return V_028C70_COLOR_16_16_16_16;
1441 case 32:
1442 return V_028C70_COLOR_32_32_32_32;
1443 }
1444 } else if (HAS_SIZE(5,5,5,1)) {
1445 return V_028C70_COLOR_1_5_5_5;
1446 } else if (HAS_SIZE(10,10,10,2)) {
1447 return V_028C70_COLOR_2_10_10_10;
1448 }
1449 break;
1450 }
1451 return V_028C70_COLOR_INVALID;
1452 }
1453
1454 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1455 {
1456 if (SI_BIG_ENDIAN) {
1457 switch(colorformat) {
1458 /* 8-bit buffers. */
1459 case V_028C70_COLOR_8:
1460 return V_028C70_ENDIAN_NONE;
1461
1462 /* 16-bit buffers. */
1463 case V_028C70_COLOR_5_6_5:
1464 case V_028C70_COLOR_1_5_5_5:
1465 case V_028C70_COLOR_4_4_4_4:
1466 case V_028C70_COLOR_16:
1467 case V_028C70_COLOR_8_8:
1468 return V_028C70_ENDIAN_8IN16;
1469
1470 /* 32-bit buffers. */
1471 case V_028C70_COLOR_8_8_8_8:
1472 case V_028C70_COLOR_2_10_10_10:
1473 case V_028C70_COLOR_8_24:
1474 case V_028C70_COLOR_24_8:
1475 case V_028C70_COLOR_16_16:
1476 return V_028C70_ENDIAN_8IN32;
1477
1478 /* 64-bit buffers. */
1479 case V_028C70_COLOR_16_16_16_16:
1480 return V_028C70_ENDIAN_8IN16;
1481
1482 case V_028C70_COLOR_32_32:
1483 return V_028C70_ENDIAN_8IN32;
1484
1485 /* 128-bit buffers. */
1486 case V_028C70_COLOR_32_32_32_32:
1487 return V_028C70_ENDIAN_8IN32;
1488 default:
1489 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1490 }
1491 } else {
1492 return V_028C70_ENDIAN_NONE;
1493 }
1494 }
1495
1496 static uint32_t si_translate_dbformat(enum pipe_format format)
1497 {
1498 switch (format) {
1499 case PIPE_FORMAT_Z16_UNORM:
1500 return V_028040_Z_16;
1501 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1502 case PIPE_FORMAT_X8Z24_UNORM:
1503 case PIPE_FORMAT_Z24X8_UNORM:
1504 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1505 return V_028040_Z_24; /* deprecated on SI */
1506 case PIPE_FORMAT_Z32_FLOAT:
1507 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1508 return V_028040_Z_32_FLOAT;
1509 default:
1510 return V_028040_Z_INVALID;
1511 }
1512 }
1513
1514 /*
1515 * Texture translation
1516 */
1517
1518 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1519 enum pipe_format format,
1520 const struct util_format_description *desc,
1521 int first_non_void)
1522 {
1523 struct si_screen *sscreen = (struct si_screen*)screen;
1524 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1525 sscreen->b.info.drm_minor >= 31) ||
1526 sscreen->b.info.drm_major == 3;
1527 bool uniform = true;
1528 int i;
1529
1530 /* Colorspace (return non-RGB formats directly). */
1531 switch (desc->colorspace) {
1532 /* Depth stencil formats */
1533 case UTIL_FORMAT_COLORSPACE_ZS:
1534 switch (format) {
1535 case PIPE_FORMAT_Z16_UNORM:
1536 return V_008F14_IMG_DATA_FORMAT_16;
1537 case PIPE_FORMAT_X24S8_UINT:
1538 case PIPE_FORMAT_S8X24_UINT:
1539 /*
1540 * Implemented as an 8_8_8_8 data format to fix texture
1541 * gathers in stencil sampling. This affects at least
1542 * GL45-CTS.texture_cube_map_array.sampling on VI.
1543 */
1544 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1545 case PIPE_FORMAT_Z24X8_UNORM:
1546 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1547 return V_008F14_IMG_DATA_FORMAT_8_24;
1548 case PIPE_FORMAT_X8Z24_UNORM:
1549 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1550 return V_008F14_IMG_DATA_FORMAT_24_8;
1551 case PIPE_FORMAT_S8_UINT:
1552 return V_008F14_IMG_DATA_FORMAT_8;
1553 case PIPE_FORMAT_Z32_FLOAT:
1554 return V_008F14_IMG_DATA_FORMAT_32;
1555 case PIPE_FORMAT_X32_S8X24_UINT:
1556 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1557 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1558 default:
1559 goto out_unknown;
1560 }
1561
1562 case UTIL_FORMAT_COLORSPACE_YUV:
1563 goto out_unknown; /* TODO */
1564
1565 case UTIL_FORMAT_COLORSPACE_SRGB:
1566 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1567 goto out_unknown;
1568 break;
1569
1570 default:
1571 break;
1572 }
1573
1574 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1575 if (!enable_compressed_formats)
1576 goto out_unknown;
1577
1578 switch (format) {
1579 case PIPE_FORMAT_RGTC1_SNORM:
1580 case PIPE_FORMAT_LATC1_SNORM:
1581 case PIPE_FORMAT_RGTC1_UNORM:
1582 case PIPE_FORMAT_LATC1_UNORM:
1583 return V_008F14_IMG_DATA_FORMAT_BC4;
1584 case PIPE_FORMAT_RGTC2_SNORM:
1585 case PIPE_FORMAT_LATC2_SNORM:
1586 case PIPE_FORMAT_RGTC2_UNORM:
1587 case PIPE_FORMAT_LATC2_UNORM:
1588 return V_008F14_IMG_DATA_FORMAT_BC5;
1589 default:
1590 goto out_unknown;
1591 }
1592 }
1593
1594 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1595 (sscreen->b.family == CHIP_STONEY ||
1596 sscreen->b.chip_class >= GFX9)) {
1597 switch (format) {
1598 case PIPE_FORMAT_ETC1_RGB8:
1599 case PIPE_FORMAT_ETC2_RGB8:
1600 case PIPE_FORMAT_ETC2_SRGB8:
1601 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1602 case PIPE_FORMAT_ETC2_RGB8A1:
1603 case PIPE_FORMAT_ETC2_SRGB8A1:
1604 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1605 case PIPE_FORMAT_ETC2_RGBA8:
1606 case PIPE_FORMAT_ETC2_SRGBA8:
1607 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1608 case PIPE_FORMAT_ETC2_R11_UNORM:
1609 case PIPE_FORMAT_ETC2_R11_SNORM:
1610 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1611 case PIPE_FORMAT_ETC2_RG11_UNORM:
1612 case PIPE_FORMAT_ETC2_RG11_SNORM:
1613 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1614 default:
1615 goto out_unknown;
1616 }
1617 }
1618
1619 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1620 if (!enable_compressed_formats)
1621 goto out_unknown;
1622
1623 switch (format) {
1624 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1625 case PIPE_FORMAT_BPTC_SRGBA:
1626 return V_008F14_IMG_DATA_FORMAT_BC7;
1627 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1628 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1629 return V_008F14_IMG_DATA_FORMAT_BC6;
1630 default:
1631 goto out_unknown;
1632 }
1633 }
1634
1635 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1636 switch (format) {
1637 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1638 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1639 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1640 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1641 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1642 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1643 default:
1644 goto out_unknown;
1645 }
1646 }
1647
1648 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1649 if (!enable_compressed_formats)
1650 goto out_unknown;
1651
1652 if (!util_format_s3tc_enabled) {
1653 goto out_unknown;
1654 }
1655
1656 switch (format) {
1657 case PIPE_FORMAT_DXT1_RGB:
1658 case PIPE_FORMAT_DXT1_RGBA:
1659 case PIPE_FORMAT_DXT1_SRGB:
1660 case PIPE_FORMAT_DXT1_SRGBA:
1661 return V_008F14_IMG_DATA_FORMAT_BC1;
1662 case PIPE_FORMAT_DXT3_RGBA:
1663 case PIPE_FORMAT_DXT3_SRGBA:
1664 return V_008F14_IMG_DATA_FORMAT_BC2;
1665 case PIPE_FORMAT_DXT5_RGBA:
1666 case PIPE_FORMAT_DXT5_SRGBA:
1667 return V_008F14_IMG_DATA_FORMAT_BC3;
1668 default:
1669 goto out_unknown;
1670 }
1671 }
1672
1673 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1674 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1675 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1676 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1677 }
1678
1679 /* R8G8Bx_SNORM - TODO CxV8U8 */
1680
1681 /* hw cannot support mixed formats (except depth/stencil, since only
1682 * depth is read).*/
1683 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1684 goto out_unknown;
1685
1686 /* See whether the components are of the same size. */
1687 for (i = 1; i < desc->nr_channels; i++) {
1688 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1689 }
1690
1691 /* Non-uniform formats. */
1692 if (!uniform) {
1693 switch(desc->nr_channels) {
1694 case 3:
1695 if (desc->channel[0].size == 5 &&
1696 desc->channel[1].size == 6 &&
1697 desc->channel[2].size == 5) {
1698 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1699 }
1700 goto out_unknown;
1701 case 4:
1702 if (desc->channel[0].size == 5 &&
1703 desc->channel[1].size == 5 &&
1704 desc->channel[2].size == 5 &&
1705 desc->channel[3].size == 1) {
1706 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1707 }
1708 if (desc->channel[0].size == 10 &&
1709 desc->channel[1].size == 10 &&
1710 desc->channel[2].size == 10 &&
1711 desc->channel[3].size == 2) {
1712 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1713 }
1714 goto out_unknown;
1715 }
1716 goto out_unknown;
1717 }
1718
1719 if (first_non_void < 0 || first_non_void > 3)
1720 goto out_unknown;
1721
1722 /* uniform formats */
1723 switch (desc->channel[first_non_void].size) {
1724 case 4:
1725 switch (desc->nr_channels) {
1726 #if 0 /* Not supported for render targets */
1727 case 2:
1728 return V_008F14_IMG_DATA_FORMAT_4_4;
1729 #endif
1730 case 4:
1731 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1732 }
1733 break;
1734 case 8:
1735 switch (desc->nr_channels) {
1736 case 1:
1737 return V_008F14_IMG_DATA_FORMAT_8;
1738 case 2:
1739 return V_008F14_IMG_DATA_FORMAT_8_8;
1740 case 4:
1741 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1742 }
1743 break;
1744 case 16:
1745 switch (desc->nr_channels) {
1746 case 1:
1747 return V_008F14_IMG_DATA_FORMAT_16;
1748 case 2:
1749 return V_008F14_IMG_DATA_FORMAT_16_16;
1750 case 4:
1751 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1752 }
1753 break;
1754 case 32:
1755 switch (desc->nr_channels) {
1756 case 1:
1757 return V_008F14_IMG_DATA_FORMAT_32;
1758 case 2:
1759 return V_008F14_IMG_DATA_FORMAT_32_32;
1760 #if 0 /* Not supported for render targets */
1761 case 3:
1762 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1763 #endif
1764 case 4:
1765 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1766 }
1767 }
1768
1769 out_unknown:
1770 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1771 return ~0;
1772 }
1773
1774 static unsigned si_tex_wrap(unsigned wrap)
1775 {
1776 switch (wrap) {
1777 default:
1778 case PIPE_TEX_WRAP_REPEAT:
1779 return V_008F30_SQ_TEX_WRAP;
1780 case PIPE_TEX_WRAP_CLAMP:
1781 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1782 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1783 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1784 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1785 return V_008F30_SQ_TEX_CLAMP_BORDER;
1786 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1787 return V_008F30_SQ_TEX_MIRROR;
1788 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1789 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1790 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1791 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1792 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1793 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1794 }
1795 }
1796
1797 static unsigned si_tex_mipfilter(unsigned filter)
1798 {
1799 switch (filter) {
1800 case PIPE_TEX_MIPFILTER_NEAREST:
1801 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1802 case PIPE_TEX_MIPFILTER_LINEAR:
1803 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1804 default:
1805 case PIPE_TEX_MIPFILTER_NONE:
1806 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1807 }
1808 }
1809
1810 static unsigned si_tex_compare(unsigned compare)
1811 {
1812 switch (compare) {
1813 default:
1814 case PIPE_FUNC_NEVER:
1815 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1816 case PIPE_FUNC_LESS:
1817 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1818 case PIPE_FUNC_EQUAL:
1819 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1820 case PIPE_FUNC_LEQUAL:
1821 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1822 case PIPE_FUNC_GREATER:
1823 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1824 case PIPE_FUNC_NOTEQUAL:
1825 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1826 case PIPE_FUNC_GEQUAL:
1827 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1828 case PIPE_FUNC_ALWAYS:
1829 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1830 }
1831 }
1832
1833 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1834 unsigned view_target, unsigned nr_samples)
1835 {
1836 unsigned res_target = rtex->resource.b.b.target;
1837
1838 if (view_target == PIPE_TEXTURE_CUBE ||
1839 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1840 res_target = view_target;
1841 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1842 else if (res_target == PIPE_TEXTURE_CUBE ||
1843 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1844 res_target = PIPE_TEXTURE_2D_ARRAY;
1845
1846 /* GFX9 allocates 1D textures as 2D. */
1847 if ((res_target == PIPE_TEXTURE_1D ||
1848 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1849 sscreen->b.chip_class >= GFX9 &&
1850 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1851 if (res_target == PIPE_TEXTURE_1D)
1852 res_target = PIPE_TEXTURE_2D;
1853 else
1854 res_target = PIPE_TEXTURE_2D_ARRAY;
1855 }
1856
1857 switch (res_target) {
1858 default:
1859 case PIPE_TEXTURE_1D:
1860 return V_008F1C_SQ_RSRC_IMG_1D;
1861 case PIPE_TEXTURE_1D_ARRAY:
1862 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1863 case PIPE_TEXTURE_2D:
1864 case PIPE_TEXTURE_RECT:
1865 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1866 V_008F1C_SQ_RSRC_IMG_2D;
1867 case PIPE_TEXTURE_2D_ARRAY:
1868 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1869 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1870 case PIPE_TEXTURE_3D:
1871 return V_008F1C_SQ_RSRC_IMG_3D;
1872 case PIPE_TEXTURE_CUBE:
1873 case PIPE_TEXTURE_CUBE_ARRAY:
1874 return V_008F1C_SQ_RSRC_IMG_CUBE;
1875 }
1876 }
1877
1878 /*
1879 * Format support testing
1880 */
1881
1882 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1883 {
1884 const struct util_format_description *desc = util_format_description(format);
1885 if (!desc)
1886 return false;
1887
1888 return si_translate_texformat(screen, format, desc,
1889 util_format_get_first_non_void_channel(format)) != ~0U;
1890 }
1891
1892 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1893 const struct util_format_description *desc,
1894 int first_non_void)
1895 {
1896 int i;
1897
1898 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1899 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1900
1901 assert(first_non_void >= 0);
1902
1903 if (desc->nr_channels == 4 &&
1904 desc->channel[0].size == 10 &&
1905 desc->channel[1].size == 10 &&
1906 desc->channel[2].size == 10 &&
1907 desc->channel[3].size == 2)
1908 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1909
1910 /* See whether the components are of the same size. */
1911 for (i = 0; i < desc->nr_channels; i++) {
1912 if (desc->channel[first_non_void].size != desc->channel[i].size)
1913 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1914 }
1915
1916 switch (desc->channel[first_non_void].size) {
1917 case 8:
1918 switch (desc->nr_channels) {
1919 case 1:
1920 case 3: /* 3 loads */
1921 return V_008F0C_BUF_DATA_FORMAT_8;
1922 case 2:
1923 return V_008F0C_BUF_DATA_FORMAT_8_8;
1924 case 4:
1925 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1926 }
1927 break;
1928 case 16:
1929 switch (desc->nr_channels) {
1930 case 1:
1931 case 3: /* 3 loads */
1932 return V_008F0C_BUF_DATA_FORMAT_16;
1933 case 2:
1934 return V_008F0C_BUF_DATA_FORMAT_16_16;
1935 case 4:
1936 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1937 }
1938 break;
1939 case 32:
1940 switch (desc->nr_channels) {
1941 case 1:
1942 return V_008F0C_BUF_DATA_FORMAT_32;
1943 case 2:
1944 return V_008F0C_BUF_DATA_FORMAT_32_32;
1945 case 3:
1946 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1947 case 4:
1948 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1949 }
1950 break;
1951 case 64:
1952 /* Legacy double formats. */
1953 switch (desc->nr_channels) {
1954 case 1: /* 1 load */
1955 return V_008F0C_BUF_DATA_FORMAT_32_32;
1956 case 2: /* 1 load */
1957 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1958 case 3: /* 3 loads */
1959 return V_008F0C_BUF_DATA_FORMAT_32_32;
1960 case 4: /* 2 loads */
1961 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1962 }
1963 break;
1964 }
1965
1966 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1967 }
1968
1969 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1970 const struct util_format_description *desc,
1971 int first_non_void)
1972 {
1973 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1974 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1975
1976 assert(first_non_void >= 0);
1977
1978 switch (desc->channel[first_non_void].type) {
1979 case UTIL_FORMAT_TYPE_SIGNED:
1980 case UTIL_FORMAT_TYPE_FIXED:
1981 if (desc->channel[first_non_void].size >= 32 ||
1982 desc->channel[first_non_void].pure_integer)
1983 return V_008F0C_BUF_NUM_FORMAT_SINT;
1984 else if (desc->channel[first_non_void].normalized)
1985 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1986 else
1987 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1988 break;
1989 case UTIL_FORMAT_TYPE_UNSIGNED:
1990 if (desc->channel[first_non_void].size >= 32 ||
1991 desc->channel[first_non_void].pure_integer)
1992 return V_008F0C_BUF_NUM_FORMAT_UINT;
1993 else if (desc->channel[first_non_void].normalized)
1994 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1995 else
1996 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1997 break;
1998 case UTIL_FORMAT_TYPE_FLOAT:
1999 default:
2000 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2001 }
2002 }
2003
2004 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2005 enum pipe_format format,
2006 unsigned usage)
2007 {
2008 const struct util_format_description *desc;
2009 int first_non_void;
2010 unsigned data_format;
2011
2012 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2013 PIPE_BIND_SAMPLER_VIEW |
2014 PIPE_BIND_VERTEX_BUFFER)) == 0);
2015
2016 desc = util_format_description(format);
2017 if (!desc)
2018 return 0;
2019
2020 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2021 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2022 * for read-only access (with caveats surrounding bounds checks), but
2023 * obviously fails for write access which we have to implement for
2024 * shader images. Luckily, OpenGL doesn't expect this to be supported
2025 * anyway, and so the only impact is on PBO uploads / downloads, which
2026 * shouldn't be expected to be fast for GL_RGB anyway.
2027 */
2028 if (desc->block.bits == 3 * 8 ||
2029 desc->block.bits == 3 * 16) {
2030 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2031 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2032 if (!usage)
2033 return 0;
2034 }
2035 }
2036
2037 first_non_void = util_format_get_first_non_void_channel(format);
2038 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2039 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2040 return 0;
2041
2042 return usage;
2043 }
2044
2045 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2046 {
2047 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2048 r600_translate_colorswap(format, false) != ~0U;
2049 }
2050
2051 static bool si_is_zs_format_supported(enum pipe_format format)
2052 {
2053 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2054 }
2055
2056 static boolean si_is_format_supported(struct pipe_screen *screen,
2057 enum pipe_format format,
2058 enum pipe_texture_target target,
2059 unsigned sample_count,
2060 unsigned usage)
2061 {
2062 unsigned retval = 0;
2063
2064 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2065 R600_ERR("r600: unsupported texture type %d\n", target);
2066 return false;
2067 }
2068
2069 if (!util_format_is_supported(format, usage))
2070 return false;
2071
2072 if (sample_count > 1) {
2073 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2074 return false;
2075
2076 if (usage & PIPE_BIND_SHADER_IMAGE)
2077 return false;
2078
2079 switch (sample_count) {
2080 case 2:
2081 case 4:
2082 case 8:
2083 break;
2084 case 16:
2085 if (format == PIPE_FORMAT_NONE)
2086 return true;
2087 else
2088 return false;
2089 default:
2090 return false;
2091 }
2092 }
2093
2094 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2095 PIPE_BIND_SHADER_IMAGE)) {
2096 if (target == PIPE_BUFFER) {
2097 retval |= si_is_vertex_format_supported(
2098 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2099 PIPE_BIND_SHADER_IMAGE));
2100 } else {
2101 if (si_is_sampler_format_supported(screen, format))
2102 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2103 PIPE_BIND_SHADER_IMAGE);
2104 }
2105 }
2106
2107 if ((usage & (PIPE_BIND_RENDER_TARGET |
2108 PIPE_BIND_DISPLAY_TARGET |
2109 PIPE_BIND_SCANOUT |
2110 PIPE_BIND_SHARED |
2111 PIPE_BIND_BLENDABLE)) &&
2112 si_is_colorbuffer_format_supported(format)) {
2113 retval |= usage &
2114 (PIPE_BIND_RENDER_TARGET |
2115 PIPE_BIND_DISPLAY_TARGET |
2116 PIPE_BIND_SCANOUT |
2117 PIPE_BIND_SHARED);
2118 if (!util_format_is_pure_integer(format) &&
2119 !util_format_is_depth_or_stencil(format))
2120 retval |= usage & PIPE_BIND_BLENDABLE;
2121 }
2122
2123 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2124 si_is_zs_format_supported(format)) {
2125 retval |= PIPE_BIND_DEPTH_STENCIL;
2126 }
2127
2128 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2129 retval |= si_is_vertex_format_supported(screen, format,
2130 PIPE_BIND_VERTEX_BUFFER);
2131 }
2132
2133 if ((usage & PIPE_BIND_LINEAR) &&
2134 !util_format_is_compressed(format) &&
2135 !(usage & PIPE_BIND_DEPTH_STENCIL))
2136 retval |= PIPE_BIND_LINEAR;
2137
2138 return retval == usage;
2139 }
2140
2141 /*
2142 * framebuffer handling
2143 */
2144
2145 static void si_choose_spi_color_formats(struct r600_surface *surf,
2146 unsigned format, unsigned swap,
2147 unsigned ntype, bool is_depth)
2148 {
2149 /* Alpha is needed for alpha-to-coverage.
2150 * Blending may be with or without alpha.
2151 */
2152 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2153 unsigned alpha = 0; /* exports alpha, but may not support blending */
2154 unsigned blend = 0; /* supports blending, but may not export alpha */
2155 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2156
2157 /* Choose the SPI color formats. These are required values for RB+.
2158 * Other chips have multiple choices, though they are not necessarily better.
2159 */
2160 switch (format) {
2161 case V_028C70_COLOR_5_6_5:
2162 case V_028C70_COLOR_1_5_5_5:
2163 case V_028C70_COLOR_5_5_5_1:
2164 case V_028C70_COLOR_4_4_4_4:
2165 case V_028C70_COLOR_10_11_11:
2166 case V_028C70_COLOR_11_11_10:
2167 case V_028C70_COLOR_8:
2168 case V_028C70_COLOR_8_8:
2169 case V_028C70_COLOR_8_8_8_8:
2170 case V_028C70_COLOR_10_10_10_2:
2171 case V_028C70_COLOR_2_10_10_10:
2172 if (ntype == V_028C70_NUMBER_UINT)
2173 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2174 else if (ntype == V_028C70_NUMBER_SINT)
2175 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2176 else
2177 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2178 break;
2179
2180 case V_028C70_COLOR_16:
2181 case V_028C70_COLOR_16_16:
2182 case V_028C70_COLOR_16_16_16_16:
2183 if (ntype == V_028C70_NUMBER_UNORM ||
2184 ntype == V_028C70_NUMBER_SNORM) {
2185 /* UNORM16 and SNORM16 don't support blending */
2186 if (ntype == V_028C70_NUMBER_UNORM)
2187 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2188 else
2189 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2190
2191 /* Use 32 bits per channel for blending. */
2192 if (format == V_028C70_COLOR_16) {
2193 if (swap == V_028C70_SWAP_STD) { /* R */
2194 blend = V_028714_SPI_SHADER_32_R;
2195 blend_alpha = V_028714_SPI_SHADER_32_AR;
2196 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2197 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2198 else
2199 assert(0);
2200 } else if (format == V_028C70_COLOR_16_16) {
2201 if (swap == V_028C70_SWAP_STD) { /* RG */
2202 blend = V_028714_SPI_SHADER_32_GR;
2203 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2204 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2205 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2206 else
2207 assert(0);
2208 } else /* 16_16_16_16 */
2209 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2210 } else if (ntype == V_028C70_NUMBER_UINT)
2211 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2212 else if (ntype == V_028C70_NUMBER_SINT)
2213 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2214 else if (ntype == V_028C70_NUMBER_FLOAT)
2215 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2216 else
2217 assert(0);
2218 break;
2219
2220 case V_028C70_COLOR_32:
2221 if (swap == V_028C70_SWAP_STD) { /* R */
2222 blend = normal = V_028714_SPI_SHADER_32_R;
2223 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2224 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2225 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2226 else
2227 assert(0);
2228 break;
2229
2230 case V_028C70_COLOR_32_32:
2231 if (swap == V_028C70_SWAP_STD) { /* RG */
2232 blend = normal = V_028714_SPI_SHADER_32_GR;
2233 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2234 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2235 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2236 else
2237 assert(0);
2238 break;
2239
2240 case V_028C70_COLOR_32_32_32_32:
2241 case V_028C70_COLOR_8_24:
2242 case V_028C70_COLOR_24_8:
2243 case V_028C70_COLOR_X24_8_32_FLOAT:
2244 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2245 break;
2246
2247 default:
2248 assert(0);
2249 return;
2250 }
2251
2252 /* The DB->CB copy needs 32_ABGR. */
2253 if (is_depth)
2254 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2255
2256 surf->spi_shader_col_format = normal;
2257 surf->spi_shader_col_format_alpha = alpha;
2258 surf->spi_shader_col_format_blend = blend;
2259 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2260 }
2261
2262 static void si_initialize_color_surface(struct si_context *sctx,
2263 struct r600_surface *surf)
2264 {
2265 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2266 unsigned color_info, color_attrib, color_view;
2267 unsigned format, swap, ntype, endian;
2268 const struct util_format_description *desc;
2269 int firstchan;
2270 unsigned blend_clamp = 0, blend_bypass = 0;
2271
2272 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2273 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2274
2275 desc = util_format_description(surf->base.format);
2276 for (firstchan = 0; firstchan < 4; firstchan++) {
2277 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2278 break;
2279 }
2280 }
2281 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2282 ntype = V_028C70_NUMBER_FLOAT;
2283 } else {
2284 ntype = V_028C70_NUMBER_UNORM;
2285 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2286 ntype = V_028C70_NUMBER_SRGB;
2287 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2288 if (desc->channel[firstchan].pure_integer) {
2289 ntype = V_028C70_NUMBER_SINT;
2290 } else {
2291 assert(desc->channel[firstchan].normalized);
2292 ntype = V_028C70_NUMBER_SNORM;
2293 }
2294 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2295 if (desc->channel[firstchan].pure_integer) {
2296 ntype = V_028C70_NUMBER_UINT;
2297 } else {
2298 assert(desc->channel[firstchan].normalized);
2299 ntype = V_028C70_NUMBER_UNORM;
2300 }
2301 }
2302 }
2303
2304 format = si_translate_colorformat(surf->base.format);
2305 if (format == V_028C70_COLOR_INVALID) {
2306 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2307 }
2308 assert(format != V_028C70_COLOR_INVALID);
2309 swap = r600_translate_colorswap(surf->base.format, false);
2310 endian = si_colorformat_endian_swap(format);
2311
2312 /* blend clamp should be set for all NORM/SRGB types */
2313 if (ntype == V_028C70_NUMBER_UNORM ||
2314 ntype == V_028C70_NUMBER_SNORM ||
2315 ntype == V_028C70_NUMBER_SRGB)
2316 blend_clamp = 1;
2317
2318 /* set blend bypass according to docs if SINT/UINT or
2319 8/24 COLOR variants */
2320 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2321 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2322 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2323 blend_clamp = 0;
2324 blend_bypass = 1;
2325 }
2326
2327 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2328 if (format == V_028C70_COLOR_8 ||
2329 format == V_028C70_COLOR_8_8 ||
2330 format == V_028C70_COLOR_8_8_8_8)
2331 surf->color_is_int8 = true;
2332 else if (format == V_028C70_COLOR_10_10_10_2 ||
2333 format == V_028C70_COLOR_2_10_10_10)
2334 surf->color_is_int10 = true;
2335 }
2336
2337 color_info = S_028C70_FORMAT(format) |
2338 S_028C70_COMP_SWAP(swap) |
2339 S_028C70_BLEND_CLAMP(blend_clamp) |
2340 S_028C70_BLEND_BYPASS(blend_bypass) |
2341 S_028C70_SIMPLE_FLOAT(1) |
2342 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2343 ntype != V_028C70_NUMBER_SNORM &&
2344 ntype != V_028C70_NUMBER_SRGB &&
2345 format != V_028C70_COLOR_8_24 &&
2346 format != V_028C70_COLOR_24_8) |
2347 S_028C70_NUMBER_TYPE(ntype) |
2348 S_028C70_ENDIAN(endian);
2349
2350 /* Intensity is implemented as Red, so treat it that way. */
2351 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2352 util_format_is_intensity(surf->base.format));
2353
2354 if (rtex->resource.b.b.nr_samples > 1) {
2355 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2356
2357 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2358 S_028C74_NUM_FRAGMENTS(log_samples);
2359
2360 if (rtex->fmask.size) {
2361 color_info |= S_028C70_COMPRESSION(1);
2362 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2363
2364 if (sctx->b.chip_class == SI) {
2365 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2366 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2367 }
2368 }
2369 }
2370
2371 surf->cb_color_view = color_view;
2372 surf->cb_color_info = color_info;
2373 surf->cb_color_attrib = color_attrib;
2374
2375 if (sctx->b.chip_class >= VI) {
2376 unsigned max_uncompressed_block_size = 2;
2377
2378 if (rtex->resource.b.b.nr_samples > 1) {
2379 if (rtex->surface.bpe == 1)
2380 max_uncompressed_block_size = 0;
2381 else if (rtex->surface.bpe == 2)
2382 max_uncompressed_block_size = 1;
2383 }
2384
2385 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2386 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2387 }
2388
2389 /* This must be set for fast clear to work without FMASK. */
2390 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2391 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2392 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2393 }
2394
2395 if (sctx->b.chip_class >= GFX9) {
2396 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2397
2398 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2399 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2400 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2401 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2402 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2403 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2404 }
2405
2406 /* Determine pixel shader export format */
2407 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2408
2409 surf->color_initialized = true;
2410 }
2411
2412 static void si_init_depth_surface(struct si_context *sctx,
2413 struct r600_surface *surf)
2414 {
2415 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2416 unsigned level = surf->base.u.tex.level;
2417 unsigned format, stencil_format;
2418 uint32_t z_info, s_info;
2419
2420 format = si_translate_dbformat(rtex->db_render_format);
2421 stencil_format = rtex->surface.has_stencil ?
2422 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2423
2424 assert(format != V_028040_Z_INVALID);
2425 if (format == V_028040_Z_INVALID)
2426 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2427
2428 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2429 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2430 surf->db_htile_data_base = 0;
2431 surf->db_htile_surface = 0;
2432
2433 if (sctx->b.chip_class >= GFX9) {
2434 assert(rtex->surface.u.gfx9.surf_offset == 0);
2435 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2436 surf->db_stencil_base = (rtex->resource.gpu_address +
2437 rtex->surface.u.gfx9.stencil_offset) >> 8;
2438 z_info = S_028038_FORMAT(format) |
2439 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2440 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2441 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2442 s_info = S_02803C_FORMAT(stencil_format) |
2443 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2444 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2445 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2446 surf->db_depth_view |= S_028008_MIPID(level);
2447 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2448 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2449
2450 if (r600_htile_enabled(rtex, level)) {
2451 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2452 S_028038_ALLOW_EXPCLEAR(1);
2453
2454 if (rtex->tc_compatible_htile) {
2455 unsigned max_zplanes = 4;
2456
2457 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2458 rtex->resource.b.b.nr_samples > 1)
2459 max_zplanes = 2;
2460
2461 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2462 S_028038_ITERATE_FLUSH(1);
2463 s_info |= S_02803C_ITERATE_FLUSH(1);
2464 }
2465
2466 if (rtex->surface.has_stencil) {
2467 /* Stencil buffer workaround ported from the SI-CI-VI code.
2468 * See that for explanation.
2469 */
2470 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2471 } else {
2472 /* Use all HTILE for depth if there's no stencil. */
2473 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2474 }
2475
2476 surf->db_htile_data_base = (rtex->resource.gpu_address +
2477 rtex->htile_offset) >> 8;
2478 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2479 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2480 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2481 }
2482 } else {
2483 /* SI-CI-VI */
2484 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2485
2486 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2487
2488 surf->db_depth_base = (rtex->resource.gpu_address +
2489 rtex->surface.u.legacy.level[level].offset) >> 8;
2490 surf->db_stencil_base = (rtex->resource.gpu_address +
2491 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2492
2493 z_info = S_028040_FORMAT(format) |
2494 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2495 s_info = S_028044_FORMAT(stencil_format);
2496 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2497
2498 if (sctx->b.chip_class >= CIK) {
2499 struct radeon_info *info = &sctx->screen->b.info;
2500 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2501 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2502 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2503 unsigned tile_mode = info->si_tile_mode_array[index];
2504 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2505 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2506
2507 surf->db_depth_info |=
2508 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2509 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2510 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2511 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2512 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2513 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2514 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2515 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2516 } else {
2517 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2518 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2519 tile_mode_index = si_tile_mode_index(rtex, level, true);
2520 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2521 }
2522
2523 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2524 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2525 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2526 levelinfo->nblk_y) / 64 - 1);
2527
2528 if (r600_htile_enabled(rtex, level)) {
2529 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2530 S_028040_ALLOW_EXPCLEAR(1);
2531
2532 if (rtex->surface.has_stencil) {
2533 /* Workaround: For a not yet understood reason, the
2534 * combination of MSAA, fast stencil clear and stencil
2535 * decompress messes with subsequent stencil buffer
2536 * uses. Problem was reproduced on Verde, Bonaire,
2537 * Tonga, and Carrizo.
2538 *
2539 * Disabling EXPCLEAR works around the problem.
2540 *
2541 * Check piglit's arb_texture_multisample-stencil-clear
2542 * test if you want to try changing this.
2543 */
2544 if (rtex->resource.b.b.nr_samples <= 1)
2545 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2546 } else if (!rtex->tc_compatible_htile) {
2547 /* Use all of the htile_buffer for depth if there's no stencil.
2548 * This must not be set when TC-compatible HTILE is enabled
2549 * due to a hw bug.
2550 */
2551 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2552 }
2553
2554 surf->db_htile_data_base = (rtex->resource.gpu_address +
2555 rtex->htile_offset) >> 8;
2556 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2557
2558 if (rtex->tc_compatible_htile) {
2559 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2560
2561 if (rtex->resource.b.b.nr_samples <= 1)
2562 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2563 else if (rtex->resource.b.b.nr_samples <= 4)
2564 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2565 else
2566 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2567 }
2568 }
2569 }
2570
2571 surf->db_z_info = z_info;
2572 surf->db_stencil_info = s_info;
2573
2574 surf->depth_initialized = true;
2575 }
2576
2577 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2578 {
2579 if (sctx->decompression_enabled)
2580 return;
2581
2582 if (sctx->framebuffer.state.zsbuf) {
2583 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2584 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2585
2586 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2587
2588 if (rtex->surface.has_stencil)
2589 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2590 }
2591 if (sctx->framebuffer.compressed_cb_mask) {
2592 struct pipe_surface *surf;
2593 struct r600_texture *rtex;
2594 unsigned mask = sctx->framebuffer.compressed_cb_mask;
2595
2596 do {
2597 unsigned i = u_bit_scan(&mask);
2598 surf = sctx->framebuffer.state.cbufs[i];
2599 rtex = (struct r600_texture*)surf->texture;
2600
2601 if (rtex->fmask.size)
2602 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2603 if (rtex->dcc_gather_statistics)
2604 rtex->separate_dcc_dirty = true;
2605 } while (mask);
2606 }
2607 }
2608
2609 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2610 {
2611 for (int i = 0; i < state->nr_cbufs; ++i) {
2612 struct r600_surface *surf = NULL;
2613 struct r600_texture *rtex;
2614
2615 if (!state->cbufs[i])
2616 continue;
2617 surf = (struct r600_surface*)state->cbufs[i];
2618 rtex = (struct r600_texture*)surf->base.texture;
2619
2620 p_atomic_dec(&rtex->framebuffers_bound);
2621 }
2622 }
2623
2624 static void si_set_framebuffer_state(struct pipe_context *ctx,
2625 const struct pipe_framebuffer_state *state)
2626 {
2627 struct si_context *sctx = (struct si_context *)ctx;
2628 struct pipe_constant_buffer constbuf = {0};
2629 struct r600_surface *surf = NULL;
2630 struct r600_texture *rtex;
2631 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2632 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2633 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2634 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2635 bool old_has_stencil =
2636 old_has_zsbuf &&
2637 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2638 bool unbound = false;
2639 int i;
2640
2641 si_update_fb_dirtiness_after_rendering(sctx);
2642
2643 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2644 if (!sctx->framebuffer.state.cbufs[i])
2645 continue;
2646
2647 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2648 if (rtex->dcc_gather_statistics)
2649 vi_separate_dcc_stop_query(ctx, rtex);
2650 }
2651
2652 /* Disable DCC if the formats are incompatible. */
2653 for (i = 0; i < state->nr_cbufs; i++) {
2654 if (!state->cbufs[i])
2655 continue;
2656
2657 surf = (struct r600_surface*)state->cbufs[i];
2658 rtex = (struct r600_texture*)surf->base.texture;
2659
2660 if (!surf->dcc_incompatible)
2661 continue;
2662
2663 /* Since the DCC decompression calls back into set_framebuffer-
2664 * _state, we need to unbind the framebuffer, so that
2665 * vi_separate_dcc_stop_query isn't called twice with the same
2666 * color buffer.
2667 */
2668 if (!unbound) {
2669 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2670 unbound = true;
2671 }
2672
2673 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2674 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2675 sctx->b.decompress_dcc(ctx, rtex);
2676
2677 surf->dcc_incompatible = false;
2678 }
2679
2680 /* Only flush TC when changing the framebuffer state, because
2681 * the only client not using TC that can change textures is
2682 * the framebuffer.
2683 *
2684 * Wait for compute shaders because of possible transitions:
2685 * - FB write -> shader read
2686 * - shader write -> FB read
2687 *
2688 * DB caches are flushed on demand (using si_decompress_textures).
2689 *
2690 * When MSAA is enabled, CB and TC caches are flushed on demand
2691 * (after FMASK decompression). Shader write -> FB read transitions
2692 * cannot happen for MSAA textures, because MSAA shader images are
2693 * not supported.
2694 *
2695 * Only flush and wait for CB if there is actually a bound color buffer.
2696 */
2697 if (sctx->framebuffer.nr_samples <= 1 &&
2698 sctx->framebuffer.state.nr_cbufs)
2699 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2700 sctx->framebuffer.CB_has_shader_readable_metadata);
2701
2702 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2703
2704 /* u_blitter doesn't invoke depth decompression when it does multiple
2705 * blits in a row, but the only case when it matters for DB is when
2706 * doing generate_mipmap. So here we flush DB manually between
2707 * individual generate_mipmap blits.
2708 * Note that lower mipmap levels aren't compressed.
2709 */
2710 if (sctx->generate_mipmap_for_depth) {
2711 si_make_DB_shader_coherent(sctx, 1, false,
2712 sctx->framebuffer.DB_has_shader_readable_metadata);
2713 } else if (sctx->b.chip_class == GFX9) {
2714 /* It appears that DB metadata "leaks" in a sequence of:
2715 * - depth clear
2716 * - DCC decompress for shader image writes (with DB disabled)
2717 * - render with DEPTH_BEFORE_SHADER=1
2718 * Flushing DB metadata works around the problem.
2719 */
2720 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2721 }
2722
2723 /* Take the maximum of the old and new count. If the new count is lower,
2724 * dirtying is needed to disable the unbound colorbuffers.
2725 */
2726 sctx->framebuffer.dirty_cbufs |=
2727 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2728 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2729
2730 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2731 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2732
2733 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2734 sctx->framebuffer.spi_shader_col_format = 0;
2735 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2736 sctx->framebuffer.spi_shader_col_format_blend = 0;
2737 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2738 sctx->framebuffer.color_is_int8 = 0;
2739 sctx->framebuffer.color_is_int10 = 0;
2740
2741 sctx->framebuffer.compressed_cb_mask = 0;
2742 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2743 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2744 sctx->framebuffer.any_dst_linear = false;
2745 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2746 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2747
2748 for (i = 0; i < state->nr_cbufs; i++) {
2749 if (!state->cbufs[i])
2750 continue;
2751
2752 surf = (struct r600_surface*)state->cbufs[i];
2753 rtex = (struct r600_texture*)surf->base.texture;
2754
2755 if (!surf->color_initialized) {
2756 si_initialize_color_surface(sctx, surf);
2757 }
2758
2759 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2760 sctx->framebuffer.spi_shader_col_format |=
2761 surf->spi_shader_col_format << (i * 4);
2762 sctx->framebuffer.spi_shader_col_format_alpha |=
2763 surf->spi_shader_col_format_alpha << (i * 4);
2764 sctx->framebuffer.spi_shader_col_format_blend |=
2765 surf->spi_shader_col_format_blend << (i * 4);
2766 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2767 surf->spi_shader_col_format_blend_alpha << (i * 4);
2768
2769 if (surf->color_is_int8)
2770 sctx->framebuffer.color_is_int8 |= 1 << i;
2771 if (surf->color_is_int10)
2772 sctx->framebuffer.color_is_int10 |= 1 << i;
2773
2774 if (rtex->fmask.size) {
2775 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2776 }
2777
2778 if (rtex->surface.is_linear)
2779 sctx->framebuffer.any_dst_linear = true;
2780
2781 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2782 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2783
2784 r600_context_add_resource_size(ctx, surf->base.texture);
2785
2786 p_atomic_inc(&rtex->framebuffers_bound);
2787
2788 if (rtex->dcc_gather_statistics) {
2789 /* Dirty tracking must be enabled for DCC usage analysis. */
2790 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2791 vi_separate_dcc_start_query(ctx, rtex);
2792 }
2793 }
2794
2795 struct r600_texture *zstex = NULL;
2796
2797 if (state->zsbuf) {
2798 surf = (struct r600_surface*)state->zsbuf;
2799 zstex = (struct r600_texture*)surf->base.texture;
2800
2801 if (!surf->depth_initialized) {
2802 si_init_depth_surface(sctx, surf);
2803 }
2804
2805 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2806 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2807
2808 r600_context_add_resource_size(ctx, surf->base.texture);
2809 }
2810
2811 si_update_poly_offset_state(sctx);
2812 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2813 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2814
2815 if (sctx->screen->dpbb_allowed)
2816 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2817
2818 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2819 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2820
2821 if (sctx->screen->has_out_of_order_rast &&
2822 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2823 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2824 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2825 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2826
2827 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2828 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2829 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2830
2831 /* Set sample locations as fragment shader constants. */
2832 switch (sctx->framebuffer.nr_samples) {
2833 case 1:
2834 constbuf.user_buffer = sctx->b.sample_locations_1x;
2835 break;
2836 case 2:
2837 constbuf.user_buffer = sctx->b.sample_locations_2x;
2838 break;
2839 case 4:
2840 constbuf.user_buffer = sctx->b.sample_locations_4x;
2841 break;
2842 case 8:
2843 constbuf.user_buffer = sctx->b.sample_locations_8x;
2844 break;
2845 case 16:
2846 constbuf.user_buffer = sctx->b.sample_locations_16x;
2847 break;
2848 default:
2849 R600_ERR("Requested an invalid number of samples %i.\n",
2850 sctx->framebuffer.nr_samples);
2851 assert(0);
2852 }
2853 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2854 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2855
2856 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2857 }
2858
2859 sctx->do_update_shaders = true;
2860
2861 if (!sctx->decompression_enabled) {
2862 /* Prevent textures decompression when the framebuffer state
2863 * changes come from the decompression passes themselves.
2864 */
2865 sctx->need_check_render_feedback = true;
2866 }
2867 }
2868
2869 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2870 {
2871 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2872 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2873 unsigned i, nr_cbufs = state->nr_cbufs;
2874 struct r600_texture *tex = NULL;
2875 struct r600_surface *cb = NULL;
2876 unsigned cb_color_info = 0;
2877
2878 /* Colorbuffers. */
2879 for (i = 0; i < nr_cbufs; i++) {
2880 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2881 unsigned cb_color_attrib;
2882
2883 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2884 continue;
2885
2886 cb = (struct r600_surface*)state->cbufs[i];
2887 if (!cb) {
2888 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2889 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2890 continue;
2891 }
2892
2893 tex = (struct r600_texture *)cb->base.texture;
2894 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2895 &tex->resource, RADEON_USAGE_READWRITE,
2896 tex->resource.b.b.nr_samples > 1 ?
2897 RADEON_PRIO_COLOR_BUFFER_MSAA :
2898 RADEON_PRIO_COLOR_BUFFER);
2899
2900 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2901 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2902 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2903 RADEON_PRIO_CMASK);
2904 }
2905
2906 if (tex->dcc_separate_buffer)
2907 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2908 tex->dcc_separate_buffer,
2909 RADEON_USAGE_READWRITE,
2910 RADEON_PRIO_DCC);
2911
2912 /* Compute mutable surface parameters. */
2913 cb_color_base = tex->resource.gpu_address >> 8;
2914 cb_color_fmask = 0;
2915 cb_dcc_base = 0;
2916 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2917 cb_color_attrib = cb->cb_color_attrib;
2918
2919 if (tex->fmask.size) {
2920 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2921 cb_color_fmask |= tex->fmask.tile_swizzle;
2922 }
2923
2924 /* Set up DCC. */
2925 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2926 bool is_msaa_resolve_dst = state->cbufs[0] &&
2927 state->cbufs[0]->texture->nr_samples > 1 &&
2928 state->cbufs[1] == &cb->base &&
2929 state->cbufs[1]->texture->nr_samples <= 1;
2930
2931 if (!is_msaa_resolve_dst)
2932 cb_color_info |= S_028C70_DCC_ENABLE(1);
2933
2934 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2935 tex->dcc_offset) >> 8;
2936 cb_dcc_base |= tex->surface.tile_swizzle;
2937 }
2938
2939 if (sctx->b.chip_class >= GFX9) {
2940 struct gfx9_surf_meta_flags meta;
2941
2942 if (tex->dcc_offset)
2943 meta = tex->surface.u.gfx9.dcc;
2944 else
2945 meta = tex->surface.u.gfx9.cmask;
2946
2947 /* Set mutable surface parameters. */
2948 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2949 cb_color_base |= tex->surface.tile_swizzle;
2950 if (!tex->fmask.size)
2951 cb_color_fmask = cb_color_base;
2952 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2953 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2954 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2955 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2956
2957 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2958 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2959 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2960 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2961 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2962 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2963 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2964 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2965 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2966 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2967 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2968 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2969 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2970 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2971 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2972 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2973
2974 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2975 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2976 } else {
2977 /* Compute mutable surface parameters (SI-CI-VI). */
2978 const struct legacy_surf_level *level_info =
2979 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2980 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2981 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2982
2983 cb_color_base += level_info->offset >> 8;
2984 /* Only macrotiled modes can set tile swizzle. */
2985 if (level_info->mode == RADEON_SURF_MODE_2D)
2986 cb_color_base |= tex->surface.tile_swizzle;
2987
2988 if (!tex->fmask.size)
2989 cb_color_fmask = cb_color_base;
2990 if (cb_dcc_base)
2991 cb_dcc_base += level_info->dcc_offset >> 8;
2992
2993 pitch_tile_max = level_info->nblk_x / 8 - 1;
2994 slice_tile_max = level_info->nblk_x *
2995 level_info->nblk_y / 64 - 1;
2996 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2997
2998 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2999 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3000 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3001
3002 if (tex->fmask.size) {
3003 if (sctx->b.chip_class >= CIK)
3004 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3005 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3006 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3007 } else {
3008 /* This must be set for fast clear to work without FMASK. */
3009 if (sctx->b.chip_class >= CIK)
3010 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3011 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3012 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3013 }
3014
3015 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3016 sctx->b.chip_class >= VI ? 14 : 13);
3017 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3018 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3019 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3020 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3021 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3022 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3023 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3024 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3025 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3026 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3027 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3028 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3029 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3030
3031 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3032 radeon_emit(cs, cb_dcc_base);
3033 }
3034 }
3035 for (; i < 8 ; i++)
3036 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3037 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3038
3039 /* ZS buffer. */
3040 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3041 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3042 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3043
3044 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3045 &rtex->resource, RADEON_USAGE_READWRITE,
3046 zb->base.texture->nr_samples > 1 ?
3047 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3048 RADEON_PRIO_DEPTH_BUFFER);
3049
3050 if (sctx->b.chip_class >= GFX9) {
3051 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3052 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3053 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3054 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3055
3056 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3057 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3058 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3059 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3060 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3061 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3062 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3063 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3064 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3065 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3066 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3067 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3068
3069 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3070 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3071 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3072 } else {
3073 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3074
3075 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3076 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3077 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3078 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3079 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3080 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3081 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3082 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3083 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3084 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3085 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3086 }
3087
3088 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3089 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3090 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3091
3092 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3093 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3094 } else if (sctx->framebuffer.dirty_zsbuf) {
3095 if (sctx->b.chip_class >= GFX9)
3096 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3097 else
3098 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3099
3100 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3101 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3102 }
3103
3104 /* Framebuffer dimensions. */
3105 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3106 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3107 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3108
3109 if (sctx->screen->dfsm_allowed) {
3110 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3111 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3112 }
3113
3114 sctx->framebuffer.dirty_cbufs = 0;
3115 sctx->framebuffer.dirty_zsbuf = false;
3116 }
3117
3118 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3119 struct r600_atom *atom)
3120 {
3121 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3122 unsigned nr_samples = sctx->framebuffer.nr_samples;
3123 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3124
3125 /* Smoothing (only possible with nr_samples == 1) uses the same
3126 * sample locations as the MSAA it simulates.
3127 */
3128 if (nr_samples <= 1 && sctx->smoothing_enabled)
3129 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3130
3131 /* On Polaris, the small primitive filter uses the sample locations
3132 * even when MSAA is off, so we need to make sure they're set to 0.
3133 */
3134 if (has_msaa_sample_loc_bug)
3135 nr_samples = MAX2(nr_samples, 1);
3136
3137 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3138 sctx->msaa_sample_locs.nr_samples = nr_samples;
3139 cayman_emit_msaa_sample_locs(cs, nr_samples);
3140 }
3141
3142 if (sctx->b.family >= CHIP_POLARIS10) {
3143 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3144 unsigned small_prim_filter_cntl =
3145 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3146 /* line bug */
3147 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3148
3149 /* The alternative of setting sample locations to 0 would
3150 * require a DB flush to avoid Z errors, see
3151 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3152 */
3153 if (has_msaa_sample_loc_bug &&
3154 sctx->framebuffer.nr_samples > 1 &&
3155 rs && !rs->multisample_enable)
3156 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3157
3158 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3159 small_prim_filter_cntl);
3160 }
3161 }
3162
3163 static bool si_out_of_order_rasterization(struct si_context *sctx)
3164 {
3165 struct si_state_blend *blend = sctx->queued.named.blend;
3166 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3167
3168 if (!sctx->screen->has_out_of_order_rast)
3169 return false;
3170
3171 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3172
3173 if (blend) {
3174 colormask &= blend->cb_target_enabled_4bit;
3175 } else {
3176 colormask = 0;
3177 }
3178
3179 /* Conservative: No logic op. */
3180 if (colormask && blend->logicop_enable)
3181 return false;
3182
3183 struct si_dsa_order_invariance dsa_order_invariant = {
3184 .zs = true, .pass_set = true, .pass_last = false
3185 };
3186
3187 if (sctx->framebuffer.state.zsbuf) {
3188 struct r600_texture *zstex =
3189 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3190 bool has_stencil = zstex->surface.has_stencil;
3191 dsa_order_invariant = dsa->order_invariance[has_stencil];
3192 if (!dsa_order_invariant.zs)
3193 return false;
3194
3195 /* The set of PS invocations is always order invariant,
3196 * except when early Z/S tests are requested. */
3197 if (sctx->ps_shader.cso &&
3198 sctx->ps_shader.cso->info.writes_memory &&
3199 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3200 !dsa_order_invariant.pass_set)
3201 return false;
3202
3203 if (sctx->b.num_perfect_occlusion_queries != 0 &&
3204 !dsa_order_invariant.pass_set)
3205 return false;
3206 }
3207
3208 if (!colormask)
3209 return true;
3210
3211 bool blend_enabled = (colormask & blend->blend_enable_4bit) != 0;
3212
3213 if (blend_enabled)
3214 return false; /* TODO */
3215
3216 return dsa_order_invariant.pass_last;
3217 }
3218
3219 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3220 {
3221 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3222 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
3223 /* 33% faster rendering to linear color buffers */
3224 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3225 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3226 unsigned sc_mode_cntl_1 =
3227 S_028A4C_WALK_SIZE(dst_is_linear) |
3228 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3229 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3230 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3231 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3232 /* always 1: */
3233 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3234 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3235 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3236 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3237 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3238 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3239
3240 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
3241 sctx->ps_iter_samples,
3242 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
3243 sc_mode_cntl_1);
3244
3245 /* GFX9: Flush DFSM when the AA mode changes. */
3246 if (sctx->screen->dfsm_allowed) {
3247 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3248 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3249 }
3250 }
3251
3252 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3253 {
3254 struct si_context *sctx = (struct si_context *)ctx;
3255
3256 if (sctx->ps_iter_samples == min_samples)
3257 return;
3258
3259 sctx->ps_iter_samples = min_samples;
3260 sctx->do_update_shaders = true;
3261
3262 if (sctx->framebuffer.nr_samples > 1)
3263 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3264 if (sctx->screen->dpbb_allowed)
3265 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3266 }
3267
3268 /*
3269 * Samplers
3270 */
3271
3272 /**
3273 * Build the sampler view descriptor for a buffer texture.
3274 * @param state 256-bit descriptor; only the high 128 bits are filled in
3275 */
3276 void
3277 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3278 enum pipe_format format,
3279 unsigned offset, unsigned size,
3280 uint32_t *state)
3281 {
3282 const struct util_format_description *desc;
3283 int first_non_void;
3284 unsigned stride;
3285 unsigned num_records;
3286 unsigned num_format, data_format;
3287
3288 desc = util_format_description(format);
3289 first_non_void = util_format_get_first_non_void_channel(format);
3290 stride = desc->block.bits / 8;
3291 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3292 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3293
3294 num_records = size / stride;
3295 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3296
3297 /* The NUM_RECORDS field has a different meaning depending on the chip,
3298 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3299 *
3300 * SI-CIK:
3301 * - If STRIDE == 0, it's in byte units.
3302 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3303 *
3304 * VI:
3305 * - For SMEM and STRIDE == 0, it's in byte units.
3306 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3307 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3308 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3309 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3310 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3311 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3312 * That way the same descriptor can be used by both SMEM and VMEM.
3313 *
3314 * GFX9:
3315 * - For SMEM and STRIDE == 0, it's in byte units.
3316 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3317 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3318 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3319 */
3320 if (screen->b.chip_class >= GFX9)
3321 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3322 * from STRIDE to bytes. This works around it by setting
3323 * NUM_RECORDS to at least the size of one element, so that
3324 * the first element is readable when IDXEN == 0.
3325 *
3326 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3327 * IDXEN is enforced?
3328 */
3329 num_records = num_records ? MAX2(num_records, stride) : 0;
3330 else if (screen->b.chip_class == VI)
3331 num_records *= stride;
3332
3333 state[4] = 0;
3334 state[5] = S_008F04_STRIDE(stride);
3335 state[6] = num_records;
3336 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3337 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3338 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3339 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3340 S_008F0C_NUM_FORMAT(num_format) |
3341 S_008F0C_DATA_FORMAT(data_format);
3342 }
3343
3344 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3345 {
3346 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3347
3348 if (swizzle[3] == PIPE_SWIZZLE_X) {
3349 /* For the pre-defined border color values (white, opaque
3350 * black, transparent black), the only thing that matters is
3351 * that the alpha channel winds up in the correct place
3352 * (because the RGB channels are all the same) so either of
3353 * these enumerations will work.
3354 */
3355 if (swizzle[2] == PIPE_SWIZZLE_Y)
3356 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3357 else
3358 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3359 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3360 if (swizzle[1] == PIPE_SWIZZLE_Y)
3361 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3362 else
3363 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3364 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3365 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3366 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3367 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3368 }
3369
3370 return bc_swizzle;
3371 }
3372
3373 /**
3374 * Build the sampler view descriptor for a texture.
3375 */
3376 void
3377 si_make_texture_descriptor(struct si_screen *screen,
3378 struct r600_texture *tex,
3379 bool sampler,
3380 enum pipe_texture_target target,
3381 enum pipe_format pipe_format,
3382 const unsigned char state_swizzle[4],
3383 unsigned first_level, unsigned last_level,
3384 unsigned first_layer, unsigned last_layer,
3385 unsigned width, unsigned height, unsigned depth,
3386 uint32_t *state,
3387 uint32_t *fmask_state)
3388 {
3389 struct pipe_resource *res = &tex->resource.b.b;
3390 const struct util_format_description *desc;
3391 unsigned char swizzle[4];
3392 int first_non_void;
3393 unsigned num_format, data_format, type;
3394 uint64_t va;
3395
3396 desc = util_format_description(pipe_format);
3397
3398 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3399 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3400 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3401 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3402
3403 switch (pipe_format) {
3404 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3405 case PIPE_FORMAT_X32_S8X24_UINT:
3406 case PIPE_FORMAT_X8Z24_UNORM:
3407 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3408 break;
3409 case PIPE_FORMAT_X24S8_UINT:
3410 /*
3411 * X24S8 is implemented as an 8_8_8_8 data format, to
3412 * fix texture gathers. This affects at least
3413 * GL45-CTS.texture_cube_map_array.sampling on VI.
3414 */
3415 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3416 break;
3417 default:
3418 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3419 }
3420 } else {
3421 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3422 }
3423
3424 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3425
3426 switch (pipe_format) {
3427 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3428 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3429 break;
3430 default:
3431 if (first_non_void < 0) {
3432 if (util_format_is_compressed(pipe_format)) {
3433 switch (pipe_format) {
3434 case PIPE_FORMAT_DXT1_SRGB:
3435 case PIPE_FORMAT_DXT1_SRGBA:
3436 case PIPE_FORMAT_DXT3_SRGBA:
3437 case PIPE_FORMAT_DXT5_SRGBA:
3438 case PIPE_FORMAT_BPTC_SRGBA:
3439 case PIPE_FORMAT_ETC2_SRGB8:
3440 case PIPE_FORMAT_ETC2_SRGB8A1:
3441 case PIPE_FORMAT_ETC2_SRGBA8:
3442 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3443 break;
3444 case PIPE_FORMAT_RGTC1_SNORM:
3445 case PIPE_FORMAT_LATC1_SNORM:
3446 case PIPE_FORMAT_RGTC2_SNORM:
3447 case PIPE_FORMAT_LATC2_SNORM:
3448 case PIPE_FORMAT_ETC2_R11_SNORM:
3449 case PIPE_FORMAT_ETC2_RG11_SNORM:
3450 /* implies float, so use SNORM/UNORM to determine
3451 whether data is signed or not */
3452 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3453 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3454 break;
3455 default:
3456 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3457 break;
3458 }
3459 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3460 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3461 } else {
3462 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3463 }
3464 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3465 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3466 } else {
3467 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3468
3469 switch (desc->channel[first_non_void].type) {
3470 case UTIL_FORMAT_TYPE_FLOAT:
3471 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3472 break;
3473 case UTIL_FORMAT_TYPE_SIGNED:
3474 if (desc->channel[first_non_void].normalized)
3475 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3476 else if (desc->channel[first_non_void].pure_integer)
3477 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3478 else
3479 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3480 break;
3481 case UTIL_FORMAT_TYPE_UNSIGNED:
3482 if (desc->channel[first_non_void].normalized)
3483 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3484 else if (desc->channel[first_non_void].pure_integer)
3485 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3486 else
3487 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3488 }
3489 }
3490 }
3491
3492 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3493 if (data_format == ~0) {
3494 data_format = 0;
3495 }
3496
3497 /* S8 with Z32 HTILE needs a special format. */
3498 if (screen->b.chip_class >= GFX9 &&
3499 pipe_format == PIPE_FORMAT_S8_UINT &&
3500 tex->tc_compatible_htile)
3501 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3502
3503 if (!sampler &&
3504 (res->target == PIPE_TEXTURE_CUBE ||
3505 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3506 (screen->b.chip_class <= VI &&
3507 res->target == PIPE_TEXTURE_3D))) {
3508 /* For the purpose of shader images, treat cube maps and 3D
3509 * textures as 2D arrays. For 3D textures, the address
3510 * calculations for mipmaps are different, so we rely on the
3511 * caller to effectively disable mipmaps.
3512 */
3513 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3514
3515 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3516 } else {
3517 type = si_tex_dim(screen, tex, target, res->nr_samples);
3518 }
3519
3520 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3521 height = 1;
3522 depth = res->array_size;
3523 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3524 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3525 if (sampler || res->target != PIPE_TEXTURE_3D)
3526 depth = res->array_size;
3527 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3528 depth = res->array_size / 6;
3529
3530 state[0] = 0;
3531 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3532 S_008F14_NUM_FORMAT_GFX6(num_format));
3533 state[2] = (S_008F18_WIDTH(width - 1) |
3534 S_008F18_HEIGHT(height - 1) |
3535 S_008F18_PERF_MOD(4));
3536 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3537 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3538 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3539 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3540 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3541 0 : first_level) |
3542 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3543 util_logbase2(res->nr_samples) :
3544 last_level) |
3545 S_008F1C_TYPE(type));
3546 state[4] = 0;
3547 state[5] = S_008F24_BASE_ARRAY(first_layer);
3548 state[6] = 0;
3549 state[7] = 0;
3550
3551 if (screen->b.chip_class >= GFX9) {
3552 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3553
3554 /* Depth is the the last accessible layer on Gfx9.
3555 * The hw doesn't need to know the total number of layers.
3556 */
3557 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3558 state[4] |= S_008F20_DEPTH(depth - 1);
3559 else
3560 state[4] |= S_008F20_DEPTH(last_layer);
3561
3562 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3563 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3564 util_logbase2(res->nr_samples) :
3565 tex->resource.b.b.last_level);
3566 } else {
3567 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3568 state[4] |= S_008F20_DEPTH(depth - 1);
3569 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3570 }
3571
3572 if (tex->dcc_offset) {
3573 unsigned swap = r600_translate_colorswap(pipe_format, false);
3574
3575 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3576 } else {
3577 /* The last dword is unused by hw. The shader uses it to clear
3578 * bits in the first dword of sampler state.
3579 */
3580 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3581 if (first_level == last_level)
3582 state[7] = C_008F30_MAX_ANISO_RATIO;
3583 else
3584 state[7] = 0xffffffff;
3585 }
3586 }
3587
3588 /* Initialize the sampler view for FMASK. */
3589 if (tex->fmask.size) {
3590 uint32_t data_format, num_format;
3591
3592 va = tex->resource.gpu_address + tex->fmask.offset;
3593
3594 if (screen->b.chip_class >= GFX9) {
3595 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3596 switch (res->nr_samples) {
3597 case 2:
3598 num_format = V_008F14_IMG_FMASK_8_2_2;
3599 break;
3600 case 4:
3601 num_format = V_008F14_IMG_FMASK_8_4_4;
3602 break;
3603 case 8:
3604 num_format = V_008F14_IMG_FMASK_32_8_8;
3605 break;
3606 default:
3607 unreachable("invalid nr_samples");
3608 }
3609 } else {
3610 switch (res->nr_samples) {
3611 case 2:
3612 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3613 break;
3614 case 4:
3615 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3616 break;
3617 case 8:
3618 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3619 break;
3620 default:
3621 unreachable("invalid nr_samples");
3622 }
3623 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3624 }
3625
3626 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3627 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3628 S_008F14_DATA_FORMAT_GFX6(data_format) |
3629 S_008F14_NUM_FORMAT_GFX6(num_format);
3630 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3631 S_008F18_HEIGHT(height - 1);
3632 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3633 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3634 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3635 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3636 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3637 fmask_state[4] = 0;
3638 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3639 fmask_state[6] = 0;
3640 fmask_state[7] = 0;
3641
3642 if (screen->b.chip_class >= GFX9) {
3643 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3644 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3645 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3646 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3647 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3648 } else {
3649 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3650 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3651 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3652 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3653 }
3654 }
3655 }
3656
3657 /**
3658 * Create a sampler view.
3659 *
3660 * @param ctx context
3661 * @param texture texture
3662 * @param state sampler view template
3663 * @param width0 width0 override (for compressed textures as int)
3664 * @param height0 height0 override (for compressed textures as int)
3665 * @param force_level set the base address to the level (for compressed textures)
3666 */
3667 struct pipe_sampler_view *
3668 si_create_sampler_view_custom(struct pipe_context *ctx,
3669 struct pipe_resource *texture,
3670 const struct pipe_sampler_view *state,
3671 unsigned width0, unsigned height0,
3672 unsigned force_level)
3673 {
3674 struct si_context *sctx = (struct si_context*)ctx;
3675 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3676 struct r600_texture *tmp = (struct r600_texture*)texture;
3677 unsigned base_level, first_level, last_level;
3678 unsigned char state_swizzle[4];
3679 unsigned height, depth, width;
3680 unsigned last_layer = state->u.tex.last_layer;
3681 enum pipe_format pipe_format;
3682 const struct legacy_surf_level *surflevel;
3683
3684 if (!view)
3685 return NULL;
3686
3687 /* initialize base object */
3688 view->base = *state;
3689 view->base.texture = NULL;
3690 view->base.reference.count = 1;
3691 view->base.context = ctx;
3692
3693 assert(texture);
3694 pipe_resource_reference(&view->base.texture, texture);
3695
3696 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3697 state->format == PIPE_FORMAT_S8X24_UINT ||
3698 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3699 state->format == PIPE_FORMAT_S8_UINT)
3700 view->is_stencil_sampler = true;
3701
3702 /* Buffer resource. */
3703 if (texture->target == PIPE_BUFFER) {
3704 si_make_buffer_descriptor(sctx->screen,
3705 (struct r600_resource *)texture,
3706 state->format,
3707 state->u.buf.offset,
3708 state->u.buf.size,
3709 view->state);
3710 return &view->base;
3711 }
3712
3713 state_swizzle[0] = state->swizzle_r;
3714 state_swizzle[1] = state->swizzle_g;
3715 state_swizzle[2] = state->swizzle_b;
3716 state_swizzle[3] = state->swizzle_a;
3717
3718 base_level = 0;
3719 first_level = state->u.tex.first_level;
3720 last_level = state->u.tex.last_level;
3721 width = width0;
3722 height = height0;
3723 depth = texture->depth0;
3724
3725 if (sctx->b.chip_class <= VI && force_level) {
3726 assert(force_level == first_level &&
3727 force_level == last_level);
3728 base_level = force_level;
3729 first_level = 0;
3730 last_level = 0;
3731 width = u_minify(width, force_level);
3732 height = u_minify(height, force_level);
3733 depth = u_minify(depth, force_level);
3734 }
3735
3736 /* This is not needed if state trackers set last_layer correctly. */
3737 if (state->target == PIPE_TEXTURE_1D ||
3738 state->target == PIPE_TEXTURE_2D ||
3739 state->target == PIPE_TEXTURE_RECT ||
3740 state->target == PIPE_TEXTURE_CUBE)
3741 last_layer = state->u.tex.first_layer;
3742
3743 /* Texturing with separate depth and stencil. */
3744 pipe_format = state->format;
3745
3746 /* Depth/stencil texturing sometimes needs separate texture. */
3747 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3748 if (!tmp->flushed_depth_texture &&
3749 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3750 pipe_resource_reference(&view->base.texture, NULL);
3751 FREE(view);
3752 return NULL;
3753 }
3754
3755 assert(tmp->flushed_depth_texture);
3756
3757 /* Override format for the case where the flushed texture
3758 * contains only Z or only S.
3759 */
3760 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3761 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3762
3763 tmp = tmp->flushed_depth_texture;
3764 }
3765
3766 surflevel = tmp->surface.u.legacy.level;
3767
3768 if (tmp->db_compatible) {
3769 if (!view->is_stencil_sampler)
3770 pipe_format = tmp->db_render_format;
3771
3772 switch (pipe_format) {
3773 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3774 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3775 break;
3776 case PIPE_FORMAT_X8Z24_UNORM:
3777 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3778 /* Z24 is always stored like this for DB
3779 * compatibility.
3780 */
3781 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3782 break;
3783 case PIPE_FORMAT_X24S8_UINT:
3784 case PIPE_FORMAT_S8X24_UINT:
3785 case PIPE_FORMAT_X32_S8X24_UINT:
3786 pipe_format = PIPE_FORMAT_S8_UINT;
3787 surflevel = tmp->surface.u.legacy.stencil_level;
3788 break;
3789 default:;
3790 }
3791 }
3792
3793 view->dcc_incompatible =
3794 vi_dcc_formats_are_incompatible(texture,
3795 state->u.tex.first_level,
3796 state->format);
3797
3798 si_make_texture_descriptor(sctx->screen, tmp, true,
3799 state->target, pipe_format, state_swizzle,
3800 first_level, last_level,
3801 state->u.tex.first_layer, last_layer,
3802 width, height, depth,
3803 view->state, view->fmask_state);
3804
3805 view->base_level_info = &surflevel[base_level];
3806 view->base_level = base_level;
3807 view->block_width = util_format_get_blockwidth(pipe_format);
3808 return &view->base;
3809 }
3810
3811 static struct pipe_sampler_view *
3812 si_create_sampler_view(struct pipe_context *ctx,
3813 struct pipe_resource *texture,
3814 const struct pipe_sampler_view *state)
3815 {
3816 return si_create_sampler_view_custom(ctx, texture, state,
3817 texture ? texture->width0 : 0,
3818 texture ? texture->height0 : 0, 0);
3819 }
3820
3821 static void si_sampler_view_destroy(struct pipe_context *ctx,
3822 struct pipe_sampler_view *state)
3823 {
3824 struct si_sampler_view *view = (struct si_sampler_view *)state;
3825
3826 pipe_resource_reference(&state->texture, NULL);
3827 FREE(view);
3828 }
3829
3830 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3831 {
3832 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3833 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3834 (linear_filter &&
3835 (wrap == PIPE_TEX_WRAP_CLAMP ||
3836 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3837 }
3838
3839 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3840 {
3841 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3842 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3843
3844 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3845 state->border_color.ui[2] || state->border_color.ui[3]) &&
3846 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3847 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3848 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3849 }
3850
3851 static void *si_create_sampler_state(struct pipe_context *ctx,
3852 const struct pipe_sampler_state *state)
3853 {
3854 struct si_context *sctx = (struct si_context *)ctx;
3855 struct r600_common_screen *rscreen = sctx->b.screen;
3856 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3857 unsigned border_color_type, border_color_index = 0;
3858 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3859 : state->max_anisotropy;
3860 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3861
3862 if (!rstate) {
3863 return NULL;
3864 }
3865
3866 if (!sampler_state_needs_border_color(state))
3867 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3868 else if (state->border_color.f[0] == 0 &&
3869 state->border_color.f[1] == 0 &&
3870 state->border_color.f[2] == 0 &&
3871 state->border_color.f[3] == 0)
3872 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3873 else if (state->border_color.f[0] == 0 &&
3874 state->border_color.f[1] == 0 &&
3875 state->border_color.f[2] == 0 &&
3876 state->border_color.f[3] == 1)
3877 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3878 else if (state->border_color.f[0] == 1 &&
3879 state->border_color.f[1] == 1 &&
3880 state->border_color.f[2] == 1 &&
3881 state->border_color.f[3] == 1)
3882 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3883 else {
3884 int i;
3885
3886 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3887
3888 /* Check if the border has been uploaded already. */
3889 for (i = 0; i < sctx->border_color_count; i++)
3890 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3891 sizeof(state->border_color)) == 0)
3892 break;
3893
3894 if (i >= SI_MAX_BORDER_COLORS) {
3895 /* Getting 4096 unique border colors is very unlikely. */
3896 fprintf(stderr, "radeonsi: The border color table is full. "
3897 "Any new border colors will be just black. "
3898 "Please file a bug.\n");
3899 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3900 } else {
3901 if (i == sctx->border_color_count) {
3902 /* Upload a new border color. */
3903 memcpy(&sctx->border_color_table[i], &state->border_color,
3904 sizeof(state->border_color));
3905 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3906 &state->border_color,
3907 sizeof(state->border_color));
3908 sctx->border_color_count++;
3909 }
3910
3911 border_color_index = i;
3912 }
3913 }
3914
3915 #ifdef DEBUG
3916 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3917 #endif
3918 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3919 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3920 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3921 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3922 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3923 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3924 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3925 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3926 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3927 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3928 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3929 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3930 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3931 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3932 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3933 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3934 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3935 S_008F38_MIP_POINT_PRECLAMP(1) |
3936 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3937 S_008F38_FILTER_PREC_FIX(1) |
3938 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3939 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3940 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3941 return rstate;
3942 }
3943
3944 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3945 {
3946 struct si_context *sctx = (struct si_context *)ctx;
3947
3948 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3949 return;
3950
3951 sctx->sample_mask.sample_mask = sample_mask;
3952 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3953 }
3954
3955 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3956 {
3957 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3958 unsigned mask = sctx->sample_mask.sample_mask;
3959
3960 /* Needed for line and polygon smoothing as well as for the Polaris
3961 * small primitive filter. We expect the state tracker to take care of
3962 * this for us.
3963 */
3964 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3965 (mask & 1 && sctx->blitter->running));
3966
3967 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3968 radeon_emit(cs, mask | (mask << 16));
3969 radeon_emit(cs, mask | (mask << 16));
3970 }
3971
3972 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3973 {
3974 #ifdef DEBUG
3975 struct si_sampler_state *s = state;
3976
3977 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3978 s->magic = 0;
3979 #endif
3980 free(state);
3981 }
3982
3983 /*
3984 * Vertex elements & buffers
3985 */
3986
3987 static void *si_create_vertex_elements(struct pipe_context *ctx,
3988 unsigned count,
3989 const struct pipe_vertex_element *elements)
3990 {
3991 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3992 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
3993 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3994 int i;
3995
3996 assert(count <= SI_MAX_ATTRIBS);
3997 if (!v)
3998 return NULL;
3999
4000 v->count = count;
4001 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4002
4003 for (i = 0; i < count; ++i) {
4004 const struct util_format_description *desc;
4005 const struct util_format_channel_description *channel;
4006 unsigned data_format, num_format;
4007 int first_non_void;
4008 unsigned vbo_index = elements[i].vertex_buffer_index;
4009 unsigned char swizzle[4];
4010
4011 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4012 FREE(v);
4013 return NULL;
4014 }
4015
4016 if (elements[i].instance_divisor) {
4017 v->uses_instance_divisors = true;
4018 v->instance_divisors[i] = elements[i].instance_divisor;
4019
4020 if (v->instance_divisors[i] == 1)
4021 v->instance_divisor_is_one |= 1u << i;
4022 else
4023 v->instance_divisor_is_fetched |= 1u << i;
4024 }
4025
4026 if (!used[vbo_index]) {
4027 v->first_vb_use_mask |= 1 << i;
4028 used[vbo_index] = true;
4029 }
4030
4031 desc = util_format_description(elements[i].src_format);
4032 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4033 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4034 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4035 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4036 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4037
4038 v->format_size[i] = desc->block.bits / 8;
4039 v->src_offset[i] = elements[i].src_offset;
4040 v->vertex_buffer_index[i] = vbo_index;
4041
4042 /* The hardware always treats the 2-bit alpha channel as
4043 * unsigned, so a shader workaround is needed. The affected
4044 * chips are VI and older except Stoney (GFX8.1).
4045 */
4046 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4047 sscreen->b.chip_class <= VI &&
4048 sscreen->b.family != CHIP_STONEY) {
4049 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4050 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4051 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4052 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4053 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4054 /* This isn't actually used in OpenGL. */
4055 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4056 }
4057 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4058 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4059 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4060 else
4061 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4062 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4063 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4064 if (channel->normalized) {
4065 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4066 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4067 else
4068 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4069 } else {
4070 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4071 }
4072 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4073 if (channel->normalized) {
4074 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4075 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4076 else
4077 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4078 } else {
4079 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4080 }
4081 }
4082 } else if (channel && channel->size == 64 &&
4083 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4084 switch (desc->nr_channels) {
4085 case 1:
4086 case 2:
4087 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4088 swizzle[0] = PIPE_SWIZZLE_X;
4089 swizzle[1] = PIPE_SWIZZLE_Y;
4090 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4091 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4092 break;
4093 case 3:
4094 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4095 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4096 swizzle[1] = PIPE_SWIZZLE_Y;
4097 swizzle[2] = PIPE_SWIZZLE_0;
4098 swizzle[3] = PIPE_SWIZZLE_0;
4099 break;
4100 case 4:
4101 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4102 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4103 swizzle[1] = PIPE_SWIZZLE_Y;
4104 swizzle[2] = PIPE_SWIZZLE_Z;
4105 swizzle[3] = PIPE_SWIZZLE_W;
4106 break;
4107 default:
4108 assert(0);
4109 }
4110 } else if (channel && desc->nr_channels == 3) {
4111 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4112
4113 if (channel->size == 8) {
4114 if (channel->pure_integer)
4115 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4116 else
4117 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4118 } else if (channel->size == 16) {
4119 if (channel->pure_integer)
4120 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4121 else
4122 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4123 }
4124 }
4125
4126 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4127 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4128 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4129 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4130 S_008F0C_NUM_FORMAT(num_format) |
4131 S_008F0C_DATA_FORMAT(data_format);
4132 }
4133 return v;
4134 }
4135
4136 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4137 {
4138 struct si_context *sctx = (struct si_context *)ctx;
4139 struct si_vertex_elements *old = sctx->vertex_elements;
4140 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4141
4142 sctx->vertex_elements = v;
4143 sctx->vertex_buffers_dirty = true;
4144
4145 if (v &&
4146 (!old ||
4147 old->count != v->count ||
4148 old->uses_instance_divisors != v->uses_instance_divisors ||
4149 v->uses_instance_divisors || /* we don't check which divisors changed */
4150 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4151 sctx->do_update_shaders = true;
4152
4153 if (v && v->instance_divisor_is_fetched) {
4154 struct pipe_constant_buffer cb;
4155
4156 cb.buffer = NULL;
4157 cb.user_buffer = v->instance_divisors;
4158 cb.buffer_offset = 0;
4159 cb.buffer_size = sizeof(uint32_t) * v->count;
4160 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4161 }
4162 }
4163
4164 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4165 {
4166 struct si_context *sctx = (struct si_context *)ctx;
4167
4168 if (sctx->vertex_elements == state)
4169 sctx->vertex_elements = NULL;
4170 FREE(state);
4171 }
4172
4173 static void si_set_vertex_buffers(struct pipe_context *ctx,
4174 unsigned start_slot, unsigned count,
4175 const struct pipe_vertex_buffer *buffers)
4176 {
4177 struct si_context *sctx = (struct si_context *)ctx;
4178 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4179 int i;
4180
4181 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4182
4183 if (buffers) {
4184 for (i = 0; i < count; i++) {
4185 const struct pipe_vertex_buffer *src = buffers + i;
4186 struct pipe_vertex_buffer *dsti = dst + i;
4187 struct pipe_resource *buf = src->buffer.resource;
4188
4189 pipe_resource_reference(&dsti->buffer.resource, buf);
4190 dsti->buffer_offset = src->buffer_offset;
4191 dsti->stride = src->stride;
4192 r600_context_add_resource_size(ctx, buf);
4193 if (buf)
4194 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4195 }
4196 } else {
4197 for (i = 0; i < count; i++) {
4198 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4199 }
4200 }
4201 sctx->vertex_buffers_dirty = true;
4202 }
4203
4204 /*
4205 * Misc
4206 */
4207
4208 static void si_set_tess_state(struct pipe_context *ctx,
4209 const float default_outer_level[4],
4210 const float default_inner_level[2])
4211 {
4212 struct si_context *sctx = (struct si_context *)ctx;
4213 struct pipe_constant_buffer cb;
4214 float array[8];
4215
4216 memcpy(array, default_outer_level, sizeof(float) * 4);
4217 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4218
4219 cb.buffer = NULL;
4220 cb.user_buffer = NULL;
4221 cb.buffer_size = sizeof(array);
4222
4223 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4224 (void*)array, sizeof(array),
4225 &cb.buffer_offset);
4226
4227 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4228 pipe_resource_reference(&cb.buffer, NULL);
4229 }
4230
4231 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4232 {
4233 struct si_context *sctx = (struct si_context *)ctx;
4234
4235 si_update_fb_dirtiness_after_rendering(sctx);
4236
4237 /* Multisample surfaces are flushed in si_decompress_textures. */
4238 if (sctx->framebuffer.nr_samples <= 1 &&
4239 sctx->framebuffer.state.nr_cbufs)
4240 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4241 sctx->framebuffer.CB_has_shader_readable_metadata);
4242 }
4243
4244 /* This only ensures coherency for shader image/buffer stores. */
4245 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4246 {
4247 struct si_context *sctx = (struct si_context *)ctx;
4248
4249 /* Subsequent commands must wait for all shader invocations to
4250 * complete. */
4251 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4252 SI_CONTEXT_CS_PARTIAL_FLUSH;
4253
4254 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4255 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4256 SI_CONTEXT_INV_VMEM_L1;
4257
4258 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4259 PIPE_BARRIER_SHADER_BUFFER |
4260 PIPE_BARRIER_TEXTURE |
4261 PIPE_BARRIER_IMAGE |
4262 PIPE_BARRIER_STREAMOUT_BUFFER |
4263 PIPE_BARRIER_GLOBAL_BUFFER)) {
4264 /* As far as I can tell, L1 contents are written back to L2
4265 * automatically at end of shader, but the contents of other
4266 * L1 caches might still be stale. */
4267 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4268 }
4269
4270 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4271 /* Indices are read through TC L2 since VI.
4272 * L1 isn't used.
4273 */
4274 if (sctx->screen->b.chip_class <= CIK)
4275 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4276 }
4277
4278 /* MSAA color, any depth and any stencil are flushed in
4279 * si_decompress_textures when needed.
4280 */
4281 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4282 sctx->framebuffer.nr_samples <= 1 &&
4283 sctx->framebuffer.state.nr_cbufs) {
4284 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4285
4286 if (sctx->b.chip_class <= VI)
4287 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4288 }
4289
4290 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4291 if (sctx->screen->b.chip_class <= VI &&
4292 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4293 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4294 }
4295
4296 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4297 {
4298 struct pipe_blend_state blend;
4299
4300 memset(&blend, 0, sizeof(blend));
4301 blend.independent_blend_enable = true;
4302 blend.rt[0].colormask = 0xf;
4303 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4304 }
4305
4306 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4307 bool include_draw_vbo)
4308 {
4309 si_need_cs_space((struct si_context*)ctx);
4310 }
4311
4312 static void si_init_config(struct si_context *sctx);
4313
4314 void si_init_state_functions(struct si_context *sctx)
4315 {
4316 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4317 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4318 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4319 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4320 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4321
4322 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4323 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4324 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4325 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4326 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4327 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4328 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4329 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4330 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4331 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4332 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4333
4334 sctx->b.b.create_blend_state = si_create_blend_state;
4335 sctx->b.b.bind_blend_state = si_bind_blend_state;
4336 sctx->b.b.delete_blend_state = si_delete_blend_state;
4337 sctx->b.b.set_blend_color = si_set_blend_color;
4338
4339 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4340 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4341 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4342
4343 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4344 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4345 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4346
4347 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4348 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4349 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4350 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4351 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4352
4353 sctx->b.b.set_clip_state = si_set_clip_state;
4354 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4355
4356 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4357 sctx->b.b.get_sample_position = cayman_get_sample_position;
4358
4359 sctx->b.b.create_sampler_state = si_create_sampler_state;
4360 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4361
4362 sctx->b.b.create_sampler_view = si_create_sampler_view;
4363 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4364
4365 sctx->b.b.set_sample_mask = si_set_sample_mask;
4366
4367 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4368 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4369 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4370 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4371
4372 sctx->b.b.texture_barrier = si_texture_barrier;
4373 sctx->b.b.memory_barrier = si_memory_barrier;
4374 sctx->b.b.set_min_samples = si_set_min_samples;
4375 sctx->b.b.set_tess_state = si_set_tess_state;
4376
4377 sctx->b.b.set_active_query_state = si_set_active_query_state;
4378 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4379 sctx->b.save_qbo_state = si_save_qbo_state;
4380 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4381
4382 sctx->b.b.draw_vbo = si_draw_vbo;
4383
4384 si_init_config(sctx);
4385 }
4386
4387 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4388 {
4389 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4390 }
4391
4392 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4393 struct r600_texture *rtex,
4394 struct radeon_bo_metadata *md)
4395 {
4396 struct si_screen *sscreen = (struct si_screen*)rscreen;
4397 struct pipe_resource *res = &rtex->resource.b.b;
4398 static const unsigned char swizzle[] = {
4399 PIPE_SWIZZLE_X,
4400 PIPE_SWIZZLE_Y,
4401 PIPE_SWIZZLE_Z,
4402 PIPE_SWIZZLE_W
4403 };
4404 uint32_t desc[8], i;
4405 bool is_array = util_resource_is_array_texture(res);
4406
4407 /* DRM 2.x.x doesn't support this. */
4408 if (rscreen->info.drm_major != 3)
4409 return;
4410
4411 assert(rtex->dcc_separate_buffer == NULL);
4412 assert(rtex->fmask.size == 0);
4413
4414 /* Metadata image format format version 1:
4415 * [0] = 1 (metadata format identifier)
4416 * [1] = (VENDOR_ID << 16) | PCI_ID
4417 * [2:9] = image descriptor for the whole resource
4418 * [2] is always 0, because the base address is cleared
4419 * [9] is the DCC offset bits [39:8] from the beginning of
4420 * the buffer
4421 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4422 */
4423
4424 md->metadata[0] = 1; /* metadata image format version 1 */
4425
4426 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4427 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4428
4429 si_make_texture_descriptor(sscreen, rtex, true,
4430 res->target, res->format,
4431 swizzle, 0, res->last_level, 0,
4432 is_array ? res->array_size - 1 : 0,
4433 res->width0, res->height0, res->depth0,
4434 desc, NULL);
4435
4436 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4437 0, 0, rtex->surface.blk_w, false, desc);
4438
4439 /* Clear the base address and set the relative DCC offset. */
4440 desc[0] = 0;
4441 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4442 desc[7] = rtex->dcc_offset >> 8;
4443
4444 /* Dwords [2:9] contain the image descriptor. */
4445 memcpy(&md->metadata[2], desc, sizeof(desc));
4446 md->size_metadata = 10 * 4;
4447
4448 /* Dwords [10:..] contain the mipmap level offsets. */
4449 if (rscreen->chip_class <= VI) {
4450 for (i = 0; i <= res->last_level; i++)
4451 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4452
4453 md->size_metadata += (1 + res->last_level) * 4;
4454 }
4455 }
4456
4457 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4458 struct r600_texture *rtex,
4459 struct radeon_bo_metadata *md)
4460 {
4461 uint32_t *desc = &md->metadata[2];
4462
4463 if (rscreen->chip_class < VI)
4464 return;
4465
4466 /* Return if DCC is enabled. The texture should be set up with it
4467 * already.
4468 */
4469 if (md->size_metadata >= 11 * 4 &&
4470 md->metadata[0] != 0 &&
4471 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4472 G_008F28_COMPRESSION_EN(desc[6])) {
4473 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4474 return;
4475 }
4476
4477 /* Disable DCC. These are always set by texture_from_handle and must
4478 * be cleared here.
4479 */
4480 rtex->dcc_offset = 0;
4481 }
4482
4483 void si_init_screen_state_functions(struct si_screen *sscreen)
4484 {
4485 sscreen->b.b.is_format_supported = si_is_format_supported;
4486 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4487 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4488 }
4489
4490 static void si_set_grbm_gfx_index(struct si_context *sctx,
4491 struct si_pm4_state *pm4, unsigned value)
4492 {
4493 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4494 GRBM_GFX_INDEX;
4495 si_pm4_set_reg(pm4, reg, value);
4496 }
4497
4498 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4499 struct si_pm4_state *pm4, unsigned se)
4500 {
4501 assert(se == ~0 || se < sctx->screen->b.info.max_se);
4502 si_set_grbm_gfx_index(sctx, pm4,
4503 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4504 S_030800_SE_INDEX(se)) |
4505 S_030800_SH_BROADCAST_WRITES(1) |
4506 S_030800_INSTANCE_BROADCAST_WRITES(1));
4507 }
4508
4509 static void
4510 si_write_harvested_raster_configs(struct si_context *sctx,
4511 struct si_pm4_state *pm4,
4512 unsigned raster_config,
4513 unsigned raster_config_1)
4514 {
4515 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4516 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4517 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4518 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4519 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4520 unsigned rb_per_se = num_rb / num_se;
4521 unsigned se_mask[4];
4522 unsigned se;
4523
4524 se_mask[0] = ((1 << rb_per_se) - 1);
4525 se_mask[1] = (se_mask[0] << rb_per_se);
4526 se_mask[2] = (se_mask[1] << rb_per_se);
4527 se_mask[3] = (se_mask[2] << rb_per_se);
4528
4529 se_mask[0] &= rb_mask;
4530 se_mask[1] &= rb_mask;
4531 se_mask[2] &= rb_mask;
4532 se_mask[3] &= rb_mask;
4533
4534 assert(num_se == 1 || num_se == 2 || num_se == 4);
4535 assert(sh_per_se == 1 || sh_per_se == 2);
4536 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4537
4538 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4539 * fields are for, so I'm leaving them as their default
4540 * values. */
4541
4542 for (se = 0; se < num_se; se++) {
4543 unsigned raster_config_se = raster_config;
4544 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4545 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4546 int idx = (se / 2) * 2;
4547
4548 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4549 raster_config_se &= C_028350_SE_MAP;
4550
4551 if (!se_mask[idx]) {
4552 raster_config_se |=
4553 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4554 } else {
4555 raster_config_se |=
4556 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4557 }
4558 }
4559
4560 pkr0_mask &= rb_mask;
4561 pkr1_mask &= rb_mask;
4562 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4563 raster_config_se &= C_028350_PKR_MAP;
4564
4565 if (!pkr0_mask) {
4566 raster_config_se |=
4567 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4568 } else {
4569 raster_config_se |=
4570 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4571 }
4572 }
4573
4574 if (rb_per_se >= 2) {
4575 unsigned rb0_mask = 1 << (se * rb_per_se);
4576 unsigned rb1_mask = rb0_mask << 1;
4577
4578 rb0_mask &= rb_mask;
4579 rb1_mask &= rb_mask;
4580 if (!rb0_mask || !rb1_mask) {
4581 raster_config_se &= C_028350_RB_MAP_PKR0;
4582
4583 if (!rb0_mask) {
4584 raster_config_se |=
4585 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4586 } else {
4587 raster_config_se |=
4588 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4589 }
4590 }
4591
4592 if (rb_per_se > 2) {
4593 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4594 rb1_mask = rb0_mask << 1;
4595 rb0_mask &= rb_mask;
4596 rb1_mask &= rb_mask;
4597 if (!rb0_mask || !rb1_mask) {
4598 raster_config_se &= C_028350_RB_MAP_PKR1;
4599
4600 if (!rb0_mask) {
4601 raster_config_se |=
4602 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4603 } else {
4604 raster_config_se |=
4605 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4606 }
4607 }
4608 }
4609 }
4610
4611 si_set_grbm_gfx_index_se(sctx, pm4, se);
4612 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4613 }
4614 si_set_grbm_gfx_index(sctx, pm4, ~0);
4615
4616 if (sctx->b.chip_class >= CIK) {
4617 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4618 (!se_mask[2] && !se_mask[3]))) {
4619 raster_config_1 &= C_028354_SE_PAIR_MAP;
4620
4621 if (!se_mask[0] && !se_mask[1]) {
4622 raster_config_1 |=
4623 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4624 } else {
4625 raster_config_1 |=
4626 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4627 }
4628 }
4629
4630 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4631 }
4632 }
4633
4634 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4635 {
4636 struct si_screen *sscreen = sctx->screen;
4637 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4638 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4639 unsigned raster_config, raster_config_1;
4640
4641 switch (sctx->b.family) {
4642 case CHIP_TAHITI:
4643 case CHIP_PITCAIRN:
4644 raster_config = 0x2a00126a;
4645 raster_config_1 = 0x00000000;
4646 break;
4647 case CHIP_VERDE:
4648 raster_config = 0x0000124a;
4649 raster_config_1 = 0x00000000;
4650 break;
4651 case CHIP_OLAND:
4652 raster_config = 0x00000082;
4653 raster_config_1 = 0x00000000;
4654 break;
4655 case CHIP_HAINAN:
4656 raster_config = 0x00000000;
4657 raster_config_1 = 0x00000000;
4658 break;
4659 case CHIP_BONAIRE:
4660 raster_config = 0x16000012;
4661 raster_config_1 = 0x00000000;
4662 break;
4663 case CHIP_HAWAII:
4664 raster_config = 0x3a00161a;
4665 raster_config_1 = 0x0000002e;
4666 break;
4667 case CHIP_FIJI:
4668 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4669 /* old kernels with old tiling config */
4670 raster_config = 0x16000012;
4671 raster_config_1 = 0x0000002a;
4672 } else {
4673 raster_config = 0x3a00161a;
4674 raster_config_1 = 0x0000002e;
4675 }
4676 break;
4677 case CHIP_POLARIS10:
4678 raster_config = 0x16000012;
4679 raster_config_1 = 0x0000002a;
4680 break;
4681 case CHIP_POLARIS11:
4682 case CHIP_POLARIS12:
4683 raster_config = 0x16000012;
4684 raster_config_1 = 0x00000000;
4685 break;
4686 case CHIP_TONGA:
4687 raster_config = 0x16000012;
4688 raster_config_1 = 0x0000002a;
4689 break;
4690 case CHIP_ICELAND:
4691 if (num_rb == 1)
4692 raster_config = 0x00000000;
4693 else
4694 raster_config = 0x00000002;
4695 raster_config_1 = 0x00000000;
4696 break;
4697 case CHIP_CARRIZO:
4698 raster_config = 0x00000002;
4699 raster_config_1 = 0x00000000;
4700 break;
4701 case CHIP_KAVERI:
4702 /* KV should be 0x00000002, but that causes problems with radeon */
4703 raster_config = 0x00000000; /* 0x00000002 */
4704 raster_config_1 = 0x00000000;
4705 break;
4706 case CHIP_KABINI:
4707 case CHIP_MULLINS:
4708 case CHIP_STONEY:
4709 raster_config = 0x00000000;
4710 raster_config_1 = 0x00000000;
4711 break;
4712 default:
4713 fprintf(stderr,
4714 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4715 raster_config = 0x00000000;
4716 raster_config_1 = 0x00000000;
4717 }
4718
4719 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4720 /* Always use the default config when all backends are enabled
4721 * (or when we failed to determine the enabled backends).
4722 */
4723 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4724 raster_config);
4725 if (sctx->b.chip_class >= CIK)
4726 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4727 raster_config_1);
4728 } else {
4729 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4730 }
4731 }
4732
4733 static void si_init_config(struct si_context *sctx)
4734 {
4735 struct si_screen *sscreen = sctx->screen;
4736 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4737 bool has_clear_state = sscreen->has_clear_state;
4738 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4739
4740 /* Only SI can disable CLEAR_STATE for now. */
4741 assert(has_clear_state || sscreen->b.chip_class == SI);
4742
4743 if (!pm4)
4744 return;
4745
4746 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4747 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4748 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4749 si_pm4_cmd_end(pm4, false);
4750
4751 if (has_clear_state) {
4752 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4753 si_pm4_cmd_add(pm4, 0);
4754 si_pm4_cmd_end(pm4, false);
4755 }
4756
4757 if (sctx->b.chip_class <= VI)
4758 si_set_raster_config(sctx, pm4);
4759
4760 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4761 if (!has_clear_state)
4762 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4763
4764 /* FIXME calculate these values somehow ??? */
4765 if (sctx->b.chip_class <= VI) {
4766 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4767 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4768 }
4769
4770 if (!has_clear_state) {
4771 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4772 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4773 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4774 }
4775
4776 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4777 if (!has_clear_state)
4778 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4779 if (sctx->b.chip_class < CIK)
4780 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4781 S_008A14_CLIP_VTX_REORDER_ENA(1));
4782
4783 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4784 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4785
4786 if (!has_clear_state)
4787 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4788
4789 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4790 * I don't know why. Deduced by trial and error.
4791 */
4792 if (sctx->b.chip_class <= CIK) {
4793 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4794 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4795 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4796 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4797 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4798 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4799 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4800 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4801 }
4802
4803 if (!has_clear_state) {
4804 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4805 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4806 S_028230_ER_TRI(0xA) |
4807 S_028230_ER_POINT(0xA) |
4808 S_028230_ER_RECT(0xA) |
4809 /* Required by DX10_DIAMOND_TEST_ENA: */
4810 S_028230_ER_LINE_LR(0x1A) |
4811 S_028230_ER_LINE_RL(0x26) |
4812 S_028230_ER_LINE_TB(0xA) |
4813 S_028230_ER_LINE_BT(0xA));
4814 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4815 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4816 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4817 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4818 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4819 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4820 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4821 }
4822
4823 if (sctx->b.chip_class >= GFX9) {
4824 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4825 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4826 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4827 } else {
4828 /* These registers, when written, also overwrite the CLEAR_STATE
4829 * context, so we can't rely on CLEAR_STATE setting them.
4830 * It would be an issue if there was another UMD changing them.
4831 */
4832 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4833 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4834 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4835 }
4836
4837 if (sctx->b.chip_class >= CIK) {
4838 if (sctx->b.chip_class >= GFX9) {
4839 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4840 } else {
4841 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4842 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4843 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4844
4845 /* If this is 0, Bonaire can hang even if GS isn't being used.
4846 * Other chips are unaffected. These are suboptimal values,
4847 * but we don't use on-chip GS.
4848 */
4849 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4850 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4851 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4852 }
4853 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4854
4855 /* Compute LATE_ALLOC_VS.LIMIT. */
4856 unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
4857 (sscreen->b.info.max_se *
4858 sscreen->b.info.max_sh_per_se);
4859 unsigned late_alloc_limit; /* The limit is per SH. */
4860
4861 if (sctx->b.family == CHIP_KABINI) {
4862 late_alloc_limit = 0; /* Potential hang on Kabini. */
4863 } else if (num_cu_per_sh <= 4) {
4864 /* Too few available compute units per SH. Disallowing
4865 * VS to run on one CU could hurt us more than late VS
4866 * allocation would help.
4867 *
4868 * 2 is the highest safe number that allows us to keep
4869 * all CUs enabled.
4870 */
4871 late_alloc_limit = 2;
4872 } else {
4873 /* This is a good initial value, allowing 1 late_alloc
4874 * wave per SIMD on num_cu - 2.
4875 */
4876 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4877
4878 /* The limit is 0-based, so 0 means 1. */
4879 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4880 late_alloc_limit -= 1;
4881 }
4882
4883 /* VS can't execute on one CU if the limit is > 2. */
4884 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4885 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff));
4886 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4887 S_00B11C_LIMIT(late_alloc_limit));
4888 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4889 }
4890
4891 if (sctx->b.chip_class >= VI) {
4892 unsigned vgt_tess_distribution;
4893
4894 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4895 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4896 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4897
4898 vgt_tess_distribution =
4899 S_028B50_ACCUM_ISOLINE(32) |
4900 S_028B50_ACCUM_TRI(11) |
4901 S_028B50_ACCUM_QUAD(11) |
4902 S_028B50_DONUT_SPLIT(16);
4903
4904 /* Testing with Unigine Heaven extreme tesselation yielded best results
4905 * with TRAP_SPLIT = 3.
4906 */
4907 if (sctx->b.family == CHIP_FIJI ||
4908 sctx->b.family >= CHIP_POLARIS10)
4909 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4910
4911 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4912 } else if (!has_clear_state) {
4913 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4914 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4915 }
4916
4917 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4918 if (sctx->b.chip_class >= CIK)
4919 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4920 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4921 RADEON_PRIO_BORDER_COLORS);
4922
4923 if (sctx->b.chip_class >= GFX9) {
4924 unsigned num_se = sscreen->b.info.max_se;
4925 unsigned pc_lines = 0;
4926
4927 switch (sctx->b.family) {
4928 case CHIP_VEGA10:
4929 pc_lines = 4096;
4930 break;
4931 case CHIP_RAVEN:
4932 pc_lines = 1024;
4933 break;
4934 default:
4935 assert(0);
4936 }
4937
4938 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4939 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4940 S_028C48_MAX_PRIM_PER_BATCH(1023));
4941 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4942 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4943 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4944 }
4945
4946 si_pm4_upload_indirect_buffer(sctx, pm4);
4947 sctx->init_config = pm4;
4948 }