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radeonsi: only set dual source blending for MRT0
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 /* Only set dual source blending for MRT0 to avoid a hang. */
464 if (i >= 1 && blend->dual_src_blend)
465 continue;
466
467 if (!state->rt[j].colormask)
468 continue;
469
470 /* cb_render_state will disable unused ones */
471 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
472
473 if (!state->rt[j].blend_enable) {
474 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
475 continue;
476 }
477
478 /* Blending optimizations for Stoney.
479 * These transformations don't change the behavior.
480 *
481 * First, get rid of DST in the blend factors:
482 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
483 */
484 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
485 PIPE_BLENDFACTOR_DST_COLOR,
486 PIPE_BLENDFACTOR_SRC_COLOR);
487 si_blend_remove_dst(&eqA, &srcA, &dstA,
488 PIPE_BLENDFACTOR_DST_COLOR,
489 PIPE_BLENDFACTOR_SRC_COLOR);
490 si_blend_remove_dst(&eqA, &srcA, &dstA,
491 PIPE_BLENDFACTOR_DST_ALPHA,
492 PIPE_BLENDFACTOR_SRC_ALPHA);
493
494 /* Look up the ideal settings from tables. */
495 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
496 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
497 srcA_opt = si_translate_blend_opt_factor(srcA, true);
498 dstA_opt = si_translate_blend_opt_factor(dstA, true);
499
500 /* Handle interdependencies. */
501 if (si_blend_factor_uses_dst(srcRGB))
502 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
503 if (si_blend_factor_uses_dst(srcA))
504 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
505
506 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
507 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
508 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
509 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
510 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
511
512 /* Set the final value. */
513 sx_mrt_blend_opt[i] =
514 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
515 S_028760_COLOR_DST_OPT(dstRGB_opt) |
516 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
517 S_028760_ALPHA_SRC_OPT(srcA_opt) |
518 S_028760_ALPHA_DST_OPT(dstA_opt) |
519 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
520
521 /* Set blend state. */
522 blend_cntl |= S_028780_ENABLE(1);
523 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
524 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
525 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
526
527 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
528 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
529 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
530 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
531 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
532 }
533 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
534
535 blend->blend_enable_4bit |= 0xfu << (i * 4);
536
537 /* This is only important for formats without alpha. */
538 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
539 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
540 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
541 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
542 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
543 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
544 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
545 }
546
547 if (blend->cb_target_mask) {
548 color_control |= S_028808_MODE(mode);
549 } else {
550 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
551 }
552
553 if (sctx->b.family == CHIP_STONEY) {
554 for (int i = 0; i < 8; i++)
555 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
556 sx_mrt_blend_opt[i]);
557
558 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
559 if (blend->dual_src_blend || state->logicop_enable ||
560 mode == V_028808_CB_RESOLVE)
561 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
562 }
563
564 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
565 return blend;
566 }
567
568 static void *si_create_blend_state(struct pipe_context *ctx,
569 const struct pipe_blend_state *state)
570 {
571 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
572 }
573
574 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
575 {
576 struct si_context *sctx = (struct si_context *)ctx;
577 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
578 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
579 sctx->do_update_shaders = true;
580 }
581
582 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
583 {
584 struct si_context *sctx = (struct si_context *)ctx;
585 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
586 }
587
588 static void si_set_blend_color(struct pipe_context *ctx,
589 const struct pipe_blend_color *state)
590 {
591 struct si_context *sctx = (struct si_context *)ctx;
592
593 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
594 return;
595
596 sctx->blend_color.state = *state;
597 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
598 }
599
600 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
601 {
602 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
603
604 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
605 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
606 }
607
608 /*
609 * Clipping
610 */
611
612 static void si_set_clip_state(struct pipe_context *ctx,
613 const struct pipe_clip_state *state)
614 {
615 struct si_context *sctx = (struct si_context *)ctx;
616 struct pipe_constant_buffer cb;
617
618 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
619 return;
620
621 sctx->clip_state.state = *state;
622 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
623
624 cb.buffer = NULL;
625 cb.user_buffer = state->ucp;
626 cb.buffer_offset = 0;
627 cb.buffer_size = 4*4*8;
628 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
629 pipe_resource_reference(&cb.buffer, NULL);
630 }
631
632 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
633 {
634 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
635
636 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
637 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
638 }
639
640 #define SIX_BITS 0x3F
641
642 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
643 {
644 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
645 struct tgsi_shader_info *info = si_get_vs_info(sctx);
646 unsigned window_space =
647 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
648 unsigned clipdist_mask =
649 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
650
651 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
652 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
653 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
654 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
655 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
656 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
657 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
658 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
659 info->writes_edgeflag ||
660 info->writes_layer ||
661 info->writes_viewport_index) |
662 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
663 (sctx->queued.named.rasterizer->clip_plane_enable &
664 clipdist_mask));
665 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
666 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
667 (clipdist_mask ? 0 :
668 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
669 S_028810_CLIP_DISABLE(window_space));
670
671 /* reuse needs to be set off if we write oViewport */
672 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
673 S_028AB4_REUSE_OFF(info->writes_viewport_index));
674 }
675
676 /*
677 * inferred state between framebuffer and rasterizer
678 */
679 static void si_update_poly_offset_state(struct si_context *sctx)
680 {
681 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
682
683 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
684 return;
685
686 switch (sctx->framebuffer.state.zsbuf->texture->format) {
687 case PIPE_FORMAT_Z16_UNORM:
688 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
689 break;
690 default: /* 24-bit */
691 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
692 break;
693 case PIPE_FORMAT_Z32_FLOAT:
694 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
695 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
696 break;
697 }
698 }
699
700 /*
701 * Rasterizer
702 */
703
704 static uint32_t si_translate_fill(uint32_t func)
705 {
706 switch(func) {
707 case PIPE_POLYGON_MODE_FILL:
708 return V_028814_X_DRAW_TRIANGLES;
709 case PIPE_POLYGON_MODE_LINE:
710 return V_028814_X_DRAW_LINES;
711 case PIPE_POLYGON_MODE_POINT:
712 return V_028814_X_DRAW_POINTS;
713 default:
714 assert(0);
715 return V_028814_X_DRAW_POINTS;
716 }
717 }
718
719 static void *si_create_rs_state(struct pipe_context *ctx,
720 const struct pipe_rasterizer_state *state)
721 {
722 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
723 struct si_pm4_state *pm4 = &rs->pm4;
724 unsigned tmp, i;
725 float psize_min, psize_max;
726
727 if (!rs) {
728 return NULL;
729 }
730
731 rs->scissor_enable = state->scissor;
732 rs->two_side = state->light_twoside;
733 rs->multisample_enable = state->multisample;
734 rs->force_persample_interp = state->force_persample_interp;
735 rs->clip_plane_enable = state->clip_plane_enable;
736 rs->line_stipple_enable = state->line_stipple_enable;
737 rs->poly_stipple_enable = state->poly_stipple_enable;
738 rs->line_smooth = state->line_smooth;
739 rs->poly_smooth = state->poly_smooth;
740 rs->uses_poly_offset = state->offset_point || state->offset_line ||
741 state->offset_tri;
742 rs->clamp_fragment_color = state->clamp_fragment_color;
743 rs->flatshade = state->flatshade;
744 rs->sprite_coord_enable = state->sprite_coord_enable;
745 rs->rasterizer_discard = state->rasterizer_discard;
746 rs->pa_sc_line_stipple = state->line_stipple_enable ?
747 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
748 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
749 rs->pa_cl_clip_cntl =
750 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
751 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
752 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
753 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
754 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
755
756 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
757 S_0286D4_FLAT_SHADE_ENA(1) |
758 S_0286D4_PNT_SPRITE_ENA(1) |
759 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
760 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
761 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
762 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
763 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
764
765 /* point size 12.4 fixed point */
766 tmp = (unsigned)(state->point_size * 8.0);
767 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
768
769 if (state->point_size_per_vertex) {
770 psize_min = util_get_min_point_size(state);
771 psize_max = 8192;
772 } else {
773 /* Force the point size to be as if the vertex output was disabled. */
774 psize_min = state->point_size;
775 psize_max = state->point_size;
776 }
777 /* Divide by two, because 0.5 = 1 pixel. */
778 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
779 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
780 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
781
782 tmp = (unsigned)state->line_width * 8;
783 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
784 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
785 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
786 S_028A48_MSAA_ENABLE(state->multisample ||
787 state->poly_smooth ||
788 state->line_smooth) |
789 S_028A48_VPORT_SCISSOR_ENABLE(1));
790
791 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
792 S_028BE4_PIX_CENTER(state->half_pixel_center) |
793 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
794
795 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
796 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
797 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
798 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
799 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
800 S_028814_FACE(!state->front_ccw) |
801 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
802 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
803 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
804 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
805 state->fill_back != PIPE_POLYGON_MODE_FILL) |
806 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
807 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
808 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
809 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
810
811 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
812 for (i = 0; i < 3; i++) {
813 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
814 float offset_units = state->offset_units;
815 float offset_scale = state->offset_scale * 16.0f;
816 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
817
818 if (!state->offset_units_unscaled) {
819 switch (i) {
820 case 0: /* 16-bit zbuffer */
821 offset_units *= 4.0f;
822 pa_su_poly_offset_db_fmt_cntl =
823 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
824 break;
825 case 1: /* 24-bit zbuffer */
826 offset_units *= 2.0f;
827 pa_su_poly_offset_db_fmt_cntl =
828 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
829 break;
830 case 2: /* 32-bit zbuffer */
831 offset_units *= 1.0f;
832 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
833 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
834 break;
835 }
836 }
837
838 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
839 fui(offset_scale));
840 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
841 fui(offset_units));
842 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
843 fui(offset_scale));
844 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
845 fui(offset_units));
846 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
847 pa_su_poly_offset_db_fmt_cntl);
848 }
849
850 return rs;
851 }
852
853 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
854 {
855 struct si_context *sctx = (struct si_context *)ctx;
856 struct si_state_rasterizer *old_rs =
857 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
858 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
859
860 if (!state)
861 return;
862
863 if (sctx->framebuffer.nr_samples > 1 &&
864 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
865 si_mark_atom_dirty(sctx, &sctx->db_render_state);
866
867 if (sctx->b.family >= CHIP_POLARIS10)
868 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
869 }
870
871 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
872
873 si_pm4_bind_state(sctx, rasterizer, rs);
874 si_update_poly_offset_state(sctx);
875
876 si_mark_atom_dirty(sctx, &sctx->clip_regs);
877 sctx->do_update_shaders = true;
878 }
879
880 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
881 {
882 struct si_context *sctx = (struct si_context *)ctx;
883
884 if (sctx->queued.named.rasterizer == state)
885 si_pm4_bind_state(sctx, poly_offset, NULL);
886 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
887 }
888
889 /*
890 * infeered state between dsa and stencil ref
891 */
892 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
893 {
894 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
895 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
896 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
897
898 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
899 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
900 S_028430_STENCILMASK(dsa->valuemask[0]) |
901 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
902 S_028430_STENCILOPVAL(1));
903 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
904 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
905 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
906 S_028434_STENCILOPVAL_BF(1));
907 }
908
909 static void si_set_stencil_ref(struct pipe_context *ctx,
910 const struct pipe_stencil_ref *state)
911 {
912 struct si_context *sctx = (struct si_context *)ctx;
913
914 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
915 return;
916
917 sctx->stencil_ref.state = *state;
918 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
919 }
920
921
922 /*
923 * DSA
924 */
925
926 static uint32_t si_translate_stencil_op(int s_op)
927 {
928 switch (s_op) {
929 case PIPE_STENCIL_OP_KEEP:
930 return V_02842C_STENCIL_KEEP;
931 case PIPE_STENCIL_OP_ZERO:
932 return V_02842C_STENCIL_ZERO;
933 case PIPE_STENCIL_OP_REPLACE:
934 return V_02842C_STENCIL_REPLACE_TEST;
935 case PIPE_STENCIL_OP_INCR:
936 return V_02842C_STENCIL_ADD_CLAMP;
937 case PIPE_STENCIL_OP_DECR:
938 return V_02842C_STENCIL_SUB_CLAMP;
939 case PIPE_STENCIL_OP_INCR_WRAP:
940 return V_02842C_STENCIL_ADD_WRAP;
941 case PIPE_STENCIL_OP_DECR_WRAP:
942 return V_02842C_STENCIL_SUB_WRAP;
943 case PIPE_STENCIL_OP_INVERT:
944 return V_02842C_STENCIL_INVERT;
945 default:
946 R600_ERR("Unknown stencil op %d", s_op);
947 assert(0);
948 break;
949 }
950 return 0;
951 }
952
953 static void *si_create_dsa_state(struct pipe_context *ctx,
954 const struct pipe_depth_stencil_alpha_state *state)
955 {
956 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
957 struct si_pm4_state *pm4 = &dsa->pm4;
958 unsigned db_depth_control;
959 uint32_t db_stencil_control = 0;
960
961 if (!dsa) {
962 return NULL;
963 }
964
965 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
966 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
967 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
968 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
969
970 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
971 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
972 S_028800_ZFUNC(state->depth.func) |
973 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
974
975 /* stencil */
976 if (state->stencil[0].enabled) {
977 db_depth_control |= S_028800_STENCIL_ENABLE(1);
978 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
979 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
980 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
981 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
982
983 if (state->stencil[1].enabled) {
984 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
985 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
986 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
987 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
988 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
989 }
990 }
991
992 /* alpha */
993 if (state->alpha.enabled) {
994 dsa->alpha_func = state->alpha.func;
995
996 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
997 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
998 } else {
999 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1000 }
1001
1002 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1003 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1004 if (state->depth.bounds_test) {
1005 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1006 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1007 }
1008
1009 return dsa;
1010 }
1011
1012 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct si_context *sctx = (struct si_context *)ctx;
1015 struct si_state_dsa *dsa = state;
1016
1017 if (!state)
1018 return;
1019
1020 si_pm4_bind_state(sctx, dsa, dsa);
1021
1022 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1023 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1024 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1025 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1026 }
1027 sctx->do_update_shaders = true;
1028 }
1029
1030 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1031 {
1032 struct si_context *sctx = (struct si_context *)ctx;
1033 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1034 }
1035
1036 static void *si_create_db_flush_dsa(struct si_context *sctx)
1037 {
1038 struct pipe_depth_stencil_alpha_state dsa = {};
1039
1040 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1041 }
1042
1043 /* DB RENDER STATE */
1044
1045 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1046 {
1047 struct si_context *sctx = (struct si_context*)ctx;
1048
1049 /* Pipeline stat & streamout queries. */
1050 if (enable) {
1051 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1052 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1053 } else {
1054 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1055 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1056 }
1057
1058 /* Occlusion queries. */
1059 if (sctx->occlusion_queries_disabled != !enable) {
1060 sctx->occlusion_queries_disabled = !enable;
1061 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1062 }
1063 }
1064
1065 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1066 {
1067 struct si_context *sctx = (struct si_context*)ctx;
1068
1069 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1070 }
1071
1072 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1073 {
1074 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1075 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1076 unsigned db_shader_control;
1077
1078 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1079
1080 /* DB_RENDER_CONTROL */
1081 if (sctx->dbcb_depth_copy_enabled ||
1082 sctx->dbcb_stencil_copy_enabled) {
1083 radeon_emit(cs,
1084 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1085 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1086 S_028000_COPY_CENTROID(1) |
1087 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1088 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1089 radeon_emit(cs,
1090 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1091 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1092 } else {
1093 radeon_emit(cs,
1094 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1095 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1096 }
1097
1098 /* DB_COUNT_CONTROL (occlusion queries) */
1099 if (sctx->b.num_occlusion_queries > 0 &&
1100 !sctx->occlusion_queries_disabled) {
1101 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1102
1103 if (sctx->b.chip_class >= CIK) {
1104 radeon_emit(cs,
1105 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1106 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1107 S_028004_ZPASS_ENABLE(1) |
1108 S_028004_SLICE_EVEN_ENABLE(1) |
1109 S_028004_SLICE_ODD_ENABLE(1));
1110 } else {
1111 radeon_emit(cs,
1112 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1113 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1114 }
1115 } else {
1116 /* Disable occlusion queries. */
1117 if (sctx->b.chip_class >= CIK) {
1118 radeon_emit(cs, 0);
1119 } else {
1120 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1121 }
1122 }
1123
1124 /* DB_RENDER_OVERRIDE2 */
1125 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1126 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1127 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1128 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1129
1130 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1131 sctx->ps_db_shader_control;
1132
1133 /* Bug workaround for smoothing (overrasterization) on SI. */
1134 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1135 db_shader_control &= C_02880C_Z_ORDER;
1136 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1137 }
1138
1139 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1140 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1141 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1142
1143 if (sctx->b.family == CHIP_STONEY &&
1144 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1145 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1146
1147 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1148 db_shader_control);
1149 }
1150
1151 /*
1152 * format translation
1153 */
1154 static uint32_t si_translate_colorformat(enum pipe_format format)
1155 {
1156 const struct util_format_description *desc = util_format_description(format);
1157
1158 #define HAS_SIZE(x,y,z,w) \
1159 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1160 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1161
1162 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1163 return V_028C70_COLOR_10_11_11;
1164
1165 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1166 return V_028C70_COLOR_INVALID;
1167
1168 /* hw cannot support mixed formats (except depth/stencil, since
1169 * stencil is not written to). */
1170 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1171 return V_028C70_COLOR_INVALID;
1172
1173 switch (desc->nr_channels) {
1174 case 1:
1175 switch (desc->channel[0].size) {
1176 case 8:
1177 return V_028C70_COLOR_8;
1178 case 16:
1179 return V_028C70_COLOR_16;
1180 case 32:
1181 return V_028C70_COLOR_32;
1182 }
1183 break;
1184 case 2:
1185 if (desc->channel[0].size == desc->channel[1].size) {
1186 switch (desc->channel[0].size) {
1187 case 8:
1188 return V_028C70_COLOR_8_8;
1189 case 16:
1190 return V_028C70_COLOR_16_16;
1191 case 32:
1192 return V_028C70_COLOR_32_32;
1193 }
1194 } else if (HAS_SIZE(8,24,0,0)) {
1195 return V_028C70_COLOR_24_8;
1196 } else if (HAS_SIZE(24,8,0,0)) {
1197 return V_028C70_COLOR_8_24;
1198 }
1199 break;
1200 case 3:
1201 if (HAS_SIZE(5,6,5,0)) {
1202 return V_028C70_COLOR_5_6_5;
1203 } else if (HAS_SIZE(32,8,24,0)) {
1204 return V_028C70_COLOR_X24_8_32_FLOAT;
1205 }
1206 break;
1207 case 4:
1208 if (desc->channel[0].size == desc->channel[1].size &&
1209 desc->channel[0].size == desc->channel[2].size &&
1210 desc->channel[0].size == desc->channel[3].size) {
1211 switch (desc->channel[0].size) {
1212 case 4:
1213 return V_028C70_COLOR_4_4_4_4;
1214 case 8:
1215 return V_028C70_COLOR_8_8_8_8;
1216 case 16:
1217 return V_028C70_COLOR_16_16_16_16;
1218 case 32:
1219 return V_028C70_COLOR_32_32_32_32;
1220 }
1221 } else if (HAS_SIZE(5,5,5,1)) {
1222 return V_028C70_COLOR_1_5_5_5;
1223 } else if (HAS_SIZE(10,10,10,2)) {
1224 return V_028C70_COLOR_2_10_10_10;
1225 }
1226 break;
1227 }
1228 return V_028C70_COLOR_INVALID;
1229 }
1230
1231 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1232 {
1233 if (SI_BIG_ENDIAN) {
1234 switch(colorformat) {
1235 /* 8-bit buffers. */
1236 case V_028C70_COLOR_8:
1237 return V_028C70_ENDIAN_NONE;
1238
1239 /* 16-bit buffers. */
1240 case V_028C70_COLOR_5_6_5:
1241 case V_028C70_COLOR_1_5_5_5:
1242 case V_028C70_COLOR_4_4_4_4:
1243 case V_028C70_COLOR_16:
1244 case V_028C70_COLOR_8_8:
1245 return V_028C70_ENDIAN_8IN16;
1246
1247 /* 32-bit buffers. */
1248 case V_028C70_COLOR_8_8_8_8:
1249 case V_028C70_COLOR_2_10_10_10:
1250 case V_028C70_COLOR_8_24:
1251 case V_028C70_COLOR_24_8:
1252 case V_028C70_COLOR_16_16:
1253 return V_028C70_ENDIAN_8IN32;
1254
1255 /* 64-bit buffers. */
1256 case V_028C70_COLOR_16_16_16_16:
1257 return V_028C70_ENDIAN_8IN16;
1258
1259 case V_028C70_COLOR_32_32:
1260 return V_028C70_ENDIAN_8IN32;
1261
1262 /* 128-bit buffers. */
1263 case V_028C70_COLOR_32_32_32_32:
1264 return V_028C70_ENDIAN_8IN32;
1265 default:
1266 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1267 }
1268 } else {
1269 return V_028C70_ENDIAN_NONE;
1270 }
1271 }
1272
1273 static uint32_t si_translate_dbformat(enum pipe_format format)
1274 {
1275 switch (format) {
1276 case PIPE_FORMAT_Z16_UNORM:
1277 return V_028040_Z_16;
1278 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1279 case PIPE_FORMAT_X8Z24_UNORM:
1280 case PIPE_FORMAT_Z24X8_UNORM:
1281 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1282 return V_028040_Z_24; /* deprecated on SI */
1283 case PIPE_FORMAT_Z32_FLOAT:
1284 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1285 return V_028040_Z_32_FLOAT;
1286 default:
1287 return V_028040_Z_INVALID;
1288 }
1289 }
1290
1291 /*
1292 * Texture translation
1293 */
1294
1295 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1296 enum pipe_format format,
1297 const struct util_format_description *desc,
1298 int first_non_void)
1299 {
1300 struct si_screen *sscreen = (struct si_screen*)screen;
1301 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1302 sscreen->b.info.drm_minor >= 31) ||
1303 sscreen->b.info.drm_major == 3;
1304 bool uniform = true;
1305 int i;
1306
1307 /* Colorspace (return non-RGB formats directly). */
1308 switch (desc->colorspace) {
1309 /* Depth stencil formats */
1310 case UTIL_FORMAT_COLORSPACE_ZS:
1311 switch (format) {
1312 case PIPE_FORMAT_Z16_UNORM:
1313 return V_008F14_IMG_DATA_FORMAT_16;
1314 case PIPE_FORMAT_X24S8_UINT:
1315 case PIPE_FORMAT_Z24X8_UNORM:
1316 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1317 return V_008F14_IMG_DATA_FORMAT_8_24;
1318 case PIPE_FORMAT_X8Z24_UNORM:
1319 case PIPE_FORMAT_S8X24_UINT:
1320 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1321 return V_008F14_IMG_DATA_FORMAT_24_8;
1322 case PIPE_FORMAT_S8_UINT:
1323 return V_008F14_IMG_DATA_FORMAT_8;
1324 case PIPE_FORMAT_Z32_FLOAT:
1325 return V_008F14_IMG_DATA_FORMAT_32;
1326 case PIPE_FORMAT_X32_S8X24_UINT:
1327 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1328 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1329 default:
1330 goto out_unknown;
1331 }
1332
1333 case UTIL_FORMAT_COLORSPACE_YUV:
1334 goto out_unknown; /* TODO */
1335
1336 case UTIL_FORMAT_COLORSPACE_SRGB:
1337 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1338 goto out_unknown;
1339 break;
1340
1341 default:
1342 break;
1343 }
1344
1345 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1346 if (!enable_compressed_formats)
1347 goto out_unknown;
1348
1349 switch (format) {
1350 case PIPE_FORMAT_RGTC1_SNORM:
1351 case PIPE_FORMAT_LATC1_SNORM:
1352 case PIPE_FORMAT_RGTC1_UNORM:
1353 case PIPE_FORMAT_LATC1_UNORM:
1354 return V_008F14_IMG_DATA_FORMAT_BC4;
1355 case PIPE_FORMAT_RGTC2_SNORM:
1356 case PIPE_FORMAT_LATC2_SNORM:
1357 case PIPE_FORMAT_RGTC2_UNORM:
1358 case PIPE_FORMAT_LATC2_UNORM:
1359 return V_008F14_IMG_DATA_FORMAT_BC5;
1360 default:
1361 goto out_unknown;
1362 }
1363 }
1364
1365 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1366 sscreen->b.family == CHIP_STONEY) {
1367 switch (format) {
1368 case PIPE_FORMAT_ETC1_RGB8:
1369 case PIPE_FORMAT_ETC2_RGB8:
1370 case PIPE_FORMAT_ETC2_SRGB8:
1371 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1372 case PIPE_FORMAT_ETC2_RGB8A1:
1373 case PIPE_FORMAT_ETC2_SRGB8A1:
1374 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1375 case PIPE_FORMAT_ETC2_RGBA8:
1376 case PIPE_FORMAT_ETC2_SRGBA8:
1377 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1378 case PIPE_FORMAT_ETC2_R11_UNORM:
1379 case PIPE_FORMAT_ETC2_R11_SNORM:
1380 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1381 case PIPE_FORMAT_ETC2_RG11_UNORM:
1382 case PIPE_FORMAT_ETC2_RG11_SNORM:
1383 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1384 default:
1385 goto out_unknown;
1386 }
1387 }
1388
1389 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1390 if (!enable_compressed_formats)
1391 goto out_unknown;
1392
1393 switch (format) {
1394 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1395 case PIPE_FORMAT_BPTC_SRGBA:
1396 return V_008F14_IMG_DATA_FORMAT_BC7;
1397 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1398 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1399 return V_008F14_IMG_DATA_FORMAT_BC6;
1400 default:
1401 goto out_unknown;
1402 }
1403 }
1404
1405 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1406 switch (format) {
1407 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1408 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1409 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1410 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1411 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1412 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1413 default:
1414 goto out_unknown;
1415 }
1416 }
1417
1418 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1419 if (!enable_compressed_formats)
1420 goto out_unknown;
1421
1422 if (!util_format_s3tc_enabled) {
1423 goto out_unknown;
1424 }
1425
1426 switch (format) {
1427 case PIPE_FORMAT_DXT1_RGB:
1428 case PIPE_FORMAT_DXT1_RGBA:
1429 case PIPE_FORMAT_DXT1_SRGB:
1430 case PIPE_FORMAT_DXT1_SRGBA:
1431 return V_008F14_IMG_DATA_FORMAT_BC1;
1432 case PIPE_FORMAT_DXT3_RGBA:
1433 case PIPE_FORMAT_DXT3_SRGBA:
1434 return V_008F14_IMG_DATA_FORMAT_BC2;
1435 case PIPE_FORMAT_DXT5_RGBA:
1436 case PIPE_FORMAT_DXT5_SRGBA:
1437 return V_008F14_IMG_DATA_FORMAT_BC3;
1438 default:
1439 goto out_unknown;
1440 }
1441 }
1442
1443 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1444 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1445 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1446 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1447 }
1448
1449 /* R8G8Bx_SNORM - TODO CxV8U8 */
1450
1451 /* hw cannot support mixed formats (except depth/stencil, since only
1452 * depth is read).*/
1453 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1454 goto out_unknown;
1455
1456 /* See whether the components are of the same size. */
1457 for (i = 1; i < desc->nr_channels; i++) {
1458 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1459 }
1460
1461 /* Non-uniform formats. */
1462 if (!uniform) {
1463 switch(desc->nr_channels) {
1464 case 3:
1465 if (desc->channel[0].size == 5 &&
1466 desc->channel[1].size == 6 &&
1467 desc->channel[2].size == 5) {
1468 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1469 }
1470 goto out_unknown;
1471 case 4:
1472 if (desc->channel[0].size == 5 &&
1473 desc->channel[1].size == 5 &&
1474 desc->channel[2].size == 5 &&
1475 desc->channel[3].size == 1) {
1476 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1477 }
1478 if (desc->channel[0].size == 10 &&
1479 desc->channel[1].size == 10 &&
1480 desc->channel[2].size == 10 &&
1481 desc->channel[3].size == 2) {
1482 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1483 }
1484 goto out_unknown;
1485 }
1486 goto out_unknown;
1487 }
1488
1489 if (first_non_void < 0 || first_non_void > 3)
1490 goto out_unknown;
1491
1492 /* uniform formats */
1493 switch (desc->channel[first_non_void].size) {
1494 case 4:
1495 switch (desc->nr_channels) {
1496 #if 0 /* Not supported for render targets */
1497 case 2:
1498 return V_008F14_IMG_DATA_FORMAT_4_4;
1499 #endif
1500 case 4:
1501 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1502 }
1503 break;
1504 case 8:
1505 switch (desc->nr_channels) {
1506 case 1:
1507 return V_008F14_IMG_DATA_FORMAT_8;
1508 case 2:
1509 return V_008F14_IMG_DATA_FORMAT_8_8;
1510 case 4:
1511 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1512 }
1513 break;
1514 case 16:
1515 switch (desc->nr_channels) {
1516 case 1:
1517 return V_008F14_IMG_DATA_FORMAT_16;
1518 case 2:
1519 return V_008F14_IMG_DATA_FORMAT_16_16;
1520 case 4:
1521 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1522 }
1523 break;
1524 case 32:
1525 switch (desc->nr_channels) {
1526 case 1:
1527 return V_008F14_IMG_DATA_FORMAT_32;
1528 case 2:
1529 return V_008F14_IMG_DATA_FORMAT_32_32;
1530 #if 0 /* Not supported for render targets */
1531 case 3:
1532 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1533 #endif
1534 case 4:
1535 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1536 }
1537 }
1538
1539 out_unknown:
1540 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1541 return ~0;
1542 }
1543
1544 static unsigned si_tex_wrap(unsigned wrap)
1545 {
1546 switch (wrap) {
1547 default:
1548 case PIPE_TEX_WRAP_REPEAT:
1549 return V_008F30_SQ_TEX_WRAP;
1550 case PIPE_TEX_WRAP_CLAMP:
1551 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1552 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1553 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1554 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1555 return V_008F30_SQ_TEX_CLAMP_BORDER;
1556 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1557 return V_008F30_SQ_TEX_MIRROR;
1558 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1559 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1560 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1561 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1562 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1563 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1564 }
1565 }
1566
1567 static unsigned si_tex_mipfilter(unsigned filter)
1568 {
1569 switch (filter) {
1570 case PIPE_TEX_MIPFILTER_NEAREST:
1571 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1572 case PIPE_TEX_MIPFILTER_LINEAR:
1573 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1574 default:
1575 case PIPE_TEX_MIPFILTER_NONE:
1576 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1577 }
1578 }
1579
1580 static unsigned si_tex_compare(unsigned compare)
1581 {
1582 switch (compare) {
1583 default:
1584 case PIPE_FUNC_NEVER:
1585 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1586 case PIPE_FUNC_LESS:
1587 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1588 case PIPE_FUNC_EQUAL:
1589 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1590 case PIPE_FUNC_LEQUAL:
1591 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1592 case PIPE_FUNC_GREATER:
1593 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1594 case PIPE_FUNC_NOTEQUAL:
1595 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1596 case PIPE_FUNC_GEQUAL:
1597 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1598 case PIPE_FUNC_ALWAYS:
1599 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1600 }
1601 }
1602
1603 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1604 unsigned nr_samples)
1605 {
1606 if (view_target == PIPE_TEXTURE_CUBE ||
1607 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1608 res_target = view_target;
1609
1610 switch (res_target) {
1611 default:
1612 case PIPE_TEXTURE_1D:
1613 return V_008F1C_SQ_RSRC_IMG_1D;
1614 case PIPE_TEXTURE_1D_ARRAY:
1615 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1616 case PIPE_TEXTURE_2D:
1617 case PIPE_TEXTURE_RECT:
1618 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1619 V_008F1C_SQ_RSRC_IMG_2D;
1620 case PIPE_TEXTURE_2D_ARRAY:
1621 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1622 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1623 case PIPE_TEXTURE_3D:
1624 return V_008F1C_SQ_RSRC_IMG_3D;
1625 case PIPE_TEXTURE_CUBE:
1626 case PIPE_TEXTURE_CUBE_ARRAY:
1627 return V_008F1C_SQ_RSRC_IMG_CUBE;
1628 }
1629 }
1630
1631 /*
1632 * Format support testing
1633 */
1634
1635 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1636 {
1637 return si_translate_texformat(screen, format, util_format_description(format),
1638 util_format_get_first_non_void_channel(format)) != ~0U;
1639 }
1640
1641 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1642 const struct util_format_description *desc,
1643 int first_non_void)
1644 {
1645 unsigned type;
1646 int i;
1647
1648 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1649 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1650
1651 assert(first_non_void >= 0);
1652 type = desc->channel[first_non_void].type;
1653
1654 if (type == UTIL_FORMAT_TYPE_FIXED)
1655 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1656
1657 if (desc->nr_channels == 4 &&
1658 desc->channel[0].size == 10 &&
1659 desc->channel[1].size == 10 &&
1660 desc->channel[2].size == 10 &&
1661 desc->channel[3].size == 2)
1662 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1663
1664 /* See whether the components are of the same size. */
1665 for (i = 0; i < desc->nr_channels; i++) {
1666 if (desc->channel[first_non_void].size != desc->channel[i].size)
1667 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1668 }
1669
1670 switch (desc->channel[first_non_void].size) {
1671 case 8:
1672 switch (desc->nr_channels) {
1673 case 1:
1674 return V_008F0C_BUF_DATA_FORMAT_8;
1675 case 2:
1676 return V_008F0C_BUF_DATA_FORMAT_8_8;
1677 case 3:
1678 case 4:
1679 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1680 }
1681 break;
1682 case 16:
1683 switch (desc->nr_channels) {
1684 case 1:
1685 return V_008F0C_BUF_DATA_FORMAT_16;
1686 case 2:
1687 return V_008F0C_BUF_DATA_FORMAT_16_16;
1688 case 3:
1689 case 4:
1690 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1691 }
1692 break;
1693 case 32:
1694 /* From the Southern Islands ISA documentation about MTBUF:
1695 * 'Memory reads of data in memory that is 32 or 64 bits do not
1696 * undergo any format conversion.'
1697 */
1698 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1699 !desc->channel[first_non_void].pure_integer)
1700 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1701
1702 switch (desc->nr_channels) {
1703 case 1:
1704 return V_008F0C_BUF_DATA_FORMAT_32;
1705 case 2:
1706 return V_008F0C_BUF_DATA_FORMAT_32_32;
1707 case 3:
1708 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1709 case 4:
1710 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1711 }
1712 break;
1713 }
1714
1715 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1716 }
1717
1718 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1719 const struct util_format_description *desc,
1720 int first_non_void)
1721 {
1722 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1723 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1724
1725 assert(first_non_void >= 0);
1726
1727 switch (desc->channel[first_non_void].type) {
1728 case UTIL_FORMAT_TYPE_SIGNED:
1729 if (desc->channel[first_non_void].normalized)
1730 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1731 else if (desc->channel[first_non_void].pure_integer)
1732 return V_008F0C_BUF_NUM_FORMAT_SINT;
1733 else
1734 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1735 break;
1736 case UTIL_FORMAT_TYPE_UNSIGNED:
1737 if (desc->channel[first_non_void].normalized)
1738 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1739 else if (desc->channel[first_non_void].pure_integer)
1740 return V_008F0C_BUF_NUM_FORMAT_UINT;
1741 else
1742 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1743 break;
1744 case UTIL_FORMAT_TYPE_FLOAT:
1745 default:
1746 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1747 }
1748 }
1749
1750 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1751 {
1752 const struct util_format_description *desc;
1753 int first_non_void;
1754 unsigned data_format;
1755
1756 desc = util_format_description(format);
1757 first_non_void = util_format_get_first_non_void_channel(format);
1758 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1759 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1760 }
1761
1762 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1763 {
1764 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1765 r600_translate_colorswap(format, false) != ~0U;
1766 }
1767
1768 static bool si_is_zs_format_supported(enum pipe_format format)
1769 {
1770 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1771 }
1772
1773 static boolean si_is_format_supported(struct pipe_screen *screen,
1774 enum pipe_format format,
1775 enum pipe_texture_target target,
1776 unsigned sample_count,
1777 unsigned usage)
1778 {
1779 unsigned retval = 0;
1780
1781 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1782 R600_ERR("r600: unsupported texture type %d\n", target);
1783 return false;
1784 }
1785
1786 if (!util_format_is_supported(format, usage))
1787 return false;
1788
1789 if (sample_count > 1) {
1790 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1791 return false;
1792
1793 if (usage & PIPE_BIND_SHADER_IMAGE)
1794 return false;
1795
1796 switch (sample_count) {
1797 case 2:
1798 case 4:
1799 case 8:
1800 break;
1801 case 16:
1802 if (format == PIPE_FORMAT_NONE)
1803 return true;
1804 else
1805 return false;
1806 default:
1807 return false;
1808 }
1809 }
1810
1811 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1812 PIPE_BIND_SHADER_IMAGE)) {
1813 if (target == PIPE_BUFFER) {
1814 if (si_is_vertex_format_supported(screen, format))
1815 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1816 PIPE_BIND_SHADER_IMAGE);
1817 } else {
1818 if (si_is_sampler_format_supported(screen, format))
1819 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1820 PIPE_BIND_SHADER_IMAGE);
1821 }
1822 }
1823
1824 if ((usage & (PIPE_BIND_RENDER_TARGET |
1825 PIPE_BIND_DISPLAY_TARGET |
1826 PIPE_BIND_SCANOUT |
1827 PIPE_BIND_SHARED |
1828 PIPE_BIND_BLENDABLE)) &&
1829 si_is_colorbuffer_format_supported(format)) {
1830 retval |= usage &
1831 (PIPE_BIND_RENDER_TARGET |
1832 PIPE_BIND_DISPLAY_TARGET |
1833 PIPE_BIND_SCANOUT |
1834 PIPE_BIND_SHARED);
1835 if (!util_format_is_pure_integer(format) &&
1836 !util_format_is_depth_or_stencil(format))
1837 retval |= usage & PIPE_BIND_BLENDABLE;
1838 }
1839
1840 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1841 si_is_zs_format_supported(format)) {
1842 retval |= PIPE_BIND_DEPTH_STENCIL;
1843 }
1844
1845 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1846 si_is_vertex_format_supported(screen, format)) {
1847 retval |= PIPE_BIND_VERTEX_BUFFER;
1848 }
1849
1850 if (usage & PIPE_BIND_TRANSFER_READ)
1851 retval |= PIPE_BIND_TRANSFER_READ;
1852 if (usage & PIPE_BIND_TRANSFER_WRITE)
1853 retval |= PIPE_BIND_TRANSFER_WRITE;
1854
1855 if ((usage & PIPE_BIND_LINEAR) &&
1856 !util_format_is_compressed(format) &&
1857 !(usage & PIPE_BIND_DEPTH_STENCIL))
1858 retval |= PIPE_BIND_LINEAR;
1859
1860 return retval == usage;
1861 }
1862
1863 /*
1864 * framebuffer handling
1865 */
1866
1867 static void si_choose_spi_color_formats(struct r600_surface *surf,
1868 unsigned format, unsigned swap,
1869 unsigned ntype, bool is_depth)
1870 {
1871 /* Alpha is needed for alpha-to-coverage.
1872 * Blending may be with or without alpha.
1873 */
1874 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1875 unsigned alpha = 0; /* exports alpha, but may not support blending */
1876 unsigned blend = 0; /* supports blending, but may not export alpha */
1877 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1878
1879 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1880 * Other chips have multiple choices, though they are not necessarily better.
1881 */
1882 switch (format) {
1883 case V_028C70_COLOR_5_6_5:
1884 case V_028C70_COLOR_1_5_5_5:
1885 case V_028C70_COLOR_5_5_5_1:
1886 case V_028C70_COLOR_4_4_4_4:
1887 case V_028C70_COLOR_10_11_11:
1888 case V_028C70_COLOR_11_11_10:
1889 case V_028C70_COLOR_8:
1890 case V_028C70_COLOR_8_8:
1891 case V_028C70_COLOR_8_8_8_8:
1892 case V_028C70_COLOR_10_10_10_2:
1893 case V_028C70_COLOR_2_10_10_10:
1894 if (ntype == V_028C70_NUMBER_UINT)
1895 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1896 else if (ntype == V_028C70_NUMBER_SINT)
1897 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1898 else
1899 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1900 break;
1901
1902 case V_028C70_COLOR_16:
1903 case V_028C70_COLOR_16_16:
1904 case V_028C70_COLOR_16_16_16_16:
1905 if (ntype == V_028C70_NUMBER_UNORM ||
1906 ntype == V_028C70_NUMBER_SNORM) {
1907 /* UNORM16 and SNORM16 don't support blending */
1908 if (ntype == V_028C70_NUMBER_UNORM)
1909 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1910 else
1911 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1912
1913 /* Use 32 bits per channel for blending. */
1914 if (format == V_028C70_COLOR_16) {
1915 if (swap == V_028C70_SWAP_STD) { /* R */
1916 blend = V_028714_SPI_SHADER_32_R;
1917 blend_alpha = V_028714_SPI_SHADER_32_AR;
1918 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1919 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1920 else
1921 assert(0);
1922 } else if (format == V_028C70_COLOR_16_16) {
1923 if (swap == V_028C70_SWAP_STD) { /* RG */
1924 blend = V_028714_SPI_SHADER_32_GR;
1925 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1926 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1927 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1928 else
1929 assert(0);
1930 } else /* 16_16_16_16 */
1931 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1932 } else if (ntype == V_028C70_NUMBER_UINT)
1933 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1934 else if (ntype == V_028C70_NUMBER_SINT)
1935 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1936 else if (ntype == V_028C70_NUMBER_FLOAT)
1937 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1938 else
1939 assert(0);
1940 break;
1941
1942 case V_028C70_COLOR_32:
1943 if (swap == V_028C70_SWAP_STD) { /* R */
1944 blend = normal = V_028714_SPI_SHADER_32_R;
1945 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1946 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1947 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1948 else
1949 assert(0);
1950 break;
1951
1952 case V_028C70_COLOR_32_32:
1953 if (swap == V_028C70_SWAP_STD) { /* RG */
1954 blend = normal = V_028714_SPI_SHADER_32_GR;
1955 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1956 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1957 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1958 else
1959 assert(0);
1960 break;
1961
1962 case V_028C70_COLOR_32_32_32_32:
1963 case V_028C70_COLOR_8_24:
1964 case V_028C70_COLOR_24_8:
1965 case V_028C70_COLOR_X24_8_32_FLOAT:
1966 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1967 break;
1968
1969 default:
1970 assert(0);
1971 return;
1972 }
1973
1974 /* The DB->CB copy needs 32_ABGR. */
1975 if (is_depth)
1976 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1977
1978 surf->spi_shader_col_format = normal;
1979 surf->spi_shader_col_format_alpha = alpha;
1980 surf->spi_shader_col_format_blend = blend;
1981 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1982 }
1983
1984 static void si_initialize_color_surface(struct si_context *sctx,
1985 struct r600_surface *surf)
1986 {
1987 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1988 unsigned color_info, color_attrib, color_view;
1989 unsigned format, swap, ntype, endian;
1990 const struct util_format_description *desc;
1991 int i;
1992 unsigned blend_clamp = 0, blend_bypass = 0;
1993
1994 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1995 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1996
1997 desc = util_format_description(surf->base.format);
1998 for (i = 0; i < 4; i++) {
1999 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2000 break;
2001 }
2002 }
2003 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2004 ntype = V_028C70_NUMBER_FLOAT;
2005 } else {
2006 ntype = V_028C70_NUMBER_UNORM;
2007 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2008 ntype = V_028C70_NUMBER_SRGB;
2009 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2010 if (desc->channel[i].pure_integer) {
2011 ntype = V_028C70_NUMBER_SINT;
2012 } else {
2013 assert(desc->channel[i].normalized);
2014 ntype = V_028C70_NUMBER_SNORM;
2015 }
2016 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2017 if (desc->channel[i].pure_integer) {
2018 ntype = V_028C70_NUMBER_UINT;
2019 } else {
2020 assert(desc->channel[i].normalized);
2021 ntype = V_028C70_NUMBER_UNORM;
2022 }
2023 }
2024 }
2025
2026 format = si_translate_colorformat(surf->base.format);
2027 if (format == V_028C70_COLOR_INVALID) {
2028 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2029 }
2030 assert(format != V_028C70_COLOR_INVALID);
2031 swap = r600_translate_colorswap(surf->base.format, false);
2032 endian = si_colorformat_endian_swap(format);
2033
2034 /* blend clamp should be set for all NORM/SRGB types */
2035 if (ntype == V_028C70_NUMBER_UNORM ||
2036 ntype == V_028C70_NUMBER_SNORM ||
2037 ntype == V_028C70_NUMBER_SRGB)
2038 blend_clamp = 1;
2039
2040 /* set blend bypass according to docs if SINT/UINT or
2041 8/24 COLOR variants */
2042 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2043 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2044 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2045 blend_clamp = 0;
2046 blend_bypass = 1;
2047 }
2048
2049 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2050 (format == V_028C70_COLOR_8 ||
2051 format == V_028C70_COLOR_8_8 ||
2052 format == V_028C70_COLOR_8_8_8_8))
2053 surf->color_is_int8 = true;
2054
2055 color_info = S_028C70_FORMAT(format) |
2056 S_028C70_COMP_SWAP(swap) |
2057 S_028C70_BLEND_CLAMP(blend_clamp) |
2058 S_028C70_BLEND_BYPASS(blend_bypass) |
2059 S_028C70_NUMBER_TYPE(ntype) |
2060 S_028C70_ENDIAN(endian);
2061
2062 /* Intensity is implemented as Red, so treat it that way. */
2063 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2064 util_format_is_intensity(surf->base.format));
2065
2066 if (rtex->resource.b.b.nr_samples > 1) {
2067 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2068
2069 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2070 S_028C74_NUM_FRAGMENTS(log_samples);
2071
2072 if (rtex->fmask.size) {
2073 color_info |= S_028C70_COMPRESSION(1);
2074 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2075
2076 if (sctx->b.chip_class == SI) {
2077 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2078 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2079 }
2080 }
2081 }
2082
2083 surf->cb_color_view = color_view;
2084 surf->cb_color_info = color_info;
2085 surf->cb_color_attrib = color_attrib;
2086
2087 if (sctx->b.chip_class >= VI) {
2088 unsigned max_uncompressed_block_size = 2;
2089
2090 if (rtex->surface.nsamples > 1) {
2091 if (rtex->surface.bpe == 1)
2092 max_uncompressed_block_size = 0;
2093 else if (rtex->surface.bpe == 2)
2094 max_uncompressed_block_size = 1;
2095 }
2096
2097 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2098 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2099 }
2100
2101 /* This must be set for fast clear to work without FMASK. */
2102 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2103 unsigned bankh = util_logbase2(rtex->surface.bankh);
2104 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2105 }
2106
2107 /* Determine pixel shader export format */
2108 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2109
2110 surf->color_initialized = true;
2111 }
2112
2113 static void si_init_depth_surface(struct si_context *sctx,
2114 struct r600_surface *surf)
2115 {
2116 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2117 unsigned level = surf->base.u.tex.level;
2118 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2119 unsigned format;
2120 uint32_t z_info, s_info, db_depth_info;
2121 uint64_t z_offs, s_offs;
2122 uint32_t db_htile_data_base, db_htile_surface;
2123
2124 format = si_translate_dbformat(rtex->resource.b.b.format);
2125
2126 if (format == V_028040_Z_INVALID) {
2127 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2128 }
2129 assert(format != V_028040_Z_INVALID);
2130
2131 s_offs = z_offs = rtex->resource.gpu_address;
2132 z_offs += rtex->surface.level[level].offset;
2133 s_offs += rtex->surface.stencil_level[level].offset;
2134
2135 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2136
2137 z_info = S_028040_FORMAT(format);
2138 if (rtex->resource.b.b.nr_samples > 1) {
2139 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2140 }
2141
2142 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2143 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2144 else
2145 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2146
2147 if (sctx->b.chip_class >= CIK) {
2148 struct radeon_info *info = &sctx->screen->b.info;
2149 unsigned index = rtex->surface.tiling_index[level];
2150 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2151 unsigned macro_index = rtex->surface.macro_tile_index;
2152 unsigned tile_mode = info->si_tile_mode_array[index];
2153 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2154 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2155
2156 db_depth_info |=
2157 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2158 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2159 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2160 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2161 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2162 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2163 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2164 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2165 } else {
2166 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2167 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2168 tile_mode_index = si_tile_mode_index(rtex, level, true);
2169 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2170 }
2171
2172 /* HiZ aka depth buffer htile */
2173 /* use htile only for first level */
2174 if (rtex->htile_buffer && !level) {
2175 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2176 S_028040_ALLOW_EXPCLEAR(1);
2177
2178 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2179 /* Workaround: For a not yet understood reason, the
2180 * combination of MSAA, fast stencil clear and stencil
2181 * decompress messes with subsequent stencil buffer
2182 * uses. Problem was reproduced on Verde, Bonaire,
2183 * Tonga, and Carrizo.
2184 *
2185 * Disabling EXPCLEAR works around the problem.
2186 *
2187 * Check piglit's arb_texture_multisample-stencil-clear
2188 * test if you want to try changing this.
2189 */
2190 if (rtex->resource.b.b.nr_samples <= 1)
2191 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2192 } else
2193 /* Use all of the htile_buffer for depth if there's no stencil. */
2194 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2195
2196 uint64_t va = rtex->htile_buffer->gpu_address;
2197 db_htile_data_base = va >> 8;
2198 db_htile_surface = S_028ABC_FULL_CACHE(1);
2199 } else {
2200 db_htile_data_base = 0;
2201 db_htile_surface = 0;
2202 }
2203
2204 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2205
2206 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2207 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2208 surf->db_htile_data_base = db_htile_data_base;
2209 surf->db_depth_info = db_depth_info;
2210 surf->db_z_info = z_info;
2211 surf->db_stencil_info = s_info;
2212 surf->db_depth_base = z_offs >> 8;
2213 surf->db_stencil_base = s_offs >> 8;
2214 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2215 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2216 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2217 levelinfo->nblk_y) / 64 - 1);
2218 surf->db_htile_surface = db_htile_surface;
2219
2220 surf->depth_initialized = true;
2221 }
2222
2223 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2224 {
2225 for (int i = 0; i < state->nr_cbufs; ++i) {
2226 struct r600_surface *surf = NULL;
2227 struct r600_texture *rtex;
2228
2229 if (!state->cbufs[i])
2230 continue;
2231 surf = (struct r600_surface*)state->cbufs[i];
2232 rtex = (struct r600_texture*)surf->base.texture;
2233
2234 p_atomic_dec(&rtex->framebuffers_bound);
2235 }
2236 }
2237
2238 static void si_set_framebuffer_state(struct pipe_context *ctx,
2239 const struct pipe_framebuffer_state *state)
2240 {
2241 struct si_context *sctx = (struct si_context *)ctx;
2242 struct pipe_constant_buffer constbuf = {0};
2243 struct r600_surface *surf = NULL;
2244 struct r600_texture *rtex;
2245 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2246 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2247 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2248 int i;
2249
2250 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2251 if (!sctx->framebuffer.state.cbufs[i])
2252 continue;
2253
2254 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2255 if (rtex->dcc_gather_statistics)
2256 vi_separate_dcc_stop_query(ctx, rtex);
2257 }
2258
2259 /* Only flush TC when changing the framebuffer state, because
2260 * the only client not using TC that can change textures is
2261 * the framebuffer.
2262 *
2263 * Flush all CB and DB caches here because all buffers can be used
2264 * for write by both TC (with shader image stores) and CB/DB.
2265 */
2266 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2267 SI_CONTEXT_INV_GLOBAL_L2 |
2268 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2269 SI_CONTEXT_CS_PARTIAL_FLUSH;
2270
2271 /* Take the maximum of the old and new count. If the new count is lower,
2272 * dirtying is needed to disable the unbound colorbuffers.
2273 */
2274 sctx->framebuffer.dirty_cbufs |=
2275 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2276 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2277
2278 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2279 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2280
2281 sctx->framebuffer.spi_shader_col_format = 0;
2282 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2283 sctx->framebuffer.spi_shader_col_format_blend = 0;
2284 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2285 sctx->framebuffer.color_is_int8 = 0;
2286
2287 sctx->framebuffer.compressed_cb_mask = 0;
2288 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2289 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2290 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2291 util_format_is_pure_integer(state->cbufs[0]->format);
2292 sctx->framebuffer.any_dst_linear = false;
2293
2294 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2295 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2296
2297 for (i = 0; i < state->nr_cbufs; i++) {
2298 if (!state->cbufs[i])
2299 continue;
2300
2301 surf = (struct r600_surface*)state->cbufs[i];
2302 rtex = (struct r600_texture*)surf->base.texture;
2303
2304 if (!surf->color_initialized) {
2305 si_initialize_color_surface(sctx, surf);
2306 }
2307
2308 sctx->framebuffer.spi_shader_col_format |=
2309 surf->spi_shader_col_format << (i * 4);
2310 sctx->framebuffer.spi_shader_col_format_alpha |=
2311 surf->spi_shader_col_format_alpha << (i * 4);
2312 sctx->framebuffer.spi_shader_col_format_blend |=
2313 surf->spi_shader_col_format_blend << (i * 4);
2314 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2315 surf->spi_shader_col_format_blend_alpha << (i * 4);
2316
2317 if (surf->color_is_int8)
2318 sctx->framebuffer.color_is_int8 |= 1 << i;
2319
2320 if (rtex->fmask.size && rtex->cmask.size) {
2321 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2322 }
2323
2324 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2325 sctx->framebuffer.any_dst_linear = true;
2326
2327 r600_context_add_resource_size(ctx, surf->base.texture);
2328
2329 p_atomic_inc(&rtex->framebuffers_bound);
2330
2331 if (rtex->dcc_gather_statistics) {
2332 /* Dirty tracking must be enabled for DCC usage analysis. */
2333 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2334 vi_separate_dcc_start_query(ctx, rtex);
2335 }
2336 }
2337 /* Set the second SPI format for possible dual-src blending. */
2338 if (i == 1 && surf) {
2339 sctx->framebuffer.spi_shader_col_format |=
2340 surf->spi_shader_col_format << (i * 4);
2341 sctx->framebuffer.spi_shader_col_format_alpha |=
2342 surf->spi_shader_col_format_alpha << (i * 4);
2343 sctx->framebuffer.spi_shader_col_format_blend |=
2344 surf->spi_shader_col_format_blend << (i * 4);
2345 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2346 surf->spi_shader_col_format_blend_alpha << (i * 4);
2347 }
2348
2349 if (state->zsbuf) {
2350 surf = (struct r600_surface*)state->zsbuf;
2351
2352 if (!surf->depth_initialized) {
2353 si_init_depth_surface(sctx, surf);
2354 }
2355 r600_context_add_resource_size(ctx, surf->base.texture);
2356 }
2357
2358 si_update_poly_offset_state(sctx);
2359 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2360 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2361
2362 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2363 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2364
2365 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2366 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2367 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2368
2369 /* Set sample locations as fragment shader constants. */
2370 switch (sctx->framebuffer.nr_samples) {
2371 case 1:
2372 constbuf.user_buffer = sctx->b.sample_locations_1x;
2373 break;
2374 case 2:
2375 constbuf.user_buffer = sctx->b.sample_locations_2x;
2376 break;
2377 case 4:
2378 constbuf.user_buffer = sctx->b.sample_locations_4x;
2379 break;
2380 case 8:
2381 constbuf.user_buffer = sctx->b.sample_locations_8x;
2382 break;
2383 case 16:
2384 constbuf.user_buffer = sctx->b.sample_locations_16x;
2385 break;
2386 default:
2387 R600_ERR("Requested an invalid number of samples %i.\n",
2388 sctx->framebuffer.nr_samples);
2389 assert(0);
2390 }
2391 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2392 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2393
2394 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2395 }
2396
2397 sctx->need_check_render_feedback = true;
2398 sctx->do_update_shaders = true;
2399 }
2400
2401 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2402 {
2403 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2404 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2405 unsigned i, nr_cbufs = state->nr_cbufs;
2406 struct r600_texture *tex = NULL;
2407 struct r600_surface *cb = NULL;
2408 unsigned cb_color_info = 0;
2409
2410 /* Colorbuffers. */
2411 for (i = 0; i < nr_cbufs; i++) {
2412 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2413 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2414 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2415
2416 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2417 continue;
2418
2419 cb = (struct r600_surface*)state->cbufs[i];
2420 if (!cb) {
2421 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2422 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2423 continue;
2424 }
2425
2426 tex = (struct r600_texture *)cb->base.texture;
2427 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2428 &tex->resource, RADEON_USAGE_READWRITE,
2429 tex->surface.nsamples > 1 ?
2430 RADEON_PRIO_COLOR_BUFFER_MSAA :
2431 RADEON_PRIO_COLOR_BUFFER);
2432
2433 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2434 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2435 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2436 RADEON_PRIO_CMASK);
2437 }
2438
2439 if (tex->dcc_separate_buffer)
2440 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2441 tex->dcc_separate_buffer,
2442 RADEON_USAGE_READWRITE,
2443 RADEON_PRIO_DCC);
2444
2445 /* Compute mutable surface parameters. */
2446 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2447 slice_tile_max = cb->level_info->nblk_x *
2448 cb->level_info->nblk_y / 64 - 1;
2449 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2450
2451 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2452 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2453 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2454 cb_color_attrib = cb->cb_color_attrib |
2455 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2456
2457 if (tex->fmask.size) {
2458 if (sctx->b.chip_class >= CIK)
2459 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2460 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2461 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2462 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2463 } else {
2464 /* This must be set for fast clear to work without FMASK. */
2465 if (sctx->b.chip_class >= CIK)
2466 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2467 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2468 cb_color_fmask = cb_color_base;
2469 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2470 }
2471
2472 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2473
2474 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2475 bool is_msaa_resolve_dst = state->cbufs[0] &&
2476 state->cbufs[0]->texture->nr_samples > 1 &&
2477 state->cbufs[1] == &cb->base &&
2478 state->cbufs[1]->texture->nr_samples <= 1;
2479
2480 if (!is_msaa_resolve_dst)
2481 cb_color_info |= S_028C70_DCC_ENABLE(1);
2482 }
2483
2484 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2485 sctx->b.chip_class >= VI ? 14 : 13);
2486 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2487 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2488 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2489 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2490 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2491 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2492 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2493 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2494 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2495 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2496 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2497 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2498 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2499
2500 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2501 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2502 tex->dcc_offset +
2503 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2504 }
2505 /* set CB_COLOR1_INFO for possible dual-src blending */
2506 if (i == 1 && state->cbufs[0] &&
2507 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2508 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2509 cb_color_info);
2510 i++;
2511 }
2512 for (; i < 8 ; i++)
2513 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2514 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2515
2516 /* ZS buffer. */
2517 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2518 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2519 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2520
2521 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2522 &rtex->resource, RADEON_USAGE_READWRITE,
2523 zb->base.texture->nr_samples > 1 ?
2524 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2525 RADEON_PRIO_DEPTH_BUFFER);
2526
2527 if (zb->db_htile_data_base) {
2528 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2529 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2530 RADEON_PRIO_HTILE);
2531 }
2532
2533 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2534 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2535
2536 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2537 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2538 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2539 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2540 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2541 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2542 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2543 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2544 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2545 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2546 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2547
2548 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2549 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2550 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2551
2552 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2553 } else if (sctx->framebuffer.dirty_zsbuf) {
2554 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2555 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2556 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2557 }
2558
2559 /* Framebuffer dimensions. */
2560 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2561 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2562 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2563
2564 sctx->framebuffer.dirty_cbufs = 0;
2565 sctx->framebuffer.dirty_zsbuf = false;
2566 }
2567
2568 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2569 struct r600_atom *atom)
2570 {
2571 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2572 unsigned nr_samples = sctx->framebuffer.nr_samples;
2573
2574 /* Smoothing (only possible with nr_samples == 1) uses the same
2575 * sample locations as the MSAA it simulates.
2576 */
2577 if (nr_samples <= 1 && sctx->smoothing_enabled)
2578 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2579
2580 /* On Polaris, the small primitive filter uses the sample locations
2581 * even when MSAA is off, so we need to make sure they're set to 0.
2582 */
2583 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2584 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2585 sctx->msaa_sample_locs.nr_samples = nr_samples;
2586 cayman_emit_msaa_sample_locs(cs, nr_samples);
2587 }
2588
2589 if (sctx->b.family >= CHIP_POLARIS10) {
2590 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2591 unsigned small_prim_filter_cntl =
2592 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2593 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2594
2595 /* The alternative of setting sample locations to 0 would
2596 * require a DB flush to avoid Z errors, see
2597 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2598 */
2599 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2600 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2601
2602 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2603 small_prim_filter_cntl);
2604 }
2605 }
2606
2607 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2608 {
2609 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2610 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2611 /* 33% faster rendering to linear color buffers */
2612 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2613 unsigned sc_mode_cntl_1 =
2614 S_028A4C_WALK_SIZE(dst_is_linear) |
2615 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2616 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2617 /* always 1: */
2618 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2619 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2620 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2621 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2622 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2623 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2624
2625 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2626 sctx->ps_iter_samples,
2627 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2628 sc_mode_cntl_1);
2629 }
2630
2631 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2632 {
2633 struct si_context *sctx = (struct si_context *)ctx;
2634
2635 if (sctx->ps_iter_samples == min_samples)
2636 return;
2637
2638 sctx->ps_iter_samples = min_samples;
2639 sctx->do_update_shaders = true;
2640
2641 if (sctx->framebuffer.nr_samples > 1)
2642 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2643 }
2644
2645 /*
2646 * Samplers
2647 */
2648
2649 /**
2650 * Build the sampler view descriptor for a buffer texture.
2651 * @param state 256-bit descriptor; only the high 128 bits are filled in
2652 */
2653 void
2654 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2655 enum pipe_format format,
2656 unsigned first_element, unsigned last_element,
2657 uint32_t *state)
2658 {
2659 const struct util_format_description *desc;
2660 int first_non_void;
2661 uint64_t va;
2662 unsigned stride;
2663 unsigned num_records;
2664 unsigned num_format, data_format;
2665
2666 desc = util_format_description(format);
2667 first_non_void = util_format_get_first_non_void_channel(format);
2668 stride = desc->block.bits / 8;
2669 va = buf->gpu_address + first_element * stride;
2670 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2671 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2672
2673 num_records = last_element + 1 - first_element;
2674 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2675
2676 if (screen->b.chip_class >= VI)
2677 num_records *= stride;
2678
2679 state[4] = va;
2680 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2681 S_008F04_STRIDE(stride);
2682 state[6] = num_records;
2683 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2684 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2685 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2686 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2687 S_008F0C_NUM_FORMAT(num_format) |
2688 S_008F0C_DATA_FORMAT(data_format);
2689 }
2690
2691 /**
2692 * Build the sampler view descriptor for a texture.
2693 */
2694 void
2695 si_make_texture_descriptor(struct si_screen *screen,
2696 struct r600_texture *tex,
2697 bool sampler,
2698 enum pipe_texture_target target,
2699 enum pipe_format pipe_format,
2700 const unsigned char state_swizzle[4],
2701 unsigned first_level, unsigned last_level,
2702 unsigned first_layer, unsigned last_layer,
2703 unsigned width, unsigned height, unsigned depth,
2704 uint32_t *state,
2705 uint32_t *fmask_state)
2706 {
2707 struct pipe_resource *res = &tex->resource.b.b;
2708 const struct util_format_description *desc;
2709 unsigned char swizzle[4];
2710 int first_non_void;
2711 unsigned num_format, data_format, type;
2712 uint64_t va;
2713
2714 desc = util_format_description(pipe_format);
2715
2716 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2717 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2718 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2719
2720 switch (pipe_format) {
2721 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2722 case PIPE_FORMAT_X24S8_UINT:
2723 case PIPE_FORMAT_X32_S8X24_UINT:
2724 case PIPE_FORMAT_X8Z24_UNORM:
2725 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2726 break;
2727 default:
2728 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2729 }
2730 } else {
2731 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2732 }
2733
2734 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2735
2736 switch (pipe_format) {
2737 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2738 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2739 break;
2740 default:
2741 if (first_non_void < 0) {
2742 if (util_format_is_compressed(pipe_format)) {
2743 switch (pipe_format) {
2744 case PIPE_FORMAT_DXT1_SRGB:
2745 case PIPE_FORMAT_DXT1_SRGBA:
2746 case PIPE_FORMAT_DXT3_SRGBA:
2747 case PIPE_FORMAT_DXT5_SRGBA:
2748 case PIPE_FORMAT_BPTC_SRGBA:
2749 case PIPE_FORMAT_ETC2_SRGB8:
2750 case PIPE_FORMAT_ETC2_SRGB8A1:
2751 case PIPE_FORMAT_ETC2_SRGBA8:
2752 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2753 break;
2754 case PIPE_FORMAT_RGTC1_SNORM:
2755 case PIPE_FORMAT_LATC1_SNORM:
2756 case PIPE_FORMAT_RGTC2_SNORM:
2757 case PIPE_FORMAT_LATC2_SNORM:
2758 case PIPE_FORMAT_ETC2_R11_SNORM:
2759 case PIPE_FORMAT_ETC2_RG11_SNORM:
2760 /* implies float, so use SNORM/UNORM to determine
2761 whether data is signed or not */
2762 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2763 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2764 break;
2765 default:
2766 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2767 break;
2768 }
2769 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2770 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2771 } else {
2772 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2773 }
2774 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2775 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2776 } else {
2777 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2778
2779 switch (desc->channel[first_non_void].type) {
2780 case UTIL_FORMAT_TYPE_FLOAT:
2781 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2782 break;
2783 case UTIL_FORMAT_TYPE_SIGNED:
2784 if (desc->channel[first_non_void].normalized)
2785 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2786 else if (desc->channel[first_non_void].pure_integer)
2787 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2788 else
2789 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2790 break;
2791 case UTIL_FORMAT_TYPE_UNSIGNED:
2792 if (desc->channel[first_non_void].normalized)
2793 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2794 else if (desc->channel[first_non_void].pure_integer)
2795 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2796 else
2797 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2798 }
2799 }
2800 }
2801
2802 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2803 if (data_format == ~0) {
2804 data_format = 0;
2805 }
2806
2807 if (!sampler &&
2808 (res->target == PIPE_TEXTURE_CUBE ||
2809 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2810 res->target == PIPE_TEXTURE_3D)) {
2811 /* For the purpose of shader images, treat cube maps and 3D
2812 * textures as 2D arrays. For 3D textures, the address
2813 * calculations for mipmaps are different, so we rely on the
2814 * caller to effectively disable mipmaps.
2815 */
2816 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2817
2818 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2819 } else {
2820 type = si_tex_dim(res->target, target, res->nr_samples);
2821 }
2822
2823 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2824 height = 1;
2825 depth = res->array_size;
2826 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2827 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2828 if (sampler || res->target != PIPE_TEXTURE_3D)
2829 depth = res->array_size;
2830 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2831 depth = res->array_size / 6;
2832
2833 state[0] = 0;
2834 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2835 S_008F14_NUM_FORMAT(num_format));
2836 state[2] = (S_008F18_WIDTH(width - 1) |
2837 S_008F18_HEIGHT(height - 1));
2838 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2839 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2840 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2841 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2842 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2843 0 : first_level) |
2844 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2845 util_logbase2(res->nr_samples) :
2846 last_level) |
2847 S_008F1C_POW2_PAD(res->last_level > 0) |
2848 S_008F1C_TYPE(type));
2849 state[4] = S_008F20_DEPTH(depth - 1);
2850 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2851 S_008F24_LAST_ARRAY(last_layer));
2852 state[6] = 0;
2853 state[7] = 0;
2854
2855 if (tex->dcc_offset) {
2856 unsigned swap = r600_translate_colorswap(pipe_format, false);
2857
2858 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2859 } else {
2860 /* The last dword is unused by hw. The shader uses it to clear
2861 * bits in the first dword of sampler state.
2862 */
2863 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2864 if (first_level == last_level)
2865 state[7] = C_008F30_MAX_ANISO_RATIO;
2866 else
2867 state[7] = 0xffffffff;
2868 }
2869 }
2870
2871 /* Initialize the sampler view for FMASK. */
2872 if (tex->fmask.size) {
2873 uint32_t fmask_format;
2874
2875 va = tex->resource.gpu_address + tex->fmask.offset;
2876
2877 switch (res->nr_samples) {
2878 case 2:
2879 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2880 break;
2881 case 4:
2882 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2883 break;
2884 case 8:
2885 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2886 break;
2887 default:
2888 assert(0);
2889 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2890 }
2891
2892 fmask_state[0] = va >> 8;
2893 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2894 S_008F14_DATA_FORMAT(fmask_format) |
2895 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2896 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2897 S_008F18_HEIGHT(height - 1);
2898 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2899 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2900 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2901 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2902 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2903 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2904 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2905 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2906 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2907 S_008F24_LAST_ARRAY(last_layer);
2908 fmask_state[6] = 0;
2909 fmask_state[7] = 0;
2910 }
2911 }
2912
2913 /**
2914 * Create a sampler view.
2915 *
2916 * @param ctx context
2917 * @param texture texture
2918 * @param state sampler view template
2919 * @param width0 width0 override (for compressed textures as int)
2920 * @param height0 height0 override (for compressed textures as int)
2921 * @param force_level set the base address to the level (for compressed textures)
2922 */
2923 struct pipe_sampler_view *
2924 si_create_sampler_view_custom(struct pipe_context *ctx,
2925 struct pipe_resource *texture,
2926 const struct pipe_sampler_view *state,
2927 unsigned width0, unsigned height0,
2928 unsigned force_level)
2929 {
2930 struct si_context *sctx = (struct si_context*)ctx;
2931 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2932 struct r600_texture *tmp = (struct r600_texture*)texture;
2933 unsigned base_level, first_level, last_level;
2934 unsigned char state_swizzle[4];
2935 unsigned height, depth, width;
2936 unsigned last_layer = state->u.tex.last_layer;
2937 enum pipe_format pipe_format;
2938 const struct radeon_surf_level *surflevel;
2939
2940 if (!view)
2941 return NULL;
2942
2943 /* initialize base object */
2944 view->base = *state;
2945 view->base.texture = NULL;
2946 view->base.reference.count = 1;
2947 view->base.context = ctx;
2948
2949 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2950 if (!texture) {
2951 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2952 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2953 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2954 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2955 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2956 return &view->base;
2957 }
2958
2959 pipe_resource_reference(&view->base.texture, texture);
2960
2961 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2962 state->format == PIPE_FORMAT_S8X24_UINT ||
2963 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2964 state->format == PIPE_FORMAT_S8_UINT)
2965 view->is_stencil_sampler = true;
2966
2967 /* Buffer resource. */
2968 if (texture->target == PIPE_BUFFER) {
2969 si_make_buffer_descriptor(sctx->screen,
2970 (struct r600_resource *)texture,
2971 state->format,
2972 state->u.buf.first_element,
2973 state->u.buf.last_element,
2974 view->state);
2975
2976 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2977 return &view->base;
2978 }
2979
2980 state_swizzle[0] = state->swizzle_r;
2981 state_swizzle[1] = state->swizzle_g;
2982 state_swizzle[2] = state->swizzle_b;
2983 state_swizzle[3] = state->swizzle_a;
2984
2985 base_level = 0;
2986 first_level = state->u.tex.first_level;
2987 last_level = state->u.tex.last_level;
2988 width = width0;
2989 height = height0;
2990 depth = texture->depth0;
2991
2992 if (force_level) {
2993 assert(force_level == first_level &&
2994 force_level == last_level);
2995 base_level = force_level;
2996 first_level = 0;
2997 last_level = 0;
2998 width = u_minify(width, force_level);
2999 height = u_minify(height, force_level);
3000 depth = u_minify(depth, force_level);
3001 }
3002
3003 /* This is not needed if state trackers set last_layer correctly. */
3004 if (state->target == PIPE_TEXTURE_1D ||
3005 state->target == PIPE_TEXTURE_2D ||
3006 state->target == PIPE_TEXTURE_RECT ||
3007 state->target == PIPE_TEXTURE_CUBE)
3008 last_layer = state->u.tex.first_layer;
3009
3010 /* Texturing with separate depth and stencil. */
3011 pipe_format = state->format;
3012
3013 /* Depth/stencil texturing sometimes needs separate texture. */
3014 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3015 if (!tmp->flushed_depth_texture &&
3016 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3017 pipe_resource_reference(&view->base.texture, NULL);
3018 FREE(view);
3019 return NULL;
3020 }
3021
3022 assert(tmp->flushed_depth_texture);
3023
3024 /* Override format for the case where the flushed texture
3025 * contains only Z or only S.
3026 */
3027 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3028 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3029
3030 tmp = tmp->flushed_depth_texture;
3031 }
3032
3033 surflevel = tmp->surface.level;
3034
3035 if (tmp->db_compatible) {
3036 switch (pipe_format) {
3037 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3038 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3039 break;
3040 case PIPE_FORMAT_X8Z24_UNORM:
3041 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3042 /* Z24 is always stored like this for DB
3043 * compatibility.
3044 */
3045 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3046 break;
3047 case PIPE_FORMAT_X24S8_UINT:
3048 case PIPE_FORMAT_S8X24_UINT:
3049 case PIPE_FORMAT_X32_S8X24_UINT:
3050 pipe_format = PIPE_FORMAT_S8_UINT;
3051 surflevel = tmp->surface.stencil_level;
3052 break;
3053 default:;
3054 }
3055 }
3056
3057 si_make_texture_descriptor(sctx->screen, tmp, true,
3058 state->target, pipe_format, state_swizzle,
3059 first_level, last_level,
3060 state->u.tex.first_layer, last_layer,
3061 width, height, depth,
3062 view->state, view->fmask_state);
3063
3064 view->base_level_info = &surflevel[base_level];
3065 view->base_level = base_level;
3066 view->block_width = util_format_get_blockwidth(pipe_format);
3067 return &view->base;
3068 }
3069
3070 static struct pipe_sampler_view *
3071 si_create_sampler_view(struct pipe_context *ctx,
3072 struct pipe_resource *texture,
3073 const struct pipe_sampler_view *state)
3074 {
3075 return si_create_sampler_view_custom(ctx, texture, state,
3076 texture ? texture->width0 : 0,
3077 texture ? texture->height0 : 0, 0);
3078 }
3079
3080 static void si_sampler_view_destroy(struct pipe_context *ctx,
3081 struct pipe_sampler_view *state)
3082 {
3083 struct si_sampler_view *view = (struct si_sampler_view *)state;
3084
3085 if (state->texture && state->texture->target == PIPE_BUFFER)
3086 LIST_DELINIT(&view->list);
3087
3088 pipe_resource_reference(&state->texture, NULL);
3089 FREE(view);
3090 }
3091
3092 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3093 {
3094 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3095 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3096 (linear_filter &&
3097 (wrap == PIPE_TEX_WRAP_CLAMP ||
3098 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3099 }
3100
3101 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3102 {
3103 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3104 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3105
3106 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3107 state->border_color.ui[2] || state->border_color.ui[3]) &&
3108 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3109 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3110 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3111 }
3112
3113 static void *si_create_sampler_state(struct pipe_context *ctx,
3114 const struct pipe_sampler_state *state)
3115 {
3116 struct si_context *sctx = (struct si_context *)ctx;
3117 struct r600_common_screen *rscreen = sctx->b.screen;
3118 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3119 unsigned border_color_type, border_color_index = 0;
3120 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3121 : state->max_anisotropy;
3122 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3123
3124 if (!rstate) {
3125 return NULL;
3126 }
3127
3128 if (!sampler_state_needs_border_color(state))
3129 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3130 else if (state->border_color.f[0] == 0 &&
3131 state->border_color.f[1] == 0 &&
3132 state->border_color.f[2] == 0 &&
3133 state->border_color.f[3] == 0)
3134 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3135 else if (state->border_color.f[0] == 0 &&
3136 state->border_color.f[1] == 0 &&
3137 state->border_color.f[2] == 0 &&
3138 state->border_color.f[3] == 1)
3139 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3140 else if (state->border_color.f[0] == 1 &&
3141 state->border_color.f[1] == 1 &&
3142 state->border_color.f[2] == 1 &&
3143 state->border_color.f[3] == 1)
3144 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3145 else {
3146 int i;
3147
3148 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3149
3150 /* Check if the border has been uploaded already. */
3151 for (i = 0; i < sctx->border_color_count; i++)
3152 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3153 sizeof(state->border_color)) == 0)
3154 break;
3155
3156 if (i >= SI_MAX_BORDER_COLORS) {
3157 /* Getting 4096 unique border colors is very unlikely. */
3158 fprintf(stderr, "radeonsi: The border color table is full. "
3159 "Any new border colors will be just black. "
3160 "Please file a bug.\n");
3161 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3162 } else {
3163 if (i == sctx->border_color_count) {
3164 /* Upload a new border color. */
3165 memcpy(&sctx->border_color_table[i], &state->border_color,
3166 sizeof(state->border_color));
3167 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3168 &state->border_color,
3169 sizeof(state->border_color));
3170 sctx->border_color_count++;
3171 }
3172
3173 border_color_index = i;
3174 }
3175 }
3176
3177 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3178 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3179 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3180 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3181 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3182 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3183 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3184 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3185 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3186 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3187 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3188 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3189 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3190 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3191 S_008F38_MIP_POINT_PRECLAMP(1) |
3192 S_008F38_DISABLE_LSB_CEIL(1) |
3193 S_008F38_FILTER_PREC_FIX(1) |
3194 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3195 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3196 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3197 return rstate;
3198 }
3199
3200 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3201 {
3202 struct si_context *sctx = (struct si_context *)ctx;
3203
3204 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3205 return;
3206
3207 sctx->sample_mask.sample_mask = sample_mask;
3208 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3209 }
3210
3211 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3212 {
3213 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3214 unsigned mask = sctx->sample_mask.sample_mask;
3215
3216 /* Needed for line and polygon smoothing as well as for the Polaris
3217 * small primitive filter. We expect the state tracker to take care of
3218 * this for us.
3219 */
3220 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3221 (mask & 1 && sctx->blitter->running));
3222
3223 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3224 radeon_emit(cs, mask | (mask << 16));
3225 radeon_emit(cs, mask | (mask << 16));
3226 }
3227
3228 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3229 {
3230 free(state);
3231 }
3232
3233 /*
3234 * Vertex elements & buffers
3235 */
3236
3237 static void *si_create_vertex_elements(struct pipe_context *ctx,
3238 unsigned count,
3239 const struct pipe_vertex_element *elements)
3240 {
3241 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3242 int i;
3243
3244 assert(count <= SI_MAX_ATTRIBS);
3245 if (!v)
3246 return NULL;
3247
3248 v->count = count;
3249 for (i = 0; i < count; ++i) {
3250 const struct util_format_description *desc;
3251 unsigned data_format, num_format;
3252 int first_non_void;
3253
3254 desc = util_format_description(elements[i].src_format);
3255 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3256 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3257 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3258
3259 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3260 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3261 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3262 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3263 S_008F0C_NUM_FORMAT(num_format) |
3264 S_008F0C_DATA_FORMAT(data_format);
3265 v->format_size[i] = desc->block.bits / 8;
3266 }
3267 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3268
3269 return v;
3270 }
3271
3272 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3273 {
3274 struct si_context *sctx = (struct si_context *)ctx;
3275 struct si_vertex_element *v = (struct si_vertex_element*)state;
3276
3277 sctx->vertex_elements = v;
3278 sctx->vertex_buffers_dirty = true;
3279 sctx->do_update_shaders = true;
3280 }
3281
3282 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3283 {
3284 struct si_context *sctx = (struct si_context *)ctx;
3285
3286 if (sctx->vertex_elements == state)
3287 sctx->vertex_elements = NULL;
3288 FREE(state);
3289 }
3290
3291 static void si_set_vertex_buffers(struct pipe_context *ctx,
3292 unsigned start_slot, unsigned count,
3293 const struct pipe_vertex_buffer *buffers)
3294 {
3295 struct si_context *sctx = (struct si_context *)ctx;
3296 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3297 int i;
3298
3299 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3300
3301 if (buffers) {
3302 for (i = 0; i < count; i++) {
3303 const struct pipe_vertex_buffer *src = buffers + i;
3304 struct pipe_vertex_buffer *dsti = dst + i;
3305
3306 pipe_resource_reference(&dsti->buffer, src->buffer);
3307 dsti->buffer_offset = src->buffer_offset;
3308 dsti->stride = src->stride;
3309 r600_context_add_resource_size(ctx, src->buffer);
3310 }
3311 } else {
3312 for (i = 0; i < count; i++) {
3313 pipe_resource_reference(&dst[i].buffer, NULL);
3314 }
3315 }
3316 sctx->vertex_buffers_dirty = true;
3317 }
3318
3319 static void si_set_index_buffer(struct pipe_context *ctx,
3320 const struct pipe_index_buffer *ib)
3321 {
3322 struct si_context *sctx = (struct si_context *)ctx;
3323
3324 if (ib) {
3325 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3326 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3327 r600_context_add_resource_size(ctx, ib->buffer);
3328 } else {
3329 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3330 }
3331 }
3332
3333 /*
3334 * Misc
3335 */
3336
3337 static void si_set_tess_state(struct pipe_context *ctx,
3338 const float default_outer_level[4],
3339 const float default_inner_level[2])
3340 {
3341 struct si_context *sctx = (struct si_context *)ctx;
3342 struct pipe_constant_buffer cb;
3343 float array[8];
3344
3345 memcpy(array, default_outer_level, sizeof(float) * 4);
3346 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3347
3348 cb.buffer = NULL;
3349 cb.user_buffer = NULL;
3350 cb.buffer_size = sizeof(array);
3351
3352 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3353 (void*)array, sizeof(array),
3354 &cb.buffer_offset);
3355
3356 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3357 pipe_resource_reference(&cb.buffer, NULL);
3358 }
3359
3360 static void si_texture_barrier(struct pipe_context *ctx)
3361 {
3362 struct si_context *sctx = (struct si_context *)ctx;
3363
3364 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3365 SI_CONTEXT_INV_GLOBAL_L2 |
3366 SI_CONTEXT_FLUSH_AND_INV_CB |
3367 SI_CONTEXT_CS_PARTIAL_FLUSH;
3368 }
3369
3370 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3371 {
3372 struct si_context *sctx = (struct si_context *)ctx;
3373
3374 /* Subsequent commands must wait for all shader invocations to
3375 * complete. */
3376 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3377 SI_CONTEXT_CS_PARTIAL_FLUSH;
3378
3379 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3380 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3381 SI_CONTEXT_INV_VMEM_L1;
3382
3383 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3384 PIPE_BARRIER_SHADER_BUFFER |
3385 PIPE_BARRIER_TEXTURE |
3386 PIPE_BARRIER_IMAGE |
3387 PIPE_BARRIER_STREAMOUT_BUFFER |
3388 PIPE_BARRIER_GLOBAL_BUFFER)) {
3389 /* As far as I can tell, L1 contents are written back to L2
3390 * automatically at end of shader, but the contents of other
3391 * L1 caches might still be stale. */
3392 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3393 }
3394
3395 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3396 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3397
3398 /* Indices are read through TC L2 since VI. */
3399 if (sctx->screen->b.chip_class <= CIK)
3400 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3401 }
3402
3403 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3404 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3405
3406 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3407 PIPE_BARRIER_FRAMEBUFFER |
3408 PIPE_BARRIER_INDIRECT_BUFFER)) {
3409 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3410 *
3411 * We need to make sure that TC L1 & L2 are written back to
3412 * memory, because neither CPU accesses nor CB fetches consider
3413 * TC, but there's no need to invalidate any TC cache lines. */
3414 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3415 }
3416 }
3417
3418 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3419 {
3420 struct pipe_blend_state blend;
3421
3422 memset(&blend, 0, sizeof(blend));
3423 blend.independent_blend_enable = true;
3424 blend.rt[0].colormask = 0xf;
3425 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3426 }
3427
3428 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3429 bool include_draw_vbo)
3430 {
3431 si_need_cs_space((struct si_context*)ctx);
3432 }
3433
3434 static void si_init_config(struct si_context *sctx);
3435
3436 void si_init_state_functions(struct si_context *sctx)
3437 {
3438 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3439 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3440 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3441 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3442 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3443
3444 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3445 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3446 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3447 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3448 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3449 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3450 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3451 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3452 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3453 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3454 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3455
3456 sctx->b.b.create_blend_state = si_create_blend_state;
3457 sctx->b.b.bind_blend_state = si_bind_blend_state;
3458 sctx->b.b.delete_blend_state = si_delete_blend_state;
3459 sctx->b.b.set_blend_color = si_set_blend_color;
3460
3461 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3462 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3463 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3464
3465 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3466 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3467 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3468
3469 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3470 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3471 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3472 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3473 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3474
3475 sctx->b.b.set_clip_state = si_set_clip_state;
3476 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3477
3478 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3479 sctx->b.b.get_sample_position = cayman_get_sample_position;
3480
3481 sctx->b.b.create_sampler_state = si_create_sampler_state;
3482 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3483
3484 sctx->b.b.create_sampler_view = si_create_sampler_view;
3485 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3486
3487 sctx->b.b.set_sample_mask = si_set_sample_mask;
3488
3489 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3490 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3491 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3492 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3493 sctx->b.b.set_index_buffer = si_set_index_buffer;
3494
3495 sctx->b.b.texture_barrier = si_texture_barrier;
3496 sctx->b.b.memory_barrier = si_memory_barrier;
3497 sctx->b.b.set_min_samples = si_set_min_samples;
3498 sctx->b.b.set_tess_state = si_set_tess_state;
3499
3500 sctx->b.b.set_active_query_state = si_set_active_query_state;
3501 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3502 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3503
3504 sctx->b.b.draw_vbo = si_draw_vbo;
3505
3506 si_init_config(sctx);
3507 }
3508
3509 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3510 {
3511 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3512 }
3513
3514 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3515 struct r600_texture *rtex,
3516 struct radeon_bo_metadata *md)
3517 {
3518 struct si_screen *sscreen = (struct si_screen*)rscreen;
3519 struct pipe_resource *res = &rtex->resource.b.b;
3520 static const unsigned char swizzle[] = {
3521 PIPE_SWIZZLE_X,
3522 PIPE_SWIZZLE_Y,
3523 PIPE_SWIZZLE_Z,
3524 PIPE_SWIZZLE_W
3525 };
3526 uint32_t desc[8], i;
3527 bool is_array = util_resource_is_array_texture(res);
3528
3529 /* DRM 2.x.x doesn't support this. */
3530 if (rscreen->info.drm_major != 3)
3531 return;
3532
3533 assert(rtex->dcc_separate_buffer == NULL);
3534 assert(rtex->fmask.size == 0);
3535
3536 /* Metadata image format format version 1:
3537 * [0] = 1 (metadata format identifier)
3538 * [1] = (VENDOR_ID << 16) | PCI_ID
3539 * [2:9] = image descriptor for the whole resource
3540 * [2] is always 0, because the base address is cleared
3541 * [9] is the DCC offset bits [39:8] from the beginning of
3542 * the buffer
3543 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3544 */
3545
3546 md->metadata[0] = 1; /* metadata image format version 1 */
3547
3548 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3549 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3550
3551 si_make_texture_descriptor(sscreen, rtex, true,
3552 res->target, res->format,
3553 swizzle, 0, res->last_level, 0,
3554 is_array ? res->array_size - 1 : 0,
3555 res->width0, res->height0, res->depth0,
3556 desc, NULL);
3557
3558 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3559 rtex->surface.blk_w, false, desc);
3560
3561 /* Clear the base address and set the relative DCC offset. */
3562 desc[0] = 0;
3563 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3564 desc[7] = rtex->dcc_offset >> 8;
3565
3566 /* Dwords [2:9] contain the image descriptor. */
3567 memcpy(&md->metadata[2], desc, sizeof(desc));
3568
3569 /* Dwords [10:..] contain the mipmap level offsets. */
3570 for (i = 0; i <= res->last_level; i++)
3571 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3572
3573 md->size_metadata = (11 + res->last_level) * 4;
3574 }
3575
3576 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3577 struct r600_texture *rtex,
3578 struct radeon_bo_metadata *md)
3579 {
3580 uint32_t *desc = &md->metadata[2];
3581
3582 if (rscreen->chip_class < VI)
3583 return;
3584
3585 /* Return if DCC is enabled. The texture should be set up with it
3586 * already.
3587 */
3588 if (md->size_metadata >= 11 * 4 &&
3589 md->metadata[0] != 0 &&
3590 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3591 G_008F28_COMPRESSION_EN(desc[6])) {
3592 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3593 return;
3594 }
3595
3596 /* Disable DCC. These are always set by texture_from_handle and must
3597 * be cleared here.
3598 */
3599 rtex->dcc_offset = 0;
3600 }
3601
3602 void si_init_screen_state_functions(struct si_screen *sscreen)
3603 {
3604 sscreen->b.b.is_format_supported = si_is_format_supported;
3605 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3606 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3607 }
3608
3609 static void
3610 si_write_harvested_raster_configs(struct si_context *sctx,
3611 struct si_pm4_state *pm4,
3612 unsigned raster_config,
3613 unsigned raster_config_1)
3614 {
3615 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3616 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3617 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3618 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3619 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3620 unsigned rb_per_se = num_rb / num_se;
3621 unsigned se_mask[4];
3622 unsigned se;
3623
3624 se_mask[0] = ((1 << rb_per_se) - 1);
3625 se_mask[1] = (se_mask[0] << rb_per_se);
3626 se_mask[2] = (se_mask[1] << rb_per_se);
3627 se_mask[3] = (se_mask[2] << rb_per_se);
3628
3629 se_mask[0] &= rb_mask;
3630 se_mask[1] &= rb_mask;
3631 se_mask[2] &= rb_mask;
3632 se_mask[3] &= rb_mask;
3633
3634 assert(num_se == 1 || num_se == 2 || num_se == 4);
3635 assert(sh_per_se == 1 || sh_per_se == 2);
3636 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3637
3638 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3639 * fields are for, so I'm leaving them as their default
3640 * values. */
3641
3642 for (se = 0; se < num_se; se++) {
3643 unsigned raster_config_se = raster_config;
3644 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3645 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3646 int idx = (se / 2) * 2;
3647
3648 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3649 raster_config_se &= C_028350_SE_MAP;
3650
3651 if (!se_mask[idx]) {
3652 raster_config_se |=
3653 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3654 } else {
3655 raster_config_se |=
3656 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3657 }
3658 }
3659
3660 pkr0_mask &= rb_mask;
3661 pkr1_mask &= rb_mask;
3662 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3663 raster_config_se &= C_028350_PKR_MAP;
3664
3665 if (!pkr0_mask) {
3666 raster_config_se |=
3667 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3668 } else {
3669 raster_config_se |=
3670 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3671 }
3672 }
3673
3674 if (rb_per_se >= 2) {
3675 unsigned rb0_mask = 1 << (se * rb_per_se);
3676 unsigned rb1_mask = rb0_mask << 1;
3677
3678 rb0_mask &= rb_mask;
3679 rb1_mask &= rb_mask;
3680 if (!rb0_mask || !rb1_mask) {
3681 raster_config_se &= C_028350_RB_MAP_PKR0;
3682
3683 if (!rb0_mask) {
3684 raster_config_se |=
3685 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3686 } else {
3687 raster_config_se |=
3688 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3689 }
3690 }
3691
3692 if (rb_per_se > 2) {
3693 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3694 rb1_mask = rb0_mask << 1;
3695 rb0_mask &= rb_mask;
3696 rb1_mask &= rb_mask;
3697 if (!rb0_mask || !rb1_mask) {
3698 raster_config_se &= C_028350_RB_MAP_PKR1;
3699
3700 if (!rb0_mask) {
3701 raster_config_se |=
3702 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3703 } else {
3704 raster_config_se |=
3705 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3706 }
3707 }
3708 }
3709 }
3710
3711 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3712 if (sctx->b.chip_class < CIK)
3713 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3714 SE_INDEX(se) | SH_BROADCAST_WRITES |
3715 INSTANCE_BROADCAST_WRITES);
3716 else
3717 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3718 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3719 S_030800_INSTANCE_BROADCAST_WRITES(1));
3720 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3721 }
3722
3723 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3724 if (sctx->b.chip_class < CIK)
3725 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3726 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3727 INSTANCE_BROADCAST_WRITES);
3728 else {
3729 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3730 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3731 S_030800_INSTANCE_BROADCAST_WRITES(1));
3732
3733 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3734 (!se_mask[2] && !se_mask[3]))) {
3735 raster_config_1 &= C_028354_SE_PAIR_MAP;
3736
3737 if (!se_mask[0] && !se_mask[1]) {
3738 raster_config_1 |=
3739 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3740 } else {
3741 raster_config_1 |=
3742 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3743 }
3744 }
3745
3746 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3747 }
3748 }
3749
3750 static void si_init_config(struct si_context *sctx)
3751 {
3752 struct si_screen *sscreen = sctx->screen;
3753 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3754 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3755 unsigned raster_config, raster_config_1;
3756 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3757 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3758 int i;
3759
3760 if (!pm4)
3761 return;
3762
3763 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3764 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3765 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3766 si_pm4_cmd_end(pm4, false);
3767
3768 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3769 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3770
3771 /* FIXME calculate these values somehow ??? */
3772 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3773 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3774 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3775
3776 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3777 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3778
3779 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3780 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3781 if (sctx->b.chip_class < CIK)
3782 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3783 S_008A14_CLIP_VTX_REORDER_ENA(1));
3784
3785 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3786 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3787
3788 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3789
3790 for (i = 0; i < 16; i++) {
3791 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3792 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3793 }
3794
3795 switch (sctx->screen->b.family) {
3796 case CHIP_TAHITI:
3797 case CHIP_PITCAIRN:
3798 raster_config = 0x2a00126a;
3799 raster_config_1 = 0x00000000;
3800 break;
3801 case CHIP_VERDE:
3802 raster_config = 0x0000124a;
3803 raster_config_1 = 0x00000000;
3804 break;
3805 case CHIP_OLAND:
3806 raster_config = 0x00000082;
3807 raster_config_1 = 0x00000000;
3808 break;
3809 case CHIP_HAINAN:
3810 raster_config = 0x00000000;
3811 raster_config_1 = 0x00000000;
3812 break;
3813 case CHIP_BONAIRE:
3814 raster_config = 0x16000012;
3815 raster_config_1 = 0x00000000;
3816 break;
3817 case CHIP_HAWAII:
3818 raster_config = 0x3a00161a;
3819 raster_config_1 = 0x0000002e;
3820 break;
3821 case CHIP_FIJI:
3822 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3823 /* old kernels with old tiling config */
3824 raster_config = 0x16000012;
3825 raster_config_1 = 0x0000002a;
3826 } else {
3827 raster_config = 0x3a00161a;
3828 raster_config_1 = 0x0000002e;
3829 }
3830 break;
3831 case CHIP_POLARIS10:
3832 raster_config = 0x16000012;
3833 raster_config_1 = 0x0000002a;
3834 break;
3835 case CHIP_POLARIS11:
3836 raster_config = 0x16000012;
3837 raster_config_1 = 0x00000000;
3838 break;
3839 case CHIP_TONGA:
3840 raster_config = 0x16000012;
3841 raster_config_1 = 0x0000002a;
3842 break;
3843 case CHIP_ICELAND:
3844 if (num_rb == 1)
3845 raster_config = 0x00000000;
3846 else
3847 raster_config = 0x00000002;
3848 raster_config_1 = 0x00000000;
3849 break;
3850 case CHIP_CARRIZO:
3851 raster_config = 0x00000002;
3852 raster_config_1 = 0x00000000;
3853 break;
3854 case CHIP_KAVERI:
3855 /* KV should be 0x00000002, but that causes problems with radeon */
3856 raster_config = 0x00000000; /* 0x00000002 */
3857 raster_config_1 = 0x00000000;
3858 break;
3859 case CHIP_KABINI:
3860 case CHIP_MULLINS:
3861 case CHIP_STONEY:
3862 raster_config = 0x00000000;
3863 raster_config_1 = 0x00000000;
3864 break;
3865 default:
3866 fprintf(stderr,
3867 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3868 raster_config = 0x00000000;
3869 raster_config_1 = 0x00000000;
3870 break;
3871 }
3872
3873 /* Always use the default config when all backends are enabled
3874 * (or when we failed to determine the enabled backends).
3875 */
3876 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3877 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3878 raster_config);
3879 if (sctx->b.chip_class >= CIK)
3880 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3881 raster_config_1);
3882 } else {
3883 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3884 }
3885
3886 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3887 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3888 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3889 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3890 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3891 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3892 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3893
3894 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3895 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3896 S_028230_ER_TRI(0xA) |
3897 S_028230_ER_POINT(0xA) |
3898 S_028230_ER_RECT(0xA) |
3899 /* Required by DX10_DIAMOND_TEST_ENA: */
3900 S_028230_ER_LINE_LR(0x1A) |
3901 S_028230_ER_LINE_RL(0x26) |
3902 S_028230_ER_LINE_TB(0xA) |
3903 S_028230_ER_LINE_BT(0xA));
3904 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3905 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3906 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3907 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3908 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3909 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3910 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3911 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3912 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3913
3914 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3915 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3916 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3917
3918 if (sctx->b.chip_class >= CIK) {
3919 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3920 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3921 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3922 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3923
3924 if (sscreen->b.info.num_good_compute_units /
3925 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3926 /* Too few available compute units per SH. Disallowing
3927 * VS to run on CU0 could hurt us more than late VS
3928 * allocation would help.
3929 *
3930 * LATE_ALLOC_VS = 2 is the highest safe number.
3931 */
3932 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3933 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3934 } else {
3935 /* Set LATE_ALLOC_VS == 31. It should be less than
3936 * the number of scratch waves. Limitations:
3937 * - VS can't execute on CU0.
3938 * - If HS writes outputs to LDS, LS can't execute on CU0.
3939 */
3940 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3941 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3942 }
3943
3944 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3945 }
3946
3947 if (sctx->b.chip_class >= VI) {
3948 unsigned vgt_tess_distribution;
3949
3950 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3951 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3952 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3953 if (sctx->b.family < CHIP_POLARIS10)
3954 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3955 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3956
3957 vgt_tess_distribution =
3958 S_028B50_ACCUM_ISOLINE(32) |
3959 S_028B50_ACCUM_TRI(11) |
3960 S_028B50_ACCUM_QUAD(11) |
3961 S_028B50_DONUT_SPLIT(16);
3962
3963 /* Testing with Unigine Heaven extreme tesselation yielded best results
3964 * with TRAP_SPLIT = 3.
3965 */
3966 if (sctx->b.family == CHIP_FIJI ||
3967 sctx->b.family >= CHIP_POLARIS10)
3968 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3969
3970 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3971 } else {
3972 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3973 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3974 }
3975
3976 if (sctx->b.family == CHIP_STONEY)
3977 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3978
3979 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3980 if (sctx->b.chip_class >= CIK)
3981 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3982 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3983 RADEON_PRIO_BORDER_COLORS);
3984
3985 si_pm4_upload_indirect_buffer(sctx, pm4);
3986 sctx->init_config = pm4;
3987 }