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radeonsi/gfx9: CB changes
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* RB+ register settings. */
121 if (sctx->screen->b.rbplus_allowed) {
122 unsigned spi_shader_col_format =
123 sctx->ps_shader.cso ?
124 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
125 unsigned sx_ps_downconvert = 0;
126 unsigned sx_blend_opt_epsilon = 0;
127 unsigned sx_blend_opt_control = 0;
128
129 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
130 struct r600_surface *surf =
131 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
132 unsigned format, swap, spi_format, colormask;
133 bool has_alpha, has_rgb;
134
135 if (!surf)
136 continue;
137
138 format = G_028C70_FORMAT(surf->cb_color_info);
139 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
140 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
141 colormask = (cb_target_mask >> (i * 4)) & 0xf;
142
143 /* Set if RGB and A are present. */
144 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
145
146 if (format == V_028C70_COLOR_8 ||
147 format == V_028C70_COLOR_16 ||
148 format == V_028C70_COLOR_32)
149 has_rgb = !has_alpha;
150 else
151 has_rgb = true;
152
153 /* Check the colormask and export format. */
154 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
155 has_rgb = false;
156 if (!(colormask & PIPE_MASK_A))
157 has_alpha = false;
158
159 if (spi_format == V_028714_SPI_SHADER_ZERO) {
160 has_rgb = false;
161 has_alpha = false;
162 }
163
164 /* Disable value checking for disabled channels. */
165 if (!has_rgb)
166 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
167 if (!has_alpha)
168 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
169
170 /* Enable down-conversion for 32bpp and smaller formats. */
171 switch (format) {
172 case V_028C70_COLOR_8:
173 case V_028C70_COLOR_8_8:
174 case V_028C70_COLOR_8_8_8_8:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
178 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
180 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
181 }
182 break;
183
184 case V_028C70_COLOR_5_6_5:
185 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_1_5_5_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_4_4_4_4:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_32:
206 if (swap == V_0280A0_SWAP_STD &&
207 spi_format == V_028714_SPI_SHADER_32_R)
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
209 else if (swap == V_0280A0_SWAP_ALT_REV &&
210 spi_format == V_028714_SPI_SHADER_32_AR)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
212 break;
213
214 case V_028C70_COLOR_16:
215 case V_028C70_COLOR_16_16:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
221 if (swap == V_0280A0_SWAP_STD ||
222 swap == V_0280A0_SWAP_STD_REV)
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
224 else
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
226 }
227 break;
228
229 case V_028C70_COLOR_10_11_11:
230 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
232 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_2_10_10_10:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
240 }
241 break;
242 }
243 }
244
245 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
246 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
249 } else if (sctx->screen->b.has_rbplus) {
250 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
251 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
252 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
253 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
254 }
255 }
256
257 /*
258 * Blender functions
259 */
260
261 static uint32_t si_translate_blend_function(int blend_func)
262 {
263 switch (blend_func) {
264 case PIPE_BLEND_ADD:
265 return V_028780_COMB_DST_PLUS_SRC;
266 case PIPE_BLEND_SUBTRACT:
267 return V_028780_COMB_SRC_MINUS_DST;
268 case PIPE_BLEND_REVERSE_SUBTRACT:
269 return V_028780_COMB_DST_MINUS_SRC;
270 case PIPE_BLEND_MIN:
271 return V_028780_COMB_MIN_DST_SRC;
272 case PIPE_BLEND_MAX:
273 return V_028780_COMB_MAX_DST_SRC;
274 default:
275 R600_ERR("Unknown blend function %d\n", blend_func);
276 assert(0);
277 break;
278 }
279 return 0;
280 }
281
282 static uint32_t si_translate_blend_factor(int blend_fact)
283 {
284 switch (blend_fact) {
285 case PIPE_BLENDFACTOR_ONE:
286 return V_028780_BLEND_ONE;
287 case PIPE_BLENDFACTOR_SRC_COLOR:
288 return V_028780_BLEND_SRC_COLOR;
289 case PIPE_BLENDFACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case PIPE_BLENDFACTOR_DST_ALPHA:
292 return V_028780_BLEND_DST_ALPHA;
293 case PIPE_BLENDFACTOR_DST_COLOR:
294 return V_028780_BLEND_DST_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE;
297 case PIPE_BLENDFACTOR_CONST_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_CONST_ALPHA:
300 return V_028780_BLEND_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_ZERO:
302 return V_028780_BLEND_ZERO;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_SRC1_COLOR:
316 return V_028780_BLEND_SRC1_COLOR;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA:
318 return V_028780_BLEND_SRC1_ALPHA;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
322 return V_028780_BLEND_INV_SRC1_ALPHA;
323 default:
324 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
325 assert(0);
326 break;
327 }
328 return 0;
329 }
330
331 static uint32_t si_translate_blend_opt_function(int blend_func)
332 {
333 switch (blend_func) {
334 case PIPE_BLEND_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case PIPE_BLEND_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case PIPE_BLEND_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case PIPE_BLEND_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case PIPE_BLEND_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
350 {
351 switch (blend_fact) {
352 case PIPE_BLENDFACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case PIPE_BLENDFACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case PIPE_BLENDFACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case PIPE_BLENDFACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 /**
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 */
378 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
379 unsigned *dst_factor, unsigned expected_dst,
380 unsigned replacement_src)
381 {
382 if (*src_factor == expected_dst &&
383 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
384 *src_factor = PIPE_BLENDFACTOR_ZERO;
385 *dst_factor = replacement_src;
386
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func == PIPE_BLEND_SUBTRACT)
389 *func = PIPE_BLEND_REVERSE_SUBTRACT;
390 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
391 *func = PIPE_BLEND_SUBTRACT;
392 }
393 }
394
395 static bool si_blend_factor_uses_dst(unsigned factor)
396 {
397 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
398 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
399 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
400 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
401 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
402 }
403
404 static void *si_create_blend_state_mode(struct pipe_context *ctx,
405 const struct pipe_blend_state *state,
406 unsigned mode)
407 {
408 struct si_context *sctx = (struct si_context*)ctx;
409 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
410 struct si_pm4_state *pm4 = &blend->pm4;
411 uint32_t sx_mrt_blend_opt[8] = {0};
412 uint32_t color_control = 0;
413
414 if (!blend)
415 return NULL;
416
417 blend->alpha_to_coverage = state->alpha_to_coverage;
418 blend->alpha_to_one = state->alpha_to_one;
419 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
420
421 if (state->logicop_enable) {
422 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
423 } else {
424 color_control |= S_028808_ROP3(0xcc);
425 }
426
427 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
428 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
429 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433
434 if (state->alpha_to_coverage)
435 blend->need_src_alpha_4bit |= 0xf;
436
437 blend->cb_target_mask = 0;
438 for (int i = 0; i < 8; i++) {
439 /* state->rt entries > 0 only written if independent blending */
440 const int j = state->independent_blend_enable ? i : 0;
441
442 unsigned eqRGB = state->rt[j].rgb_func;
443 unsigned srcRGB = state->rt[j].rgb_src_factor;
444 unsigned dstRGB = state->rt[j].rgb_dst_factor;
445 unsigned eqA = state->rt[j].alpha_func;
446 unsigned srcA = state->rt[j].alpha_src_factor;
447 unsigned dstA = state->rt[j].alpha_dst_factor;
448
449 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
450 unsigned blend_cntl = 0;
451
452 sx_mrt_blend_opt[i] =
453 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
454 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
455
456 /* Only set dual source blending for MRT0 to avoid a hang. */
457 if (i >= 1 && blend->dual_src_blend) {
458 /* Vulkan does this for dual source blending. */
459 if (i == 1)
460 blend_cntl |= S_028780_ENABLE(1);
461
462 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
463 continue;
464 }
465
466 /* Only addition and subtraction equations are supported with
467 * dual source blending.
468 */
469 if (blend->dual_src_blend &&
470 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
471 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
472 assert(!"Unsupported equation for dual source blending");
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* cb_render_state will disable unused ones */
478 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
479
480 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
481 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
482 continue;
483 }
484
485 /* Blending optimizations for RB+.
486 * These transformations don't change the behavior.
487 *
488 * First, get rid of DST in the blend factors:
489 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
490 */
491 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
492 PIPE_BLENDFACTOR_DST_COLOR,
493 PIPE_BLENDFACTOR_SRC_COLOR);
494 si_blend_remove_dst(&eqA, &srcA, &dstA,
495 PIPE_BLENDFACTOR_DST_COLOR,
496 PIPE_BLENDFACTOR_SRC_COLOR);
497 si_blend_remove_dst(&eqA, &srcA, &dstA,
498 PIPE_BLENDFACTOR_DST_ALPHA,
499 PIPE_BLENDFACTOR_SRC_ALPHA);
500
501 /* Look up the ideal settings from tables. */
502 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
503 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
504 srcA_opt = si_translate_blend_opt_factor(srcA, true);
505 dstA_opt = si_translate_blend_opt_factor(dstA, true);
506
507 /* Handle interdependencies. */
508 if (si_blend_factor_uses_dst(srcRGB))
509 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
510 if (si_blend_factor_uses_dst(srcA))
511 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
512
513 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
514 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
516 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
517 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
518
519 /* Set the final value. */
520 sx_mrt_blend_opt[i] =
521 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
522 S_028760_COLOR_DST_OPT(dstRGB_opt) |
523 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
524 S_028760_ALPHA_SRC_OPT(srcA_opt) |
525 S_028760_ALPHA_DST_OPT(dstA_opt) |
526 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
527
528 /* Set blend state. */
529 blend_cntl |= S_028780_ENABLE(1);
530 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
531 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
532 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
533
534 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
535 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
536 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
537 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
538 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
539 }
540 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
541
542 blend->blend_enable_4bit |= 0xfu << (i * 4);
543
544 /* This is only important for formats without alpha. */
545 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
547 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
549 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
550 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
551 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
552 }
553
554 if (blend->cb_target_mask) {
555 color_control |= S_028808_MODE(mode);
556 } else {
557 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
558 }
559
560 if (sctx->screen->b.has_rbplus) {
561 /* Disable RB+ blend optimizations for dual source blending.
562 * Vulkan does this.
563 */
564 if (blend->dual_src_blend) {
565 for (int i = 0; i < 8; i++) {
566 sx_mrt_blend_opt[i] =
567 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
568 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
569 }
570 }
571
572 for (int i = 0; i < 8; i++)
573 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
574 sx_mrt_blend_opt[i]);
575
576 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
577 if (blend->dual_src_blend || state->logicop_enable ||
578 mode == V_028808_CB_RESOLVE)
579 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
580 }
581
582 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
583 return blend;
584 }
585
586 static void *si_create_blend_state(struct pipe_context *ctx,
587 const struct pipe_blend_state *state)
588 {
589 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
590 }
591
592 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
596 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
597 sctx->do_update_shaders = true;
598 }
599
600 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
601 {
602 struct si_context *sctx = (struct si_context *)ctx;
603 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
604 }
605
606 static void si_set_blend_color(struct pipe_context *ctx,
607 const struct pipe_blend_color *state)
608 {
609 struct si_context *sctx = (struct si_context *)ctx;
610
611 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
612 return;
613
614 sctx->blend_color.state = *state;
615 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
616 }
617
618 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
619 {
620 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
621
622 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
623 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
624 }
625
626 /*
627 * Clipping
628 */
629
630 static void si_set_clip_state(struct pipe_context *ctx,
631 const struct pipe_clip_state *state)
632 {
633 struct si_context *sctx = (struct si_context *)ctx;
634 struct pipe_constant_buffer cb;
635
636 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
637 return;
638
639 sctx->clip_state.state = *state;
640 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
641
642 cb.buffer = NULL;
643 cb.user_buffer = state->ucp;
644 cb.buffer_offset = 0;
645 cb.buffer_size = 4*4*8;
646 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
647 pipe_resource_reference(&cb.buffer, NULL);
648 }
649
650 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
651 {
652 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
653
654 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
655 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
656 }
657
658 #define SIX_BITS 0x3F
659
660 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
661 {
662 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
663 struct si_shader *vs = si_get_vs_state(sctx);
664 struct tgsi_shader_info *info = si_get_vs_info(sctx);
665 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
666 unsigned window_space =
667 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
668 unsigned clipdist_mask =
669 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
670 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
671 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
672 unsigned total_mask;
673 bool misc_vec_ena;
674
675 if (vs->key.opt.hw_vs.clip_disable) {
676 assert(!info->culldist_writemask);
677 clipdist_mask = 0;
678 culldist_mask = 0;
679 }
680 total_mask = clipdist_mask | culldist_mask;
681
682 /* Clip distances on points have no effect, so need to be implemented
683 * as cull distances. This applies for the clipvertex case as well.
684 *
685 * Setting this for primitives other than points should have no adverse
686 * effects.
687 */
688 clipdist_mask &= rs->clip_plane_enable;
689 culldist_mask |= clipdist_mask;
690
691 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
692 info->writes_layer || info->writes_viewport_index;
693
694 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
695 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
696 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
697 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
698 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
699 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
700 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
701 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
702 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
703 clipdist_mask | (culldist_mask << 8));
704 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
705 rs->pa_cl_clip_cntl |
706 ucp_mask |
707 S_028810_CLIP_DISABLE(window_space));
708
709 /* reuse needs to be set off if we write oViewport */
710 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
711 S_028AB4_REUSE_OFF(info->writes_viewport_index));
712 }
713
714 /*
715 * inferred state between framebuffer and rasterizer
716 */
717 static void si_update_poly_offset_state(struct si_context *sctx)
718 {
719 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
720
721 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
722 si_pm4_bind_state(sctx, poly_offset, NULL);
723 return;
724 }
725
726 /* Use the user format, not db_render_format, so that the polygon
727 * offset behaves as expected by applications.
728 */
729 switch (sctx->framebuffer.state.zsbuf->texture->format) {
730 case PIPE_FORMAT_Z16_UNORM:
731 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
732 break;
733 default: /* 24-bit */
734 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
735 break;
736 case PIPE_FORMAT_Z32_FLOAT:
737 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
738 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
739 break;
740 }
741 }
742
743 /*
744 * Rasterizer
745 */
746
747 static uint32_t si_translate_fill(uint32_t func)
748 {
749 switch(func) {
750 case PIPE_POLYGON_MODE_FILL:
751 return V_028814_X_DRAW_TRIANGLES;
752 case PIPE_POLYGON_MODE_LINE:
753 return V_028814_X_DRAW_LINES;
754 case PIPE_POLYGON_MODE_POINT:
755 return V_028814_X_DRAW_POINTS;
756 default:
757 assert(0);
758 return V_028814_X_DRAW_POINTS;
759 }
760 }
761
762 static void *si_create_rs_state(struct pipe_context *ctx,
763 const struct pipe_rasterizer_state *state)
764 {
765 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
766 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
767 struct si_pm4_state *pm4 = &rs->pm4;
768 unsigned tmp, i;
769 float psize_min, psize_max;
770
771 if (!rs) {
772 return NULL;
773 }
774
775 rs->scissor_enable = state->scissor;
776 rs->clip_halfz = state->clip_halfz;
777 rs->two_side = state->light_twoside;
778 rs->multisample_enable = state->multisample;
779 rs->force_persample_interp = state->force_persample_interp;
780 rs->clip_plane_enable = state->clip_plane_enable;
781 rs->line_stipple_enable = state->line_stipple_enable;
782 rs->poly_stipple_enable = state->poly_stipple_enable;
783 rs->line_smooth = state->line_smooth;
784 rs->poly_smooth = state->poly_smooth;
785 rs->uses_poly_offset = state->offset_point || state->offset_line ||
786 state->offset_tri;
787 rs->clamp_fragment_color = state->clamp_fragment_color;
788 rs->flatshade = state->flatshade;
789 rs->sprite_coord_enable = state->sprite_coord_enable;
790 rs->rasterizer_discard = state->rasterizer_discard;
791 rs->pa_sc_line_stipple = state->line_stipple_enable ?
792 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
793 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
794 rs->pa_cl_clip_cntl =
795 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
796 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
797 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
798 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
799 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
800
801 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
802 S_0286D4_FLAT_SHADE_ENA(1) |
803 S_0286D4_PNT_SPRITE_ENA(1) |
804 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
805 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
806 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
807 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
808 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
809
810 /* point size 12.4 fixed point */
811 tmp = (unsigned)(state->point_size * 8.0);
812 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
813
814 if (state->point_size_per_vertex) {
815 psize_min = util_get_min_point_size(state);
816 psize_max = 8192;
817 } else {
818 /* Force the point size to be as if the vertex output was disabled. */
819 psize_min = state->point_size;
820 psize_max = state->point_size;
821 }
822 /* Divide by two, because 0.5 = 1 pixel. */
823 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
824 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
825 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
826
827 tmp = (unsigned)state->line_width * 8;
828 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
829 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
830 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
831 S_028A48_MSAA_ENABLE(state->multisample ||
832 state->poly_smooth ||
833 state->line_smooth) |
834 S_028A48_VPORT_SCISSOR_ENABLE(1) |
835 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
836
837 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
838 S_028BE4_PIX_CENTER(state->half_pixel_center) |
839 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
840
841 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
842 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
843 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
844 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
845 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
846 S_028814_FACE(!state->front_ccw) |
847 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
848 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
849 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
850 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
851 state->fill_back != PIPE_POLYGON_MODE_FILL) |
852 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
853 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
854 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
855 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
856
857 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
858 for (i = 0; i < 3; i++) {
859 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
860 float offset_units = state->offset_units;
861 float offset_scale = state->offset_scale * 16.0f;
862 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
863
864 if (!state->offset_units_unscaled) {
865 switch (i) {
866 case 0: /* 16-bit zbuffer */
867 offset_units *= 4.0f;
868 pa_su_poly_offset_db_fmt_cntl =
869 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
870 break;
871 case 1: /* 24-bit zbuffer */
872 offset_units *= 2.0f;
873 pa_su_poly_offset_db_fmt_cntl =
874 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
875 break;
876 case 2: /* 32-bit zbuffer */
877 offset_units *= 1.0f;
878 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
879 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
880 break;
881 }
882 }
883
884 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
885 fui(offset_scale));
886 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
887 fui(offset_units));
888 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
889 fui(offset_scale));
890 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
891 fui(offset_units));
892 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
893 pa_su_poly_offset_db_fmt_cntl);
894 }
895
896 return rs;
897 }
898
899 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
900 {
901 struct si_context *sctx = (struct si_context *)ctx;
902 struct si_state_rasterizer *old_rs =
903 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
904 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
905
906 if (!state)
907 return;
908
909 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
910 si_mark_atom_dirty(sctx, &sctx->db_render_state);
911
912 /* Update the small primitive filter workaround if necessary. */
913 if (sctx->b.family >= CHIP_POLARIS10 &&
914 sctx->framebuffer.nr_samples > 1)
915 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
916 }
917
918 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
919
920 si_pm4_bind_state(sctx, rasterizer, rs);
921 si_update_poly_offset_state(sctx);
922
923 si_mark_atom_dirty(sctx, &sctx->clip_regs);
924 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
925 rs->line_stipple_enable;
926 sctx->do_update_shaders = true;
927 }
928
929 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
930 {
931 struct si_context *sctx = (struct si_context *)ctx;
932
933 if (sctx->queued.named.rasterizer == state)
934 si_pm4_bind_state(sctx, poly_offset, NULL);
935 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
936 }
937
938 /*
939 * infeered state between dsa and stencil ref
940 */
941 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
942 {
943 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
944 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
945 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
946
947 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
948 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
949 S_028430_STENCILMASK(dsa->valuemask[0]) |
950 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
951 S_028430_STENCILOPVAL(1));
952 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
953 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
954 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
955 S_028434_STENCILOPVAL_BF(1));
956 }
957
958 static void si_set_stencil_ref(struct pipe_context *ctx,
959 const struct pipe_stencil_ref *state)
960 {
961 struct si_context *sctx = (struct si_context *)ctx;
962
963 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
964 return;
965
966 sctx->stencil_ref.state = *state;
967 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
968 }
969
970
971 /*
972 * DSA
973 */
974
975 static uint32_t si_translate_stencil_op(int s_op)
976 {
977 switch (s_op) {
978 case PIPE_STENCIL_OP_KEEP:
979 return V_02842C_STENCIL_KEEP;
980 case PIPE_STENCIL_OP_ZERO:
981 return V_02842C_STENCIL_ZERO;
982 case PIPE_STENCIL_OP_REPLACE:
983 return V_02842C_STENCIL_REPLACE_TEST;
984 case PIPE_STENCIL_OP_INCR:
985 return V_02842C_STENCIL_ADD_CLAMP;
986 case PIPE_STENCIL_OP_DECR:
987 return V_02842C_STENCIL_SUB_CLAMP;
988 case PIPE_STENCIL_OP_INCR_WRAP:
989 return V_02842C_STENCIL_ADD_WRAP;
990 case PIPE_STENCIL_OP_DECR_WRAP:
991 return V_02842C_STENCIL_SUB_WRAP;
992 case PIPE_STENCIL_OP_INVERT:
993 return V_02842C_STENCIL_INVERT;
994 default:
995 R600_ERR("Unknown stencil op %d", s_op);
996 assert(0);
997 break;
998 }
999 return 0;
1000 }
1001
1002 static void *si_create_dsa_state(struct pipe_context *ctx,
1003 const struct pipe_depth_stencil_alpha_state *state)
1004 {
1005 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1006 struct si_pm4_state *pm4 = &dsa->pm4;
1007 unsigned db_depth_control;
1008 uint32_t db_stencil_control = 0;
1009
1010 if (!dsa) {
1011 return NULL;
1012 }
1013
1014 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1015 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1016 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1017 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1018
1019 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1020 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1021 S_028800_ZFUNC(state->depth.func) |
1022 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1023
1024 /* stencil */
1025 if (state->stencil[0].enabled) {
1026 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1027 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1028 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1029 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1030 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1031
1032 if (state->stencil[1].enabled) {
1033 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1034 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1035 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1036 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1037 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1038 }
1039 }
1040
1041 /* alpha */
1042 if (state->alpha.enabled) {
1043 dsa->alpha_func = state->alpha.func;
1044
1045 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1046 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1047 } else {
1048 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1049 }
1050
1051 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1052 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1053 if (state->depth.bounds_test) {
1054 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1055 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1056 }
1057
1058 return dsa;
1059 }
1060
1061 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1062 {
1063 struct si_context *sctx = (struct si_context *)ctx;
1064 struct si_state_dsa *dsa = state;
1065
1066 if (!state)
1067 return;
1068
1069 si_pm4_bind_state(sctx, dsa, dsa);
1070
1071 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1072 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1073 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1074 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1075 }
1076 sctx->do_update_shaders = true;
1077 }
1078
1079 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1080 {
1081 struct si_context *sctx = (struct si_context *)ctx;
1082 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1083 }
1084
1085 static void *si_create_db_flush_dsa(struct si_context *sctx)
1086 {
1087 struct pipe_depth_stencil_alpha_state dsa = {};
1088
1089 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1090 }
1091
1092 /* DB RENDER STATE */
1093
1094 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1095 {
1096 struct si_context *sctx = (struct si_context*)ctx;
1097
1098 /* Pipeline stat & streamout queries. */
1099 if (enable) {
1100 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1101 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1102 } else {
1103 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1104 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1105 }
1106
1107 /* Occlusion queries. */
1108 if (sctx->occlusion_queries_disabled != !enable) {
1109 sctx->occlusion_queries_disabled = !enable;
1110 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1111 }
1112 }
1113
1114 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1115 {
1116 struct si_context *sctx = (struct si_context*)ctx;
1117
1118 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1119 }
1120
1121 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1122 {
1123 struct si_context *sctx = (struct si_context*)ctx;
1124
1125 st->saved_compute = sctx->cs_shader_state.program;
1126
1127 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1128 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1129 }
1130
1131 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1132 {
1133 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1134 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1135 unsigned db_shader_control;
1136
1137 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1138
1139 /* DB_RENDER_CONTROL */
1140 if (sctx->dbcb_depth_copy_enabled ||
1141 sctx->dbcb_stencil_copy_enabled) {
1142 radeon_emit(cs,
1143 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1144 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1145 S_028000_COPY_CENTROID(1) |
1146 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1147 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1148 radeon_emit(cs,
1149 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1150 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1151 } else {
1152 radeon_emit(cs,
1153 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1154 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1155 }
1156
1157 /* DB_COUNT_CONTROL (occlusion queries) */
1158 if (sctx->b.num_occlusion_queries > 0 &&
1159 !sctx->occlusion_queries_disabled) {
1160 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1161
1162 if (sctx->b.chip_class >= CIK) {
1163 radeon_emit(cs,
1164 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1165 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1166 S_028004_ZPASS_ENABLE(1) |
1167 S_028004_SLICE_EVEN_ENABLE(1) |
1168 S_028004_SLICE_ODD_ENABLE(1));
1169 } else {
1170 radeon_emit(cs,
1171 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1172 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1173 }
1174 } else {
1175 /* Disable occlusion queries. */
1176 if (sctx->b.chip_class >= CIK) {
1177 radeon_emit(cs, 0);
1178 } else {
1179 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1180 }
1181 }
1182
1183 /* DB_RENDER_OVERRIDE2 */
1184 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1185 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1186 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1187 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1188
1189 db_shader_control = sctx->ps_db_shader_control;
1190
1191 /* Bug workaround for smoothing (overrasterization) on SI. */
1192 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1193 db_shader_control &= C_02880C_Z_ORDER;
1194 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1195 }
1196
1197 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1198 if (!rs || !rs->multisample_enable)
1199 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1200
1201 if (sctx->screen->b.has_rbplus &&
1202 !sctx->screen->b.rbplus_allowed)
1203 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1204
1205 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1206 db_shader_control);
1207 }
1208
1209 /*
1210 * format translation
1211 */
1212 static uint32_t si_translate_colorformat(enum pipe_format format)
1213 {
1214 const struct util_format_description *desc = util_format_description(format);
1215
1216 #define HAS_SIZE(x,y,z,w) \
1217 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1218 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1219
1220 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1221 return V_028C70_COLOR_10_11_11;
1222
1223 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1224 return V_028C70_COLOR_INVALID;
1225
1226 /* hw cannot support mixed formats (except depth/stencil, since
1227 * stencil is not written to). */
1228 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1229 return V_028C70_COLOR_INVALID;
1230
1231 switch (desc->nr_channels) {
1232 case 1:
1233 switch (desc->channel[0].size) {
1234 case 8:
1235 return V_028C70_COLOR_8;
1236 case 16:
1237 return V_028C70_COLOR_16;
1238 case 32:
1239 return V_028C70_COLOR_32;
1240 }
1241 break;
1242 case 2:
1243 if (desc->channel[0].size == desc->channel[1].size) {
1244 switch (desc->channel[0].size) {
1245 case 8:
1246 return V_028C70_COLOR_8_8;
1247 case 16:
1248 return V_028C70_COLOR_16_16;
1249 case 32:
1250 return V_028C70_COLOR_32_32;
1251 }
1252 } else if (HAS_SIZE(8,24,0,0)) {
1253 return V_028C70_COLOR_24_8;
1254 } else if (HAS_SIZE(24,8,0,0)) {
1255 return V_028C70_COLOR_8_24;
1256 }
1257 break;
1258 case 3:
1259 if (HAS_SIZE(5,6,5,0)) {
1260 return V_028C70_COLOR_5_6_5;
1261 } else if (HAS_SIZE(32,8,24,0)) {
1262 return V_028C70_COLOR_X24_8_32_FLOAT;
1263 }
1264 break;
1265 case 4:
1266 if (desc->channel[0].size == desc->channel[1].size &&
1267 desc->channel[0].size == desc->channel[2].size &&
1268 desc->channel[0].size == desc->channel[3].size) {
1269 switch (desc->channel[0].size) {
1270 case 4:
1271 return V_028C70_COLOR_4_4_4_4;
1272 case 8:
1273 return V_028C70_COLOR_8_8_8_8;
1274 case 16:
1275 return V_028C70_COLOR_16_16_16_16;
1276 case 32:
1277 return V_028C70_COLOR_32_32_32_32;
1278 }
1279 } else if (HAS_SIZE(5,5,5,1)) {
1280 return V_028C70_COLOR_1_5_5_5;
1281 } else if (HAS_SIZE(10,10,10,2)) {
1282 return V_028C70_COLOR_2_10_10_10;
1283 }
1284 break;
1285 }
1286 return V_028C70_COLOR_INVALID;
1287 }
1288
1289 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1290 {
1291 if (SI_BIG_ENDIAN) {
1292 switch(colorformat) {
1293 /* 8-bit buffers. */
1294 case V_028C70_COLOR_8:
1295 return V_028C70_ENDIAN_NONE;
1296
1297 /* 16-bit buffers. */
1298 case V_028C70_COLOR_5_6_5:
1299 case V_028C70_COLOR_1_5_5_5:
1300 case V_028C70_COLOR_4_4_4_4:
1301 case V_028C70_COLOR_16:
1302 case V_028C70_COLOR_8_8:
1303 return V_028C70_ENDIAN_8IN16;
1304
1305 /* 32-bit buffers. */
1306 case V_028C70_COLOR_8_8_8_8:
1307 case V_028C70_COLOR_2_10_10_10:
1308 case V_028C70_COLOR_8_24:
1309 case V_028C70_COLOR_24_8:
1310 case V_028C70_COLOR_16_16:
1311 return V_028C70_ENDIAN_8IN32;
1312
1313 /* 64-bit buffers. */
1314 case V_028C70_COLOR_16_16_16_16:
1315 return V_028C70_ENDIAN_8IN16;
1316
1317 case V_028C70_COLOR_32_32:
1318 return V_028C70_ENDIAN_8IN32;
1319
1320 /* 128-bit buffers. */
1321 case V_028C70_COLOR_32_32_32_32:
1322 return V_028C70_ENDIAN_8IN32;
1323 default:
1324 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1325 }
1326 } else {
1327 return V_028C70_ENDIAN_NONE;
1328 }
1329 }
1330
1331 static uint32_t si_translate_dbformat(enum pipe_format format)
1332 {
1333 switch (format) {
1334 case PIPE_FORMAT_Z16_UNORM:
1335 return V_028040_Z_16;
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1337 case PIPE_FORMAT_X8Z24_UNORM:
1338 case PIPE_FORMAT_Z24X8_UNORM:
1339 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1340 return V_028040_Z_24; /* deprecated on SI */
1341 case PIPE_FORMAT_Z32_FLOAT:
1342 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1343 return V_028040_Z_32_FLOAT;
1344 default:
1345 return V_028040_Z_INVALID;
1346 }
1347 }
1348
1349 /*
1350 * Texture translation
1351 */
1352
1353 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1354 enum pipe_format format,
1355 const struct util_format_description *desc,
1356 int first_non_void)
1357 {
1358 struct si_screen *sscreen = (struct si_screen*)screen;
1359 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1360 sscreen->b.info.drm_minor >= 31) ||
1361 sscreen->b.info.drm_major == 3;
1362 bool uniform = true;
1363 int i;
1364
1365 /* Colorspace (return non-RGB formats directly). */
1366 switch (desc->colorspace) {
1367 /* Depth stencil formats */
1368 case UTIL_FORMAT_COLORSPACE_ZS:
1369 switch (format) {
1370 case PIPE_FORMAT_Z16_UNORM:
1371 return V_008F14_IMG_DATA_FORMAT_16;
1372 case PIPE_FORMAT_X24S8_UINT:
1373 case PIPE_FORMAT_S8X24_UINT:
1374 /*
1375 * Implemented as an 8_8_8_8 data format to fix texture
1376 * gathers in stencil sampling. This affects at least
1377 * GL45-CTS.texture_cube_map_array.sampling on VI.
1378 */
1379 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1380 case PIPE_FORMAT_Z24X8_UNORM:
1381 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1382 return V_008F14_IMG_DATA_FORMAT_8_24;
1383 case PIPE_FORMAT_X8Z24_UNORM:
1384 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1385 return V_008F14_IMG_DATA_FORMAT_24_8;
1386 case PIPE_FORMAT_S8_UINT:
1387 return V_008F14_IMG_DATA_FORMAT_8;
1388 case PIPE_FORMAT_Z32_FLOAT:
1389 return V_008F14_IMG_DATA_FORMAT_32;
1390 case PIPE_FORMAT_X32_S8X24_UINT:
1391 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1392 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1393 default:
1394 goto out_unknown;
1395 }
1396
1397 case UTIL_FORMAT_COLORSPACE_YUV:
1398 goto out_unknown; /* TODO */
1399
1400 case UTIL_FORMAT_COLORSPACE_SRGB:
1401 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1402 goto out_unknown;
1403 break;
1404
1405 default:
1406 break;
1407 }
1408
1409 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1410 if (!enable_compressed_formats)
1411 goto out_unknown;
1412
1413 switch (format) {
1414 case PIPE_FORMAT_RGTC1_SNORM:
1415 case PIPE_FORMAT_LATC1_SNORM:
1416 case PIPE_FORMAT_RGTC1_UNORM:
1417 case PIPE_FORMAT_LATC1_UNORM:
1418 return V_008F14_IMG_DATA_FORMAT_BC4;
1419 case PIPE_FORMAT_RGTC2_SNORM:
1420 case PIPE_FORMAT_LATC2_SNORM:
1421 case PIPE_FORMAT_RGTC2_UNORM:
1422 case PIPE_FORMAT_LATC2_UNORM:
1423 return V_008F14_IMG_DATA_FORMAT_BC5;
1424 default:
1425 goto out_unknown;
1426 }
1427 }
1428
1429 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1430 (sscreen->b.family == CHIP_STONEY ||
1431 sscreen->b.chip_class >= GFX9)) {
1432 switch (format) {
1433 case PIPE_FORMAT_ETC1_RGB8:
1434 case PIPE_FORMAT_ETC2_RGB8:
1435 case PIPE_FORMAT_ETC2_SRGB8:
1436 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1437 case PIPE_FORMAT_ETC2_RGB8A1:
1438 case PIPE_FORMAT_ETC2_SRGB8A1:
1439 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1440 case PIPE_FORMAT_ETC2_RGBA8:
1441 case PIPE_FORMAT_ETC2_SRGBA8:
1442 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1443 case PIPE_FORMAT_ETC2_R11_UNORM:
1444 case PIPE_FORMAT_ETC2_R11_SNORM:
1445 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1446 case PIPE_FORMAT_ETC2_RG11_UNORM:
1447 case PIPE_FORMAT_ETC2_RG11_SNORM:
1448 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1449 default:
1450 goto out_unknown;
1451 }
1452 }
1453
1454 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1455 if (!enable_compressed_formats)
1456 goto out_unknown;
1457
1458 switch (format) {
1459 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1460 case PIPE_FORMAT_BPTC_SRGBA:
1461 return V_008F14_IMG_DATA_FORMAT_BC7;
1462 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1463 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1464 return V_008F14_IMG_DATA_FORMAT_BC6;
1465 default:
1466 goto out_unknown;
1467 }
1468 }
1469
1470 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1471 switch (format) {
1472 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1473 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1474 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1475 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1476 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1477 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1478 default:
1479 goto out_unknown;
1480 }
1481 }
1482
1483 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1484 if (!enable_compressed_formats)
1485 goto out_unknown;
1486
1487 if (!util_format_s3tc_enabled) {
1488 goto out_unknown;
1489 }
1490
1491 switch (format) {
1492 case PIPE_FORMAT_DXT1_RGB:
1493 case PIPE_FORMAT_DXT1_RGBA:
1494 case PIPE_FORMAT_DXT1_SRGB:
1495 case PIPE_FORMAT_DXT1_SRGBA:
1496 return V_008F14_IMG_DATA_FORMAT_BC1;
1497 case PIPE_FORMAT_DXT3_RGBA:
1498 case PIPE_FORMAT_DXT3_SRGBA:
1499 return V_008F14_IMG_DATA_FORMAT_BC2;
1500 case PIPE_FORMAT_DXT5_RGBA:
1501 case PIPE_FORMAT_DXT5_SRGBA:
1502 return V_008F14_IMG_DATA_FORMAT_BC3;
1503 default:
1504 goto out_unknown;
1505 }
1506 }
1507
1508 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1509 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1510 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1511 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1512 }
1513
1514 /* R8G8Bx_SNORM - TODO CxV8U8 */
1515
1516 /* hw cannot support mixed formats (except depth/stencil, since only
1517 * depth is read).*/
1518 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1519 goto out_unknown;
1520
1521 /* See whether the components are of the same size. */
1522 for (i = 1; i < desc->nr_channels; i++) {
1523 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1524 }
1525
1526 /* Non-uniform formats. */
1527 if (!uniform) {
1528 switch(desc->nr_channels) {
1529 case 3:
1530 if (desc->channel[0].size == 5 &&
1531 desc->channel[1].size == 6 &&
1532 desc->channel[2].size == 5) {
1533 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1534 }
1535 goto out_unknown;
1536 case 4:
1537 if (desc->channel[0].size == 5 &&
1538 desc->channel[1].size == 5 &&
1539 desc->channel[2].size == 5 &&
1540 desc->channel[3].size == 1) {
1541 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1542 }
1543 if (desc->channel[0].size == 10 &&
1544 desc->channel[1].size == 10 &&
1545 desc->channel[2].size == 10 &&
1546 desc->channel[3].size == 2) {
1547 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1548 }
1549 goto out_unknown;
1550 }
1551 goto out_unknown;
1552 }
1553
1554 if (first_non_void < 0 || first_non_void > 3)
1555 goto out_unknown;
1556
1557 /* uniform formats */
1558 switch (desc->channel[first_non_void].size) {
1559 case 4:
1560 switch (desc->nr_channels) {
1561 #if 0 /* Not supported for render targets */
1562 case 2:
1563 return V_008F14_IMG_DATA_FORMAT_4_4;
1564 #endif
1565 case 4:
1566 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1567 }
1568 break;
1569 case 8:
1570 switch (desc->nr_channels) {
1571 case 1:
1572 return V_008F14_IMG_DATA_FORMAT_8;
1573 case 2:
1574 return V_008F14_IMG_DATA_FORMAT_8_8;
1575 case 4:
1576 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1577 }
1578 break;
1579 case 16:
1580 switch (desc->nr_channels) {
1581 case 1:
1582 return V_008F14_IMG_DATA_FORMAT_16;
1583 case 2:
1584 return V_008F14_IMG_DATA_FORMAT_16_16;
1585 case 4:
1586 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1587 }
1588 break;
1589 case 32:
1590 switch (desc->nr_channels) {
1591 case 1:
1592 return V_008F14_IMG_DATA_FORMAT_32;
1593 case 2:
1594 return V_008F14_IMG_DATA_FORMAT_32_32;
1595 #if 0 /* Not supported for render targets */
1596 case 3:
1597 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1598 #endif
1599 case 4:
1600 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1601 }
1602 }
1603
1604 out_unknown:
1605 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1606 return ~0;
1607 }
1608
1609 static unsigned si_tex_wrap(unsigned wrap)
1610 {
1611 switch (wrap) {
1612 default:
1613 case PIPE_TEX_WRAP_REPEAT:
1614 return V_008F30_SQ_TEX_WRAP;
1615 case PIPE_TEX_WRAP_CLAMP:
1616 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1617 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1618 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1619 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1620 return V_008F30_SQ_TEX_CLAMP_BORDER;
1621 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1622 return V_008F30_SQ_TEX_MIRROR;
1623 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1624 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1625 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1626 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1627 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1628 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1629 }
1630 }
1631
1632 static unsigned si_tex_mipfilter(unsigned filter)
1633 {
1634 switch (filter) {
1635 case PIPE_TEX_MIPFILTER_NEAREST:
1636 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1637 case PIPE_TEX_MIPFILTER_LINEAR:
1638 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1639 default:
1640 case PIPE_TEX_MIPFILTER_NONE:
1641 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1642 }
1643 }
1644
1645 static unsigned si_tex_compare(unsigned compare)
1646 {
1647 switch (compare) {
1648 default:
1649 case PIPE_FUNC_NEVER:
1650 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1651 case PIPE_FUNC_LESS:
1652 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1653 case PIPE_FUNC_EQUAL:
1654 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1655 case PIPE_FUNC_LEQUAL:
1656 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1657 case PIPE_FUNC_GREATER:
1658 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1659 case PIPE_FUNC_NOTEQUAL:
1660 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1661 case PIPE_FUNC_GEQUAL:
1662 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1663 case PIPE_FUNC_ALWAYS:
1664 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1665 }
1666 }
1667
1668 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1669 unsigned nr_samples)
1670 {
1671 if (view_target == PIPE_TEXTURE_CUBE ||
1672 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1673 res_target = view_target;
1674 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1675 else if (res_target == PIPE_TEXTURE_CUBE ||
1676 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1677 res_target = PIPE_TEXTURE_2D_ARRAY;
1678
1679 switch (res_target) {
1680 default:
1681 case PIPE_TEXTURE_1D:
1682 return V_008F1C_SQ_RSRC_IMG_1D;
1683 case PIPE_TEXTURE_1D_ARRAY:
1684 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1685 case PIPE_TEXTURE_2D:
1686 case PIPE_TEXTURE_RECT:
1687 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1688 V_008F1C_SQ_RSRC_IMG_2D;
1689 case PIPE_TEXTURE_2D_ARRAY:
1690 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1691 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1692 case PIPE_TEXTURE_3D:
1693 return V_008F1C_SQ_RSRC_IMG_3D;
1694 case PIPE_TEXTURE_CUBE:
1695 case PIPE_TEXTURE_CUBE_ARRAY:
1696 return V_008F1C_SQ_RSRC_IMG_CUBE;
1697 }
1698 }
1699
1700 /*
1701 * Format support testing
1702 */
1703
1704 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1705 {
1706 return si_translate_texformat(screen, format, util_format_description(format),
1707 util_format_get_first_non_void_channel(format)) != ~0U;
1708 }
1709
1710 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1711 const struct util_format_description *desc,
1712 int first_non_void)
1713 {
1714 int i;
1715
1716 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1717 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1718
1719 assert(first_non_void >= 0);
1720
1721 if (desc->nr_channels == 4 &&
1722 desc->channel[0].size == 10 &&
1723 desc->channel[1].size == 10 &&
1724 desc->channel[2].size == 10 &&
1725 desc->channel[3].size == 2)
1726 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1727
1728 /* See whether the components are of the same size. */
1729 for (i = 0; i < desc->nr_channels; i++) {
1730 if (desc->channel[first_non_void].size != desc->channel[i].size)
1731 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1732 }
1733
1734 switch (desc->channel[first_non_void].size) {
1735 case 8:
1736 switch (desc->nr_channels) {
1737 case 1:
1738 case 3: /* 3 loads */
1739 return V_008F0C_BUF_DATA_FORMAT_8;
1740 case 2:
1741 return V_008F0C_BUF_DATA_FORMAT_8_8;
1742 case 4:
1743 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1744 }
1745 break;
1746 case 16:
1747 switch (desc->nr_channels) {
1748 case 1:
1749 case 3: /* 3 loads */
1750 return V_008F0C_BUF_DATA_FORMAT_16;
1751 case 2:
1752 return V_008F0C_BUF_DATA_FORMAT_16_16;
1753 case 4:
1754 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1755 }
1756 break;
1757 case 32:
1758 switch (desc->nr_channels) {
1759 case 1:
1760 return V_008F0C_BUF_DATA_FORMAT_32;
1761 case 2:
1762 return V_008F0C_BUF_DATA_FORMAT_32_32;
1763 case 3:
1764 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1765 case 4:
1766 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1767 }
1768 break;
1769 case 64:
1770 /* Legacy double formats. */
1771 switch (desc->nr_channels) {
1772 case 1: /* 1 load */
1773 return V_008F0C_BUF_DATA_FORMAT_32_32;
1774 case 2: /* 1 load */
1775 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1776 case 3: /* 3 loads */
1777 return V_008F0C_BUF_DATA_FORMAT_32_32;
1778 case 4: /* 2 loads */
1779 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1780 }
1781 break;
1782 }
1783
1784 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1785 }
1786
1787 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1788 const struct util_format_description *desc,
1789 int first_non_void)
1790 {
1791 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1792 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1793
1794 assert(first_non_void >= 0);
1795
1796 switch (desc->channel[first_non_void].type) {
1797 case UTIL_FORMAT_TYPE_SIGNED:
1798 case UTIL_FORMAT_TYPE_FIXED:
1799 if (desc->channel[first_non_void].size >= 32 ||
1800 desc->channel[first_non_void].pure_integer)
1801 return V_008F0C_BUF_NUM_FORMAT_SINT;
1802 else if (desc->channel[first_non_void].normalized)
1803 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1804 else
1805 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1806 break;
1807 case UTIL_FORMAT_TYPE_UNSIGNED:
1808 if (desc->channel[first_non_void].size >= 32 ||
1809 desc->channel[first_non_void].pure_integer)
1810 return V_008F0C_BUF_NUM_FORMAT_UINT;
1811 else if (desc->channel[first_non_void].normalized)
1812 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1813 else
1814 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1815 break;
1816 case UTIL_FORMAT_TYPE_FLOAT:
1817 default:
1818 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1819 }
1820 }
1821
1822 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1823 enum pipe_format format,
1824 unsigned usage)
1825 {
1826 const struct util_format_description *desc;
1827 int first_non_void;
1828 unsigned data_format;
1829
1830 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1831 PIPE_BIND_SAMPLER_VIEW |
1832 PIPE_BIND_VERTEX_BUFFER)) == 0);
1833
1834 desc = util_format_description(format);
1835
1836 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1837 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1838 * for read-only access (with caveats surrounding bounds checks), but
1839 * obviously fails for write access which we have to implement for
1840 * shader images. Luckily, OpenGL doesn't expect this to be supported
1841 * anyway, and so the only impact is on PBO uploads / downloads, which
1842 * shouldn't be expected to be fast for GL_RGB anyway.
1843 */
1844 if (desc->block.bits == 3 * 8 ||
1845 desc->block.bits == 3 * 16) {
1846 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1847 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1848 if (!usage)
1849 return 0;
1850 }
1851 }
1852
1853 first_non_void = util_format_get_first_non_void_channel(format);
1854 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1855 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1856 return 0;
1857
1858 return usage;
1859 }
1860
1861 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1862 {
1863 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1864 r600_translate_colorswap(format, false) != ~0U;
1865 }
1866
1867 static bool si_is_zs_format_supported(enum pipe_format format)
1868 {
1869 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1870 }
1871
1872 static boolean si_is_format_supported(struct pipe_screen *screen,
1873 enum pipe_format format,
1874 enum pipe_texture_target target,
1875 unsigned sample_count,
1876 unsigned usage)
1877 {
1878 unsigned retval = 0;
1879
1880 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1881 R600_ERR("r600: unsupported texture type %d\n", target);
1882 return false;
1883 }
1884
1885 if (!util_format_is_supported(format, usage))
1886 return false;
1887
1888 if (sample_count > 1) {
1889 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1890 return false;
1891
1892 if (usage & PIPE_BIND_SHADER_IMAGE)
1893 return false;
1894
1895 switch (sample_count) {
1896 case 2:
1897 case 4:
1898 case 8:
1899 break;
1900 case 16:
1901 if (format == PIPE_FORMAT_NONE)
1902 return true;
1903 else
1904 return false;
1905 default:
1906 return false;
1907 }
1908 }
1909
1910 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1911 PIPE_BIND_SHADER_IMAGE)) {
1912 if (target == PIPE_BUFFER) {
1913 retval |= si_is_vertex_format_supported(
1914 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1915 PIPE_BIND_SHADER_IMAGE));
1916 } else {
1917 if (si_is_sampler_format_supported(screen, format))
1918 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1919 PIPE_BIND_SHADER_IMAGE);
1920 }
1921 }
1922
1923 if ((usage & (PIPE_BIND_RENDER_TARGET |
1924 PIPE_BIND_DISPLAY_TARGET |
1925 PIPE_BIND_SCANOUT |
1926 PIPE_BIND_SHARED |
1927 PIPE_BIND_BLENDABLE)) &&
1928 si_is_colorbuffer_format_supported(format)) {
1929 retval |= usage &
1930 (PIPE_BIND_RENDER_TARGET |
1931 PIPE_BIND_DISPLAY_TARGET |
1932 PIPE_BIND_SCANOUT |
1933 PIPE_BIND_SHARED);
1934 if (!util_format_is_pure_integer(format) &&
1935 !util_format_is_depth_or_stencil(format))
1936 retval |= usage & PIPE_BIND_BLENDABLE;
1937 }
1938
1939 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1940 si_is_zs_format_supported(format)) {
1941 retval |= PIPE_BIND_DEPTH_STENCIL;
1942 }
1943
1944 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1945 retval |= si_is_vertex_format_supported(screen, format,
1946 PIPE_BIND_VERTEX_BUFFER);
1947 }
1948
1949 if ((usage & PIPE_BIND_LINEAR) &&
1950 !util_format_is_compressed(format) &&
1951 !(usage & PIPE_BIND_DEPTH_STENCIL))
1952 retval |= PIPE_BIND_LINEAR;
1953
1954 return retval == usage;
1955 }
1956
1957 /*
1958 * framebuffer handling
1959 */
1960
1961 static void si_choose_spi_color_formats(struct r600_surface *surf,
1962 unsigned format, unsigned swap,
1963 unsigned ntype, bool is_depth)
1964 {
1965 /* Alpha is needed for alpha-to-coverage.
1966 * Blending may be with or without alpha.
1967 */
1968 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1969 unsigned alpha = 0; /* exports alpha, but may not support blending */
1970 unsigned blend = 0; /* supports blending, but may not export alpha */
1971 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1972
1973 /* Choose the SPI color formats. These are required values for RB+.
1974 * Other chips have multiple choices, though they are not necessarily better.
1975 */
1976 switch (format) {
1977 case V_028C70_COLOR_5_6_5:
1978 case V_028C70_COLOR_1_5_5_5:
1979 case V_028C70_COLOR_5_5_5_1:
1980 case V_028C70_COLOR_4_4_4_4:
1981 case V_028C70_COLOR_10_11_11:
1982 case V_028C70_COLOR_11_11_10:
1983 case V_028C70_COLOR_8:
1984 case V_028C70_COLOR_8_8:
1985 case V_028C70_COLOR_8_8_8_8:
1986 case V_028C70_COLOR_10_10_10_2:
1987 case V_028C70_COLOR_2_10_10_10:
1988 if (ntype == V_028C70_NUMBER_UINT)
1989 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1990 else if (ntype == V_028C70_NUMBER_SINT)
1991 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1992 else
1993 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1994 break;
1995
1996 case V_028C70_COLOR_16:
1997 case V_028C70_COLOR_16_16:
1998 case V_028C70_COLOR_16_16_16_16:
1999 if (ntype == V_028C70_NUMBER_UNORM ||
2000 ntype == V_028C70_NUMBER_SNORM) {
2001 /* UNORM16 and SNORM16 don't support blending */
2002 if (ntype == V_028C70_NUMBER_UNORM)
2003 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2004 else
2005 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2006
2007 /* Use 32 bits per channel for blending. */
2008 if (format == V_028C70_COLOR_16) {
2009 if (swap == V_028C70_SWAP_STD) { /* R */
2010 blend = V_028714_SPI_SHADER_32_R;
2011 blend_alpha = V_028714_SPI_SHADER_32_AR;
2012 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2013 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2014 else
2015 assert(0);
2016 } else if (format == V_028C70_COLOR_16_16) {
2017 if (swap == V_028C70_SWAP_STD) { /* RG */
2018 blend = V_028714_SPI_SHADER_32_GR;
2019 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2020 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2021 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2022 else
2023 assert(0);
2024 } else /* 16_16_16_16 */
2025 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2026 } else if (ntype == V_028C70_NUMBER_UINT)
2027 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2028 else if (ntype == V_028C70_NUMBER_SINT)
2029 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2030 else if (ntype == V_028C70_NUMBER_FLOAT)
2031 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2032 else
2033 assert(0);
2034 break;
2035
2036 case V_028C70_COLOR_32:
2037 if (swap == V_028C70_SWAP_STD) { /* R */
2038 blend = normal = V_028714_SPI_SHADER_32_R;
2039 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2040 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2041 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2042 else
2043 assert(0);
2044 break;
2045
2046 case V_028C70_COLOR_32_32:
2047 if (swap == V_028C70_SWAP_STD) { /* RG */
2048 blend = normal = V_028714_SPI_SHADER_32_GR;
2049 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2050 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2051 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2052 else
2053 assert(0);
2054 break;
2055
2056 case V_028C70_COLOR_32_32_32_32:
2057 case V_028C70_COLOR_8_24:
2058 case V_028C70_COLOR_24_8:
2059 case V_028C70_COLOR_X24_8_32_FLOAT:
2060 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2061 break;
2062
2063 default:
2064 assert(0);
2065 return;
2066 }
2067
2068 /* The DB->CB copy needs 32_ABGR. */
2069 if (is_depth)
2070 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2071
2072 surf->spi_shader_col_format = normal;
2073 surf->spi_shader_col_format_alpha = alpha;
2074 surf->spi_shader_col_format_blend = blend;
2075 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2076 }
2077
2078 static void si_initialize_color_surface(struct si_context *sctx,
2079 struct r600_surface *surf)
2080 {
2081 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2082 unsigned color_info, color_attrib, color_view;
2083 unsigned format, swap, ntype, endian;
2084 const struct util_format_description *desc;
2085 int i;
2086 unsigned blend_clamp = 0, blend_bypass = 0;
2087
2088 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2089 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2090
2091 desc = util_format_description(surf->base.format);
2092 for (i = 0; i < 4; i++) {
2093 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2094 break;
2095 }
2096 }
2097 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2098 ntype = V_028C70_NUMBER_FLOAT;
2099 } else {
2100 ntype = V_028C70_NUMBER_UNORM;
2101 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2102 ntype = V_028C70_NUMBER_SRGB;
2103 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2104 if (desc->channel[i].pure_integer) {
2105 ntype = V_028C70_NUMBER_SINT;
2106 } else {
2107 assert(desc->channel[i].normalized);
2108 ntype = V_028C70_NUMBER_SNORM;
2109 }
2110 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2111 if (desc->channel[i].pure_integer) {
2112 ntype = V_028C70_NUMBER_UINT;
2113 } else {
2114 assert(desc->channel[i].normalized);
2115 ntype = V_028C70_NUMBER_UNORM;
2116 }
2117 }
2118 }
2119
2120 format = si_translate_colorformat(surf->base.format);
2121 if (format == V_028C70_COLOR_INVALID) {
2122 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2123 }
2124 assert(format != V_028C70_COLOR_INVALID);
2125 swap = r600_translate_colorswap(surf->base.format, false);
2126 endian = si_colorformat_endian_swap(format);
2127
2128 /* blend clamp should be set for all NORM/SRGB types */
2129 if (ntype == V_028C70_NUMBER_UNORM ||
2130 ntype == V_028C70_NUMBER_SNORM ||
2131 ntype == V_028C70_NUMBER_SRGB)
2132 blend_clamp = 1;
2133
2134 /* set blend bypass according to docs if SINT/UINT or
2135 8/24 COLOR variants */
2136 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2137 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2138 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2139 blend_clamp = 0;
2140 blend_bypass = 1;
2141 }
2142
2143 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2144 if (format == V_028C70_COLOR_8 ||
2145 format == V_028C70_COLOR_8_8 ||
2146 format == V_028C70_COLOR_8_8_8_8)
2147 surf->color_is_int8 = true;
2148 else if (format == V_028C70_COLOR_10_10_10_2 ||
2149 format == V_028C70_COLOR_2_10_10_10)
2150 surf->color_is_int10 = true;
2151 }
2152
2153 color_info = S_028C70_FORMAT(format) |
2154 S_028C70_COMP_SWAP(swap) |
2155 S_028C70_BLEND_CLAMP(blend_clamp) |
2156 S_028C70_BLEND_BYPASS(blend_bypass) |
2157 S_028C70_SIMPLE_FLOAT(1) |
2158 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2159 ntype != V_028C70_NUMBER_SNORM &&
2160 ntype != V_028C70_NUMBER_SRGB &&
2161 format != V_028C70_COLOR_8_24 &&
2162 format != V_028C70_COLOR_24_8) |
2163 S_028C70_NUMBER_TYPE(ntype) |
2164 S_028C70_ENDIAN(endian);
2165
2166 /* Intensity is implemented as Red, so treat it that way. */
2167 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2168 util_format_is_intensity(surf->base.format));
2169
2170 if (rtex->resource.b.b.nr_samples > 1) {
2171 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2172
2173 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2174 S_028C74_NUM_FRAGMENTS(log_samples);
2175
2176 if (rtex->fmask.size) {
2177 color_info |= S_028C70_COMPRESSION(1);
2178 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2179
2180 if (sctx->b.chip_class == SI) {
2181 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2182 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2183 }
2184 }
2185 }
2186
2187 surf->cb_color_view = color_view;
2188 surf->cb_color_info = color_info;
2189 surf->cb_color_attrib = color_attrib;
2190
2191 if (sctx->b.chip_class >= VI) {
2192 unsigned max_uncompressed_block_size = 2;
2193
2194 if (rtex->resource.b.b.nr_samples > 1) {
2195 if (rtex->surface.bpe == 1)
2196 max_uncompressed_block_size = 0;
2197 else if (rtex->surface.bpe == 2)
2198 max_uncompressed_block_size = 1;
2199 }
2200
2201 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2202 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2203 }
2204
2205 /* This must be set for fast clear to work without FMASK. */
2206 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2207 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2208 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2209 }
2210
2211 if (sctx->b.chip_class >= GFX9) {
2212 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2213 unsigned type;
2214
2215 switch (rtex->resource.b.b.target) {
2216 case PIPE_TEXTURE_1D:
2217 case PIPE_TEXTURE_1D_ARRAY:
2218 type = V_028C74_1D;
2219 break;
2220 default:
2221 type = V_028C74_2D;
2222 break;
2223 case PIPE_TEXTURE_3D:
2224 type = V_028C74_3D;
2225 break;
2226 }
2227
2228 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2229 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2230 S_028C74_RESOURCE_TYPE(type);
2231 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(rtex->resource.b.b.width0 - 1) |
2232 S_028C68_MIP0_HEIGHT(rtex->resource.b.b.height0 - 1) |
2233 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2234 }
2235
2236 /* Determine pixel shader export format */
2237 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2238
2239 surf->color_initialized = true;
2240 }
2241
2242 static void si_init_depth_surface(struct si_context *sctx,
2243 struct r600_surface *surf)
2244 {
2245 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2246 unsigned level = surf->base.u.tex.level;
2247 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2248 unsigned format, stencil_format;
2249 uint32_t z_info, s_info;
2250
2251 format = si_translate_dbformat(rtex->db_render_format);
2252 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2253 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2254
2255 assert(format != V_028040_Z_INVALID);
2256 if (format == V_028040_Z_INVALID)
2257 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2258
2259 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2260 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2261 surf->db_htile_data_base = 0;
2262 surf->db_htile_surface = 0;
2263
2264 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2265
2266 surf->db_depth_base = (rtex->resource.gpu_address +
2267 rtex->surface.u.legacy.level[level].offset) >> 8;
2268 surf->db_stencil_base = (rtex->resource.gpu_address +
2269 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2270
2271 z_info = S_028040_FORMAT(format) |
2272 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2273 s_info = S_028044_FORMAT(stencil_format);
2274 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2275
2276 if (sctx->b.chip_class >= CIK) {
2277 struct radeon_info *info = &sctx->screen->b.info;
2278 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2279 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2280 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2281 unsigned tile_mode = info->si_tile_mode_array[index];
2282 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2283 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2284
2285 surf->db_depth_info |=
2286 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2287 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2288 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2289 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2290 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2291 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2292 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2293 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2294 } else {
2295 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2296 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2297 tile_mode_index = si_tile_mode_index(rtex, level, true);
2298 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2299 }
2300
2301 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2302 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2303 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2304 levelinfo->nblk_y) / 64 - 1);
2305
2306 /* Only use HTILE for the first level. */
2307 if (rtex->htile_buffer && !level) {
2308 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2309 S_028040_ALLOW_EXPCLEAR(1);
2310
2311 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2312 /* Workaround: For a not yet understood reason, the
2313 * combination of MSAA, fast stencil clear and stencil
2314 * decompress messes with subsequent stencil buffer
2315 * uses. Problem was reproduced on Verde, Bonaire,
2316 * Tonga, and Carrizo.
2317 *
2318 * Disabling EXPCLEAR works around the problem.
2319 *
2320 * Check piglit's arb_texture_multisample-stencil-clear
2321 * test if you want to try changing this.
2322 */
2323 if (rtex->resource.b.b.nr_samples <= 1)
2324 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2325 } else if (!rtex->tc_compatible_htile) {
2326 /* Use all of the htile_buffer for depth if there's no stencil.
2327 * This must not be set when TC-compatible HTILE is enabled
2328 * due to a hw bug.
2329 */
2330 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2331 }
2332
2333 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2334 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2335
2336 if (rtex->tc_compatible_htile) {
2337 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2338
2339 if (rtex->resource.b.b.nr_samples <= 1)
2340 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2341 else if (rtex->resource.b.b.nr_samples <= 4)
2342 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2343 else
2344 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2345 }
2346 }
2347
2348 surf->db_z_info = z_info;
2349 surf->db_stencil_info = s_info;
2350
2351 surf->depth_initialized = true;
2352 }
2353
2354 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2355 {
2356 for (int i = 0; i < state->nr_cbufs; ++i) {
2357 struct r600_surface *surf = NULL;
2358 struct r600_texture *rtex;
2359
2360 if (!state->cbufs[i])
2361 continue;
2362 surf = (struct r600_surface*)state->cbufs[i];
2363 rtex = (struct r600_texture*)surf->base.texture;
2364
2365 p_atomic_dec(&rtex->framebuffers_bound);
2366 }
2367 }
2368
2369 static void si_set_framebuffer_state(struct pipe_context *ctx,
2370 const struct pipe_framebuffer_state *state)
2371 {
2372 struct si_context *sctx = (struct si_context *)ctx;
2373 struct pipe_constant_buffer constbuf = {0};
2374 struct r600_surface *surf = NULL;
2375 struct r600_texture *rtex;
2376 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2377 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2378 int i;
2379
2380 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2381 if (!sctx->framebuffer.state.cbufs[i])
2382 continue;
2383
2384 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2385 if (rtex->dcc_gather_statistics)
2386 vi_separate_dcc_stop_query(ctx, rtex);
2387 }
2388
2389 /* Only flush TC when changing the framebuffer state, because
2390 * the only client not using TC that can change textures is
2391 * the framebuffer.
2392 *
2393 * Flush all CB and DB caches here because all buffers can be used
2394 * for write by both TC (with shader image stores) and CB/DB.
2395 */
2396 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2397 SI_CONTEXT_INV_GLOBAL_L2 |
2398 SI_CONTEXT_FLUSH_AND_INV_CB |
2399 SI_CONTEXT_FLUSH_AND_INV_DB |
2400 SI_CONTEXT_CS_PARTIAL_FLUSH;
2401
2402 /* Take the maximum of the old and new count. If the new count is lower,
2403 * dirtying is needed to disable the unbound colorbuffers.
2404 */
2405 sctx->framebuffer.dirty_cbufs |=
2406 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2407 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2408
2409 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2410 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2411
2412 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2413 sctx->framebuffer.spi_shader_col_format = 0;
2414 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2415 sctx->framebuffer.spi_shader_col_format_blend = 0;
2416 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2417 sctx->framebuffer.color_is_int8 = 0;
2418 sctx->framebuffer.color_is_int10 = 0;
2419
2420 sctx->framebuffer.compressed_cb_mask = 0;
2421 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2422 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2423 sctx->framebuffer.any_dst_linear = false;
2424
2425 for (i = 0; i < state->nr_cbufs; i++) {
2426 if (!state->cbufs[i])
2427 continue;
2428
2429 surf = (struct r600_surface*)state->cbufs[i];
2430 rtex = (struct r600_texture*)surf->base.texture;
2431
2432 if (!surf->color_initialized) {
2433 si_initialize_color_surface(sctx, surf);
2434 }
2435
2436 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2437 sctx->framebuffer.spi_shader_col_format |=
2438 surf->spi_shader_col_format << (i * 4);
2439 sctx->framebuffer.spi_shader_col_format_alpha |=
2440 surf->spi_shader_col_format_alpha << (i * 4);
2441 sctx->framebuffer.spi_shader_col_format_blend |=
2442 surf->spi_shader_col_format_blend << (i * 4);
2443 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2444 surf->spi_shader_col_format_blend_alpha << (i * 4);
2445
2446 if (surf->color_is_int8)
2447 sctx->framebuffer.color_is_int8 |= 1 << i;
2448 if (surf->color_is_int10)
2449 sctx->framebuffer.color_is_int10 |= 1 << i;
2450
2451 if (rtex->fmask.size) {
2452 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2453 }
2454
2455 if (rtex->surface.is_linear)
2456 sctx->framebuffer.any_dst_linear = true;
2457
2458 r600_context_add_resource_size(ctx, surf->base.texture);
2459
2460 p_atomic_inc(&rtex->framebuffers_bound);
2461
2462 if (rtex->dcc_gather_statistics) {
2463 /* Dirty tracking must be enabled for DCC usage analysis. */
2464 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2465 vi_separate_dcc_start_query(ctx, rtex);
2466 }
2467 }
2468
2469 if (state->zsbuf) {
2470 surf = (struct r600_surface*)state->zsbuf;
2471 rtex = (struct r600_texture*)surf->base.texture;
2472
2473 if (!surf->depth_initialized) {
2474 si_init_depth_surface(sctx, surf);
2475 }
2476 r600_context_add_resource_size(ctx, surf->base.texture);
2477 }
2478
2479 si_update_poly_offset_state(sctx);
2480 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2481 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2482
2483 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2484 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2485
2486 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2487 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2488 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2489
2490 /* Set sample locations as fragment shader constants. */
2491 switch (sctx->framebuffer.nr_samples) {
2492 case 1:
2493 constbuf.user_buffer = sctx->b.sample_locations_1x;
2494 break;
2495 case 2:
2496 constbuf.user_buffer = sctx->b.sample_locations_2x;
2497 break;
2498 case 4:
2499 constbuf.user_buffer = sctx->b.sample_locations_4x;
2500 break;
2501 case 8:
2502 constbuf.user_buffer = sctx->b.sample_locations_8x;
2503 break;
2504 case 16:
2505 constbuf.user_buffer = sctx->b.sample_locations_16x;
2506 break;
2507 default:
2508 R600_ERR("Requested an invalid number of samples %i.\n",
2509 sctx->framebuffer.nr_samples);
2510 assert(0);
2511 }
2512 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2513 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2514
2515 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2516 }
2517
2518 sctx->need_check_render_feedback = true;
2519 sctx->do_update_shaders = true;
2520 sctx->framebuffer.do_update_surf_dirtiness = true;
2521 }
2522
2523 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2524 {
2525 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2526 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2527 unsigned i, nr_cbufs = state->nr_cbufs;
2528 struct r600_texture *tex = NULL;
2529 struct r600_surface *cb = NULL;
2530 unsigned cb_color_info = 0;
2531
2532 /* Colorbuffers. */
2533 for (i = 0; i < nr_cbufs; i++) {
2534 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2535 unsigned cb_color_attrib;
2536
2537 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2538 continue;
2539
2540 cb = (struct r600_surface*)state->cbufs[i];
2541 if (!cb) {
2542 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2543 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2544 continue;
2545 }
2546
2547 tex = (struct r600_texture *)cb->base.texture;
2548 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2549 &tex->resource, RADEON_USAGE_READWRITE,
2550 tex->resource.b.b.nr_samples > 1 ?
2551 RADEON_PRIO_COLOR_BUFFER_MSAA :
2552 RADEON_PRIO_COLOR_BUFFER);
2553
2554 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2555 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2556 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2557 RADEON_PRIO_CMASK);
2558 }
2559
2560 if (tex->dcc_separate_buffer)
2561 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2562 tex->dcc_separate_buffer,
2563 RADEON_USAGE_READWRITE,
2564 RADEON_PRIO_DCC);
2565
2566 /* Compute mutable surface parameters. */
2567 cb_color_base = tex->resource.gpu_address >> 8;
2568 cb_color_fmask = cb_color_base;
2569 cb_dcc_base = 0;
2570 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2571 cb_color_attrib = cb->cb_color_attrib;
2572
2573 if (tex->fmask.size)
2574 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2575
2576 /* Set up DCC. */
2577 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2578 bool is_msaa_resolve_dst = state->cbufs[0] &&
2579 state->cbufs[0]->texture->nr_samples > 1 &&
2580 state->cbufs[1] == &cb->base &&
2581 state->cbufs[1]->texture->nr_samples <= 1;
2582
2583 if (!is_msaa_resolve_dst)
2584 cb_color_info |= S_028C70_DCC_ENABLE(1);
2585
2586 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2587 tex->dcc_offset) >> 8;
2588 }
2589
2590 if (sctx->b.chip_class >= GFX9) {
2591 struct gfx9_surf_meta_flags meta;
2592
2593 if (tex->dcc_offset)
2594 meta = tex->surface.u.gfx9.dcc;
2595 else
2596 meta = tex->surface.u.gfx9.cmask;
2597
2598 /* Set mutable surface parameters. */
2599 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2600 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2601 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2602 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2603
2604 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2605 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2606 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2607 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2608 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2609 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2610 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2611 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2612 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2613 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2614 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2615 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2616 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2617 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2618 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2619 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2620
2621 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2622 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2623 } else {
2624 /* Compute mutable surface parameters (SI-CI-VI). */
2625 const struct legacy_surf_level *level_info =
2626 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2627 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2628 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2629
2630 cb_color_base += level_info->offset >> 8;
2631 if (cb_dcc_base)
2632 cb_dcc_base += level_info->dcc_offset >> 8;
2633
2634 pitch_tile_max = level_info->nblk_x / 8 - 1;
2635 slice_tile_max = level_info->nblk_x *
2636 level_info->nblk_y / 64 - 1;
2637 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2638
2639 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2640 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2641 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2642
2643 if (tex->fmask.size) {
2644 if (sctx->b.chip_class >= CIK)
2645 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2646 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2647 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2648 } else {
2649 /* This must be set for fast clear to work without FMASK. */
2650 if (sctx->b.chip_class >= CIK)
2651 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2652 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2653 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2654 }
2655
2656 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2657 sctx->b.chip_class >= VI ? 14 : 13);
2658 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2659 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2660 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2661 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2662 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2663 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2664 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2665 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2666 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2667 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2668 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2669 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2670 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2671
2672 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2673 radeon_emit(cs, cb_dcc_base);
2674 }
2675 }
2676 for (; i < 8 ; i++)
2677 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2678 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2679
2680 /* ZS buffer. */
2681 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2682 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2683 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2684
2685 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2686 &rtex->resource, RADEON_USAGE_READWRITE,
2687 zb->base.texture->nr_samples > 1 ?
2688 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2689 RADEON_PRIO_DEPTH_BUFFER);
2690
2691 if (zb->db_htile_data_base) {
2692 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2693 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2694 RADEON_PRIO_HTILE);
2695 }
2696
2697 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2698 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2699
2700 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2701 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2702 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2703 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2704 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2705 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2706 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2707 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2708 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2709 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2710 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2711
2712 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2713 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2714 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2715
2716 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2717 } else if (sctx->framebuffer.dirty_zsbuf) {
2718 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2719 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2720 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2721 }
2722
2723 /* Framebuffer dimensions. */
2724 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2725 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2726 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2727
2728 sctx->framebuffer.dirty_cbufs = 0;
2729 sctx->framebuffer.dirty_zsbuf = false;
2730 }
2731
2732 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2733 struct r600_atom *atom)
2734 {
2735 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2736 unsigned nr_samples = sctx->framebuffer.nr_samples;
2737
2738 /* Smoothing (only possible with nr_samples == 1) uses the same
2739 * sample locations as the MSAA it simulates.
2740 */
2741 if (nr_samples <= 1 && sctx->smoothing_enabled)
2742 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2743
2744 /* On Polaris, the small primitive filter uses the sample locations
2745 * even when MSAA is off, so we need to make sure they're set to 0.
2746 */
2747 if (sctx->b.family >= CHIP_POLARIS10)
2748 nr_samples = MAX2(nr_samples, 1);
2749
2750 if (nr_samples >= 1 &&
2751 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2752 sctx->msaa_sample_locs.nr_samples = nr_samples;
2753 cayman_emit_msaa_sample_locs(cs, nr_samples);
2754 }
2755
2756 if (sctx->b.family >= CHIP_POLARIS10) {
2757 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2758 unsigned small_prim_filter_cntl =
2759 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2760 S_028830_LINE_FILTER_DISABLE(sctx->b.chip_class == VI); /* line bug */
2761
2762 /* The alternative of setting sample locations to 0 would
2763 * require a DB flush to avoid Z errors, see
2764 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2765 */
2766 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2767 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2768
2769 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2770 small_prim_filter_cntl);
2771 }
2772 }
2773
2774 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2775 {
2776 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2777 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2778 /* 33% faster rendering to linear color buffers */
2779 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2780 unsigned sc_mode_cntl_1 =
2781 S_028A4C_WALK_SIZE(dst_is_linear) |
2782 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2783 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2784 /* always 1: */
2785 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2786 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2787 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2788 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2789 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2790 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2791
2792 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2793 sctx->ps_iter_samples,
2794 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2795 sc_mode_cntl_1);
2796 }
2797
2798 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2799 {
2800 struct si_context *sctx = (struct si_context *)ctx;
2801
2802 if (sctx->ps_iter_samples == min_samples)
2803 return;
2804
2805 sctx->ps_iter_samples = min_samples;
2806 sctx->do_update_shaders = true;
2807
2808 if (sctx->framebuffer.nr_samples > 1)
2809 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2810 }
2811
2812 /*
2813 * Samplers
2814 */
2815
2816 /**
2817 * Build the sampler view descriptor for a buffer texture.
2818 * @param state 256-bit descriptor; only the high 128 bits are filled in
2819 */
2820 void
2821 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2822 enum pipe_format format,
2823 unsigned offset, unsigned size,
2824 uint32_t *state)
2825 {
2826 const struct util_format_description *desc;
2827 int first_non_void;
2828 unsigned stride;
2829 unsigned num_records;
2830 unsigned num_format, data_format;
2831
2832 desc = util_format_description(format);
2833 first_non_void = util_format_get_first_non_void_channel(format);
2834 stride = desc->block.bits / 8;
2835 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2836 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2837
2838 num_records = size / stride;
2839 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2840
2841 if (screen->b.chip_class == VI)
2842 num_records *= stride;
2843
2844 state[4] = 0;
2845 state[5] = S_008F04_STRIDE(stride);
2846 state[6] = num_records;
2847 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2848 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2849 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2850 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2851 S_008F0C_NUM_FORMAT(num_format) |
2852 S_008F0C_DATA_FORMAT(data_format);
2853 }
2854
2855 /**
2856 * Build the sampler view descriptor for a texture.
2857 */
2858 void
2859 si_make_texture_descriptor(struct si_screen *screen,
2860 struct r600_texture *tex,
2861 bool sampler,
2862 enum pipe_texture_target target,
2863 enum pipe_format pipe_format,
2864 const unsigned char state_swizzle[4],
2865 unsigned first_level, unsigned last_level,
2866 unsigned first_layer, unsigned last_layer,
2867 unsigned width, unsigned height, unsigned depth,
2868 uint32_t *state,
2869 uint32_t *fmask_state)
2870 {
2871 struct pipe_resource *res = &tex->resource.b.b;
2872 const struct util_format_description *desc;
2873 unsigned char swizzle[4];
2874 int first_non_void;
2875 unsigned num_format, data_format, type;
2876 uint64_t va;
2877
2878 desc = util_format_description(pipe_format);
2879
2880 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2881 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2882 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2883 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
2884
2885 switch (pipe_format) {
2886 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2887 case PIPE_FORMAT_X32_S8X24_UINT:
2888 case PIPE_FORMAT_X8Z24_UNORM:
2889 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2890 break;
2891 case PIPE_FORMAT_X24S8_UINT:
2892 /*
2893 * X24S8 is implemented as an 8_8_8_8 data format, to
2894 * fix texture gathers. This affects at least
2895 * GL45-CTS.texture_cube_map_array.sampling on VI.
2896 */
2897 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
2898 break;
2899 default:
2900 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2901 }
2902 } else {
2903 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2904 }
2905
2906 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2907
2908 switch (pipe_format) {
2909 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2910 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2911 break;
2912 default:
2913 if (first_non_void < 0) {
2914 if (util_format_is_compressed(pipe_format)) {
2915 switch (pipe_format) {
2916 case PIPE_FORMAT_DXT1_SRGB:
2917 case PIPE_FORMAT_DXT1_SRGBA:
2918 case PIPE_FORMAT_DXT3_SRGBA:
2919 case PIPE_FORMAT_DXT5_SRGBA:
2920 case PIPE_FORMAT_BPTC_SRGBA:
2921 case PIPE_FORMAT_ETC2_SRGB8:
2922 case PIPE_FORMAT_ETC2_SRGB8A1:
2923 case PIPE_FORMAT_ETC2_SRGBA8:
2924 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2925 break;
2926 case PIPE_FORMAT_RGTC1_SNORM:
2927 case PIPE_FORMAT_LATC1_SNORM:
2928 case PIPE_FORMAT_RGTC2_SNORM:
2929 case PIPE_FORMAT_LATC2_SNORM:
2930 case PIPE_FORMAT_ETC2_R11_SNORM:
2931 case PIPE_FORMAT_ETC2_RG11_SNORM:
2932 /* implies float, so use SNORM/UNORM to determine
2933 whether data is signed or not */
2934 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2935 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2936 break;
2937 default:
2938 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2939 break;
2940 }
2941 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2942 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2943 } else {
2944 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2945 }
2946 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2947 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2948 } else {
2949 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2950
2951 switch (desc->channel[first_non_void].type) {
2952 case UTIL_FORMAT_TYPE_FLOAT:
2953 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2954 break;
2955 case UTIL_FORMAT_TYPE_SIGNED:
2956 if (desc->channel[first_non_void].normalized)
2957 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2958 else if (desc->channel[first_non_void].pure_integer)
2959 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2960 else
2961 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2962 break;
2963 case UTIL_FORMAT_TYPE_UNSIGNED:
2964 if (desc->channel[first_non_void].normalized)
2965 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2966 else if (desc->channel[first_non_void].pure_integer)
2967 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2968 else
2969 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2970 }
2971 }
2972 }
2973
2974 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2975 if (data_format == ~0) {
2976 data_format = 0;
2977 }
2978
2979 if (!sampler &&
2980 (res->target == PIPE_TEXTURE_CUBE ||
2981 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2982 res->target == PIPE_TEXTURE_3D)) {
2983 /* For the purpose of shader images, treat cube maps and 3D
2984 * textures as 2D arrays. For 3D textures, the address
2985 * calculations for mipmaps are different, so we rely on the
2986 * caller to effectively disable mipmaps.
2987 */
2988 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2989
2990 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2991 } else {
2992 type = si_tex_dim(res->target, target, res->nr_samples);
2993 }
2994
2995 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2996 height = 1;
2997 depth = res->array_size;
2998 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2999 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3000 if (sampler || res->target != PIPE_TEXTURE_3D)
3001 depth = res->array_size;
3002 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3003 depth = res->array_size / 6;
3004
3005 state[0] = 0;
3006 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3007 S_008F14_NUM_FORMAT_GFX6(num_format));
3008 state[2] = (S_008F18_WIDTH(width - 1) |
3009 S_008F18_HEIGHT(height - 1) |
3010 S_008F18_PERF_MOD(4));
3011 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3012 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3013 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3014 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3015 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3016 0 : first_level) |
3017 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3018 util_logbase2(res->nr_samples) :
3019 last_level) |
3020 S_008F1C_POW2_PAD(res->last_level > 0) |
3021 S_008F1C_TYPE(type));
3022 state[4] = S_008F20_DEPTH(depth - 1);
3023 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
3024 S_008F24_LAST_ARRAY(last_layer));
3025 state[6] = 0;
3026 state[7] = 0;
3027
3028 if (tex->dcc_offset) {
3029 unsigned swap = r600_translate_colorswap(pipe_format, false);
3030
3031 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3032 } else {
3033 /* The last dword is unused by hw. The shader uses it to clear
3034 * bits in the first dword of sampler state.
3035 */
3036 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3037 if (first_level == last_level)
3038 state[7] = C_008F30_MAX_ANISO_RATIO;
3039 else
3040 state[7] = 0xffffffff;
3041 }
3042 }
3043
3044 /* Initialize the sampler view for FMASK. */
3045 if (tex->fmask.size) {
3046 uint32_t fmask_format;
3047
3048 va = tex->resource.gpu_address + tex->fmask.offset;
3049
3050 switch (res->nr_samples) {
3051 case 2:
3052 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3053 break;
3054 case 4:
3055 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3056 break;
3057 case 8:
3058 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3059 break;
3060 default:
3061 assert(0);
3062 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3063 }
3064
3065 fmask_state[0] = va >> 8;
3066 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3067 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
3068 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_UINT);
3069 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3070 S_008F18_HEIGHT(height - 1);
3071 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3072 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3073 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3074 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3075 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3076 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3077 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3078 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3079 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3080 S_008F24_LAST_ARRAY(last_layer);
3081 fmask_state[6] = 0;
3082 fmask_state[7] = 0;
3083 }
3084 }
3085
3086 /**
3087 * Create a sampler view.
3088 *
3089 * @param ctx context
3090 * @param texture texture
3091 * @param state sampler view template
3092 * @param width0 width0 override (for compressed textures as int)
3093 * @param height0 height0 override (for compressed textures as int)
3094 * @param force_level set the base address to the level (for compressed textures)
3095 */
3096 struct pipe_sampler_view *
3097 si_create_sampler_view_custom(struct pipe_context *ctx,
3098 struct pipe_resource *texture,
3099 const struct pipe_sampler_view *state,
3100 unsigned width0, unsigned height0,
3101 unsigned force_level)
3102 {
3103 struct si_context *sctx = (struct si_context*)ctx;
3104 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3105 struct r600_texture *tmp = (struct r600_texture*)texture;
3106 unsigned base_level, first_level, last_level;
3107 unsigned char state_swizzle[4];
3108 unsigned height, depth, width;
3109 unsigned last_layer = state->u.tex.last_layer;
3110 enum pipe_format pipe_format;
3111 const struct legacy_surf_level *surflevel;
3112
3113 if (!view)
3114 return NULL;
3115
3116 /* initialize base object */
3117 view->base = *state;
3118 view->base.texture = NULL;
3119 view->base.reference.count = 1;
3120 view->base.context = ctx;
3121
3122 assert(texture);
3123 pipe_resource_reference(&view->base.texture, texture);
3124
3125 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3126 state->format == PIPE_FORMAT_S8X24_UINT ||
3127 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3128 state->format == PIPE_FORMAT_S8_UINT)
3129 view->is_stencil_sampler = true;
3130
3131 /* Buffer resource. */
3132 if (texture->target == PIPE_BUFFER) {
3133 si_make_buffer_descriptor(sctx->screen,
3134 (struct r600_resource *)texture,
3135 state->format,
3136 state->u.buf.offset,
3137 state->u.buf.size,
3138 view->state);
3139 return &view->base;
3140 }
3141
3142 state_swizzle[0] = state->swizzle_r;
3143 state_swizzle[1] = state->swizzle_g;
3144 state_swizzle[2] = state->swizzle_b;
3145 state_swizzle[3] = state->swizzle_a;
3146
3147 base_level = 0;
3148 first_level = state->u.tex.first_level;
3149 last_level = state->u.tex.last_level;
3150 width = width0;
3151 height = height0;
3152 depth = texture->depth0;
3153
3154 if (force_level) {
3155 assert(force_level == first_level &&
3156 force_level == last_level);
3157 base_level = force_level;
3158 first_level = 0;
3159 last_level = 0;
3160 width = u_minify(width, force_level);
3161 height = u_minify(height, force_level);
3162 depth = u_minify(depth, force_level);
3163 }
3164
3165 /* This is not needed if state trackers set last_layer correctly. */
3166 if (state->target == PIPE_TEXTURE_1D ||
3167 state->target == PIPE_TEXTURE_2D ||
3168 state->target == PIPE_TEXTURE_RECT ||
3169 state->target == PIPE_TEXTURE_CUBE)
3170 last_layer = state->u.tex.first_layer;
3171
3172 /* Texturing with separate depth and stencil. */
3173 pipe_format = state->format;
3174
3175 /* Depth/stencil texturing sometimes needs separate texture. */
3176 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3177 if (!tmp->flushed_depth_texture &&
3178 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3179 pipe_resource_reference(&view->base.texture, NULL);
3180 FREE(view);
3181 return NULL;
3182 }
3183
3184 assert(tmp->flushed_depth_texture);
3185
3186 /* Override format for the case where the flushed texture
3187 * contains only Z or only S.
3188 */
3189 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3190 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3191
3192 tmp = tmp->flushed_depth_texture;
3193 }
3194
3195 surflevel = tmp->surface.u.legacy.level;
3196
3197 if (tmp->db_compatible) {
3198 if (!view->is_stencil_sampler)
3199 pipe_format = tmp->db_render_format;
3200
3201 switch (pipe_format) {
3202 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3203 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3204 break;
3205 case PIPE_FORMAT_X8Z24_UNORM:
3206 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3207 /* Z24 is always stored like this for DB
3208 * compatibility.
3209 */
3210 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3211 break;
3212 case PIPE_FORMAT_X24S8_UINT:
3213 case PIPE_FORMAT_S8X24_UINT:
3214 case PIPE_FORMAT_X32_S8X24_UINT:
3215 pipe_format = PIPE_FORMAT_S8_UINT;
3216 surflevel = tmp->surface.u.legacy.stencil_level;
3217 break;
3218 default:;
3219 }
3220 }
3221
3222 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3223 state->u.tex.first_level,
3224 state->format);
3225
3226 si_make_texture_descriptor(sctx->screen, tmp, true,
3227 state->target, pipe_format, state_swizzle,
3228 first_level, last_level,
3229 state->u.tex.first_layer, last_layer,
3230 width, height, depth,
3231 view->state, view->fmask_state);
3232
3233 view->base_level_info = &surflevel[base_level];
3234 view->base_level = base_level;
3235 view->block_width = util_format_get_blockwidth(pipe_format);
3236 return &view->base;
3237 }
3238
3239 static struct pipe_sampler_view *
3240 si_create_sampler_view(struct pipe_context *ctx,
3241 struct pipe_resource *texture,
3242 const struct pipe_sampler_view *state)
3243 {
3244 return si_create_sampler_view_custom(ctx, texture, state,
3245 texture ? texture->width0 : 0,
3246 texture ? texture->height0 : 0, 0);
3247 }
3248
3249 static void si_sampler_view_destroy(struct pipe_context *ctx,
3250 struct pipe_sampler_view *state)
3251 {
3252 struct si_sampler_view *view = (struct si_sampler_view *)state;
3253
3254 pipe_resource_reference(&state->texture, NULL);
3255 FREE(view);
3256 }
3257
3258 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3259 {
3260 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3261 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3262 (linear_filter &&
3263 (wrap == PIPE_TEX_WRAP_CLAMP ||
3264 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3265 }
3266
3267 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3268 {
3269 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3270 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3271
3272 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3273 state->border_color.ui[2] || state->border_color.ui[3]) &&
3274 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3275 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3276 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3277 }
3278
3279 static void *si_create_sampler_state(struct pipe_context *ctx,
3280 const struct pipe_sampler_state *state)
3281 {
3282 struct si_context *sctx = (struct si_context *)ctx;
3283 struct r600_common_screen *rscreen = sctx->b.screen;
3284 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3285 unsigned border_color_type, border_color_index = 0;
3286 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3287 : state->max_anisotropy;
3288 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3289
3290 if (!rstate) {
3291 return NULL;
3292 }
3293
3294 if (!sampler_state_needs_border_color(state))
3295 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3296 else if (state->border_color.f[0] == 0 &&
3297 state->border_color.f[1] == 0 &&
3298 state->border_color.f[2] == 0 &&
3299 state->border_color.f[3] == 0)
3300 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3301 else if (state->border_color.f[0] == 0 &&
3302 state->border_color.f[1] == 0 &&
3303 state->border_color.f[2] == 0 &&
3304 state->border_color.f[3] == 1)
3305 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3306 else if (state->border_color.f[0] == 1 &&
3307 state->border_color.f[1] == 1 &&
3308 state->border_color.f[2] == 1 &&
3309 state->border_color.f[3] == 1)
3310 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3311 else {
3312 int i;
3313
3314 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3315
3316 /* Check if the border has been uploaded already. */
3317 for (i = 0; i < sctx->border_color_count; i++)
3318 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3319 sizeof(state->border_color)) == 0)
3320 break;
3321
3322 if (i >= SI_MAX_BORDER_COLORS) {
3323 /* Getting 4096 unique border colors is very unlikely. */
3324 fprintf(stderr, "radeonsi: The border color table is full. "
3325 "Any new border colors will be just black. "
3326 "Please file a bug.\n");
3327 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3328 } else {
3329 if (i == sctx->border_color_count) {
3330 /* Upload a new border color. */
3331 memcpy(&sctx->border_color_table[i], &state->border_color,
3332 sizeof(state->border_color));
3333 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3334 &state->border_color,
3335 sizeof(state->border_color));
3336 sctx->border_color_count++;
3337 }
3338
3339 border_color_index = i;
3340 }
3341 }
3342
3343 #ifdef DEBUG
3344 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3345 #endif
3346 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3347 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3348 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3349 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3350 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3351 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3352 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3353 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3354 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3355 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3356 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3357 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3358 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3359 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3360 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3361 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3362 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3363 S_008F38_MIP_POINT_PRECLAMP(1) |
3364 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3365 S_008F38_FILTER_PREC_FIX(1) |
3366 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3367 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3368 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3369 return rstate;
3370 }
3371
3372 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3373 {
3374 struct si_context *sctx = (struct si_context *)ctx;
3375
3376 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3377 return;
3378
3379 sctx->sample_mask.sample_mask = sample_mask;
3380 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3381 }
3382
3383 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3384 {
3385 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3386 unsigned mask = sctx->sample_mask.sample_mask;
3387
3388 /* Needed for line and polygon smoothing as well as for the Polaris
3389 * small primitive filter. We expect the state tracker to take care of
3390 * this for us.
3391 */
3392 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3393 (mask & 1 && sctx->blitter->running));
3394
3395 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3396 radeon_emit(cs, mask | (mask << 16));
3397 radeon_emit(cs, mask | (mask << 16));
3398 }
3399
3400 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3401 {
3402 #ifdef DEBUG
3403 struct si_sampler_state *s = state;
3404
3405 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3406 s->magic = 0;
3407 #endif
3408 free(state);
3409 }
3410
3411 /*
3412 * Vertex elements & buffers
3413 */
3414
3415 static void *si_create_vertex_elements(struct pipe_context *ctx,
3416 unsigned count,
3417 const struct pipe_vertex_element *elements)
3418 {
3419 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3420 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3421 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3422 int i;
3423
3424 assert(count <= SI_MAX_ATTRIBS);
3425 if (!v)
3426 return NULL;
3427
3428 v->count = count;
3429 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3430
3431 for (i = 0; i < count; ++i) {
3432 const struct util_format_description *desc;
3433 const struct util_format_channel_description *channel;
3434 unsigned data_format, num_format;
3435 int first_non_void;
3436 unsigned vbo_index = elements[i].vertex_buffer_index;
3437 unsigned char swizzle[4];
3438
3439 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3440 FREE(v);
3441 return NULL;
3442 }
3443
3444 if (!used[vbo_index]) {
3445 v->first_vb_use_mask |= 1 << i;
3446 used[vbo_index] = true;
3447 }
3448
3449 desc = util_format_description(elements[i].src_format);
3450 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3451 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3452 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3453 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3454 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3455
3456 v->format_size[i] = desc->block.bits / 8;
3457
3458 /* The hardware always treats the 2-bit alpha channel as
3459 * unsigned, so a shader workaround is needed. The affected
3460 * chips are VI and older except Stoney (GFX8.1).
3461 */
3462 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3463 sscreen->b.chip_class <= VI &&
3464 sscreen->b.family != CHIP_STONEY) {
3465 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3466 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3467 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3468 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3469 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3470 /* This isn't actually used in OpenGL. */
3471 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3472 }
3473 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3474 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3475 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3476 else
3477 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3478 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3479 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3480 if (channel->normalized) {
3481 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3482 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3483 else
3484 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3485 } else {
3486 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3487 }
3488 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3489 if (channel->normalized) {
3490 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3491 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3492 else
3493 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3494 } else {
3495 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3496 }
3497 }
3498 } else if (channel && channel->size == 64 &&
3499 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3500 switch (desc->nr_channels) {
3501 case 1:
3502 case 2:
3503 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3504 swizzle[0] = PIPE_SWIZZLE_X;
3505 swizzle[1] = PIPE_SWIZZLE_Y;
3506 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3507 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3508 break;
3509 case 3:
3510 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3511 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3512 swizzle[1] = PIPE_SWIZZLE_Y;
3513 swizzle[2] = PIPE_SWIZZLE_0;
3514 swizzle[3] = PIPE_SWIZZLE_0;
3515 break;
3516 case 4:
3517 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3518 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3519 swizzle[1] = PIPE_SWIZZLE_Y;
3520 swizzle[2] = PIPE_SWIZZLE_Z;
3521 swizzle[3] = PIPE_SWIZZLE_W;
3522 break;
3523 default:
3524 assert(0);
3525 }
3526 } else if (channel && desc->nr_channels == 3) {
3527 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3528
3529 if (channel->size == 8) {
3530 if (channel->pure_integer)
3531 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3532 else
3533 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3534 } else if (channel->size == 16) {
3535 if (channel->pure_integer)
3536 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3537 else
3538 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3539 }
3540 }
3541
3542 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3543 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3544 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3545 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3546 S_008F0C_NUM_FORMAT(num_format) |
3547 S_008F0C_DATA_FORMAT(data_format);
3548 }
3549 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3550
3551 return v;
3552 }
3553
3554 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3555 {
3556 struct si_context *sctx = (struct si_context *)ctx;
3557 struct si_vertex_element *v = (struct si_vertex_element*)state;
3558
3559 sctx->vertex_elements = v;
3560 sctx->vertex_buffers_dirty = true;
3561 sctx->do_update_shaders = true;
3562 }
3563
3564 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3565 {
3566 struct si_context *sctx = (struct si_context *)ctx;
3567
3568 if (sctx->vertex_elements == state)
3569 sctx->vertex_elements = NULL;
3570 FREE(state);
3571 }
3572
3573 static void si_set_vertex_buffers(struct pipe_context *ctx,
3574 unsigned start_slot, unsigned count,
3575 const struct pipe_vertex_buffer *buffers)
3576 {
3577 struct si_context *sctx = (struct si_context *)ctx;
3578 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3579 int i;
3580
3581 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3582
3583 if (buffers) {
3584 for (i = 0; i < count; i++) {
3585 const struct pipe_vertex_buffer *src = buffers + i;
3586 struct pipe_vertex_buffer *dsti = dst + i;
3587
3588 if (unlikely(src->user_buffer)) {
3589 /* Zero-stride attribs only. */
3590 assert(src->stride == 0);
3591
3592 /* Assume that the user_buffer comes from
3593 * gl_current_attrib, which implies it has
3594 * 4 * 8 bytes (for dvec4 attributes).
3595 *
3596 * Use const_uploader to upload into VRAM directly.
3597 */
3598 u_upload_data(sctx->b.b.const_uploader, 0, 32, 32,
3599 src->user_buffer,
3600 &dsti->buffer_offset,
3601 &dsti->buffer);
3602 dsti->stride = 0;
3603 } else {
3604 struct pipe_resource *buf = src->buffer;
3605
3606 pipe_resource_reference(&dsti->buffer, buf);
3607 dsti->buffer_offset = src->buffer_offset;
3608 dsti->stride = src->stride;
3609 r600_context_add_resource_size(ctx, buf);
3610 if (buf)
3611 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3612 }
3613 }
3614 } else {
3615 for (i = 0; i < count; i++) {
3616 pipe_resource_reference(&dst[i].buffer, NULL);
3617 }
3618 }
3619 sctx->vertex_buffers_dirty = true;
3620 }
3621
3622 static void si_set_index_buffer(struct pipe_context *ctx,
3623 const struct pipe_index_buffer *ib)
3624 {
3625 struct si_context *sctx = (struct si_context *)ctx;
3626
3627 if (ib) {
3628 struct pipe_resource *buf = ib->buffer;
3629
3630 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3631 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3632 r600_context_add_resource_size(ctx, buf);
3633 if (buf)
3634 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3635 } else {
3636 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3637 }
3638 }
3639
3640 /*
3641 * Misc
3642 */
3643
3644 static void si_set_tess_state(struct pipe_context *ctx,
3645 const float default_outer_level[4],
3646 const float default_inner_level[2])
3647 {
3648 struct si_context *sctx = (struct si_context *)ctx;
3649 struct pipe_constant_buffer cb;
3650 float array[8];
3651
3652 memcpy(array, default_outer_level, sizeof(float) * 4);
3653 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3654
3655 cb.buffer = NULL;
3656 cb.user_buffer = NULL;
3657 cb.buffer_size = sizeof(array);
3658
3659 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3660 (void*)array, sizeof(array),
3661 &cb.buffer_offset);
3662
3663 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3664 pipe_resource_reference(&cb.buffer, NULL);
3665 }
3666
3667 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3668 {
3669 struct si_context *sctx = (struct si_context *)ctx;
3670
3671 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3672 SI_CONTEXT_INV_GLOBAL_L2 |
3673 SI_CONTEXT_FLUSH_AND_INV_CB;
3674 sctx->framebuffer.do_update_surf_dirtiness = true;
3675 }
3676
3677 /* This only ensures coherency for shader image/buffer stores. */
3678 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3679 {
3680 struct si_context *sctx = (struct si_context *)ctx;
3681
3682 /* Subsequent commands must wait for all shader invocations to
3683 * complete. */
3684 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3685 SI_CONTEXT_CS_PARTIAL_FLUSH;
3686
3687 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3688 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3689 SI_CONTEXT_INV_VMEM_L1;
3690
3691 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3692 PIPE_BARRIER_SHADER_BUFFER |
3693 PIPE_BARRIER_TEXTURE |
3694 PIPE_BARRIER_IMAGE |
3695 PIPE_BARRIER_STREAMOUT_BUFFER |
3696 PIPE_BARRIER_GLOBAL_BUFFER)) {
3697 /* As far as I can tell, L1 contents are written back to L2
3698 * automatically at end of shader, but the contents of other
3699 * L1 caches might still be stale. */
3700 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3701 }
3702
3703 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3704 /* Indices are read through TC L2 since VI.
3705 * L1 isn't used.
3706 */
3707 if (sctx->screen->b.chip_class <= CIK)
3708 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3709 }
3710
3711 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3712 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3713 SI_CONTEXT_FLUSH_AND_INV_DB;
3714
3715 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3716 PIPE_BARRIER_INDIRECT_BUFFER))
3717 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3718 }
3719
3720 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3721 {
3722 struct pipe_blend_state blend;
3723
3724 memset(&blend, 0, sizeof(blend));
3725 blend.independent_blend_enable = true;
3726 blend.rt[0].colormask = 0xf;
3727 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3728 }
3729
3730 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3731 bool include_draw_vbo)
3732 {
3733 si_need_cs_space((struct si_context*)ctx);
3734 }
3735
3736 static void si_init_config(struct si_context *sctx);
3737
3738 void si_init_state_functions(struct si_context *sctx)
3739 {
3740 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3741 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3742 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3743 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3744 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3745
3746 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3747 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3748 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3749 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3750 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3751 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3752 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3753 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3754 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3755 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3756
3757 sctx->b.b.create_blend_state = si_create_blend_state;
3758 sctx->b.b.bind_blend_state = si_bind_blend_state;
3759 sctx->b.b.delete_blend_state = si_delete_blend_state;
3760 sctx->b.b.set_blend_color = si_set_blend_color;
3761
3762 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3763 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3764 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3765
3766 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3767 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3768 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3769
3770 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3771 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3772 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3773 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3774 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3775
3776 sctx->b.b.set_clip_state = si_set_clip_state;
3777 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3778
3779 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3780 sctx->b.b.get_sample_position = cayman_get_sample_position;
3781
3782 sctx->b.b.create_sampler_state = si_create_sampler_state;
3783 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3784
3785 sctx->b.b.create_sampler_view = si_create_sampler_view;
3786 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3787
3788 sctx->b.b.set_sample_mask = si_set_sample_mask;
3789
3790 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3791 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3792 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3793 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3794 sctx->b.b.set_index_buffer = si_set_index_buffer;
3795
3796 sctx->b.b.texture_barrier = si_texture_barrier;
3797 sctx->b.b.memory_barrier = si_memory_barrier;
3798 sctx->b.b.set_min_samples = si_set_min_samples;
3799 sctx->b.b.set_tess_state = si_set_tess_state;
3800
3801 sctx->b.b.set_active_query_state = si_set_active_query_state;
3802 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3803 sctx->b.save_qbo_state = si_save_qbo_state;
3804 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3805
3806 sctx->b.b.draw_vbo = si_draw_vbo;
3807
3808 si_init_config(sctx);
3809 }
3810
3811 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3812 {
3813 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3814 }
3815
3816 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3817 struct r600_texture *rtex,
3818 struct radeon_bo_metadata *md)
3819 {
3820 struct si_screen *sscreen = (struct si_screen*)rscreen;
3821 struct pipe_resource *res = &rtex->resource.b.b;
3822 static const unsigned char swizzle[] = {
3823 PIPE_SWIZZLE_X,
3824 PIPE_SWIZZLE_Y,
3825 PIPE_SWIZZLE_Z,
3826 PIPE_SWIZZLE_W
3827 };
3828 uint32_t desc[8], i;
3829 bool is_array = util_resource_is_array_texture(res);
3830
3831 /* DRM 2.x.x doesn't support this. */
3832 if (rscreen->info.drm_major != 3)
3833 return;
3834
3835 assert(rtex->dcc_separate_buffer == NULL);
3836 assert(rtex->fmask.size == 0);
3837
3838 /* Metadata image format format version 1:
3839 * [0] = 1 (metadata format identifier)
3840 * [1] = (VENDOR_ID << 16) | PCI_ID
3841 * [2:9] = image descriptor for the whole resource
3842 * [2] is always 0, because the base address is cleared
3843 * [9] is the DCC offset bits [39:8] from the beginning of
3844 * the buffer
3845 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3846 */
3847
3848 md->metadata[0] = 1; /* metadata image format version 1 */
3849
3850 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3851 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3852
3853 si_make_texture_descriptor(sscreen, rtex, true,
3854 res->target, res->format,
3855 swizzle, 0, res->last_level, 0,
3856 is_array ? res->array_size - 1 : 0,
3857 res->width0, res->height0, res->depth0,
3858 desc, NULL);
3859
3860 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.u.legacy.level[0], 0, 0,
3861 rtex->surface.blk_w, false, desc);
3862
3863 /* Clear the base address and set the relative DCC offset. */
3864 desc[0] = 0;
3865 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3866 desc[7] = rtex->dcc_offset >> 8;
3867
3868 /* Dwords [2:9] contain the image descriptor. */
3869 memcpy(&md->metadata[2], desc, sizeof(desc));
3870
3871 /* Dwords [10:..] contain the mipmap level offsets. */
3872 for (i = 0; i <= res->last_level; i++)
3873 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
3874
3875 md->size_metadata = (11 + res->last_level) * 4;
3876 }
3877
3878 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3879 struct r600_texture *rtex,
3880 struct radeon_bo_metadata *md)
3881 {
3882 uint32_t *desc = &md->metadata[2];
3883
3884 if (rscreen->chip_class < VI)
3885 return;
3886
3887 /* Return if DCC is enabled. The texture should be set up with it
3888 * already.
3889 */
3890 if (md->size_metadata >= 11 * 4 &&
3891 md->metadata[0] != 0 &&
3892 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3893 G_008F28_COMPRESSION_EN(desc[6])) {
3894 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3895 return;
3896 }
3897
3898 /* Disable DCC. These are always set by texture_from_handle and must
3899 * be cleared here.
3900 */
3901 rtex->dcc_offset = 0;
3902 }
3903
3904 void si_init_screen_state_functions(struct si_screen *sscreen)
3905 {
3906 sscreen->b.b.is_format_supported = si_is_format_supported;
3907 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3908 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3909 }
3910
3911 static void
3912 si_write_harvested_raster_configs(struct si_context *sctx,
3913 struct si_pm4_state *pm4,
3914 unsigned raster_config,
3915 unsigned raster_config_1)
3916 {
3917 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3918 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3919 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3920 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3921 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3922 unsigned rb_per_se = num_rb / num_se;
3923 unsigned se_mask[4];
3924 unsigned se;
3925
3926 se_mask[0] = ((1 << rb_per_se) - 1);
3927 se_mask[1] = (se_mask[0] << rb_per_se);
3928 se_mask[2] = (se_mask[1] << rb_per_se);
3929 se_mask[3] = (se_mask[2] << rb_per_se);
3930
3931 se_mask[0] &= rb_mask;
3932 se_mask[1] &= rb_mask;
3933 se_mask[2] &= rb_mask;
3934 se_mask[3] &= rb_mask;
3935
3936 assert(num_se == 1 || num_se == 2 || num_se == 4);
3937 assert(sh_per_se == 1 || sh_per_se == 2);
3938 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3939
3940 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3941 * fields are for, so I'm leaving them as their default
3942 * values. */
3943
3944 for (se = 0; se < num_se; se++) {
3945 unsigned raster_config_se = raster_config;
3946 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3947 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3948 int idx = (se / 2) * 2;
3949
3950 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3951 raster_config_se &= C_028350_SE_MAP;
3952
3953 if (!se_mask[idx]) {
3954 raster_config_se |=
3955 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3956 } else {
3957 raster_config_se |=
3958 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3959 }
3960 }
3961
3962 pkr0_mask &= rb_mask;
3963 pkr1_mask &= rb_mask;
3964 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3965 raster_config_se &= C_028350_PKR_MAP;
3966
3967 if (!pkr0_mask) {
3968 raster_config_se |=
3969 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3970 } else {
3971 raster_config_se |=
3972 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3973 }
3974 }
3975
3976 if (rb_per_se >= 2) {
3977 unsigned rb0_mask = 1 << (se * rb_per_se);
3978 unsigned rb1_mask = rb0_mask << 1;
3979
3980 rb0_mask &= rb_mask;
3981 rb1_mask &= rb_mask;
3982 if (!rb0_mask || !rb1_mask) {
3983 raster_config_se &= C_028350_RB_MAP_PKR0;
3984
3985 if (!rb0_mask) {
3986 raster_config_se |=
3987 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3988 } else {
3989 raster_config_se |=
3990 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3991 }
3992 }
3993
3994 if (rb_per_se > 2) {
3995 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3996 rb1_mask = rb0_mask << 1;
3997 rb0_mask &= rb_mask;
3998 rb1_mask &= rb_mask;
3999 if (!rb0_mask || !rb1_mask) {
4000 raster_config_se &= C_028350_RB_MAP_PKR1;
4001
4002 if (!rb0_mask) {
4003 raster_config_se |=
4004 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4005 } else {
4006 raster_config_se |=
4007 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4008 }
4009 }
4010 }
4011 }
4012
4013 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4014 if (sctx->b.chip_class < CIK)
4015 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4016 SE_INDEX(se) | SH_BROADCAST_WRITES |
4017 INSTANCE_BROADCAST_WRITES);
4018 else
4019 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4020 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4021 S_030800_INSTANCE_BROADCAST_WRITES(1));
4022 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4023 }
4024
4025 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4026 if (sctx->b.chip_class < CIK)
4027 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4028 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4029 INSTANCE_BROADCAST_WRITES);
4030 else {
4031 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4032 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4033 S_030800_INSTANCE_BROADCAST_WRITES(1));
4034
4035 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4036 (!se_mask[2] && !se_mask[3]))) {
4037 raster_config_1 &= C_028354_SE_PAIR_MAP;
4038
4039 if (!se_mask[0] && !se_mask[1]) {
4040 raster_config_1 |=
4041 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4042 } else {
4043 raster_config_1 |=
4044 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4045 }
4046 }
4047
4048 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4049 }
4050 }
4051
4052 static void si_init_config(struct si_context *sctx)
4053 {
4054 struct si_screen *sscreen = sctx->screen;
4055 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4056 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4057 unsigned raster_config, raster_config_1;
4058 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4059 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4060
4061 if (!pm4)
4062 return;
4063
4064 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4065 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4066 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4067 si_pm4_cmd_end(pm4, false);
4068
4069 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4070 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4071
4072 /* FIXME calculate these values somehow ??? */
4073 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4074 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4075 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4076
4077 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4078 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4079
4080 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4081 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4082 if (sctx->b.chip_class < CIK)
4083 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4084 S_008A14_CLIP_VTX_REORDER_ENA(1));
4085
4086 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4087 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4088
4089 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4090
4091 switch (sctx->screen->b.family) {
4092 case CHIP_TAHITI:
4093 case CHIP_PITCAIRN:
4094 raster_config = 0x2a00126a;
4095 raster_config_1 = 0x00000000;
4096 break;
4097 case CHIP_VERDE:
4098 raster_config = 0x0000124a;
4099 raster_config_1 = 0x00000000;
4100 break;
4101 case CHIP_OLAND:
4102 raster_config = 0x00000082;
4103 raster_config_1 = 0x00000000;
4104 break;
4105 case CHIP_HAINAN:
4106 raster_config = 0x00000000;
4107 raster_config_1 = 0x00000000;
4108 break;
4109 case CHIP_BONAIRE:
4110 raster_config = 0x16000012;
4111 raster_config_1 = 0x00000000;
4112 break;
4113 case CHIP_HAWAII:
4114 raster_config = 0x3a00161a;
4115 raster_config_1 = 0x0000002e;
4116 break;
4117 case CHIP_FIJI:
4118 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4119 /* old kernels with old tiling config */
4120 raster_config = 0x16000012;
4121 raster_config_1 = 0x0000002a;
4122 } else {
4123 raster_config = 0x3a00161a;
4124 raster_config_1 = 0x0000002e;
4125 }
4126 break;
4127 case CHIP_POLARIS10:
4128 raster_config = 0x16000012;
4129 raster_config_1 = 0x0000002a;
4130 break;
4131 case CHIP_POLARIS11:
4132 case CHIP_POLARIS12:
4133 raster_config = 0x16000012;
4134 raster_config_1 = 0x00000000;
4135 break;
4136 case CHIP_TONGA:
4137 raster_config = 0x16000012;
4138 raster_config_1 = 0x0000002a;
4139 break;
4140 case CHIP_ICELAND:
4141 if (num_rb == 1)
4142 raster_config = 0x00000000;
4143 else
4144 raster_config = 0x00000002;
4145 raster_config_1 = 0x00000000;
4146 break;
4147 case CHIP_CARRIZO:
4148 raster_config = 0x00000002;
4149 raster_config_1 = 0x00000000;
4150 break;
4151 case CHIP_KAVERI:
4152 /* KV should be 0x00000002, but that causes problems with radeon */
4153 raster_config = 0x00000000; /* 0x00000002 */
4154 raster_config_1 = 0x00000000;
4155 break;
4156 case CHIP_KABINI:
4157 case CHIP_MULLINS:
4158 case CHIP_STONEY:
4159 raster_config = 0x00000000;
4160 raster_config_1 = 0x00000000;
4161 break;
4162 default:
4163 if (sctx->b.chip_class <= VI) {
4164 fprintf(stderr,
4165 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4166 raster_config = 0x00000000;
4167 raster_config_1 = 0x00000000;
4168 }
4169 break;
4170 }
4171
4172 if (sctx->b.chip_class <= VI) {
4173 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4174 /* Always use the default config when all backends are enabled
4175 * (or when we failed to determine the enabled backends).
4176 */
4177 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4178 raster_config);
4179 if (sctx->b.chip_class >= CIK)
4180 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4181 raster_config_1);
4182 } else {
4183 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4184 }
4185 }
4186
4187 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4188 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4189 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4190 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4191 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4192 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4193 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4194
4195 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4196 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4197 S_028230_ER_TRI(0xA) |
4198 S_028230_ER_POINT(0xA) |
4199 S_028230_ER_RECT(0xA) |
4200 /* Required by DX10_DIAMOND_TEST_ENA: */
4201 S_028230_ER_LINE_LR(0x1A) |
4202 S_028230_ER_LINE_RL(0x26) |
4203 S_028230_ER_LINE_TB(0xA) |
4204 S_028230_ER_LINE_BT(0xA));
4205 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4206 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4207 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4208 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4209 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4210 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4211 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4212
4213 if (sctx->b.chip_class >= GFX9) {
4214 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4215 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4216 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4217 } else {
4218 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4219 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4220 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4221 }
4222
4223 if (sctx->b.chip_class >= CIK) {
4224 /* If this is 0, Bonaire can hang even if GS isn't being used.
4225 * Other chips are unaffected. These are suboptimal values,
4226 * but we don't use on-chip GS.
4227 */
4228 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4229 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4230 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4231
4232 if (sctx->b.chip_class >= GFX9) {
4233 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4234 } else {
4235 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4236 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4237 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4238 }
4239 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4240
4241 if (sscreen->b.info.num_good_compute_units /
4242 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4243 /* Too few available compute units per SH. Disallowing
4244 * VS to run on CU0 could hurt us more than late VS
4245 * allocation would help.
4246 *
4247 * LATE_ALLOC_VS = 2 is the highest safe number.
4248 */
4249 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4250 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4251 } else {
4252 /* Set LATE_ALLOC_VS == 31. It should be less than
4253 * the number of scratch waves. Limitations:
4254 * - VS can't execute on CU0.
4255 * - If HS writes outputs to LDS, LS can't execute on CU0.
4256 */
4257 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4258 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4259 }
4260
4261 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4262 }
4263
4264 if (sctx->b.chip_class >= VI) {
4265 unsigned vgt_tess_distribution;
4266
4267 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4268 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4269 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4270 if (sctx->b.family < CHIP_POLARIS10)
4271 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4272 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4273
4274 vgt_tess_distribution =
4275 S_028B50_ACCUM_ISOLINE(32) |
4276 S_028B50_ACCUM_TRI(11) |
4277 S_028B50_ACCUM_QUAD(11) |
4278 S_028B50_DONUT_SPLIT(16);
4279
4280 /* Testing with Unigine Heaven extreme tesselation yielded best results
4281 * with TRAP_SPLIT = 3.
4282 */
4283 if (sctx->b.family == CHIP_FIJI ||
4284 sctx->b.family >= CHIP_POLARIS10)
4285 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4286
4287 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4288 } else {
4289 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4290 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4291 }
4292
4293 if (sctx->screen->b.has_rbplus)
4294 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4295
4296 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4297 if (sctx->b.chip_class >= CIK)
4298 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4299 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4300 RADEON_PRIO_BORDER_COLORS);
4301
4302 if (sctx->b.chip_class >= GFX9) {
4303 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
4304 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4305 /* TODO: We can use this to disable RBs for rendering to GART: */
4306 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4307 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4308 /* TODO: Enable the binner: */
4309 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4310 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
4311 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
4312 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4313 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4314 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4315 }
4316
4317 si_pm4_upload_indirect_buffer(sctx, pm4);
4318 sctx->init_config = pm4;
4319 }