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radeonsi: implement line and polygon smoothing
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_pstipple.h"
36
37 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
38 void (*emit)(struct si_context *ctx, struct r600_atom *state),
39 unsigned num_dw)
40 {
41 atom->emit = (void*)emit;
42 atom->num_dw = num_dw;
43 atom->dirty = false;
44 *list_elem = atom;
45 }
46
47 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
48 {
49 if (sscreen->b.chip_class == CIK &&
50 sscreen->b.info.cik_macrotile_mode_array_valid) {
51 unsigned index, tileb;
52
53 tileb = 8 * 8 * tex->surface.bpe;
54 tileb = MIN2(tex->surface.tile_split, tileb);
55
56 for (index = 0; tileb > 64; index++) {
57 tileb >>= 1;
58 }
59 assert(index < 16);
60
61 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
62 }
63
64 if (sscreen->b.chip_class == SI &&
65 sscreen->b.info.si_tile_mode_array_valid) {
66 /* Don't use stencil_tiling_index, because num_banks is always
67 * read from the depth mode. */
68 unsigned tile_mode_index = tex->surface.tiling_index[0];
69 assert(tile_mode_index < 32);
70
71 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
72 }
73
74 /* The old way. */
75 switch (sscreen->b.tiling_info.num_banks) {
76 case 2:
77 return V_02803C_ADDR_SURF_2_BANK;
78 case 4:
79 return V_02803C_ADDR_SURF_4_BANK;
80 case 8:
81 default:
82 return V_02803C_ADDR_SURF_8_BANK;
83 case 16:
84 return V_02803C_ADDR_SURF_16_BANK;
85 }
86 }
87
88 unsigned cik_tile_split(unsigned tile_split)
89 {
90 switch (tile_split) {
91 case 64:
92 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
93 break;
94 case 128:
95 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
96 break;
97 case 256:
98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
99 break;
100 case 512:
101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
102 break;
103 default:
104 case 1024:
105 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
106 break;
107 case 2048:
108 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
109 break;
110 case 4096:
111 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
112 break;
113 }
114 return tile_split;
115 }
116
117 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
118 {
119 switch (macro_tile_aspect) {
120 default:
121 case 1:
122 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
123 break;
124 case 2:
125 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
126 break;
127 case 4:
128 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
129 break;
130 case 8:
131 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
132 break;
133 }
134 return macro_tile_aspect;
135 }
136
137 unsigned cik_bank_wh(unsigned bankwh)
138 {
139 switch (bankwh) {
140 default:
141 case 1:
142 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
143 break;
144 case 2:
145 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
146 break;
147 case 4:
148 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
149 break;
150 case 8:
151 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
152 break;
153 }
154 return bankwh;
155 }
156
157 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
158 {
159 if (sscreen->b.info.si_tile_mode_array_valid) {
160 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
161
162 return G_009910_PIPE_CONFIG(gb_tile_mode);
163 }
164
165 /* This is probably broken for a lot of chips, but it's only used
166 * if the kernel cannot return the tile mode array for CIK. */
167 switch (sscreen->b.info.r600_num_tile_pipes) {
168 case 16:
169 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
170 case 8:
171 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
172 case 4:
173 default:
174 if (sscreen->b.info.r600_num_backends == 4)
175 return V_02803C_X_ADDR_SURF_P4_16X16;
176 else
177 return V_02803C_X_ADDR_SURF_P4_8X16;
178 case 2:
179 return V_02803C_ADDR_SURF_P2;
180 }
181 }
182
183 static unsigned si_map_swizzle(unsigned swizzle)
184 {
185 switch (swizzle) {
186 case UTIL_FORMAT_SWIZZLE_Y:
187 return V_008F0C_SQ_SEL_Y;
188 case UTIL_FORMAT_SWIZZLE_Z:
189 return V_008F0C_SQ_SEL_Z;
190 case UTIL_FORMAT_SWIZZLE_W:
191 return V_008F0C_SQ_SEL_W;
192 case UTIL_FORMAT_SWIZZLE_0:
193 return V_008F0C_SQ_SEL_0;
194 case UTIL_FORMAT_SWIZZLE_1:
195 return V_008F0C_SQ_SEL_1;
196 default: /* UTIL_FORMAT_SWIZZLE_X */
197 return V_008F0C_SQ_SEL_X;
198 }
199 }
200
201 static uint32_t S_FIXED(float value, uint32_t frac_bits)
202 {
203 return value * (1 << frac_bits);
204 }
205
206 /* 12.4 fixed-point */
207 static unsigned si_pack_float_12p4(float x)
208 {
209 return x <= 0 ? 0 :
210 x >= 4096 ? 0xffff : x * 16;
211 }
212
213 /*
214 * Inferred framebuffer and blender state.
215 *
216 * One of the reasons this must be derived from the framebuffer state is that:
217 * - The blend state mask is 0xf most of the time.
218 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
219 * so COLOR1 is enabled pretty much all the time.
220 * So CB_TARGET_MASK is the only register that can disable COLOR1.
221 */
222 static void si_update_fb_blend_state(struct si_context *sctx)
223 {
224 struct si_pm4_state *pm4;
225 struct si_state_blend *blend = sctx->queued.named.blend;
226 uint32_t mask = 0, i;
227
228 if (blend == NULL)
229 return;
230
231 pm4 = CALLOC_STRUCT(si_pm4_state);
232 if (pm4 == NULL)
233 return;
234
235 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
236 if (sctx->framebuffer.state.cbufs[i])
237 mask |= 0xf << (4*i);
238 mask &= blend->cb_target_mask;
239
240 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
241 si_pm4_set_state(sctx, fb_blend, pm4);
242 }
243
244 /*
245 * Blender functions
246 */
247
248 static uint32_t si_translate_blend_function(int blend_func)
249 {
250 switch (blend_func) {
251 case PIPE_BLEND_ADD:
252 return V_028780_COMB_DST_PLUS_SRC;
253 case PIPE_BLEND_SUBTRACT:
254 return V_028780_COMB_SRC_MINUS_DST;
255 case PIPE_BLEND_REVERSE_SUBTRACT:
256 return V_028780_COMB_DST_MINUS_SRC;
257 case PIPE_BLEND_MIN:
258 return V_028780_COMB_MIN_DST_SRC;
259 case PIPE_BLEND_MAX:
260 return V_028780_COMB_MAX_DST_SRC;
261 default:
262 R600_ERR("Unknown blend function %d\n", blend_func);
263 assert(0);
264 break;
265 }
266 return 0;
267 }
268
269 static uint32_t si_translate_blend_factor(int blend_fact)
270 {
271 switch (blend_fact) {
272 case PIPE_BLENDFACTOR_ONE:
273 return V_028780_BLEND_ONE;
274 case PIPE_BLENDFACTOR_SRC_COLOR:
275 return V_028780_BLEND_SRC_COLOR;
276 case PIPE_BLENDFACTOR_SRC_ALPHA:
277 return V_028780_BLEND_SRC_ALPHA;
278 case PIPE_BLENDFACTOR_DST_ALPHA:
279 return V_028780_BLEND_DST_ALPHA;
280 case PIPE_BLENDFACTOR_DST_COLOR:
281 return V_028780_BLEND_DST_COLOR;
282 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
283 return V_028780_BLEND_SRC_ALPHA_SATURATE;
284 case PIPE_BLENDFACTOR_CONST_COLOR:
285 return V_028780_BLEND_CONSTANT_COLOR;
286 case PIPE_BLENDFACTOR_CONST_ALPHA:
287 return V_028780_BLEND_CONSTANT_ALPHA;
288 case PIPE_BLENDFACTOR_ZERO:
289 return V_028780_BLEND_ZERO;
290 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
291 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
292 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
293 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
294 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
295 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
296 case PIPE_BLENDFACTOR_INV_DST_COLOR:
297 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
298 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
299 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
300 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
301 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
302 case PIPE_BLENDFACTOR_SRC1_COLOR:
303 return V_028780_BLEND_SRC1_COLOR;
304 case PIPE_BLENDFACTOR_SRC1_ALPHA:
305 return V_028780_BLEND_SRC1_ALPHA;
306 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
307 return V_028780_BLEND_INV_SRC1_COLOR;
308 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
309 return V_028780_BLEND_INV_SRC1_ALPHA;
310 default:
311 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
312 assert(0);
313 break;
314 }
315 return 0;
316 }
317
318 static void *si_create_blend_state_mode(struct pipe_context *ctx,
319 const struct pipe_blend_state *state,
320 unsigned mode)
321 {
322 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
323 struct si_pm4_state *pm4 = &blend->pm4;
324
325 uint32_t color_control = 0;
326
327 if (blend == NULL)
328 return NULL;
329
330 blend->alpha_to_one = state->alpha_to_one;
331
332 if (state->logicop_enable) {
333 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
334 } else {
335 color_control |= S_028808_ROP3(0xcc);
336 }
337
338 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
339 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
340 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
341 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
342 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
343 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
344
345 blend->cb_target_mask = 0;
346 for (int i = 0; i < 8; i++) {
347 /* state->rt entries > 0 only written if independent blending */
348 const int j = state->independent_blend_enable ? i : 0;
349
350 unsigned eqRGB = state->rt[j].rgb_func;
351 unsigned srcRGB = state->rt[j].rgb_src_factor;
352 unsigned dstRGB = state->rt[j].rgb_dst_factor;
353 unsigned eqA = state->rt[j].alpha_func;
354 unsigned srcA = state->rt[j].alpha_src_factor;
355 unsigned dstA = state->rt[j].alpha_dst_factor;
356
357 unsigned blend_cntl = 0;
358
359 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
360 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
361
362 if (!state->rt[j].blend_enable) {
363 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
364 continue;
365 }
366
367 blend_cntl |= S_028780_ENABLE(1);
368 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
369 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
370 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
371
372 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
373 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
374 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
375 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
376 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
377 }
378 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
379 }
380
381 if (blend->cb_target_mask) {
382 color_control |= S_028808_MODE(mode);
383 } else {
384 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
385 }
386 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
387
388 return blend;
389 }
390
391 static void *si_create_blend_state(struct pipe_context *ctx,
392 const struct pipe_blend_state *state)
393 {
394 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
395 }
396
397 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
398 {
399 struct si_context *sctx = (struct si_context *)ctx;
400 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
401 si_update_fb_blend_state(sctx);
402 }
403
404 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
405 {
406 struct si_context *sctx = (struct si_context *)ctx;
407 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
408 }
409
410 static void si_set_blend_color(struct pipe_context *ctx,
411 const struct pipe_blend_color *state)
412 {
413 struct si_context *sctx = (struct si_context *)ctx;
414 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
415
416 if (pm4 == NULL)
417 return;
418
419 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
420 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
421 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
422 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
423
424 si_pm4_set_state(sctx, blend_color, pm4);
425 }
426
427 /*
428 * Clipping, scissors and viewport
429 */
430
431 static void si_set_clip_state(struct pipe_context *ctx,
432 const struct pipe_clip_state *state)
433 {
434 struct si_context *sctx = (struct si_context *)ctx;
435 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
436 struct pipe_constant_buffer cb;
437
438 if (pm4 == NULL)
439 return;
440
441 for (int i = 0; i < 6; i++) {
442 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
443 fui(state->ucp[i][0]));
444 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
445 fui(state->ucp[i][1]));
446 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
447 fui(state->ucp[i][2]));
448 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
449 fui(state->ucp[i][3]));
450 }
451
452 cb.buffer = NULL;
453 cb.user_buffer = state->ucp;
454 cb.buffer_offset = 0;
455 cb.buffer_size = 4*4*8;
456 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
457 pipe_resource_reference(&cb.buffer, NULL);
458
459 si_pm4_set_state(sctx, clip, pm4);
460 }
461
462 #define SIX_BITS 0x3F
463
464 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
465 {
466 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
467 struct tgsi_shader_info *info = si_get_vs_info(sctx);
468 unsigned window_space =
469 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
470 unsigned clipdist_mask =
471 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
472
473 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
474 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
475 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
476 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
477 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
478 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
479 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
480 info->writes_edgeflag ||
481 info->writes_layer) |
482 (sctx->queued.named.rasterizer->clip_plane_enable &
483 clipdist_mask));
484 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
485 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
486 (clipdist_mask ? 0 :
487 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
488 S_028810_CLIP_DISABLE(window_space));
489 }
490
491 static void si_set_scissor_states(struct pipe_context *ctx,
492 unsigned start_slot,
493 unsigned num_scissors,
494 const struct pipe_scissor_state *state)
495 {
496 struct si_context *sctx = (struct si_context *)ctx;
497 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
498 struct si_pm4_state *pm4 = &scissor->pm4;
499
500 if (scissor == NULL)
501 return;
502
503 scissor->scissor = *state;
504 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
505 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
506 S_028250_WINDOW_OFFSET_DISABLE(1));
507 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
508 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
509
510 si_pm4_set_state(sctx, scissor, scissor);
511 }
512
513 static void si_set_viewport_states(struct pipe_context *ctx,
514 unsigned start_slot,
515 unsigned num_viewports,
516 const struct pipe_viewport_state *state)
517 {
518 struct si_context *sctx = (struct si_context *)ctx;
519 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
520 struct si_pm4_state *pm4 = &viewport->pm4;
521
522 if (viewport == NULL)
523 return;
524
525 viewport->viewport = *state;
526 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
527 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
528 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
529 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
530 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
531 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
532
533 si_pm4_set_state(sctx, viewport, viewport);
534 }
535
536 /*
537 * inferred state between framebuffer and rasterizer
538 */
539 static void si_update_fb_rs_state(struct si_context *sctx)
540 {
541 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
542 struct si_pm4_state *pm4;
543 float offset_units;
544
545 if (!rs || !sctx->framebuffer.state.zsbuf)
546 return;
547
548 offset_units = sctx->queued.named.rasterizer->offset_units;
549 switch (sctx->framebuffer.state.zsbuf->texture->format) {
550 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
551 case PIPE_FORMAT_X8Z24_UNORM:
552 case PIPE_FORMAT_Z24X8_UNORM:
553 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
554 offset_units *= 2.0f;
555 break;
556 case PIPE_FORMAT_Z32_FLOAT:
557 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
558 offset_units *= 1.0f;
559 break;
560 case PIPE_FORMAT_Z16_UNORM:
561 offset_units *= 4.0f;
562 break;
563 default:
564 return;
565 }
566
567 pm4 = CALLOC_STRUCT(si_pm4_state);
568
569 if (pm4 == NULL)
570 return;
571
572 /* FIXME some of those reg can be computed with cso */
573 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
574 fui(sctx->queued.named.rasterizer->offset_scale));
575 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
576 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
577 fui(sctx->queued.named.rasterizer->offset_scale));
578 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
579
580 si_pm4_set_state(sctx, fb_rs, pm4);
581 }
582
583 /*
584 * Rasterizer
585 */
586
587 static uint32_t si_translate_fill(uint32_t func)
588 {
589 switch(func) {
590 case PIPE_POLYGON_MODE_FILL:
591 return V_028814_X_DRAW_TRIANGLES;
592 case PIPE_POLYGON_MODE_LINE:
593 return V_028814_X_DRAW_LINES;
594 case PIPE_POLYGON_MODE_POINT:
595 return V_028814_X_DRAW_POINTS;
596 default:
597 assert(0);
598 return V_028814_X_DRAW_POINTS;
599 }
600 }
601
602 static void *si_create_rs_state(struct pipe_context *ctx,
603 const struct pipe_rasterizer_state *state)
604 {
605 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
606 struct si_pm4_state *pm4 = &rs->pm4;
607 unsigned tmp;
608 unsigned prov_vtx = 1, polygon_dual_mode;
609 float psize_min, psize_max;
610
611 if (rs == NULL) {
612 return NULL;
613 }
614
615 rs->two_side = state->light_twoside;
616 rs->multisample_enable = state->multisample;
617 rs->clip_plane_enable = state->clip_plane_enable;
618 rs->line_stipple_enable = state->line_stipple_enable;
619 rs->poly_stipple_enable = state->poly_stipple_enable;
620 rs->line_smooth = state->line_smooth;
621 rs->poly_smooth = state->poly_smooth;
622
623 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
624 state->fill_back != PIPE_POLYGON_MODE_FILL);
625
626 if (state->flatshade_first)
627 prov_vtx = 0;
628
629 rs->flatshade = state->flatshade;
630 rs->sprite_coord_enable = state->sprite_coord_enable;
631 rs->pa_sc_line_stipple = state->line_stipple_enable ?
632 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
633 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
634 rs->pa_su_sc_mode_cntl =
635 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
636 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
637 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
638 S_028814_FACE(!state->front_ccw) |
639 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
640 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
641 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
642 S_028814_POLY_MODE(polygon_dual_mode) |
643 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
644 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
645 rs->pa_cl_clip_cntl =
646 S_028810_PS_UCP_MODE(3) |
647 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
648 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
649 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
650 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
651 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
652
653 /* offset */
654 rs->offset_units = state->offset_units;
655 rs->offset_scale = state->offset_scale * 12.0f;
656
657 tmp = S_0286D4_FLAT_SHADE_ENA(1);
658 if (state->sprite_coord_enable) {
659 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
660 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
661 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
662 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
663 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
664 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
665 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
666 }
667 }
668 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
669
670 /* point size 12.4 fixed point */
671 tmp = (unsigned)(state->point_size * 8.0);
672 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
673
674 if (state->point_size_per_vertex) {
675 psize_min = util_get_min_point_size(state);
676 psize_max = 8192;
677 } else {
678 /* Force the point size to be as if the vertex output was disabled. */
679 psize_min = state->point_size;
680 psize_max = state->point_size;
681 }
682 /* Divide by two, because 0.5 = 1 pixel. */
683 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
684 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
685 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
686
687 tmp = (unsigned)state->line_width * 8;
688 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
689 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
690 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
691 S_028A48_MSAA_ENABLE(state->multisample ||
692 state->poly_smooth ||
693 state->line_smooth) |
694 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
695
696 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
697 S_028BE4_PIX_CENTER(state->half_pixel_center) |
698 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
699
700 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
701
702 return rs;
703 }
704
705 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
706 {
707 struct si_context *sctx = (struct si_context *)ctx;
708 struct si_state_rasterizer *old_rs =
709 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
710 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
711
712 if (state == NULL)
713 return;
714
715 // TODO
716 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
717 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
718
719 if (sctx->framebuffer.nr_samples > 1 &&
720 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
721 sctx->db_render_state.dirty = true;
722
723 si_pm4_bind_state(sctx, rasterizer, rs);
724 si_update_fb_rs_state(sctx);
725
726 sctx->clip_regs.dirty = true;
727 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
728 }
729
730 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
731 {
732 struct si_context *sctx = (struct si_context *)ctx;
733 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
734 }
735
736 /*
737 * infeered state between dsa and stencil ref
738 */
739 static void si_update_dsa_stencil_ref(struct si_context *sctx)
740 {
741 struct si_pm4_state *pm4;
742 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
743 struct si_state_dsa *dsa = sctx->queued.named.dsa;
744
745 if (!dsa)
746 return;
747
748 pm4 = CALLOC_STRUCT(si_pm4_state);
749 if (pm4 == NULL)
750 return;
751
752 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
753 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
754 S_028430_STENCILMASK(dsa->valuemask[0]) |
755 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
756 S_028430_STENCILOPVAL(1));
757 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
758 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
759 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
760 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
761 S_028434_STENCILOPVAL_BF(1));
762
763 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
764 }
765
766 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
767 const struct pipe_stencil_ref *state)
768 {
769 struct si_context *sctx = (struct si_context *)ctx;
770 sctx->stencil_ref = *state;
771 si_update_dsa_stencil_ref(sctx);
772 }
773
774
775 /*
776 * DSA
777 */
778
779 static uint32_t si_translate_stencil_op(int s_op)
780 {
781 switch (s_op) {
782 case PIPE_STENCIL_OP_KEEP:
783 return V_02842C_STENCIL_KEEP;
784 case PIPE_STENCIL_OP_ZERO:
785 return V_02842C_STENCIL_ZERO;
786 case PIPE_STENCIL_OP_REPLACE:
787 return V_02842C_STENCIL_REPLACE_TEST;
788 case PIPE_STENCIL_OP_INCR:
789 return V_02842C_STENCIL_ADD_CLAMP;
790 case PIPE_STENCIL_OP_DECR:
791 return V_02842C_STENCIL_SUB_CLAMP;
792 case PIPE_STENCIL_OP_INCR_WRAP:
793 return V_02842C_STENCIL_ADD_WRAP;
794 case PIPE_STENCIL_OP_DECR_WRAP:
795 return V_02842C_STENCIL_SUB_WRAP;
796 case PIPE_STENCIL_OP_INVERT:
797 return V_02842C_STENCIL_INVERT;
798 default:
799 R600_ERR("Unknown stencil op %d", s_op);
800 assert(0);
801 break;
802 }
803 return 0;
804 }
805
806 static void *si_create_dsa_state(struct pipe_context *ctx,
807 const struct pipe_depth_stencil_alpha_state *state)
808 {
809 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
810 struct si_pm4_state *pm4 = &dsa->pm4;
811 unsigned db_depth_control;
812 uint32_t db_stencil_control = 0;
813
814 if (dsa == NULL) {
815 return NULL;
816 }
817
818 dsa->valuemask[0] = state->stencil[0].valuemask;
819 dsa->valuemask[1] = state->stencil[1].valuemask;
820 dsa->writemask[0] = state->stencil[0].writemask;
821 dsa->writemask[1] = state->stencil[1].writemask;
822
823 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
824 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
825 S_028800_ZFUNC(state->depth.func);
826
827 /* stencil */
828 if (state->stencil[0].enabled) {
829 db_depth_control |= S_028800_STENCIL_ENABLE(1);
830 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
831 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
832 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
833 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
834
835 if (state->stencil[1].enabled) {
836 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
837 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
838 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
839 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
840 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
841 }
842 }
843
844 /* alpha */
845 if (state->alpha.enabled) {
846 dsa->alpha_func = state->alpha.func;
847
848 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
849 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
850 } else {
851 dsa->alpha_func = PIPE_FUNC_ALWAYS;
852 }
853
854 /* misc */
855 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
856 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
857
858 return dsa;
859 }
860
861 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
862 {
863 struct si_context *sctx = (struct si_context *)ctx;
864 struct si_state_dsa *dsa = state;
865
866 if (state == NULL)
867 return;
868
869 si_pm4_bind_state(sctx, dsa, dsa);
870 si_update_dsa_stencil_ref(sctx);
871 }
872
873 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
874 {
875 struct si_context *sctx = (struct si_context *)ctx;
876 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
877 }
878
879 static void *si_create_db_flush_dsa(struct si_context *sctx)
880 {
881 struct pipe_depth_stencil_alpha_state dsa = {};
882
883 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
884 }
885
886 /* DB RENDER STATE */
887
888 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
889 {
890 struct si_context *sctx = (struct si_context*)ctx;
891
892 sctx->db_render_state.dirty = true;
893 }
894
895 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
896 {
897 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
898 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
899 unsigned db_shader_control;
900
901 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
902
903 /* DB_RENDER_CONTROL */
904 if (sctx->dbcb_depth_copy_enabled ||
905 sctx->dbcb_stencil_copy_enabled) {
906 radeon_emit(cs,
907 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
908 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
909 S_028000_COPY_CENTROID(1) |
910 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
911 } else if (sctx->db_inplace_flush_enabled) {
912 radeon_emit(cs,
913 S_028000_DEPTH_COMPRESS_DISABLE(1) |
914 S_028000_STENCIL_COMPRESS_DISABLE(1));
915 } else if (sctx->db_depth_clear) {
916 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
917 } else {
918 radeon_emit(cs, 0);
919 }
920
921 /* DB_COUNT_CONTROL (occlusion queries) */
922 if (sctx->b.num_occlusion_queries > 0) {
923 if (sctx->b.chip_class >= CIK) {
924 radeon_emit(cs,
925 S_028004_PERFECT_ZPASS_COUNTS(1) |
926 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
927 S_028004_ZPASS_ENABLE(1) |
928 S_028004_SLICE_EVEN_ENABLE(1) |
929 S_028004_SLICE_ODD_ENABLE(1));
930 } else {
931 radeon_emit(cs,
932 S_028004_PERFECT_ZPASS_COUNTS(1) |
933 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
934 }
935 } else {
936 /* Disable occlusion queries. */
937 if (sctx->b.chip_class >= CIK) {
938 radeon_emit(cs, 0);
939 } else {
940 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
941 }
942 }
943
944 /* DB_RENDER_OVERRIDE2 */
945 if (sctx->db_depth_disable_expclear) {
946 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
947 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
948 } else {
949 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
950 }
951
952 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
953 sctx->ps_db_shader_control;
954
955 /* Bug workaround for smoothing (overrasterization) on SI. */
956 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
957 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
958 else
959 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
960
961 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
962 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
963 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
964
965 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
966 db_shader_control);
967 }
968
969 /*
970 * format translation
971 */
972 static uint32_t si_translate_colorformat(enum pipe_format format)
973 {
974 const struct util_format_description *desc = util_format_description(format);
975
976 #define HAS_SIZE(x,y,z,w) \
977 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
978 desc->channel[2].size == (z) && desc->channel[3].size == (w))
979
980 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
981 return V_028C70_COLOR_10_11_11;
982
983 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
984 return V_028C70_COLOR_INVALID;
985
986 switch (desc->nr_channels) {
987 case 1:
988 switch (desc->channel[0].size) {
989 case 8:
990 return V_028C70_COLOR_8;
991 case 16:
992 return V_028C70_COLOR_16;
993 case 32:
994 return V_028C70_COLOR_32;
995 }
996 break;
997 case 2:
998 if (desc->channel[0].size == desc->channel[1].size) {
999 switch (desc->channel[0].size) {
1000 case 8:
1001 return V_028C70_COLOR_8_8;
1002 case 16:
1003 return V_028C70_COLOR_16_16;
1004 case 32:
1005 return V_028C70_COLOR_32_32;
1006 }
1007 } else if (HAS_SIZE(8,24,0,0)) {
1008 return V_028C70_COLOR_24_8;
1009 } else if (HAS_SIZE(24,8,0,0)) {
1010 return V_028C70_COLOR_8_24;
1011 }
1012 break;
1013 case 3:
1014 if (HAS_SIZE(5,6,5,0)) {
1015 return V_028C70_COLOR_5_6_5;
1016 } else if (HAS_SIZE(32,8,24,0)) {
1017 return V_028C70_COLOR_X24_8_32_FLOAT;
1018 }
1019 break;
1020 case 4:
1021 if (desc->channel[0].size == desc->channel[1].size &&
1022 desc->channel[0].size == desc->channel[2].size &&
1023 desc->channel[0].size == desc->channel[3].size) {
1024 switch (desc->channel[0].size) {
1025 case 4:
1026 return V_028C70_COLOR_4_4_4_4;
1027 case 8:
1028 return V_028C70_COLOR_8_8_8_8;
1029 case 16:
1030 return V_028C70_COLOR_16_16_16_16;
1031 case 32:
1032 return V_028C70_COLOR_32_32_32_32;
1033 }
1034 } else if (HAS_SIZE(5,5,5,1)) {
1035 return V_028C70_COLOR_1_5_5_5;
1036 } else if (HAS_SIZE(10,10,10,2)) {
1037 return V_028C70_COLOR_2_10_10_10;
1038 }
1039 break;
1040 }
1041 return V_028C70_COLOR_INVALID;
1042 }
1043
1044 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1045 {
1046 if (SI_BIG_ENDIAN) {
1047 switch(colorformat) {
1048 /* 8-bit buffers. */
1049 case V_028C70_COLOR_8:
1050 return V_028C70_ENDIAN_NONE;
1051
1052 /* 16-bit buffers. */
1053 case V_028C70_COLOR_5_6_5:
1054 case V_028C70_COLOR_1_5_5_5:
1055 case V_028C70_COLOR_4_4_4_4:
1056 case V_028C70_COLOR_16:
1057 case V_028C70_COLOR_8_8:
1058 return V_028C70_ENDIAN_8IN16;
1059
1060 /* 32-bit buffers. */
1061 case V_028C70_COLOR_8_8_8_8:
1062 case V_028C70_COLOR_2_10_10_10:
1063 case V_028C70_COLOR_8_24:
1064 case V_028C70_COLOR_24_8:
1065 case V_028C70_COLOR_16_16:
1066 return V_028C70_ENDIAN_8IN32;
1067
1068 /* 64-bit buffers. */
1069 case V_028C70_COLOR_16_16_16_16:
1070 return V_028C70_ENDIAN_8IN16;
1071
1072 case V_028C70_COLOR_32_32:
1073 return V_028C70_ENDIAN_8IN32;
1074
1075 /* 128-bit buffers. */
1076 case V_028C70_COLOR_32_32_32_32:
1077 return V_028C70_ENDIAN_8IN32;
1078 default:
1079 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1080 }
1081 } else {
1082 return V_028C70_ENDIAN_NONE;
1083 }
1084 }
1085
1086 /* Returns the size in bits of the widest component of a CB format */
1087 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1088 {
1089 switch(colorformat) {
1090 case V_028C70_COLOR_4_4_4_4:
1091 return 4;
1092
1093 case V_028C70_COLOR_1_5_5_5:
1094 case V_028C70_COLOR_5_5_5_1:
1095 return 5;
1096
1097 case V_028C70_COLOR_5_6_5:
1098 return 6;
1099
1100 case V_028C70_COLOR_8:
1101 case V_028C70_COLOR_8_8:
1102 case V_028C70_COLOR_8_8_8_8:
1103 return 8;
1104
1105 case V_028C70_COLOR_10_10_10_2:
1106 case V_028C70_COLOR_2_10_10_10:
1107 return 10;
1108
1109 case V_028C70_COLOR_10_11_11:
1110 case V_028C70_COLOR_11_11_10:
1111 return 11;
1112
1113 case V_028C70_COLOR_16:
1114 case V_028C70_COLOR_16_16:
1115 case V_028C70_COLOR_16_16_16_16:
1116 return 16;
1117
1118 case V_028C70_COLOR_8_24:
1119 case V_028C70_COLOR_24_8:
1120 return 24;
1121
1122 case V_028C70_COLOR_32:
1123 case V_028C70_COLOR_32_32:
1124 case V_028C70_COLOR_32_32_32_32:
1125 case V_028C70_COLOR_X24_8_32_FLOAT:
1126 return 32;
1127 }
1128
1129 assert(!"Unknown maximum component size");
1130 return 0;
1131 }
1132
1133 static uint32_t si_translate_dbformat(enum pipe_format format)
1134 {
1135 switch (format) {
1136 case PIPE_FORMAT_Z16_UNORM:
1137 return V_028040_Z_16;
1138 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1139 case PIPE_FORMAT_X8Z24_UNORM:
1140 case PIPE_FORMAT_Z24X8_UNORM:
1141 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1142 return V_028040_Z_24; /* deprecated on SI */
1143 case PIPE_FORMAT_Z32_FLOAT:
1144 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1145 return V_028040_Z_32_FLOAT;
1146 default:
1147 return V_028040_Z_INVALID;
1148 }
1149 }
1150
1151 /*
1152 * Texture translation
1153 */
1154
1155 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1156 enum pipe_format format,
1157 const struct util_format_description *desc,
1158 int first_non_void)
1159 {
1160 struct si_screen *sscreen = (struct si_screen*)screen;
1161 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1162 boolean uniform = TRUE;
1163 int i;
1164
1165 /* Colorspace (return non-RGB formats directly). */
1166 switch (desc->colorspace) {
1167 /* Depth stencil formats */
1168 case UTIL_FORMAT_COLORSPACE_ZS:
1169 switch (format) {
1170 case PIPE_FORMAT_Z16_UNORM:
1171 return V_008F14_IMG_DATA_FORMAT_16;
1172 case PIPE_FORMAT_X24S8_UINT:
1173 case PIPE_FORMAT_Z24X8_UNORM:
1174 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1175 return V_008F14_IMG_DATA_FORMAT_8_24;
1176 case PIPE_FORMAT_X8Z24_UNORM:
1177 case PIPE_FORMAT_S8X24_UINT:
1178 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1179 return V_008F14_IMG_DATA_FORMAT_24_8;
1180 case PIPE_FORMAT_S8_UINT:
1181 return V_008F14_IMG_DATA_FORMAT_8;
1182 case PIPE_FORMAT_Z32_FLOAT:
1183 return V_008F14_IMG_DATA_FORMAT_32;
1184 case PIPE_FORMAT_X32_S8X24_UINT:
1185 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1186 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1187 default:
1188 goto out_unknown;
1189 }
1190
1191 case UTIL_FORMAT_COLORSPACE_YUV:
1192 goto out_unknown; /* TODO */
1193
1194 case UTIL_FORMAT_COLORSPACE_SRGB:
1195 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1196 goto out_unknown;
1197 break;
1198
1199 default:
1200 break;
1201 }
1202
1203 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1204 if (!enable_s3tc)
1205 goto out_unknown;
1206
1207 switch (format) {
1208 case PIPE_FORMAT_RGTC1_SNORM:
1209 case PIPE_FORMAT_LATC1_SNORM:
1210 case PIPE_FORMAT_RGTC1_UNORM:
1211 case PIPE_FORMAT_LATC1_UNORM:
1212 return V_008F14_IMG_DATA_FORMAT_BC4;
1213 case PIPE_FORMAT_RGTC2_SNORM:
1214 case PIPE_FORMAT_LATC2_SNORM:
1215 case PIPE_FORMAT_RGTC2_UNORM:
1216 case PIPE_FORMAT_LATC2_UNORM:
1217 return V_008F14_IMG_DATA_FORMAT_BC5;
1218 default:
1219 goto out_unknown;
1220 }
1221 }
1222
1223 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1224 if (!enable_s3tc)
1225 goto out_unknown;
1226
1227 switch (format) {
1228 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1229 case PIPE_FORMAT_BPTC_SRGBA:
1230 return V_008F14_IMG_DATA_FORMAT_BC7;
1231 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1232 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1233 return V_008F14_IMG_DATA_FORMAT_BC6;
1234 default:
1235 goto out_unknown;
1236 }
1237 }
1238
1239 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1240 switch (format) {
1241 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1242 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1243 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1244 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1245 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1246 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1247 default:
1248 goto out_unknown;
1249 }
1250 }
1251
1252 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1253
1254 if (!enable_s3tc)
1255 goto out_unknown;
1256
1257 if (!util_format_s3tc_enabled) {
1258 goto out_unknown;
1259 }
1260
1261 switch (format) {
1262 case PIPE_FORMAT_DXT1_RGB:
1263 case PIPE_FORMAT_DXT1_RGBA:
1264 case PIPE_FORMAT_DXT1_SRGB:
1265 case PIPE_FORMAT_DXT1_SRGBA:
1266 return V_008F14_IMG_DATA_FORMAT_BC1;
1267 case PIPE_FORMAT_DXT3_RGBA:
1268 case PIPE_FORMAT_DXT3_SRGBA:
1269 return V_008F14_IMG_DATA_FORMAT_BC2;
1270 case PIPE_FORMAT_DXT5_RGBA:
1271 case PIPE_FORMAT_DXT5_SRGBA:
1272 return V_008F14_IMG_DATA_FORMAT_BC3;
1273 default:
1274 goto out_unknown;
1275 }
1276 }
1277
1278 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1279 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1280 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1281 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1282 }
1283
1284 /* R8G8Bx_SNORM - TODO CxV8U8 */
1285
1286 /* See whether the components are of the same size. */
1287 for (i = 1; i < desc->nr_channels; i++) {
1288 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1289 }
1290
1291 /* Non-uniform formats. */
1292 if (!uniform) {
1293 switch(desc->nr_channels) {
1294 case 3:
1295 if (desc->channel[0].size == 5 &&
1296 desc->channel[1].size == 6 &&
1297 desc->channel[2].size == 5) {
1298 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1299 }
1300 goto out_unknown;
1301 case 4:
1302 if (desc->channel[0].size == 5 &&
1303 desc->channel[1].size == 5 &&
1304 desc->channel[2].size == 5 &&
1305 desc->channel[3].size == 1) {
1306 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1307 }
1308 if (desc->channel[0].size == 10 &&
1309 desc->channel[1].size == 10 &&
1310 desc->channel[2].size == 10 &&
1311 desc->channel[3].size == 2) {
1312 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1313 }
1314 goto out_unknown;
1315 }
1316 goto out_unknown;
1317 }
1318
1319 if (first_non_void < 0 || first_non_void > 3)
1320 goto out_unknown;
1321
1322 /* uniform formats */
1323 switch (desc->channel[first_non_void].size) {
1324 case 4:
1325 switch (desc->nr_channels) {
1326 #if 0 /* Not supported for render targets */
1327 case 2:
1328 return V_008F14_IMG_DATA_FORMAT_4_4;
1329 #endif
1330 case 4:
1331 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1332 }
1333 break;
1334 case 8:
1335 switch (desc->nr_channels) {
1336 case 1:
1337 return V_008F14_IMG_DATA_FORMAT_8;
1338 case 2:
1339 return V_008F14_IMG_DATA_FORMAT_8_8;
1340 case 4:
1341 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1342 }
1343 break;
1344 case 16:
1345 switch (desc->nr_channels) {
1346 case 1:
1347 return V_008F14_IMG_DATA_FORMAT_16;
1348 case 2:
1349 return V_008F14_IMG_DATA_FORMAT_16_16;
1350 case 4:
1351 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1352 }
1353 break;
1354 case 32:
1355 switch (desc->nr_channels) {
1356 case 1:
1357 return V_008F14_IMG_DATA_FORMAT_32;
1358 case 2:
1359 return V_008F14_IMG_DATA_FORMAT_32_32;
1360 #if 0 /* Not supported for render targets */
1361 case 3:
1362 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1363 #endif
1364 case 4:
1365 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1366 }
1367 }
1368
1369 out_unknown:
1370 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1371 return ~0;
1372 }
1373
1374 static unsigned si_tex_wrap(unsigned wrap)
1375 {
1376 switch (wrap) {
1377 default:
1378 case PIPE_TEX_WRAP_REPEAT:
1379 return V_008F30_SQ_TEX_WRAP;
1380 case PIPE_TEX_WRAP_CLAMP:
1381 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1382 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1383 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1384 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1385 return V_008F30_SQ_TEX_CLAMP_BORDER;
1386 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1387 return V_008F30_SQ_TEX_MIRROR;
1388 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1389 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1390 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1391 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1392 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1393 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1394 }
1395 }
1396
1397 static unsigned si_tex_filter(unsigned filter)
1398 {
1399 switch (filter) {
1400 default:
1401 case PIPE_TEX_FILTER_NEAREST:
1402 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1403 case PIPE_TEX_FILTER_LINEAR:
1404 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1405 }
1406 }
1407
1408 static unsigned si_tex_mipfilter(unsigned filter)
1409 {
1410 switch (filter) {
1411 case PIPE_TEX_MIPFILTER_NEAREST:
1412 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1413 case PIPE_TEX_MIPFILTER_LINEAR:
1414 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1415 default:
1416 case PIPE_TEX_MIPFILTER_NONE:
1417 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1418 }
1419 }
1420
1421 static unsigned si_tex_compare(unsigned compare)
1422 {
1423 switch (compare) {
1424 default:
1425 case PIPE_FUNC_NEVER:
1426 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1427 case PIPE_FUNC_LESS:
1428 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1429 case PIPE_FUNC_EQUAL:
1430 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1431 case PIPE_FUNC_LEQUAL:
1432 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1433 case PIPE_FUNC_GREATER:
1434 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1435 case PIPE_FUNC_NOTEQUAL:
1436 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1437 case PIPE_FUNC_GEQUAL:
1438 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1439 case PIPE_FUNC_ALWAYS:
1440 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1441 }
1442 }
1443
1444 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1445 {
1446 switch (dim) {
1447 default:
1448 case PIPE_TEXTURE_1D:
1449 return V_008F1C_SQ_RSRC_IMG_1D;
1450 case PIPE_TEXTURE_1D_ARRAY:
1451 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1452 case PIPE_TEXTURE_2D:
1453 case PIPE_TEXTURE_RECT:
1454 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1455 V_008F1C_SQ_RSRC_IMG_2D;
1456 case PIPE_TEXTURE_2D_ARRAY:
1457 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1458 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1459 case PIPE_TEXTURE_3D:
1460 return V_008F1C_SQ_RSRC_IMG_3D;
1461 case PIPE_TEXTURE_CUBE:
1462 case PIPE_TEXTURE_CUBE_ARRAY:
1463 return V_008F1C_SQ_RSRC_IMG_CUBE;
1464 }
1465 }
1466
1467 /*
1468 * Format support testing
1469 */
1470
1471 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1472 {
1473 return si_translate_texformat(screen, format, util_format_description(format),
1474 util_format_get_first_non_void_channel(format)) != ~0U;
1475 }
1476
1477 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1478 const struct util_format_description *desc,
1479 int first_non_void)
1480 {
1481 unsigned type = desc->channel[first_non_void].type;
1482 int i;
1483
1484 if (type == UTIL_FORMAT_TYPE_FIXED)
1485 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1486
1487 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1488 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1489
1490 if (desc->nr_channels == 4 &&
1491 desc->channel[0].size == 10 &&
1492 desc->channel[1].size == 10 &&
1493 desc->channel[2].size == 10 &&
1494 desc->channel[3].size == 2)
1495 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1496
1497 /* See whether the components are of the same size. */
1498 for (i = 0; i < desc->nr_channels; i++) {
1499 if (desc->channel[first_non_void].size != desc->channel[i].size)
1500 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1501 }
1502
1503 switch (desc->channel[first_non_void].size) {
1504 case 8:
1505 switch (desc->nr_channels) {
1506 case 1:
1507 return V_008F0C_BUF_DATA_FORMAT_8;
1508 case 2:
1509 return V_008F0C_BUF_DATA_FORMAT_8_8;
1510 case 3:
1511 case 4:
1512 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1513 }
1514 break;
1515 case 16:
1516 switch (desc->nr_channels) {
1517 case 1:
1518 return V_008F0C_BUF_DATA_FORMAT_16;
1519 case 2:
1520 return V_008F0C_BUF_DATA_FORMAT_16_16;
1521 case 3:
1522 case 4:
1523 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1524 }
1525 break;
1526 case 32:
1527 /* From the Southern Islands ISA documentation about MTBUF:
1528 * 'Memory reads of data in memory that is 32 or 64 bits do not
1529 * undergo any format conversion.'
1530 */
1531 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1532 !desc->channel[first_non_void].pure_integer)
1533 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1534
1535 switch (desc->nr_channels) {
1536 case 1:
1537 return V_008F0C_BUF_DATA_FORMAT_32;
1538 case 2:
1539 return V_008F0C_BUF_DATA_FORMAT_32_32;
1540 case 3:
1541 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1542 case 4:
1543 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1544 }
1545 break;
1546 }
1547
1548 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1549 }
1550
1551 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1552 const struct util_format_description *desc,
1553 int first_non_void)
1554 {
1555 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1556 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1557
1558 switch (desc->channel[first_non_void].type) {
1559 case UTIL_FORMAT_TYPE_SIGNED:
1560 if (desc->channel[first_non_void].normalized)
1561 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1562 else if (desc->channel[first_non_void].pure_integer)
1563 return V_008F0C_BUF_NUM_FORMAT_SINT;
1564 else
1565 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1566 break;
1567 case UTIL_FORMAT_TYPE_UNSIGNED:
1568 if (desc->channel[first_non_void].normalized)
1569 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1570 else if (desc->channel[first_non_void].pure_integer)
1571 return V_008F0C_BUF_NUM_FORMAT_UINT;
1572 else
1573 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1574 break;
1575 case UTIL_FORMAT_TYPE_FLOAT:
1576 default:
1577 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1578 }
1579 }
1580
1581 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1582 {
1583 const struct util_format_description *desc;
1584 int first_non_void;
1585 unsigned data_format;
1586
1587 desc = util_format_description(format);
1588 first_non_void = util_format_get_first_non_void_channel(format);
1589 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1590 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1591 }
1592
1593 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1594 {
1595 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1596 r600_translate_colorswap(format) != ~0U;
1597 }
1598
1599 static bool si_is_zs_format_supported(enum pipe_format format)
1600 {
1601 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1602 }
1603
1604 boolean si_is_format_supported(struct pipe_screen *screen,
1605 enum pipe_format format,
1606 enum pipe_texture_target target,
1607 unsigned sample_count,
1608 unsigned usage)
1609 {
1610 struct si_screen *sscreen = (struct si_screen *)screen;
1611 unsigned retval = 0;
1612
1613 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1614 R600_ERR("r600: unsupported texture type %d\n", target);
1615 return FALSE;
1616 }
1617
1618 if (!util_format_is_supported(format, usage))
1619 return FALSE;
1620
1621 if (sample_count > 1) {
1622 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1623 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1624 return FALSE;
1625
1626 switch (sample_count) {
1627 case 2:
1628 case 4:
1629 case 8:
1630 break;
1631 default:
1632 return FALSE;
1633 }
1634 }
1635
1636 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1637 if (target == PIPE_BUFFER) {
1638 if (si_is_vertex_format_supported(screen, format))
1639 retval |= PIPE_BIND_SAMPLER_VIEW;
1640 } else {
1641 if (si_is_sampler_format_supported(screen, format))
1642 retval |= PIPE_BIND_SAMPLER_VIEW;
1643 }
1644 }
1645
1646 if ((usage & (PIPE_BIND_RENDER_TARGET |
1647 PIPE_BIND_DISPLAY_TARGET |
1648 PIPE_BIND_SCANOUT |
1649 PIPE_BIND_SHARED |
1650 PIPE_BIND_BLENDABLE)) &&
1651 si_is_colorbuffer_format_supported(format)) {
1652 retval |= usage &
1653 (PIPE_BIND_RENDER_TARGET |
1654 PIPE_BIND_DISPLAY_TARGET |
1655 PIPE_BIND_SCANOUT |
1656 PIPE_BIND_SHARED);
1657 if (!util_format_is_pure_integer(format) &&
1658 !util_format_is_depth_or_stencil(format))
1659 retval |= usage & PIPE_BIND_BLENDABLE;
1660 }
1661
1662 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1663 si_is_zs_format_supported(format)) {
1664 retval |= PIPE_BIND_DEPTH_STENCIL;
1665 }
1666
1667 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1668 si_is_vertex_format_supported(screen, format)) {
1669 retval |= PIPE_BIND_VERTEX_BUFFER;
1670 }
1671
1672 if (usage & PIPE_BIND_TRANSFER_READ)
1673 retval |= PIPE_BIND_TRANSFER_READ;
1674 if (usage & PIPE_BIND_TRANSFER_WRITE)
1675 retval |= PIPE_BIND_TRANSFER_WRITE;
1676
1677 return retval == usage;
1678 }
1679
1680 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1681 {
1682 unsigned tile_mode_index = 0;
1683
1684 if (stencil) {
1685 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1686 } else {
1687 tile_mode_index = rtex->surface.tiling_index[level];
1688 }
1689 return tile_mode_index;
1690 }
1691
1692 /*
1693 * framebuffer handling
1694 */
1695
1696 static void si_initialize_color_surface(struct si_context *sctx,
1697 struct r600_surface *surf)
1698 {
1699 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1700 unsigned level = surf->base.u.tex.level;
1701 uint64_t offset = rtex->surface.level[level].offset;
1702 unsigned pitch, slice;
1703 unsigned color_info, color_attrib, color_pitch, color_view;
1704 unsigned tile_mode_index;
1705 unsigned format, swap, ntype, endian;
1706 const struct util_format_description *desc;
1707 int i;
1708 unsigned blend_clamp = 0, blend_bypass = 0;
1709 unsigned max_comp_size;
1710
1711 /* Layered rendering doesn't work with LINEAR_GENERAL.
1712 * (LINEAR_ALIGNED and others work) */
1713 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1714 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1715 offset += rtex->surface.level[level].slice_size *
1716 surf->base.u.tex.first_layer;
1717 color_view = 0;
1718 } else {
1719 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1720 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1721 }
1722
1723 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1724 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1725 if (slice) {
1726 slice = slice - 1;
1727 }
1728
1729 tile_mode_index = si_tile_mode_index(rtex, level, false);
1730
1731 desc = util_format_description(surf->base.format);
1732 for (i = 0; i < 4; i++) {
1733 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1734 break;
1735 }
1736 }
1737 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1738 ntype = V_028C70_NUMBER_FLOAT;
1739 } else {
1740 ntype = V_028C70_NUMBER_UNORM;
1741 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1742 ntype = V_028C70_NUMBER_SRGB;
1743 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1744 if (desc->channel[i].pure_integer) {
1745 ntype = V_028C70_NUMBER_SINT;
1746 } else {
1747 assert(desc->channel[i].normalized);
1748 ntype = V_028C70_NUMBER_SNORM;
1749 }
1750 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1751 if (desc->channel[i].pure_integer) {
1752 ntype = V_028C70_NUMBER_UINT;
1753 } else {
1754 assert(desc->channel[i].normalized);
1755 ntype = V_028C70_NUMBER_UNORM;
1756 }
1757 }
1758 }
1759
1760 format = si_translate_colorformat(surf->base.format);
1761 if (format == V_028C70_COLOR_INVALID) {
1762 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1763 }
1764 assert(format != V_028C70_COLOR_INVALID);
1765 swap = r600_translate_colorswap(surf->base.format);
1766 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1767 endian = V_028C70_ENDIAN_NONE;
1768 } else {
1769 endian = si_colorformat_endian_swap(format);
1770 }
1771
1772 /* blend clamp should be set for all NORM/SRGB types */
1773 if (ntype == V_028C70_NUMBER_UNORM ||
1774 ntype == V_028C70_NUMBER_SNORM ||
1775 ntype == V_028C70_NUMBER_SRGB)
1776 blend_clamp = 1;
1777
1778 /* set blend bypass according to docs if SINT/UINT or
1779 8/24 COLOR variants */
1780 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1781 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1782 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1783 blend_clamp = 0;
1784 blend_bypass = 1;
1785 }
1786
1787 color_info = S_028C70_FORMAT(format) |
1788 S_028C70_COMP_SWAP(swap) |
1789 S_028C70_BLEND_CLAMP(blend_clamp) |
1790 S_028C70_BLEND_BYPASS(blend_bypass) |
1791 S_028C70_NUMBER_TYPE(ntype) |
1792 S_028C70_ENDIAN(endian);
1793
1794 color_pitch = S_028C64_TILE_MAX(pitch);
1795
1796 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1797 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1798
1799 if (rtex->resource.b.b.nr_samples > 1) {
1800 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1801
1802 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1803 S_028C74_NUM_FRAGMENTS(log_samples);
1804
1805 if (rtex->fmask.size) {
1806 color_info |= S_028C70_COMPRESSION(1);
1807 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1808
1809 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1810
1811 if (sctx->b.chip_class == SI) {
1812 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1813 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1814 }
1815 if (sctx->b.chip_class >= CIK) {
1816 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1817 }
1818 }
1819 }
1820
1821 offset += rtex->resource.gpu_address;
1822
1823 surf->cb_color_base = offset >> 8;
1824 surf->cb_color_pitch = color_pitch;
1825 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1826 surf->cb_color_view = color_view;
1827 surf->cb_color_info = color_info;
1828 surf->cb_color_attrib = color_attrib;
1829
1830 if (rtex->fmask.size) {
1831 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1832 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1833 } else {
1834 /* This must be set for fast clear to work without FMASK. */
1835 surf->cb_color_fmask = surf->cb_color_base;
1836 surf->cb_color_fmask_slice = surf->cb_color_slice;
1837 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1838
1839 if (sctx->b.chip_class == SI) {
1840 unsigned bankh = util_logbase2(rtex->surface.bankh);
1841 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1842 }
1843
1844 if (sctx->b.chip_class >= CIK) {
1845 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1846 }
1847 }
1848
1849 /* Determine pixel shader export format */
1850 max_comp_size = si_colorformat_max_comp_size(format);
1851 if (ntype == V_028C70_NUMBER_SRGB ||
1852 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1853 max_comp_size <= 10) ||
1854 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1855 surf->export_16bpc = true;
1856 }
1857
1858 surf->color_initialized = true;
1859 }
1860
1861 static void si_init_depth_surface(struct si_context *sctx,
1862 struct r600_surface *surf)
1863 {
1864 struct si_screen *sscreen = sctx->screen;
1865 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1866 unsigned level = surf->base.u.tex.level;
1867 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1868 unsigned format, tile_mode_index, array_mode;
1869 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1870 uint32_t z_info, s_info, db_depth_info;
1871 uint64_t z_offs, s_offs;
1872 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1873
1874 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1875 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1876 case PIPE_FORMAT_X8Z24_UNORM:
1877 case PIPE_FORMAT_Z24X8_UNORM:
1878 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1879 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1880 break;
1881 case PIPE_FORMAT_Z32_FLOAT:
1882 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1883 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1884 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1885 break;
1886 case PIPE_FORMAT_Z16_UNORM:
1887 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1888 break;
1889 default:
1890 assert(0);
1891 }
1892
1893 format = si_translate_dbformat(rtex->resource.b.b.format);
1894
1895 if (format == V_028040_Z_INVALID) {
1896 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1897 }
1898 assert(format != V_028040_Z_INVALID);
1899
1900 s_offs = z_offs = rtex->resource.gpu_address;
1901 z_offs += rtex->surface.level[level].offset;
1902 s_offs += rtex->surface.stencil_level[level].offset;
1903
1904 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1905
1906 z_info = S_028040_FORMAT(format);
1907 if (rtex->resource.b.b.nr_samples > 1) {
1908 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1909 }
1910
1911 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1912 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1913 else
1914 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1915
1916 if (sctx->b.chip_class >= CIK) {
1917 switch (rtex->surface.level[level].mode) {
1918 case RADEON_SURF_MODE_2D:
1919 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1920 break;
1921 case RADEON_SURF_MODE_1D:
1922 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1923 case RADEON_SURF_MODE_LINEAR:
1924 default:
1925 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1926 break;
1927 }
1928 tile_split = rtex->surface.tile_split;
1929 stile_split = rtex->surface.stencil_tile_split;
1930 macro_aspect = rtex->surface.mtilea;
1931 bankw = rtex->surface.bankw;
1932 bankh = rtex->surface.bankh;
1933 tile_split = cik_tile_split(tile_split);
1934 stile_split = cik_tile_split(stile_split);
1935 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1936 bankw = cik_bank_wh(bankw);
1937 bankh = cik_bank_wh(bankh);
1938 nbanks = si_num_banks(sscreen, rtex);
1939 tile_mode_index = si_tile_mode_index(rtex, level, false);
1940 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1941
1942 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1943 S_02803C_PIPE_CONFIG(pipe_config) |
1944 S_02803C_BANK_WIDTH(bankw) |
1945 S_02803C_BANK_HEIGHT(bankh) |
1946 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1947 S_02803C_NUM_BANKS(nbanks);
1948 z_info |= S_028040_TILE_SPLIT(tile_split);
1949 s_info |= S_028044_TILE_SPLIT(stile_split);
1950 } else {
1951 tile_mode_index = si_tile_mode_index(rtex, level, false);
1952 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1953 tile_mode_index = si_tile_mode_index(rtex, level, true);
1954 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1955 }
1956
1957 /* HiZ aka depth buffer htile */
1958 /* use htile only for first level */
1959 if (rtex->htile_buffer && !level) {
1960 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1961 S_028040_ALLOW_EXPCLEAR(1);
1962
1963 /* This is optimal for the clear value of 1.0 and using
1964 * the LESS and LEQUAL test functions. Set this to 0
1965 * for the opposite case. This can only be changed when
1966 * clearing. */
1967 z_info |= S_028040_ZRANGE_PRECISION(1);
1968
1969 /* Use all of the htile_buffer for depth, because we don't
1970 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1971 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1972
1973 uint64_t va = rtex->htile_buffer->gpu_address;
1974 db_htile_data_base = va >> 8;
1975 db_htile_surface = S_028ABC_FULL_CACHE(1);
1976 } else {
1977 db_htile_data_base = 0;
1978 db_htile_surface = 0;
1979 }
1980
1981 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1982
1983 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1984 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1985 surf->db_htile_data_base = db_htile_data_base;
1986 surf->db_depth_info = db_depth_info;
1987 surf->db_z_info = z_info;
1988 surf->db_stencil_info = s_info;
1989 surf->db_depth_base = z_offs >> 8;
1990 surf->db_stencil_base = s_offs >> 8;
1991 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1992 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1993 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1994 levelinfo->nblk_y) / 64 - 1);
1995 surf->db_htile_surface = db_htile_surface;
1996 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1997
1998 surf->depth_initialized = true;
1999 }
2000
2001 static void si_set_framebuffer_state(struct pipe_context *ctx,
2002 const struct pipe_framebuffer_state *state)
2003 {
2004 struct si_context *sctx = (struct si_context *)ctx;
2005 struct pipe_constant_buffer constbuf = {0};
2006 struct r600_surface *surf = NULL;
2007 struct r600_texture *rtex;
2008 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2009 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2010 int i;
2011
2012 /* Only flush TC when changing the framebuffer state, because
2013 * the only client not using TC that can change textures is
2014 * the framebuffer.
2015 *
2016 * Flush all CB and DB caches here because all buffers can be used
2017 * for write by both TC (with shader image stores) and CB/DB.
2018 */
2019 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2020 SI_CONTEXT_INV_TC_L2 |
2021 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2022
2023 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2024
2025 sctx->framebuffer.export_16bpc = 0;
2026 sctx->framebuffer.compressed_cb_mask = 0;
2027 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2028 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2029 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2030 util_format_is_pure_integer(state->cbufs[0]->format);
2031
2032 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2033 sctx->db_render_state.dirty = true;
2034
2035 for (i = 0; i < state->nr_cbufs; i++) {
2036 if (!state->cbufs[i])
2037 continue;
2038
2039 surf = (struct r600_surface*)state->cbufs[i];
2040 rtex = (struct r600_texture*)surf->base.texture;
2041
2042 if (!surf->color_initialized) {
2043 si_initialize_color_surface(sctx, surf);
2044 }
2045
2046 if (surf->export_16bpc) {
2047 sctx->framebuffer.export_16bpc |= 1 << i;
2048 }
2049
2050 if (rtex->fmask.size && rtex->cmask.size) {
2051 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2052 }
2053 }
2054 /* Set the 16BPC export for possible dual-src blending. */
2055 if (i == 1 && surf && surf->export_16bpc) {
2056 sctx->framebuffer.export_16bpc |= 1 << 1;
2057 }
2058
2059 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2060
2061 if (state->zsbuf) {
2062 surf = (struct r600_surface*)state->zsbuf;
2063
2064 if (!surf->depth_initialized) {
2065 si_init_depth_surface(sctx, surf);
2066 }
2067 }
2068
2069 si_update_fb_rs_state(sctx);
2070 si_update_fb_blend_state(sctx);
2071
2072 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2073 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2074 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2075 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2076 sctx->framebuffer.atom.dirty = true;
2077
2078 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2079 sctx->msaa_config.dirty = true;
2080 sctx->db_render_state.dirty = true;
2081
2082 /* Set sample locations as fragment shader constants. */
2083 switch (sctx->framebuffer.nr_samples) {
2084 case 1:
2085 constbuf.user_buffer = sctx->b.sample_locations_1x;
2086 break;
2087 case 2:
2088 constbuf.user_buffer = sctx->b.sample_locations_2x;
2089 break;
2090 case 4:
2091 constbuf.user_buffer = sctx->b.sample_locations_4x;
2092 break;
2093 case 8:
2094 constbuf.user_buffer = sctx->b.sample_locations_8x;
2095 break;
2096 case 16:
2097 constbuf.user_buffer = sctx->b.sample_locations_16x;
2098 break;
2099 default:
2100 assert(0);
2101 }
2102 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2103 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2104 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2105
2106 /* Smoothing (only possible with nr_samples == 1) uses the same
2107 * sample locations as the MSAA it simulates.
2108 *
2109 * Therefore, don't update the sample locations when
2110 * transitioning from no AA to smoothing-equivalent AA, and
2111 * vice versa.
2112 */
2113 if ((sctx->framebuffer.nr_samples != 1 ||
2114 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2115 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2116 old_nr_samples != 1))
2117 sctx->msaa_sample_locs.dirty = true;
2118 }
2119 }
2120
2121 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2122 {
2123 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2124 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2125 unsigned i, nr_cbufs = state->nr_cbufs;
2126 struct r600_texture *tex = NULL;
2127 struct r600_surface *cb = NULL;
2128
2129 /* Colorbuffers. */
2130 for (i = 0; i < nr_cbufs; i++) {
2131 cb = (struct r600_surface*)state->cbufs[i];
2132 if (!cb) {
2133 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2134 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2135 continue;
2136 }
2137
2138 tex = (struct r600_texture *)cb->base.texture;
2139 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2140 &tex->resource, RADEON_USAGE_READWRITE,
2141 tex->surface.nsamples > 1 ?
2142 RADEON_PRIO_COLOR_BUFFER_MSAA :
2143 RADEON_PRIO_COLOR_BUFFER);
2144
2145 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2146 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2147 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2148 RADEON_PRIO_COLOR_META);
2149 }
2150
2151 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2152 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2153 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2154 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2155 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2156 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2157 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2158 radeon_emit(cs, 0); /* R_028C78 unused */
2159 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2160 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2161 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2162 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2163 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2164 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2165 }
2166 /* set CB_COLOR1_INFO for possible dual-src blending */
2167 if (i == 1 && state->cbufs[0]) {
2168 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2169 cb->cb_color_info | tex->cb_color_info);
2170 i++;
2171 }
2172 for (; i < 8 ; i++) {
2173 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2174 }
2175
2176 /* ZS buffer. */
2177 if (state->zsbuf) {
2178 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2179 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2180
2181 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2182 &rtex->resource, RADEON_USAGE_READWRITE,
2183 zb->base.texture->nr_samples > 1 ?
2184 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2185 RADEON_PRIO_DEPTH_BUFFER);
2186
2187 if (zb->db_htile_data_base) {
2188 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2189 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2190 RADEON_PRIO_DEPTH_META);
2191 }
2192
2193 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2194 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2195
2196 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2197 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2198 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2199 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2200 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2201 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2202 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2203 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2204 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2205 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2206
2207 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2208 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2209 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2210 zb->pa_su_poly_offset_db_fmt_cntl);
2211 } else {
2212 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2213 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2214 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2215 }
2216
2217 /* Framebuffer dimensions. */
2218 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2219 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2220 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2221 }
2222
2223 static void si_emit_msaa_sample_locs(struct r600_common_context *rctx,
2224 struct r600_atom *atom)
2225 {
2226 struct si_context *sctx = (struct si_context *)rctx;
2227 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2228 unsigned nr_samples = sctx->framebuffer.nr_samples;
2229
2230 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2231 SI_NUM_SMOOTH_AA_SAMPLES);
2232 }
2233
2234 const struct r600_atom si_atom_msaa_sample_locs = { si_emit_msaa_sample_locs, 18 }; /* number of CS dwords */
2235
2236 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2237 {
2238 struct si_context *sctx = (struct si_context *)rctx;
2239 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2240
2241 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2242 sctx->ps_iter_samples,
2243 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2244 }
2245
2246 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2247
2248 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2249 {
2250 struct si_context *sctx = (struct si_context *)ctx;
2251
2252 if (sctx->ps_iter_samples == min_samples)
2253 return;
2254
2255 sctx->ps_iter_samples = min_samples;
2256
2257 if (sctx->framebuffer.nr_samples > 1)
2258 sctx->msaa_config.dirty = true;
2259 }
2260
2261 /*
2262 * Samplers
2263 */
2264
2265 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2266 struct pipe_resource *texture,
2267 const struct pipe_sampler_view *state)
2268 {
2269 struct si_context *sctx = (struct si_context*)ctx;
2270 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2271 struct r600_texture *tmp = (struct r600_texture*)texture;
2272 const struct util_format_description *desc;
2273 unsigned format, num_format;
2274 uint32_t pitch = 0;
2275 unsigned char state_swizzle[4], swizzle[4];
2276 unsigned height, depth, width;
2277 enum pipe_format pipe_format = state->format;
2278 struct radeon_surface_level *surflevel;
2279 int first_non_void;
2280 uint64_t va;
2281
2282 if (view == NULL)
2283 return NULL;
2284
2285 /* initialize base object */
2286 view->base = *state;
2287 view->base.texture = NULL;
2288 view->base.reference.count = 1;
2289 view->base.context = ctx;
2290
2291 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2292 if (!texture) {
2293 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2294 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2295 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2296 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2297 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2298 return &view->base;
2299 }
2300
2301 pipe_resource_reference(&view->base.texture, texture);
2302 view->resource = &tmp->resource;
2303
2304 /* Buffer resource. */
2305 if (texture->target == PIPE_BUFFER) {
2306 unsigned stride;
2307
2308 desc = util_format_description(state->format);
2309 first_non_void = util_format_get_first_non_void_channel(state->format);
2310 stride = desc->block.bits / 8;
2311 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2312 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2313 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2314
2315 view->state[4] = va;
2316 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2317 S_008F04_STRIDE(stride);
2318 view->state[6] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2319 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2320 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2321 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2322 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2323 S_008F0C_NUM_FORMAT(num_format) |
2324 S_008F0C_DATA_FORMAT(format);
2325
2326 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2327 return &view->base;
2328 }
2329
2330 state_swizzle[0] = state->swizzle_r;
2331 state_swizzle[1] = state->swizzle_g;
2332 state_swizzle[2] = state->swizzle_b;
2333 state_swizzle[3] = state->swizzle_a;
2334
2335 surflevel = tmp->surface.level;
2336
2337 /* Texturing with separate depth and stencil. */
2338 if (tmp->is_depth && !tmp->is_flushing_texture) {
2339 switch (pipe_format) {
2340 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2341 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2342 break;
2343 case PIPE_FORMAT_X8Z24_UNORM:
2344 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2345 /* Z24 is always stored like this. */
2346 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2347 break;
2348 case PIPE_FORMAT_X24S8_UINT:
2349 case PIPE_FORMAT_S8X24_UINT:
2350 case PIPE_FORMAT_X32_S8X24_UINT:
2351 pipe_format = PIPE_FORMAT_S8_UINT;
2352 surflevel = tmp->surface.stencil_level;
2353 break;
2354 default:;
2355 }
2356 }
2357
2358 desc = util_format_description(pipe_format);
2359
2360 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2361 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2362 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2363
2364 switch (pipe_format) {
2365 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2366 case PIPE_FORMAT_X24S8_UINT:
2367 case PIPE_FORMAT_X32_S8X24_UINT:
2368 case PIPE_FORMAT_X8Z24_UNORM:
2369 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2370 break;
2371 default:
2372 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2373 }
2374 } else {
2375 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2376 }
2377
2378 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2379
2380 switch (pipe_format) {
2381 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2382 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2383 break;
2384 default:
2385 if (first_non_void < 0) {
2386 if (util_format_is_compressed(pipe_format)) {
2387 switch (pipe_format) {
2388 case PIPE_FORMAT_DXT1_SRGB:
2389 case PIPE_FORMAT_DXT1_SRGBA:
2390 case PIPE_FORMAT_DXT3_SRGBA:
2391 case PIPE_FORMAT_DXT5_SRGBA:
2392 case PIPE_FORMAT_BPTC_SRGBA:
2393 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2394 break;
2395 case PIPE_FORMAT_RGTC1_SNORM:
2396 case PIPE_FORMAT_LATC1_SNORM:
2397 case PIPE_FORMAT_RGTC2_SNORM:
2398 case PIPE_FORMAT_LATC2_SNORM:
2399 /* implies float, so use SNORM/UNORM to determine
2400 whether data is signed or not */
2401 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2402 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2403 break;
2404 default:
2405 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2406 break;
2407 }
2408 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2409 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2410 } else {
2411 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2412 }
2413 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2414 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2415 } else {
2416 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2417
2418 switch (desc->channel[first_non_void].type) {
2419 case UTIL_FORMAT_TYPE_FLOAT:
2420 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2421 break;
2422 case UTIL_FORMAT_TYPE_SIGNED:
2423 if (desc->channel[first_non_void].normalized)
2424 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2425 else if (desc->channel[first_non_void].pure_integer)
2426 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2427 else
2428 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2429 break;
2430 case UTIL_FORMAT_TYPE_UNSIGNED:
2431 if (desc->channel[first_non_void].normalized)
2432 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2433 else if (desc->channel[first_non_void].pure_integer)
2434 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2435 else
2436 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2437 }
2438 }
2439 }
2440
2441 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2442 if (format == ~0) {
2443 format = 0;
2444 }
2445
2446 /* not supported any more */
2447 //endian = si_colorformat_endian_swap(format);
2448
2449 width = surflevel[0].npix_x;
2450 height = surflevel[0].npix_y;
2451 depth = surflevel[0].npix_z;
2452 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2453
2454 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2455 height = 1;
2456 depth = texture->array_size;
2457 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2458 depth = texture->array_size;
2459 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2460 depth = texture->array_size / 6;
2461
2462 va = tmp->resource.gpu_address + surflevel[0].offset;
2463 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2464
2465 view->state[0] = va >> 8;
2466 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2467 S_008F14_DATA_FORMAT(format) |
2468 S_008F14_NUM_FORMAT(num_format));
2469 view->state[2] = (S_008F18_WIDTH(width - 1) |
2470 S_008F18_HEIGHT(height - 1));
2471 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2472 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2473 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2474 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2475 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2476 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2477 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2478 util_logbase2(texture->nr_samples) :
2479 state->u.tex.last_level - tmp->mipmap_shift) |
2480 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2481 S_008F1C_POW2_PAD(texture->last_level > 0) |
2482 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2483 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2484 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2485 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2486 view->state[6] = 0;
2487 view->state[7] = 0;
2488
2489 /* Initialize the sampler view for FMASK. */
2490 if (tmp->fmask.size) {
2491 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2492 uint32_t fmask_format;
2493
2494 switch (texture->nr_samples) {
2495 case 2:
2496 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2497 break;
2498 case 4:
2499 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2500 break;
2501 case 8:
2502 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2503 break;
2504 default:
2505 assert(0);
2506 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2507 }
2508
2509 view->fmask_state[0] = va >> 8;
2510 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2511 S_008F14_DATA_FORMAT(fmask_format) |
2512 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2513 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2514 S_008F18_HEIGHT(height - 1);
2515 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2516 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2517 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2518 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2519 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2520 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2521 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2522 S_008F20_PITCH(tmp->fmask.pitch - 1);
2523 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2524 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2525 view->fmask_state[6] = 0;
2526 view->fmask_state[7] = 0;
2527 }
2528
2529 return &view->base;
2530 }
2531
2532 static void si_sampler_view_destroy(struct pipe_context *ctx,
2533 struct pipe_sampler_view *state)
2534 {
2535 struct si_sampler_view *view = (struct si_sampler_view *)state;
2536
2537 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2538 LIST_DELINIT(&view->list);
2539
2540 pipe_resource_reference(&state->texture, NULL);
2541 FREE(view);
2542 }
2543
2544 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2545 {
2546 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2547 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2548 (linear_filter &&
2549 (wrap == PIPE_TEX_WRAP_CLAMP ||
2550 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2551 }
2552
2553 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2554 {
2555 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2556 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2557
2558 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2559 state->border_color.ui[2] || state->border_color.ui[3]) &&
2560 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2561 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2562 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2563 }
2564
2565 static void *si_create_sampler_state(struct pipe_context *ctx,
2566 const struct pipe_sampler_state *state)
2567 {
2568 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2569 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2570 unsigned border_color_type;
2571
2572 if (rstate == NULL) {
2573 return NULL;
2574 }
2575
2576 if (sampler_state_needs_border_color(state))
2577 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2578 else
2579 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2580
2581 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2582 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2583 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2584 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2585 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2586 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2587 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2588 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2589 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2590 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2591 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2592 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2593 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2594 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2595
2596 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2597 memcpy(rstate->border_color, state->border_color.ui,
2598 sizeof(rstate->border_color));
2599 }
2600
2601 return rstate;
2602 }
2603
2604 /* Upload border colors and update the pointers in resource descriptors.
2605 * There can only be 4096 border colors per context.
2606 *
2607 * XXX: This is broken if the buffer gets reallocated.
2608 */
2609 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2610 void **states)
2611 {
2612 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2613 uint32_t *border_color_table = NULL;
2614 int i, j;
2615
2616 for (i = 0; i < count; i++) {
2617 if (rstates[i] &&
2618 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2619 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2620 if (!sctx->border_color_table ||
2621 ((sctx->border_color_offset + count - i) &
2622 C_008F3C_BORDER_COLOR_PTR)) {
2623 r600_resource_reference(&sctx->border_color_table, NULL);
2624 sctx->border_color_offset = 0;
2625
2626 sctx->border_color_table =
2627 si_resource_create_custom(&sctx->screen->b.b,
2628 PIPE_USAGE_DYNAMIC,
2629 4096 * 4 * 4);
2630 }
2631
2632 if (!border_color_table) {
2633 border_color_table =
2634 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2635 sctx->b.rings.gfx.cs,
2636 PIPE_TRANSFER_WRITE |
2637 PIPE_TRANSFER_UNSYNCHRONIZED);
2638 }
2639
2640 for (j = 0; j < 4; j++) {
2641 border_color_table[4 * sctx->border_color_offset + j] =
2642 util_le32_to_cpu(rstates[i]->border_color[j]);
2643 }
2644
2645 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2646 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2647 }
2648 }
2649
2650 if (border_color_table) {
2651 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2652
2653 uint64_t va_offset = sctx->border_color_table->gpu_address;
2654
2655 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2656 if (sctx->b.chip_class >= CIK)
2657 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2658 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2659 RADEON_PRIO_SHADER_DATA);
2660 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2661 }
2662 }
2663
2664 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2665 unsigned start, unsigned count,
2666 void **states)
2667 {
2668 struct si_context *sctx = (struct si_context *)ctx;
2669
2670 if (!count || shader >= SI_NUM_SHADERS)
2671 return;
2672
2673 si_set_border_colors(sctx, count, states);
2674 si_set_sampler_descriptors(sctx, shader, start, count, states);
2675 }
2676
2677 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2678 {
2679 struct si_context *sctx = (struct si_context *)ctx;
2680 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2681 struct si_pm4_state *pm4 = &state->pm4;
2682 uint16_t mask = sample_mask;
2683
2684 if (state == NULL)
2685 return;
2686
2687 state->sample_mask = mask;
2688 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2689 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2690
2691 si_pm4_set_state(sctx, sample_mask, state);
2692 }
2693
2694 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2695 {
2696 free(state);
2697 }
2698
2699 /*
2700 * Vertex elements & buffers
2701 */
2702
2703 static void *si_create_vertex_elements(struct pipe_context *ctx,
2704 unsigned count,
2705 const struct pipe_vertex_element *elements)
2706 {
2707 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2708 int i;
2709
2710 assert(count < PIPE_MAX_ATTRIBS);
2711 if (!v)
2712 return NULL;
2713
2714 v->count = count;
2715 for (i = 0; i < count; ++i) {
2716 const struct util_format_description *desc;
2717 unsigned data_format, num_format;
2718 int first_non_void;
2719
2720 desc = util_format_description(elements[i].src_format);
2721 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2722 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2723 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2724
2725 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2726 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2727 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2728 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2729 S_008F0C_NUM_FORMAT(num_format) |
2730 S_008F0C_DATA_FORMAT(data_format);
2731 v->format_size[i] = desc->block.bits / 8;
2732 }
2733 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2734
2735 return v;
2736 }
2737
2738 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2739 {
2740 struct si_context *sctx = (struct si_context *)ctx;
2741 struct si_vertex_element *v = (struct si_vertex_element*)state;
2742
2743 sctx->vertex_elements = v;
2744 sctx->vertex_buffers_dirty = true;
2745 }
2746
2747 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2748 {
2749 struct si_context *sctx = (struct si_context *)ctx;
2750
2751 if (sctx->vertex_elements == state)
2752 sctx->vertex_elements = NULL;
2753 FREE(state);
2754 }
2755
2756 static void si_set_vertex_buffers(struct pipe_context *ctx,
2757 unsigned start_slot, unsigned count,
2758 const struct pipe_vertex_buffer *buffers)
2759 {
2760 struct si_context *sctx = (struct si_context *)ctx;
2761 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2762 int i;
2763
2764 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2765
2766 if (buffers) {
2767 for (i = 0; i < count; i++) {
2768 const struct pipe_vertex_buffer *src = buffers + i;
2769 struct pipe_vertex_buffer *dsti = dst + i;
2770
2771 pipe_resource_reference(&dsti->buffer, src->buffer);
2772 dsti->buffer_offset = src->buffer_offset;
2773 dsti->stride = src->stride;
2774 }
2775 } else {
2776 for (i = 0; i < count; i++) {
2777 pipe_resource_reference(&dst[i].buffer, NULL);
2778 }
2779 }
2780 sctx->vertex_buffers_dirty = true;
2781 }
2782
2783 static void si_set_index_buffer(struct pipe_context *ctx,
2784 const struct pipe_index_buffer *ib)
2785 {
2786 struct si_context *sctx = (struct si_context *)ctx;
2787
2788 if (ib) {
2789 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2790 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2791 } else {
2792 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2793 }
2794 }
2795
2796 /*
2797 * Misc
2798 */
2799 static void si_set_polygon_stipple(struct pipe_context *ctx,
2800 const struct pipe_poly_stipple *state)
2801 {
2802 struct si_context *sctx = (struct si_context *)ctx;
2803 struct pipe_resource *tex;
2804 struct pipe_sampler_view *view;
2805 bool is_zero = true;
2806 bool is_one = true;
2807 int i;
2808
2809 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2810 * the resource is NULL/invalid. Take advantage of this fact and skip
2811 * texture allocation if the stipple pattern is constant.
2812 *
2813 * This is an optimization for the common case when stippling isn't
2814 * used but set_polygon_stipple is still called by st/mesa.
2815 */
2816 for (i = 0; i < Elements(state->stipple); i++) {
2817 is_zero = is_zero && state->stipple[i] == 0;
2818 is_one = is_one && state->stipple[i] == 0xffffffff;
2819 }
2820
2821 if (is_zero || is_one) {
2822 struct pipe_sampler_view templ = {{0}};
2823
2824 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2825 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2826 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2827 /* The pattern should be inverted in the texture. */
2828 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2829
2830 view = ctx->create_sampler_view(ctx, NULL, &templ);
2831 } else {
2832 /* Create a new texture. */
2833 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2834 if (!tex)
2835 return;
2836
2837 view = util_pstipple_create_sampler_view(ctx, tex);
2838 pipe_resource_reference(&tex, NULL);
2839 }
2840
2841 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2842 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2843 pipe_sampler_view_reference(&view, NULL);
2844
2845 /* Bind the sampler state if needed. */
2846 if (!sctx->pstipple_sampler_state) {
2847 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2848 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2849 SI_POLY_STIPPLE_SAMPLER, 1,
2850 &sctx->pstipple_sampler_state);
2851 }
2852 }
2853
2854 static void si_texture_barrier(struct pipe_context *ctx)
2855 {
2856 struct si_context *sctx = (struct si_context *)ctx;
2857
2858 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2859 SI_CONTEXT_INV_TC_L2 |
2860 SI_CONTEXT_FLUSH_AND_INV_CB;
2861 }
2862
2863 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2864 {
2865 struct pipe_blend_state blend;
2866
2867 memset(&blend, 0, sizeof(blend));
2868 blend.independent_blend_enable = true;
2869 blend.rt[0].colormask = 0xf;
2870 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2871 }
2872
2873 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2874 bool include_draw_vbo)
2875 {
2876 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2877 }
2878
2879 void si_init_state_functions(struct si_context *sctx)
2880 {
2881 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2882 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2883 si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
2884
2885 sctx->b.b.create_blend_state = si_create_blend_state;
2886 sctx->b.b.bind_blend_state = si_bind_blend_state;
2887 sctx->b.b.delete_blend_state = si_delete_blend_state;
2888 sctx->b.b.set_blend_color = si_set_blend_color;
2889
2890 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2891 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2892 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2893
2894 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2895 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2896 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2897
2898 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2899 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2900 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2901 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2902
2903 sctx->b.b.set_clip_state = si_set_clip_state;
2904 sctx->b.b.set_scissor_states = si_set_scissor_states;
2905 sctx->b.b.set_viewport_states = si_set_viewport_states;
2906 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2907
2908 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2909 sctx->b.b.get_sample_position = cayman_get_sample_position;
2910
2911 sctx->b.b.create_sampler_state = si_create_sampler_state;
2912 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2913 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2914
2915 sctx->b.b.create_sampler_view = si_create_sampler_view;
2916 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2917
2918 sctx->b.b.set_sample_mask = si_set_sample_mask;
2919
2920 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2921 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2922 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2923 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2924 sctx->b.b.set_index_buffer = si_set_index_buffer;
2925
2926 sctx->b.b.texture_barrier = si_texture_barrier;
2927 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2928 sctx->b.b.set_min_samples = si_set_min_samples;
2929
2930 sctx->b.dma_copy = si_dma_copy;
2931 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2932 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2933
2934 sctx->b.b.draw_vbo = si_draw_vbo;
2935 }
2936
2937 static void
2938 si_write_harvested_raster_configs(struct si_context *sctx,
2939 struct si_pm4_state *pm4,
2940 unsigned raster_config)
2941 {
2942 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
2943 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
2944 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2945 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2946 unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
2947 unsigned rb_per_se = num_rb / num_se;
2948 unsigned se0_mask = (1 << rb_per_se) - 1;
2949 unsigned se1_mask = se0_mask << rb_per_se;
2950 unsigned se;
2951
2952 assert(num_se == 1 || num_se == 2);
2953 assert(sh_per_se == 1 || sh_per_se == 2);
2954 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
2955
2956 /* XXX: I can't figure out what the *_XSEL and *_YSEL
2957 * fields are for, so I'm leaving them as their default
2958 * values. */
2959
2960 se0_mask &= rb_mask;
2961 se1_mask &= rb_mask;
2962 if (num_se == 2 && (!se0_mask || !se1_mask)) {
2963 raster_config &= C_028350_SE_MAP;
2964
2965 if (!se0_mask) {
2966 raster_config |=
2967 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
2968 } else {
2969 raster_config |=
2970 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
2971 }
2972 }
2973
2974 for (se = 0; se < num_se; se++) {
2975 unsigned raster_config_se = raster_config;
2976 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
2977 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
2978
2979 pkr0_mask &= rb_mask;
2980 pkr1_mask &= rb_mask;
2981 if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
2982 raster_config_se &= C_028350_PKR_MAP;
2983
2984 if (!pkr0_mask) {
2985 raster_config_se |=
2986 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
2987 } else {
2988 raster_config_se |=
2989 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
2990 }
2991 }
2992
2993 if (rb_per_pkr == 2) {
2994 unsigned rb0_mask = 1 << (se * rb_per_se);
2995 unsigned rb1_mask = rb0_mask << 1;
2996
2997 rb0_mask &= rb_mask;
2998 rb1_mask &= rb_mask;
2999 if (!rb0_mask || !rb1_mask) {
3000 raster_config_se &= C_028350_RB_MAP_PKR0;
3001
3002 if (!rb0_mask) {
3003 raster_config_se |=
3004 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3005 } else {
3006 raster_config_se |=
3007 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3008 }
3009 }
3010
3011 if (sh_per_se == 2) {
3012 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3013 rb1_mask = rb0_mask << 1;
3014 rb0_mask &= rb_mask;
3015 rb1_mask &= rb_mask;
3016 if (!rb0_mask || !rb1_mask) {
3017 raster_config_se &= C_028350_RB_MAP_PKR1;
3018
3019 if (!rb0_mask) {
3020 raster_config_se |=
3021 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3022 } else {
3023 raster_config_se |=
3024 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3025 }
3026 }
3027 }
3028 }
3029
3030 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3031 SE_INDEX(se) | SH_BROADCAST_WRITES |
3032 INSTANCE_BROADCAST_WRITES);
3033 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3034 }
3035
3036 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3037 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3038 INSTANCE_BROADCAST_WRITES);
3039 }
3040
3041 void si_init_config(struct si_context *sctx)
3042 {
3043 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3044
3045 if (pm4 == NULL)
3046 return;
3047
3048 si_cmd_context_control(pm4);
3049
3050 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3051 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3052 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3053 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3054 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3055 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3056 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3057 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3058 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3059 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3060 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3061 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3062
3063 /* FIXME calculate these values somehow ??? */
3064 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3065 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3066 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3067
3068 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3069 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3070 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3071 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3072
3073 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3074 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3075 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3076 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3077
3078 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3079 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3080 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3081 if (sctx->b.chip_class < CIK)
3082 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3083 S_008A14_CLIP_VTX_REORDER_ENA(1));
3084
3085 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3086 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3087
3088 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3089
3090 if (sctx->b.chip_class >= CIK) {
3091 switch (sctx->screen->b.family) {
3092 case CHIP_BONAIRE:
3093 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3094 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3095 break;
3096 case CHIP_HAWAII:
3097 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3098 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3099 break;
3100 case CHIP_KAVERI:
3101 /* XXX todo */
3102 case CHIP_KABINI:
3103 /* XXX todo */
3104 case CHIP_MULLINS:
3105 /* XXX todo */
3106 default:
3107 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
3108 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3109 break;
3110 }
3111 } else {
3112 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3113 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
3114 unsigned raster_config;
3115
3116 switch (sctx->screen->b.family) {
3117 case CHIP_TAHITI:
3118 case CHIP_PITCAIRN:
3119 raster_config = 0x2a00126a;
3120 break;
3121 case CHIP_VERDE:
3122 raster_config = 0x0000124a;
3123 break;
3124 case CHIP_OLAND:
3125 raster_config = 0x00000082;
3126 break;
3127 case CHIP_HAINAN:
3128 raster_config = 0;
3129 break;
3130 default:
3131 fprintf(stderr,
3132 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3133 raster_config = 0;
3134 break;
3135 }
3136
3137 /* Always use the default config when all backends are enabled
3138 * (or when we failed to determine the enabled backends).
3139 */
3140 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3141 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3142 raster_config);
3143 } else {
3144 si_write_harvested_raster_configs(sctx, pm4, raster_config);
3145 }
3146 }
3147
3148 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3149 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3150 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3151 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3152 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3153 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3154 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3155
3156 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3157 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3158 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3159 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3160 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0);
3161 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, fui(1.0));
3162 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3163 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3164 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3165 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3166 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3167 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0);
3168 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0);
3169 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3170 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3171 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3172 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3173
3174 /* There is a hang if stencil is used and fast stencil is enabled
3175 * regardless of whether HTILE is depth-only or not.
3176 */
3177 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3178 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3179 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3180 S_02800C_FAST_STENCIL_DISABLE(1));
3181
3182 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3183 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3184 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3185
3186 if (sctx->b.chip_class >= CIK) {
3187 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3188 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3189 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3190 }
3191
3192 sctx->init_config = pm4;
3193 }