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radeonsi/gfx9: set optimal OVERWRITE_COMBINER_WATERMARK
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= VI) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == VI ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
117
118 radeon_opt_set_context_reg(
119 sctx, R_028424_CB_DCC_CONTROL,
120 SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct si_surface *surf =
137 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_028C70_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_028C70_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_028C70_SWAP_STD ||
228 swap == V_028C70_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
252 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
253 SI_TRACKED_SX_PS_DOWNCONVERT,
254 sx_ps_downconvert, sx_blend_opt_epsilon,
255 sx_blend_opt_control);
256 }
257 if (initial_cdw != cs->current.cdw)
258 sctx->context_roll_counter++;
259 }
260
261 /*
262 * Blender functions
263 */
264
265 static uint32_t si_translate_blend_function(int blend_func)
266 {
267 switch (blend_func) {
268 case PIPE_BLEND_ADD:
269 return V_028780_COMB_DST_PLUS_SRC;
270 case PIPE_BLEND_SUBTRACT:
271 return V_028780_COMB_SRC_MINUS_DST;
272 case PIPE_BLEND_REVERSE_SUBTRACT:
273 return V_028780_COMB_DST_MINUS_SRC;
274 case PIPE_BLEND_MIN:
275 return V_028780_COMB_MIN_DST_SRC;
276 case PIPE_BLEND_MAX:
277 return V_028780_COMB_MAX_DST_SRC;
278 default:
279 PRINT_ERR("Unknown blend function %d\n", blend_func);
280 assert(0);
281 break;
282 }
283 return 0;
284 }
285
286 static uint32_t si_translate_blend_factor(int blend_fact)
287 {
288 switch (blend_fact) {
289 case PIPE_BLENDFACTOR_ONE:
290 return V_028780_BLEND_ONE;
291 case PIPE_BLENDFACTOR_SRC_COLOR:
292 return V_028780_BLEND_SRC_COLOR;
293 case PIPE_BLENDFACTOR_SRC_ALPHA:
294 return V_028780_BLEND_SRC_ALPHA;
295 case PIPE_BLENDFACTOR_DST_ALPHA:
296 return V_028780_BLEND_DST_ALPHA;
297 case PIPE_BLENDFACTOR_DST_COLOR:
298 return V_028780_BLEND_DST_COLOR;
299 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
300 return V_028780_BLEND_SRC_ALPHA_SATURATE;
301 case PIPE_BLENDFACTOR_CONST_COLOR:
302 return V_028780_BLEND_CONSTANT_COLOR;
303 case PIPE_BLENDFACTOR_CONST_ALPHA:
304 return V_028780_BLEND_CONSTANT_ALPHA;
305 case PIPE_BLENDFACTOR_ZERO:
306 return V_028780_BLEND_ZERO;
307 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
308 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
309 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
310 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
311 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_COLOR:
314 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
315 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
319 case PIPE_BLENDFACTOR_SRC1_COLOR:
320 return V_028780_BLEND_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_SRC1_ALPHA:
322 return V_028780_BLEND_SRC1_ALPHA;
323 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
324 return V_028780_BLEND_INV_SRC1_COLOR;
325 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
326 return V_028780_BLEND_INV_SRC1_ALPHA;
327 default:
328 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
329 assert(0);
330 break;
331 }
332 return 0;
333 }
334
335 static uint32_t si_translate_blend_opt_function(int blend_func)
336 {
337 switch (blend_func) {
338 case PIPE_BLEND_ADD:
339 return V_028760_OPT_COMB_ADD;
340 case PIPE_BLEND_SUBTRACT:
341 return V_028760_OPT_COMB_SUBTRACT;
342 case PIPE_BLEND_REVERSE_SUBTRACT:
343 return V_028760_OPT_COMB_REVSUBTRACT;
344 case PIPE_BLEND_MIN:
345 return V_028760_OPT_COMB_MIN;
346 case PIPE_BLEND_MAX:
347 return V_028760_OPT_COMB_MAX;
348 default:
349 return V_028760_OPT_COMB_BLEND_DISABLED;
350 }
351 }
352
353 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
354 {
355 switch (blend_fact) {
356 case PIPE_BLENDFACTOR_ZERO:
357 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
358 case PIPE_BLENDFACTOR_ONE:
359 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
360 case PIPE_BLENDFACTOR_SRC_COLOR:
361 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
362 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
363 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
365 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA:
367 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
368 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
370 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
372 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
373 default:
374 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
375 }
376 }
377
378 static void si_blend_check_commutativity(struct si_screen *sscreen,
379 struct si_state_blend *blend,
380 enum pipe_blend_func func,
381 enum pipe_blendfactor src,
382 enum pipe_blendfactor dst,
383 unsigned chanmask)
384 {
385 /* Src factor is allowed when it does not depend on Dst */
386 static const uint32_t src_allowed =
387 (1u << PIPE_BLENDFACTOR_ONE) |
388 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
389 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
391 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
392 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
394 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_ZERO) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
398 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
400 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
402
403 if (dst == PIPE_BLENDFACTOR_ONE &&
404 (src_allowed & (1u << src))) {
405 /* Addition is commutative, but floating point addition isn't
406 * associative: subtle changes can be introduced via different
407 * rounding.
408 *
409 * Out-of-order is also non-deterministic, which means that
410 * this breaks OpenGL invariance requirements. So only enable
411 * out-of-order additive blending if explicitly allowed by a
412 * setting.
413 */
414 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
415 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
416 blend->commutative_4bit |= chanmask;
417 }
418 }
419
420 /**
421 * Get rid of DST in the blend factors by commuting the operands:
422 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
423 */
424 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
425 unsigned *dst_factor, unsigned expected_dst,
426 unsigned replacement_src)
427 {
428 if (*src_factor == expected_dst &&
429 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
430 *src_factor = PIPE_BLENDFACTOR_ZERO;
431 *dst_factor = replacement_src;
432
433 /* Commuting the operands requires reversing subtractions. */
434 if (*func == PIPE_BLEND_SUBTRACT)
435 *func = PIPE_BLEND_REVERSE_SUBTRACT;
436 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
437 *func = PIPE_BLEND_SUBTRACT;
438 }
439 }
440
441 static bool si_blend_factor_uses_dst(unsigned factor)
442 {
443 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
444 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
445 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
446 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
447 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
448 }
449
450 static void *si_create_blend_state_mode(struct pipe_context *ctx,
451 const struct pipe_blend_state *state,
452 unsigned mode)
453 {
454 struct si_context *sctx = (struct si_context*)ctx;
455 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
456 struct si_pm4_state *pm4 = &blend->pm4;
457 uint32_t sx_mrt_blend_opt[8] = {0};
458 uint32_t color_control = 0;
459
460 if (!blend)
461 return NULL;
462
463 blend->alpha_to_coverage = state->alpha_to_coverage;
464 blend->alpha_to_one = state->alpha_to_one;
465 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
466 blend->logicop_enable = state->logicop_enable;
467
468 if (state->logicop_enable) {
469 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
470 } else {
471 color_control |= S_028808_ROP3(0xcc);
472 }
473
474 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
475 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
476 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
477 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
478 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
480
481 if (state->alpha_to_coverage)
482 blend->need_src_alpha_4bit |= 0xf;
483
484 blend->cb_target_mask = 0;
485 blend->cb_target_enabled_4bit = 0;
486
487 for (int i = 0; i < 8; i++) {
488 /* state->rt entries > 0 only written if independent blending */
489 const int j = state->independent_blend_enable ? i : 0;
490
491 unsigned eqRGB = state->rt[j].rgb_func;
492 unsigned srcRGB = state->rt[j].rgb_src_factor;
493 unsigned dstRGB = state->rt[j].rgb_dst_factor;
494 unsigned eqA = state->rt[j].alpha_func;
495 unsigned srcA = state->rt[j].alpha_src_factor;
496 unsigned dstA = state->rt[j].alpha_dst_factor;
497
498 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
499 unsigned blend_cntl = 0;
500
501 sx_mrt_blend_opt[i] =
502 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
503 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
504
505 /* Only set dual source blending for MRT0 to avoid a hang. */
506 if (i >= 1 && blend->dual_src_blend) {
507 /* Vulkan does this for dual source blending. */
508 if (i == 1)
509 blend_cntl |= S_028780_ENABLE(1);
510
511 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
512 continue;
513 }
514
515 /* Only addition and subtraction equations are supported with
516 * dual source blending.
517 */
518 if (blend->dual_src_blend &&
519 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
520 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
521 assert(!"Unsupported equation for dual source blending");
522 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
523 continue;
524 }
525
526 /* cb_render_state will disable unused ones */
527 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
528 if (state->rt[j].colormask)
529 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
530
531 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 si_blend_check_commutativity(sctx->screen, blend,
537 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqA, srcA, dstA, 0x8 << (4 * i));
540
541 /* Blending optimizations for RB+.
542 * These transformations don't change the behavior.
543 *
544 * First, get rid of DST in the blend factors:
545 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
546 */
547 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
548 PIPE_BLENDFACTOR_DST_COLOR,
549 PIPE_BLENDFACTOR_SRC_COLOR);
550 si_blend_remove_dst(&eqA, &srcA, &dstA,
551 PIPE_BLENDFACTOR_DST_COLOR,
552 PIPE_BLENDFACTOR_SRC_COLOR);
553 si_blend_remove_dst(&eqA, &srcA, &dstA,
554 PIPE_BLENDFACTOR_DST_ALPHA,
555 PIPE_BLENDFACTOR_SRC_ALPHA);
556
557 /* Look up the ideal settings from tables. */
558 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
559 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
560 srcA_opt = si_translate_blend_opt_factor(srcA, true);
561 dstA_opt = si_translate_blend_opt_factor(dstA, true);
562
563 /* Handle interdependencies. */
564 if (si_blend_factor_uses_dst(srcRGB))
565 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
566 if (si_blend_factor_uses_dst(srcA))
567 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568
569 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
570 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
571 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
572 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
573 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
574
575 /* Set the final value. */
576 sx_mrt_blend_opt[i] =
577 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
578 S_028760_COLOR_DST_OPT(dstRGB_opt) |
579 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
580 S_028760_ALPHA_SRC_OPT(srcA_opt) |
581 S_028760_ALPHA_DST_OPT(dstA_opt) |
582 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
583
584 /* Set blend state. */
585 blend_cntl |= S_028780_ENABLE(1);
586 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
587 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
588 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
589
590 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
591 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
592 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
593 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
594 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
595 }
596 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
597
598 blend->blend_enable_4bit |= 0xfu << (i * 4);
599
600 /* This is only important for formats without alpha. */
601 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
602 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
603 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
605 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
606 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
607 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
608 }
609
610 if (blend->cb_target_mask) {
611 color_control |= S_028808_MODE(mode);
612 } else {
613 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
614 }
615
616 if (sctx->screen->rbplus_allowed) {
617 /* Disable RB+ blend optimizations for dual source blending.
618 * Vulkan does this.
619 */
620 if (blend->dual_src_blend) {
621 for (int i = 0; i < 8; i++) {
622 sx_mrt_blend_opt[i] =
623 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
624 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
625 }
626 }
627
628 for (int i = 0; i < 8; i++)
629 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
630 sx_mrt_blend_opt[i]);
631
632 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
633 if (blend->dual_src_blend || state->logicop_enable ||
634 mode == V_028808_CB_RESOLVE)
635 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
636 }
637
638 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
639 return blend;
640 }
641
642 static void *si_create_blend_state(struct pipe_context *ctx,
643 const struct pipe_blend_state *state)
644 {
645 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
646 }
647
648 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
649 {
650 struct si_context *sctx = (struct si_context *)ctx;
651 struct si_state_blend *old_blend = sctx->queued.named.blend;
652 struct si_state_blend *blend = (struct si_state_blend *)state;
653
654 if (!state)
655 return;
656
657 si_pm4_bind_state(sctx, blend, state);
658
659 if (!old_blend ||
660 old_blend->cb_target_mask != blend->cb_target_mask ||
661 old_blend->dual_src_blend != blend->dual_src_blend ||
662 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
663 sctx->framebuffer.nr_samples >= 2 &&
664 sctx->screen->dcc_msaa_allowed))
665 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
666
667 if (!old_blend ||
668 old_blend->cb_target_mask != blend->cb_target_mask ||
669 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
670 old_blend->alpha_to_one != blend->alpha_to_one ||
671 old_blend->dual_src_blend != blend->dual_src_blend ||
672 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
673 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
674 sctx->do_update_shaders = true;
675
676 if (sctx->screen->dpbb_allowed &&
677 (!old_blend ||
678 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
679 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
680 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
681 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
682
683 if (sctx->screen->has_out_of_order_rast &&
684 (!old_blend ||
685 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
686 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
687 old_blend->commutative_4bit != blend->commutative_4bit ||
688 old_blend->logicop_enable != blend->logicop_enable)))
689 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
690 }
691
692 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
693 {
694 struct si_context *sctx = (struct si_context *)ctx;
695 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
696 }
697
698 static void si_set_blend_color(struct pipe_context *ctx,
699 const struct pipe_blend_color *state)
700 {
701 struct si_context *sctx = (struct si_context *)ctx;
702 static const struct pipe_blend_color zeros;
703
704 sctx->blend_color.state = *state;
705 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
706 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
707 }
708
709 static void si_emit_blend_color(struct si_context *sctx)
710 {
711 struct radeon_cmdbuf *cs = sctx->gfx_cs;
712
713 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
714 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
715 }
716
717 /*
718 * Clipping
719 */
720
721 static void si_set_clip_state(struct pipe_context *ctx,
722 const struct pipe_clip_state *state)
723 {
724 struct si_context *sctx = (struct si_context *)ctx;
725 struct pipe_constant_buffer cb;
726 static const struct pipe_clip_state zeros;
727
728 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
729 return;
730
731 sctx->clip_state.state = *state;
732 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
733 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
734
735 cb.buffer = NULL;
736 cb.user_buffer = state->ucp;
737 cb.buffer_offset = 0;
738 cb.buffer_size = 4*4*8;
739 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
740 pipe_resource_reference(&cb.buffer, NULL);
741 }
742
743 static void si_emit_clip_state(struct si_context *sctx)
744 {
745 struct radeon_cmdbuf *cs = sctx->gfx_cs;
746
747 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
748 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
749 }
750
751 static void si_emit_clip_regs(struct si_context *sctx)
752 {
753 struct si_shader *vs = si_get_vs_state(sctx);
754 struct si_shader_selector *vs_sel = vs->selector;
755 struct tgsi_shader_info *info = &vs_sel->info;
756 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
757 unsigned window_space =
758 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
759 unsigned clipdist_mask = vs_sel->clipdist_mask;
760 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
761 unsigned culldist_mask = vs_sel->culldist_mask;
762 unsigned total_mask;
763
764 if (vs->key.opt.clip_disable) {
765 assert(!info->culldist_writemask);
766 clipdist_mask = 0;
767 culldist_mask = 0;
768 }
769 total_mask = clipdist_mask | culldist_mask;
770
771 /* Clip distances on points have no effect, so need to be implemented
772 * as cull distances. This applies for the clipvertex case as well.
773 *
774 * Setting this for primitives other than points should have no adverse
775 * effects.
776 */
777 clipdist_mask &= rs->clip_plane_enable;
778 culldist_mask |= clipdist_mask;
779
780 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
781 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
782 SI_TRACKED_PA_CL_VS_OUT_CNTL,
783 vs_sel->pa_cl_vs_out_cntl |
784 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
785 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
786 clipdist_mask | (culldist_mask << 8));
787 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
788 SI_TRACKED_PA_CL_CLIP_CNTL,
789 rs->pa_cl_clip_cntl |
790 ucp_mask |
791 S_028810_CLIP_DISABLE(window_space));
792
793 if (initial_cdw != sctx->gfx_cs->current.cdw)
794 sctx->context_roll_counter++;
795 }
796
797 /*
798 * inferred state between framebuffer and rasterizer
799 */
800 static void si_update_poly_offset_state(struct si_context *sctx)
801 {
802 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
803
804 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
805 si_pm4_bind_state(sctx, poly_offset, NULL);
806 return;
807 }
808
809 /* Use the user format, not db_render_format, so that the polygon
810 * offset behaves as expected by applications.
811 */
812 switch (sctx->framebuffer.state.zsbuf->texture->format) {
813 case PIPE_FORMAT_Z16_UNORM:
814 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
815 break;
816 default: /* 24-bit */
817 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
818 break;
819 case PIPE_FORMAT_Z32_FLOAT:
820 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
821 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
822 break;
823 }
824 }
825
826 /*
827 * Rasterizer
828 */
829
830 static uint32_t si_translate_fill(uint32_t func)
831 {
832 switch(func) {
833 case PIPE_POLYGON_MODE_FILL:
834 return V_028814_X_DRAW_TRIANGLES;
835 case PIPE_POLYGON_MODE_LINE:
836 return V_028814_X_DRAW_LINES;
837 case PIPE_POLYGON_MODE_POINT:
838 return V_028814_X_DRAW_POINTS;
839 default:
840 assert(0);
841 return V_028814_X_DRAW_POINTS;
842 }
843 }
844
845 static void *si_create_rs_state(struct pipe_context *ctx,
846 const struct pipe_rasterizer_state *state)
847 {
848 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
849 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
850 struct si_pm4_state *pm4 = &rs->pm4;
851 unsigned tmp, i;
852 float psize_min, psize_max;
853
854 if (!rs) {
855 return NULL;
856 }
857
858 rs->scissor_enable = state->scissor;
859 rs->clip_halfz = state->clip_halfz;
860 rs->two_side = state->light_twoside;
861 rs->multisample_enable = state->multisample;
862 rs->force_persample_interp = state->force_persample_interp;
863 rs->clip_plane_enable = state->clip_plane_enable;
864 rs->half_pixel_center = state->half_pixel_center;
865 rs->line_stipple_enable = state->line_stipple_enable;
866 rs->poly_stipple_enable = state->poly_stipple_enable;
867 rs->line_smooth = state->line_smooth;
868 rs->line_width = state->line_width;
869 rs->poly_smooth = state->poly_smooth;
870 rs->uses_poly_offset = state->offset_point || state->offset_line ||
871 state->offset_tri;
872 rs->clamp_fragment_color = state->clamp_fragment_color;
873 rs->clamp_vertex_color = state->clamp_vertex_color;
874 rs->flatshade = state->flatshade;
875 rs->sprite_coord_enable = state->sprite_coord_enable;
876 rs->rasterizer_discard = state->rasterizer_discard;
877 rs->pa_sc_line_stipple = state->line_stipple_enable ?
878 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
879 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
880 rs->pa_cl_clip_cntl =
881 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
882 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
883 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
884 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
885 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
886
887 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
888 S_0286D4_FLAT_SHADE_ENA(1) |
889 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
890 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
891 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
892 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
893 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
894 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
895
896 /* point size 12.4 fixed point */
897 tmp = (unsigned)(state->point_size * 8.0);
898 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
899
900 if (state->point_size_per_vertex) {
901 psize_min = util_get_min_point_size(state);
902 psize_max = SI_MAX_POINT_SIZE;
903 } else {
904 /* Force the point size to be as if the vertex output was disabled. */
905 psize_min = state->point_size;
906 psize_max = state->point_size;
907 }
908 rs->max_point_size = psize_max;
909
910 /* Divide by two, because 0.5 = 1 pixel. */
911 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
912 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
913 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
914
915 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
916 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
917 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
918 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
919 S_028A48_MSAA_ENABLE(state->multisample ||
920 state->poly_smooth ||
921 state->line_smooth) |
922 S_028A48_VPORT_SCISSOR_ENABLE(1) |
923 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
924
925 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
926 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
927 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
928 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
929 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
930 S_028814_FACE(!state->front_ccw) |
931 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
932 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
933 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
934 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
935 state->fill_back != PIPE_POLYGON_MODE_FILL) |
936 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
937 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
938
939 if (!rs->uses_poly_offset)
940 return rs;
941
942 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
943 if (!rs->pm4_poly_offset) {
944 FREE(rs);
945 return NULL;
946 }
947
948 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
949 for (i = 0; i < 3; i++) {
950 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
951 float offset_units = state->offset_units;
952 float offset_scale = state->offset_scale * 16.0f;
953 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
954
955 if (!state->offset_units_unscaled) {
956 switch (i) {
957 case 0: /* 16-bit zbuffer */
958 offset_units *= 4.0f;
959 pa_su_poly_offset_db_fmt_cntl =
960 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
961 break;
962 case 1: /* 24-bit zbuffer */
963 offset_units *= 2.0f;
964 pa_su_poly_offset_db_fmt_cntl =
965 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
966 break;
967 case 2: /* 32-bit zbuffer */
968 offset_units *= 1.0f;
969 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
970 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
971 break;
972 }
973 }
974
975 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
976 fui(offset_scale));
977 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
978 fui(offset_units));
979 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
980 fui(offset_scale));
981 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
982 fui(offset_units));
983 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
984 pa_su_poly_offset_db_fmt_cntl);
985 }
986
987 return rs;
988 }
989
990 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
991 {
992 struct si_context *sctx = (struct si_context *)ctx;
993 struct si_state_rasterizer *old_rs =
994 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
995 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
996
997 if (!state)
998 return;
999
1000 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1001 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1002
1003 /* Update the small primitive filter workaround if necessary. */
1004 if (sctx->screen->has_msaa_sample_loc_bug &&
1005 sctx->framebuffer.nr_samples > 1)
1006 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1007 }
1008
1009 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1010 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1011
1012 si_pm4_bind_state(sctx, rasterizer, rs);
1013 si_update_poly_offset_state(sctx);
1014
1015 if (!old_rs ||
1016 old_rs->scissor_enable != rs->scissor_enable) {
1017 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1018 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1019 }
1020
1021 if (!old_rs ||
1022 old_rs->line_width != rs->line_width ||
1023 old_rs->max_point_size != rs->max_point_size ||
1024 old_rs->half_pixel_center != rs->half_pixel_center)
1025 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1026
1027 if (!old_rs ||
1028 old_rs->clip_halfz != rs->clip_halfz) {
1029 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1030 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1031 }
1032
1033 if (!old_rs ||
1034 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1035 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1036 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1037
1038 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1039 rs->line_stipple_enable;
1040
1041 if (!old_rs ||
1042 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1043 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1044 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1045 old_rs->flatshade != rs->flatshade ||
1046 old_rs->two_side != rs->two_side ||
1047 old_rs->multisample_enable != rs->multisample_enable ||
1048 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1049 old_rs->poly_smooth != rs->poly_smooth ||
1050 old_rs->line_smooth != rs->line_smooth ||
1051 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1052 old_rs->force_persample_interp != rs->force_persample_interp)
1053 sctx->do_update_shaders = true;
1054 }
1055
1056 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1057 {
1058 struct si_context *sctx = (struct si_context *)ctx;
1059 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1060
1061 if (sctx->queued.named.rasterizer == state)
1062 si_pm4_bind_state(sctx, poly_offset, NULL);
1063
1064 FREE(rs->pm4_poly_offset);
1065 si_pm4_delete_state(sctx, rasterizer, rs);
1066 }
1067
1068 /*
1069 * infeered state between dsa and stencil ref
1070 */
1071 static void si_emit_stencil_ref(struct si_context *sctx)
1072 {
1073 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1074 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1075 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1076
1077 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1078 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1079 S_028430_STENCILMASK(dsa->valuemask[0]) |
1080 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1081 S_028430_STENCILOPVAL(1));
1082 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1083 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1084 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1085 S_028434_STENCILOPVAL_BF(1));
1086 }
1087
1088 static void si_set_stencil_ref(struct pipe_context *ctx,
1089 const struct pipe_stencil_ref *state)
1090 {
1091 struct si_context *sctx = (struct si_context *)ctx;
1092
1093 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1094 return;
1095
1096 sctx->stencil_ref.state = *state;
1097 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1098 }
1099
1100
1101 /*
1102 * DSA
1103 */
1104
1105 static uint32_t si_translate_stencil_op(int s_op)
1106 {
1107 switch (s_op) {
1108 case PIPE_STENCIL_OP_KEEP:
1109 return V_02842C_STENCIL_KEEP;
1110 case PIPE_STENCIL_OP_ZERO:
1111 return V_02842C_STENCIL_ZERO;
1112 case PIPE_STENCIL_OP_REPLACE:
1113 return V_02842C_STENCIL_REPLACE_TEST;
1114 case PIPE_STENCIL_OP_INCR:
1115 return V_02842C_STENCIL_ADD_CLAMP;
1116 case PIPE_STENCIL_OP_DECR:
1117 return V_02842C_STENCIL_SUB_CLAMP;
1118 case PIPE_STENCIL_OP_INCR_WRAP:
1119 return V_02842C_STENCIL_ADD_WRAP;
1120 case PIPE_STENCIL_OP_DECR_WRAP:
1121 return V_02842C_STENCIL_SUB_WRAP;
1122 case PIPE_STENCIL_OP_INVERT:
1123 return V_02842C_STENCIL_INVERT;
1124 default:
1125 PRINT_ERR("Unknown stencil op %d", s_op);
1126 assert(0);
1127 break;
1128 }
1129 return 0;
1130 }
1131
1132 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1133 {
1134 return s->enabled && s->writemask &&
1135 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1136 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1137 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1138 }
1139
1140 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1141 {
1142 /* REPLACE is normally order invariant, except when the stencil
1143 * reference value is written by the fragment shader. Tracking this
1144 * interaction does not seem worth the effort, so be conservative. */
1145 return op != PIPE_STENCIL_OP_INCR &&
1146 op != PIPE_STENCIL_OP_DECR &&
1147 op != PIPE_STENCIL_OP_REPLACE;
1148 }
1149
1150 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1151 * invariant in the sense that the set of passing fragments as well as the
1152 * final stencil buffer result does not depend on the order of fragments. */
1153 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1154 {
1155 return !state->enabled || !state->writemask ||
1156 /* The following assumes that Z writes are disabled. */
1157 (state->func == PIPE_FUNC_ALWAYS &&
1158 si_order_invariant_stencil_op(state->zpass_op) &&
1159 si_order_invariant_stencil_op(state->zfail_op)) ||
1160 (state->func == PIPE_FUNC_NEVER &&
1161 si_order_invariant_stencil_op(state->fail_op));
1162 }
1163
1164 static void *si_create_dsa_state(struct pipe_context *ctx,
1165 const struct pipe_depth_stencil_alpha_state *state)
1166 {
1167 struct si_context *sctx = (struct si_context *)ctx;
1168 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1169 struct si_pm4_state *pm4 = &dsa->pm4;
1170 unsigned db_depth_control;
1171 uint32_t db_stencil_control = 0;
1172
1173 if (!dsa) {
1174 return NULL;
1175 }
1176
1177 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1178 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1179 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1180 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1181
1182 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1183 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1184 S_028800_ZFUNC(state->depth.func) |
1185 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1186
1187 /* stencil */
1188 if (state->stencil[0].enabled) {
1189 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1190 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1191 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1192 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1193 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1194
1195 if (state->stencil[1].enabled) {
1196 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1197 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1198 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1199 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1200 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1201 }
1202 }
1203
1204 /* alpha */
1205 if (state->alpha.enabled) {
1206 dsa->alpha_func = state->alpha.func;
1207
1208 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1209 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1210 } else {
1211 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1212 }
1213
1214 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1215 if (state->stencil[0].enabled)
1216 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1217 if (state->depth.bounds_test) {
1218 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1219 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1220 }
1221
1222 dsa->depth_enabled = state->depth.enabled;
1223 dsa->depth_write_enabled = state->depth.enabled &&
1224 state->depth.writemask;
1225 dsa->stencil_enabled = state->stencil[0].enabled;
1226 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1227 (si_dsa_writes_stencil(&state->stencil[0]) ||
1228 si_dsa_writes_stencil(&state->stencil[1]));
1229 dsa->db_can_write = dsa->depth_write_enabled ||
1230 dsa->stencil_write_enabled;
1231
1232 bool zfunc_is_ordered =
1233 state->depth.func == PIPE_FUNC_NEVER ||
1234 state->depth.func == PIPE_FUNC_LESS ||
1235 state->depth.func == PIPE_FUNC_LEQUAL ||
1236 state->depth.func == PIPE_FUNC_GREATER ||
1237 state->depth.func == PIPE_FUNC_GEQUAL;
1238
1239 bool nozwrite_and_order_invariant_stencil =
1240 !dsa->db_can_write ||
1241 (!dsa->depth_write_enabled &&
1242 si_order_invariant_stencil_state(&state->stencil[0]) &&
1243 si_order_invariant_stencil_state(&state->stencil[1]));
1244
1245 dsa->order_invariance[1].zs =
1246 nozwrite_and_order_invariant_stencil ||
1247 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1248 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1249
1250 dsa->order_invariance[1].pass_set =
1251 nozwrite_and_order_invariant_stencil ||
1252 (!dsa->stencil_write_enabled &&
1253 (state->depth.func == PIPE_FUNC_ALWAYS ||
1254 state->depth.func == PIPE_FUNC_NEVER));
1255 dsa->order_invariance[0].pass_set =
1256 !dsa->depth_write_enabled ||
1257 (state->depth.func == PIPE_FUNC_ALWAYS ||
1258 state->depth.func == PIPE_FUNC_NEVER);
1259
1260 dsa->order_invariance[1].pass_last =
1261 sctx->screen->assume_no_z_fights &&
1262 !dsa->stencil_write_enabled &&
1263 dsa->depth_write_enabled && zfunc_is_ordered;
1264 dsa->order_invariance[0].pass_last =
1265 sctx->screen->assume_no_z_fights &&
1266 dsa->depth_write_enabled && zfunc_is_ordered;
1267
1268 return dsa;
1269 }
1270
1271 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1272 {
1273 struct si_context *sctx = (struct si_context *)ctx;
1274 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1275 struct si_state_dsa *dsa = state;
1276
1277 if (!state)
1278 return;
1279
1280 si_pm4_bind_state(sctx, dsa, dsa);
1281
1282 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1283 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1284 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1285 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1286 }
1287
1288 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1289 sctx->do_update_shaders = true;
1290
1291 if (sctx->screen->dpbb_allowed &&
1292 (!old_dsa ||
1293 (old_dsa->depth_enabled != dsa->depth_enabled ||
1294 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1295 old_dsa->db_can_write != dsa->db_can_write)))
1296 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1297
1298 if (sctx->screen->has_out_of_order_rast &&
1299 (!old_dsa ||
1300 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1301 sizeof(old_dsa->order_invariance))))
1302 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1303 }
1304
1305 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1306 {
1307 struct si_context *sctx = (struct si_context *)ctx;
1308 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1309 }
1310
1311 static void *si_create_db_flush_dsa(struct si_context *sctx)
1312 {
1313 struct pipe_depth_stencil_alpha_state dsa = {};
1314
1315 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1316 }
1317
1318 /* DB RENDER STATE */
1319
1320 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1321 {
1322 struct si_context *sctx = (struct si_context*)ctx;
1323
1324 /* Pipeline stat & streamout queries. */
1325 if (enable) {
1326 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1327 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1328 } else {
1329 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1330 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1331 }
1332
1333 /* Occlusion queries. */
1334 if (sctx->occlusion_queries_disabled != !enable) {
1335 sctx->occlusion_queries_disabled = !enable;
1336 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1337 }
1338 }
1339
1340 void si_set_occlusion_query_state(struct si_context *sctx,
1341 bool old_perfect_enable)
1342 {
1343 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1344
1345 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1346
1347 if (perfect_enable != old_perfect_enable)
1348 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1349 }
1350
1351 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1352 {
1353 st->saved_compute = sctx->cs_shader_state.program;
1354
1355 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1356 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1357 }
1358
1359 static void si_emit_db_render_state(struct si_context *sctx)
1360 {
1361 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1362 unsigned db_shader_control, db_render_control, db_count_control;
1363 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1364
1365 /* DB_RENDER_CONTROL */
1366 if (sctx->dbcb_depth_copy_enabled ||
1367 sctx->dbcb_stencil_copy_enabled) {
1368 db_render_control =
1369 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1370 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1371 S_028000_COPY_CENTROID(1) |
1372 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1373 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1374 db_render_control =
1375 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1376 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1377 } else {
1378 db_render_control =
1379 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1380 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1381 }
1382
1383 /* DB_COUNT_CONTROL (occlusion queries) */
1384 if (sctx->num_occlusion_queries > 0 &&
1385 !sctx->occlusion_queries_disabled) {
1386 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1387
1388 if (sctx->chip_class >= CIK) {
1389 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1390
1391 /* Stoney doesn't increment occlusion query counters
1392 * if the sample rate is 16x. Use 8x sample rate instead.
1393 */
1394 if (sctx->family == CHIP_STONEY)
1395 log_sample_rate = MIN2(log_sample_rate, 3);
1396
1397 db_count_control =
1398 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1399 S_028004_SAMPLE_RATE(log_sample_rate) |
1400 S_028004_ZPASS_ENABLE(1) |
1401 S_028004_SLICE_EVEN_ENABLE(1) |
1402 S_028004_SLICE_ODD_ENABLE(1);
1403 } else {
1404 db_count_control =
1405 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1406 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1407 }
1408 } else {
1409 /* Disable occlusion queries. */
1410 if (sctx->chip_class >= CIK) {
1411 db_count_control = 0;
1412 } else {
1413 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1414 }
1415 }
1416
1417 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1418 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1419 db_count_control);
1420
1421 /* DB_RENDER_OVERRIDE2 */
1422 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1423 SI_TRACKED_DB_RENDER_OVERRIDE2,
1424 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1425 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1426 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1427
1428 db_shader_control = sctx->ps_db_shader_control;
1429
1430 /* Bug workaround for smoothing (overrasterization) on SI. */
1431 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1432 db_shader_control &= C_02880C_Z_ORDER;
1433 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1434 }
1435
1436 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1437 if (!rs->multisample_enable)
1438 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1439
1440 if (sctx->screen->has_rbplus &&
1441 !sctx->screen->rbplus_allowed)
1442 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1443
1444 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1445 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1446
1447 if (initial_cdw != sctx->gfx_cs->current.cdw)
1448 sctx->context_roll_counter++;
1449 }
1450
1451 /*
1452 * format translation
1453 */
1454 static uint32_t si_translate_colorformat(enum pipe_format format)
1455 {
1456 const struct util_format_description *desc = util_format_description(format);
1457 if (!desc)
1458 return V_028C70_COLOR_INVALID;
1459
1460 #define HAS_SIZE(x,y,z,w) \
1461 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1462 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1463
1464 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1465 return V_028C70_COLOR_10_11_11;
1466
1467 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1468 return V_028C70_COLOR_INVALID;
1469
1470 /* hw cannot support mixed formats (except depth/stencil, since
1471 * stencil is not written to). */
1472 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1473 return V_028C70_COLOR_INVALID;
1474
1475 switch (desc->nr_channels) {
1476 case 1:
1477 switch (desc->channel[0].size) {
1478 case 8:
1479 return V_028C70_COLOR_8;
1480 case 16:
1481 return V_028C70_COLOR_16;
1482 case 32:
1483 return V_028C70_COLOR_32;
1484 }
1485 break;
1486 case 2:
1487 if (desc->channel[0].size == desc->channel[1].size) {
1488 switch (desc->channel[0].size) {
1489 case 8:
1490 return V_028C70_COLOR_8_8;
1491 case 16:
1492 return V_028C70_COLOR_16_16;
1493 case 32:
1494 return V_028C70_COLOR_32_32;
1495 }
1496 } else if (HAS_SIZE(8,24,0,0)) {
1497 return V_028C70_COLOR_24_8;
1498 } else if (HAS_SIZE(24,8,0,0)) {
1499 return V_028C70_COLOR_8_24;
1500 }
1501 break;
1502 case 3:
1503 if (HAS_SIZE(5,6,5,0)) {
1504 return V_028C70_COLOR_5_6_5;
1505 } else if (HAS_SIZE(32,8,24,0)) {
1506 return V_028C70_COLOR_X24_8_32_FLOAT;
1507 }
1508 break;
1509 case 4:
1510 if (desc->channel[0].size == desc->channel[1].size &&
1511 desc->channel[0].size == desc->channel[2].size &&
1512 desc->channel[0].size == desc->channel[3].size) {
1513 switch (desc->channel[0].size) {
1514 case 4:
1515 return V_028C70_COLOR_4_4_4_4;
1516 case 8:
1517 return V_028C70_COLOR_8_8_8_8;
1518 case 16:
1519 return V_028C70_COLOR_16_16_16_16;
1520 case 32:
1521 return V_028C70_COLOR_32_32_32_32;
1522 }
1523 } else if (HAS_SIZE(5,5,5,1)) {
1524 return V_028C70_COLOR_1_5_5_5;
1525 } else if (HAS_SIZE(1,5,5,5)) {
1526 return V_028C70_COLOR_5_5_5_1;
1527 } else if (HAS_SIZE(10,10,10,2)) {
1528 return V_028C70_COLOR_2_10_10_10;
1529 }
1530 break;
1531 }
1532 return V_028C70_COLOR_INVALID;
1533 }
1534
1535 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1536 {
1537 if (SI_BIG_ENDIAN) {
1538 switch(colorformat) {
1539 /* 8-bit buffers. */
1540 case V_028C70_COLOR_8:
1541 return V_028C70_ENDIAN_NONE;
1542
1543 /* 16-bit buffers. */
1544 case V_028C70_COLOR_5_6_5:
1545 case V_028C70_COLOR_1_5_5_5:
1546 case V_028C70_COLOR_4_4_4_4:
1547 case V_028C70_COLOR_16:
1548 case V_028C70_COLOR_8_8:
1549 return V_028C70_ENDIAN_8IN16;
1550
1551 /* 32-bit buffers. */
1552 case V_028C70_COLOR_8_8_8_8:
1553 case V_028C70_COLOR_2_10_10_10:
1554 case V_028C70_COLOR_8_24:
1555 case V_028C70_COLOR_24_8:
1556 case V_028C70_COLOR_16_16:
1557 return V_028C70_ENDIAN_8IN32;
1558
1559 /* 64-bit buffers. */
1560 case V_028C70_COLOR_16_16_16_16:
1561 return V_028C70_ENDIAN_8IN16;
1562
1563 case V_028C70_COLOR_32_32:
1564 return V_028C70_ENDIAN_8IN32;
1565
1566 /* 128-bit buffers. */
1567 case V_028C70_COLOR_32_32_32_32:
1568 return V_028C70_ENDIAN_8IN32;
1569 default:
1570 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1571 }
1572 } else {
1573 return V_028C70_ENDIAN_NONE;
1574 }
1575 }
1576
1577 static uint32_t si_translate_dbformat(enum pipe_format format)
1578 {
1579 switch (format) {
1580 case PIPE_FORMAT_Z16_UNORM:
1581 return V_028040_Z_16;
1582 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1583 case PIPE_FORMAT_X8Z24_UNORM:
1584 case PIPE_FORMAT_Z24X8_UNORM:
1585 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1586 return V_028040_Z_24; /* deprecated on SI */
1587 case PIPE_FORMAT_Z32_FLOAT:
1588 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1589 return V_028040_Z_32_FLOAT;
1590 default:
1591 return V_028040_Z_INVALID;
1592 }
1593 }
1594
1595 /*
1596 * Texture translation
1597 */
1598
1599 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1600 enum pipe_format format,
1601 const struct util_format_description *desc,
1602 int first_non_void)
1603 {
1604 struct si_screen *sscreen = (struct si_screen*)screen;
1605 bool uniform = true;
1606 int i;
1607
1608 /* Colorspace (return non-RGB formats directly). */
1609 switch (desc->colorspace) {
1610 /* Depth stencil formats */
1611 case UTIL_FORMAT_COLORSPACE_ZS:
1612 switch (format) {
1613 case PIPE_FORMAT_Z16_UNORM:
1614 return V_008F14_IMG_DATA_FORMAT_16;
1615 case PIPE_FORMAT_X24S8_UINT:
1616 case PIPE_FORMAT_S8X24_UINT:
1617 /*
1618 * Implemented as an 8_8_8_8 data format to fix texture
1619 * gathers in stencil sampling. This affects at least
1620 * GL45-CTS.texture_cube_map_array.sampling on VI.
1621 */
1622 if (sscreen->info.chip_class <= VI)
1623 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1624
1625 if (format == PIPE_FORMAT_X24S8_UINT)
1626 return V_008F14_IMG_DATA_FORMAT_8_24;
1627 else
1628 return V_008F14_IMG_DATA_FORMAT_24_8;
1629 case PIPE_FORMAT_Z24X8_UNORM:
1630 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1631 return V_008F14_IMG_DATA_FORMAT_8_24;
1632 case PIPE_FORMAT_X8Z24_UNORM:
1633 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1634 return V_008F14_IMG_DATA_FORMAT_24_8;
1635 case PIPE_FORMAT_S8_UINT:
1636 return V_008F14_IMG_DATA_FORMAT_8;
1637 case PIPE_FORMAT_Z32_FLOAT:
1638 return V_008F14_IMG_DATA_FORMAT_32;
1639 case PIPE_FORMAT_X32_S8X24_UINT:
1640 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1641 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1642 default:
1643 goto out_unknown;
1644 }
1645
1646 case UTIL_FORMAT_COLORSPACE_YUV:
1647 goto out_unknown; /* TODO */
1648
1649 case UTIL_FORMAT_COLORSPACE_SRGB:
1650 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1651 goto out_unknown;
1652 break;
1653
1654 default:
1655 break;
1656 }
1657
1658 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1659 if (!sscreen->info.has_format_bc1_through_bc7)
1660 goto out_unknown;
1661
1662 switch (format) {
1663 case PIPE_FORMAT_RGTC1_SNORM:
1664 case PIPE_FORMAT_LATC1_SNORM:
1665 case PIPE_FORMAT_RGTC1_UNORM:
1666 case PIPE_FORMAT_LATC1_UNORM:
1667 return V_008F14_IMG_DATA_FORMAT_BC4;
1668 case PIPE_FORMAT_RGTC2_SNORM:
1669 case PIPE_FORMAT_LATC2_SNORM:
1670 case PIPE_FORMAT_RGTC2_UNORM:
1671 case PIPE_FORMAT_LATC2_UNORM:
1672 return V_008F14_IMG_DATA_FORMAT_BC5;
1673 default:
1674 goto out_unknown;
1675 }
1676 }
1677
1678 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1679 (sscreen->info.family == CHIP_STONEY ||
1680 sscreen->info.family == CHIP_VEGA10 ||
1681 sscreen->info.family == CHIP_RAVEN)) {
1682 switch (format) {
1683 case PIPE_FORMAT_ETC1_RGB8:
1684 case PIPE_FORMAT_ETC2_RGB8:
1685 case PIPE_FORMAT_ETC2_SRGB8:
1686 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1687 case PIPE_FORMAT_ETC2_RGB8A1:
1688 case PIPE_FORMAT_ETC2_SRGB8A1:
1689 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1690 case PIPE_FORMAT_ETC2_RGBA8:
1691 case PIPE_FORMAT_ETC2_SRGBA8:
1692 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1693 case PIPE_FORMAT_ETC2_R11_UNORM:
1694 case PIPE_FORMAT_ETC2_R11_SNORM:
1695 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1696 case PIPE_FORMAT_ETC2_RG11_UNORM:
1697 case PIPE_FORMAT_ETC2_RG11_SNORM:
1698 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1699 default:
1700 goto out_unknown;
1701 }
1702 }
1703
1704 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1705 if (!sscreen->info.has_format_bc1_through_bc7)
1706 goto out_unknown;
1707
1708 switch (format) {
1709 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1710 case PIPE_FORMAT_BPTC_SRGBA:
1711 return V_008F14_IMG_DATA_FORMAT_BC7;
1712 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1713 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1714 return V_008F14_IMG_DATA_FORMAT_BC6;
1715 default:
1716 goto out_unknown;
1717 }
1718 }
1719
1720 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1721 switch (format) {
1722 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1723 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1724 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1725 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1726 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1727 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1728 default:
1729 goto out_unknown;
1730 }
1731 }
1732
1733 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1734 if (!sscreen->info.has_format_bc1_through_bc7)
1735 goto out_unknown;
1736
1737 switch (format) {
1738 case PIPE_FORMAT_DXT1_RGB:
1739 case PIPE_FORMAT_DXT1_RGBA:
1740 case PIPE_FORMAT_DXT1_SRGB:
1741 case PIPE_FORMAT_DXT1_SRGBA:
1742 return V_008F14_IMG_DATA_FORMAT_BC1;
1743 case PIPE_FORMAT_DXT3_RGBA:
1744 case PIPE_FORMAT_DXT3_SRGBA:
1745 return V_008F14_IMG_DATA_FORMAT_BC2;
1746 case PIPE_FORMAT_DXT5_RGBA:
1747 case PIPE_FORMAT_DXT5_SRGBA:
1748 return V_008F14_IMG_DATA_FORMAT_BC3;
1749 default:
1750 goto out_unknown;
1751 }
1752 }
1753
1754 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1755 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1756 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1757 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1758 }
1759
1760 /* R8G8Bx_SNORM - TODO CxV8U8 */
1761
1762 /* hw cannot support mixed formats (except depth/stencil, since only
1763 * depth is read).*/
1764 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1765 goto out_unknown;
1766
1767 /* See whether the components are of the same size. */
1768 for (i = 1; i < desc->nr_channels; i++) {
1769 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1770 }
1771
1772 /* Non-uniform formats. */
1773 if (!uniform) {
1774 switch(desc->nr_channels) {
1775 case 3:
1776 if (desc->channel[0].size == 5 &&
1777 desc->channel[1].size == 6 &&
1778 desc->channel[2].size == 5) {
1779 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1780 }
1781 goto out_unknown;
1782 case 4:
1783 if (desc->channel[0].size == 5 &&
1784 desc->channel[1].size == 5 &&
1785 desc->channel[2].size == 5 &&
1786 desc->channel[3].size == 1) {
1787 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1788 }
1789 if (desc->channel[0].size == 1 &&
1790 desc->channel[1].size == 5 &&
1791 desc->channel[2].size == 5 &&
1792 desc->channel[3].size == 5) {
1793 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1794 }
1795 if (desc->channel[0].size == 10 &&
1796 desc->channel[1].size == 10 &&
1797 desc->channel[2].size == 10 &&
1798 desc->channel[3].size == 2) {
1799 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1800 }
1801 goto out_unknown;
1802 }
1803 goto out_unknown;
1804 }
1805
1806 if (first_non_void < 0 || first_non_void > 3)
1807 goto out_unknown;
1808
1809 /* uniform formats */
1810 switch (desc->channel[first_non_void].size) {
1811 case 4:
1812 switch (desc->nr_channels) {
1813 #if 0 /* Not supported for render targets */
1814 case 2:
1815 return V_008F14_IMG_DATA_FORMAT_4_4;
1816 #endif
1817 case 4:
1818 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1819 }
1820 break;
1821 case 8:
1822 switch (desc->nr_channels) {
1823 case 1:
1824 return V_008F14_IMG_DATA_FORMAT_8;
1825 case 2:
1826 return V_008F14_IMG_DATA_FORMAT_8_8;
1827 case 4:
1828 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1829 }
1830 break;
1831 case 16:
1832 switch (desc->nr_channels) {
1833 case 1:
1834 return V_008F14_IMG_DATA_FORMAT_16;
1835 case 2:
1836 return V_008F14_IMG_DATA_FORMAT_16_16;
1837 case 4:
1838 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1839 }
1840 break;
1841 case 32:
1842 switch (desc->nr_channels) {
1843 case 1:
1844 return V_008F14_IMG_DATA_FORMAT_32;
1845 case 2:
1846 return V_008F14_IMG_DATA_FORMAT_32_32;
1847 #if 0 /* Not supported for render targets */
1848 case 3:
1849 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1850 #endif
1851 case 4:
1852 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1853 }
1854 }
1855
1856 out_unknown:
1857 return ~0;
1858 }
1859
1860 static unsigned si_tex_wrap(unsigned wrap)
1861 {
1862 switch (wrap) {
1863 default:
1864 case PIPE_TEX_WRAP_REPEAT:
1865 return V_008F30_SQ_TEX_WRAP;
1866 case PIPE_TEX_WRAP_CLAMP:
1867 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1868 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1869 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1870 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1871 return V_008F30_SQ_TEX_CLAMP_BORDER;
1872 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1873 return V_008F30_SQ_TEX_MIRROR;
1874 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1875 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1876 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1877 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1878 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1879 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1880 }
1881 }
1882
1883 static unsigned si_tex_mipfilter(unsigned filter)
1884 {
1885 switch (filter) {
1886 case PIPE_TEX_MIPFILTER_NEAREST:
1887 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1888 case PIPE_TEX_MIPFILTER_LINEAR:
1889 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1890 default:
1891 case PIPE_TEX_MIPFILTER_NONE:
1892 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1893 }
1894 }
1895
1896 static unsigned si_tex_compare(unsigned compare)
1897 {
1898 switch (compare) {
1899 default:
1900 case PIPE_FUNC_NEVER:
1901 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1902 case PIPE_FUNC_LESS:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1904 case PIPE_FUNC_EQUAL:
1905 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1906 case PIPE_FUNC_LEQUAL:
1907 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1908 case PIPE_FUNC_GREATER:
1909 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1910 case PIPE_FUNC_NOTEQUAL:
1911 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1912 case PIPE_FUNC_GEQUAL:
1913 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1914 case PIPE_FUNC_ALWAYS:
1915 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1916 }
1917 }
1918
1919 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1920 unsigned view_target, unsigned nr_samples)
1921 {
1922 unsigned res_target = tex->buffer.b.b.target;
1923
1924 if (view_target == PIPE_TEXTURE_CUBE ||
1925 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1926 res_target = view_target;
1927 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1928 else if (res_target == PIPE_TEXTURE_CUBE ||
1929 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1930 res_target = PIPE_TEXTURE_2D_ARRAY;
1931
1932 /* GFX9 allocates 1D textures as 2D. */
1933 if ((res_target == PIPE_TEXTURE_1D ||
1934 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1935 sscreen->info.chip_class >= GFX9 &&
1936 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1937 if (res_target == PIPE_TEXTURE_1D)
1938 res_target = PIPE_TEXTURE_2D;
1939 else
1940 res_target = PIPE_TEXTURE_2D_ARRAY;
1941 }
1942
1943 switch (res_target) {
1944 default:
1945 case PIPE_TEXTURE_1D:
1946 return V_008F1C_SQ_RSRC_IMG_1D;
1947 case PIPE_TEXTURE_1D_ARRAY:
1948 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1949 case PIPE_TEXTURE_2D:
1950 case PIPE_TEXTURE_RECT:
1951 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1952 V_008F1C_SQ_RSRC_IMG_2D;
1953 case PIPE_TEXTURE_2D_ARRAY:
1954 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1955 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1956 case PIPE_TEXTURE_3D:
1957 return V_008F1C_SQ_RSRC_IMG_3D;
1958 case PIPE_TEXTURE_CUBE:
1959 case PIPE_TEXTURE_CUBE_ARRAY:
1960 return V_008F1C_SQ_RSRC_IMG_CUBE;
1961 }
1962 }
1963
1964 /*
1965 * Format support testing
1966 */
1967
1968 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1969 {
1970 const struct util_format_description *desc = util_format_description(format);
1971 if (!desc)
1972 return false;
1973
1974 return si_translate_texformat(screen, format, desc,
1975 util_format_get_first_non_void_channel(format)) != ~0U;
1976 }
1977
1978 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1979 const struct util_format_description *desc,
1980 int first_non_void)
1981 {
1982 int i;
1983
1984 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1985 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1986
1987 assert(first_non_void >= 0);
1988
1989 if (desc->nr_channels == 4 &&
1990 desc->channel[0].size == 10 &&
1991 desc->channel[1].size == 10 &&
1992 desc->channel[2].size == 10 &&
1993 desc->channel[3].size == 2)
1994 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1995
1996 /* See whether the components are of the same size. */
1997 for (i = 0; i < desc->nr_channels; i++) {
1998 if (desc->channel[first_non_void].size != desc->channel[i].size)
1999 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2000 }
2001
2002 switch (desc->channel[first_non_void].size) {
2003 case 8:
2004 switch (desc->nr_channels) {
2005 case 1:
2006 case 3: /* 3 loads */
2007 return V_008F0C_BUF_DATA_FORMAT_8;
2008 case 2:
2009 return V_008F0C_BUF_DATA_FORMAT_8_8;
2010 case 4:
2011 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2012 }
2013 break;
2014 case 16:
2015 switch (desc->nr_channels) {
2016 case 1:
2017 case 3: /* 3 loads */
2018 return V_008F0C_BUF_DATA_FORMAT_16;
2019 case 2:
2020 return V_008F0C_BUF_DATA_FORMAT_16_16;
2021 case 4:
2022 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2023 }
2024 break;
2025 case 32:
2026 switch (desc->nr_channels) {
2027 case 1:
2028 return V_008F0C_BUF_DATA_FORMAT_32;
2029 case 2:
2030 return V_008F0C_BUF_DATA_FORMAT_32_32;
2031 case 3:
2032 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2033 case 4:
2034 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2035 }
2036 break;
2037 case 64:
2038 /* Legacy double formats. */
2039 switch (desc->nr_channels) {
2040 case 1: /* 1 load */
2041 return V_008F0C_BUF_DATA_FORMAT_32_32;
2042 case 2: /* 1 load */
2043 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2044 case 3: /* 3 loads */
2045 return V_008F0C_BUF_DATA_FORMAT_32_32;
2046 case 4: /* 2 loads */
2047 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2048 }
2049 break;
2050 }
2051
2052 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2053 }
2054
2055 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2056 const struct util_format_description *desc,
2057 int first_non_void)
2058 {
2059 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2060 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2061
2062 assert(first_non_void >= 0);
2063
2064 switch (desc->channel[first_non_void].type) {
2065 case UTIL_FORMAT_TYPE_SIGNED:
2066 case UTIL_FORMAT_TYPE_FIXED:
2067 if (desc->channel[first_non_void].size >= 32 ||
2068 desc->channel[first_non_void].pure_integer)
2069 return V_008F0C_BUF_NUM_FORMAT_SINT;
2070 else if (desc->channel[first_non_void].normalized)
2071 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2072 else
2073 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2074 break;
2075 case UTIL_FORMAT_TYPE_UNSIGNED:
2076 if (desc->channel[first_non_void].size >= 32 ||
2077 desc->channel[first_non_void].pure_integer)
2078 return V_008F0C_BUF_NUM_FORMAT_UINT;
2079 else if (desc->channel[first_non_void].normalized)
2080 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2081 else
2082 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2083 break;
2084 case UTIL_FORMAT_TYPE_FLOAT:
2085 default:
2086 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2087 }
2088 }
2089
2090 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2091 enum pipe_format format,
2092 unsigned usage)
2093 {
2094 const struct util_format_description *desc;
2095 int first_non_void;
2096 unsigned data_format;
2097
2098 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2099 PIPE_BIND_SAMPLER_VIEW |
2100 PIPE_BIND_VERTEX_BUFFER)) == 0);
2101
2102 desc = util_format_description(format);
2103 if (!desc)
2104 return 0;
2105
2106 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2107 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2108 * for read-only access (with caveats surrounding bounds checks), but
2109 * obviously fails for write access which we have to implement for
2110 * shader images. Luckily, OpenGL doesn't expect this to be supported
2111 * anyway, and so the only impact is on PBO uploads / downloads, which
2112 * shouldn't be expected to be fast for GL_RGB anyway.
2113 */
2114 if (desc->block.bits == 3 * 8 ||
2115 desc->block.bits == 3 * 16) {
2116 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2117 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2118 if (!usage)
2119 return 0;
2120 }
2121 }
2122
2123 first_non_void = util_format_get_first_non_void_channel(format);
2124 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2125 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2126 return 0;
2127
2128 return usage;
2129 }
2130
2131 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2132 {
2133 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2134 si_translate_colorswap(format, false) != ~0U;
2135 }
2136
2137 static bool si_is_zs_format_supported(enum pipe_format format)
2138 {
2139 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2140 }
2141
2142 static boolean si_is_format_supported(struct pipe_screen *screen,
2143 enum pipe_format format,
2144 enum pipe_texture_target target,
2145 unsigned sample_count,
2146 unsigned storage_sample_count,
2147 unsigned usage)
2148 {
2149 struct si_screen *sscreen = (struct si_screen *)screen;
2150 unsigned retval = 0;
2151
2152 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2153 PRINT_ERR("r600: unsupported texture type %d\n", target);
2154 return false;
2155 }
2156
2157 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2158 return false;
2159
2160 if (sample_count > 1) {
2161 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2162 return false;
2163
2164 if (usage & PIPE_BIND_SHADER_IMAGE)
2165 return false;
2166
2167 /* Only power-of-two sample counts are supported. */
2168 if (!util_is_power_of_two_or_zero(sample_count) ||
2169 !util_is_power_of_two_or_zero(storage_sample_count))
2170 return false;
2171
2172 /* MSAA support without framebuffer attachments. */
2173 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2174 return true;
2175
2176 if (!sscreen->info.has_eqaa_surface_allocator ||
2177 util_format_is_depth_or_stencil(format)) {
2178 /* Color without EQAA or depth/stencil. */
2179 if (sample_count > 8 ||
2180 sample_count != storage_sample_count)
2181 return false;
2182 } else {
2183 /* Color with EQAA. */
2184 if (sample_count > 16 ||
2185 storage_sample_count > 8)
2186 return false;
2187 }
2188 }
2189
2190 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2191 PIPE_BIND_SHADER_IMAGE)) {
2192 if (target == PIPE_BUFFER) {
2193 retval |= si_is_vertex_format_supported(
2194 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2195 PIPE_BIND_SHADER_IMAGE));
2196 } else {
2197 if (si_is_sampler_format_supported(screen, format))
2198 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2199 PIPE_BIND_SHADER_IMAGE);
2200 }
2201 }
2202
2203 if ((usage & (PIPE_BIND_RENDER_TARGET |
2204 PIPE_BIND_DISPLAY_TARGET |
2205 PIPE_BIND_SCANOUT |
2206 PIPE_BIND_SHARED |
2207 PIPE_BIND_BLENDABLE)) &&
2208 si_is_colorbuffer_format_supported(format)) {
2209 retval |= usage &
2210 (PIPE_BIND_RENDER_TARGET |
2211 PIPE_BIND_DISPLAY_TARGET |
2212 PIPE_BIND_SCANOUT |
2213 PIPE_BIND_SHARED);
2214 if (!util_format_is_pure_integer(format) &&
2215 !util_format_is_depth_or_stencil(format))
2216 retval |= usage & PIPE_BIND_BLENDABLE;
2217 }
2218
2219 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2220 si_is_zs_format_supported(format)) {
2221 retval |= PIPE_BIND_DEPTH_STENCIL;
2222 }
2223
2224 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2225 retval |= si_is_vertex_format_supported(screen, format,
2226 PIPE_BIND_VERTEX_BUFFER);
2227 }
2228
2229 if ((usage & PIPE_BIND_LINEAR) &&
2230 !util_format_is_compressed(format) &&
2231 !(usage & PIPE_BIND_DEPTH_STENCIL))
2232 retval |= PIPE_BIND_LINEAR;
2233
2234 return retval == usage;
2235 }
2236
2237 /*
2238 * framebuffer handling
2239 */
2240
2241 static void si_choose_spi_color_formats(struct si_surface *surf,
2242 unsigned format, unsigned swap,
2243 unsigned ntype, bool is_depth)
2244 {
2245 /* Alpha is needed for alpha-to-coverage.
2246 * Blending may be with or without alpha.
2247 */
2248 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2249 unsigned alpha = 0; /* exports alpha, but may not support blending */
2250 unsigned blend = 0; /* supports blending, but may not export alpha */
2251 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2252
2253 /* Choose the SPI color formats. These are required values for RB+.
2254 * Other chips have multiple choices, though they are not necessarily better.
2255 */
2256 switch (format) {
2257 case V_028C70_COLOR_5_6_5:
2258 case V_028C70_COLOR_1_5_5_5:
2259 case V_028C70_COLOR_5_5_5_1:
2260 case V_028C70_COLOR_4_4_4_4:
2261 case V_028C70_COLOR_10_11_11:
2262 case V_028C70_COLOR_11_11_10:
2263 case V_028C70_COLOR_8:
2264 case V_028C70_COLOR_8_8:
2265 case V_028C70_COLOR_8_8_8_8:
2266 case V_028C70_COLOR_10_10_10_2:
2267 case V_028C70_COLOR_2_10_10_10:
2268 if (ntype == V_028C70_NUMBER_UINT)
2269 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2270 else if (ntype == V_028C70_NUMBER_SINT)
2271 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2272 else
2273 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2274 break;
2275
2276 case V_028C70_COLOR_16:
2277 case V_028C70_COLOR_16_16:
2278 case V_028C70_COLOR_16_16_16_16:
2279 if (ntype == V_028C70_NUMBER_UNORM ||
2280 ntype == V_028C70_NUMBER_SNORM) {
2281 /* UNORM16 and SNORM16 don't support blending */
2282 if (ntype == V_028C70_NUMBER_UNORM)
2283 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2284 else
2285 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2286
2287 /* Use 32 bits per channel for blending. */
2288 if (format == V_028C70_COLOR_16) {
2289 if (swap == V_028C70_SWAP_STD) { /* R */
2290 blend = V_028714_SPI_SHADER_32_R;
2291 blend_alpha = V_028714_SPI_SHADER_32_AR;
2292 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2293 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2294 else
2295 assert(0);
2296 } else if (format == V_028C70_COLOR_16_16) {
2297 if (swap == V_028C70_SWAP_STD) { /* RG */
2298 blend = V_028714_SPI_SHADER_32_GR;
2299 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2300 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2301 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2302 else
2303 assert(0);
2304 } else /* 16_16_16_16 */
2305 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2306 } else if (ntype == V_028C70_NUMBER_UINT)
2307 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2308 else if (ntype == V_028C70_NUMBER_SINT)
2309 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2310 else if (ntype == V_028C70_NUMBER_FLOAT)
2311 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2312 else
2313 assert(0);
2314 break;
2315
2316 case V_028C70_COLOR_32:
2317 if (swap == V_028C70_SWAP_STD) { /* R */
2318 blend = normal = V_028714_SPI_SHADER_32_R;
2319 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2320 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2321 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2322 else
2323 assert(0);
2324 break;
2325
2326 case V_028C70_COLOR_32_32:
2327 if (swap == V_028C70_SWAP_STD) { /* RG */
2328 blend = normal = V_028714_SPI_SHADER_32_GR;
2329 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2330 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2331 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2332 else
2333 assert(0);
2334 break;
2335
2336 case V_028C70_COLOR_32_32_32_32:
2337 case V_028C70_COLOR_8_24:
2338 case V_028C70_COLOR_24_8:
2339 case V_028C70_COLOR_X24_8_32_FLOAT:
2340 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2341 break;
2342
2343 default:
2344 assert(0);
2345 return;
2346 }
2347
2348 /* The DB->CB copy needs 32_ABGR. */
2349 if (is_depth)
2350 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2351
2352 surf->spi_shader_col_format = normal;
2353 surf->spi_shader_col_format_alpha = alpha;
2354 surf->spi_shader_col_format_blend = blend;
2355 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2356 }
2357
2358 static void si_initialize_color_surface(struct si_context *sctx,
2359 struct si_surface *surf)
2360 {
2361 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2362 unsigned color_info, color_attrib;
2363 unsigned format, swap, ntype, endian;
2364 const struct util_format_description *desc;
2365 int firstchan;
2366 unsigned blend_clamp = 0, blend_bypass = 0;
2367
2368 desc = util_format_description(surf->base.format);
2369 for (firstchan = 0; firstchan < 4; firstchan++) {
2370 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2371 break;
2372 }
2373 }
2374 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2375 ntype = V_028C70_NUMBER_FLOAT;
2376 } else {
2377 ntype = V_028C70_NUMBER_UNORM;
2378 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2379 ntype = V_028C70_NUMBER_SRGB;
2380 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2381 if (desc->channel[firstchan].pure_integer) {
2382 ntype = V_028C70_NUMBER_SINT;
2383 } else {
2384 assert(desc->channel[firstchan].normalized);
2385 ntype = V_028C70_NUMBER_SNORM;
2386 }
2387 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2388 if (desc->channel[firstchan].pure_integer) {
2389 ntype = V_028C70_NUMBER_UINT;
2390 } else {
2391 assert(desc->channel[firstchan].normalized);
2392 ntype = V_028C70_NUMBER_UNORM;
2393 }
2394 }
2395 }
2396
2397 format = si_translate_colorformat(surf->base.format);
2398 if (format == V_028C70_COLOR_INVALID) {
2399 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2400 }
2401 assert(format != V_028C70_COLOR_INVALID);
2402 swap = si_translate_colorswap(surf->base.format, false);
2403 endian = si_colorformat_endian_swap(format);
2404
2405 /* blend clamp should be set for all NORM/SRGB types */
2406 if (ntype == V_028C70_NUMBER_UNORM ||
2407 ntype == V_028C70_NUMBER_SNORM ||
2408 ntype == V_028C70_NUMBER_SRGB)
2409 blend_clamp = 1;
2410
2411 /* set blend bypass according to docs if SINT/UINT or
2412 8/24 COLOR variants */
2413 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2414 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2415 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2416 blend_clamp = 0;
2417 blend_bypass = 1;
2418 }
2419
2420 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2421 if (format == V_028C70_COLOR_8 ||
2422 format == V_028C70_COLOR_8_8 ||
2423 format == V_028C70_COLOR_8_8_8_8)
2424 surf->color_is_int8 = true;
2425 else if (format == V_028C70_COLOR_10_10_10_2 ||
2426 format == V_028C70_COLOR_2_10_10_10)
2427 surf->color_is_int10 = true;
2428 }
2429
2430 color_info = S_028C70_FORMAT(format) |
2431 S_028C70_COMP_SWAP(swap) |
2432 S_028C70_BLEND_CLAMP(blend_clamp) |
2433 S_028C70_BLEND_BYPASS(blend_bypass) |
2434 S_028C70_SIMPLE_FLOAT(1) |
2435 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2436 ntype != V_028C70_NUMBER_SNORM &&
2437 ntype != V_028C70_NUMBER_SRGB &&
2438 format != V_028C70_COLOR_8_24 &&
2439 format != V_028C70_COLOR_24_8) |
2440 S_028C70_NUMBER_TYPE(ntype) |
2441 S_028C70_ENDIAN(endian);
2442
2443 /* Intensity is implemented as Red, so treat it that way. */
2444 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2445 util_format_is_intensity(surf->base.format));
2446
2447 if (tex->buffer.b.b.nr_samples > 1) {
2448 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2449 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2450
2451 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2452 S_028C74_NUM_FRAGMENTS(log_fragments);
2453
2454 if (tex->surface.fmask_size) {
2455 color_info |= S_028C70_COMPRESSION(1);
2456 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2457
2458 if (sctx->chip_class == SI) {
2459 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2460 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2461 }
2462 }
2463 }
2464
2465 if (sctx->chip_class >= VI) {
2466 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2467 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2468
2469 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2470 64 for APU because all of our APUs to date use DIMMs which have
2471 a request granularity size of 64B while all other chips have a
2472 32B request size */
2473 if (!sctx->screen->info.has_dedicated_vram)
2474 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2475
2476 if (tex->buffer.b.b.nr_storage_samples > 1) {
2477 if (tex->surface.bpe == 1)
2478 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2479 else if (tex->surface.bpe == 2)
2480 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2481 }
2482
2483 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2484 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2485 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2486 }
2487
2488 /* This must be set for fast clear to work without FMASK. */
2489 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2490 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2491 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2492 }
2493
2494 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2495 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2496
2497 if (sctx->chip_class >= GFX9) {
2498 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2499
2500 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2501 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2502 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2503 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2504 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2505 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2506 }
2507
2508 surf->cb_color_view = color_view;
2509 surf->cb_color_info = color_info;
2510 surf->cb_color_attrib = color_attrib;
2511
2512 /* Determine pixel shader export format */
2513 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2514
2515 surf->color_initialized = true;
2516 }
2517
2518 static void si_init_depth_surface(struct si_context *sctx,
2519 struct si_surface *surf)
2520 {
2521 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2522 unsigned level = surf->base.u.tex.level;
2523 unsigned format, stencil_format;
2524 uint32_t z_info, s_info;
2525
2526 format = si_translate_dbformat(tex->db_render_format);
2527 stencil_format = tex->surface.has_stencil ?
2528 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2529
2530 assert(format != V_028040_Z_INVALID);
2531 if (format == V_028040_Z_INVALID)
2532 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2533
2534 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2535 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2536 surf->db_htile_data_base = 0;
2537 surf->db_htile_surface = 0;
2538
2539 if (sctx->chip_class >= GFX9) {
2540 assert(tex->surface.u.gfx9.surf_offset == 0);
2541 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2542 surf->db_stencil_base = (tex->buffer.gpu_address +
2543 tex->surface.u.gfx9.stencil_offset) >> 8;
2544 z_info = S_028038_FORMAT(format) |
2545 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2546 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2547 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2548 s_info = S_02803C_FORMAT(stencil_format) |
2549 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2550 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2551 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2552 surf->db_depth_view |= S_028008_MIPID(level);
2553 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2554 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2555
2556 if (si_htile_enabled(tex, level)) {
2557 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2558 S_028038_ALLOW_EXPCLEAR(1);
2559
2560 if (tex->tc_compatible_htile) {
2561 unsigned max_zplanes = 4;
2562
2563 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2564 tex->buffer.b.b.nr_samples > 1)
2565 max_zplanes = 2;
2566
2567 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2568 S_028038_ITERATE_FLUSH(1);
2569 s_info |= S_02803C_ITERATE_FLUSH(1);
2570 }
2571
2572 if (tex->surface.has_stencil) {
2573 /* Stencil buffer workaround ported from the SI-CI-VI code.
2574 * See that for explanation.
2575 */
2576 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2577 } else {
2578 /* Use all HTILE for depth if there's no stencil. */
2579 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2580 }
2581
2582 surf->db_htile_data_base = (tex->buffer.gpu_address +
2583 tex->htile_offset) >> 8;
2584 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2585 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2586 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2587 }
2588 } else {
2589 /* SI-CI-VI */
2590 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2591
2592 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2593
2594 surf->db_depth_base = (tex->buffer.gpu_address +
2595 tex->surface.u.legacy.level[level].offset) >> 8;
2596 surf->db_stencil_base = (tex->buffer.gpu_address +
2597 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2598
2599 z_info = S_028040_FORMAT(format) |
2600 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2601 s_info = S_028044_FORMAT(stencil_format);
2602 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2603
2604 if (sctx->chip_class >= CIK) {
2605 struct radeon_info *info = &sctx->screen->info;
2606 unsigned index = tex->surface.u.legacy.tiling_index[level];
2607 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2608 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2609 unsigned tile_mode = info->si_tile_mode_array[index];
2610 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2611 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2612
2613 surf->db_depth_info |=
2614 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2615 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2616 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2617 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2618 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2619 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2620 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2621 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2622 } else {
2623 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2624 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2625 tile_mode_index = si_tile_mode_index(tex, level, true);
2626 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2627 }
2628
2629 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2630 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2631 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2632 levelinfo->nblk_y) / 64 - 1);
2633
2634 if (si_htile_enabled(tex, level)) {
2635 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2636 S_028040_ALLOW_EXPCLEAR(1);
2637
2638 if (tex->surface.has_stencil) {
2639 /* Workaround: For a not yet understood reason, the
2640 * combination of MSAA, fast stencil clear and stencil
2641 * decompress messes with subsequent stencil buffer
2642 * uses. Problem was reproduced on Verde, Bonaire,
2643 * Tonga, and Carrizo.
2644 *
2645 * Disabling EXPCLEAR works around the problem.
2646 *
2647 * Check piglit's arb_texture_multisample-stencil-clear
2648 * test if you want to try changing this.
2649 */
2650 if (tex->buffer.b.b.nr_samples <= 1)
2651 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2652 } else if (!tex->tc_compatible_htile) {
2653 /* Use all of the htile_buffer for depth if there's no stencil.
2654 * This must not be set when TC-compatible HTILE is enabled
2655 * due to a hw bug.
2656 */
2657 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2658 }
2659
2660 surf->db_htile_data_base = (tex->buffer.gpu_address +
2661 tex->htile_offset) >> 8;
2662 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2663
2664 if (tex->tc_compatible_htile) {
2665 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2666
2667 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2668 if (tex->buffer.b.b.nr_samples <= 1)
2669 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2670 else if (tex->buffer.b.b.nr_samples <= 4)
2671 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2672 else
2673 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2674 }
2675 }
2676 }
2677
2678 surf->db_z_info = z_info;
2679 surf->db_stencil_info = s_info;
2680
2681 surf->depth_initialized = true;
2682 }
2683
2684 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2685 {
2686 if (sctx->decompression_enabled)
2687 return;
2688
2689 if (sctx->framebuffer.state.zsbuf) {
2690 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2691 struct si_texture *tex = (struct si_texture *)surf->texture;
2692
2693 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2694
2695 if (tex->surface.has_stencil)
2696 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2697 }
2698
2699 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2700 while (compressed_cb_mask) {
2701 unsigned i = u_bit_scan(&compressed_cb_mask);
2702 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2703 struct si_texture *tex = (struct si_texture*)surf->texture;
2704
2705 if (tex->surface.fmask_size)
2706 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2707 if (tex->dcc_gather_statistics)
2708 tex->separate_dcc_dirty = true;
2709 }
2710 }
2711
2712 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2713 {
2714 for (int i = 0; i < state->nr_cbufs; ++i) {
2715 struct si_surface *surf = NULL;
2716 struct si_texture *tex;
2717
2718 if (!state->cbufs[i])
2719 continue;
2720 surf = (struct si_surface*)state->cbufs[i];
2721 tex = (struct si_texture*)surf->base.texture;
2722
2723 p_atomic_dec(&tex->framebuffers_bound);
2724 }
2725 }
2726
2727 static void si_set_framebuffer_state(struct pipe_context *ctx,
2728 const struct pipe_framebuffer_state *state)
2729 {
2730 struct si_context *sctx = (struct si_context *)ctx;
2731 struct si_surface *surf = NULL;
2732 struct si_texture *tex;
2733 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2734 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2735 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2736 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2737 bool old_has_stencil =
2738 old_has_zsbuf &&
2739 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2740 bool unbound = false;
2741 int i;
2742
2743 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2744 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2745 * We could implement the full workaround here, but it's a useless case.
2746 */
2747 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2748 unreachable("the framebuffer shouldn't have zero area");
2749 return;
2750 }
2751
2752 si_update_fb_dirtiness_after_rendering(sctx);
2753
2754 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2755 if (!sctx->framebuffer.state.cbufs[i])
2756 continue;
2757
2758 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2759 if (tex->dcc_gather_statistics)
2760 vi_separate_dcc_stop_query(sctx, tex);
2761 }
2762
2763 /* Disable DCC if the formats are incompatible. */
2764 for (i = 0; i < state->nr_cbufs; i++) {
2765 if (!state->cbufs[i])
2766 continue;
2767
2768 surf = (struct si_surface*)state->cbufs[i];
2769 tex = (struct si_texture*)surf->base.texture;
2770
2771 if (!surf->dcc_incompatible)
2772 continue;
2773
2774 /* Since the DCC decompression calls back into set_framebuffer-
2775 * _state, we need to unbind the framebuffer, so that
2776 * vi_separate_dcc_stop_query isn't called twice with the same
2777 * color buffer.
2778 */
2779 if (!unbound) {
2780 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2781 unbound = true;
2782 }
2783
2784 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2785 if (!si_texture_disable_dcc(sctx, tex))
2786 si_decompress_dcc(sctx, tex);
2787
2788 surf->dcc_incompatible = false;
2789 }
2790
2791 /* Only flush TC when changing the framebuffer state, because
2792 * the only client not using TC that can change textures is
2793 * the framebuffer.
2794 *
2795 * Wait for compute shaders because of possible transitions:
2796 * - FB write -> shader read
2797 * - shader write -> FB read
2798 *
2799 * DB caches are flushed on demand (using si_decompress_textures).
2800 *
2801 * When MSAA is enabled, CB and TC caches are flushed on demand
2802 * (after FMASK decompression). Shader write -> FB read transitions
2803 * cannot happen for MSAA textures, because MSAA shader images are
2804 * not supported.
2805 *
2806 * Only flush and wait for CB if there is actually a bound color buffer.
2807 */
2808 if (sctx->framebuffer.uncompressed_cb_mask)
2809 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2810 sctx->framebuffer.CB_has_shader_readable_metadata);
2811
2812 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2813
2814 /* u_blitter doesn't invoke depth decompression when it does multiple
2815 * blits in a row, but the only case when it matters for DB is when
2816 * doing generate_mipmap. So here we flush DB manually between
2817 * individual generate_mipmap blits.
2818 * Note that lower mipmap levels aren't compressed.
2819 */
2820 if (sctx->generate_mipmap_for_depth) {
2821 si_make_DB_shader_coherent(sctx, 1, false,
2822 sctx->framebuffer.DB_has_shader_readable_metadata);
2823 } else if (sctx->chip_class == GFX9) {
2824 /* It appears that DB metadata "leaks" in a sequence of:
2825 * - depth clear
2826 * - DCC decompress for shader image writes (with DB disabled)
2827 * - render with DEPTH_BEFORE_SHADER=1
2828 * Flushing DB metadata works around the problem.
2829 */
2830 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2831 }
2832
2833 /* Take the maximum of the old and new count. If the new count is lower,
2834 * dirtying is needed to disable the unbound colorbuffers.
2835 */
2836 sctx->framebuffer.dirty_cbufs |=
2837 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2838 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2839
2840 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2841 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2842
2843 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2844 sctx->framebuffer.spi_shader_col_format = 0;
2845 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2846 sctx->framebuffer.spi_shader_col_format_blend = 0;
2847 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2848 sctx->framebuffer.color_is_int8 = 0;
2849 sctx->framebuffer.color_is_int10 = 0;
2850
2851 sctx->framebuffer.compressed_cb_mask = 0;
2852 sctx->framebuffer.uncompressed_cb_mask = 0;
2853 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2854 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2855 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2856 sctx->framebuffer.any_dst_linear = false;
2857 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2858 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2859 unsigned num_bpp64_colorbufs = 0;
2860
2861 for (i = 0; i < state->nr_cbufs; i++) {
2862 if (!state->cbufs[i])
2863 continue;
2864
2865 surf = (struct si_surface*)state->cbufs[i];
2866 tex = (struct si_texture*)surf->base.texture;
2867
2868 if (!surf->color_initialized) {
2869 si_initialize_color_surface(sctx, surf);
2870 }
2871
2872 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2873 sctx->framebuffer.spi_shader_col_format |=
2874 surf->spi_shader_col_format << (i * 4);
2875 sctx->framebuffer.spi_shader_col_format_alpha |=
2876 surf->spi_shader_col_format_alpha << (i * 4);
2877 sctx->framebuffer.spi_shader_col_format_blend |=
2878 surf->spi_shader_col_format_blend << (i * 4);
2879 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2880 surf->spi_shader_col_format_blend_alpha << (i * 4);
2881
2882 if (surf->color_is_int8)
2883 sctx->framebuffer.color_is_int8 |= 1 << i;
2884 if (surf->color_is_int10)
2885 sctx->framebuffer.color_is_int10 |= 1 << i;
2886
2887 if (tex->surface.fmask_size)
2888 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2889 else
2890 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2891
2892 /* Don't update nr_color_samples for non-AA buffers.
2893 * (e.g. destination of MSAA resolve)
2894 */
2895 if (tex->buffer.b.b.nr_samples >= 2 &&
2896 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2897 sctx->framebuffer.nr_color_samples =
2898 MIN2(sctx->framebuffer.nr_color_samples,
2899 tex->buffer.b.b.nr_storage_samples);
2900 sctx->framebuffer.nr_color_samples =
2901 MAX2(1, sctx->framebuffer.nr_color_samples);
2902 }
2903
2904 if (tex->surface.is_linear)
2905 sctx->framebuffer.any_dst_linear = true;
2906 if (tex->surface.bpe >= 8)
2907 num_bpp64_colorbufs++;
2908
2909 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2910 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2911
2912 si_context_add_resource_size(sctx, surf->base.texture);
2913
2914 p_atomic_inc(&tex->framebuffers_bound);
2915
2916 if (tex->dcc_gather_statistics) {
2917 /* Dirty tracking must be enabled for DCC usage analysis. */
2918 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2919 vi_separate_dcc_start_query(sctx, tex);
2920 }
2921 }
2922
2923 /* For optimal DCC performance. */
2924 if (sctx->chip_class == VI)
2925 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2926 else if (num_bpp64_colorbufs >= 5)
2927 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2928 else
2929 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2930
2931 struct si_texture *zstex = NULL;
2932
2933 if (state->zsbuf) {
2934 surf = (struct si_surface*)state->zsbuf;
2935 zstex = (struct si_texture*)surf->base.texture;
2936
2937 if (!surf->depth_initialized) {
2938 si_init_depth_surface(sctx, surf);
2939 }
2940
2941 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2942 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2943
2944 si_context_add_resource_size(sctx, surf->base.texture);
2945 }
2946
2947 si_update_ps_colorbuf0_slot(sctx);
2948 si_update_poly_offset_state(sctx);
2949 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2950 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2951
2952 if (sctx->screen->dpbb_allowed)
2953 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2954
2955 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2956 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2957
2958 if (sctx->screen->has_out_of_order_rast &&
2959 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2960 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2961 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2962 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2963
2964 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2965 struct pipe_constant_buffer constbuf = {0};
2966
2967 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2968 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2969
2970 constbuf.buffer = sctx->sample_pos_buffer;
2971
2972 /* Set sample locations as fragment shader constants. */
2973 switch (sctx->framebuffer.nr_samples) {
2974 case 1:
2975 constbuf.buffer_offset = 0;
2976 break;
2977 case 2:
2978 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
2979 (ubyte*)sctx->sample_positions.x1;
2980 break;
2981 case 4:
2982 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
2983 (ubyte*)sctx->sample_positions.x1;
2984 break;
2985 case 8:
2986 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
2987 (ubyte*)sctx->sample_positions.x1;
2988 break;
2989 case 16:
2990 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
2991 (ubyte*)sctx->sample_positions.x1;
2992 break;
2993 default:
2994 PRINT_ERR("Requested an invalid number of samples %i.\n",
2995 sctx->framebuffer.nr_samples);
2996 assert(0);
2997 }
2998 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2999 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3000
3001 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3002 }
3003
3004 sctx->do_update_shaders = true;
3005
3006 if (!sctx->decompression_enabled) {
3007 /* Prevent textures decompression when the framebuffer state
3008 * changes come from the decompression passes themselves.
3009 */
3010 sctx->need_check_render_feedback = true;
3011 }
3012 }
3013
3014 static void si_emit_framebuffer_state(struct si_context *sctx)
3015 {
3016 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3017 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3018 unsigned i, nr_cbufs = state->nr_cbufs;
3019 struct si_texture *tex = NULL;
3020 struct si_surface *cb = NULL;
3021 unsigned cb_color_info = 0;
3022
3023 /* Colorbuffers. */
3024 for (i = 0; i < nr_cbufs; i++) {
3025 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3026 unsigned cb_color_attrib;
3027
3028 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3029 continue;
3030
3031 cb = (struct si_surface*)state->cbufs[i];
3032 if (!cb) {
3033 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3034 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3035 continue;
3036 }
3037
3038 tex = (struct si_texture *)cb->base.texture;
3039 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3040 &tex->buffer, RADEON_USAGE_READWRITE,
3041 tex->buffer.b.b.nr_samples > 1 ?
3042 RADEON_PRIO_COLOR_BUFFER_MSAA :
3043 RADEON_PRIO_COLOR_BUFFER);
3044
3045 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3046 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3047 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3048 RADEON_PRIO_SEPARATE_META);
3049 }
3050
3051 if (tex->dcc_separate_buffer)
3052 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3053 tex->dcc_separate_buffer,
3054 RADEON_USAGE_READWRITE,
3055 RADEON_PRIO_SEPARATE_META);
3056
3057 /* Compute mutable surface parameters. */
3058 cb_color_base = tex->buffer.gpu_address >> 8;
3059 cb_color_fmask = 0;
3060 cb_color_cmask = tex->cmask_base_address_reg;
3061 cb_dcc_base = 0;
3062 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3063 cb_color_attrib = cb->cb_color_attrib;
3064
3065 if (cb->base.u.tex.level > 0)
3066 cb_color_info &= C_028C70_FAST_CLEAR;
3067
3068 if (tex->surface.fmask_size) {
3069 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3070 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3071 }
3072
3073 /* Set up DCC. */
3074 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3075 bool is_msaa_resolve_dst = state->cbufs[0] &&
3076 state->cbufs[0]->texture->nr_samples > 1 &&
3077 state->cbufs[1] == &cb->base &&
3078 state->cbufs[1]->texture->nr_samples <= 1;
3079
3080 if (!is_msaa_resolve_dst)
3081 cb_color_info |= S_028C70_DCC_ENABLE(1);
3082
3083 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3084 tex->dcc_offset) >> 8;
3085 cb_dcc_base |= tex->surface.tile_swizzle;
3086 }
3087
3088 if (sctx->chip_class >= GFX9) {
3089 struct gfx9_surf_meta_flags meta;
3090
3091 if (tex->dcc_offset)
3092 meta = tex->surface.u.gfx9.dcc;
3093 else
3094 meta = tex->surface.u.gfx9.cmask;
3095
3096 /* Set mutable surface parameters. */
3097 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3098 cb_color_base |= tex->surface.tile_swizzle;
3099 if (!tex->surface.fmask_size)
3100 cb_color_fmask = cb_color_base;
3101 if (cb->base.u.tex.level > 0)
3102 cb_color_cmask = cb_color_base;
3103 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3104 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3105 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3106 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3107
3108 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3109 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3110 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3111 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3112 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3113 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3114 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3115 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3116 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3117 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3118 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3119 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3120 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3121 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3122 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3123 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3124
3125 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3126 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3127 } else {
3128 /* Compute mutable surface parameters (SI-CI-VI). */
3129 const struct legacy_surf_level *level_info =
3130 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3131 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3132 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3133
3134 cb_color_base += level_info->offset >> 8;
3135 /* Only macrotiled modes can set tile swizzle. */
3136 if (level_info->mode == RADEON_SURF_MODE_2D)
3137 cb_color_base |= tex->surface.tile_swizzle;
3138
3139 if (!tex->surface.fmask_size)
3140 cb_color_fmask = cb_color_base;
3141 if (cb->base.u.tex.level > 0)
3142 cb_color_cmask = cb_color_base;
3143 if (cb_dcc_base)
3144 cb_dcc_base += level_info->dcc_offset >> 8;
3145
3146 pitch_tile_max = level_info->nblk_x / 8 - 1;
3147 slice_tile_max = level_info->nblk_x *
3148 level_info->nblk_y / 64 - 1;
3149 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3150
3151 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3152 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3153 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3154
3155 if (tex->surface.fmask_size) {
3156 if (sctx->chip_class >= CIK)
3157 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3158 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3159 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3160 } else {
3161 /* This must be set for fast clear to work without FMASK. */
3162 if (sctx->chip_class >= CIK)
3163 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3164 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3165 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3166 }
3167
3168 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3169 sctx->chip_class >= VI ? 14 : 13);
3170 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3171 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3172 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3173 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3174 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3175 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3176 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3177 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3178 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3179 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3180 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3181 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3182 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3183
3184 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3185 radeon_emit(cs, cb_dcc_base);
3186 }
3187 }
3188 for (; i < 8 ; i++)
3189 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3190 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3191
3192 /* ZS buffer. */
3193 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3194 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3195 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3196
3197 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3198 &tex->buffer, RADEON_USAGE_READWRITE,
3199 zb->base.texture->nr_samples > 1 ?
3200 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3201 RADEON_PRIO_DEPTH_BUFFER);
3202
3203 if (sctx->chip_class >= GFX9) {
3204 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3205 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3206 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3207 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3208
3209 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3210 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3211 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3212 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3213 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3214 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3215 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3216 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3217 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3218 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3219 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3220 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3221
3222 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3223 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3224 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3225 } else {
3226 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3227
3228 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3229 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3230 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3231 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3232 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3233 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3234 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3235 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3236 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3237 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3238 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3239 }
3240
3241 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3242 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3243 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3244
3245 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3246 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3247 } else if (sctx->framebuffer.dirty_zsbuf) {
3248 if (sctx->chip_class >= GFX9)
3249 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3250 else
3251 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3252
3253 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3254 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3255 }
3256
3257 /* Framebuffer dimensions. */
3258 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3259 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3260 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3261
3262 if (sctx->screen->dfsm_allowed) {
3263 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3264 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3265 }
3266
3267 sctx->framebuffer.dirty_cbufs = 0;
3268 sctx->framebuffer.dirty_zsbuf = false;
3269 }
3270
3271 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3272 {
3273 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3274 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3275 unsigned nr_samples = sctx->framebuffer.nr_samples;
3276 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3277
3278 /* Smoothing (only possible with nr_samples == 1) uses the same
3279 * sample locations as the MSAA it simulates.
3280 */
3281 if (nr_samples <= 1 && sctx->smoothing_enabled)
3282 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3283
3284 /* On Polaris, the small primitive filter uses the sample locations
3285 * even when MSAA is off, so we need to make sure they're set to 0.
3286 */
3287 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3288 nr_samples != sctx->sample_locs_num_samples) {
3289 sctx->sample_locs_num_samples = nr_samples;
3290 si_emit_sample_locations(cs, nr_samples);
3291 }
3292
3293 if (sctx->family >= CHIP_POLARIS10) {
3294 unsigned small_prim_filter_cntl =
3295 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3296 /* line bug */
3297 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3298
3299 /* The alternative of setting sample locations to 0 would
3300 * require a DB flush to avoid Z errors, see
3301 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3302 */
3303 if (has_msaa_sample_loc_bug &&
3304 sctx->framebuffer.nr_samples > 1 &&
3305 !rs->multisample_enable)
3306 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3307
3308 radeon_opt_set_context_reg(sctx,
3309 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3310 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3311 small_prim_filter_cntl);
3312 }
3313
3314 /* The exclusion bits can be set to improve rasterization efficiency
3315 * if no sample lies on the pixel boundary (-8 sample offset).
3316 */
3317 bool exclusion = sctx->chip_class >= CIK &&
3318 (!rs->multisample_enable || nr_samples != 16);
3319 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3320 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3321 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3322 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3323 }
3324
3325 static bool si_out_of_order_rasterization(struct si_context *sctx)
3326 {
3327 struct si_state_blend *blend = sctx->queued.named.blend;
3328 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3329
3330 if (!sctx->screen->has_out_of_order_rast)
3331 return false;
3332
3333 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3334
3335 if (blend) {
3336 colormask &= blend->cb_target_enabled_4bit;
3337 } else {
3338 colormask = 0;
3339 }
3340
3341 /* Conservative: No logic op. */
3342 if (colormask && blend->logicop_enable)
3343 return false;
3344
3345 struct si_dsa_order_invariance dsa_order_invariant = {
3346 .zs = true, .pass_set = true, .pass_last = false
3347 };
3348
3349 if (sctx->framebuffer.state.zsbuf) {
3350 struct si_texture *zstex =
3351 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3352 bool has_stencil = zstex->surface.has_stencil;
3353 dsa_order_invariant = dsa->order_invariance[has_stencil];
3354 if (!dsa_order_invariant.zs)
3355 return false;
3356
3357 /* The set of PS invocations is always order invariant,
3358 * except when early Z/S tests are requested. */
3359 if (sctx->ps_shader.cso &&
3360 sctx->ps_shader.cso->info.writes_memory &&
3361 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3362 !dsa_order_invariant.pass_set)
3363 return false;
3364
3365 if (sctx->num_perfect_occlusion_queries != 0 &&
3366 !dsa_order_invariant.pass_set)
3367 return false;
3368 }
3369
3370 if (!colormask)
3371 return true;
3372
3373 unsigned blendmask = colormask & blend->blend_enable_4bit;
3374
3375 if (blendmask) {
3376 /* Only commutative blending. */
3377 if (blendmask & ~blend->commutative_4bit)
3378 return false;
3379
3380 if (!dsa_order_invariant.pass_set)
3381 return false;
3382 }
3383
3384 if (colormask & ~blendmask) {
3385 if (!dsa_order_invariant.pass_last)
3386 return false;
3387 }
3388
3389 return true;
3390 }
3391
3392 static void si_emit_msaa_config(struct si_context *sctx)
3393 {
3394 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3395 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3396 /* 33% faster rendering to linear color buffers */
3397 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3398 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3399 unsigned sc_mode_cntl_1 =
3400 S_028A4C_WALK_SIZE(dst_is_linear) |
3401 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3402 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3403 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3404 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3405 /* always 1: */
3406 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3407 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3408 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3409 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3410 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3411 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3412 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3413 S_028804_INCOHERENT_EQAA_READS(1) |
3414 S_028804_INTERPOLATE_COMP_Z(1) |
3415 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3416 unsigned coverage_samples, color_samples, z_samples;
3417
3418 /* S: Coverage samples (up to 16x):
3419 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3420 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3421 *
3422 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3423 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3424 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3425 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3426 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3427 * # Z samples).
3428 *
3429 * F: Color samples (up to 8x, must be <= coverage samples):
3430 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3431 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3432 *
3433 * Can be anything between coverage and color samples:
3434 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3435 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3436 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3437 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3438 * # All are currently set the same as coverage samples.
3439 *
3440 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3441 * flag for undefined color samples. A shader-based resolve must handle unknowns
3442 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3443 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3444 * useful. The CB resolve always drops unknowns.
3445 *
3446 * Sensible AA configurations:
3447 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3448 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3449 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3450 * EQAA 8s 8z 8f = 8x MSAA
3451 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3452 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3453 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3454 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3455 * EQAA 4s 4z 4f = 4x MSAA
3456 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3457 * EQAA 2s 2z 2f = 2x MSAA
3458 */
3459 if (sctx->framebuffer.nr_samples > 1) {
3460 coverage_samples = sctx->framebuffer.nr_samples;
3461 color_samples = sctx->framebuffer.nr_color_samples;
3462
3463 if (sctx->framebuffer.state.zsbuf) {
3464 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3465 z_samples = MAX2(1, z_samples);
3466 } else {
3467 z_samples = coverage_samples;
3468 }
3469 } else if (sctx->smoothing_enabled) {
3470 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3471 } else {
3472 coverage_samples = color_samples = z_samples = 1;
3473 }
3474
3475 /* Required by OpenGL line rasterization.
3476 *
3477 * TODO: We should also enable perpendicular endcaps for AA lines,
3478 * but that requires implementing line stippling in the pixel
3479 * shader. SC can only do line stippling with axis-aligned
3480 * endcaps.
3481 */
3482 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3483 unsigned sc_aa_config = 0;
3484
3485 if (coverage_samples > 1) {
3486 /* distance from the pixel center, indexed by log2(nr_samples) */
3487 static unsigned max_dist[] = {
3488 0, /* unused */
3489 4, /* 2x MSAA */
3490 6, /* 4x MSAA */
3491 7, /* 8x MSAA */
3492 8, /* 16x MSAA */
3493 };
3494 unsigned log_samples = util_logbase2(coverage_samples);
3495 unsigned log_z_samples = util_logbase2(z_samples);
3496 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3497 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3498
3499 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3500 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3501 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3502 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3503
3504 if (sctx->framebuffer.nr_samples > 1) {
3505 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3506 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3507 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3508 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3509 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3510 } else if (sctx->smoothing_enabled) {
3511 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3512 }
3513 }
3514
3515 unsigned initial_cdw = cs->current.cdw;
3516
3517 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3518 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3519 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3520 sc_aa_config);
3521 /* R_028804_DB_EQAA */
3522 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3523 db_eqaa);
3524 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3525 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3526 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3527
3528 if (initial_cdw != cs->current.cdw) {
3529 sctx->context_roll_counter++;
3530
3531 /* GFX9: Flush DFSM when the AA mode changes. */
3532 if (sctx->screen->dfsm_allowed) {
3533 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3534 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3535 }
3536 }
3537 }
3538
3539 void si_update_ps_iter_samples(struct si_context *sctx)
3540 {
3541 if (sctx->framebuffer.nr_samples > 1)
3542 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3543 if (sctx->screen->dpbb_allowed)
3544 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3545 }
3546
3547 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3548 {
3549 struct si_context *sctx = (struct si_context *)ctx;
3550
3551 /* The hardware can only do sample shading with 2^n samples. */
3552 min_samples = util_next_power_of_two(min_samples);
3553
3554 if (sctx->ps_iter_samples == min_samples)
3555 return;
3556
3557 sctx->ps_iter_samples = min_samples;
3558 sctx->do_update_shaders = true;
3559
3560 si_update_ps_iter_samples(sctx);
3561 }
3562
3563 /*
3564 * Samplers
3565 */
3566
3567 /**
3568 * Build the sampler view descriptor for a buffer texture.
3569 * @param state 256-bit descriptor; only the high 128 bits are filled in
3570 */
3571 void
3572 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3573 enum pipe_format format,
3574 unsigned offset, unsigned size,
3575 uint32_t *state)
3576 {
3577 const struct util_format_description *desc;
3578 int first_non_void;
3579 unsigned stride;
3580 unsigned num_records;
3581 unsigned num_format, data_format;
3582
3583 desc = util_format_description(format);
3584 first_non_void = util_format_get_first_non_void_channel(format);
3585 stride = desc->block.bits / 8;
3586 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3587 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3588
3589 num_records = size / stride;
3590 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3591
3592 /* The NUM_RECORDS field has a different meaning depending on the chip,
3593 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3594 *
3595 * SI-CIK:
3596 * - If STRIDE == 0, it's in byte units.
3597 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3598 *
3599 * VI:
3600 * - For SMEM and STRIDE == 0, it's in byte units.
3601 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3602 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3603 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3604 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3605 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3606 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3607 * That way the same descriptor can be used by both SMEM and VMEM.
3608 *
3609 * GFX9:
3610 * - For SMEM and STRIDE == 0, it's in byte units.
3611 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3612 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3613 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3614 */
3615 if (screen->info.chip_class >= GFX9)
3616 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3617 * from STRIDE to bytes. This works around it by setting
3618 * NUM_RECORDS to at least the size of one element, so that
3619 * the first element is readable when IDXEN == 0.
3620 *
3621 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3622 * IDXEN is enforced?
3623 */
3624 num_records = num_records ? MAX2(num_records, stride) : 0;
3625 else if (screen->info.chip_class == VI)
3626 num_records *= stride;
3627
3628 state[4] = 0;
3629 state[5] = S_008F04_STRIDE(stride);
3630 state[6] = num_records;
3631 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3632 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3633 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3634 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3635 S_008F0C_NUM_FORMAT(num_format) |
3636 S_008F0C_DATA_FORMAT(data_format);
3637 }
3638
3639 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3640 {
3641 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3642
3643 if (swizzle[3] == PIPE_SWIZZLE_X) {
3644 /* For the pre-defined border color values (white, opaque
3645 * black, transparent black), the only thing that matters is
3646 * that the alpha channel winds up in the correct place
3647 * (because the RGB channels are all the same) so either of
3648 * these enumerations will work.
3649 */
3650 if (swizzle[2] == PIPE_SWIZZLE_Y)
3651 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3652 else
3653 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3654 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3655 if (swizzle[1] == PIPE_SWIZZLE_Y)
3656 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3657 else
3658 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3659 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3660 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3661 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3662 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3663 }
3664
3665 return bc_swizzle;
3666 }
3667
3668 /**
3669 * Build the sampler view descriptor for a texture.
3670 */
3671 void
3672 si_make_texture_descriptor(struct si_screen *screen,
3673 struct si_texture *tex,
3674 bool sampler,
3675 enum pipe_texture_target target,
3676 enum pipe_format pipe_format,
3677 const unsigned char state_swizzle[4],
3678 unsigned first_level, unsigned last_level,
3679 unsigned first_layer, unsigned last_layer,
3680 unsigned width, unsigned height, unsigned depth,
3681 uint32_t *state,
3682 uint32_t *fmask_state)
3683 {
3684 struct pipe_resource *res = &tex->buffer.b.b;
3685 const struct util_format_description *desc;
3686 unsigned char swizzle[4];
3687 int first_non_void;
3688 unsigned num_format, data_format, type, num_samples;
3689 uint64_t va;
3690
3691 desc = util_format_description(pipe_format);
3692
3693 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3694 MAX2(1, res->nr_samples) :
3695 MAX2(1, res->nr_storage_samples);
3696
3697 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3698 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3699 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3700 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3701
3702 switch (pipe_format) {
3703 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3704 case PIPE_FORMAT_X32_S8X24_UINT:
3705 case PIPE_FORMAT_X8Z24_UNORM:
3706 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3707 break;
3708 case PIPE_FORMAT_X24S8_UINT:
3709 /*
3710 * X24S8 is implemented as an 8_8_8_8 data format, to
3711 * fix texture gathers. This affects at least
3712 * GL45-CTS.texture_cube_map_array.sampling on VI.
3713 */
3714 if (screen->info.chip_class <= VI)
3715 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3716 else
3717 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3718 break;
3719 default:
3720 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3721 }
3722 } else {
3723 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3724 }
3725
3726 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3727
3728 switch (pipe_format) {
3729 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3730 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3731 break;
3732 default:
3733 if (first_non_void < 0) {
3734 if (util_format_is_compressed(pipe_format)) {
3735 switch (pipe_format) {
3736 case PIPE_FORMAT_DXT1_SRGB:
3737 case PIPE_FORMAT_DXT1_SRGBA:
3738 case PIPE_FORMAT_DXT3_SRGBA:
3739 case PIPE_FORMAT_DXT5_SRGBA:
3740 case PIPE_FORMAT_BPTC_SRGBA:
3741 case PIPE_FORMAT_ETC2_SRGB8:
3742 case PIPE_FORMAT_ETC2_SRGB8A1:
3743 case PIPE_FORMAT_ETC2_SRGBA8:
3744 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3745 break;
3746 case PIPE_FORMAT_RGTC1_SNORM:
3747 case PIPE_FORMAT_LATC1_SNORM:
3748 case PIPE_FORMAT_RGTC2_SNORM:
3749 case PIPE_FORMAT_LATC2_SNORM:
3750 case PIPE_FORMAT_ETC2_R11_SNORM:
3751 case PIPE_FORMAT_ETC2_RG11_SNORM:
3752 /* implies float, so use SNORM/UNORM to determine
3753 whether data is signed or not */
3754 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3755 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3756 break;
3757 default:
3758 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3759 break;
3760 }
3761 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3762 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3763 } else {
3764 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3765 }
3766 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3767 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3768 } else {
3769 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3770
3771 switch (desc->channel[first_non_void].type) {
3772 case UTIL_FORMAT_TYPE_FLOAT:
3773 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3774 break;
3775 case UTIL_FORMAT_TYPE_SIGNED:
3776 if (desc->channel[first_non_void].normalized)
3777 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3778 else if (desc->channel[first_non_void].pure_integer)
3779 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3780 else
3781 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3782 break;
3783 case UTIL_FORMAT_TYPE_UNSIGNED:
3784 if (desc->channel[first_non_void].normalized)
3785 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3786 else if (desc->channel[first_non_void].pure_integer)
3787 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3788 else
3789 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3790 }
3791 }
3792 }
3793
3794 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3795 if (data_format == ~0) {
3796 data_format = 0;
3797 }
3798
3799 /* S8 with Z32 HTILE needs a special format. */
3800 if (screen->info.chip_class >= GFX9 &&
3801 pipe_format == PIPE_FORMAT_S8_UINT &&
3802 tex->tc_compatible_htile)
3803 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3804
3805 if (!sampler &&
3806 (res->target == PIPE_TEXTURE_CUBE ||
3807 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3808 (screen->info.chip_class <= VI &&
3809 res->target == PIPE_TEXTURE_3D))) {
3810 /* For the purpose of shader images, treat cube maps and 3D
3811 * textures as 2D arrays. For 3D textures, the address
3812 * calculations for mipmaps are different, so we rely on the
3813 * caller to effectively disable mipmaps.
3814 */
3815 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3816
3817 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3818 } else {
3819 type = si_tex_dim(screen, tex, target, num_samples);
3820 }
3821
3822 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3823 height = 1;
3824 depth = res->array_size;
3825 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3826 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3827 if (sampler || res->target != PIPE_TEXTURE_3D)
3828 depth = res->array_size;
3829 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3830 depth = res->array_size / 6;
3831
3832 state[0] = 0;
3833 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3834 S_008F14_NUM_FORMAT_GFX6(num_format));
3835 state[2] = (S_008F18_WIDTH(width - 1) |
3836 S_008F18_HEIGHT(height - 1) |
3837 S_008F18_PERF_MOD(4));
3838 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3839 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3840 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3841 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3842 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3843 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3844 util_logbase2(num_samples) :
3845 last_level) |
3846 S_008F1C_TYPE(type));
3847 state[4] = 0;
3848 state[5] = S_008F24_BASE_ARRAY(first_layer);
3849 state[6] = 0;
3850 state[7] = 0;
3851
3852 if (screen->info.chip_class >= GFX9) {
3853 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3854
3855 /* Depth is the the last accessible layer on Gfx9.
3856 * The hw doesn't need to know the total number of layers.
3857 */
3858 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3859 state[4] |= S_008F20_DEPTH(depth - 1);
3860 else
3861 state[4] |= S_008F20_DEPTH(last_layer);
3862
3863 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3864 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3865 util_logbase2(num_samples) :
3866 tex->buffer.b.b.last_level);
3867 } else {
3868 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3869 state[4] |= S_008F20_DEPTH(depth - 1);
3870 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3871 }
3872
3873 if (tex->dcc_offset) {
3874 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3875 } else {
3876 /* The last dword is unused by hw. The shader uses it to clear
3877 * bits in the first dword of sampler state.
3878 */
3879 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3880 if (first_level == last_level)
3881 state[7] = C_008F30_MAX_ANISO_RATIO;
3882 else
3883 state[7] = 0xffffffff;
3884 }
3885 }
3886
3887 /* Initialize the sampler view for FMASK. */
3888 if (tex->surface.fmask_size) {
3889 uint32_t data_format, num_format;
3890
3891 va = tex->buffer.gpu_address + tex->fmask_offset;
3892
3893 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3894 if (screen->info.chip_class >= GFX9) {
3895 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3896 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3897 case FMASK(2,1):
3898 num_format = V_008F14_IMG_FMASK_8_2_1;
3899 break;
3900 case FMASK(2,2):
3901 num_format = V_008F14_IMG_FMASK_8_2_2;
3902 break;
3903 case FMASK(4,1):
3904 num_format = V_008F14_IMG_FMASK_8_4_1;
3905 break;
3906 case FMASK(4,2):
3907 num_format = V_008F14_IMG_FMASK_8_4_2;
3908 break;
3909 case FMASK(4,4):
3910 num_format = V_008F14_IMG_FMASK_8_4_4;
3911 break;
3912 case FMASK(8,1):
3913 num_format = V_008F14_IMG_FMASK_8_8_1;
3914 break;
3915 case FMASK(8,2):
3916 num_format = V_008F14_IMG_FMASK_16_8_2;
3917 break;
3918 case FMASK(8,4):
3919 num_format = V_008F14_IMG_FMASK_32_8_4;
3920 break;
3921 case FMASK(8,8):
3922 num_format = V_008F14_IMG_FMASK_32_8_8;
3923 break;
3924 case FMASK(16,1):
3925 num_format = V_008F14_IMG_FMASK_16_16_1;
3926 break;
3927 case FMASK(16,2):
3928 num_format = V_008F14_IMG_FMASK_32_16_2;
3929 break;
3930 case FMASK(16,4):
3931 num_format = V_008F14_IMG_FMASK_64_16_4;
3932 break;
3933 case FMASK(16,8):
3934 num_format = V_008F14_IMG_FMASK_64_16_8;
3935 break;
3936 default:
3937 unreachable("invalid nr_samples");
3938 }
3939 } else {
3940 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3941 case FMASK(2,1):
3942 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3943 break;
3944 case FMASK(2,2):
3945 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3946 break;
3947 case FMASK(4,1):
3948 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3949 break;
3950 case FMASK(4,2):
3951 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3952 break;
3953 case FMASK(4,4):
3954 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3955 break;
3956 case FMASK(8,1):
3957 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3958 break;
3959 case FMASK(8,2):
3960 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3961 break;
3962 case FMASK(8,4):
3963 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3964 break;
3965 case FMASK(8,8):
3966 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3967 break;
3968 case FMASK(16,1):
3969 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3970 break;
3971 case FMASK(16,2):
3972 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3973 break;
3974 case FMASK(16,4):
3975 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3976 break;
3977 case FMASK(16,8):
3978 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3979 break;
3980 default:
3981 unreachable("invalid nr_samples");
3982 }
3983 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3984 }
3985 #undef FMASK
3986
3987 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3988 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3989 S_008F14_DATA_FORMAT_GFX6(data_format) |
3990 S_008F14_NUM_FORMAT_GFX6(num_format);
3991 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3992 S_008F18_HEIGHT(height - 1);
3993 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3994 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3995 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3996 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3997 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3998 fmask_state[4] = 0;
3999 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4000 fmask_state[6] = 0;
4001 fmask_state[7] = 0;
4002
4003 if (screen->info.chip_class >= GFX9) {
4004 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4005 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4006 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
4007 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4008 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4009 } else {
4010 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4011 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4012 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4013 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4014 }
4015 }
4016 }
4017
4018 /**
4019 * Create a sampler view.
4020 *
4021 * @param ctx context
4022 * @param texture texture
4023 * @param state sampler view template
4024 * @param width0 width0 override (for compressed textures as int)
4025 * @param height0 height0 override (for compressed textures as int)
4026 * @param force_level set the base address to the level (for compressed textures)
4027 */
4028 struct pipe_sampler_view *
4029 si_create_sampler_view_custom(struct pipe_context *ctx,
4030 struct pipe_resource *texture,
4031 const struct pipe_sampler_view *state,
4032 unsigned width0, unsigned height0,
4033 unsigned force_level)
4034 {
4035 struct si_context *sctx = (struct si_context*)ctx;
4036 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4037 struct si_texture *tex = (struct si_texture*)texture;
4038 unsigned base_level, first_level, last_level;
4039 unsigned char state_swizzle[4];
4040 unsigned height, depth, width;
4041 unsigned last_layer = state->u.tex.last_layer;
4042 enum pipe_format pipe_format;
4043 const struct legacy_surf_level *surflevel;
4044
4045 if (!view)
4046 return NULL;
4047
4048 /* initialize base object */
4049 view->base = *state;
4050 view->base.texture = NULL;
4051 view->base.reference.count = 1;
4052 view->base.context = ctx;
4053
4054 assert(texture);
4055 pipe_resource_reference(&view->base.texture, texture);
4056
4057 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4058 state->format == PIPE_FORMAT_S8X24_UINT ||
4059 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4060 state->format == PIPE_FORMAT_S8_UINT)
4061 view->is_stencil_sampler = true;
4062
4063 /* Buffer resource. */
4064 if (texture->target == PIPE_BUFFER) {
4065 si_make_buffer_descriptor(sctx->screen,
4066 r600_resource(texture),
4067 state->format,
4068 state->u.buf.offset,
4069 state->u.buf.size,
4070 view->state);
4071 return &view->base;
4072 }
4073
4074 state_swizzle[0] = state->swizzle_r;
4075 state_swizzle[1] = state->swizzle_g;
4076 state_swizzle[2] = state->swizzle_b;
4077 state_swizzle[3] = state->swizzle_a;
4078
4079 base_level = 0;
4080 first_level = state->u.tex.first_level;
4081 last_level = state->u.tex.last_level;
4082 width = width0;
4083 height = height0;
4084 depth = texture->depth0;
4085
4086 if (sctx->chip_class <= VI && force_level) {
4087 assert(force_level == first_level &&
4088 force_level == last_level);
4089 base_level = force_level;
4090 first_level = 0;
4091 last_level = 0;
4092 width = u_minify(width, force_level);
4093 height = u_minify(height, force_level);
4094 depth = u_minify(depth, force_level);
4095 }
4096
4097 /* This is not needed if state trackers set last_layer correctly. */
4098 if (state->target == PIPE_TEXTURE_1D ||
4099 state->target == PIPE_TEXTURE_2D ||
4100 state->target == PIPE_TEXTURE_RECT ||
4101 state->target == PIPE_TEXTURE_CUBE)
4102 last_layer = state->u.tex.first_layer;
4103
4104 /* Texturing with separate depth and stencil. */
4105 pipe_format = state->format;
4106
4107 /* Depth/stencil texturing sometimes needs separate texture. */
4108 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4109 if (!tex->flushed_depth_texture &&
4110 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4111 pipe_resource_reference(&view->base.texture, NULL);
4112 FREE(view);
4113 return NULL;
4114 }
4115
4116 assert(tex->flushed_depth_texture);
4117
4118 /* Override format for the case where the flushed texture
4119 * contains only Z or only S.
4120 */
4121 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4122 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4123
4124 tex = tex->flushed_depth_texture;
4125 }
4126
4127 surflevel = tex->surface.u.legacy.level;
4128
4129 if (tex->db_compatible) {
4130 if (!view->is_stencil_sampler)
4131 pipe_format = tex->db_render_format;
4132
4133 switch (pipe_format) {
4134 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4135 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4136 break;
4137 case PIPE_FORMAT_X8Z24_UNORM:
4138 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4139 /* Z24 is always stored like this for DB
4140 * compatibility.
4141 */
4142 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4143 break;
4144 case PIPE_FORMAT_X24S8_UINT:
4145 case PIPE_FORMAT_S8X24_UINT:
4146 case PIPE_FORMAT_X32_S8X24_UINT:
4147 pipe_format = PIPE_FORMAT_S8_UINT;
4148 surflevel = tex->surface.u.legacy.stencil_level;
4149 break;
4150 default:;
4151 }
4152 }
4153
4154 view->dcc_incompatible =
4155 vi_dcc_formats_are_incompatible(texture,
4156 state->u.tex.first_level,
4157 state->format);
4158
4159 si_make_texture_descriptor(sctx->screen, tex, true,
4160 state->target, pipe_format, state_swizzle,
4161 first_level, last_level,
4162 state->u.tex.first_layer, last_layer,
4163 width, height, depth,
4164 view->state, view->fmask_state);
4165
4166 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4167 view->is_integer =
4168 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4169 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4170 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4171 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4172 view->base_level_info = &surflevel[base_level];
4173 view->base_level = base_level;
4174 view->block_width = util_format_get_blockwidth(pipe_format);
4175 return &view->base;
4176 }
4177
4178 static struct pipe_sampler_view *
4179 si_create_sampler_view(struct pipe_context *ctx,
4180 struct pipe_resource *texture,
4181 const struct pipe_sampler_view *state)
4182 {
4183 return si_create_sampler_view_custom(ctx, texture, state,
4184 texture ? texture->width0 : 0,
4185 texture ? texture->height0 : 0, 0);
4186 }
4187
4188 static void si_sampler_view_destroy(struct pipe_context *ctx,
4189 struct pipe_sampler_view *state)
4190 {
4191 struct si_sampler_view *view = (struct si_sampler_view *)state;
4192
4193 pipe_resource_reference(&state->texture, NULL);
4194 FREE(view);
4195 }
4196
4197 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4198 {
4199 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4200 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4201 (linear_filter &&
4202 (wrap == PIPE_TEX_WRAP_CLAMP ||
4203 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4204 }
4205
4206 static uint32_t si_translate_border_color(struct si_context *sctx,
4207 const struct pipe_sampler_state *state,
4208 const union pipe_color_union *color,
4209 bool is_integer)
4210 {
4211 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4212 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4213
4214 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4215 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4216 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4217 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4218
4219 #define simple_border_types(elt) \
4220 do { \
4221 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4222 color->elt[2] == 0 && color->elt[3] == 0) \
4223 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4224 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4225 color->elt[2] == 0 && color->elt[3] == 1) \
4226 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4227 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4228 color->elt[2] == 1 && color->elt[3] == 1) \
4229 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4230 } while (false)
4231
4232 if (is_integer)
4233 simple_border_types(ui);
4234 else
4235 simple_border_types(f);
4236
4237 #undef simple_border_types
4238
4239 int i;
4240
4241 /* Check if the border has been uploaded already. */
4242 for (i = 0; i < sctx->border_color_count; i++)
4243 if (memcmp(&sctx->border_color_table[i], color,
4244 sizeof(*color)) == 0)
4245 break;
4246
4247 if (i >= SI_MAX_BORDER_COLORS) {
4248 /* Getting 4096 unique border colors is very unlikely. */
4249 fprintf(stderr, "radeonsi: The border color table is full. "
4250 "Any new border colors will be just black. "
4251 "Please file a bug.\n");
4252 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4253 }
4254
4255 if (i == sctx->border_color_count) {
4256 /* Upload a new border color. */
4257 memcpy(&sctx->border_color_table[i], color,
4258 sizeof(*color));
4259 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4260 color, sizeof(*color));
4261 sctx->border_color_count++;
4262 }
4263
4264 return S_008F3C_BORDER_COLOR_PTR(i) |
4265 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4266 }
4267
4268 static inline int S_FIXED(float value, unsigned frac_bits)
4269 {
4270 return value * (1 << frac_bits);
4271 }
4272
4273 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4274 {
4275 if (filter == PIPE_TEX_FILTER_LINEAR)
4276 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4277 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4278 else
4279 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4280 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4281 }
4282
4283 static inline unsigned si_tex_aniso_filter(unsigned filter)
4284 {
4285 if (filter < 2)
4286 return 0;
4287 if (filter < 4)
4288 return 1;
4289 if (filter < 8)
4290 return 2;
4291 if (filter < 16)
4292 return 3;
4293 return 4;
4294 }
4295
4296 static void *si_create_sampler_state(struct pipe_context *ctx,
4297 const struct pipe_sampler_state *state)
4298 {
4299 struct si_context *sctx = (struct si_context *)ctx;
4300 struct si_screen *sscreen = sctx->screen;
4301 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4302 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4303 : state->max_anisotropy;
4304 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4305 union pipe_color_union clamped_border_color;
4306
4307 if (!rstate) {
4308 return NULL;
4309 }
4310
4311 #ifdef DEBUG
4312 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4313 #endif
4314 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4315 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4316 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4317 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4318 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4319 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4320 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4321 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4322 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4323 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4324 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4325 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4326 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4327 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4328 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4329 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4330 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4331 S_008F38_MIP_POINT_PRECLAMP(0) |
4332 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4333 S_008F38_FILTER_PREC_FIX(1) |
4334 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4335 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4336
4337 /* Create sampler resource for integer textures. */
4338 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4339 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4340
4341 /* Create sampler resource for upgraded depth textures. */
4342 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4343
4344 for (unsigned i = 0; i < 4; ++i) {
4345 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4346 * when the border color is 1.0. */
4347 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4348 }
4349
4350 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4351 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4352 else
4353 rstate->upgraded_depth_val[3] =
4354 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4355 S_008F3C_UPGRADED_DEPTH(1);
4356
4357 return rstate;
4358 }
4359
4360 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4361 {
4362 struct si_context *sctx = (struct si_context *)ctx;
4363
4364 if (sctx->sample_mask == (uint16_t)sample_mask)
4365 return;
4366
4367 sctx->sample_mask = sample_mask;
4368 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4369 }
4370
4371 static void si_emit_sample_mask(struct si_context *sctx)
4372 {
4373 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4374 unsigned mask = sctx->sample_mask;
4375
4376 /* Needed for line and polygon smoothing as well as for the Polaris
4377 * small primitive filter. We expect the state tracker to take care of
4378 * this for us.
4379 */
4380 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4381 (mask & 1 && sctx->blitter->running));
4382
4383 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4384 radeon_emit(cs, mask | (mask << 16));
4385 radeon_emit(cs, mask | (mask << 16));
4386 }
4387
4388 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4389 {
4390 #ifdef DEBUG
4391 struct si_sampler_state *s = state;
4392
4393 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4394 s->magic = 0;
4395 #endif
4396 free(state);
4397 }
4398
4399 /*
4400 * Vertex elements & buffers
4401 */
4402
4403 struct util_fast_udiv_info32 {
4404 unsigned multiplier; /* the "magic number" multiplier */
4405 unsigned pre_shift; /* shift for the dividend before multiplying */
4406 unsigned post_shift; /* shift for the dividend after multiplying */
4407 int increment; /* 0 or 1; if set then increment the numerator, using one of
4408 the two strategies */
4409 };
4410
4411 static struct util_fast_udiv_info32
4412 util_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4413 {
4414 struct util_fast_udiv_info info =
4415 util_compute_fast_udiv_info(D, num_bits, 32);
4416
4417 struct util_fast_udiv_info32 result = {
4418 info.multiplier,
4419 info.pre_shift,
4420 info.post_shift,
4421 info.increment,
4422 };
4423 return result;
4424 }
4425
4426 static void *si_create_vertex_elements(struct pipe_context *ctx,
4427 unsigned count,
4428 const struct pipe_vertex_element *elements)
4429 {
4430 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4431 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4432 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4433 struct util_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4434 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32) == 16);
4435 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4436 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4437 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4438 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4439 int i;
4440
4441 assert(count <= SI_MAX_ATTRIBS);
4442 if (!v)
4443 return NULL;
4444
4445 v->count = count;
4446 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4447
4448 for (i = 0; i < count; ++i) {
4449 const struct util_format_description *desc;
4450 const struct util_format_channel_description *channel;
4451 unsigned data_format, num_format;
4452 int first_non_void;
4453 unsigned vbo_index = elements[i].vertex_buffer_index;
4454 unsigned char swizzle[4];
4455
4456 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4457 FREE(v);
4458 return NULL;
4459 }
4460
4461 unsigned instance_divisor = elements[i].instance_divisor;
4462 if (instance_divisor) {
4463 v->uses_instance_divisors = true;
4464
4465 if (instance_divisor == 1) {
4466 v->instance_divisor_is_one |= 1u << i;
4467 } else {
4468 v->instance_divisor_is_fetched |= 1u << i;
4469 divisor_factors[i] =
4470 util_compute_fast_udiv_info32(instance_divisor, 32);
4471 }
4472 }
4473
4474 if (!used[vbo_index]) {
4475 v->first_vb_use_mask |= 1 << i;
4476 used[vbo_index] = true;
4477 }
4478
4479 desc = util_format_description(elements[i].src_format);
4480 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4481 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4482 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4483 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4484 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4485
4486 v->format_size[i] = desc->block.bits / 8;
4487 v->src_offset[i] = elements[i].src_offset;
4488 v->vertex_buffer_index[i] = vbo_index;
4489
4490 /* The hardware always treats the 2-bit alpha channel as
4491 * unsigned, so a shader workaround is needed. The affected
4492 * chips are VI and older except Stoney (GFX8.1).
4493 */
4494 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4495 sscreen->info.chip_class <= VI &&
4496 sscreen->info.family != CHIP_STONEY) {
4497 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4498 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4499 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4500 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4501 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4502 /* This isn't actually used in OpenGL. */
4503 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4504 }
4505 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4506 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4507 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4508 else
4509 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4510 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4511 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4512 if (channel->normalized) {
4513 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4514 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4515 else
4516 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4517 } else {
4518 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4519 }
4520 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4521 if (channel->normalized) {
4522 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4523 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4524 else
4525 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4526 } else {
4527 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4528 }
4529 }
4530 } else if (channel && channel->size == 64 &&
4531 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4532 switch (desc->nr_channels) {
4533 case 1:
4534 case 2:
4535 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4536 swizzle[0] = PIPE_SWIZZLE_X;
4537 swizzle[1] = PIPE_SWIZZLE_Y;
4538 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4539 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4540 break;
4541 case 3:
4542 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4543 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4544 swizzle[1] = PIPE_SWIZZLE_Y;
4545 swizzle[2] = PIPE_SWIZZLE_0;
4546 swizzle[3] = PIPE_SWIZZLE_0;
4547 break;
4548 case 4:
4549 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4550 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4551 swizzle[1] = PIPE_SWIZZLE_Y;
4552 swizzle[2] = PIPE_SWIZZLE_Z;
4553 swizzle[3] = PIPE_SWIZZLE_W;
4554 break;
4555 default:
4556 assert(0);
4557 }
4558 } else if (channel && desc->nr_channels == 3) {
4559 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4560
4561 if (channel->size == 8) {
4562 if (channel->pure_integer)
4563 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4564 else
4565 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4566 } else if (channel->size == 16) {
4567 if (channel->pure_integer)
4568 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4569 else
4570 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4571 }
4572 }
4573
4574 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4575 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4576 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4577 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4578 S_008F0C_NUM_FORMAT(num_format) |
4579 S_008F0C_DATA_FORMAT(data_format);
4580 }
4581
4582 if (v->instance_divisor_is_fetched) {
4583 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4584
4585 v->instance_divisor_factor_buffer =
4586 (struct r600_resource*)
4587 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4588 num_divisors * sizeof(divisor_factors[0]));
4589 if (!v->instance_divisor_factor_buffer) {
4590 FREE(v);
4591 return NULL;
4592 }
4593 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4594 NULL, PIPE_TRANSFER_WRITE);
4595 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4596 }
4597 return v;
4598 }
4599
4600 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4601 {
4602 struct si_context *sctx = (struct si_context *)ctx;
4603 struct si_vertex_elements *old = sctx->vertex_elements;
4604 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4605
4606 sctx->vertex_elements = v;
4607 sctx->vertex_buffers_dirty = true;
4608
4609 if (v &&
4610 (!old ||
4611 old->count != v->count ||
4612 old->uses_instance_divisors != v->uses_instance_divisors ||
4613 v->uses_instance_divisors || /* we don't check which divisors changed */
4614 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4615 sctx->do_update_shaders = true;
4616
4617 if (v && v->instance_divisor_is_fetched) {
4618 struct pipe_constant_buffer cb;
4619
4620 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4621 cb.user_buffer = NULL;
4622 cb.buffer_offset = 0;
4623 cb.buffer_size = 0xffffffff;
4624 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4625 }
4626 }
4627
4628 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4629 {
4630 struct si_context *sctx = (struct si_context *)ctx;
4631 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4632
4633 if (sctx->vertex_elements == state)
4634 sctx->vertex_elements = NULL;
4635 r600_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4636 FREE(state);
4637 }
4638
4639 static void si_set_vertex_buffers(struct pipe_context *ctx,
4640 unsigned start_slot, unsigned count,
4641 const struct pipe_vertex_buffer *buffers)
4642 {
4643 struct si_context *sctx = (struct si_context *)ctx;
4644 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4645 int i;
4646
4647 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4648
4649 if (buffers) {
4650 for (i = 0; i < count; i++) {
4651 const struct pipe_vertex_buffer *src = buffers + i;
4652 struct pipe_vertex_buffer *dsti = dst + i;
4653 struct pipe_resource *buf = src->buffer.resource;
4654
4655 pipe_resource_reference(&dsti->buffer.resource, buf);
4656 dsti->buffer_offset = src->buffer_offset;
4657 dsti->stride = src->stride;
4658 si_context_add_resource_size(sctx, buf);
4659 if (buf)
4660 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4661 }
4662 } else {
4663 for (i = 0; i < count; i++) {
4664 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4665 }
4666 }
4667 sctx->vertex_buffers_dirty = true;
4668 }
4669
4670 /*
4671 * Misc
4672 */
4673
4674 static void si_set_tess_state(struct pipe_context *ctx,
4675 const float default_outer_level[4],
4676 const float default_inner_level[2])
4677 {
4678 struct si_context *sctx = (struct si_context *)ctx;
4679 struct pipe_constant_buffer cb;
4680 float array[8];
4681
4682 memcpy(array, default_outer_level, sizeof(float) * 4);
4683 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4684
4685 cb.buffer = NULL;
4686 cb.user_buffer = NULL;
4687 cb.buffer_size = sizeof(array);
4688
4689 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4690 (void*)array, sizeof(array),
4691 &cb.buffer_offset);
4692
4693 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4694 pipe_resource_reference(&cb.buffer, NULL);
4695 }
4696
4697 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4698 {
4699 struct si_context *sctx = (struct si_context *)ctx;
4700
4701 si_update_fb_dirtiness_after_rendering(sctx);
4702
4703 /* Multisample surfaces are flushed in si_decompress_textures. */
4704 if (sctx->framebuffer.uncompressed_cb_mask)
4705 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4706 sctx->framebuffer.CB_has_shader_readable_metadata);
4707 }
4708
4709 /* This only ensures coherency for shader image/buffer stores. */
4710 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4711 {
4712 struct si_context *sctx = (struct si_context *)ctx;
4713
4714 /* Subsequent commands must wait for all shader invocations to
4715 * complete. */
4716 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4717 SI_CONTEXT_CS_PARTIAL_FLUSH;
4718
4719 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4720 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4721 SI_CONTEXT_INV_VMEM_L1;
4722
4723 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4724 PIPE_BARRIER_SHADER_BUFFER |
4725 PIPE_BARRIER_TEXTURE |
4726 PIPE_BARRIER_IMAGE |
4727 PIPE_BARRIER_STREAMOUT_BUFFER |
4728 PIPE_BARRIER_GLOBAL_BUFFER)) {
4729 /* As far as I can tell, L1 contents are written back to L2
4730 * automatically at end of shader, but the contents of other
4731 * L1 caches might still be stale. */
4732 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4733 }
4734
4735 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4736 /* Indices are read through TC L2 since VI.
4737 * L1 isn't used.
4738 */
4739 if (sctx->screen->info.chip_class <= CIK)
4740 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4741 }
4742
4743 /* MSAA color, any depth and any stencil are flushed in
4744 * si_decompress_textures when needed.
4745 */
4746 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4747 sctx->framebuffer.uncompressed_cb_mask) {
4748 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4749
4750 if (sctx->chip_class <= VI)
4751 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4752 }
4753
4754 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4755 if (sctx->screen->info.chip_class <= VI &&
4756 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4757 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4758 }
4759
4760 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4761 {
4762 struct pipe_blend_state blend;
4763
4764 memset(&blend, 0, sizeof(blend));
4765 blend.independent_blend_enable = true;
4766 blend.rt[0].colormask = 0xf;
4767 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4768 }
4769
4770 static void si_init_config(struct si_context *sctx);
4771
4772 void si_init_state_functions(struct si_context *sctx)
4773 {
4774 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4775 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4776 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4777 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4778 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4779 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4780 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4781 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4782 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4783 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4784 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4785
4786 sctx->b.create_blend_state = si_create_blend_state;
4787 sctx->b.bind_blend_state = si_bind_blend_state;
4788 sctx->b.delete_blend_state = si_delete_blend_state;
4789 sctx->b.set_blend_color = si_set_blend_color;
4790
4791 sctx->b.create_rasterizer_state = si_create_rs_state;
4792 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4793 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4794
4795 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4796 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4797 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4798
4799 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4800 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4801 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4802 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4803 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4804
4805 sctx->b.set_clip_state = si_set_clip_state;
4806 sctx->b.set_stencil_ref = si_set_stencil_ref;
4807
4808 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4809
4810 sctx->b.create_sampler_state = si_create_sampler_state;
4811 sctx->b.delete_sampler_state = si_delete_sampler_state;
4812
4813 sctx->b.create_sampler_view = si_create_sampler_view;
4814 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4815
4816 sctx->b.set_sample_mask = si_set_sample_mask;
4817
4818 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4819 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4820 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4821 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4822
4823 sctx->b.texture_barrier = si_texture_barrier;
4824 sctx->b.memory_barrier = si_memory_barrier;
4825 sctx->b.set_min_samples = si_set_min_samples;
4826 sctx->b.set_tess_state = si_set_tess_state;
4827
4828 sctx->b.set_active_query_state = si_set_active_query_state;
4829
4830 sctx->b.draw_vbo = si_draw_vbo;
4831
4832 si_init_config(sctx);
4833 }
4834
4835 void si_init_screen_state_functions(struct si_screen *sscreen)
4836 {
4837 sscreen->b.is_format_supported = si_is_format_supported;
4838 }
4839
4840 static void si_set_grbm_gfx_index(struct si_context *sctx,
4841 struct si_pm4_state *pm4, unsigned value)
4842 {
4843 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4844 R_00802C_GRBM_GFX_INDEX;
4845 si_pm4_set_reg(pm4, reg, value);
4846 }
4847
4848 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4849 struct si_pm4_state *pm4, unsigned se)
4850 {
4851 assert(se == ~0 || se < sctx->screen->info.max_se);
4852 si_set_grbm_gfx_index(sctx, pm4,
4853 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4854 S_030800_SE_INDEX(se)) |
4855 S_030800_SH_BROADCAST_WRITES(1) |
4856 S_030800_INSTANCE_BROADCAST_WRITES(1));
4857 }
4858
4859 static void
4860 si_write_harvested_raster_configs(struct si_context *sctx,
4861 struct si_pm4_state *pm4,
4862 unsigned raster_config,
4863 unsigned raster_config_1)
4864 {
4865 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4866 unsigned raster_config_se[4];
4867 unsigned se;
4868
4869 ac_get_harvested_configs(&sctx->screen->info,
4870 raster_config,
4871 &raster_config_1,
4872 raster_config_se);
4873
4874 for (se = 0; se < num_se; se++) {
4875 si_set_grbm_gfx_index_se(sctx, pm4, se);
4876 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4877 }
4878 si_set_grbm_gfx_index(sctx, pm4, ~0);
4879
4880 if (sctx->chip_class >= CIK) {
4881 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4882 }
4883 }
4884
4885 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4886 {
4887 struct si_screen *sscreen = sctx->screen;
4888 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4889 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4890 unsigned raster_config = sscreen->pa_sc_raster_config;
4891 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4892
4893 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4894 /* Always use the default config when all backends are enabled
4895 * (or when we failed to determine the enabled backends).
4896 */
4897 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4898 raster_config);
4899 if (sctx->chip_class >= CIK)
4900 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4901 raster_config_1);
4902 } else {
4903 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4904 }
4905 }
4906
4907 static void si_init_config(struct si_context *sctx)
4908 {
4909 struct si_screen *sscreen = sctx->screen;
4910 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4911 bool has_clear_state = sscreen->has_clear_state;
4912 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4913
4914 /* SI, radeon kernel disabled CLEAR_STATE. */
4915 assert(has_clear_state || sscreen->info.chip_class == SI ||
4916 sscreen->info.drm_major != 3);
4917
4918 if (!pm4)
4919 return;
4920
4921 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4922 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4923 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4924 si_pm4_cmd_end(pm4, false);
4925
4926 if (has_clear_state) {
4927 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4928 si_pm4_cmd_add(pm4, 0);
4929 si_pm4_cmd_end(pm4, false);
4930 }
4931
4932 if (sctx->chip_class <= VI)
4933 si_set_raster_config(sctx, pm4);
4934
4935 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4936 if (!has_clear_state)
4937 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4938
4939 /* FIXME calculate these values somehow ??? */
4940 if (sctx->chip_class <= VI) {
4941 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4942 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4943 }
4944
4945 if (!has_clear_state) {
4946 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4947 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4948 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4949 }
4950
4951 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4952 if (!has_clear_state)
4953 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4954 if (sctx->chip_class < CIK)
4955 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4956 S_008A14_CLIP_VTX_REORDER_ENA(1));
4957
4958 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4959 * I don't know why. Deduced by trial and error.
4960 */
4961 if (sctx->chip_class <= CIK) {
4962 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4963 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4964 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4965 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4966 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4967 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4968 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4969 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4970 }
4971
4972 if (!has_clear_state) {
4973 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4974 S_028230_ER_TRI(0xA) |
4975 S_028230_ER_POINT(0xA) |
4976 S_028230_ER_RECT(0xA) |
4977 /* Required by DX10_DIAMOND_TEST_ENA: */
4978 S_028230_ER_LINE_LR(0x1A) |
4979 S_028230_ER_LINE_RL(0x26) |
4980 S_028230_ER_LINE_TB(0xA) |
4981 S_028230_ER_LINE_BT(0xA));
4982 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4983 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4984 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4985 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4986 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4987 }
4988
4989 if (sctx->chip_class >= GFX9) {
4990 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4991 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4992 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4993 } else {
4994 /* These registers, when written, also overwrite the CLEAR_STATE
4995 * context, so we can't rely on CLEAR_STATE setting them.
4996 * It would be an issue if there was another UMD changing them.
4997 */
4998 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4999 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5000 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5001 }
5002
5003 if (sctx->chip_class >= CIK) {
5004 if (sctx->chip_class >= GFX9) {
5005 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5006 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5007 } else {
5008 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5009 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5010 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5011 S_00B41C_WAVE_LIMIT(0x3F));
5012 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5013 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5014
5015 /* If this is 0, Bonaire can hang even if GS isn't being used.
5016 * Other chips are unaffected. These are suboptimal values,
5017 * but we don't use on-chip GS.
5018 */
5019 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5020 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5021 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5022 }
5023 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5024 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5025
5026 /* Compute LATE_ALLOC_VS.LIMIT. */
5027 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5028 unsigned late_alloc_limit; /* The limit is per SH. */
5029
5030 if (sctx->family == CHIP_KABINI) {
5031 late_alloc_limit = 0; /* Potential hang on Kabini. */
5032 } else if (num_cu_per_sh <= 4) {
5033 /* Too few available compute units per SH. Disallowing
5034 * VS to run on one CU could hurt us more than late VS
5035 * allocation would help.
5036 *
5037 * 2 is the highest safe number that allows us to keep
5038 * all CUs enabled.
5039 */
5040 late_alloc_limit = 2;
5041 } else {
5042 /* This is a good initial value, allowing 1 late_alloc
5043 * wave per SIMD on num_cu - 2.
5044 */
5045 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5046
5047 /* The limit is 0-based, so 0 means 1. */
5048 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5049 late_alloc_limit -= 1;
5050 }
5051
5052 /* VS can't execute on one CU if the limit is > 2. */
5053 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5054 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5055 S_00B118_WAVE_LIMIT(0x3F));
5056 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5057 S_00B11C_LIMIT(late_alloc_limit));
5058 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5059 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5060 }
5061
5062 if (sctx->chip_class >= VI) {
5063 unsigned vgt_tess_distribution;
5064
5065 vgt_tess_distribution =
5066 S_028B50_ACCUM_ISOLINE(32) |
5067 S_028B50_ACCUM_TRI(11) |
5068 S_028B50_ACCUM_QUAD(11) |
5069 S_028B50_DONUT_SPLIT(16);
5070
5071 /* Testing with Unigine Heaven extreme tesselation yielded best results
5072 * with TRAP_SPLIT = 3.
5073 */
5074 if (sctx->family == CHIP_FIJI ||
5075 sctx->family >= CHIP_POLARIS10)
5076 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5077
5078 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5079 } else if (!has_clear_state) {
5080 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5081 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5082 }
5083
5084 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5085 if (sctx->chip_class >= CIK) {
5086 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5087 S_028084_ADDRESS(border_color_va >> 40));
5088 }
5089 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5090 RADEON_PRIO_BORDER_COLORS);
5091
5092 if (sctx->chip_class >= GFX9) {
5093 unsigned num_se = sscreen->info.max_se;
5094 unsigned pc_lines = 0;
5095
5096 switch (sctx->family) {
5097 case CHIP_VEGA10:
5098 case CHIP_VEGA12:
5099 case CHIP_VEGA20:
5100 pc_lines = 4096;
5101 break;
5102 case CHIP_RAVEN:
5103 pc_lines = 1024;
5104 break;
5105 default:
5106 assert(0);
5107 }
5108
5109 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5110 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5111 S_028C48_MAX_PRIM_PER_BATCH(1023));
5112 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5113 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5114 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5115 }
5116
5117 si_pm4_upload_indirect_buffer(sctx, pm4);
5118 sctx->init_config = pm4;
5119 }