projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: implement glDrawTransformFeedback functionality
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528
529 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
530 state->fill_back != PIPE_POLYGON_MODE_FILL);
531
532 if (state->flatshade_first)
533 prov_vtx = 0;
534
535 rs->flatshade = state->flatshade;
536 rs->sprite_coord_enable = state->sprite_coord_enable;
537 rs->pa_sc_line_stipple = state->line_stipple_enable ?
538 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
539 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
540 rs->pa_su_sc_mode_cntl =
541 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
542 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
543 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
548 S_028814_POLY_MODE(polygon_dual_mode) |
549 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
551 rs->pa_cl_clip_cntl =
552 S_028810_PS_UCP_MODE(3) |
553 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
554 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
555 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
556 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
557
558 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
559
560 /* offset */
561 rs->offset_units = state->offset_units;
562 rs->offset_scale = state->offset_scale * 12.0f;
563
564 tmp = S_0286D4_FLAT_SHADE_ENA(1);
565 if (state->sprite_coord_enable) {
566 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
567 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
568 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
569 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
570 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
571 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
572 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
573 }
574 }
575 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
576
577 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
578 /* point size 12.4 fixed point */
579 tmp = (unsigned)(state->point_size * 8.0);
580 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
581
582 if (state->point_size_per_vertex) {
583 psize_min = util_get_min_point_size(state);
584 psize_max = 8192;
585 } else {
586 /* Force the point size to be as if the vertex output was disabled. */
587 psize_min = state->point_size;
588 psize_max = state->point_size;
589 }
590 /* Divide by two, because 0.5 = 1 pixel. */
591 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
592 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
593 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
594
595 tmp = (unsigned)state->line_width * 8;
596 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
597 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
598 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
599 S_028A48_MSAA_ENABLE(state->multisample));
600
601 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
602 S_028BE4_PIX_CENTER(state->half_pixel_center) |
603 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
604 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
605 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
608
609 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
610 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
611
612 return rs;
613 }
614
615 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
616 {
617 struct r600_context *rctx = (struct r600_context *)ctx;
618 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
619
620 if (state == NULL)
621 return;
622
623 // TODO
624 rctx->sprite_coord_enable = rs->sprite_coord_enable;
625 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
626 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
627
628 si_pm4_bind_state(rctx, rasterizer, rs);
629 si_update_fb_rs_state(rctx);
630 }
631
632 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
633 {
634 struct r600_context *rctx = (struct r600_context *)ctx;
635 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
636 }
637
638 /*
639 * infeered state between dsa and stencil ref
640 */
641 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
642 {
643 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
644 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
645 struct si_state_dsa *dsa = rctx->queued.named.dsa;
646
647 if (pm4 == NULL)
648 return;
649
650 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
651 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
652 S_028430_STENCILMASK(dsa->valuemask[0]) |
653 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
654 S_028430_STENCILOPVAL(1));
655 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
656 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
657 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
658 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
659 S_028434_STENCILOPVAL_BF(1));
660
661 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
662 }
663
664 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
665 const struct pipe_stencil_ref *state)
666 {
667 struct r600_context *rctx = (struct r600_context *)ctx;
668 rctx->stencil_ref = *state;
669 si_update_dsa_stencil_ref(rctx);
670 }
671
672
673 /*
674 * DSA
675 */
676
677 static uint32_t si_translate_stencil_op(int s_op)
678 {
679 switch (s_op) {
680 case PIPE_STENCIL_OP_KEEP:
681 return V_02842C_STENCIL_KEEP;
682 case PIPE_STENCIL_OP_ZERO:
683 return V_02842C_STENCIL_ZERO;
684 case PIPE_STENCIL_OP_REPLACE:
685 return V_02842C_STENCIL_REPLACE_TEST;
686 case PIPE_STENCIL_OP_INCR:
687 return V_02842C_STENCIL_ADD_CLAMP;
688 case PIPE_STENCIL_OP_DECR:
689 return V_02842C_STENCIL_SUB_CLAMP;
690 case PIPE_STENCIL_OP_INCR_WRAP:
691 return V_02842C_STENCIL_ADD_WRAP;
692 case PIPE_STENCIL_OP_DECR_WRAP:
693 return V_02842C_STENCIL_SUB_WRAP;
694 case PIPE_STENCIL_OP_INVERT:
695 return V_02842C_STENCIL_INVERT;
696 default:
697 R600_ERR("Unknown stencil op %d", s_op);
698 assert(0);
699 break;
700 }
701 return 0;
702 }
703
704 static void *si_create_dsa_state(struct pipe_context *ctx,
705 const struct pipe_depth_stencil_alpha_state *state)
706 {
707 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
708 struct si_pm4_state *pm4 = &dsa->pm4;
709 unsigned db_depth_control;
710 unsigned db_render_override, db_render_control;
711 uint32_t db_stencil_control = 0;
712
713 if (dsa == NULL) {
714 return NULL;
715 }
716
717 dsa->valuemask[0] = state->stencil[0].valuemask;
718 dsa->valuemask[1] = state->stencil[1].valuemask;
719 dsa->writemask[0] = state->stencil[0].writemask;
720 dsa->writemask[1] = state->stencil[1].writemask;
721
722 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
723 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
724 S_028800_ZFUNC(state->depth.func);
725
726 /* stencil */
727 if (state->stencil[0].enabled) {
728 db_depth_control |= S_028800_STENCIL_ENABLE(1);
729 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
730 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
731 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
732 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
733
734 if (state->stencil[1].enabled) {
735 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
736 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
737 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
738 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
739 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
740 }
741 }
742
743 /* alpha */
744 if (state->alpha.enabled) {
745 dsa->alpha_func = state->alpha.func;
746 dsa->alpha_ref = state->alpha.ref_value;
747 } else {
748 dsa->alpha_func = PIPE_FUNC_ALWAYS;
749 }
750
751 /* misc */
752 db_render_control = 0;
753 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
754 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
755 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
756 /* TODO db_render_override depends on query */
757 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
758 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
759 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
760 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
761 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
762 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
763 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
764 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
765 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
766 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
767 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
768 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
769 dsa->db_render_override = db_render_override;
770
771 return dsa;
772 }
773
774 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
775 {
776 struct r600_context *rctx = (struct r600_context *)ctx;
777 struct si_state_dsa *dsa = state;
778
779 if (state == NULL)
780 return;
781
782 si_pm4_bind_state(rctx, dsa, dsa);
783 si_update_dsa_stencil_ref(rctx);
784 }
785
786 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
787 {
788 struct r600_context *rctx = (struct r600_context *)ctx;
789 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
790 }
791
792 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
793 bool copy_stencil, int sample)
794 {
795 struct pipe_depth_stencil_alpha_state dsa;
796 struct si_state_dsa *state;
797
798 memset(&dsa, 0, sizeof(dsa));
799
800 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
801 if (copy_depth || copy_stencil) {
802 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
803 S_028000_DEPTH_COPY(copy_depth) |
804 S_028000_STENCIL_COPY(copy_stencil) |
805 S_028000_COPY_CENTROID(1) |
806 S_028000_COPY_SAMPLE(sample));
807 } else {
808 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
809 S_028000_DEPTH_COMPRESS_DISABLE(1) |
810 S_028000_STENCIL_COMPRESS_DISABLE(1));
811 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
812 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
813 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
814 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
815 S_02800C_DISABLE_TILE_RATE_TILES(1));
816 }
817
818 return state;
819 }
820
821 /*
822 * format translation
823 */
824 static uint32_t si_translate_colorformat(enum pipe_format format)
825 {
826 switch (format) {
827 /* 8-bit buffers. */
828 case PIPE_FORMAT_A8_UNORM:
829 case PIPE_FORMAT_A8_SNORM:
830 case PIPE_FORMAT_A8_UINT:
831 case PIPE_FORMAT_A8_SINT:
832 case PIPE_FORMAT_I8_UNORM:
833 case PIPE_FORMAT_I8_SNORM:
834 case PIPE_FORMAT_I8_UINT:
835 case PIPE_FORMAT_I8_SINT:
836 case PIPE_FORMAT_L8_UNORM:
837 case PIPE_FORMAT_L8_SNORM:
838 case PIPE_FORMAT_L8_UINT:
839 case PIPE_FORMAT_L8_SINT:
840 case PIPE_FORMAT_L8_SRGB:
841 case PIPE_FORMAT_R8_UNORM:
842 case PIPE_FORMAT_R8_SNORM:
843 case PIPE_FORMAT_R8_UINT:
844 case PIPE_FORMAT_R8_SINT:
845 return V_028C70_COLOR_8;
846
847 /* 16-bit buffers. */
848 case PIPE_FORMAT_B5G6R5_UNORM:
849 return V_028C70_COLOR_5_6_5;
850
851 case PIPE_FORMAT_B5G5R5A1_UNORM:
852 case PIPE_FORMAT_B5G5R5X1_UNORM:
853 return V_028C70_COLOR_1_5_5_5;
854
855 case PIPE_FORMAT_B4G4R4A4_UNORM:
856 case PIPE_FORMAT_B4G4R4X4_UNORM:
857 return V_028C70_COLOR_4_4_4_4;
858
859 case PIPE_FORMAT_L8A8_UNORM:
860 case PIPE_FORMAT_L8A8_SNORM:
861 case PIPE_FORMAT_L8A8_UINT:
862 case PIPE_FORMAT_L8A8_SINT:
863 case PIPE_FORMAT_R8G8_SNORM:
864 case PIPE_FORMAT_R8G8_UNORM:
865 case PIPE_FORMAT_R8G8_UINT:
866 case PIPE_FORMAT_R8G8_SINT:
867 return V_028C70_COLOR_8_8;
868
869 case PIPE_FORMAT_Z16_UNORM:
870 case PIPE_FORMAT_R16_UNORM:
871 case PIPE_FORMAT_R16_SNORM:
872 case PIPE_FORMAT_R16_UINT:
873 case PIPE_FORMAT_R16_SINT:
874 case PIPE_FORMAT_R16_FLOAT:
875 case PIPE_FORMAT_L16_UNORM:
876 case PIPE_FORMAT_L16_SNORM:
877 case PIPE_FORMAT_L16_FLOAT:
878 case PIPE_FORMAT_I16_UNORM:
879 case PIPE_FORMAT_I16_SNORM:
880 case PIPE_FORMAT_I16_FLOAT:
881 case PIPE_FORMAT_A16_UNORM:
882 case PIPE_FORMAT_A16_SNORM:
883 case PIPE_FORMAT_A16_FLOAT:
884 return V_028C70_COLOR_16;
885
886 /* 32-bit buffers. */
887 case PIPE_FORMAT_A8B8G8R8_SRGB:
888 case PIPE_FORMAT_A8B8G8R8_UNORM:
889 case PIPE_FORMAT_A8R8G8B8_UNORM:
890 case PIPE_FORMAT_B8G8R8A8_SRGB:
891 case PIPE_FORMAT_B8G8R8A8_UNORM:
892 case PIPE_FORMAT_B8G8R8X8_UNORM:
893 case PIPE_FORMAT_R8G8B8A8_SNORM:
894 case PIPE_FORMAT_R8G8B8A8_UNORM:
895 case PIPE_FORMAT_R8G8B8X8_UNORM:
896 case PIPE_FORMAT_R8G8B8X8_SNORM:
897 case PIPE_FORMAT_R8G8B8X8_SRGB:
898 case PIPE_FORMAT_R8G8B8X8_UINT:
899 case PIPE_FORMAT_R8G8B8X8_SINT:
900 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
901 case PIPE_FORMAT_X8B8G8R8_UNORM:
902 case PIPE_FORMAT_X8R8G8B8_UNORM:
903 case PIPE_FORMAT_R8G8B8A8_SSCALED:
904 case PIPE_FORMAT_R8G8B8A8_USCALED:
905 case PIPE_FORMAT_R8G8B8A8_SINT:
906 case PIPE_FORMAT_R8G8B8A8_UINT:
907 return V_028C70_COLOR_8_8_8_8;
908
909 case PIPE_FORMAT_R10G10B10A2_UNORM:
910 case PIPE_FORMAT_R10G10B10X2_SNORM:
911 case PIPE_FORMAT_B10G10R10A2_UNORM:
912 case PIPE_FORMAT_B10G10R10A2_UINT:
913 case PIPE_FORMAT_B10G10R10X2_UNORM:
914 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
915 return V_028C70_COLOR_2_10_10_10;
916
917 case PIPE_FORMAT_Z24X8_UNORM:
918 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
919 return V_028C70_COLOR_8_24;
920
921 case PIPE_FORMAT_S8X24_UINT:
922 case PIPE_FORMAT_X8Z24_UNORM:
923 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
924 return V_028C70_COLOR_24_8;
925
926 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
927 return V_028C70_COLOR_X24_8_32_FLOAT;
928
929 case PIPE_FORMAT_I32_FLOAT:
930 case PIPE_FORMAT_L32_FLOAT:
931 case PIPE_FORMAT_R32_FLOAT:
932 case PIPE_FORMAT_A32_FLOAT:
933 case PIPE_FORMAT_Z32_FLOAT:
934 return V_028C70_COLOR_32;
935
936 case PIPE_FORMAT_L16A16_UNORM:
937 case PIPE_FORMAT_L16A16_SNORM:
938 case PIPE_FORMAT_L16A16_FLOAT:
939 case PIPE_FORMAT_R16G16_SSCALED:
940 case PIPE_FORMAT_R16G16_UNORM:
941 case PIPE_FORMAT_R16G16_SNORM:
942 case PIPE_FORMAT_R16G16_UINT:
943 case PIPE_FORMAT_R16G16_SINT:
944 case PIPE_FORMAT_R16G16_FLOAT:
945 return V_028C70_COLOR_16_16;
946
947 case PIPE_FORMAT_R11G11B10_FLOAT:
948 return V_028C70_COLOR_10_11_11;
949
950 /* 64-bit buffers. */
951 case PIPE_FORMAT_R16G16B16A16_UINT:
952 case PIPE_FORMAT_R16G16B16A16_SINT:
953 case PIPE_FORMAT_R16G16B16A16_USCALED:
954 case PIPE_FORMAT_R16G16B16A16_SSCALED:
955 case PIPE_FORMAT_R16G16B16A16_UNORM:
956 case PIPE_FORMAT_R16G16B16A16_SNORM:
957 case PIPE_FORMAT_R16G16B16A16_FLOAT:
958 case PIPE_FORMAT_R16G16B16X16_UNORM:
959 case PIPE_FORMAT_R16G16B16X16_SNORM:
960 case PIPE_FORMAT_R16G16B16X16_FLOAT:
961 case PIPE_FORMAT_R16G16B16X16_UINT:
962 case PIPE_FORMAT_R16G16B16X16_SINT:
963 return V_028C70_COLOR_16_16_16_16;
964
965 case PIPE_FORMAT_L32A32_FLOAT:
966 case PIPE_FORMAT_L32A32_UINT:
967 case PIPE_FORMAT_L32A32_SINT:
968 case PIPE_FORMAT_R32G32_FLOAT:
969 case PIPE_FORMAT_R32G32_USCALED:
970 case PIPE_FORMAT_R32G32_SSCALED:
971 case PIPE_FORMAT_R32G32_SINT:
972 case PIPE_FORMAT_R32G32_UINT:
973 return V_028C70_COLOR_32_32;
974
975 /* 128-bit buffers. */
976 case PIPE_FORMAT_R32G32B32A32_SNORM:
977 case PIPE_FORMAT_R32G32B32A32_UNORM:
978 case PIPE_FORMAT_R32G32B32A32_SSCALED:
979 case PIPE_FORMAT_R32G32B32A32_USCALED:
980 case PIPE_FORMAT_R32G32B32A32_SINT:
981 case PIPE_FORMAT_R32G32B32A32_UINT:
982 case PIPE_FORMAT_R32G32B32A32_FLOAT:
983 case PIPE_FORMAT_R32G32B32X32_FLOAT:
984 case PIPE_FORMAT_R32G32B32X32_UINT:
985 case PIPE_FORMAT_R32G32B32X32_SINT:
986 return V_028C70_COLOR_32_32_32_32;
987
988 /* YUV buffers. */
989 case PIPE_FORMAT_UYVY:
990 case PIPE_FORMAT_YUYV:
991 /* 96-bit buffers. */
992 case PIPE_FORMAT_R32G32B32_FLOAT:
993 /* 8-bit buffers. */
994 case PIPE_FORMAT_L4A4_UNORM:
995 case PIPE_FORMAT_R4A4_UNORM:
996 case PIPE_FORMAT_A4R4_UNORM:
997 default:
998 return V_028C70_COLOR_INVALID; /* Unsupported. */
999 }
1000 }
1001
1002 static uint32_t si_translate_colorswap(enum pipe_format format)
1003 {
1004 switch (format) {
1005 /* 8-bit buffers. */
1006 case PIPE_FORMAT_L4A4_UNORM:
1007 case PIPE_FORMAT_A4R4_UNORM:
1008 return V_028C70_SWAP_ALT;
1009
1010 case PIPE_FORMAT_A8_UNORM:
1011 case PIPE_FORMAT_A8_SNORM:
1012 case PIPE_FORMAT_A8_UINT:
1013 case PIPE_FORMAT_A8_SINT:
1014 case PIPE_FORMAT_R4A4_UNORM:
1015 return V_028C70_SWAP_ALT_REV;
1016 case PIPE_FORMAT_I8_UNORM:
1017 case PIPE_FORMAT_I8_SNORM:
1018 case PIPE_FORMAT_L8_UNORM:
1019 case PIPE_FORMAT_L8_SNORM:
1020 case PIPE_FORMAT_I8_UINT:
1021 case PIPE_FORMAT_I8_SINT:
1022 case PIPE_FORMAT_L8_UINT:
1023 case PIPE_FORMAT_L8_SINT:
1024 case PIPE_FORMAT_L8_SRGB:
1025 case PIPE_FORMAT_R8_UNORM:
1026 case PIPE_FORMAT_R8_SNORM:
1027 case PIPE_FORMAT_R8_UINT:
1028 case PIPE_FORMAT_R8_SINT:
1029 return V_028C70_SWAP_STD;
1030
1031 /* 16-bit buffers. */
1032 case PIPE_FORMAT_B5G6R5_UNORM:
1033 return V_028C70_SWAP_STD_REV;
1034
1035 case PIPE_FORMAT_B5G5R5A1_UNORM:
1036 case PIPE_FORMAT_B5G5R5X1_UNORM:
1037 return V_028C70_SWAP_ALT;
1038
1039 case PIPE_FORMAT_B4G4R4A4_UNORM:
1040 case PIPE_FORMAT_B4G4R4X4_UNORM:
1041 return V_028C70_SWAP_ALT;
1042
1043 case PIPE_FORMAT_Z16_UNORM:
1044 return V_028C70_SWAP_STD;
1045
1046 case PIPE_FORMAT_L8A8_UNORM:
1047 case PIPE_FORMAT_L8A8_SNORM:
1048 case PIPE_FORMAT_L8A8_UINT:
1049 case PIPE_FORMAT_L8A8_SINT:
1050 return V_028C70_SWAP_ALT;
1051 case PIPE_FORMAT_R8G8_SNORM:
1052 case PIPE_FORMAT_R8G8_UNORM:
1053 case PIPE_FORMAT_R8G8_UINT:
1054 case PIPE_FORMAT_R8G8_SINT:
1055 return V_028C70_SWAP_STD;
1056
1057 case PIPE_FORMAT_I16_UNORM:
1058 case PIPE_FORMAT_I16_SNORM:
1059 case PIPE_FORMAT_I16_FLOAT:
1060 case PIPE_FORMAT_L16_UNORM:
1061 case PIPE_FORMAT_L16_SNORM:
1062 case PIPE_FORMAT_L16_FLOAT:
1063 case PIPE_FORMAT_R16_UNORM:
1064 case PIPE_FORMAT_R16_SNORM:
1065 case PIPE_FORMAT_R16_UINT:
1066 case PIPE_FORMAT_R16_SINT:
1067 case PIPE_FORMAT_R16_FLOAT:
1068 return V_028C70_SWAP_STD;
1069
1070 case PIPE_FORMAT_A16_UNORM:
1071 case PIPE_FORMAT_A16_SNORM:
1072 case PIPE_FORMAT_A16_FLOAT:
1073 return V_028C70_SWAP_ALT_REV;
1074
1075 /* 32-bit buffers. */
1076 case PIPE_FORMAT_A8B8G8R8_SRGB:
1077 return V_028C70_SWAP_STD_REV;
1078 case PIPE_FORMAT_B8G8R8A8_SRGB:
1079 return V_028C70_SWAP_ALT;
1080
1081 case PIPE_FORMAT_B8G8R8A8_UNORM:
1082 case PIPE_FORMAT_B8G8R8X8_UNORM:
1083 return V_028C70_SWAP_ALT;
1084
1085 case PIPE_FORMAT_A8R8G8B8_UNORM:
1086 case PIPE_FORMAT_X8R8G8B8_UNORM:
1087 return V_028C70_SWAP_ALT_REV;
1088 case PIPE_FORMAT_R8G8B8A8_SNORM:
1089 case PIPE_FORMAT_R8G8B8A8_UNORM:
1090 case PIPE_FORMAT_R8G8B8A8_SSCALED:
1091 case PIPE_FORMAT_R8G8B8A8_USCALED:
1092 case PIPE_FORMAT_R8G8B8A8_SINT:
1093 case PIPE_FORMAT_R8G8B8A8_UINT:
1094 case PIPE_FORMAT_R8G8B8X8_UNORM:
1095 case PIPE_FORMAT_R8G8B8X8_SNORM:
1096 case PIPE_FORMAT_R8G8B8X8_SRGB:
1097 case PIPE_FORMAT_R8G8B8X8_UINT:
1098 case PIPE_FORMAT_R8G8B8X8_SINT:
1099 return V_028C70_SWAP_STD;
1100
1101 case PIPE_FORMAT_A8B8G8R8_UNORM:
1102 case PIPE_FORMAT_X8B8G8R8_UNORM:
1103 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
1104 return V_028C70_SWAP_STD_REV;
1105
1106 case PIPE_FORMAT_Z24X8_UNORM:
1107 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1108 return V_028C70_SWAP_STD;
1109
1110 case PIPE_FORMAT_S8X24_UINT:
1111 case PIPE_FORMAT_X8Z24_UNORM:
1112 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1113 return V_028C70_SWAP_STD_REV;
1114
1115 case PIPE_FORMAT_R10G10B10A2_UNORM:
1116 case PIPE_FORMAT_R10G10B10X2_SNORM:
1117 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
1118 return V_028C70_SWAP_STD;
1119
1120 case PIPE_FORMAT_B10G10R10A2_UNORM:
1121 case PIPE_FORMAT_B10G10R10A2_UINT:
1122 case PIPE_FORMAT_B10G10R10X2_UNORM:
1123 return V_028C70_SWAP_ALT;
1124
1125 case PIPE_FORMAT_R11G11B10_FLOAT:
1126 case PIPE_FORMAT_I32_FLOAT:
1127 case PIPE_FORMAT_L32_FLOAT:
1128 case PIPE_FORMAT_R32_FLOAT:
1129 case PIPE_FORMAT_R32_UINT:
1130 case PIPE_FORMAT_R32_SINT:
1131 case PIPE_FORMAT_Z32_FLOAT:
1132 case PIPE_FORMAT_R16G16_FLOAT:
1133 case PIPE_FORMAT_R16G16_UNORM:
1134 case PIPE_FORMAT_R16G16_SNORM:
1135 case PIPE_FORMAT_R16G16_UINT:
1136 case PIPE_FORMAT_R16G16_SINT:
1137 return V_028C70_SWAP_STD;
1138
1139 case PIPE_FORMAT_L16A16_UNORM:
1140 case PIPE_FORMAT_L16A16_SNORM:
1141 case PIPE_FORMAT_L16A16_FLOAT:
1142 return V_028C70_SWAP_ALT;
1143
1144 case PIPE_FORMAT_A32_FLOAT:
1145 return V_028C70_SWAP_ALT_REV;
1146
1147 /* 64-bit buffers. */
1148 case PIPE_FORMAT_R32G32_FLOAT:
1149 case PIPE_FORMAT_R32G32_UINT:
1150 case PIPE_FORMAT_R32G32_SINT:
1151 case PIPE_FORMAT_R16G16B16A16_UNORM:
1152 case PIPE_FORMAT_R16G16B16A16_SNORM:
1153 case PIPE_FORMAT_R16G16B16A16_USCALED:
1154 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1155 case PIPE_FORMAT_R16G16B16A16_UINT:
1156 case PIPE_FORMAT_R16G16B16A16_SINT:
1157 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1158 case PIPE_FORMAT_R16G16B16X16_UNORM:
1159 case PIPE_FORMAT_R16G16B16X16_SNORM:
1160 case PIPE_FORMAT_R16G16B16X16_FLOAT:
1161 case PIPE_FORMAT_R16G16B16X16_UINT:
1162 case PIPE_FORMAT_R16G16B16X16_SINT:
1163 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1164 return V_028C70_SWAP_STD;
1165
1166 case PIPE_FORMAT_L32A32_FLOAT:
1167 case PIPE_FORMAT_L32A32_UINT:
1168 case PIPE_FORMAT_L32A32_SINT:
1169 return V_028C70_SWAP_ALT;
1170
1171 /* 128-bit buffers. */
1172 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1173 case PIPE_FORMAT_R32G32B32A32_SNORM:
1174 case PIPE_FORMAT_R32G32B32A32_UNORM:
1175 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1176 case PIPE_FORMAT_R32G32B32A32_USCALED:
1177 case PIPE_FORMAT_R32G32B32A32_SINT:
1178 case PIPE_FORMAT_R32G32B32A32_UINT:
1179 case PIPE_FORMAT_R32G32B32X32_FLOAT:
1180 case PIPE_FORMAT_R32G32B32X32_UINT:
1181 case PIPE_FORMAT_R32G32B32X32_SINT:
1182 return V_028C70_SWAP_STD;
1183 default:
1184 R600_ERR("unsupported colorswap format %d\n", format);
1185 return ~0U;
1186 }
1187 return ~0U;
1188 }
1189
1190 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1191 {
1192 if (R600_BIG_ENDIAN) {
1193 switch(colorformat) {
1194 /* 8-bit buffers. */
1195 case V_028C70_COLOR_8:
1196 return V_028C70_ENDIAN_NONE;
1197
1198 /* 16-bit buffers. */
1199 case V_028C70_COLOR_5_6_5:
1200 case V_028C70_COLOR_1_5_5_5:
1201 case V_028C70_COLOR_4_4_4_4:
1202 case V_028C70_COLOR_16:
1203 case V_028C70_COLOR_8_8:
1204 return V_028C70_ENDIAN_8IN16;
1205
1206 /* 32-bit buffers. */
1207 case V_028C70_COLOR_8_8_8_8:
1208 case V_028C70_COLOR_2_10_10_10:
1209 case V_028C70_COLOR_8_24:
1210 case V_028C70_COLOR_24_8:
1211 case V_028C70_COLOR_16_16:
1212 return V_028C70_ENDIAN_8IN32;
1213
1214 /* 64-bit buffers. */
1215 case V_028C70_COLOR_16_16_16_16:
1216 return V_028C70_ENDIAN_8IN16;
1217
1218 case V_028C70_COLOR_32_32:
1219 return V_028C70_ENDIAN_8IN32;
1220
1221 /* 128-bit buffers. */
1222 case V_028C70_COLOR_32_32_32_32:
1223 return V_028C70_ENDIAN_8IN32;
1224 default:
1225 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1226 }
1227 } else {
1228 return V_028C70_ENDIAN_NONE;
1229 }
1230 }
1231
1232 /* Returns the size in bits of the widest component of a CB format */
1233 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1234 {
1235 switch(colorformat) {
1236 case V_028C70_COLOR_4_4_4_4:
1237 return 4;
1238
1239 case V_028C70_COLOR_1_5_5_5:
1240 case V_028C70_COLOR_5_5_5_1:
1241 return 5;
1242
1243 case V_028C70_COLOR_5_6_5:
1244 return 6;
1245
1246 case V_028C70_COLOR_8:
1247 case V_028C70_COLOR_8_8:
1248 case V_028C70_COLOR_8_8_8_8:
1249 return 8;
1250
1251 case V_028C70_COLOR_10_10_10_2:
1252 case V_028C70_COLOR_2_10_10_10:
1253 return 10;
1254
1255 case V_028C70_COLOR_10_11_11:
1256 case V_028C70_COLOR_11_11_10:
1257 return 11;
1258
1259 case V_028C70_COLOR_16:
1260 case V_028C70_COLOR_16_16:
1261 case V_028C70_COLOR_16_16_16_16:
1262 return 16;
1263
1264 case V_028C70_COLOR_8_24:
1265 case V_028C70_COLOR_24_8:
1266 return 24;
1267
1268 case V_028C70_COLOR_32:
1269 case V_028C70_COLOR_32_32:
1270 case V_028C70_COLOR_32_32_32_32:
1271 case V_028C70_COLOR_X24_8_32_FLOAT:
1272 return 32;
1273 }
1274
1275 assert(!"Unknown maximum component size");
1276 return 0;
1277 }
1278
1279 static uint32_t si_translate_dbformat(enum pipe_format format)
1280 {
1281 switch (format) {
1282 case PIPE_FORMAT_Z16_UNORM:
1283 return V_028040_Z_16;
1284 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1285 case PIPE_FORMAT_X8Z24_UNORM:
1286 case PIPE_FORMAT_Z24X8_UNORM:
1287 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1288 return V_028040_Z_24; /* deprecated on SI */
1289 case PIPE_FORMAT_Z32_FLOAT:
1290 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1291 return V_028040_Z_32_FLOAT;
1292 default:
1293 return V_028040_Z_INVALID;
1294 }
1295 }
1296
1297 /*
1298 * Texture translation
1299 */
1300
1301 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1302 enum pipe_format format,
1303 const struct util_format_description *desc,
1304 int first_non_void)
1305 {
1306 struct r600_screen *rscreen = (struct r600_screen*)screen;
1307 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1308 boolean uniform = TRUE;
1309 int i;
1310
1311 /* Colorspace (return non-RGB formats directly). */
1312 switch (desc->colorspace) {
1313 /* Depth stencil formats */
1314 case UTIL_FORMAT_COLORSPACE_ZS:
1315 switch (format) {
1316 case PIPE_FORMAT_Z16_UNORM:
1317 return V_008F14_IMG_DATA_FORMAT_16;
1318 case PIPE_FORMAT_X24S8_UINT:
1319 case PIPE_FORMAT_Z24X8_UNORM:
1320 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1321 return V_008F14_IMG_DATA_FORMAT_8_24;
1322 case PIPE_FORMAT_X8Z24_UNORM:
1323 case PIPE_FORMAT_S8X24_UINT:
1324 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1325 return V_008F14_IMG_DATA_FORMAT_24_8;
1326 case PIPE_FORMAT_S8_UINT:
1327 return V_008F14_IMG_DATA_FORMAT_8;
1328 case PIPE_FORMAT_Z32_FLOAT:
1329 return V_008F14_IMG_DATA_FORMAT_32;
1330 case PIPE_FORMAT_X32_S8X24_UINT:
1331 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1332 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1333 default:
1334 goto out_unknown;
1335 }
1336
1337 case UTIL_FORMAT_COLORSPACE_YUV:
1338 goto out_unknown; /* TODO */
1339
1340 case UTIL_FORMAT_COLORSPACE_SRGB:
1341 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1342 goto out_unknown;
1343 break;
1344
1345 default:
1346 break;
1347 }
1348
1349 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1350 if (!enable_s3tc)
1351 goto out_unknown;
1352
1353 switch (format) {
1354 case PIPE_FORMAT_RGTC1_SNORM:
1355 case PIPE_FORMAT_LATC1_SNORM:
1356 case PIPE_FORMAT_RGTC1_UNORM:
1357 case PIPE_FORMAT_LATC1_UNORM:
1358 return V_008F14_IMG_DATA_FORMAT_BC4;
1359 case PIPE_FORMAT_RGTC2_SNORM:
1360 case PIPE_FORMAT_LATC2_SNORM:
1361 case PIPE_FORMAT_RGTC2_UNORM:
1362 case PIPE_FORMAT_LATC2_UNORM:
1363 return V_008F14_IMG_DATA_FORMAT_BC5;
1364 default:
1365 goto out_unknown;
1366 }
1367 }
1368
1369 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1370
1371 if (!enable_s3tc)
1372 goto out_unknown;
1373
1374 if (!util_format_s3tc_enabled) {
1375 goto out_unknown;
1376 }
1377
1378 switch (format) {
1379 case PIPE_FORMAT_DXT1_RGB:
1380 case PIPE_FORMAT_DXT1_RGBA:
1381 case PIPE_FORMAT_DXT1_SRGB:
1382 case PIPE_FORMAT_DXT1_SRGBA:
1383 return V_008F14_IMG_DATA_FORMAT_BC1;
1384 case PIPE_FORMAT_DXT3_RGBA:
1385 case PIPE_FORMAT_DXT3_SRGBA:
1386 return V_008F14_IMG_DATA_FORMAT_BC2;
1387 case PIPE_FORMAT_DXT5_RGBA:
1388 case PIPE_FORMAT_DXT5_SRGBA:
1389 return V_008F14_IMG_DATA_FORMAT_BC3;
1390 default:
1391 goto out_unknown;
1392 }
1393 }
1394
1395 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1396 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1397 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1398 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1399 }
1400
1401 /* R8G8Bx_SNORM - TODO CxV8U8 */
1402
1403 /* See whether the components are of the same size. */
1404 for (i = 1; i < desc->nr_channels; i++) {
1405 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1406 }
1407
1408 /* Non-uniform formats. */
1409 if (!uniform) {
1410 switch(desc->nr_channels) {
1411 case 3:
1412 if (desc->channel[0].size == 5 &&
1413 desc->channel[1].size == 6 &&
1414 desc->channel[2].size == 5) {
1415 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1416 }
1417 goto out_unknown;
1418 case 4:
1419 if (desc->channel[0].size == 5 &&
1420 desc->channel[1].size == 5 &&
1421 desc->channel[2].size == 5 &&
1422 desc->channel[3].size == 1) {
1423 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1424 }
1425 if (desc->channel[0].size == 10 &&
1426 desc->channel[1].size == 10 &&
1427 desc->channel[2].size == 10 &&
1428 desc->channel[3].size == 2) {
1429 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1430 }
1431 goto out_unknown;
1432 }
1433 goto out_unknown;
1434 }
1435
1436 if (first_non_void < 0 || first_non_void > 3)
1437 goto out_unknown;
1438
1439 /* uniform formats */
1440 switch (desc->channel[first_non_void].size) {
1441 case 4:
1442 switch (desc->nr_channels) {
1443 #if 0 /* Not supported for render targets */
1444 case 2:
1445 return V_008F14_IMG_DATA_FORMAT_4_4;
1446 #endif
1447 case 4:
1448 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1449 }
1450 break;
1451 case 8:
1452 switch (desc->nr_channels) {
1453 case 1:
1454 return V_008F14_IMG_DATA_FORMAT_8;
1455 case 2:
1456 return V_008F14_IMG_DATA_FORMAT_8_8;
1457 case 4:
1458 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1459 }
1460 break;
1461 case 16:
1462 switch (desc->nr_channels) {
1463 case 1:
1464 return V_008F14_IMG_DATA_FORMAT_16;
1465 case 2:
1466 return V_008F14_IMG_DATA_FORMAT_16_16;
1467 case 4:
1468 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1469 }
1470 break;
1471 case 32:
1472 switch (desc->nr_channels) {
1473 case 1:
1474 return V_008F14_IMG_DATA_FORMAT_32;
1475 case 2:
1476 return V_008F14_IMG_DATA_FORMAT_32_32;
1477 #if 0 /* Not supported for render targets */
1478 case 3:
1479 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1480 #endif
1481 case 4:
1482 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1483 }
1484 }
1485
1486 out_unknown:
1487 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1488 return ~0;
1489 }
1490
1491 static unsigned si_tex_wrap(unsigned wrap)
1492 {
1493 switch (wrap) {
1494 default:
1495 case PIPE_TEX_WRAP_REPEAT:
1496 return V_008F30_SQ_TEX_WRAP;
1497 case PIPE_TEX_WRAP_CLAMP:
1498 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1499 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1500 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1501 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1502 return V_008F30_SQ_TEX_CLAMP_BORDER;
1503 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1504 return V_008F30_SQ_TEX_MIRROR;
1505 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1506 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1507 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1508 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1509 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1510 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1511 }
1512 }
1513
1514 static unsigned si_tex_filter(unsigned filter)
1515 {
1516 switch (filter) {
1517 default:
1518 case PIPE_TEX_FILTER_NEAREST:
1519 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1520 case PIPE_TEX_FILTER_LINEAR:
1521 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1522 }
1523 }
1524
1525 static unsigned si_tex_mipfilter(unsigned filter)
1526 {
1527 switch (filter) {
1528 case PIPE_TEX_MIPFILTER_NEAREST:
1529 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1530 case PIPE_TEX_MIPFILTER_LINEAR:
1531 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1532 default:
1533 case PIPE_TEX_MIPFILTER_NONE:
1534 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1535 }
1536 }
1537
1538 static unsigned si_tex_compare(unsigned compare)
1539 {
1540 switch (compare) {
1541 default:
1542 case PIPE_FUNC_NEVER:
1543 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1544 case PIPE_FUNC_LESS:
1545 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1546 case PIPE_FUNC_EQUAL:
1547 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1548 case PIPE_FUNC_LEQUAL:
1549 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1550 case PIPE_FUNC_GREATER:
1551 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1552 case PIPE_FUNC_NOTEQUAL:
1553 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1554 case PIPE_FUNC_GEQUAL:
1555 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1556 case PIPE_FUNC_ALWAYS:
1557 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1558 }
1559 }
1560
1561 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1562 {
1563 switch (dim) {
1564 default:
1565 case PIPE_TEXTURE_1D:
1566 return V_008F1C_SQ_RSRC_IMG_1D;
1567 case PIPE_TEXTURE_1D_ARRAY:
1568 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1569 case PIPE_TEXTURE_2D:
1570 case PIPE_TEXTURE_RECT:
1571 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1572 V_008F1C_SQ_RSRC_IMG_2D;
1573 case PIPE_TEXTURE_2D_ARRAY:
1574 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1575 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1576 case PIPE_TEXTURE_3D:
1577 return V_008F1C_SQ_RSRC_IMG_3D;
1578 case PIPE_TEXTURE_CUBE:
1579 return V_008F1C_SQ_RSRC_IMG_CUBE;
1580 }
1581 }
1582
1583 /*
1584 * Format support testing
1585 */
1586
1587 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1588 {
1589 return si_translate_texformat(screen, format, util_format_description(format),
1590 util_format_get_first_non_void_channel(format)) != ~0U;
1591 }
1592
1593 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1594 enum pipe_format format,
1595 const struct util_format_description *desc,
1596 int first_non_void)
1597 {
1598 unsigned type = desc->channel[first_non_void].type;
1599 int i;
1600
1601 if (type == UTIL_FORMAT_TYPE_FIXED)
1602 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1603
1604 /* See whether the components are of the same size. */
1605 for (i = 0; i < desc->nr_channels; i++) {
1606 if (desc->channel[first_non_void].size != desc->channel[i].size)
1607 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1608 }
1609
1610 switch (desc->channel[first_non_void].size) {
1611 case 8:
1612 switch (desc->nr_channels) {
1613 case 1:
1614 return V_008F0C_BUF_DATA_FORMAT_8;
1615 case 2:
1616 return V_008F0C_BUF_DATA_FORMAT_8_8;
1617 case 3:
1618 case 4:
1619 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1620 }
1621 break;
1622 case 16:
1623 switch (desc->nr_channels) {
1624 case 1:
1625 return V_008F0C_BUF_DATA_FORMAT_16;
1626 case 2:
1627 return V_008F0C_BUF_DATA_FORMAT_16_16;
1628 case 3:
1629 case 4:
1630 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1631 }
1632 break;
1633 case 32:
1634 /* From the Southern Islands ISA documentation about MTBUF:
1635 * 'Memory reads of data in memory that is 32 or 64 bits do not
1636 * undergo any format conversion.'
1637 */
1638 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1639 !desc->channel[first_non_void].pure_integer)
1640 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1641
1642 switch (desc->nr_channels) {
1643 case 1:
1644 return V_008F0C_BUF_DATA_FORMAT_32;
1645 case 2:
1646 return V_008F0C_BUF_DATA_FORMAT_32_32;
1647 case 3:
1648 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1649 case 4:
1650 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1651 }
1652 break;
1653 }
1654
1655 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1656 }
1657
1658 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1659 {
1660 const struct util_format_description *desc;
1661 int first_non_void;
1662 unsigned data_format;
1663
1664 desc = util_format_description(format);
1665 first_non_void = util_format_get_first_non_void_channel(format);
1666 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1667 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1668 }
1669
1670 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1671 {
1672 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1673 si_translate_colorswap(format) != ~0U;
1674 }
1675
1676 static bool si_is_zs_format_supported(enum pipe_format format)
1677 {
1678 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1679 }
1680
1681 boolean si_is_format_supported(struct pipe_screen *screen,
1682 enum pipe_format format,
1683 enum pipe_texture_target target,
1684 unsigned sample_count,
1685 unsigned usage)
1686 {
1687 struct r600_screen *rscreen = (struct r600_screen *)screen;
1688 unsigned retval = 0;
1689
1690 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1691 R600_ERR("r600: unsupported texture type %d\n", target);
1692 return FALSE;
1693 }
1694
1695 if (!util_format_is_supported(format, usage))
1696 return FALSE;
1697
1698 if (sample_count > 1) {
1699 if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI)
1700 return FALSE;
1701
1702 switch (sample_count) {
1703 case 2:
1704 case 4:
1705 case 8:
1706 break;
1707 default:
1708 return FALSE;
1709 }
1710 }
1711
1712 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1713 si_is_sampler_format_supported(screen, format)) {
1714 retval |= PIPE_BIND_SAMPLER_VIEW;
1715 }
1716
1717 if ((usage & (PIPE_BIND_RENDER_TARGET |
1718 PIPE_BIND_DISPLAY_TARGET |
1719 PIPE_BIND_SCANOUT |
1720 PIPE_BIND_SHARED)) &&
1721 si_is_colorbuffer_format_supported(format)) {
1722 retval |= usage &
1723 (PIPE_BIND_RENDER_TARGET |
1724 PIPE_BIND_DISPLAY_TARGET |
1725 PIPE_BIND_SCANOUT |
1726 PIPE_BIND_SHARED);
1727 }
1728
1729 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1730 si_is_zs_format_supported(format)) {
1731 retval |= PIPE_BIND_DEPTH_STENCIL;
1732 }
1733
1734 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1735 si_is_vertex_format_supported(screen, format)) {
1736 retval |= PIPE_BIND_VERTEX_BUFFER;
1737 }
1738
1739 if (usage & PIPE_BIND_TRANSFER_READ)
1740 retval |= PIPE_BIND_TRANSFER_READ;
1741 if (usage & PIPE_BIND_TRANSFER_WRITE)
1742 retval |= PIPE_BIND_TRANSFER_WRITE;
1743
1744 return retval == usage;
1745 }
1746
1747 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1748 {
1749 unsigned tile_mode_index = 0;
1750
1751 if (stencil) {
1752 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1753 } else {
1754 tile_mode_index = rtex->surface.tiling_index[level];
1755 }
1756 return tile_mode_index;
1757 }
1758
1759 /*
1760 * framebuffer handling
1761 */
1762
1763 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1764 const struct pipe_framebuffer_state *state, int cb)
1765 {
1766 struct r600_texture *rtex;
1767 struct r600_surface *surf;
1768 unsigned level = state->cbufs[cb]->u.tex.level;
1769 unsigned pitch, slice;
1770 unsigned color_info, color_attrib;
1771 unsigned tile_mode_index;
1772 unsigned format, swap, ntype, endian;
1773 uint64_t offset;
1774 const struct util_format_description *desc;
1775 int i;
1776 unsigned blend_clamp = 0, blend_bypass = 0;
1777 unsigned max_comp_size;
1778
1779 surf = (struct r600_surface *)state->cbufs[cb];
1780 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1781
1782 offset = rtex->surface.level[level].offset;
1783 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1784 offset += rtex->surface.level[level].slice_size *
1785 state->cbufs[cb]->u.tex.first_layer;
1786 }
1787 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1788 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1789 if (slice) {
1790 slice = slice - 1;
1791 }
1792
1793 tile_mode_index = si_tile_mode_index(rtex, level, false);
1794
1795 desc = util_format_description(surf->base.format);
1796 for (i = 0; i < 4; i++) {
1797 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1798 break;
1799 }
1800 }
1801 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1802 ntype = V_028C70_NUMBER_FLOAT;
1803 } else {
1804 ntype = V_028C70_NUMBER_UNORM;
1805 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1806 ntype = V_028C70_NUMBER_SRGB;
1807 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1808 if (desc->channel[i].pure_integer) {
1809 ntype = V_028C70_NUMBER_SINT;
1810 } else {
1811 assert(desc->channel[i].normalized);
1812 ntype = V_028C70_NUMBER_SNORM;
1813 }
1814 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1815 if (desc->channel[i].pure_integer) {
1816 ntype = V_028C70_NUMBER_UINT;
1817 } else {
1818 assert(desc->channel[i].normalized);
1819 ntype = V_028C70_NUMBER_UNORM;
1820 }
1821 }
1822 }
1823
1824 format = si_translate_colorformat(surf->base.format);
1825 if (format == V_028C70_COLOR_INVALID) {
1826 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1827 }
1828 assert(format != V_028C70_COLOR_INVALID);
1829 swap = si_translate_colorswap(surf->base.format);
1830 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1831 endian = V_028C70_ENDIAN_NONE;
1832 } else {
1833 endian = si_colorformat_endian_swap(format);
1834 }
1835
1836 /* blend clamp should be set for all NORM/SRGB types */
1837 if (ntype == V_028C70_NUMBER_UNORM ||
1838 ntype == V_028C70_NUMBER_SNORM ||
1839 ntype == V_028C70_NUMBER_SRGB)
1840 blend_clamp = 1;
1841
1842 /* set blend bypass according to docs if SINT/UINT or
1843 8/24 COLOR variants */
1844 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1845 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1846 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1847 blend_clamp = 0;
1848 blend_bypass = 1;
1849 }
1850
1851 color_info = S_028C70_FORMAT(format) |
1852 S_028C70_COMP_SWAP(swap) |
1853 S_028C70_BLEND_CLAMP(blend_clamp) |
1854 S_028C70_BLEND_BYPASS(blend_bypass) |
1855 S_028C70_NUMBER_TYPE(ntype) |
1856 S_028C70_ENDIAN(endian);
1857
1858 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1859 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1860
1861 if (rtex->resource.b.b.nr_samples > 1) {
1862 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1863
1864 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1865 S_028C74_NUM_FRAGMENTS(log_samples);
1866
1867 if (rtex->fmask.size) {
1868 color_info |= S_028C70_COMPRESSION(1);
1869 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1870
1871 /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */
1872 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) |
1873 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1874 }
1875 }
1876
1877 if (rtex->cmask.size) {
1878 color_info |= S_028C70_FAST_CLEAR(1);
1879 }
1880
1881 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1882 offset >>= 8;
1883
1884 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1885 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1886 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1887 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1888 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1889
1890 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1891 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1892 } else {
1893 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1894 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1895 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1896 }
1897 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1898 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1899
1900 if (rtex->cmask.size) {
1901 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1902 offset + (rtex->cmask.offset >> 8));
1903 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1904 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1905 }
1906 if (rtex->fmask.size) {
1907 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1908 offset + (rtex->fmask.offset >> 8));
1909 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1910 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1911 }
1912
1913 /* set CB_COLOR1_INFO for possible dual-src blending */
1914 if (state->nr_cbufs == 1) {
1915 assert(cb == 0);
1916 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1917 }
1918
1919 /* Determine pixel shader export format */
1920 max_comp_size = si_colorformat_max_comp_size(format);
1921 if (ntype == V_028C70_NUMBER_SRGB ||
1922 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1923 max_comp_size <= 10) ||
1924 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1925 rctx->export_16bpc |= 1 << cb;
1926 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1927 if (state->nr_cbufs == 1)
1928 rctx->export_16bpc |= 1 << 1;
1929 }
1930 }
1931
1932 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1933 const struct pipe_framebuffer_state *state)
1934 {
1935 struct r600_screen *rscreen = rctx->screen;
1936 struct r600_texture *rtex;
1937 struct r600_surface *surf;
1938 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1939 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1940 uint32_t z_info, s_info, db_depth_info;
1941 uint64_t z_offs, s_offs;
1942
1943 if (state->zsbuf == NULL) {
1944 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1945 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1946 return;
1947 }
1948
1949 surf = (struct r600_surface *)state->zsbuf;
1950 level = surf->base.u.tex.level;
1951 rtex = (struct r600_texture*)surf->base.texture;
1952
1953 format = si_translate_dbformat(rtex->resource.b.b.format);
1954
1955 if (format == V_028040_Z_INVALID) {
1956 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1957 }
1958 assert(format != V_028040_Z_INVALID);
1959
1960 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1961 z_offs += rtex->surface.level[level].offset;
1962 s_offs += rtex->surface.stencil_level[level].offset;
1963
1964 z_offs >>= 8;
1965 s_offs >>= 8;
1966
1967 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1968 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1969 if (slice) {
1970 slice = slice - 1;
1971 }
1972
1973 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1974
1975 z_info = S_028040_FORMAT(format);
1976 if (rtex->resource.b.b.nr_samples > 1) {
1977 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1978 }
1979
1980 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1981 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1982 else
1983 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1984
1985 if (rctx->b.chip_class >= CIK) {
1986 switch (rtex->surface.level[level].mode) {
1987 case RADEON_SURF_MODE_2D:
1988 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1989 break;
1990 case RADEON_SURF_MODE_1D:
1991 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1992 case RADEON_SURF_MODE_LINEAR:
1993 default:
1994 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1995 break;
1996 }
1997 tile_split = rtex->surface.tile_split;
1998 stile_split = rtex->surface.stencil_tile_split;
1999 macro_aspect = rtex->surface.mtilea;
2000 bankw = rtex->surface.bankw;
2001 bankh = rtex->surface.bankh;
2002 tile_split = cik_tile_split(tile_split);
2003 stile_split = cik_tile_split(stile_split);
2004 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2005 bankw = cik_bank_wh(bankw);
2006 bankh = cik_bank_wh(bankh);
2007 nbanks = cik_num_banks(rscreen->tiling_info.num_banks);
2008 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
2009 rscreen->b.info.r600_num_backends);
2010
2011 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2012 S_02803C_PIPE_CONFIG(pipe_config) |
2013 S_02803C_BANK_WIDTH(bankw) |
2014 S_02803C_BANK_HEIGHT(bankh) |
2015 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2016 S_02803C_NUM_BANKS(nbanks);
2017 z_info |= S_028040_TILE_SPLIT(tile_split);
2018 s_info |= S_028044_TILE_SPLIT(stile_split);
2019 } else {
2020 tile_mode_index = si_tile_mode_index(rtex, level, false);
2021 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2022 tile_mode_index = si_tile_mode_index(rtex, level, true);
2023 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2024 }
2025
2026 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
2027 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
2028 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
2029
2030 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
2031 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
2032 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
2033
2034 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
2035 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
2036 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
2037 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
2038 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
2039
2040 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
2041 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
2042 }
2043
2044 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
2045 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
2046 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
2047 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
2048 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
2049
2050 /* 2xMSAA
2051 * There are two locations (-4, 4), (4, -4). */
2052 static uint32_t sample_locs_2x[] = {
2053 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2054 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2055 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2056 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2057 };
2058 static unsigned max_dist_2x = 4;
2059 /* 4xMSAA
2060 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
2061 static uint32_t sample_locs_4x[] = {
2062 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2063 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2064 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2065 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2066 };
2067 static unsigned max_dist_4x = 6;
2068 /* Cayman/SI 8xMSAA */
2069 static uint32_t cm_sample_locs_8x[] = {
2070 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2071 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2072 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2073 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2074 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2075 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2076 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2077 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2078 };
2079 static unsigned cm_max_dist_8x = 8;
2080 /* Cayman/SI 16xMSAA */
2081 static uint32_t cm_sample_locs_16x[] = {
2082 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2083 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2084 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2085 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2086 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2087 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2088 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2089 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2090 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2091 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2092 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2093 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2094 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2095 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2096 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2097 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2098 };
2099 static unsigned cm_max_dist_16x = 8;
2100
2101 static void si_get_sample_position(struct pipe_context *ctx,
2102 unsigned sample_count,
2103 unsigned sample_index,
2104 float *out_value)
2105 {
2106 int offset, index;
2107 struct {
2108 int idx:4;
2109 } val;
2110 switch (sample_count) {
2111 case 1:
2112 default:
2113 out_value[0] = out_value[1] = 0.5;
2114 break;
2115 case 2:
2116 offset = 4 * (sample_index * 2);
2117 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
2118 out_value[0] = (float)(val.idx + 8) / 16.0f;
2119 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
2120 out_value[1] = (float)(val.idx + 8) / 16.0f;
2121 break;
2122 case 4:
2123 offset = 4 * (sample_index * 2);
2124 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
2125 out_value[0] = (float)(val.idx + 8) / 16.0f;
2126 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
2127 out_value[1] = (float)(val.idx + 8) / 16.0f;
2128 break;
2129 case 8:
2130 offset = 4 * (sample_index % 4 * 2);
2131 index = (sample_index / 4) * 4;
2132 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
2133 out_value[0] = (float)(val.idx + 8) / 16.0f;
2134 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2135 out_value[1] = (float)(val.idx + 8) / 16.0f;
2136 break;
2137 case 16:
2138 offset = 4 * (sample_index % 4 * 2);
2139 index = (sample_index / 4) * 4;
2140 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2141 out_value[0] = (float)(val.idx + 8) / 16.0f;
2142 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2143 out_value[1] = (float)(val.idx + 8) / 16.0f;
2144 break;
2145 }
2146 }
2147
2148 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
2149 {
2150 unsigned max_dist = 0;
2151
2152 switch (nr_samples) {
2153 default:
2154 nr_samples = 0;
2155 break;
2156 case 2:
2157 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2158 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2159 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2160 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2161 max_dist = max_dist_2x;
2162 break;
2163 case 4:
2164 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2165 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2166 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2167 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2168 max_dist = max_dist_4x;
2169 break;
2170 case 8:
2171 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2172 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2173 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2174 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2175 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2176 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2177 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2178 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2179 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2180 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2181 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2182 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2183 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2184 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2185 max_dist = cm_max_dist_8x;
2186 break;
2187 case 16:
2188 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2189 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2190 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2191 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2192 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2193 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2194 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2195 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2196 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2197 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2198 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2199 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2200 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2201 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2202 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2203 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2204 max_dist = cm_max_dist_16x;
2205 break;
2206 }
2207
2208 if (nr_samples > 1) {
2209 unsigned log_samples = util_logbase2(nr_samples);
2210
2211 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2212 S_028BDC_LAST_PIXEL(1) |
2213 S_028BDC_EXPAND_LINE_WIDTH(1));
2214 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2215 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2216 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2217 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2218
2219 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2220 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2221 S_028804_PS_ITER_SAMPLES(log_samples) |
2222 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2223 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2224 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2225 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2226 } else {
2227 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2228 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2229
2230 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2231 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2232 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2233 }
2234 }
2235
2236 static void si_set_framebuffer_state(struct pipe_context *ctx,
2237 const struct pipe_framebuffer_state *state)
2238 {
2239 struct r600_context *rctx = (struct r600_context *)ctx;
2240 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2241 uint32_t tl, br;
2242 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2243
2244 if (pm4 == NULL)
2245 return;
2246
2247 if (rctx->framebuffer.nr_cbufs) {
2248 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2249 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2250 }
2251 if (rctx->framebuffer.zsbuf) {
2252 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2253 }
2254
2255 util_copy_framebuffer_state(&rctx->framebuffer, state);
2256
2257 /* build states */
2258 rctx->export_16bpc = 0;
2259 rctx->fb_compressed_cb_mask = 0;
2260 for (i = 0; i < state->nr_cbufs; i++) {
2261 struct r600_texture *rtex =
2262 (struct r600_texture*)state->cbufs[i]->texture;
2263
2264 si_cb(rctx, pm4, state, i);
2265
2266 if (rtex->fmask.size || rtex->cmask.size) {
2267 rctx->fb_compressed_cb_mask |= 1 << i;
2268 }
2269 }
2270 for (; i < 8; i++) {
2271 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2272 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2273 }
2274
2275 assert(!(rctx->export_16bpc & ~0xff));
2276 si_db(rctx, pm4, state);
2277
2278 tl_x = 0;
2279 tl_y = 0;
2280 br_x = state->width;
2281 br_y = state->height;
2282
2283 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2284 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2285
2286 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2287 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2288 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2289 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2290 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2291 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2292 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2293 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2294 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2295 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2296
2297 if (state->nr_cbufs)
2298 nr_samples = state->cbufs[0]->texture->nr_samples;
2299 else if (state->zsbuf)
2300 nr_samples = state->zsbuf->texture->nr_samples;
2301 else
2302 nr_samples = 0;
2303
2304 si_set_msaa_state(rctx, pm4, nr_samples);
2305 rctx->fb_log_samples = util_logbase2(nr_samples);
2306 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2307 util_format_is_pure_integer(state->cbufs[0]->format);
2308
2309 si_pm4_set_state(rctx, framebuffer, pm4);
2310 si_update_fb_rs_state(rctx);
2311 si_update_fb_blend_state(rctx);
2312 }
2313
2314 /*
2315 * shaders
2316 */
2317
2318 /* Compute the key for the hw shader variant */
2319 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2320 struct si_pipe_shader_selector *sel,
2321 union si_shader_key *key)
2322 {
2323 struct r600_context *rctx = (struct r600_context *)ctx;
2324 memset(key, 0, sizeof(*key));
2325
2326 if (sel->type == PIPE_SHADER_VERTEX) {
2327 unsigned i;
2328 if (!rctx->vertex_elements)
2329 return;
2330
2331 for (i = 0; i < rctx->vertex_elements->count; ++i)
2332 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2333
2334 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2335 key->vs.ucps_enabled |= 0x2;
2336 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2337 key->vs.ucps_enabled |= 0x1;
2338 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2339 if (sel->fs_write_all)
2340 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2341 key->ps.export_16bpc = rctx->export_16bpc;
2342
2343 if (rctx->queued.named.rasterizer) {
2344 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2345 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2346
2347 if (rctx->queued.named.blend) {
2348 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2349 rctx->queued.named.rasterizer->multisample_enable &&
2350 !rctx->fb_cb0_is_integer;
2351 }
2352 }
2353 if (rctx->queued.named.dsa) {
2354 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2355 key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
2356 } else {
2357 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2358 }
2359 }
2360 }
2361
2362 /* Select the hw shader variant depending on the current state.
2363 * (*dirty) is set to 1 if current variant was changed */
2364 int si_shader_select(struct pipe_context *ctx,
2365 struct si_pipe_shader_selector *sel,
2366 unsigned *dirty)
2367 {
2368 union si_shader_key key;
2369 struct si_pipe_shader * shader = NULL;
2370 int r;
2371
2372 si_shader_selector_key(ctx, sel, &key);
2373
2374 /* Check if we don't need to change anything.
2375 * This path is also used for most shaders that don't need multiple
2376 * variants, it will cost just a computation of the key and this
2377 * test. */
2378 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2379 return 0;
2380 }
2381
2382 /* lookup if we have other variants in the list */
2383 if (sel->num_shaders > 1) {
2384 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2385
2386 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2387 p = c;
2388 c = c->next_variant;
2389 }
2390
2391 if (c) {
2392 p->next_variant = c->next_variant;
2393 shader = c;
2394 }
2395 }
2396
2397 if (unlikely(!shader)) {
2398 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2399 shader->selector = sel;
2400 shader->key = key;
2401
2402 r = si_pipe_shader_create(ctx, shader);
2403 if (unlikely(r)) {
2404 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2405 sel->type, r);
2406 sel->current = NULL;
2407 FREE(shader);
2408 return r;
2409 }
2410
2411 /* We don't know the value of fs_write_all property until we built
2412 * at least one variant, so we may need to recompute the key (include
2413 * rctx->framebuffer.nr_cbufs) after building first variant. */
2414 if (sel->type == PIPE_SHADER_FRAGMENT &&
2415 sel->num_shaders == 0 &&
2416 shader->shader.fs_write_all) {
2417 sel->fs_write_all = 1;
2418 si_shader_selector_key(ctx, sel, &shader->key);
2419 }
2420
2421 sel->num_shaders++;
2422 }
2423
2424 if (dirty)
2425 *dirty = 1;
2426
2427 shader->next_variant = sel->current;
2428 sel->current = shader;
2429
2430 return 0;
2431 }
2432
2433 static void *si_create_shader_state(struct pipe_context *ctx,
2434 const struct pipe_shader_state *state,
2435 unsigned pipe_shader_type)
2436 {
2437 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2438 int r;
2439
2440 sel->type = pipe_shader_type;
2441 sel->tokens = tgsi_dup_tokens(state->tokens);
2442 sel->so = state->stream_output;
2443
2444 r = si_shader_select(ctx, sel, NULL);
2445 if (r) {
2446 free(sel);
2447 return NULL;
2448 }
2449
2450 return sel;
2451 }
2452
2453 static void *si_create_fs_state(struct pipe_context *ctx,
2454 const struct pipe_shader_state *state)
2455 {
2456 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2457 }
2458
2459 static void *si_create_vs_state(struct pipe_context *ctx,
2460 const struct pipe_shader_state *state)
2461 {
2462 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2463 }
2464
2465 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2466 {
2467 struct r600_context *rctx = (struct r600_context *)ctx;
2468 struct si_pipe_shader_selector *sel = state;
2469
2470 if (rctx->vs_shader == sel)
2471 return;
2472
2473 rctx->vs_shader = sel;
2474
2475 if (sel && sel->current) {
2476 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2477 rctx->b.streamout.stride_in_dw = sel->so.stride;
2478 } else {
2479 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2480 }
2481
2482 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2483 }
2484
2485 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2486 {
2487 struct r600_context *rctx = (struct r600_context *)ctx;
2488 struct si_pipe_shader_selector *sel = state;
2489
2490 if (rctx->ps_shader == sel)
2491 return;
2492
2493 rctx->ps_shader = sel;
2494
2495 if (sel && sel->current)
2496 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2497 else
2498 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2499
2500 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2501 }
2502
2503 static void si_delete_shader_selector(struct pipe_context *ctx,
2504 struct si_pipe_shader_selector *sel)
2505 {
2506 struct r600_context *rctx = (struct r600_context *)ctx;
2507 struct si_pipe_shader *p = sel->current, *c;
2508
2509 while (p) {
2510 c = p->next_variant;
2511 si_pm4_delete_state(rctx, vs, p->pm4);
2512 si_pipe_shader_destroy(ctx, p);
2513 free(p);
2514 p = c;
2515 }
2516
2517 free(sel->tokens);
2518 free(sel);
2519 }
2520
2521 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2522 {
2523 struct r600_context *rctx = (struct r600_context *)ctx;
2524 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2525
2526 if (rctx->vs_shader == sel) {
2527 rctx->vs_shader = NULL;
2528 }
2529
2530 si_delete_shader_selector(ctx, sel);
2531 }
2532
2533 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2534 {
2535 struct r600_context *rctx = (struct r600_context *)ctx;
2536 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2537
2538 if (rctx->ps_shader == sel) {
2539 rctx->ps_shader = NULL;
2540 }
2541
2542 si_delete_shader_selector(ctx, sel);
2543 }
2544
2545 /*
2546 * Samplers
2547 */
2548
2549 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2550 struct pipe_resource *texture,
2551 const struct pipe_sampler_view *state)
2552 {
2553 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2554 struct r600_texture *tmp = (struct r600_texture*)texture;
2555 const struct util_format_description *desc;
2556 unsigned format, num_format;
2557 uint32_t pitch = 0;
2558 unsigned char state_swizzle[4], swizzle[4];
2559 unsigned height, depth, width;
2560 enum pipe_format pipe_format = state->format;
2561 struct radeon_surface_level *surflevel;
2562 int first_non_void;
2563 uint64_t va;
2564
2565 if (view == NULL)
2566 return NULL;
2567
2568 /* initialize base object */
2569 view->base = *state;
2570 view->base.texture = NULL;
2571 pipe_reference(NULL, &texture->reference);
2572 view->base.texture = texture;
2573 view->base.reference.count = 1;
2574 view->base.context = ctx;
2575
2576 state_swizzle[0] = state->swizzle_r;
2577 state_swizzle[1] = state->swizzle_g;
2578 state_swizzle[2] = state->swizzle_b;
2579 state_swizzle[3] = state->swizzle_a;
2580
2581 surflevel = tmp->surface.level;
2582
2583 /* Texturing with separate depth and stencil. */
2584 if (tmp->is_depth && !tmp->is_flushing_texture) {
2585 switch (pipe_format) {
2586 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2587 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2588 break;
2589 case PIPE_FORMAT_X8Z24_UNORM:
2590 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2591 /* Z24 is always stored like this. */
2592 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2593 break;
2594 case PIPE_FORMAT_X24S8_UINT:
2595 case PIPE_FORMAT_S8X24_UINT:
2596 case PIPE_FORMAT_X32_S8X24_UINT:
2597 pipe_format = PIPE_FORMAT_S8_UINT;
2598 surflevel = tmp->surface.stencil_level;
2599 break;
2600 default:;
2601 }
2602 }
2603
2604 desc = util_format_description(pipe_format);
2605
2606 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2607 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2608 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2609
2610 switch (pipe_format) {
2611 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2612 case PIPE_FORMAT_X24S8_UINT:
2613 case PIPE_FORMAT_X32_S8X24_UINT:
2614 case PIPE_FORMAT_X8Z24_UNORM:
2615 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2616 break;
2617 default:
2618 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2619 }
2620 } else {
2621 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2622 }
2623
2624 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2625
2626 switch (pipe_format) {
2627 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2628 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2629 break;
2630 default:
2631 if (first_non_void < 0) {
2632 if (util_format_is_compressed(pipe_format)) {
2633 switch (pipe_format) {
2634 case PIPE_FORMAT_DXT1_SRGB:
2635 case PIPE_FORMAT_DXT1_SRGBA:
2636 case PIPE_FORMAT_DXT3_SRGBA:
2637 case PIPE_FORMAT_DXT5_SRGBA:
2638 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2639 break;
2640 case PIPE_FORMAT_RGTC1_SNORM:
2641 case PIPE_FORMAT_LATC1_SNORM:
2642 case PIPE_FORMAT_RGTC2_SNORM:
2643 case PIPE_FORMAT_LATC2_SNORM:
2644 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2645 break;
2646 default:
2647 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2648 break;
2649 }
2650 } else {
2651 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2652 }
2653 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2654 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2655 } else {
2656 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2657
2658 switch (desc->channel[first_non_void].type) {
2659 case UTIL_FORMAT_TYPE_FLOAT:
2660 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2661 break;
2662 case UTIL_FORMAT_TYPE_SIGNED:
2663 if (desc->channel[first_non_void].normalized)
2664 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2665 else if (desc->channel[first_non_void].pure_integer)
2666 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2667 else
2668 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2669 break;
2670 case UTIL_FORMAT_TYPE_UNSIGNED:
2671 if (desc->channel[first_non_void].normalized)
2672 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2673 else if (desc->channel[first_non_void].pure_integer)
2674 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2675 else
2676 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2677 }
2678 }
2679 }
2680
2681 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2682 if (format == ~0) {
2683 format = 0;
2684 }
2685
2686 view->resource = &tmp->resource;
2687
2688 /* not supported any more */
2689 //endian = si_colorformat_endian_swap(format);
2690
2691 width = surflevel[0].npix_x;
2692 height = surflevel[0].npix_y;
2693 depth = surflevel[0].npix_z;
2694 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2695
2696 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2697 height = 1;
2698 depth = texture->array_size;
2699 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2700 depth = texture->array_size;
2701 }
2702
2703 va = r600_resource_va(ctx->screen, texture);
2704 va += surflevel[0].offset;
2705 view->state[0] = va >> 8;
2706 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2707 S_008F14_DATA_FORMAT(format) |
2708 S_008F14_NUM_FORMAT(num_format));
2709 view->state[2] = (S_008F18_WIDTH(width - 1) |
2710 S_008F18_HEIGHT(height - 1));
2711 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2712 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2713 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2714 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2715 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2716 0 : state->u.tex.first_level) |
2717 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2718 util_logbase2(texture->nr_samples) :
2719 state->u.tex.last_level) |
2720 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2721 S_008F1C_POW2_PAD(texture->last_level > 0) |
2722 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2723 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2724 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2725 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2726 view->state[6] = 0;
2727 view->state[7] = 0;
2728
2729 /* Initialize the sampler view for FMASK. */
2730 if (tmp->fmask.size) {
2731 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2732 uint32_t fmask_format;
2733
2734 switch (texture->nr_samples) {
2735 case 2:
2736 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2737 break;
2738 case 4:
2739 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2740 break;
2741 case 8:
2742 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2743 break;
2744 default:
2745 assert(0);
2746 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2747 }
2748
2749 view->fmask_state[0] = va >> 8;
2750 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2751 S_008F14_DATA_FORMAT(fmask_format) |
2752 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2753 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2754 S_008F18_HEIGHT(height - 1);
2755 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2756 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2757 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2758 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2759 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2760 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2761 view->fmask_state[4] = S_008F20_PITCH(tmp->fmask.pitch - 1);
2762 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2763 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2764 view->fmask_state[6] = 0;
2765 view->fmask_state[7] = 0;
2766 }
2767
2768 return &view->base;
2769 }
2770
2771 static void si_sampler_view_destroy(struct pipe_context *ctx,
2772 struct pipe_sampler_view *state)
2773 {
2774 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2775
2776 pipe_resource_reference(&state->texture, NULL);
2777 FREE(resource);
2778 }
2779
2780 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2781 {
2782 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2783 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2784 (linear_filter &&
2785 (wrap == PIPE_TEX_WRAP_CLAMP ||
2786 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2787 }
2788
2789 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2790 {
2791 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2792 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2793
2794 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2795 state->border_color.ui[2] || state->border_color.ui[3]) &&
2796 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2797 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2798 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2799 }
2800
2801 static void *si_create_sampler_state(struct pipe_context *ctx,
2802 const struct pipe_sampler_state *state)
2803 {
2804 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2805 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2806 unsigned border_color_type;
2807
2808 if (rstate == NULL) {
2809 return NULL;
2810 }
2811
2812 if (sampler_state_needs_border_color(state))
2813 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2814 else
2815 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2816
2817 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2818 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2819 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2820 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2821 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2822 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2823 aniso_flag_offset << 16 | /* XXX */
2824 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2825 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2826 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2827 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2828 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2829 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2830 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2831 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2832
2833 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2834 memcpy(rstate->border_color, state->border_color.ui,
2835 sizeof(rstate->border_color));
2836 }
2837
2838 return rstate;
2839 }
2840
2841 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2842 * the si_set_sampler_view calls. LTO might help too. */
2843 static void si_set_sampler_views(struct r600_context *rctx,
2844 unsigned shader, unsigned count,
2845 struct pipe_sampler_view **views)
2846 {
2847 struct r600_textures_info *samplers = &rctx->samplers[shader];
2848 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2849 int i;
2850
2851 for (i = 0; i < count; i++) {
2852 if (views[i]) {
2853 struct r600_texture *rtex =
2854 (struct r600_texture*)views[i]->texture;
2855
2856 if (rtex->is_depth && !rtex->is_flushing_texture) {
2857 samplers->depth_texture_mask |= 1 << i;
2858 } else {
2859 samplers->depth_texture_mask &= ~(1 << i);
2860 }
2861 if (rtex->cmask.size || rtex->fmask.size) {
2862 samplers->compressed_colortex_mask |= 1 << i;
2863 } else {
2864 samplers->compressed_colortex_mask &= ~(1 << i);
2865 }
2866
2867 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2868
2869 if (rtex->fmask.size) {
2870 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2871 views[i], rviews[i]->fmask_state);
2872 } else {
2873 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2874 NULL, NULL);
2875 }
2876 } else {
2877 samplers->depth_texture_mask &= ~(1 << i);
2878 samplers->compressed_colortex_mask &= ~(1 << i);
2879 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2880 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2881 NULL, NULL);
2882 }
2883 }
2884 for (; i < samplers->n_views; i++) {
2885 samplers->depth_texture_mask &= ~(1 << i);
2886 samplers->compressed_colortex_mask &= ~(1 << i);
2887 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2888 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2889 NULL, NULL);
2890 }
2891
2892 samplers->n_views = count;
2893 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2894 }
2895
2896 static void si_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
2897 struct pipe_sampler_view **views)
2898 {
2899 struct r600_context *rctx = (struct r600_context *)ctx;
2900
2901 si_set_sampler_views(rctx, PIPE_SHADER_VERTEX, count, views);
2902 }
2903
2904 static void si_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
2905 struct pipe_sampler_view **views)
2906 {
2907 struct r600_context *rctx = (struct r600_context *)ctx;
2908
2909 si_set_sampler_views(rctx, PIPE_SHADER_FRAGMENT, count, views);
2910 }
2911
2912 static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx, unsigned count,
2913 void **states,
2914 struct r600_textures_info *samplers,
2915 unsigned user_data_reg)
2916 {
2917 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2918 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2919 uint32_t *border_color_table = NULL;
2920 int i, j;
2921
2922 if (!count)
2923 goto out;
2924
2925 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2926
2927 si_pm4_sh_data_begin(pm4);
2928 for (i = 0; i < count; i++) {
2929 if (rstates[i] &&
2930 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2931 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2932 if (!rctx->border_color_table ||
2933 ((rctx->border_color_offset + count - i) &
2934 C_008F3C_BORDER_COLOR_PTR)) {
2935 r600_resource_reference(&rctx->border_color_table, NULL);
2936 rctx->border_color_offset = 0;
2937
2938 rctx->border_color_table =
2939 r600_resource_create_custom(&rctx->screen->b.b,
2940 PIPE_USAGE_STAGING,
2941 4096 * 4 * 4);
2942 }
2943
2944 if (!border_color_table) {
2945 border_color_table =
2946 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2947 rctx->b.rings.gfx.cs,
2948 PIPE_TRANSFER_WRITE |
2949 PIPE_TRANSFER_UNSYNCHRONIZED);
2950 }
2951
2952 for (j = 0; j < 4; j++) {
2953 border_color_table[4 * rctx->border_color_offset + j] =
2954 util_le32_to_cpu(rstates[i]->border_color[j]);
2955 }
2956
2957 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2958 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2959 }
2960
2961 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2962 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2963 }
2964 }
2965 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2966
2967 if (border_color_table) {
2968 uint64_t va_offset =
2969 r600_resource_va(&rctx->screen->b.b,
2970 (void*)rctx->border_color_table);
2971
2972 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2973 if (rctx->b.chip_class >= CIK)
2974 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2975 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2976 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2977 }
2978
2979 memcpy(samplers->samplers, states, sizeof(void*) * count);
2980
2981 out:
2982 samplers->n_samplers = count;
2983 return pm4;
2984 }
2985
2986 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2987 {
2988 struct r600_context *rctx = (struct r600_context *)ctx;
2989 struct si_pm4_state *pm4;
2990
2991 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2992 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2993 si_pm4_set_state(rctx, vs_sampler, pm4);
2994 }
2995
2996 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2997 {
2998 struct r600_context *rctx = (struct r600_context *)ctx;
2999 struct si_pm4_state *pm4;
3000
3001 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
3002 R_00B030_SPI_SHADER_USER_DATA_PS_0);
3003 si_pm4_set_state(rctx, ps_sampler, pm4);
3004 }
3005
3006 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3007 {
3008 struct r600_context *rctx = (struct r600_context *)ctx;
3009 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3010 uint16_t mask = sample_mask;
3011
3012 if (pm4 == NULL)
3013 return;
3014
3015 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
3016 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
3017
3018 si_pm4_set_state(rctx, sample_mask, pm4);
3019 }
3020
3021 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3022 {
3023 free(state);
3024 }
3025
3026 /*
3027 * Vertex elements & buffers
3028 */
3029
3030 static void *si_create_vertex_elements(struct pipe_context *ctx,
3031 unsigned count,
3032 const struct pipe_vertex_element *elements)
3033 {
3034 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3035 int i;
3036
3037 assert(count < PIPE_MAX_ATTRIBS);
3038 if (!v)
3039 return NULL;
3040
3041 v->count = count;
3042 for (i = 0; i < count; ++i) {
3043 const struct util_format_description *desc;
3044 unsigned data_format, num_format;
3045 int first_non_void;
3046
3047 desc = util_format_description(elements[i].src_format);
3048 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3049 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
3050 desc, first_non_void);
3051
3052 switch (desc->channel[first_non_void].type) {
3053 case UTIL_FORMAT_TYPE_FIXED:
3054 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
3055 break;
3056 case UTIL_FORMAT_TYPE_SIGNED:
3057 if (desc->channel[first_non_void].normalized)
3058 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
3059 else if (desc->channel[first_non_void].pure_integer)
3060 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
3061 else
3062 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
3063 break;
3064 case UTIL_FORMAT_TYPE_UNSIGNED:
3065 if (desc->channel[first_non_void].normalized)
3066 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
3067 else if (desc->channel[first_non_void].pure_integer)
3068 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
3069 else
3070 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
3071 break;
3072 case UTIL_FORMAT_TYPE_FLOAT:
3073 default:
3074 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3075 }
3076
3077 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3078 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3079 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3080 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3081 S_008F0C_NUM_FORMAT(num_format) |
3082 S_008F0C_DATA_FORMAT(data_format);
3083 }
3084 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3085
3086 return v;
3087 }
3088
3089 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3090 {
3091 struct r600_context *rctx = (struct r600_context *)ctx;
3092 struct si_vertex_element *v = (struct si_vertex_element*)state;
3093
3094 rctx->vertex_elements = v;
3095 }
3096
3097 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3098 {
3099 struct r600_context *rctx = (struct r600_context *)ctx;
3100
3101 if (rctx->vertex_elements == state)
3102 rctx->vertex_elements = NULL;
3103 FREE(state);
3104 }
3105
3106 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
3107 const struct pipe_vertex_buffer *buffers)
3108 {
3109 struct r600_context *rctx = (struct r600_context *)ctx;
3110
3111 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
3112 }
3113
3114 static void si_set_index_buffer(struct pipe_context *ctx,
3115 const struct pipe_index_buffer *ib)
3116 {
3117 struct r600_context *rctx = (struct r600_context *)ctx;
3118
3119 if (ib) {
3120 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
3121 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
3122 } else {
3123 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
3124 }
3125 }
3126
3127 /*
3128 * Misc
3129 */
3130 static void si_set_polygon_stipple(struct pipe_context *ctx,
3131 const struct pipe_poly_stipple *state)
3132 {
3133 }
3134
3135 static void si_texture_barrier(struct pipe_context *ctx)
3136 {
3137 struct r600_context *rctx = (struct r600_context *)ctx;
3138
3139 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
3140 R600_CONTEXT_FLUSH_AND_INV_CB;
3141 }
3142
3143 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
3144 {
3145 struct pipe_blend_state blend;
3146
3147 memset(&blend, 0, sizeof(blend));
3148 blend.independent_blend_enable = true;
3149 blend.rt[0].colormask = 0xf;
3150 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
3151 }
3152
3153 void si_init_state_functions(struct r600_context *rctx)
3154 {
3155 int i;
3156
3157 rctx->b.b.create_blend_state = si_create_blend_state;
3158 rctx->b.b.bind_blend_state = si_bind_blend_state;
3159 rctx->b.b.delete_blend_state = si_delete_blend_state;
3160 rctx->b.b.set_blend_color = si_set_blend_color;
3161
3162 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3163 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3164 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3165
3166 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3167 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3168 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3169
3170 for (i = 0; i < 8; i++) {
3171 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3172 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3173 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3174 }
3175 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3176 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3177 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3178
3179 rctx->b.b.set_clip_state = si_set_clip_state;
3180 rctx->b.b.set_scissor_states = si_set_scissor_states;
3181 rctx->b.b.set_viewport_states = si_set_viewport_states;
3182 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3183
3184 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3185 rctx->b.b.get_sample_position = si_get_sample_position;
3186
3187 rctx->b.b.create_vs_state = si_create_vs_state;
3188 rctx->b.b.create_fs_state = si_create_fs_state;
3189 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3190 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3191 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3192 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3193
3194 rctx->b.b.create_sampler_state = si_create_sampler_state;
3195 rctx->b.b.bind_vertex_sampler_states = si_bind_vs_sampler_states;
3196 rctx->b.b.bind_fragment_sampler_states = si_bind_ps_sampler_states;
3197 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3198
3199 rctx->b.b.create_sampler_view = si_create_sampler_view;
3200 rctx->b.b.set_vertex_sampler_views = si_set_vs_sampler_views;
3201 rctx->b.b.set_fragment_sampler_views = si_set_ps_sampler_views;
3202 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3203
3204 rctx->b.b.set_sample_mask = si_set_sample_mask;
3205
3206 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3207 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3208 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3209 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3210 rctx->b.b.set_index_buffer = si_set_index_buffer;
3211
3212 rctx->b.b.texture_barrier = si_texture_barrier;
3213 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3214
3215 rctx->b.b.draw_vbo = si_draw_vbo;
3216 }
3217
3218 void si_init_config(struct r600_context *rctx)
3219 {
3220 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3221
3222 if (pm4 == NULL)
3223 return;
3224
3225 si_cmd_context_control(pm4);
3226
3227 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3228
3229 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3230 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3231 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3232 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3233 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3234 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3235 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3236 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3237 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3238 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3239 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3240 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3241 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3242 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3243 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3244 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3245 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3246 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3247 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3248 S_028AA8_SWITCH_ON_EOP(1) |
3249 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3250 S_028AA8_PRIMGROUP_SIZE(63));
3251 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3252 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3253 if (rctx->b.chip_class < CIK)
3254 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3255 S_008A14_CLIP_VTX_REORDER_ENA(1));
3256
3257 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3258 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3259 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3260
3261 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3262
3263 if (rctx->b.chip_class >= CIK) {
3264 switch (rctx->screen->b.family) {
3265 case CHIP_BONAIRE:
3266 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3267 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3268 break;
3269 case CHIP_KAVERI:
3270 /* XXX todo */
3271 case CHIP_KABINI:
3272 /* XXX todo */
3273 default:
3274 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3275 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3276 break;
3277 }
3278 } else {
3279 switch (rctx->screen->b.family) {
3280 case CHIP_TAHITI:
3281 case CHIP_PITCAIRN:
3282 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3283 break;
3284 case CHIP_VERDE:
3285 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3286 break;
3287 case CHIP_OLAND:
3288 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3289 break;
3290 case CHIP_HAINAN:
3291 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3292 break;
3293 default:
3294 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3295 break;
3296 }
3297 }
3298
3299 si_pm4_set_state(rctx, init, pm4);
3300 }