2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
36 static unsigned si_map_swizzle(unsigned swizzle
)
40 return V_008F0C_SQ_SEL_Y
;
42 return V_008F0C_SQ_SEL_Z
;
44 return V_008F0C_SQ_SEL_W
;
46 return V_008F0C_SQ_SEL_0
;
48 return V_008F0C_SQ_SEL_1
;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X
;
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x
)
58 x
>= 4096 ? 0xffff : x
* 16;
62 * Inferred framebuffer and blender state.
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
67 static void si_emit_cb_render_state(struct si_context
*sctx
)
69 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
70 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
77 cb_target_mask
&= blend
->cb_target_mask
;
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 if (blend
&& blend
->dual_src_blend
&&
86 sctx
->ps_shader
.cso
&&
87 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
90 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
92 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
93 * I think we don't have to do anything between IBs.
95 if (sctx
->screen
->dfsm_allowed
&&
96 sctx
->last_cb_target_mask
!= cb_target_mask
) {
97 sctx
->last_cb_target_mask
= cb_target_mask
;
99 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
100 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
103 if (sctx
->chip_class
>= VI
) {
104 /* DCC MSAA workaround for blending.
105 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
106 * COMBINER_DISABLE, but that would be more complicated.
108 bool oc_disable
= (sctx
->chip_class
== VI
||
109 sctx
->chip_class
== GFX9
) &&
111 blend
->blend_enable_4bit
& cb_target_mask
&&
112 sctx
->framebuffer
.nr_samples
>= 2;
114 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
115 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
116 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
117 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
));
120 /* RB+ register settings. */
121 if (sctx
->screen
->rbplus_allowed
) {
122 unsigned spi_shader_col_format
=
123 sctx
->ps_shader
.cso
?
124 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
125 unsigned sx_ps_downconvert
= 0;
126 unsigned sx_blend_opt_epsilon
= 0;
127 unsigned sx_blend_opt_control
= 0;
129 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
130 struct r600_surface
*surf
=
131 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
132 unsigned format
, swap
, spi_format
, colormask
;
133 bool has_alpha
, has_rgb
;
138 format
= G_028C70_FORMAT(surf
->cb_color_info
);
139 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
140 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
141 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
143 /* Set if RGB and A are present. */
144 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
146 if (format
== V_028C70_COLOR_8
||
147 format
== V_028C70_COLOR_16
||
148 format
== V_028C70_COLOR_32
)
149 has_rgb
= !has_alpha
;
153 /* Check the colormask and export format. */
154 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
156 if (!(colormask
& PIPE_MASK_A
))
159 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
164 /* Disable value checking for disabled channels. */
166 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
168 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
170 /* Enable down-conversion for 32bpp and smaller formats. */
172 case V_028C70_COLOR_8
:
173 case V_028C70_COLOR_8_8
:
174 case V_028C70_COLOR_8_8_8_8
:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
177 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
178 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
179 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
180 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
184 case V_028C70_COLOR_5_6_5
:
185 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
186 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
187 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
191 case V_028C70_COLOR_1_5_5_5
:
192 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
193 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
194 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
198 case V_028C70_COLOR_4_4_4_4
:
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
200 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
201 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
205 case V_028C70_COLOR_32
:
206 if (swap
== V_028C70_SWAP_STD
&&
207 spi_format
== V_028714_SPI_SHADER_32_R
)
208 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
209 else if (swap
== V_028C70_SWAP_ALT_REV
&&
210 spi_format
== V_028714_SPI_SHADER_32_AR
)
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
214 case V_028C70_COLOR_16
:
215 case V_028C70_COLOR_16_16
:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
218 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
219 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
220 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
221 if (swap
== V_028C70_SWAP_STD
||
222 swap
== V_028C70_SWAP_STD_REV
)
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
225 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
229 case V_028C70_COLOR_10_11_11
:
230 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
232 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
236 case V_028C70_COLOR_2_10_10_10
:
237 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
238 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
239 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
245 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
246 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
256 static uint32_t si_translate_blend_function(int blend_func
)
258 switch (blend_func
) {
260 return V_028780_COMB_DST_PLUS_SRC
;
261 case PIPE_BLEND_SUBTRACT
:
262 return V_028780_COMB_SRC_MINUS_DST
;
263 case PIPE_BLEND_REVERSE_SUBTRACT
:
264 return V_028780_COMB_DST_MINUS_SRC
;
266 return V_028780_COMB_MIN_DST_SRC
;
268 return V_028780_COMB_MAX_DST_SRC
;
270 PRINT_ERR("Unknown blend function %d\n", blend_func
);
277 static uint32_t si_translate_blend_factor(int blend_fact
)
279 switch (blend_fact
) {
280 case PIPE_BLENDFACTOR_ONE
:
281 return V_028780_BLEND_ONE
;
282 case PIPE_BLENDFACTOR_SRC_COLOR
:
283 return V_028780_BLEND_SRC_COLOR
;
284 case PIPE_BLENDFACTOR_SRC_ALPHA
:
285 return V_028780_BLEND_SRC_ALPHA
;
286 case PIPE_BLENDFACTOR_DST_ALPHA
:
287 return V_028780_BLEND_DST_ALPHA
;
288 case PIPE_BLENDFACTOR_DST_COLOR
:
289 return V_028780_BLEND_DST_COLOR
;
290 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
291 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
292 case PIPE_BLENDFACTOR_CONST_COLOR
:
293 return V_028780_BLEND_CONSTANT_COLOR
;
294 case PIPE_BLENDFACTOR_CONST_ALPHA
:
295 return V_028780_BLEND_CONSTANT_ALPHA
;
296 case PIPE_BLENDFACTOR_ZERO
:
297 return V_028780_BLEND_ZERO
;
298 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
299 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
300 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
301 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
302 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
303 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
304 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
305 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
306 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
307 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
308 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
309 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
310 case PIPE_BLENDFACTOR_SRC1_COLOR
:
311 return V_028780_BLEND_SRC1_COLOR
;
312 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
313 return V_028780_BLEND_SRC1_ALPHA
;
314 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
315 return V_028780_BLEND_INV_SRC1_COLOR
;
316 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
317 return V_028780_BLEND_INV_SRC1_ALPHA
;
319 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
326 static uint32_t si_translate_blend_opt_function(int blend_func
)
328 switch (blend_func
) {
330 return V_028760_OPT_COMB_ADD
;
331 case PIPE_BLEND_SUBTRACT
:
332 return V_028760_OPT_COMB_SUBTRACT
;
333 case PIPE_BLEND_REVERSE_SUBTRACT
:
334 return V_028760_OPT_COMB_REVSUBTRACT
;
336 return V_028760_OPT_COMB_MIN
;
338 return V_028760_OPT_COMB_MAX
;
340 return V_028760_OPT_COMB_BLEND_DISABLED
;
344 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
346 switch (blend_fact
) {
347 case PIPE_BLENDFACTOR_ZERO
:
348 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
349 case PIPE_BLENDFACTOR_ONE
:
350 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
351 case PIPE_BLENDFACTOR_SRC_COLOR
:
352 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
353 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
354 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
355 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
356 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
357 case PIPE_BLENDFACTOR_SRC_ALPHA
:
358 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
359 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
360 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
361 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
362 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
363 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
365 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
369 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
370 struct si_state_blend
*blend
,
371 enum pipe_blend_func func
,
372 enum pipe_blendfactor src
,
373 enum pipe_blendfactor dst
,
376 /* Src factor is allowed when it does not depend on Dst */
377 static const uint32_t src_allowed
=
378 (1u << PIPE_BLENDFACTOR_ONE
) |
379 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
380 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
381 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
382 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
383 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
384 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
385 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
386 (1u << PIPE_BLENDFACTOR_ZERO
) |
387 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
388 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
389 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
394 if (dst
== PIPE_BLENDFACTOR_ONE
&&
395 (src_allowed
& (1u << src
))) {
396 /* Addition is commutative, but floating point addition isn't
397 * associative: subtle changes can be introduced via different
400 * Out-of-order is also non-deterministic, which means that
401 * this breaks OpenGL invariance requirements. So only enable
402 * out-of-order additive blending if explicitly allowed by a
405 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
406 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
407 blend
->commutative_4bit
|= chanmask
;
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
415 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
416 unsigned *dst_factor
, unsigned expected_dst
,
417 unsigned replacement_src
)
419 if (*src_factor
== expected_dst
&&
420 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
421 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
422 *dst_factor
= replacement_src
;
424 /* Commuting the operands requires reversing subtractions. */
425 if (*func
== PIPE_BLEND_SUBTRACT
)
426 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
427 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
428 *func
= PIPE_BLEND_SUBTRACT
;
432 static bool si_blend_factor_uses_dst(unsigned factor
)
434 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
435 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
436 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
437 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
438 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
441 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
442 const struct pipe_blend_state
*state
,
445 struct si_context
*sctx
= (struct si_context
*)ctx
;
446 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
447 struct si_pm4_state
*pm4
= &blend
->pm4
;
448 uint32_t sx_mrt_blend_opt
[8] = {0};
449 uint32_t color_control
= 0;
454 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
455 blend
->alpha_to_one
= state
->alpha_to_one
;
456 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
457 blend
->logicop_enable
= state
->logicop_enable
;
459 if (state
->logicop_enable
) {
460 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
462 color_control
|= S_028808_ROP3(0xcc);
465 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
468 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
469 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
470 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
472 if (state
->alpha_to_coverage
)
473 blend
->need_src_alpha_4bit
|= 0xf;
475 blend
->cb_target_mask
= 0;
476 blend
->cb_target_enabled_4bit
= 0;
478 for (int i
= 0; i
< 8; i
++) {
479 /* state->rt entries > 0 only written if independent blending */
480 const int j
= state
->independent_blend_enable
? i
: 0;
482 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
483 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
484 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
485 unsigned eqA
= state
->rt
[j
].alpha_func
;
486 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
487 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
489 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
490 unsigned blend_cntl
= 0;
492 sx_mrt_blend_opt
[i
] =
493 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
494 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
496 /* Only set dual source blending for MRT0 to avoid a hang. */
497 if (i
>= 1 && blend
->dual_src_blend
) {
498 /* Vulkan does this for dual source blending. */
500 blend_cntl
|= S_028780_ENABLE(1);
502 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
506 /* Only addition and subtraction equations are supported with
507 * dual source blending.
509 if (blend
->dual_src_blend
&&
510 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
511 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
512 assert(!"Unsupported equation for dual source blending");
513 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
517 /* cb_render_state will disable unused ones */
518 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
519 if (state
->rt
[j
].colormask
)
520 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
522 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
523 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
527 si_blend_check_commutativity(sctx
->screen
, blend
,
528 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
529 si_blend_check_commutativity(sctx
->screen
, blend
,
530 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
532 /* Blending optimizations for RB+.
533 * These transformations don't change the behavior.
535 * First, get rid of DST in the blend factors:
536 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
538 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
539 PIPE_BLENDFACTOR_DST_COLOR
,
540 PIPE_BLENDFACTOR_SRC_COLOR
);
541 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
542 PIPE_BLENDFACTOR_DST_COLOR
,
543 PIPE_BLENDFACTOR_SRC_COLOR
);
544 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
545 PIPE_BLENDFACTOR_DST_ALPHA
,
546 PIPE_BLENDFACTOR_SRC_ALPHA
);
548 /* Look up the ideal settings from tables. */
549 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
550 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
551 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
552 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
554 /* Handle interdependencies. */
555 if (si_blend_factor_uses_dst(srcRGB
))
556 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
557 if (si_blend_factor_uses_dst(srcA
))
558 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
560 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
561 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
562 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
563 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
564 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
566 /* Set the final value. */
567 sx_mrt_blend_opt
[i
] =
568 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
569 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
570 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
571 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
572 S_028760_ALPHA_DST_OPT(dstA_opt
) |
573 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
575 /* Set blend state. */
576 blend_cntl
|= S_028780_ENABLE(1);
577 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
578 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
579 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
581 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
582 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
583 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
584 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
585 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
587 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
589 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
591 /* This is only important for formats without alpha. */
592 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
593 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
594 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
595 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
596 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
597 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
598 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
601 if (blend
->cb_target_mask
) {
602 color_control
|= S_028808_MODE(mode
);
604 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
607 if (sctx
->screen
->rbplus_allowed
) {
608 /* Disable RB+ blend optimizations for dual source blending.
611 if (blend
->dual_src_blend
) {
612 for (int i
= 0; i
< 8; i
++) {
613 sx_mrt_blend_opt
[i
] =
614 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
615 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
619 for (int i
= 0; i
< 8; i
++)
620 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
621 sx_mrt_blend_opt
[i
]);
623 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
624 if (blend
->dual_src_blend
|| state
->logicop_enable
||
625 mode
== V_028808_CB_RESOLVE
)
626 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
629 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
633 static void *si_create_blend_state(struct pipe_context
*ctx
,
634 const struct pipe_blend_state
*state
)
636 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
639 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
641 struct si_context
*sctx
= (struct si_context
*)ctx
;
642 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
643 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
648 si_pm4_bind_state(sctx
, blend
, state
);
651 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
652 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
653 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
654 sctx
->framebuffer
.nr_samples
>= 2 &&
655 sctx
->screen
->dcc_msaa_allowed
))
656 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
659 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
660 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
661 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
662 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
663 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
664 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
665 sctx
->do_update_shaders
= true;
667 if (sctx
->screen
->dpbb_allowed
&&
669 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
670 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
671 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
672 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
674 if (sctx
->screen
->has_out_of_order_rast
&&
676 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
677 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
678 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
679 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
680 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
683 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
685 struct si_context
*sctx
= (struct si_context
*)ctx
;
686 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
689 static void si_set_blend_color(struct pipe_context
*ctx
,
690 const struct pipe_blend_color
*state
)
692 struct si_context
*sctx
= (struct si_context
*)ctx
;
693 static const struct pipe_blend_color zeros
;
695 sctx
->blend_color
.state
= *state
;
696 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
697 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
700 static void si_emit_blend_color(struct si_context
*sctx
)
702 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
704 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
705 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
712 static void si_set_clip_state(struct pipe_context
*ctx
,
713 const struct pipe_clip_state
*state
)
715 struct si_context
*sctx
= (struct si_context
*)ctx
;
716 struct pipe_constant_buffer cb
;
717 static const struct pipe_clip_state zeros
;
719 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
722 sctx
->clip_state
.state
= *state
;
723 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
724 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
727 cb
.user_buffer
= state
->ucp
;
728 cb
.buffer_offset
= 0;
729 cb
.buffer_size
= 4*4*8;
730 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
731 pipe_resource_reference(&cb
.buffer
, NULL
);
734 static void si_emit_clip_state(struct si_context
*sctx
)
736 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
738 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
739 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
742 static void si_emit_clip_regs(struct si_context
*sctx
)
744 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
745 struct si_shader
*vs
= si_get_vs_state(sctx
);
746 struct si_shader_selector
*vs_sel
= vs
->selector
;
747 struct tgsi_shader_info
*info
= &vs_sel
->info
;
748 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
749 unsigned window_space
=
750 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
751 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
752 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
753 unsigned culldist_mask
= vs_sel
->culldist_mask
;
756 if (vs
->key
.opt
.clip_disable
) {
757 assert(!info
->culldist_writemask
);
761 total_mask
= clipdist_mask
| culldist_mask
;
763 /* Clip distances on points have no effect, so need to be implemented
764 * as cull distances. This applies for the clipvertex case as well.
766 * Setting this for primitives other than points should have no adverse
769 clipdist_mask
&= rs
->clip_plane_enable
;
770 culldist_mask
|= clipdist_mask
;
772 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
773 vs_sel
->pa_cl_vs_out_cntl
|
774 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
775 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
776 clipdist_mask
| (culldist_mask
<< 8));
777 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
778 rs
->pa_cl_clip_cntl
|
780 S_028810_CLIP_DISABLE(window_space
));
784 * inferred state between framebuffer and rasterizer
786 static void si_update_poly_offset_state(struct si_context
*sctx
)
788 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
790 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
791 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
795 /* Use the user format, not db_render_format, so that the polygon
796 * offset behaves as expected by applications.
798 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
799 case PIPE_FORMAT_Z16_UNORM
:
800 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
802 default: /* 24-bit */
803 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
805 case PIPE_FORMAT_Z32_FLOAT
:
806 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
807 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
816 static uint32_t si_translate_fill(uint32_t func
)
819 case PIPE_POLYGON_MODE_FILL
:
820 return V_028814_X_DRAW_TRIANGLES
;
821 case PIPE_POLYGON_MODE_LINE
:
822 return V_028814_X_DRAW_LINES
;
823 case PIPE_POLYGON_MODE_POINT
:
824 return V_028814_X_DRAW_POINTS
;
827 return V_028814_X_DRAW_POINTS
;
831 static void *si_create_rs_state(struct pipe_context
*ctx
,
832 const struct pipe_rasterizer_state
*state
)
834 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
835 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
836 struct si_pm4_state
*pm4
= &rs
->pm4
;
838 float psize_min
, psize_max
;
844 rs
->scissor_enable
= state
->scissor
;
845 rs
->clip_halfz
= state
->clip_halfz
;
846 rs
->two_side
= state
->light_twoside
;
847 rs
->multisample_enable
= state
->multisample
;
848 rs
->force_persample_interp
= state
->force_persample_interp
;
849 rs
->clip_plane_enable
= state
->clip_plane_enable
;
850 rs
->line_stipple_enable
= state
->line_stipple_enable
;
851 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
852 rs
->line_smooth
= state
->line_smooth
;
853 rs
->line_width
= state
->line_width
;
854 rs
->poly_smooth
= state
->poly_smooth
;
855 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
857 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
858 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
859 rs
->flatshade
= state
->flatshade
;
860 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
861 rs
->rasterizer_discard
= state
->rasterizer_discard
;
862 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
863 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
864 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
865 rs
->pa_cl_clip_cntl
=
866 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
867 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
868 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
869 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
870 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
872 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
873 S_0286D4_FLAT_SHADE_ENA(1) |
874 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
875 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
876 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
877 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
878 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
879 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
881 /* point size 12.4 fixed point */
882 tmp
= (unsigned)(state
->point_size
* 8.0);
883 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
885 if (state
->point_size_per_vertex
) {
886 psize_min
= util_get_min_point_size(state
);
889 /* Force the point size to be as if the vertex output was disabled. */
890 psize_min
= state
->point_size
;
891 psize_max
= state
->point_size
;
893 rs
->max_point_size
= psize_max
;
895 /* Divide by two, because 0.5 = 1 pixel. */
896 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
897 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
898 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
900 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
901 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
902 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
903 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
904 S_028A48_MSAA_ENABLE(state
->multisample
||
905 state
->poly_smooth
||
906 state
->line_smooth
) |
907 S_028A48_VPORT_SCISSOR_ENABLE(1) |
908 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
910 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
911 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
912 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
914 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
915 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
916 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
917 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
918 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
919 S_028814_FACE(!state
->front_ccw
) |
920 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
921 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
922 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
923 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
924 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
925 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
926 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
928 if (!rs
->uses_poly_offset
)
931 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
932 if (!rs
->pm4_poly_offset
) {
937 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
938 for (i
= 0; i
< 3; i
++) {
939 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
940 float offset_units
= state
->offset_units
;
941 float offset_scale
= state
->offset_scale
* 16.0f
;
942 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
944 if (!state
->offset_units_unscaled
) {
946 case 0: /* 16-bit zbuffer */
947 offset_units
*= 4.0f
;
948 pa_su_poly_offset_db_fmt_cntl
=
949 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
951 case 1: /* 24-bit zbuffer */
952 offset_units
*= 2.0f
;
953 pa_su_poly_offset_db_fmt_cntl
=
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
956 case 2: /* 32-bit zbuffer */
957 offset_units
*= 1.0f
;
958 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
959 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
964 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
966 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
968 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
970 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
972 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
973 pa_su_poly_offset_db_fmt_cntl
);
979 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
981 struct si_context
*sctx
= (struct si_context
*)ctx
;
982 struct si_state_rasterizer
*old_rs
=
983 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
984 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
989 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
990 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
992 /* Update the small primitive filter workaround if necessary. */
993 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
994 sctx
->framebuffer
.nr_samples
> 1)
995 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
998 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
999 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1001 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1002 si_update_poly_offset_state(sctx
);
1005 (old_rs
->scissor_enable
!= rs
->scissor_enable
||
1006 old_rs
->line_width
!= rs
->line_width
||
1007 old_rs
->max_point_size
!= rs
->max_point_size
)) {
1008 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1009 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1013 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1014 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1015 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1019 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1020 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1021 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1023 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1024 rs
->line_stipple_enable
;
1027 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1028 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1029 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1030 old_rs
->flatshade
!= rs
->flatshade
||
1031 old_rs
->two_side
!= rs
->two_side
||
1032 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1033 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1034 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1035 old_rs
->line_smooth
!= rs
->line_smooth
||
1036 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1037 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1038 sctx
->do_update_shaders
= true;
1041 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1043 struct si_context
*sctx
= (struct si_context
*)ctx
;
1044 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1046 if (sctx
->queued
.named
.rasterizer
== state
)
1047 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1049 FREE(rs
->pm4_poly_offset
);
1050 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1054 * infeered state between dsa and stencil ref
1056 static void si_emit_stencil_ref(struct si_context
*sctx
)
1058 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
1059 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1060 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1062 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1063 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1064 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1065 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1066 S_028430_STENCILOPVAL(1));
1067 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1068 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1069 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1070 S_028434_STENCILOPVAL_BF(1));
1073 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1074 const struct pipe_stencil_ref
*state
)
1076 struct si_context
*sctx
= (struct si_context
*)ctx
;
1078 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1081 sctx
->stencil_ref
.state
= *state
;
1082 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1090 static uint32_t si_translate_stencil_op(int s_op
)
1093 case PIPE_STENCIL_OP_KEEP
:
1094 return V_02842C_STENCIL_KEEP
;
1095 case PIPE_STENCIL_OP_ZERO
:
1096 return V_02842C_STENCIL_ZERO
;
1097 case PIPE_STENCIL_OP_REPLACE
:
1098 return V_02842C_STENCIL_REPLACE_TEST
;
1099 case PIPE_STENCIL_OP_INCR
:
1100 return V_02842C_STENCIL_ADD_CLAMP
;
1101 case PIPE_STENCIL_OP_DECR
:
1102 return V_02842C_STENCIL_SUB_CLAMP
;
1103 case PIPE_STENCIL_OP_INCR_WRAP
:
1104 return V_02842C_STENCIL_ADD_WRAP
;
1105 case PIPE_STENCIL_OP_DECR_WRAP
:
1106 return V_02842C_STENCIL_SUB_WRAP
;
1107 case PIPE_STENCIL_OP_INVERT
:
1108 return V_02842C_STENCIL_INVERT
;
1110 PRINT_ERR("Unknown stencil op %d", s_op
);
1117 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1119 return s
->enabled
&& s
->writemask
&&
1120 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1121 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1122 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1125 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1127 /* REPLACE is normally order invariant, except when the stencil
1128 * reference value is written by the fragment shader. Tracking this
1129 * interaction does not seem worth the effort, so be conservative. */
1130 return op
!= PIPE_STENCIL_OP_INCR
&&
1131 op
!= PIPE_STENCIL_OP_DECR
&&
1132 op
!= PIPE_STENCIL_OP_REPLACE
;
1135 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1136 * invariant in the sense that the set of passing fragments as well as the
1137 * final stencil buffer result does not depend on the order of fragments. */
1138 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1140 return !state
->enabled
|| !state
->writemask
||
1141 /* The following assumes that Z writes are disabled. */
1142 (state
->func
== PIPE_FUNC_ALWAYS
&&
1143 si_order_invariant_stencil_op(state
->zpass_op
) &&
1144 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1145 (state
->func
== PIPE_FUNC_NEVER
&&
1146 si_order_invariant_stencil_op(state
->fail_op
));
1149 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1150 const struct pipe_depth_stencil_alpha_state
*state
)
1152 struct si_context
*sctx
= (struct si_context
*)ctx
;
1153 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1154 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1155 unsigned db_depth_control
;
1156 uint32_t db_stencil_control
= 0;
1162 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1163 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1164 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1165 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1167 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1168 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1169 S_028800_ZFUNC(state
->depth
.func
) |
1170 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1173 if (state
->stencil
[0].enabled
) {
1174 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1175 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1176 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1177 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1178 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1180 if (state
->stencil
[1].enabled
) {
1181 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1182 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1183 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1184 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1185 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1190 if (state
->alpha
.enabled
) {
1191 dsa
->alpha_func
= state
->alpha
.func
;
1193 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1194 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1196 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1199 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1200 if (state
->stencil
[0].enabled
)
1201 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1202 if (state
->depth
.bounds_test
) {
1203 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1204 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1207 dsa
->depth_enabled
= state
->depth
.enabled
;
1208 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1209 state
->depth
.writemask
;
1210 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1211 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1212 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1213 si_dsa_writes_stencil(&state
->stencil
[1]));
1214 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1215 dsa
->stencil_write_enabled
;
1217 bool zfunc_is_ordered
=
1218 state
->depth
.func
== PIPE_FUNC_NEVER
||
1219 state
->depth
.func
== PIPE_FUNC_LESS
||
1220 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1221 state
->depth
.func
== PIPE_FUNC_GREATER
||
1222 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1224 bool nozwrite_and_order_invariant_stencil
=
1225 !dsa
->db_can_write
||
1226 (!dsa
->depth_write_enabled
&&
1227 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1228 si_order_invariant_stencil_state(&state
->stencil
[1]));
1230 dsa
->order_invariance
[1].zs
=
1231 nozwrite_and_order_invariant_stencil
||
1232 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1233 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1235 dsa
->order_invariance
[1].pass_set
=
1236 nozwrite_and_order_invariant_stencil
||
1237 (!dsa
->stencil_write_enabled
&&
1238 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1239 state
->depth
.func
== PIPE_FUNC_NEVER
));
1240 dsa
->order_invariance
[0].pass_set
=
1241 !dsa
->depth_write_enabled
||
1242 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1243 state
->depth
.func
== PIPE_FUNC_NEVER
);
1245 dsa
->order_invariance
[1].pass_last
=
1246 sctx
->screen
->assume_no_z_fights
&&
1247 !dsa
->stencil_write_enabled
&&
1248 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1249 dsa
->order_invariance
[0].pass_last
=
1250 sctx
->screen
->assume_no_z_fights
&&
1251 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1256 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1258 struct si_context
*sctx
= (struct si_context
*)ctx
;
1259 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1260 struct si_state_dsa
*dsa
= state
;
1265 si_pm4_bind_state(sctx
, dsa
, dsa
);
1267 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1268 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1269 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1270 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1273 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1274 sctx
->do_update_shaders
= true;
1276 if (sctx
->screen
->dpbb_allowed
&&
1278 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1279 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1280 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1281 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1283 if (sctx
->screen
->has_out_of_order_rast
&&
1285 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1286 sizeof(old_dsa
->order_invariance
))))
1287 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1290 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1292 struct si_context
*sctx
= (struct si_context
*)ctx
;
1293 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1296 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1298 struct pipe_depth_stencil_alpha_state dsa
= {};
1300 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1303 /* DB RENDER STATE */
1305 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1307 struct si_context
*sctx
= (struct si_context
*)ctx
;
1309 /* Pipeline stat & streamout queries. */
1311 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1312 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1314 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1315 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1318 /* Occlusion queries. */
1319 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1320 sctx
->occlusion_queries_disabled
= !enable
;
1321 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1325 void si_set_occlusion_query_state(struct si_context
*sctx
,
1326 bool old_perfect_enable
)
1328 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1330 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1332 if (perfect_enable
!= old_perfect_enable
)
1333 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1336 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1338 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1340 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1341 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1344 static void si_emit_db_render_state(struct si_context
*sctx
)
1346 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
1347 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1348 unsigned db_shader_control
;
1350 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1352 /* DB_RENDER_CONTROL */
1353 if (sctx
->dbcb_depth_copy_enabled
||
1354 sctx
->dbcb_stencil_copy_enabled
) {
1356 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1357 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1358 S_028000_COPY_CENTROID(1) |
1359 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1360 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1362 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1363 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1366 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1367 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1370 /* DB_COUNT_CONTROL (occlusion queries) */
1371 if (sctx
->num_occlusion_queries
> 0 &&
1372 !sctx
->occlusion_queries_disabled
) {
1373 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1375 if (sctx
->chip_class
>= CIK
) {
1377 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1378 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1379 S_028004_ZPASS_ENABLE(1) |
1380 S_028004_SLICE_EVEN_ENABLE(1) |
1381 S_028004_SLICE_ODD_ENABLE(1));
1384 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1385 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1388 /* Disable occlusion queries. */
1389 if (sctx
->chip_class
>= CIK
) {
1392 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1396 /* DB_RENDER_OVERRIDE2 */
1397 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1398 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1399 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1400 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1402 db_shader_control
= sctx
->ps_db_shader_control
;
1404 /* Bug workaround for smoothing (overrasterization) on SI. */
1405 if (sctx
->chip_class
== SI
&& sctx
->smoothing_enabled
) {
1406 db_shader_control
&= C_02880C_Z_ORDER
;
1407 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1410 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1411 if (!rs
|| !rs
->multisample_enable
)
1412 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1414 if (sctx
->screen
->has_rbplus
&&
1415 !sctx
->screen
->rbplus_allowed
)
1416 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1418 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1423 * format translation
1425 static uint32_t si_translate_colorformat(enum pipe_format format
)
1427 const struct util_format_description
*desc
= util_format_description(format
);
1429 return V_028C70_COLOR_INVALID
;
1431 #define HAS_SIZE(x,y,z,w) \
1432 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1433 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1435 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1436 return V_028C70_COLOR_10_11_11
;
1438 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1439 return V_028C70_COLOR_INVALID
;
1441 /* hw cannot support mixed formats (except depth/stencil, since
1442 * stencil is not written to). */
1443 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1444 return V_028C70_COLOR_INVALID
;
1446 switch (desc
->nr_channels
) {
1448 switch (desc
->channel
[0].size
) {
1450 return V_028C70_COLOR_8
;
1452 return V_028C70_COLOR_16
;
1454 return V_028C70_COLOR_32
;
1458 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1459 switch (desc
->channel
[0].size
) {
1461 return V_028C70_COLOR_8_8
;
1463 return V_028C70_COLOR_16_16
;
1465 return V_028C70_COLOR_32_32
;
1467 } else if (HAS_SIZE(8,24,0,0)) {
1468 return V_028C70_COLOR_24_8
;
1469 } else if (HAS_SIZE(24,8,0,0)) {
1470 return V_028C70_COLOR_8_24
;
1474 if (HAS_SIZE(5,6,5,0)) {
1475 return V_028C70_COLOR_5_6_5
;
1476 } else if (HAS_SIZE(32,8,24,0)) {
1477 return V_028C70_COLOR_X24_8_32_FLOAT
;
1481 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1482 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1483 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1484 switch (desc
->channel
[0].size
) {
1486 return V_028C70_COLOR_4_4_4_4
;
1488 return V_028C70_COLOR_8_8_8_8
;
1490 return V_028C70_COLOR_16_16_16_16
;
1492 return V_028C70_COLOR_32_32_32_32
;
1494 } else if (HAS_SIZE(5,5,5,1)) {
1495 return V_028C70_COLOR_1_5_5_5
;
1496 } else if (HAS_SIZE(1,5,5,5)) {
1497 return V_028C70_COLOR_5_5_5_1
;
1498 } else if (HAS_SIZE(10,10,10,2)) {
1499 return V_028C70_COLOR_2_10_10_10
;
1503 return V_028C70_COLOR_INVALID
;
1506 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1508 if (SI_BIG_ENDIAN
) {
1509 switch(colorformat
) {
1510 /* 8-bit buffers. */
1511 case V_028C70_COLOR_8
:
1512 return V_028C70_ENDIAN_NONE
;
1514 /* 16-bit buffers. */
1515 case V_028C70_COLOR_5_6_5
:
1516 case V_028C70_COLOR_1_5_5_5
:
1517 case V_028C70_COLOR_4_4_4_4
:
1518 case V_028C70_COLOR_16
:
1519 case V_028C70_COLOR_8_8
:
1520 return V_028C70_ENDIAN_8IN16
;
1522 /* 32-bit buffers. */
1523 case V_028C70_COLOR_8_8_8_8
:
1524 case V_028C70_COLOR_2_10_10_10
:
1525 case V_028C70_COLOR_8_24
:
1526 case V_028C70_COLOR_24_8
:
1527 case V_028C70_COLOR_16_16
:
1528 return V_028C70_ENDIAN_8IN32
;
1530 /* 64-bit buffers. */
1531 case V_028C70_COLOR_16_16_16_16
:
1532 return V_028C70_ENDIAN_8IN16
;
1534 case V_028C70_COLOR_32_32
:
1535 return V_028C70_ENDIAN_8IN32
;
1537 /* 128-bit buffers. */
1538 case V_028C70_COLOR_32_32_32_32
:
1539 return V_028C70_ENDIAN_8IN32
;
1541 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1544 return V_028C70_ENDIAN_NONE
;
1548 static uint32_t si_translate_dbformat(enum pipe_format format
)
1551 case PIPE_FORMAT_Z16_UNORM
:
1552 return V_028040_Z_16
;
1553 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1554 case PIPE_FORMAT_X8Z24_UNORM
:
1555 case PIPE_FORMAT_Z24X8_UNORM
:
1556 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1557 return V_028040_Z_24
; /* deprecated on SI */
1558 case PIPE_FORMAT_Z32_FLOAT
:
1559 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1560 return V_028040_Z_32_FLOAT
;
1562 return V_028040_Z_INVALID
;
1567 * Texture translation
1570 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1571 enum pipe_format format
,
1572 const struct util_format_description
*desc
,
1575 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1576 bool enable_compressed_formats
= (sscreen
->info
.drm_major
== 2 &&
1577 sscreen
->info
.drm_minor
>= 31) ||
1578 sscreen
->info
.drm_major
== 3;
1579 bool uniform
= true;
1582 /* Colorspace (return non-RGB formats directly). */
1583 switch (desc
->colorspace
) {
1584 /* Depth stencil formats */
1585 case UTIL_FORMAT_COLORSPACE_ZS
:
1587 case PIPE_FORMAT_Z16_UNORM
:
1588 return V_008F14_IMG_DATA_FORMAT_16
;
1589 case PIPE_FORMAT_X24S8_UINT
:
1590 case PIPE_FORMAT_S8X24_UINT
:
1592 * Implemented as an 8_8_8_8 data format to fix texture
1593 * gathers in stencil sampling. This affects at least
1594 * GL45-CTS.texture_cube_map_array.sampling on VI.
1596 if (sscreen
->info
.chip_class
<= VI
)
1597 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1599 if (format
== PIPE_FORMAT_X24S8_UINT
)
1600 return V_008F14_IMG_DATA_FORMAT_8_24
;
1602 return V_008F14_IMG_DATA_FORMAT_24_8
;
1603 case PIPE_FORMAT_Z24X8_UNORM
:
1604 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1605 return V_008F14_IMG_DATA_FORMAT_8_24
;
1606 case PIPE_FORMAT_X8Z24_UNORM
:
1607 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1608 return V_008F14_IMG_DATA_FORMAT_24_8
;
1609 case PIPE_FORMAT_S8_UINT
:
1610 return V_008F14_IMG_DATA_FORMAT_8
;
1611 case PIPE_FORMAT_Z32_FLOAT
:
1612 return V_008F14_IMG_DATA_FORMAT_32
;
1613 case PIPE_FORMAT_X32_S8X24_UINT
:
1614 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1615 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1620 case UTIL_FORMAT_COLORSPACE_YUV
:
1621 goto out_unknown
; /* TODO */
1623 case UTIL_FORMAT_COLORSPACE_SRGB
:
1624 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1632 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1633 if (!enable_compressed_formats
)
1637 case PIPE_FORMAT_RGTC1_SNORM
:
1638 case PIPE_FORMAT_LATC1_SNORM
:
1639 case PIPE_FORMAT_RGTC1_UNORM
:
1640 case PIPE_FORMAT_LATC1_UNORM
:
1641 return V_008F14_IMG_DATA_FORMAT_BC4
;
1642 case PIPE_FORMAT_RGTC2_SNORM
:
1643 case PIPE_FORMAT_LATC2_SNORM
:
1644 case PIPE_FORMAT_RGTC2_UNORM
:
1645 case PIPE_FORMAT_LATC2_UNORM
:
1646 return V_008F14_IMG_DATA_FORMAT_BC5
;
1652 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1653 (sscreen
->info
.family
== CHIP_STONEY
||
1654 sscreen
->info
.family
== CHIP_VEGA10
||
1655 sscreen
->info
.family
== CHIP_RAVEN
)) {
1657 case PIPE_FORMAT_ETC1_RGB8
:
1658 case PIPE_FORMAT_ETC2_RGB8
:
1659 case PIPE_FORMAT_ETC2_SRGB8
:
1660 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1661 case PIPE_FORMAT_ETC2_RGB8A1
:
1662 case PIPE_FORMAT_ETC2_SRGB8A1
:
1663 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1664 case PIPE_FORMAT_ETC2_RGBA8
:
1665 case PIPE_FORMAT_ETC2_SRGBA8
:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1667 case PIPE_FORMAT_ETC2_R11_UNORM
:
1668 case PIPE_FORMAT_ETC2_R11_SNORM
:
1669 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1670 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1671 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1672 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1678 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1679 if (!enable_compressed_formats
)
1683 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1684 case PIPE_FORMAT_BPTC_SRGBA
:
1685 return V_008F14_IMG_DATA_FORMAT_BC7
;
1686 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1687 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1688 return V_008F14_IMG_DATA_FORMAT_BC6
;
1694 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1696 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1697 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1698 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1699 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1700 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1701 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1707 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1708 if (!enable_compressed_formats
)
1712 case PIPE_FORMAT_DXT1_RGB
:
1713 case PIPE_FORMAT_DXT1_RGBA
:
1714 case PIPE_FORMAT_DXT1_SRGB
:
1715 case PIPE_FORMAT_DXT1_SRGBA
:
1716 return V_008F14_IMG_DATA_FORMAT_BC1
;
1717 case PIPE_FORMAT_DXT3_RGBA
:
1718 case PIPE_FORMAT_DXT3_SRGBA
:
1719 return V_008F14_IMG_DATA_FORMAT_BC2
;
1720 case PIPE_FORMAT_DXT5_RGBA
:
1721 case PIPE_FORMAT_DXT5_SRGBA
:
1722 return V_008F14_IMG_DATA_FORMAT_BC3
;
1728 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1729 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1730 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1731 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1734 /* R8G8Bx_SNORM - TODO CxV8U8 */
1736 /* hw cannot support mixed formats (except depth/stencil, since only
1738 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1741 /* See whether the components are of the same size. */
1742 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1743 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1746 /* Non-uniform formats. */
1748 switch(desc
->nr_channels
) {
1750 if (desc
->channel
[0].size
== 5 &&
1751 desc
->channel
[1].size
== 6 &&
1752 desc
->channel
[2].size
== 5) {
1753 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1757 if (desc
->channel
[0].size
== 5 &&
1758 desc
->channel
[1].size
== 5 &&
1759 desc
->channel
[2].size
== 5 &&
1760 desc
->channel
[3].size
== 1) {
1761 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1763 if (desc
->channel
[0].size
== 1 &&
1764 desc
->channel
[1].size
== 5 &&
1765 desc
->channel
[2].size
== 5 &&
1766 desc
->channel
[3].size
== 5) {
1767 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1769 if (desc
->channel
[0].size
== 10 &&
1770 desc
->channel
[1].size
== 10 &&
1771 desc
->channel
[2].size
== 10 &&
1772 desc
->channel
[3].size
== 2) {
1773 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1780 if (first_non_void
< 0 || first_non_void
> 3)
1783 /* uniform formats */
1784 switch (desc
->channel
[first_non_void
].size
) {
1786 switch (desc
->nr_channels
) {
1787 #if 0 /* Not supported for render targets */
1789 return V_008F14_IMG_DATA_FORMAT_4_4
;
1792 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1796 switch (desc
->nr_channels
) {
1798 return V_008F14_IMG_DATA_FORMAT_8
;
1800 return V_008F14_IMG_DATA_FORMAT_8_8
;
1802 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1806 switch (desc
->nr_channels
) {
1808 return V_008F14_IMG_DATA_FORMAT_16
;
1810 return V_008F14_IMG_DATA_FORMAT_16_16
;
1812 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1816 switch (desc
->nr_channels
) {
1818 return V_008F14_IMG_DATA_FORMAT_32
;
1820 return V_008F14_IMG_DATA_FORMAT_32_32
;
1821 #if 0 /* Not supported for render targets */
1823 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1826 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1834 static unsigned si_tex_wrap(unsigned wrap
)
1838 case PIPE_TEX_WRAP_REPEAT
:
1839 return V_008F30_SQ_TEX_WRAP
;
1840 case PIPE_TEX_WRAP_CLAMP
:
1841 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1842 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1843 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1844 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1845 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1846 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1847 return V_008F30_SQ_TEX_MIRROR
;
1848 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1849 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1850 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1851 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1852 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1853 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1857 static unsigned si_tex_mipfilter(unsigned filter
)
1860 case PIPE_TEX_MIPFILTER_NEAREST
:
1861 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1862 case PIPE_TEX_MIPFILTER_LINEAR
:
1863 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1865 case PIPE_TEX_MIPFILTER_NONE
:
1866 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1870 static unsigned si_tex_compare(unsigned compare
)
1874 case PIPE_FUNC_NEVER
:
1875 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1876 case PIPE_FUNC_LESS
:
1877 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1878 case PIPE_FUNC_EQUAL
:
1879 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1880 case PIPE_FUNC_LEQUAL
:
1881 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1882 case PIPE_FUNC_GREATER
:
1883 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1884 case PIPE_FUNC_NOTEQUAL
:
1885 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1886 case PIPE_FUNC_GEQUAL
:
1887 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1888 case PIPE_FUNC_ALWAYS
:
1889 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1893 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1894 unsigned view_target
, unsigned nr_samples
)
1896 unsigned res_target
= rtex
->buffer
.b
.b
.target
;
1898 if (view_target
== PIPE_TEXTURE_CUBE
||
1899 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1900 res_target
= view_target
;
1901 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1902 else if (res_target
== PIPE_TEXTURE_CUBE
||
1903 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1904 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1906 /* GFX9 allocates 1D textures as 2D. */
1907 if ((res_target
== PIPE_TEXTURE_1D
||
1908 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1909 sscreen
->info
.chip_class
>= GFX9
&&
1910 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1911 if (res_target
== PIPE_TEXTURE_1D
)
1912 res_target
= PIPE_TEXTURE_2D
;
1914 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1917 switch (res_target
) {
1919 case PIPE_TEXTURE_1D
:
1920 return V_008F1C_SQ_RSRC_IMG_1D
;
1921 case PIPE_TEXTURE_1D_ARRAY
:
1922 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1923 case PIPE_TEXTURE_2D
:
1924 case PIPE_TEXTURE_RECT
:
1925 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1926 V_008F1C_SQ_RSRC_IMG_2D
;
1927 case PIPE_TEXTURE_2D_ARRAY
:
1928 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1929 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1930 case PIPE_TEXTURE_3D
:
1931 return V_008F1C_SQ_RSRC_IMG_3D
;
1932 case PIPE_TEXTURE_CUBE
:
1933 case PIPE_TEXTURE_CUBE_ARRAY
:
1934 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1939 * Format support testing
1942 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1944 const struct util_format_description
*desc
= util_format_description(format
);
1948 return si_translate_texformat(screen
, format
, desc
,
1949 util_format_get_first_non_void_channel(format
)) != ~0U;
1952 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1953 const struct util_format_description
*desc
,
1958 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1959 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1961 assert(first_non_void
>= 0);
1963 if (desc
->nr_channels
== 4 &&
1964 desc
->channel
[0].size
== 10 &&
1965 desc
->channel
[1].size
== 10 &&
1966 desc
->channel
[2].size
== 10 &&
1967 desc
->channel
[3].size
== 2)
1968 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1970 /* See whether the components are of the same size. */
1971 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1972 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1973 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1976 switch (desc
->channel
[first_non_void
].size
) {
1978 switch (desc
->nr_channels
) {
1980 case 3: /* 3 loads */
1981 return V_008F0C_BUF_DATA_FORMAT_8
;
1983 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1985 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1989 switch (desc
->nr_channels
) {
1991 case 3: /* 3 loads */
1992 return V_008F0C_BUF_DATA_FORMAT_16
;
1994 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1996 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2000 switch (desc
->nr_channels
) {
2002 return V_008F0C_BUF_DATA_FORMAT_32
;
2004 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2006 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2008 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2012 /* Legacy double formats. */
2013 switch (desc
->nr_channels
) {
2014 case 1: /* 1 load */
2015 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2016 case 2: /* 1 load */
2017 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2018 case 3: /* 3 loads */
2019 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2020 case 4: /* 2 loads */
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2026 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2029 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2030 const struct util_format_description
*desc
,
2033 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2034 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2036 assert(first_non_void
>= 0);
2038 switch (desc
->channel
[first_non_void
].type
) {
2039 case UTIL_FORMAT_TYPE_SIGNED
:
2040 case UTIL_FORMAT_TYPE_FIXED
:
2041 if (desc
->channel
[first_non_void
].size
>= 32 ||
2042 desc
->channel
[first_non_void
].pure_integer
)
2043 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2044 else if (desc
->channel
[first_non_void
].normalized
)
2045 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2047 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2049 case UTIL_FORMAT_TYPE_UNSIGNED
:
2050 if (desc
->channel
[first_non_void
].size
>= 32 ||
2051 desc
->channel
[first_non_void
].pure_integer
)
2052 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2053 else if (desc
->channel
[first_non_void
].normalized
)
2054 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2056 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2058 case UTIL_FORMAT_TYPE_FLOAT
:
2060 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2064 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2065 enum pipe_format format
,
2068 const struct util_format_description
*desc
;
2070 unsigned data_format
;
2072 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2073 PIPE_BIND_SAMPLER_VIEW
|
2074 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2076 desc
= util_format_description(format
);
2080 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2081 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2082 * for read-only access (with caveats surrounding bounds checks), but
2083 * obviously fails for write access which we have to implement for
2084 * shader images. Luckily, OpenGL doesn't expect this to be supported
2085 * anyway, and so the only impact is on PBO uploads / downloads, which
2086 * shouldn't be expected to be fast for GL_RGB anyway.
2088 if (desc
->block
.bits
== 3 * 8 ||
2089 desc
->block
.bits
== 3 * 16) {
2090 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2091 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2097 first_non_void
= util_format_get_first_non_void_channel(format
);
2098 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2099 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2105 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2107 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2108 si_translate_colorswap(format
, false) != ~0U;
2111 static bool si_is_zs_format_supported(enum pipe_format format
)
2113 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2116 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2117 enum pipe_format format
,
2118 enum pipe_texture_target target
,
2119 unsigned sample_count
,
2122 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2123 unsigned retval
= 0;
2125 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2126 PRINT_ERR("r600: unsupported texture type %d\n", target
);
2130 if (!util_format_is_supported(format
, usage
))
2133 if (sample_count
> 1) {
2134 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2137 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2140 switch (sample_count
) {
2146 /* Allow resource_copy_region with nr_samples == 16. */
2147 if (sscreen
->eqaa_force_coverage_samples
== 16 &&
2148 !util_format_is_depth_or_stencil(format
))
2150 if (format
== PIPE_FORMAT_NONE
)
2159 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2160 PIPE_BIND_SHADER_IMAGE
)) {
2161 if (target
== PIPE_BUFFER
) {
2162 retval
|= si_is_vertex_format_supported(
2163 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2164 PIPE_BIND_SHADER_IMAGE
));
2166 if (si_is_sampler_format_supported(screen
, format
))
2167 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2168 PIPE_BIND_SHADER_IMAGE
);
2172 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2173 PIPE_BIND_DISPLAY_TARGET
|
2176 PIPE_BIND_BLENDABLE
)) &&
2177 si_is_colorbuffer_format_supported(format
)) {
2179 (PIPE_BIND_RENDER_TARGET
|
2180 PIPE_BIND_DISPLAY_TARGET
|
2183 if (!util_format_is_pure_integer(format
) &&
2184 !util_format_is_depth_or_stencil(format
))
2185 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2188 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2189 si_is_zs_format_supported(format
)) {
2190 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2193 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2194 retval
|= si_is_vertex_format_supported(screen
, format
,
2195 PIPE_BIND_VERTEX_BUFFER
);
2198 if ((usage
& PIPE_BIND_LINEAR
) &&
2199 !util_format_is_compressed(format
) &&
2200 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2201 retval
|= PIPE_BIND_LINEAR
;
2203 return retval
== usage
;
2207 * framebuffer handling
2210 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2211 unsigned format
, unsigned swap
,
2212 unsigned ntype
, bool is_depth
)
2214 /* Alpha is needed for alpha-to-coverage.
2215 * Blending may be with or without alpha.
2217 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2218 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2219 unsigned blend
= 0; /* supports blending, but may not export alpha */
2220 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2222 /* Choose the SPI color formats. These are required values for RB+.
2223 * Other chips have multiple choices, though they are not necessarily better.
2226 case V_028C70_COLOR_5_6_5
:
2227 case V_028C70_COLOR_1_5_5_5
:
2228 case V_028C70_COLOR_5_5_5_1
:
2229 case V_028C70_COLOR_4_4_4_4
:
2230 case V_028C70_COLOR_10_11_11
:
2231 case V_028C70_COLOR_11_11_10
:
2232 case V_028C70_COLOR_8
:
2233 case V_028C70_COLOR_8_8
:
2234 case V_028C70_COLOR_8_8_8_8
:
2235 case V_028C70_COLOR_10_10_10_2
:
2236 case V_028C70_COLOR_2_10_10_10
:
2237 if (ntype
== V_028C70_NUMBER_UINT
)
2238 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2239 else if (ntype
== V_028C70_NUMBER_SINT
)
2240 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2242 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2245 case V_028C70_COLOR_16
:
2246 case V_028C70_COLOR_16_16
:
2247 case V_028C70_COLOR_16_16_16_16
:
2248 if (ntype
== V_028C70_NUMBER_UNORM
||
2249 ntype
== V_028C70_NUMBER_SNORM
) {
2250 /* UNORM16 and SNORM16 don't support blending */
2251 if (ntype
== V_028C70_NUMBER_UNORM
)
2252 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2254 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2256 /* Use 32 bits per channel for blending. */
2257 if (format
== V_028C70_COLOR_16
) {
2258 if (swap
== V_028C70_SWAP_STD
) { /* R */
2259 blend
= V_028714_SPI_SHADER_32_R
;
2260 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2261 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2262 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2265 } else if (format
== V_028C70_COLOR_16_16
) {
2266 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2267 blend
= V_028714_SPI_SHADER_32_GR
;
2268 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2269 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2270 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2273 } else /* 16_16_16_16 */
2274 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2275 } else if (ntype
== V_028C70_NUMBER_UINT
)
2276 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2277 else if (ntype
== V_028C70_NUMBER_SINT
)
2278 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2279 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2280 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2285 case V_028C70_COLOR_32
:
2286 if (swap
== V_028C70_SWAP_STD
) { /* R */
2287 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2288 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2289 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2290 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2295 case V_028C70_COLOR_32_32
:
2296 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2297 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2298 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2299 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2300 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2305 case V_028C70_COLOR_32_32_32_32
:
2306 case V_028C70_COLOR_8_24
:
2307 case V_028C70_COLOR_24_8
:
2308 case V_028C70_COLOR_X24_8_32_FLOAT
:
2309 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2317 /* The DB->CB copy needs 32_ABGR. */
2319 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2321 surf
->spi_shader_col_format
= normal
;
2322 surf
->spi_shader_col_format_alpha
= alpha
;
2323 surf
->spi_shader_col_format_blend
= blend
;
2324 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2327 static void si_initialize_color_surface(struct si_context
*sctx
,
2328 struct r600_surface
*surf
)
2330 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2331 unsigned color_info
, color_attrib
;
2332 unsigned format
, swap
, ntype
, endian
;
2333 const struct util_format_description
*desc
;
2335 unsigned blend_clamp
= 0, blend_bypass
= 0;
2337 desc
= util_format_description(surf
->base
.format
);
2338 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2339 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2343 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2344 ntype
= V_028C70_NUMBER_FLOAT
;
2346 ntype
= V_028C70_NUMBER_UNORM
;
2347 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2348 ntype
= V_028C70_NUMBER_SRGB
;
2349 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2350 if (desc
->channel
[firstchan
].pure_integer
) {
2351 ntype
= V_028C70_NUMBER_SINT
;
2353 assert(desc
->channel
[firstchan
].normalized
);
2354 ntype
= V_028C70_NUMBER_SNORM
;
2356 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2357 if (desc
->channel
[firstchan
].pure_integer
) {
2358 ntype
= V_028C70_NUMBER_UINT
;
2360 assert(desc
->channel
[firstchan
].normalized
);
2361 ntype
= V_028C70_NUMBER_UNORM
;
2366 format
= si_translate_colorformat(surf
->base
.format
);
2367 if (format
== V_028C70_COLOR_INVALID
) {
2368 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2370 assert(format
!= V_028C70_COLOR_INVALID
);
2371 swap
= si_translate_colorswap(surf
->base
.format
, false);
2372 endian
= si_colorformat_endian_swap(format
);
2374 /* blend clamp should be set for all NORM/SRGB types */
2375 if (ntype
== V_028C70_NUMBER_UNORM
||
2376 ntype
== V_028C70_NUMBER_SNORM
||
2377 ntype
== V_028C70_NUMBER_SRGB
)
2380 /* set blend bypass according to docs if SINT/UINT or
2381 8/24 COLOR variants */
2382 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2383 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2384 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2389 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2390 if (format
== V_028C70_COLOR_8
||
2391 format
== V_028C70_COLOR_8_8
||
2392 format
== V_028C70_COLOR_8_8_8_8
)
2393 surf
->color_is_int8
= true;
2394 else if (format
== V_028C70_COLOR_10_10_10_2
||
2395 format
== V_028C70_COLOR_2_10_10_10
)
2396 surf
->color_is_int10
= true;
2399 color_info
= S_028C70_FORMAT(format
) |
2400 S_028C70_COMP_SWAP(swap
) |
2401 S_028C70_BLEND_CLAMP(blend_clamp
) |
2402 S_028C70_BLEND_BYPASS(blend_bypass
) |
2403 S_028C70_SIMPLE_FLOAT(1) |
2404 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2405 ntype
!= V_028C70_NUMBER_SNORM
&&
2406 ntype
!= V_028C70_NUMBER_SRGB
&&
2407 format
!= V_028C70_COLOR_8_24
&&
2408 format
!= V_028C70_COLOR_24_8
) |
2409 S_028C70_NUMBER_TYPE(ntype
) |
2410 S_028C70_ENDIAN(endian
);
2412 /* Intensity is implemented as Red, so treat it that way. */
2413 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2414 util_format_is_intensity(surf
->base
.format
));
2416 if (rtex
->buffer
.b
.b
.nr_samples
> 1) {
2417 unsigned log_samples
= util_logbase2(rtex
->buffer
.b
.b
.nr_samples
);
2418 unsigned log_fragments
= util_logbase2(rtex
->num_color_samples
);
2420 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2421 S_028C74_NUM_FRAGMENTS(log_fragments
);
2423 if (rtex
->surface
.fmask_size
) {
2424 color_info
|= S_028C70_COMPRESSION(1);
2425 unsigned fmask_bankh
= util_logbase2(rtex
->surface
.u
.legacy
.fmask
.bankh
);
2427 if (sctx
->chip_class
== SI
) {
2428 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2429 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2434 if (sctx
->chip_class
>= VI
) {
2435 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2436 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2438 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2439 64 for APU because all of our APUs to date use DIMMs which have
2440 a request granularity size of 64B while all other chips have a
2442 if (!sctx
->screen
->info
.has_dedicated_vram
)
2443 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2445 if (rtex
->num_color_samples
> 1) {
2446 if (rtex
->surface
.bpe
== 1)
2447 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2448 else if (rtex
->surface
.bpe
== 2)
2449 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2452 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2453 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2454 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2457 /* This must be set for fast clear to work without FMASK. */
2458 if (!rtex
->surface
.fmask_size
&& sctx
->chip_class
== SI
) {
2459 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2460 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2463 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2464 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2466 if (sctx
->chip_class
>= GFX9
) {
2467 unsigned mip0_depth
= util_max_layer(&rtex
->buffer
.b
.b
, 0);
2469 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2470 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2471 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2472 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2473 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2474 S_028C68_MAX_MIP(rtex
->buffer
.b
.b
.last_level
);
2477 surf
->cb_color_view
= color_view
;
2478 surf
->cb_color_info
= color_info
;
2479 surf
->cb_color_attrib
= color_attrib
;
2481 /* Determine pixel shader export format */
2482 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2484 surf
->color_initialized
= true;
2487 static void si_init_depth_surface(struct si_context
*sctx
,
2488 struct r600_surface
*surf
)
2490 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2491 unsigned level
= surf
->base
.u
.tex
.level
;
2492 unsigned format
, stencil_format
;
2493 uint32_t z_info
, s_info
;
2495 format
= si_translate_dbformat(rtex
->db_render_format
);
2496 stencil_format
= rtex
->surface
.has_stencil
?
2497 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2499 assert(format
!= V_028040_Z_INVALID
);
2500 if (format
== V_028040_Z_INVALID
)
2501 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->buffer
.b
.b
.format
);
2503 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2504 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2505 surf
->db_htile_data_base
= 0;
2506 surf
->db_htile_surface
= 0;
2508 if (sctx
->chip_class
>= GFX9
) {
2509 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2510 surf
->db_depth_base
= rtex
->buffer
.gpu_address
>> 8;
2511 surf
->db_stencil_base
= (rtex
->buffer
.gpu_address
+
2512 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2513 z_info
= S_028038_FORMAT(format
) |
2514 S_028038_NUM_SAMPLES(util_logbase2(rtex
->buffer
.b
.b
.nr_samples
)) |
2515 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2516 S_028038_MAXMIP(rtex
->buffer
.b
.b
.last_level
);
2517 s_info
= S_02803C_FORMAT(stencil_format
) |
2518 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2519 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2520 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2521 surf
->db_depth_view
|= S_028008_MIPID(level
);
2522 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->buffer
.b
.b
.width0
- 1) |
2523 S_02801C_Y_MAX(rtex
->buffer
.b
.b
.height0
- 1);
2525 if (si_htile_enabled(rtex
, level
)) {
2526 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2527 S_028038_ALLOW_EXPCLEAR(1);
2529 if (rtex
->tc_compatible_htile
) {
2530 unsigned max_zplanes
= 4;
2532 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2533 rtex
->buffer
.b
.b
.nr_samples
> 1)
2536 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2537 S_028038_ITERATE_FLUSH(1);
2538 s_info
|= S_02803C_ITERATE_FLUSH(1);
2541 if (rtex
->surface
.has_stencil
) {
2542 /* Stencil buffer workaround ported from the SI-CI-VI code.
2543 * See that for explanation.
2545 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->buffer
.b
.b
.nr_samples
<= 1);
2547 /* Use all HTILE for depth if there's no stencil. */
2548 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2551 surf
->db_htile_data_base
= (rtex
->buffer
.gpu_address
+
2552 rtex
->htile_offset
) >> 8;
2553 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2554 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2555 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2559 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2561 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2563 surf
->db_depth_base
= (rtex
->buffer
.gpu_address
+
2564 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2565 surf
->db_stencil_base
= (rtex
->buffer
.gpu_address
+
2566 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2568 z_info
= S_028040_FORMAT(format
) |
2569 S_028040_NUM_SAMPLES(util_logbase2(rtex
->buffer
.b
.b
.nr_samples
));
2570 s_info
= S_028044_FORMAT(stencil_format
);
2571 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2573 if (sctx
->chip_class
>= CIK
) {
2574 struct radeon_info
*info
= &sctx
->screen
->info
;
2575 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2576 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2577 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2578 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2579 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2580 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2582 surf
->db_depth_info
|=
2583 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2584 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2585 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2586 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2587 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2588 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2589 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2590 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2592 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2593 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2594 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2595 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2598 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2599 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2600 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2601 levelinfo
->nblk_y
) / 64 - 1);
2603 if (si_htile_enabled(rtex
, level
)) {
2604 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2605 S_028040_ALLOW_EXPCLEAR(1);
2607 if (rtex
->surface
.has_stencil
) {
2608 /* Workaround: For a not yet understood reason, the
2609 * combination of MSAA, fast stencil clear and stencil
2610 * decompress messes with subsequent stencil buffer
2611 * uses. Problem was reproduced on Verde, Bonaire,
2612 * Tonga, and Carrizo.
2614 * Disabling EXPCLEAR works around the problem.
2616 * Check piglit's arb_texture_multisample-stencil-clear
2617 * test if you want to try changing this.
2619 if (rtex
->buffer
.b
.b
.nr_samples
<= 1)
2620 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2621 } else if (!rtex
->tc_compatible_htile
) {
2622 /* Use all of the htile_buffer for depth if there's no stencil.
2623 * This must not be set when TC-compatible HTILE is enabled
2626 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2629 surf
->db_htile_data_base
= (rtex
->buffer
.gpu_address
+
2630 rtex
->htile_offset
) >> 8;
2631 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2633 if (rtex
->tc_compatible_htile
) {
2634 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2636 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2637 if (rtex
->buffer
.b
.b
.nr_samples
<= 1)
2638 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2639 else if (rtex
->buffer
.b
.b
.nr_samples
<= 4)
2640 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2642 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2647 surf
->db_z_info
= z_info
;
2648 surf
->db_stencil_info
= s_info
;
2650 surf
->depth_initialized
= true;
2653 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2655 if (sctx
->decompression_enabled
)
2658 if (sctx
->framebuffer
.state
.zsbuf
) {
2659 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2660 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2662 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2664 if (rtex
->surface
.has_stencil
)
2665 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2668 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2669 while (compressed_cb_mask
) {
2670 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2671 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2672 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2674 if (rtex
->surface
.fmask_size
)
2675 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2676 if (rtex
->dcc_gather_statistics
)
2677 rtex
->separate_dcc_dirty
= true;
2681 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2683 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2684 struct r600_surface
*surf
= NULL
;
2685 struct r600_texture
*rtex
;
2687 if (!state
->cbufs
[i
])
2689 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2690 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2692 p_atomic_dec(&rtex
->framebuffers_bound
);
2696 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2697 const struct pipe_framebuffer_state
*state
)
2699 struct si_context
*sctx
= (struct si_context
*)ctx
;
2700 struct pipe_constant_buffer constbuf
= {0};
2701 struct r600_surface
*surf
= NULL
;
2702 struct r600_texture
*rtex
;
2703 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2704 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2705 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2706 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2707 bool old_has_stencil
=
2709 ((struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2710 bool unbound
= false;
2713 si_update_fb_dirtiness_after_rendering(sctx
);
2715 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2716 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2719 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2720 if (rtex
->dcc_gather_statistics
)
2721 vi_separate_dcc_stop_query(sctx
, rtex
);
2724 /* Disable DCC if the formats are incompatible. */
2725 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2726 if (!state
->cbufs
[i
])
2729 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2730 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2732 if (!surf
->dcc_incompatible
)
2735 /* Since the DCC decompression calls back into set_framebuffer-
2736 * _state, we need to unbind the framebuffer, so that
2737 * vi_separate_dcc_stop_query isn't called twice with the same
2741 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2745 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2746 if (!si_texture_disable_dcc(sctx
, rtex
))
2747 si_decompress_dcc(sctx
, rtex
);
2749 surf
->dcc_incompatible
= false;
2752 /* Only flush TC when changing the framebuffer state, because
2753 * the only client not using TC that can change textures is
2756 * Wait for compute shaders because of possible transitions:
2757 * - FB write -> shader read
2758 * - shader write -> FB read
2760 * DB caches are flushed on demand (using si_decompress_textures).
2762 * When MSAA is enabled, CB and TC caches are flushed on demand
2763 * (after FMASK decompression). Shader write -> FB read transitions
2764 * cannot happen for MSAA textures, because MSAA shader images are
2767 * Only flush and wait for CB if there is actually a bound color buffer.
2769 if (sctx
->framebuffer
.uncompressed_cb_mask
)
2770 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2771 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2773 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2775 /* u_blitter doesn't invoke depth decompression when it does multiple
2776 * blits in a row, but the only case when it matters for DB is when
2777 * doing generate_mipmap. So here we flush DB manually between
2778 * individual generate_mipmap blits.
2779 * Note that lower mipmap levels aren't compressed.
2781 if (sctx
->generate_mipmap_for_depth
) {
2782 si_make_DB_shader_coherent(sctx
, 1, false,
2783 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2784 } else if (sctx
->chip_class
== GFX9
) {
2785 /* It appears that DB metadata "leaks" in a sequence of:
2787 * - DCC decompress for shader image writes (with DB disabled)
2788 * - render with DEPTH_BEFORE_SHADER=1
2789 * Flushing DB metadata works around the problem.
2791 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2794 /* Take the maximum of the old and new count. If the new count is lower,
2795 * dirtying is needed to disable the unbound colorbuffers.
2797 sctx
->framebuffer
.dirty_cbufs
|=
2798 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2799 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2801 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2802 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2804 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2805 sctx
->framebuffer
.spi_shader_col_format
= 0;
2806 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2807 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2808 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2809 sctx
->framebuffer
.color_is_int8
= 0;
2810 sctx
->framebuffer
.color_is_int10
= 0;
2812 sctx
->framebuffer
.compressed_cb_mask
= 0;
2813 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2814 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2815 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2816 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2817 sctx
->framebuffer
.any_dst_linear
= false;
2818 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2819 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2821 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2822 if (!state
->cbufs
[i
])
2825 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2826 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2828 if (!surf
->color_initialized
) {
2829 si_initialize_color_surface(sctx
, surf
);
2832 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2833 sctx
->framebuffer
.spi_shader_col_format
|=
2834 surf
->spi_shader_col_format
<< (i
* 4);
2835 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2836 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2837 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2838 surf
->spi_shader_col_format_blend
<< (i
* 4);
2839 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2840 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2842 if (surf
->color_is_int8
)
2843 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2844 if (surf
->color_is_int10
)
2845 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2847 if (rtex
->surface
.fmask_size
)
2848 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2850 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2852 /* Don't update nr_color_samples for non-AA buffers.
2853 * (e.g. destination of MSAA resolve)
2855 if (rtex
->buffer
.b
.b
.nr_samples
>= 2 &&
2856 rtex
->num_color_samples
< rtex
->buffer
.b
.b
.nr_samples
) {
2857 sctx
->framebuffer
.nr_color_samples
=
2858 MIN2(sctx
->framebuffer
.nr_color_samples
,
2859 rtex
->num_color_samples
);
2862 if (rtex
->surface
.is_linear
)
2863 sctx
->framebuffer
.any_dst_linear
= true;
2865 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2866 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2868 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2870 p_atomic_inc(&rtex
->framebuffers_bound
);
2872 if (rtex
->dcc_gather_statistics
) {
2873 /* Dirty tracking must be enabled for DCC usage analysis. */
2874 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2875 vi_separate_dcc_start_query(sctx
, rtex
);
2879 struct r600_texture
*zstex
= NULL
;
2882 surf
= (struct r600_surface
*)state
->zsbuf
;
2883 zstex
= (struct r600_texture
*)surf
->base
.texture
;
2885 if (!surf
->depth_initialized
) {
2886 si_init_depth_surface(sctx
, surf
);
2889 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2890 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2892 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2895 si_update_ps_colorbuf0_slot(sctx
);
2896 si_update_poly_offset_state(sctx
);
2897 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2898 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2900 if (sctx
->screen
->dpbb_allowed
)
2901 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2903 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2904 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2906 if (sctx
->screen
->has_out_of_order_rast
&&
2907 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2908 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2909 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2910 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2912 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2913 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2914 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2916 /* Set sample locations as fragment shader constants. */
2917 switch (sctx
->framebuffer
.nr_samples
) {
2919 constbuf
.user_buffer
= sctx
->sample_locations_1x
;
2922 constbuf
.user_buffer
= sctx
->sample_locations_2x
;
2925 constbuf
.user_buffer
= sctx
->sample_locations_4x
;
2928 constbuf
.user_buffer
= sctx
->sample_locations_8x
;
2931 constbuf
.user_buffer
= sctx
->sample_locations_16x
;
2934 PRINT_ERR("Requested an invalid number of samples %i.\n",
2935 sctx
->framebuffer
.nr_samples
);
2938 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2939 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2941 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2944 sctx
->do_update_shaders
= true;
2946 if (!sctx
->decompression_enabled
) {
2947 /* Prevent textures decompression when the framebuffer state
2948 * changes come from the decompression passes themselves.
2950 sctx
->need_check_render_feedback
= true;
2954 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2956 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2957 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2958 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2959 struct r600_texture
*tex
= NULL
;
2960 struct r600_surface
*cb
= NULL
;
2961 unsigned cb_color_info
= 0;
2964 for (i
= 0; i
< nr_cbufs
; i
++) {
2965 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
2966 unsigned cb_color_attrib
;
2968 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2971 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2973 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2974 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2978 tex
= (struct r600_texture
*)cb
->base
.texture
;
2979 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
2980 &tex
->buffer
, RADEON_USAGE_READWRITE
,
2981 tex
->buffer
.b
.b
.nr_samples
> 1 ?
2982 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2983 RADEON_PRIO_COLOR_BUFFER
);
2985 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
2986 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
2987 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2991 if (tex
->dcc_separate_buffer
)
2992 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
2993 tex
->dcc_separate_buffer
,
2994 RADEON_USAGE_READWRITE
,
2997 /* Compute mutable surface parameters. */
2998 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3000 cb_color_cmask
= tex
->cmask
.base_address_reg
;
3002 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3003 cb_color_attrib
= cb
->cb_color_attrib
;
3005 if (cb
->base
.u
.tex
.level
> 0)
3006 cb_color_info
&= C_028C70_FAST_CLEAR
;
3008 if (tex
->surface
.fmask_size
) {
3009 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3010 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3014 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3015 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3016 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3017 state
->cbufs
[1] == &cb
->base
&&
3018 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3020 if (!is_msaa_resolve_dst
)
3021 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3023 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3024 tex
->dcc_offset
) >> 8;
3025 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3028 if (sctx
->chip_class
>= GFX9
) {
3029 struct gfx9_surf_meta_flags meta
;
3031 if (tex
->dcc_offset
)
3032 meta
= tex
->surface
.u
.gfx9
.dcc
;
3034 meta
= tex
->surface
.u
.gfx9
.cmask
;
3036 /* Set mutable surface parameters. */
3037 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3038 cb_color_base
|= tex
->surface
.tile_swizzle
;
3039 if (!tex
->surface
.fmask_size
)
3040 cb_color_fmask
= cb_color_base
;
3041 if (cb
->base
.u
.tex
.level
> 0)
3042 cb_color_cmask
= cb_color_base
;
3043 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3044 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3045 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3046 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3048 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3049 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3050 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3051 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3052 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3053 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3054 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3055 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3056 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3057 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3058 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3059 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3060 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3061 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3062 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3063 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3065 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3066 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3068 /* Compute mutable surface parameters (SI-CI-VI). */
3069 const struct legacy_surf_level
*level_info
=
3070 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3071 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3072 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3074 cb_color_base
+= level_info
->offset
>> 8;
3075 /* Only macrotiled modes can set tile swizzle. */
3076 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3077 cb_color_base
|= tex
->surface
.tile_swizzle
;
3079 if (!tex
->surface
.fmask_size
)
3080 cb_color_fmask
= cb_color_base
;
3081 if (cb
->base
.u
.tex
.level
> 0)
3082 cb_color_cmask
= cb_color_base
;
3084 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3086 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3087 slice_tile_max
= level_info
->nblk_x
*
3088 level_info
->nblk_y
/ 64 - 1;
3089 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3091 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3092 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3093 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3095 if (tex
->surface
.fmask_size
) {
3096 if (sctx
->chip_class
>= CIK
)
3097 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3098 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3099 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3101 /* This must be set for fast clear to work without FMASK. */
3102 if (sctx
->chip_class
>= CIK
)
3103 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3104 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3105 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3108 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3109 sctx
->chip_class
>= VI
? 14 : 13);
3110 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3111 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3112 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3113 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3114 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3115 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3116 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3117 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3118 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3119 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3120 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3121 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3122 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3124 if (sctx
->chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3125 radeon_emit(cs
, cb_dcc_base
);
3129 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3130 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3133 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3134 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
3135 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
3137 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3138 &rtex
->buffer
, RADEON_USAGE_READWRITE
,
3139 zb
->base
.texture
->nr_samples
> 1 ?
3140 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3141 RADEON_PRIO_DEPTH_BUFFER
);
3143 if (sctx
->chip_class
>= GFX9
) {
3144 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3145 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3146 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3147 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3149 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3150 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3151 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3152 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3153 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3154 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3155 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3156 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3157 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3158 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3159 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3160 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3162 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3163 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3164 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3166 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3168 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3169 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3170 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3171 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3172 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3173 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3174 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3175 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3176 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3177 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3178 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3181 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3182 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3183 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3185 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3186 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3187 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3188 if (sctx
->chip_class
>= GFX9
)
3189 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3191 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3193 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3194 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3197 /* Framebuffer dimensions. */
3198 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3199 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3200 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3202 if (sctx
->screen
->dfsm_allowed
) {
3203 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3204 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3207 sctx
->framebuffer
.dirty_cbufs
= 0;
3208 sctx
->framebuffer
.dirty_zsbuf
= false;
3211 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3213 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
3214 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3215 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3217 /* Smoothing (only possible with nr_samples == 1) uses the same
3218 * sample locations as the MSAA it simulates.
3220 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3221 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3223 /* On Polaris, the small primitive filter uses the sample locations
3224 * even when MSAA is off, so we need to make sure they're set to 0.
3226 if (has_msaa_sample_loc_bug
)
3227 nr_samples
= MAX2(nr_samples
, 1);
3229 if (nr_samples
!= sctx
->sample_locs_num_samples
) {
3230 sctx
->sample_locs_num_samples
= nr_samples
;
3231 si_emit_sample_locations(cs
, nr_samples
);
3234 if (sctx
->family
>= CHIP_POLARIS10
) {
3235 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3236 unsigned small_prim_filter_cntl
=
3237 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3239 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3241 /* The alternative of setting sample locations to 0 would
3242 * require a DB flush to avoid Z errors, see
3243 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3245 if (has_msaa_sample_loc_bug
&&
3246 sctx
->framebuffer
.nr_samples
> 1 &&
3247 rs
&& !rs
->multisample_enable
)
3248 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3250 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3251 small_prim_filter_cntl
);
3255 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3257 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3258 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3260 if (!sctx
->screen
->has_out_of_order_rast
)
3263 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3266 colormask
&= blend
->cb_target_enabled_4bit
;
3271 /* Conservative: No logic op. */
3272 if (colormask
&& blend
->logicop_enable
)
3275 struct si_dsa_order_invariance dsa_order_invariant
= {
3276 .zs
= true, .pass_set
= true, .pass_last
= false
3279 if (sctx
->framebuffer
.state
.zsbuf
) {
3280 struct r600_texture
*zstex
=
3281 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3282 bool has_stencil
= zstex
->surface
.has_stencil
;
3283 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3284 if (!dsa_order_invariant
.zs
)
3287 /* The set of PS invocations is always order invariant,
3288 * except when early Z/S tests are requested. */
3289 if (sctx
->ps_shader
.cso
&&
3290 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3291 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3292 !dsa_order_invariant
.pass_set
)
3295 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3296 !dsa_order_invariant
.pass_set
)
3303 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3306 /* Only commutative blending. */
3307 if (blendmask
& ~blend
->commutative_4bit
)
3310 if (!dsa_order_invariant
.pass_set
)
3314 if (colormask
& ~blendmask
) {
3315 if (!dsa_order_invariant
.pass_last
)
3322 static void si_emit_msaa_config(struct si_context
*sctx
)
3324 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
3325 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3326 /* 33% faster rendering to linear color buffers */
3327 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3328 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3329 unsigned sc_mode_cntl_1
=
3330 S_028A4C_WALK_SIZE(dst_is_linear
) |
3331 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3332 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3333 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3334 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3336 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3337 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3338 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3339 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3340 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3341 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3342 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3343 S_028804_INCOHERENT_EQAA_READS(1) |
3344 S_028804_INTERPOLATE_COMP_Z(1) |
3345 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3346 unsigned coverage_samples
, color_samples
;
3348 /* S: Coverage samples (up to 16x):
3349 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3350 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3352 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3353 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3354 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3355 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3356 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3359 * F: Color samples (up to 8x, must be <= coverage samples):
3360 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3361 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3363 * Can be anything between coverage and color samples:
3364 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3365 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3366 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3367 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3368 * # All are currently set the same as coverage samples.
3370 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3371 * flag for undefined color samples. A shader-based resolve must handle unknowns
3372 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3373 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3374 * useful. The CB resolve always drops unknowns.
3376 * Sensible AA configurations:
3377 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3378 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3379 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3380 * EQAA 8s 8z 8f = 8x MSAA
3381 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3382 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3383 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3384 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3385 * EQAA 4s 4z 4f = 4x MSAA
3386 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3387 * EQAA 2s 2z 2f = 2x MSAA
3389 if (sctx
->framebuffer
.nr_samples
> 1) {
3390 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3391 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3392 } else if (sctx
->smoothing_enabled
) {
3393 coverage_samples
= color_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3395 coverage_samples
= color_samples
= 1;
3398 /* Required by OpenGL line rasterization.
3400 * TODO: We should also enable perpendicular endcaps for AA lines,
3401 * but that requires implementing line stippling in the pixel
3402 * shader. SC can only do line stippling with axis-aligned
3405 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3407 if (coverage_samples
> 1) {
3408 /* distance from the pixel center, indexed by log2(nr_samples) */
3409 static unsigned max_dist
[] = {
3416 unsigned log_samples
= util_logbase2(coverage_samples
);
3417 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3418 ps_iter_samples
= MIN2(ps_iter_samples
, color_samples
);
3419 unsigned log_ps_iter_samples
=
3420 util_logbase2(util_next_power_of_two(ps_iter_samples
));
3422 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3423 radeon_emit(cs
, sc_line_cntl
|
3424 S_028BDC_EXPAND_LINE_WIDTH(1)); /* R_028BDC_PA_SC_LINE_CNTL */
3425 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3426 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3427 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* R_028BE0_PA_SC_AA_CONFIG */
3429 if (sctx
->framebuffer
.nr_samples
> 1) {
3430 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3432 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
3433 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3434 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3435 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
));
3436 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3437 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
3439 } else if (sctx
->smoothing_enabled
) {
3440 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3442 S_028804_OVERRASTERIZATION_AMOUNT(log_samples
));
3443 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3447 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3448 radeon_emit(cs
, sc_line_cntl
); /* R_028BDC_PA_SC_LINE_CNTL */
3449 radeon_emit(cs
, 0); /* R_028BE0_PA_SC_AA_CONFIG */
3451 radeon_set_context_reg(cs
, R_028804_DB_EQAA
, db_eqaa
);
3452 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3456 /* GFX9: Flush DFSM when the AA mode changes. */
3457 if (sctx
->screen
->dfsm_allowed
) {
3458 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3459 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3463 void si_update_ps_iter_samples(struct si_context
*sctx
)
3465 if (sctx
->framebuffer
.nr_samples
> 1)
3466 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3467 if (sctx
->screen
->dpbb_allowed
)
3468 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3471 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3473 struct si_context
*sctx
= (struct si_context
*)ctx
;
3475 if (sctx
->ps_iter_samples
== min_samples
)
3478 sctx
->ps_iter_samples
= min_samples
;
3479 sctx
->do_update_shaders
= true;
3481 si_update_ps_iter_samples(sctx
);
3489 * Build the sampler view descriptor for a buffer texture.
3490 * @param state 256-bit descriptor; only the high 128 bits are filled in
3493 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3494 enum pipe_format format
,
3495 unsigned offset
, unsigned size
,
3498 const struct util_format_description
*desc
;
3501 unsigned num_records
;
3502 unsigned num_format
, data_format
;
3504 desc
= util_format_description(format
);
3505 first_non_void
= util_format_get_first_non_void_channel(format
);
3506 stride
= desc
->block
.bits
/ 8;
3507 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3508 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3510 num_records
= size
/ stride
;
3511 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3513 /* The NUM_RECORDS field has a different meaning depending on the chip,
3514 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3517 * - If STRIDE == 0, it's in byte units.
3518 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3521 * - For SMEM and STRIDE == 0, it's in byte units.
3522 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3523 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3524 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3525 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3526 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3527 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3528 * That way the same descriptor can be used by both SMEM and VMEM.
3531 * - For SMEM and STRIDE == 0, it's in byte units.
3532 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3533 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3534 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3536 if (screen
->info
.chip_class
>= GFX9
)
3537 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3538 * from STRIDE to bytes. This works around it by setting
3539 * NUM_RECORDS to at least the size of one element, so that
3540 * the first element is readable when IDXEN == 0.
3542 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3543 * IDXEN is enforced?
3545 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3546 else if (screen
->info
.chip_class
== VI
)
3547 num_records
*= stride
;
3550 state
[5] = S_008F04_STRIDE(stride
);
3551 state
[6] = num_records
;
3552 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3553 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3554 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3555 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3556 S_008F0C_NUM_FORMAT(num_format
) |
3557 S_008F0C_DATA_FORMAT(data_format
);
3560 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3562 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3564 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3565 /* For the pre-defined border color values (white, opaque
3566 * black, transparent black), the only thing that matters is
3567 * that the alpha channel winds up in the correct place
3568 * (because the RGB channels are all the same) so either of
3569 * these enumerations will work.
3571 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3572 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3574 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3575 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3576 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3577 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3579 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3580 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3581 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3582 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3583 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3590 * Build the sampler view descriptor for a texture.
3593 si_make_texture_descriptor(struct si_screen
*screen
,
3594 struct r600_texture
*tex
,
3596 enum pipe_texture_target target
,
3597 enum pipe_format pipe_format
,
3598 const unsigned char state_swizzle
[4],
3599 unsigned first_level
, unsigned last_level
,
3600 unsigned first_layer
, unsigned last_layer
,
3601 unsigned width
, unsigned height
, unsigned depth
,
3603 uint32_t *fmask_state
)
3605 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3606 const struct util_format_description
*desc
;
3607 unsigned char swizzle
[4];
3609 unsigned num_format
, data_format
, type
, num_samples
;
3612 desc
= util_format_description(pipe_format
);
3614 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
3615 MAX2(1, res
->nr_samples
) : tex
->num_color_samples
;
3617 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3618 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3619 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3620 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3622 switch (pipe_format
) {
3623 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3624 case PIPE_FORMAT_X32_S8X24_UINT
:
3625 case PIPE_FORMAT_X8Z24_UNORM
:
3626 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3628 case PIPE_FORMAT_X24S8_UINT
:
3630 * X24S8 is implemented as an 8_8_8_8 data format, to
3631 * fix texture gathers. This affects at least
3632 * GL45-CTS.texture_cube_map_array.sampling on VI.
3634 if (screen
->info
.chip_class
<= VI
)
3635 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3637 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3640 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3643 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3646 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3648 switch (pipe_format
) {
3649 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3650 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3653 if (first_non_void
< 0) {
3654 if (util_format_is_compressed(pipe_format
)) {
3655 switch (pipe_format
) {
3656 case PIPE_FORMAT_DXT1_SRGB
:
3657 case PIPE_FORMAT_DXT1_SRGBA
:
3658 case PIPE_FORMAT_DXT3_SRGBA
:
3659 case PIPE_FORMAT_DXT5_SRGBA
:
3660 case PIPE_FORMAT_BPTC_SRGBA
:
3661 case PIPE_FORMAT_ETC2_SRGB8
:
3662 case PIPE_FORMAT_ETC2_SRGB8A1
:
3663 case PIPE_FORMAT_ETC2_SRGBA8
:
3664 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3666 case PIPE_FORMAT_RGTC1_SNORM
:
3667 case PIPE_FORMAT_LATC1_SNORM
:
3668 case PIPE_FORMAT_RGTC2_SNORM
:
3669 case PIPE_FORMAT_LATC2_SNORM
:
3670 case PIPE_FORMAT_ETC2_R11_SNORM
:
3671 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3672 /* implies float, so use SNORM/UNORM to determine
3673 whether data is signed or not */
3674 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3675 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3678 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3681 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3682 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3684 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3686 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3687 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3689 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3691 switch (desc
->channel
[first_non_void
].type
) {
3692 case UTIL_FORMAT_TYPE_FLOAT
:
3693 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3695 case UTIL_FORMAT_TYPE_SIGNED
:
3696 if (desc
->channel
[first_non_void
].normalized
)
3697 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3698 else if (desc
->channel
[first_non_void
].pure_integer
)
3699 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3701 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3703 case UTIL_FORMAT_TYPE_UNSIGNED
:
3704 if (desc
->channel
[first_non_void
].normalized
)
3705 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3706 else if (desc
->channel
[first_non_void
].pure_integer
)
3707 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3709 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3714 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3715 if (data_format
== ~0) {
3719 /* S8 with Z32 HTILE needs a special format. */
3720 if (screen
->info
.chip_class
>= GFX9
&&
3721 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3722 tex
->tc_compatible_htile
)
3723 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3726 (res
->target
== PIPE_TEXTURE_CUBE
||
3727 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3728 (screen
->info
.chip_class
<= VI
&&
3729 res
->target
== PIPE_TEXTURE_3D
))) {
3730 /* For the purpose of shader images, treat cube maps and 3D
3731 * textures as 2D arrays. For 3D textures, the address
3732 * calculations for mipmaps are different, so we rely on the
3733 * caller to effectively disable mipmaps.
3735 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3737 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3739 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
3742 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3744 depth
= res
->array_size
;
3745 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3746 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3747 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3748 depth
= res
->array_size
;
3749 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3750 depth
= res
->array_size
/ 6;
3753 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3754 S_008F14_NUM_FORMAT_GFX6(num_format
));
3755 state
[2] = (S_008F18_WIDTH(width
- 1) |
3756 S_008F18_HEIGHT(height
- 1) |
3757 S_008F18_PERF_MOD(4));
3758 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3759 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3760 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3761 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3762 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
3763 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
3764 util_logbase2(num_samples
) :
3766 S_008F1C_TYPE(type
));
3768 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3772 if (screen
->info
.chip_class
>= GFX9
) {
3773 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3775 /* Depth is the the last accessible layer on Gfx9.
3776 * The hw doesn't need to know the total number of layers.
3778 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3779 state
[4] |= S_008F20_DEPTH(depth
- 1);
3781 state
[4] |= S_008F20_DEPTH(last_layer
);
3783 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3784 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
3785 util_logbase2(num_samples
) :
3786 tex
->buffer
.b
.b
.last_level
);
3788 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3789 state
[4] |= S_008F20_DEPTH(depth
- 1);
3790 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3793 if (tex
->dcc_offset
) {
3794 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
3796 /* The last dword is unused by hw. The shader uses it to clear
3797 * bits in the first dword of sampler state.
3799 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3800 if (first_level
== last_level
)
3801 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3803 state
[7] = 0xffffffff;
3807 /* Initialize the sampler view for FMASK. */
3808 if (tex
->surface
.fmask_size
) {
3809 uint32_t data_format
, num_format
;
3811 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3813 #define FMASK(s,f) (((unsigned)(s) * 16) + (f))
3814 if (screen
->info
.chip_class
>= GFX9
) {
3815 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3816 switch (FMASK(res
->nr_samples
, tex
->num_color_samples
)) {
3818 num_format
= V_008F14_IMG_FMASK_8_2_1
;
3821 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3824 num_format
= V_008F14_IMG_FMASK_8_4_1
;
3827 num_format
= V_008F14_IMG_FMASK_8_4_2
;
3830 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3833 num_format
= V_008F14_IMG_FMASK_8_8_1
;
3836 num_format
= V_008F14_IMG_FMASK_16_8_2
;
3839 num_format
= V_008F14_IMG_FMASK_32_8_4
;
3842 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3845 num_format
= V_008F14_IMG_FMASK_16_16_1
;
3848 num_format
= V_008F14_IMG_FMASK_32_16_2
;
3851 num_format
= V_008F14_IMG_FMASK_64_16_4
;
3854 num_format
= V_008F14_IMG_FMASK_64_16_8
;
3857 unreachable("invalid nr_samples");
3860 switch (FMASK(res
->nr_samples
, tex
->num_color_samples
)) {
3862 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
3865 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3868 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
3871 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
3874 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3877 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
3880 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
3883 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
3886 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3889 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
3892 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
3895 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
3898 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
3901 unreachable("invalid nr_samples");
3903 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3907 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3908 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3909 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3910 S_008F14_NUM_FORMAT_GFX6(num_format
);
3911 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3912 S_008F18_HEIGHT(height
- 1);
3913 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3914 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3915 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3916 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3917 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3919 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3923 if (screen
->info
.chip_class
>= GFX9
) {
3924 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3925 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3926 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3927 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3928 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3930 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3931 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3932 S_008F20_PITCH_GFX6(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
3933 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3939 * Create a sampler view.
3941 * @param ctx context
3942 * @param texture texture
3943 * @param state sampler view template
3944 * @param width0 width0 override (for compressed textures as int)
3945 * @param height0 height0 override (for compressed textures as int)
3946 * @param force_level set the base address to the level (for compressed textures)
3948 struct pipe_sampler_view
*
3949 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3950 struct pipe_resource
*texture
,
3951 const struct pipe_sampler_view
*state
,
3952 unsigned width0
, unsigned height0
,
3953 unsigned force_level
)
3955 struct si_context
*sctx
= (struct si_context
*)ctx
;
3956 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3957 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3958 unsigned base_level
, first_level
, last_level
;
3959 unsigned char state_swizzle
[4];
3960 unsigned height
, depth
, width
;
3961 unsigned last_layer
= state
->u
.tex
.last_layer
;
3962 enum pipe_format pipe_format
;
3963 const struct legacy_surf_level
*surflevel
;
3968 /* initialize base object */
3969 view
->base
= *state
;
3970 view
->base
.texture
= NULL
;
3971 view
->base
.reference
.count
= 1;
3972 view
->base
.context
= ctx
;
3975 pipe_resource_reference(&view
->base
.texture
, texture
);
3977 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3978 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3979 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3980 state
->format
== PIPE_FORMAT_S8_UINT
)
3981 view
->is_stencil_sampler
= true;
3983 /* Buffer resource. */
3984 if (texture
->target
== PIPE_BUFFER
) {
3985 si_make_buffer_descriptor(sctx
->screen
,
3986 r600_resource(texture
),
3988 state
->u
.buf
.offset
,
3994 state_swizzle
[0] = state
->swizzle_r
;
3995 state_swizzle
[1] = state
->swizzle_g
;
3996 state_swizzle
[2] = state
->swizzle_b
;
3997 state_swizzle
[3] = state
->swizzle_a
;
4000 first_level
= state
->u
.tex
.first_level
;
4001 last_level
= state
->u
.tex
.last_level
;
4004 depth
= texture
->depth0
;
4006 if (sctx
->chip_class
<= VI
&& force_level
) {
4007 assert(force_level
== first_level
&&
4008 force_level
== last_level
);
4009 base_level
= force_level
;
4012 width
= u_minify(width
, force_level
);
4013 height
= u_minify(height
, force_level
);
4014 depth
= u_minify(depth
, force_level
);
4017 /* This is not needed if state trackers set last_layer correctly. */
4018 if (state
->target
== PIPE_TEXTURE_1D
||
4019 state
->target
== PIPE_TEXTURE_2D
||
4020 state
->target
== PIPE_TEXTURE_RECT
||
4021 state
->target
== PIPE_TEXTURE_CUBE
)
4022 last_layer
= state
->u
.tex
.first_layer
;
4024 /* Texturing with separate depth and stencil. */
4025 pipe_format
= state
->format
;
4027 /* Depth/stencil texturing sometimes needs separate texture. */
4028 if (tmp
->is_depth
&& !si_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
4029 if (!tmp
->flushed_depth_texture
&&
4030 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
4031 pipe_resource_reference(&view
->base
.texture
, NULL
);
4036 assert(tmp
->flushed_depth_texture
);
4038 /* Override format for the case where the flushed texture
4039 * contains only Z or only S.
4041 if (tmp
->flushed_depth_texture
->buffer
.b
.b
.format
!= tmp
->buffer
.b
.b
.format
)
4042 pipe_format
= tmp
->flushed_depth_texture
->buffer
.b
.b
.format
;
4044 tmp
= tmp
->flushed_depth_texture
;
4047 surflevel
= tmp
->surface
.u
.legacy
.level
;
4049 if (tmp
->db_compatible
) {
4050 if (!view
->is_stencil_sampler
)
4051 pipe_format
= tmp
->db_render_format
;
4053 switch (pipe_format
) {
4054 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4055 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4057 case PIPE_FORMAT_X8Z24_UNORM
:
4058 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4059 /* Z24 is always stored like this for DB
4062 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4064 case PIPE_FORMAT_X24S8_UINT
:
4065 case PIPE_FORMAT_S8X24_UINT
:
4066 case PIPE_FORMAT_X32_S8X24_UINT
:
4067 pipe_format
= PIPE_FORMAT_S8_UINT
;
4068 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
4074 view
->dcc_incompatible
=
4075 vi_dcc_formats_are_incompatible(texture
,
4076 state
->u
.tex
.first_level
,
4079 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
4080 state
->target
, pipe_format
, state_swizzle
,
4081 first_level
, last_level
,
4082 state
->u
.tex
.first_layer
, last_layer
,
4083 width
, height
, depth
,
4084 view
->state
, view
->fmask_state
);
4086 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
4088 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
4089 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
4090 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
4091 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
4092 view
->base_level_info
= &surflevel
[base_level
];
4093 view
->base_level
= base_level
;
4094 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4098 static struct pipe_sampler_view
*
4099 si_create_sampler_view(struct pipe_context
*ctx
,
4100 struct pipe_resource
*texture
,
4101 const struct pipe_sampler_view
*state
)
4103 return si_create_sampler_view_custom(ctx
, texture
, state
,
4104 texture
? texture
->width0
: 0,
4105 texture
? texture
->height0
: 0, 0);
4108 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4109 struct pipe_sampler_view
*state
)
4111 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4113 pipe_resource_reference(&state
->texture
, NULL
);
4117 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4119 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4120 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4122 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4123 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4126 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4127 const struct pipe_sampler_state
*state
,
4128 const union pipe_color_union
*color
,
4131 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4132 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4134 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4135 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4136 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4137 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4139 #define simple_border_types(elt) \
4141 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4142 color->elt[2] == 0 && color->elt[3] == 0) \
4143 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4144 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4145 color->elt[2] == 0 && color->elt[3] == 1) \
4146 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4147 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4148 color->elt[2] == 1 && color->elt[3] == 1) \
4149 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4153 simple_border_types(ui
);
4155 simple_border_types(f
);
4157 #undef simple_border_types
4161 /* Check if the border has been uploaded already. */
4162 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4163 if (memcmp(&sctx
->border_color_table
[i
], color
,
4164 sizeof(*color
)) == 0)
4167 if (i
>= SI_MAX_BORDER_COLORS
) {
4168 /* Getting 4096 unique border colors is very unlikely. */
4169 fprintf(stderr
, "radeonsi: The border color table is full. "
4170 "Any new border colors will be just black. "
4171 "Please file a bug.\n");
4172 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4175 if (i
== sctx
->border_color_count
) {
4176 /* Upload a new border color. */
4177 memcpy(&sctx
->border_color_table
[i
], color
,
4179 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4180 color
, sizeof(*color
));
4181 sctx
->border_color_count
++;
4184 return S_008F3C_BORDER_COLOR_PTR(i
) |
4185 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4188 static inline int S_FIXED(float value
, unsigned frac_bits
)
4190 return value
* (1 << frac_bits
);
4193 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4195 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4196 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4197 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4199 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4200 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4203 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4216 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4217 const struct pipe_sampler_state
*state
)
4219 struct si_context
*sctx
= (struct si_context
*)ctx
;
4220 struct si_screen
*sscreen
= sctx
->screen
;
4221 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4222 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4223 : state
->max_anisotropy
;
4224 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4225 union pipe_color_union clamped_border_color
;
4232 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4234 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4235 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4236 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4237 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4238 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4239 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4240 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4241 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4242 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4243 S_008F30_COMPAT_MODE(sctx
->chip_class
>= VI
));
4244 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4245 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4246 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4247 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4248 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4249 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4250 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4251 S_008F38_MIP_POINT_PRECLAMP(0) |
4252 S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= VI
) |
4253 S_008F38_FILTER_PREC_FIX(1) |
4254 S_008F38_ANISO_OVERRIDE(sctx
->chip_class
>= VI
));
4255 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4257 /* Create sampler resource for integer textures. */
4258 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4259 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4261 /* Create sampler resource for upgraded depth textures. */
4262 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4264 for (unsigned i
= 0; i
< 4; ++i
) {
4265 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4266 * when the border color is 1.0. */
4267 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4270 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4271 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4273 rstate
->upgraded_depth_val
[3] =
4274 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4275 S_008F3C_UPGRADED_DEPTH(1);
4280 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4282 struct si_context
*sctx
= (struct si_context
*)ctx
;
4284 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4287 sctx
->sample_mask
= sample_mask
;
4288 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4291 static void si_emit_sample_mask(struct si_context
*sctx
)
4293 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
4294 unsigned mask
= sctx
->sample_mask
;
4296 /* Needed for line and polygon smoothing as well as for the Polaris
4297 * small primitive filter. We expect the state tracker to take care of
4300 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4301 (mask
& 1 && sctx
->blitter
->running
));
4303 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4304 radeon_emit(cs
, mask
| (mask
<< 16));
4305 radeon_emit(cs
, mask
| (mask
<< 16));
4308 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4311 struct si_sampler_state
*s
= state
;
4313 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4320 * Vertex elements & buffers
4323 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4325 const struct pipe_vertex_element
*elements
)
4327 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4328 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4329 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4332 assert(count
<= SI_MAX_ATTRIBS
);
4337 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4339 for (i
= 0; i
< count
; ++i
) {
4340 const struct util_format_description
*desc
;
4341 const struct util_format_channel_description
*channel
;
4342 unsigned data_format
, num_format
;
4344 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4345 unsigned char swizzle
[4];
4347 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4352 if (elements
[i
].instance_divisor
) {
4353 v
->uses_instance_divisors
= true;
4354 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4356 if (v
->instance_divisors
[i
] == 1)
4357 v
->instance_divisor_is_one
|= 1u << i
;
4359 v
->instance_divisor_is_fetched
|= 1u << i
;
4362 if (!used
[vbo_index
]) {
4363 v
->first_vb_use_mask
|= 1 << i
;
4364 used
[vbo_index
] = true;
4367 desc
= util_format_description(elements
[i
].src_format
);
4368 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4369 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4370 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4371 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4372 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4374 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4375 v
->src_offset
[i
] = elements
[i
].src_offset
;
4376 v
->vertex_buffer_index
[i
] = vbo_index
;
4378 /* The hardware always treats the 2-bit alpha channel as
4379 * unsigned, so a shader workaround is needed. The affected
4380 * chips are VI and older except Stoney (GFX8.1).
4382 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4383 sscreen
->info
.chip_class
<= VI
&&
4384 sscreen
->info
.family
!= CHIP_STONEY
) {
4385 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4386 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4387 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4388 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4389 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4390 /* This isn't actually used in OpenGL. */
4391 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4393 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4394 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4395 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4397 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4398 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4399 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4400 if (channel
->normalized
) {
4401 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4402 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4404 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4406 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4408 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4409 if (channel
->normalized
) {
4410 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4411 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4413 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4415 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4418 } else if (channel
&& channel
->size
== 64 &&
4419 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4420 switch (desc
->nr_channels
) {
4423 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4424 swizzle
[0] = PIPE_SWIZZLE_X
;
4425 swizzle
[1] = PIPE_SWIZZLE_Y
;
4426 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4427 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4430 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4431 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4432 swizzle
[1] = PIPE_SWIZZLE_Y
;
4433 swizzle
[2] = PIPE_SWIZZLE_0
;
4434 swizzle
[3] = PIPE_SWIZZLE_0
;
4437 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4438 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4439 swizzle
[1] = PIPE_SWIZZLE_Y
;
4440 swizzle
[2] = PIPE_SWIZZLE_Z
;
4441 swizzle
[3] = PIPE_SWIZZLE_W
;
4446 } else if (channel
&& desc
->nr_channels
== 3) {
4447 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4449 if (channel
->size
== 8) {
4450 if (channel
->pure_integer
)
4451 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4453 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4454 } else if (channel
->size
== 16) {
4455 if (channel
->pure_integer
)
4456 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4458 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4462 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4463 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4464 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4465 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4466 S_008F0C_NUM_FORMAT(num_format
) |
4467 S_008F0C_DATA_FORMAT(data_format
);
4472 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4474 struct si_context
*sctx
= (struct si_context
*)ctx
;
4475 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4476 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4478 sctx
->vertex_elements
= v
;
4479 sctx
->vertex_buffers_dirty
= true;
4483 old
->count
!= v
->count
||
4484 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4485 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4486 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4487 sctx
->do_update_shaders
= true;
4489 if (v
&& v
->instance_divisor_is_fetched
) {
4490 struct pipe_constant_buffer cb
;
4493 cb
.user_buffer
= v
->instance_divisors
;
4494 cb
.buffer_offset
= 0;
4495 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4496 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4500 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4502 struct si_context
*sctx
= (struct si_context
*)ctx
;
4504 if (sctx
->vertex_elements
== state
)
4505 sctx
->vertex_elements
= NULL
;
4509 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4510 unsigned start_slot
, unsigned count
,
4511 const struct pipe_vertex_buffer
*buffers
)
4513 struct si_context
*sctx
= (struct si_context
*)ctx
;
4514 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4517 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4520 for (i
= 0; i
< count
; i
++) {
4521 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4522 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4523 struct pipe_resource
*buf
= src
->buffer
.resource
;
4525 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4526 dsti
->buffer_offset
= src
->buffer_offset
;
4527 dsti
->stride
= src
->stride
;
4528 si_context_add_resource_size(sctx
, buf
);
4530 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4533 for (i
= 0; i
< count
; i
++) {
4534 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4537 sctx
->vertex_buffers_dirty
= true;
4544 static void si_set_tess_state(struct pipe_context
*ctx
,
4545 const float default_outer_level
[4],
4546 const float default_inner_level
[2])
4548 struct si_context
*sctx
= (struct si_context
*)ctx
;
4549 struct pipe_constant_buffer cb
;
4552 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4553 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4556 cb
.user_buffer
= NULL
;
4557 cb
.buffer_size
= sizeof(array
);
4559 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4560 (void*)array
, sizeof(array
),
4563 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4564 pipe_resource_reference(&cb
.buffer
, NULL
);
4567 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4569 struct si_context
*sctx
= (struct si_context
*)ctx
;
4571 si_update_fb_dirtiness_after_rendering(sctx
);
4573 /* Multisample surfaces are flushed in si_decompress_textures. */
4574 if (sctx
->framebuffer
.uncompressed_cb_mask
)
4575 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4576 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4579 /* This only ensures coherency for shader image/buffer stores. */
4580 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4582 struct si_context
*sctx
= (struct si_context
*)ctx
;
4584 /* Subsequent commands must wait for all shader invocations to
4586 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4587 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4589 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4590 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
|
4591 SI_CONTEXT_INV_VMEM_L1
;
4593 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4594 PIPE_BARRIER_SHADER_BUFFER
|
4595 PIPE_BARRIER_TEXTURE
|
4596 PIPE_BARRIER_IMAGE
|
4597 PIPE_BARRIER_STREAMOUT_BUFFER
|
4598 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4599 /* As far as I can tell, L1 contents are written back to L2
4600 * automatically at end of shader, but the contents of other
4601 * L1 caches might still be stale. */
4602 sctx
->flags
|= SI_CONTEXT_INV_VMEM_L1
;
4605 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4606 /* Indices are read through TC L2 since VI.
4609 if (sctx
->screen
->info
.chip_class
<= CIK
)
4610 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4613 /* MSAA color, any depth and any stencil are flushed in
4614 * si_decompress_textures when needed.
4616 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4617 sctx
->framebuffer
.uncompressed_cb_mask
) {
4618 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4620 if (sctx
->chip_class
<= VI
)
4621 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4624 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4625 if (sctx
->screen
->info
.chip_class
<= VI
&&
4626 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4627 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4630 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4632 struct pipe_blend_state blend
;
4634 memset(&blend
, 0, sizeof(blend
));
4635 blend
.independent_blend_enable
= true;
4636 blend
.rt
[0].colormask
= 0xf;
4637 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4640 static void si_init_config(struct si_context
*sctx
);
4642 void si_init_state_functions(struct si_context
*sctx
)
4644 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
4645 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
4646 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
4647 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
4648 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
4649 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
4650 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
4651 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
4652 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
4653 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
4654 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
4656 sctx
->b
.create_blend_state
= si_create_blend_state
;
4657 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4658 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4659 sctx
->b
.set_blend_color
= si_set_blend_color
;
4661 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4662 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4663 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4665 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4666 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4667 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4669 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4670 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4671 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4672 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4673 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4675 sctx
->b
.set_clip_state
= si_set_clip_state
;
4676 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
4678 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
4680 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4681 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4683 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4684 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4686 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
4688 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
4689 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4690 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4691 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
4693 sctx
->b
.texture_barrier
= si_texture_barrier
;
4694 sctx
->b
.memory_barrier
= si_memory_barrier
;
4695 sctx
->b
.set_min_samples
= si_set_min_samples
;
4696 sctx
->b
.set_tess_state
= si_set_tess_state
;
4698 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
4700 sctx
->b
.draw_vbo
= si_draw_vbo
;
4702 si_init_config(sctx
);
4705 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4707 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4710 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4711 struct si_pm4_state
*pm4
, unsigned value
)
4713 unsigned reg
= sctx
->chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4714 R_00802C_GRBM_GFX_INDEX
;
4715 si_pm4_set_reg(pm4
, reg
, value
);
4718 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4719 struct si_pm4_state
*pm4
, unsigned se
)
4721 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4722 si_set_grbm_gfx_index(sctx
, pm4
,
4723 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4724 S_030800_SE_INDEX(se
)) |
4725 S_030800_SH_BROADCAST_WRITES(1) |
4726 S_030800_INSTANCE_BROADCAST_WRITES(1));
4730 si_write_harvested_raster_configs(struct si_context
*sctx
,
4731 struct si_pm4_state
*pm4
,
4732 unsigned raster_config
,
4733 unsigned raster_config_1
)
4735 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4736 unsigned raster_config_se
[4];
4739 ac_get_harvested_configs(&sctx
->screen
->info
,
4744 for (se
= 0; se
< num_se
; se
++) {
4745 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4746 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
4748 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4750 if (sctx
->chip_class
>= CIK
) {
4751 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4755 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4757 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4758 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4759 unsigned raster_config
, raster_config_1
;
4761 ac_get_raster_config(&sctx
->screen
->info
,
4765 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4766 /* Always use the default config when all backends are enabled
4767 * (or when we failed to determine the enabled backends).
4769 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4771 if (sctx
->chip_class
>= CIK
)
4772 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4775 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4779 static void si_init_config(struct si_context
*sctx
)
4781 struct si_screen
*sscreen
= sctx
->screen
;
4782 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4783 bool has_clear_state
= sscreen
->has_clear_state
;
4784 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4786 /* Only SI can disable CLEAR_STATE for now. */
4787 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
);
4792 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4793 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4794 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4795 si_pm4_cmd_end(pm4
, false);
4797 if (has_clear_state
) {
4798 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4799 si_pm4_cmd_add(pm4
, 0);
4800 si_pm4_cmd_end(pm4
, false);
4803 if (sctx
->chip_class
<= VI
)
4804 si_set_raster_config(sctx
, pm4
);
4806 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4807 if (!has_clear_state
)
4808 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4810 /* FIXME calculate these values somehow ??? */
4811 if (sctx
->chip_class
<= VI
) {
4812 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4813 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4816 if (!has_clear_state
) {
4817 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4818 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4819 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4822 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4823 if (!has_clear_state
)
4824 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4825 if (sctx
->chip_class
< CIK
)
4826 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4827 S_008A14_CLIP_VTX_REORDER_ENA(1));
4829 if (!has_clear_state
)
4830 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4832 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4833 * I don't know why. Deduced by trial and error.
4835 if (sctx
->chip_class
<= CIK
) {
4836 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4837 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4838 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4839 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4840 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4841 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4842 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4843 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4846 if (!has_clear_state
) {
4847 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4848 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4849 S_028230_ER_TRI(0xA) |
4850 S_028230_ER_POINT(0xA) |
4851 S_028230_ER_RECT(0xA) |
4852 /* Required by DX10_DIAMOND_TEST_ENA: */
4853 S_028230_ER_LINE_LR(0x1A) |
4854 S_028230_ER_LINE_RL(0x26) |
4855 S_028230_ER_LINE_TB(0xA) |
4856 S_028230_ER_LINE_BT(0xA));
4857 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4858 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4859 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4860 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4861 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4862 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4863 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4866 if (sctx
->chip_class
>= GFX9
) {
4867 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4868 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4869 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4871 /* These registers, when written, also overwrite the CLEAR_STATE
4872 * context, so we can't rely on CLEAR_STATE setting them.
4873 * It would be an issue if there was another UMD changing them.
4875 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4876 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4877 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4880 if (sctx
->chip_class
>= CIK
) {
4881 if (sctx
->chip_class
>= GFX9
) {
4882 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4883 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4885 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4886 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4887 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4888 S_00B41C_WAVE_LIMIT(0x3F));
4889 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
4890 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4892 /* If this is 0, Bonaire can hang even if GS isn't being used.
4893 * Other chips are unaffected. These are suboptimal values,
4894 * but we don't use on-chip GS.
4896 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4897 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4898 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4900 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
4901 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4903 /* Compute LATE_ALLOC_VS.LIMIT. */
4904 unsigned num_cu_per_sh
= sscreen
->info
.num_good_compute_units
/
4905 (sscreen
->info
.max_se
*
4906 sscreen
->info
.max_sh_per_se
);
4907 unsigned late_alloc_limit
; /* The limit is per SH. */
4909 if (sctx
->family
== CHIP_KABINI
) {
4910 late_alloc_limit
= 0; /* Potential hang on Kabini. */
4911 } else if (num_cu_per_sh
<= 4) {
4912 /* Too few available compute units per SH. Disallowing
4913 * VS to run on one CU could hurt us more than late VS
4914 * allocation would help.
4916 * 2 is the highest safe number that allows us to keep
4919 late_alloc_limit
= 2;
4921 /* This is a good initial value, allowing 1 late_alloc
4922 * wave per SIMD on num_cu - 2.
4924 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
4926 /* The limit is 0-based, so 0 means 1. */
4927 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
4928 late_alloc_limit
-= 1;
4931 /* VS can't execute on one CU if the limit is > 2. */
4932 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
4933 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
4934 S_00B118_WAVE_LIMIT(0x3F));
4935 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
4936 S_00B11C_LIMIT(late_alloc_limit
));
4937 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
4938 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4941 if (sctx
->chip_class
>= VI
) {
4942 unsigned vgt_tess_distribution
;
4944 vgt_tess_distribution
=
4945 S_028B50_ACCUM_ISOLINE(32) |
4946 S_028B50_ACCUM_TRI(11) |
4947 S_028B50_ACCUM_QUAD(11) |
4948 S_028B50_DONUT_SPLIT(16);
4950 /* Testing with Unigine Heaven extreme tesselation yielded best results
4951 * with TRAP_SPLIT = 3.
4953 if (sctx
->family
== CHIP_FIJI
||
4954 sctx
->family
>= CHIP_POLARIS10
)
4955 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
4957 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
4958 } else if (!has_clear_state
) {
4959 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
4960 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
4963 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4964 if (sctx
->chip_class
>= CIK
) {
4965 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
4966 S_028084_ADDRESS(border_color_va
>> 40));
4968 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4969 RADEON_PRIO_BORDER_COLORS
);
4971 if (sctx
->chip_class
>= GFX9
) {
4972 unsigned num_se
= sscreen
->info
.max_se
;
4973 unsigned pc_lines
= 0;
4975 switch (sctx
->family
) {
4987 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
4988 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
4989 S_028C48_MAX_PRIM_PER_BATCH(1023));
4990 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
4991 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4992 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
4995 si_pm4_upload_indirect_buffer(sctx
, pm4
);
4996 sctx
->init_config
= pm4
;