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radeonsi: convert constant buffers to si_descriptors
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528
529 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
530 state->fill_back != PIPE_POLYGON_MODE_FILL);
531
532 if (state->flatshade_first)
533 prov_vtx = 0;
534
535 rs->flatshade = state->flatshade;
536 rs->sprite_coord_enable = state->sprite_coord_enable;
537 rs->pa_sc_line_stipple = state->line_stipple_enable ?
538 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
539 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
540 rs->pa_su_sc_mode_cntl =
541 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
542 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
543 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
544 S_028814_FACE(!state->front_ccw) |
545 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
548 S_028814_POLY_MODE(polygon_dual_mode) |
549 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
551 rs->pa_cl_clip_cntl =
552 S_028810_PS_UCP_MODE(3) |
553 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
554 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
555 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
556
557 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
558
559 /* offset */
560 rs->offset_units = state->offset_units;
561 rs->offset_scale = state->offset_scale * 12.0f;
562
563 tmp = S_0286D4_FLAT_SHADE_ENA(1);
564 if (state->sprite_coord_enable) {
565 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
566 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
567 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
568 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
569 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
570 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
571 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
572 }
573 }
574 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
575
576 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
577 /* point size 12.4 fixed point */
578 tmp = (unsigned)(state->point_size * 8.0);
579 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
580
581 if (state->point_size_per_vertex) {
582 psize_min = util_get_min_point_size(state);
583 psize_max = 8192;
584 } else {
585 /* Force the point size to be as if the vertex output was disabled. */
586 psize_min = state->point_size;
587 psize_max = state->point_size;
588 }
589 /* Divide by two, because 0.5 = 1 pixel. */
590 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
591 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
592 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
593
594 tmp = (unsigned)state->line_width * 8;
595 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
596 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
597 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
598 S_028A48_MSAA_ENABLE(state->multisample));
599
600 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
601 S_028BE4_PIX_CENTER(state->half_pixel_center) |
602 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
603 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
604 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
605 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
607
608 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
609 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
610
611 return rs;
612 }
613
614 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
615 {
616 struct r600_context *rctx = (struct r600_context *)ctx;
617 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
618
619 if (state == NULL)
620 return;
621
622 // TODO
623 rctx->sprite_coord_enable = rs->sprite_coord_enable;
624 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
625 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
626
627 si_pm4_bind_state(rctx, rasterizer, rs);
628 si_update_fb_rs_state(rctx);
629 }
630
631 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
632 {
633 struct r600_context *rctx = (struct r600_context *)ctx;
634 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
635 }
636
637 /*
638 * infeered state between dsa and stencil ref
639 */
640 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
641 {
642 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
643 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
644 struct si_state_dsa *dsa = rctx->queued.named.dsa;
645
646 if (pm4 == NULL)
647 return;
648
649 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
650 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
651 S_028430_STENCILMASK(dsa->valuemask[0]) |
652 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
653 S_028430_STENCILOPVAL(1));
654 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
655 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
656 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
657 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
658 S_028434_STENCILOPVAL_BF(1));
659
660 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
661 }
662
663 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
664 const struct pipe_stencil_ref *state)
665 {
666 struct r600_context *rctx = (struct r600_context *)ctx;
667 rctx->stencil_ref = *state;
668 si_update_dsa_stencil_ref(rctx);
669 }
670
671
672 /*
673 * DSA
674 */
675
676 static uint32_t si_translate_stencil_op(int s_op)
677 {
678 switch (s_op) {
679 case PIPE_STENCIL_OP_KEEP:
680 return V_02842C_STENCIL_KEEP;
681 case PIPE_STENCIL_OP_ZERO:
682 return V_02842C_STENCIL_ZERO;
683 case PIPE_STENCIL_OP_REPLACE:
684 return V_02842C_STENCIL_REPLACE_TEST;
685 case PIPE_STENCIL_OP_INCR:
686 return V_02842C_STENCIL_ADD_CLAMP;
687 case PIPE_STENCIL_OP_DECR:
688 return V_02842C_STENCIL_SUB_CLAMP;
689 case PIPE_STENCIL_OP_INCR_WRAP:
690 return V_02842C_STENCIL_ADD_WRAP;
691 case PIPE_STENCIL_OP_DECR_WRAP:
692 return V_02842C_STENCIL_SUB_WRAP;
693 case PIPE_STENCIL_OP_INVERT:
694 return V_02842C_STENCIL_INVERT;
695 default:
696 R600_ERR("Unknown stencil op %d", s_op);
697 assert(0);
698 break;
699 }
700 return 0;
701 }
702
703 static void *si_create_dsa_state(struct pipe_context *ctx,
704 const struct pipe_depth_stencil_alpha_state *state)
705 {
706 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
707 struct si_pm4_state *pm4 = &dsa->pm4;
708 unsigned db_depth_control;
709 unsigned db_render_override, db_render_control;
710 uint32_t db_stencil_control = 0;
711
712 if (dsa == NULL) {
713 return NULL;
714 }
715
716 dsa->valuemask[0] = state->stencil[0].valuemask;
717 dsa->valuemask[1] = state->stencil[1].valuemask;
718 dsa->writemask[0] = state->stencil[0].writemask;
719 dsa->writemask[1] = state->stencil[1].writemask;
720
721 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
722 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
723 S_028800_ZFUNC(state->depth.func);
724
725 /* stencil */
726 if (state->stencil[0].enabled) {
727 db_depth_control |= S_028800_STENCIL_ENABLE(1);
728 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
729 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
730 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
731 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
732
733 if (state->stencil[1].enabled) {
734 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
735 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
736 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
737 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
738 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
739 }
740 }
741
742 /* alpha */
743 if (state->alpha.enabled) {
744 dsa->alpha_func = state->alpha.func;
745 dsa->alpha_ref = state->alpha.ref_value;
746 } else {
747 dsa->alpha_func = PIPE_FUNC_ALWAYS;
748 }
749
750 /* misc */
751 db_render_control = 0;
752 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
753 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
754 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
755 /* TODO db_render_override depends on query */
756 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
757 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
758 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
759 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
760 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
761 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
762 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
763 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
764 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
765 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
766 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
767 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
768 dsa->db_render_override = db_render_override;
769
770 return dsa;
771 }
772
773 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
774 {
775 struct r600_context *rctx = (struct r600_context *)ctx;
776 struct si_state_dsa *dsa = state;
777
778 if (state == NULL)
779 return;
780
781 si_pm4_bind_state(rctx, dsa, dsa);
782 si_update_dsa_stencil_ref(rctx);
783 }
784
785 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
786 {
787 struct r600_context *rctx = (struct r600_context *)ctx;
788 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
789 }
790
791 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
792 bool copy_stencil, int sample)
793 {
794 struct pipe_depth_stencil_alpha_state dsa;
795 struct si_state_dsa *state;
796
797 memset(&dsa, 0, sizeof(dsa));
798
799 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
800 if (copy_depth || copy_stencil) {
801 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
802 S_028000_DEPTH_COPY(copy_depth) |
803 S_028000_STENCIL_COPY(copy_stencil) |
804 S_028000_COPY_CENTROID(1) |
805 S_028000_COPY_SAMPLE(sample));
806 } else {
807 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
808 S_028000_DEPTH_COMPRESS_DISABLE(1) |
809 S_028000_STENCIL_COMPRESS_DISABLE(1));
810 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
811 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
812 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
813 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
814 S_02800C_DISABLE_TILE_RATE_TILES(1));
815 }
816
817 return state;
818 }
819
820 /*
821 * format translation
822 */
823 static uint32_t si_translate_colorformat(enum pipe_format format)
824 {
825 switch (format) {
826 /* 8-bit buffers. */
827 case PIPE_FORMAT_A8_UNORM:
828 case PIPE_FORMAT_A8_SNORM:
829 case PIPE_FORMAT_A8_UINT:
830 case PIPE_FORMAT_A8_SINT:
831 case PIPE_FORMAT_I8_UNORM:
832 case PIPE_FORMAT_I8_SNORM:
833 case PIPE_FORMAT_I8_UINT:
834 case PIPE_FORMAT_I8_SINT:
835 case PIPE_FORMAT_L8_UNORM:
836 case PIPE_FORMAT_L8_SNORM:
837 case PIPE_FORMAT_L8_UINT:
838 case PIPE_FORMAT_L8_SINT:
839 case PIPE_FORMAT_L8_SRGB:
840 case PIPE_FORMAT_R8_UNORM:
841 case PIPE_FORMAT_R8_SNORM:
842 case PIPE_FORMAT_R8_UINT:
843 case PIPE_FORMAT_R8_SINT:
844 return V_028C70_COLOR_8;
845
846 /* 16-bit buffers. */
847 case PIPE_FORMAT_B5G6R5_UNORM:
848 return V_028C70_COLOR_5_6_5;
849
850 case PIPE_FORMAT_B5G5R5A1_UNORM:
851 case PIPE_FORMAT_B5G5R5X1_UNORM:
852 return V_028C70_COLOR_1_5_5_5;
853
854 case PIPE_FORMAT_B4G4R4A4_UNORM:
855 case PIPE_FORMAT_B4G4R4X4_UNORM:
856 return V_028C70_COLOR_4_4_4_4;
857
858 case PIPE_FORMAT_L8A8_UNORM:
859 case PIPE_FORMAT_L8A8_SNORM:
860 case PIPE_FORMAT_L8A8_UINT:
861 case PIPE_FORMAT_L8A8_SINT:
862 case PIPE_FORMAT_R8G8_SNORM:
863 case PIPE_FORMAT_R8G8_UNORM:
864 case PIPE_FORMAT_R8G8_UINT:
865 case PIPE_FORMAT_R8G8_SINT:
866 return V_028C70_COLOR_8_8;
867
868 case PIPE_FORMAT_Z16_UNORM:
869 case PIPE_FORMAT_R16_UNORM:
870 case PIPE_FORMAT_R16_SNORM:
871 case PIPE_FORMAT_R16_UINT:
872 case PIPE_FORMAT_R16_SINT:
873 case PIPE_FORMAT_R16_FLOAT:
874 case PIPE_FORMAT_L16_UNORM:
875 case PIPE_FORMAT_L16_SNORM:
876 case PIPE_FORMAT_L16_FLOAT:
877 case PIPE_FORMAT_I16_UNORM:
878 case PIPE_FORMAT_I16_SNORM:
879 case PIPE_FORMAT_I16_FLOAT:
880 case PIPE_FORMAT_A16_UNORM:
881 case PIPE_FORMAT_A16_SNORM:
882 case PIPE_FORMAT_A16_FLOAT:
883 return V_028C70_COLOR_16;
884
885 /* 32-bit buffers. */
886 case PIPE_FORMAT_A8B8G8R8_SRGB:
887 case PIPE_FORMAT_A8B8G8R8_UNORM:
888 case PIPE_FORMAT_A8R8G8B8_UNORM:
889 case PIPE_FORMAT_B8G8R8A8_SRGB:
890 case PIPE_FORMAT_B8G8R8A8_UNORM:
891 case PIPE_FORMAT_B8G8R8X8_UNORM:
892 case PIPE_FORMAT_R8G8B8A8_SNORM:
893 case PIPE_FORMAT_R8G8B8A8_UNORM:
894 case PIPE_FORMAT_R8G8B8X8_UNORM:
895 case PIPE_FORMAT_R8G8B8X8_SNORM:
896 case PIPE_FORMAT_R8G8B8X8_SRGB:
897 case PIPE_FORMAT_R8G8B8X8_UINT:
898 case PIPE_FORMAT_R8G8B8X8_SINT:
899 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
900 case PIPE_FORMAT_X8B8G8R8_UNORM:
901 case PIPE_FORMAT_X8R8G8B8_UNORM:
902 case PIPE_FORMAT_R8G8B8A8_SSCALED:
903 case PIPE_FORMAT_R8G8B8A8_USCALED:
904 case PIPE_FORMAT_R8G8B8A8_SINT:
905 case PIPE_FORMAT_R8G8B8A8_UINT:
906 return V_028C70_COLOR_8_8_8_8;
907
908 case PIPE_FORMAT_R10G10B10A2_UNORM:
909 case PIPE_FORMAT_R10G10B10X2_SNORM:
910 case PIPE_FORMAT_B10G10R10A2_UNORM:
911 case PIPE_FORMAT_B10G10R10A2_UINT:
912 case PIPE_FORMAT_B10G10R10X2_UNORM:
913 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
914 return V_028C70_COLOR_2_10_10_10;
915
916 case PIPE_FORMAT_Z24X8_UNORM:
917 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
918 return V_028C70_COLOR_8_24;
919
920 case PIPE_FORMAT_S8X24_UINT:
921 case PIPE_FORMAT_X8Z24_UNORM:
922 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
923 return V_028C70_COLOR_24_8;
924
925 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
926 return V_028C70_COLOR_X24_8_32_FLOAT;
927
928 case PIPE_FORMAT_I32_FLOAT:
929 case PIPE_FORMAT_L32_FLOAT:
930 case PIPE_FORMAT_R32_FLOAT:
931 case PIPE_FORMAT_A32_FLOAT:
932 case PIPE_FORMAT_Z32_FLOAT:
933 return V_028C70_COLOR_32;
934
935 case PIPE_FORMAT_L16A16_UNORM:
936 case PIPE_FORMAT_L16A16_SNORM:
937 case PIPE_FORMAT_L16A16_FLOAT:
938 case PIPE_FORMAT_R16G16_SSCALED:
939 case PIPE_FORMAT_R16G16_UNORM:
940 case PIPE_FORMAT_R16G16_SNORM:
941 case PIPE_FORMAT_R16G16_UINT:
942 case PIPE_FORMAT_R16G16_SINT:
943 case PIPE_FORMAT_R16G16_FLOAT:
944 return V_028C70_COLOR_16_16;
945
946 case PIPE_FORMAT_R11G11B10_FLOAT:
947 return V_028C70_COLOR_10_11_11;
948
949 /* 64-bit buffers. */
950 case PIPE_FORMAT_R16G16B16A16_UINT:
951 case PIPE_FORMAT_R16G16B16A16_SINT:
952 case PIPE_FORMAT_R16G16B16A16_USCALED:
953 case PIPE_FORMAT_R16G16B16A16_SSCALED:
954 case PIPE_FORMAT_R16G16B16A16_UNORM:
955 case PIPE_FORMAT_R16G16B16A16_SNORM:
956 case PIPE_FORMAT_R16G16B16A16_FLOAT:
957 case PIPE_FORMAT_R16G16B16X16_UNORM:
958 case PIPE_FORMAT_R16G16B16X16_SNORM:
959 case PIPE_FORMAT_R16G16B16X16_FLOAT:
960 case PIPE_FORMAT_R16G16B16X16_UINT:
961 case PIPE_FORMAT_R16G16B16X16_SINT:
962 return V_028C70_COLOR_16_16_16_16;
963
964 case PIPE_FORMAT_L32A32_FLOAT:
965 case PIPE_FORMAT_L32A32_UINT:
966 case PIPE_FORMAT_L32A32_SINT:
967 case PIPE_FORMAT_R32G32_FLOAT:
968 case PIPE_FORMAT_R32G32_USCALED:
969 case PIPE_FORMAT_R32G32_SSCALED:
970 case PIPE_FORMAT_R32G32_SINT:
971 case PIPE_FORMAT_R32G32_UINT:
972 return V_028C70_COLOR_32_32;
973
974 /* 128-bit buffers. */
975 case PIPE_FORMAT_R32G32B32A32_SNORM:
976 case PIPE_FORMAT_R32G32B32A32_UNORM:
977 case PIPE_FORMAT_R32G32B32A32_SSCALED:
978 case PIPE_FORMAT_R32G32B32A32_USCALED:
979 case PIPE_FORMAT_R32G32B32A32_SINT:
980 case PIPE_FORMAT_R32G32B32A32_UINT:
981 case PIPE_FORMAT_R32G32B32A32_FLOAT:
982 case PIPE_FORMAT_R32G32B32X32_FLOAT:
983 case PIPE_FORMAT_R32G32B32X32_UINT:
984 case PIPE_FORMAT_R32G32B32X32_SINT:
985 return V_028C70_COLOR_32_32_32_32;
986
987 /* YUV buffers. */
988 case PIPE_FORMAT_UYVY:
989 case PIPE_FORMAT_YUYV:
990 /* 96-bit buffers. */
991 case PIPE_FORMAT_R32G32B32_FLOAT:
992 /* 8-bit buffers. */
993 case PIPE_FORMAT_L4A4_UNORM:
994 case PIPE_FORMAT_R4A4_UNORM:
995 case PIPE_FORMAT_A4R4_UNORM:
996 default:
997 return V_028C70_COLOR_INVALID; /* Unsupported. */
998 }
999 }
1000
1001 static uint32_t si_translate_colorswap(enum pipe_format format)
1002 {
1003 switch (format) {
1004 /* 8-bit buffers. */
1005 case PIPE_FORMAT_L4A4_UNORM:
1006 case PIPE_FORMAT_A4R4_UNORM:
1007 return V_028C70_SWAP_ALT;
1008
1009 case PIPE_FORMAT_A8_UNORM:
1010 case PIPE_FORMAT_A8_SNORM:
1011 case PIPE_FORMAT_A8_UINT:
1012 case PIPE_FORMAT_A8_SINT:
1013 case PIPE_FORMAT_R4A4_UNORM:
1014 return V_028C70_SWAP_ALT_REV;
1015 case PIPE_FORMAT_I8_UNORM:
1016 case PIPE_FORMAT_I8_SNORM:
1017 case PIPE_FORMAT_L8_UNORM:
1018 case PIPE_FORMAT_L8_SNORM:
1019 case PIPE_FORMAT_I8_UINT:
1020 case PIPE_FORMAT_I8_SINT:
1021 case PIPE_FORMAT_L8_UINT:
1022 case PIPE_FORMAT_L8_SINT:
1023 case PIPE_FORMAT_L8_SRGB:
1024 case PIPE_FORMAT_R8_UNORM:
1025 case PIPE_FORMAT_R8_SNORM:
1026 case PIPE_FORMAT_R8_UINT:
1027 case PIPE_FORMAT_R8_SINT:
1028 return V_028C70_SWAP_STD;
1029
1030 /* 16-bit buffers. */
1031 case PIPE_FORMAT_B5G6R5_UNORM:
1032 return V_028C70_SWAP_STD_REV;
1033
1034 case PIPE_FORMAT_B5G5R5A1_UNORM:
1035 case PIPE_FORMAT_B5G5R5X1_UNORM:
1036 return V_028C70_SWAP_ALT;
1037
1038 case PIPE_FORMAT_B4G4R4A4_UNORM:
1039 case PIPE_FORMAT_B4G4R4X4_UNORM:
1040 return V_028C70_SWAP_ALT;
1041
1042 case PIPE_FORMAT_Z16_UNORM:
1043 return V_028C70_SWAP_STD;
1044
1045 case PIPE_FORMAT_L8A8_UNORM:
1046 case PIPE_FORMAT_L8A8_SNORM:
1047 case PIPE_FORMAT_L8A8_UINT:
1048 case PIPE_FORMAT_L8A8_SINT:
1049 return V_028C70_SWAP_ALT;
1050 case PIPE_FORMAT_R8G8_SNORM:
1051 case PIPE_FORMAT_R8G8_UNORM:
1052 case PIPE_FORMAT_R8G8_UINT:
1053 case PIPE_FORMAT_R8G8_SINT:
1054 return V_028C70_SWAP_STD;
1055
1056 case PIPE_FORMAT_I16_UNORM:
1057 case PIPE_FORMAT_I16_SNORM:
1058 case PIPE_FORMAT_I16_FLOAT:
1059 case PIPE_FORMAT_L16_UNORM:
1060 case PIPE_FORMAT_L16_SNORM:
1061 case PIPE_FORMAT_L16_FLOAT:
1062 case PIPE_FORMAT_R16_UNORM:
1063 case PIPE_FORMAT_R16_SNORM:
1064 case PIPE_FORMAT_R16_UINT:
1065 case PIPE_FORMAT_R16_SINT:
1066 case PIPE_FORMAT_R16_FLOAT:
1067 return V_028C70_SWAP_STD;
1068
1069 case PIPE_FORMAT_A16_UNORM:
1070 case PIPE_FORMAT_A16_SNORM:
1071 case PIPE_FORMAT_A16_FLOAT:
1072 return V_028C70_SWAP_ALT_REV;
1073
1074 /* 32-bit buffers. */
1075 case PIPE_FORMAT_A8B8G8R8_SRGB:
1076 return V_028C70_SWAP_STD_REV;
1077 case PIPE_FORMAT_B8G8R8A8_SRGB:
1078 return V_028C70_SWAP_ALT;
1079
1080 case PIPE_FORMAT_B8G8R8A8_UNORM:
1081 case PIPE_FORMAT_B8G8R8X8_UNORM:
1082 return V_028C70_SWAP_ALT;
1083
1084 case PIPE_FORMAT_A8R8G8B8_UNORM:
1085 case PIPE_FORMAT_X8R8G8B8_UNORM:
1086 return V_028C70_SWAP_ALT_REV;
1087 case PIPE_FORMAT_R8G8B8A8_SNORM:
1088 case PIPE_FORMAT_R8G8B8A8_UNORM:
1089 case PIPE_FORMAT_R8G8B8A8_SSCALED:
1090 case PIPE_FORMAT_R8G8B8A8_USCALED:
1091 case PIPE_FORMAT_R8G8B8A8_SINT:
1092 case PIPE_FORMAT_R8G8B8A8_UINT:
1093 case PIPE_FORMAT_R8G8B8X8_UNORM:
1094 case PIPE_FORMAT_R8G8B8X8_SNORM:
1095 case PIPE_FORMAT_R8G8B8X8_SRGB:
1096 case PIPE_FORMAT_R8G8B8X8_UINT:
1097 case PIPE_FORMAT_R8G8B8X8_SINT:
1098 return V_028C70_SWAP_STD;
1099
1100 case PIPE_FORMAT_A8B8G8R8_UNORM:
1101 case PIPE_FORMAT_X8B8G8R8_UNORM:
1102 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
1103 return V_028C70_SWAP_STD_REV;
1104
1105 case PIPE_FORMAT_Z24X8_UNORM:
1106 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1107 return V_028C70_SWAP_STD;
1108
1109 case PIPE_FORMAT_S8X24_UINT:
1110 case PIPE_FORMAT_X8Z24_UNORM:
1111 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1112 return V_028C70_SWAP_STD_REV;
1113
1114 case PIPE_FORMAT_R10G10B10A2_UNORM:
1115 case PIPE_FORMAT_R10G10B10X2_SNORM:
1116 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
1117 return V_028C70_SWAP_STD;
1118
1119 case PIPE_FORMAT_B10G10R10A2_UNORM:
1120 case PIPE_FORMAT_B10G10R10A2_UINT:
1121 case PIPE_FORMAT_B10G10R10X2_UNORM:
1122 return V_028C70_SWAP_ALT;
1123
1124 case PIPE_FORMAT_R11G11B10_FLOAT:
1125 case PIPE_FORMAT_I32_FLOAT:
1126 case PIPE_FORMAT_L32_FLOAT:
1127 case PIPE_FORMAT_R32_FLOAT:
1128 case PIPE_FORMAT_R32_UINT:
1129 case PIPE_FORMAT_R32_SINT:
1130 case PIPE_FORMAT_Z32_FLOAT:
1131 case PIPE_FORMAT_R16G16_FLOAT:
1132 case PIPE_FORMAT_R16G16_UNORM:
1133 case PIPE_FORMAT_R16G16_SNORM:
1134 case PIPE_FORMAT_R16G16_UINT:
1135 case PIPE_FORMAT_R16G16_SINT:
1136 return V_028C70_SWAP_STD;
1137
1138 case PIPE_FORMAT_L16A16_UNORM:
1139 case PIPE_FORMAT_L16A16_SNORM:
1140 case PIPE_FORMAT_L16A16_FLOAT:
1141 return V_028C70_SWAP_ALT;
1142
1143 case PIPE_FORMAT_A32_FLOAT:
1144 return V_028C70_SWAP_ALT_REV;
1145
1146 /* 64-bit buffers. */
1147 case PIPE_FORMAT_R32G32_FLOAT:
1148 case PIPE_FORMAT_R32G32_UINT:
1149 case PIPE_FORMAT_R32G32_SINT:
1150 case PIPE_FORMAT_R16G16B16A16_UNORM:
1151 case PIPE_FORMAT_R16G16B16A16_SNORM:
1152 case PIPE_FORMAT_R16G16B16A16_USCALED:
1153 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1154 case PIPE_FORMAT_R16G16B16A16_UINT:
1155 case PIPE_FORMAT_R16G16B16A16_SINT:
1156 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1157 case PIPE_FORMAT_R16G16B16X16_UNORM:
1158 case PIPE_FORMAT_R16G16B16X16_SNORM:
1159 case PIPE_FORMAT_R16G16B16X16_FLOAT:
1160 case PIPE_FORMAT_R16G16B16X16_UINT:
1161 case PIPE_FORMAT_R16G16B16X16_SINT:
1162 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1163 return V_028C70_SWAP_STD;
1164
1165 case PIPE_FORMAT_L32A32_FLOAT:
1166 case PIPE_FORMAT_L32A32_UINT:
1167 case PIPE_FORMAT_L32A32_SINT:
1168 return V_028C70_SWAP_ALT;
1169
1170 /* 128-bit buffers. */
1171 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1172 case PIPE_FORMAT_R32G32B32A32_SNORM:
1173 case PIPE_FORMAT_R32G32B32A32_UNORM:
1174 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1175 case PIPE_FORMAT_R32G32B32A32_USCALED:
1176 case PIPE_FORMAT_R32G32B32A32_SINT:
1177 case PIPE_FORMAT_R32G32B32A32_UINT:
1178 case PIPE_FORMAT_R32G32B32X32_FLOAT:
1179 case PIPE_FORMAT_R32G32B32X32_UINT:
1180 case PIPE_FORMAT_R32G32B32X32_SINT:
1181 return V_028C70_SWAP_STD;
1182 default:
1183 R600_ERR("unsupported colorswap format %d\n", format);
1184 return ~0U;
1185 }
1186 return ~0U;
1187 }
1188
1189 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1190 {
1191 if (R600_BIG_ENDIAN) {
1192 switch(colorformat) {
1193 /* 8-bit buffers. */
1194 case V_028C70_COLOR_8:
1195 return V_028C70_ENDIAN_NONE;
1196
1197 /* 16-bit buffers. */
1198 case V_028C70_COLOR_5_6_5:
1199 case V_028C70_COLOR_1_5_5_5:
1200 case V_028C70_COLOR_4_4_4_4:
1201 case V_028C70_COLOR_16:
1202 case V_028C70_COLOR_8_8:
1203 return V_028C70_ENDIAN_8IN16;
1204
1205 /* 32-bit buffers. */
1206 case V_028C70_COLOR_8_8_8_8:
1207 case V_028C70_COLOR_2_10_10_10:
1208 case V_028C70_COLOR_8_24:
1209 case V_028C70_COLOR_24_8:
1210 case V_028C70_COLOR_16_16:
1211 return V_028C70_ENDIAN_8IN32;
1212
1213 /* 64-bit buffers. */
1214 case V_028C70_COLOR_16_16_16_16:
1215 return V_028C70_ENDIAN_8IN16;
1216
1217 case V_028C70_COLOR_32_32:
1218 return V_028C70_ENDIAN_8IN32;
1219
1220 /* 128-bit buffers. */
1221 case V_028C70_COLOR_32_32_32_32:
1222 return V_028C70_ENDIAN_8IN32;
1223 default:
1224 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1225 }
1226 } else {
1227 return V_028C70_ENDIAN_NONE;
1228 }
1229 }
1230
1231 /* Returns the size in bits of the widest component of a CB format */
1232 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1233 {
1234 switch(colorformat) {
1235 case V_028C70_COLOR_4_4_4_4:
1236 return 4;
1237
1238 case V_028C70_COLOR_1_5_5_5:
1239 case V_028C70_COLOR_5_5_5_1:
1240 return 5;
1241
1242 case V_028C70_COLOR_5_6_5:
1243 return 6;
1244
1245 case V_028C70_COLOR_8:
1246 case V_028C70_COLOR_8_8:
1247 case V_028C70_COLOR_8_8_8_8:
1248 return 8;
1249
1250 case V_028C70_COLOR_10_10_10_2:
1251 case V_028C70_COLOR_2_10_10_10:
1252 return 10;
1253
1254 case V_028C70_COLOR_10_11_11:
1255 case V_028C70_COLOR_11_11_10:
1256 return 11;
1257
1258 case V_028C70_COLOR_16:
1259 case V_028C70_COLOR_16_16:
1260 case V_028C70_COLOR_16_16_16_16:
1261 return 16;
1262
1263 case V_028C70_COLOR_8_24:
1264 case V_028C70_COLOR_24_8:
1265 return 24;
1266
1267 case V_028C70_COLOR_32:
1268 case V_028C70_COLOR_32_32:
1269 case V_028C70_COLOR_32_32_32_32:
1270 case V_028C70_COLOR_X24_8_32_FLOAT:
1271 return 32;
1272 }
1273
1274 assert(!"Unknown maximum component size");
1275 return 0;
1276 }
1277
1278 static uint32_t si_translate_dbformat(enum pipe_format format)
1279 {
1280 switch (format) {
1281 case PIPE_FORMAT_Z16_UNORM:
1282 return V_028040_Z_16;
1283 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1284 case PIPE_FORMAT_X8Z24_UNORM:
1285 case PIPE_FORMAT_Z24X8_UNORM:
1286 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1287 return V_028040_Z_24; /* deprecated on SI */
1288 case PIPE_FORMAT_Z32_FLOAT:
1289 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1290 return V_028040_Z_32_FLOAT;
1291 default:
1292 return V_028040_Z_INVALID;
1293 }
1294 }
1295
1296 /*
1297 * Texture translation
1298 */
1299
1300 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1301 enum pipe_format format,
1302 const struct util_format_description *desc,
1303 int first_non_void)
1304 {
1305 struct r600_screen *rscreen = (struct r600_screen*)screen;
1306 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1307 boolean uniform = TRUE;
1308 int i;
1309
1310 /* Colorspace (return non-RGB formats directly). */
1311 switch (desc->colorspace) {
1312 /* Depth stencil formats */
1313 case UTIL_FORMAT_COLORSPACE_ZS:
1314 switch (format) {
1315 case PIPE_FORMAT_Z16_UNORM:
1316 return V_008F14_IMG_DATA_FORMAT_16;
1317 case PIPE_FORMAT_X24S8_UINT:
1318 case PIPE_FORMAT_Z24X8_UNORM:
1319 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1320 return V_008F14_IMG_DATA_FORMAT_8_24;
1321 case PIPE_FORMAT_X8Z24_UNORM:
1322 case PIPE_FORMAT_S8X24_UINT:
1323 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1324 return V_008F14_IMG_DATA_FORMAT_24_8;
1325 case PIPE_FORMAT_S8_UINT:
1326 return V_008F14_IMG_DATA_FORMAT_8;
1327 case PIPE_FORMAT_Z32_FLOAT:
1328 return V_008F14_IMG_DATA_FORMAT_32;
1329 case PIPE_FORMAT_X32_S8X24_UINT:
1330 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1331 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1332 default:
1333 goto out_unknown;
1334 }
1335
1336 case UTIL_FORMAT_COLORSPACE_YUV:
1337 goto out_unknown; /* TODO */
1338
1339 case UTIL_FORMAT_COLORSPACE_SRGB:
1340 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1341 goto out_unknown;
1342 break;
1343
1344 default:
1345 break;
1346 }
1347
1348 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1349 if (!enable_s3tc)
1350 goto out_unknown;
1351
1352 switch (format) {
1353 case PIPE_FORMAT_RGTC1_SNORM:
1354 case PIPE_FORMAT_LATC1_SNORM:
1355 case PIPE_FORMAT_RGTC1_UNORM:
1356 case PIPE_FORMAT_LATC1_UNORM:
1357 return V_008F14_IMG_DATA_FORMAT_BC4;
1358 case PIPE_FORMAT_RGTC2_SNORM:
1359 case PIPE_FORMAT_LATC2_SNORM:
1360 case PIPE_FORMAT_RGTC2_UNORM:
1361 case PIPE_FORMAT_LATC2_UNORM:
1362 return V_008F14_IMG_DATA_FORMAT_BC5;
1363 default:
1364 goto out_unknown;
1365 }
1366 }
1367
1368 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1369
1370 if (!enable_s3tc)
1371 goto out_unknown;
1372
1373 if (!util_format_s3tc_enabled) {
1374 goto out_unknown;
1375 }
1376
1377 switch (format) {
1378 case PIPE_FORMAT_DXT1_RGB:
1379 case PIPE_FORMAT_DXT1_RGBA:
1380 case PIPE_FORMAT_DXT1_SRGB:
1381 case PIPE_FORMAT_DXT1_SRGBA:
1382 return V_008F14_IMG_DATA_FORMAT_BC1;
1383 case PIPE_FORMAT_DXT3_RGBA:
1384 case PIPE_FORMAT_DXT3_SRGBA:
1385 return V_008F14_IMG_DATA_FORMAT_BC2;
1386 case PIPE_FORMAT_DXT5_RGBA:
1387 case PIPE_FORMAT_DXT5_SRGBA:
1388 return V_008F14_IMG_DATA_FORMAT_BC3;
1389 default:
1390 goto out_unknown;
1391 }
1392 }
1393
1394 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1395 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1396 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1397 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1398 }
1399
1400 /* R8G8Bx_SNORM - TODO CxV8U8 */
1401
1402 /* See whether the components are of the same size. */
1403 for (i = 1; i < desc->nr_channels; i++) {
1404 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1405 }
1406
1407 /* Non-uniform formats. */
1408 if (!uniform) {
1409 switch(desc->nr_channels) {
1410 case 3:
1411 if (desc->channel[0].size == 5 &&
1412 desc->channel[1].size == 6 &&
1413 desc->channel[2].size == 5) {
1414 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1415 }
1416 goto out_unknown;
1417 case 4:
1418 if (desc->channel[0].size == 5 &&
1419 desc->channel[1].size == 5 &&
1420 desc->channel[2].size == 5 &&
1421 desc->channel[3].size == 1) {
1422 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1423 }
1424 if (desc->channel[0].size == 10 &&
1425 desc->channel[1].size == 10 &&
1426 desc->channel[2].size == 10 &&
1427 desc->channel[3].size == 2) {
1428 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1429 }
1430 goto out_unknown;
1431 }
1432 goto out_unknown;
1433 }
1434
1435 if (first_non_void < 0 || first_non_void > 3)
1436 goto out_unknown;
1437
1438 /* uniform formats */
1439 switch (desc->channel[first_non_void].size) {
1440 case 4:
1441 switch (desc->nr_channels) {
1442 #if 0 /* Not supported for render targets */
1443 case 2:
1444 return V_008F14_IMG_DATA_FORMAT_4_4;
1445 #endif
1446 case 4:
1447 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1448 }
1449 break;
1450 case 8:
1451 switch (desc->nr_channels) {
1452 case 1:
1453 return V_008F14_IMG_DATA_FORMAT_8;
1454 case 2:
1455 return V_008F14_IMG_DATA_FORMAT_8_8;
1456 case 4:
1457 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1458 }
1459 break;
1460 case 16:
1461 switch (desc->nr_channels) {
1462 case 1:
1463 return V_008F14_IMG_DATA_FORMAT_16;
1464 case 2:
1465 return V_008F14_IMG_DATA_FORMAT_16_16;
1466 case 4:
1467 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1468 }
1469 break;
1470 case 32:
1471 switch (desc->nr_channels) {
1472 case 1:
1473 return V_008F14_IMG_DATA_FORMAT_32;
1474 case 2:
1475 return V_008F14_IMG_DATA_FORMAT_32_32;
1476 #if 0 /* Not supported for render targets */
1477 case 3:
1478 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1479 #endif
1480 case 4:
1481 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1482 }
1483 }
1484
1485 out_unknown:
1486 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1487 return ~0;
1488 }
1489
1490 static unsigned si_tex_wrap(unsigned wrap)
1491 {
1492 switch (wrap) {
1493 default:
1494 case PIPE_TEX_WRAP_REPEAT:
1495 return V_008F30_SQ_TEX_WRAP;
1496 case PIPE_TEX_WRAP_CLAMP:
1497 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1498 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1499 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1500 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1501 return V_008F30_SQ_TEX_CLAMP_BORDER;
1502 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1503 return V_008F30_SQ_TEX_MIRROR;
1504 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1505 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1506 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1507 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1508 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1509 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1510 }
1511 }
1512
1513 static unsigned si_tex_filter(unsigned filter)
1514 {
1515 switch (filter) {
1516 default:
1517 case PIPE_TEX_FILTER_NEAREST:
1518 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1519 case PIPE_TEX_FILTER_LINEAR:
1520 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1521 }
1522 }
1523
1524 static unsigned si_tex_mipfilter(unsigned filter)
1525 {
1526 switch (filter) {
1527 case PIPE_TEX_MIPFILTER_NEAREST:
1528 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1529 case PIPE_TEX_MIPFILTER_LINEAR:
1530 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1531 default:
1532 case PIPE_TEX_MIPFILTER_NONE:
1533 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1534 }
1535 }
1536
1537 static unsigned si_tex_compare(unsigned compare)
1538 {
1539 switch (compare) {
1540 default:
1541 case PIPE_FUNC_NEVER:
1542 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1543 case PIPE_FUNC_LESS:
1544 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1545 case PIPE_FUNC_EQUAL:
1546 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1547 case PIPE_FUNC_LEQUAL:
1548 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1549 case PIPE_FUNC_GREATER:
1550 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1551 case PIPE_FUNC_NOTEQUAL:
1552 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1553 case PIPE_FUNC_GEQUAL:
1554 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1555 case PIPE_FUNC_ALWAYS:
1556 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1557 }
1558 }
1559
1560 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1561 {
1562 switch (dim) {
1563 default:
1564 case PIPE_TEXTURE_1D:
1565 return V_008F1C_SQ_RSRC_IMG_1D;
1566 case PIPE_TEXTURE_1D_ARRAY:
1567 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1568 case PIPE_TEXTURE_2D:
1569 case PIPE_TEXTURE_RECT:
1570 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1571 V_008F1C_SQ_RSRC_IMG_2D;
1572 case PIPE_TEXTURE_2D_ARRAY:
1573 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1574 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1575 case PIPE_TEXTURE_3D:
1576 return V_008F1C_SQ_RSRC_IMG_3D;
1577 case PIPE_TEXTURE_CUBE:
1578 return V_008F1C_SQ_RSRC_IMG_CUBE;
1579 }
1580 }
1581
1582 /*
1583 * Format support testing
1584 */
1585
1586 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1587 {
1588 return si_translate_texformat(screen, format, util_format_description(format),
1589 util_format_get_first_non_void_channel(format)) != ~0U;
1590 }
1591
1592 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1593 enum pipe_format format,
1594 const struct util_format_description *desc,
1595 int first_non_void)
1596 {
1597 unsigned type = desc->channel[first_non_void].type;
1598 int i;
1599
1600 if (type == UTIL_FORMAT_TYPE_FIXED)
1601 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1602
1603 /* See whether the components are of the same size. */
1604 for (i = 0; i < desc->nr_channels; i++) {
1605 if (desc->channel[first_non_void].size != desc->channel[i].size)
1606 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1607 }
1608
1609 switch (desc->channel[first_non_void].size) {
1610 case 8:
1611 switch (desc->nr_channels) {
1612 case 1:
1613 return V_008F0C_BUF_DATA_FORMAT_8;
1614 case 2:
1615 return V_008F0C_BUF_DATA_FORMAT_8_8;
1616 case 3:
1617 case 4:
1618 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1619 }
1620 break;
1621 case 16:
1622 switch (desc->nr_channels) {
1623 case 1:
1624 return V_008F0C_BUF_DATA_FORMAT_16;
1625 case 2:
1626 return V_008F0C_BUF_DATA_FORMAT_16_16;
1627 case 3:
1628 case 4:
1629 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1630 }
1631 break;
1632 case 32:
1633 if (type != UTIL_FORMAT_TYPE_FLOAT)
1634 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1635
1636 switch (desc->nr_channels) {
1637 case 1:
1638 return V_008F0C_BUF_DATA_FORMAT_32;
1639 case 2:
1640 return V_008F0C_BUF_DATA_FORMAT_32_32;
1641 case 3:
1642 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1643 case 4:
1644 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1645 }
1646 break;
1647 }
1648
1649 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1650 }
1651
1652 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1653 {
1654 const struct util_format_description *desc;
1655 int first_non_void;
1656 unsigned data_format;
1657
1658 desc = util_format_description(format);
1659 first_non_void = util_format_get_first_non_void_channel(format);
1660 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1661 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1662 }
1663
1664 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1665 {
1666 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1667 si_translate_colorswap(format) != ~0U;
1668 }
1669
1670 static bool si_is_zs_format_supported(enum pipe_format format)
1671 {
1672 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1673 }
1674
1675 boolean si_is_format_supported(struct pipe_screen *screen,
1676 enum pipe_format format,
1677 enum pipe_texture_target target,
1678 unsigned sample_count,
1679 unsigned usage)
1680 {
1681 struct r600_screen *rscreen = (struct r600_screen *)screen;
1682 unsigned retval = 0;
1683
1684 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1685 R600_ERR("r600: unsupported texture type %d\n", target);
1686 return FALSE;
1687 }
1688
1689 if (!util_format_is_supported(format, usage))
1690 return FALSE;
1691
1692 if (sample_count > 1) {
1693 if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI)
1694 return FALSE;
1695
1696 switch (sample_count) {
1697 case 2:
1698 case 4:
1699 case 8:
1700 break;
1701 default:
1702 return FALSE;
1703 }
1704 }
1705
1706 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1707 si_is_sampler_format_supported(screen, format)) {
1708 retval |= PIPE_BIND_SAMPLER_VIEW;
1709 }
1710
1711 if ((usage & (PIPE_BIND_RENDER_TARGET |
1712 PIPE_BIND_DISPLAY_TARGET |
1713 PIPE_BIND_SCANOUT |
1714 PIPE_BIND_SHARED)) &&
1715 si_is_colorbuffer_format_supported(format)) {
1716 retval |= usage &
1717 (PIPE_BIND_RENDER_TARGET |
1718 PIPE_BIND_DISPLAY_TARGET |
1719 PIPE_BIND_SCANOUT |
1720 PIPE_BIND_SHARED);
1721 }
1722
1723 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1724 si_is_zs_format_supported(format)) {
1725 retval |= PIPE_BIND_DEPTH_STENCIL;
1726 }
1727
1728 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1729 si_is_vertex_format_supported(screen, format)) {
1730 retval |= PIPE_BIND_VERTEX_BUFFER;
1731 }
1732
1733 if (usage & PIPE_BIND_TRANSFER_READ)
1734 retval |= PIPE_BIND_TRANSFER_READ;
1735 if (usage & PIPE_BIND_TRANSFER_WRITE)
1736 retval |= PIPE_BIND_TRANSFER_WRITE;
1737
1738 return retval == usage;
1739 }
1740
1741 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1742 {
1743 unsigned tile_mode_index = 0;
1744
1745 if (stencil) {
1746 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1747 } else {
1748 tile_mode_index = rtex->surface.tiling_index[level];
1749 }
1750 return tile_mode_index;
1751 }
1752
1753 /*
1754 * framebuffer handling
1755 */
1756
1757 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1758 const struct pipe_framebuffer_state *state, int cb)
1759 {
1760 struct r600_texture *rtex;
1761 struct r600_surface *surf;
1762 unsigned level = state->cbufs[cb]->u.tex.level;
1763 unsigned pitch, slice;
1764 unsigned color_info, color_attrib;
1765 unsigned tile_mode_index;
1766 unsigned format, swap, ntype, endian;
1767 uint64_t offset;
1768 const struct util_format_description *desc;
1769 int i;
1770 unsigned blend_clamp = 0, blend_bypass = 0;
1771 unsigned max_comp_size;
1772
1773 surf = (struct r600_surface *)state->cbufs[cb];
1774 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1775
1776 offset = rtex->surface.level[level].offset;
1777 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1778 offset += rtex->surface.level[level].slice_size *
1779 state->cbufs[cb]->u.tex.first_layer;
1780 }
1781 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1782 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1783 if (slice) {
1784 slice = slice - 1;
1785 }
1786
1787 tile_mode_index = si_tile_mode_index(rtex, level, false);
1788
1789 desc = util_format_description(surf->base.format);
1790 for (i = 0; i < 4; i++) {
1791 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1792 break;
1793 }
1794 }
1795 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1796 ntype = V_028C70_NUMBER_FLOAT;
1797 } else {
1798 ntype = V_028C70_NUMBER_UNORM;
1799 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1800 ntype = V_028C70_NUMBER_SRGB;
1801 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1802 if (desc->channel[i].pure_integer) {
1803 ntype = V_028C70_NUMBER_SINT;
1804 } else {
1805 assert(desc->channel[i].normalized);
1806 ntype = V_028C70_NUMBER_SNORM;
1807 }
1808 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1809 if (desc->channel[i].pure_integer) {
1810 ntype = V_028C70_NUMBER_UINT;
1811 } else {
1812 assert(desc->channel[i].normalized);
1813 ntype = V_028C70_NUMBER_UNORM;
1814 }
1815 }
1816 }
1817
1818 format = si_translate_colorformat(surf->base.format);
1819 if (format == V_028C70_COLOR_INVALID) {
1820 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1821 }
1822 assert(format != V_028C70_COLOR_INVALID);
1823 swap = si_translate_colorswap(surf->base.format);
1824 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1825 endian = V_028C70_ENDIAN_NONE;
1826 } else {
1827 endian = si_colorformat_endian_swap(format);
1828 }
1829
1830 /* blend clamp should be set for all NORM/SRGB types */
1831 if (ntype == V_028C70_NUMBER_UNORM ||
1832 ntype == V_028C70_NUMBER_SNORM ||
1833 ntype == V_028C70_NUMBER_SRGB)
1834 blend_clamp = 1;
1835
1836 /* set blend bypass according to docs if SINT/UINT or
1837 8/24 COLOR variants */
1838 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1839 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1840 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1841 blend_clamp = 0;
1842 blend_bypass = 1;
1843 }
1844
1845 color_info = S_028C70_FORMAT(format) |
1846 S_028C70_COMP_SWAP(swap) |
1847 S_028C70_BLEND_CLAMP(blend_clamp) |
1848 S_028C70_BLEND_BYPASS(blend_bypass) |
1849 S_028C70_NUMBER_TYPE(ntype) |
1850 S_028C70_ENDIAN(endian);
1851
1852 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1853 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1854
1855 if (rtex->resource.b.b.nr_samples > 1) {
1856 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1857
1858 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1859 S_028C74_NUM_FRAGMENTS(log_samples);
1860
1861 if (rtex->fmask.size) {
1862 color_info |= S_028C70_COMPRESSION(1);
1863 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1864
1865 /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */
1866 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) |
1867 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1868 }
1869 }
1870
1871 if (rtex->cmask.size) {
1872 color_info |= S_028C70_FAST_CLEAR(1);
1873 }
1874
1875 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1876 offset >>= 8;
1877
1878 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1879 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1880 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1881 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1882 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1883
1884 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1885 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1886 } else {
1887 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1888 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1889 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1890 }
1891 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1892 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1893
1894 if (rtex->cmask.size) {
1895 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1896 offset + (rtex->cmask.offset >> 8));
1897 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1898 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1899 }
1900 if (rtex->fmask.size) {
1901 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1902 offset + (rtex->fmask.offset >> 8));
1903 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1904 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1905 }
1906
1907 /* set CB_COLOR1_INFO for possible dual-src blending */
1908 if (state->nr_cbufs == 1) {
1909 assert(cb == 0);
1910 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1911 }
1912
1913 /* Determine pixel shader export format */
1914 max_comp_size = si_colorformat_max_comp_size(format);
1915 if (ntype == V_028C70_NUMBER_SRGB ||
1916 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1917 max_comp_size <= 10) ||
1918 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1919 rctx->export_16bpc |= 1 << cb;
1920 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1921 if (state->nr_cbufs == 1)
1922 rctx->export_16bpc |= 1 << 1;
1923 }
1924 }
1925
1926 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1927 const struct pipe_framebuffer_state *state)
1928 {
1929 struct r600_screen *rscreen = rctx->screen;
1930 struct r600_texture *rtex;
1931 struct r600_surface *surf;
1932 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1933 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1934 uint32_t z_info, s_info, db_depth_info;
1935 uint64_t z_offs, s_offs;
1936
1937 if (state->zsbuf == NULL) {
1938 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1939 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1940 return;
1941 }
1942
1943 surf = (struct r600_surface *)state->zsbuf;
1944 level = surf->base.u.tex.level;
1945 rtex = (struct r600_texture*)surf->base.texture;
1946
1947 format = si_translate_dbformat(rtex->resource.b.b.format);
1948
1949 if (format == V_028040_Z_INVALID) {
1950 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1951 }
1952 assert(format != V_028040_Z_INVALID);
1953
1954 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1955 z_offs += rtex->surface.level[level].offset;
1956 s_offs += rtex->surface.stencil_level[level].offset;
1957
1958 z_offs >>= 8;
1959 s_offs >>= 8;
1960
1961 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1962 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1963 if (slice) {
1964 slice = slice - 1;
1965 }
1966
1967 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1968
1969 z_info = S_028040_FORMAT(format);
1970 if (rtex->resource.b.b.nr_samples > 1) {
1971 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1972 }
1973
1974 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1975 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1976 else
1977 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1978
1979 if (rctx->b.chip_class >= CIK) {
1980 switch (rtex->surface.level[level].mode) {
1981 case RADEON_SURF_MODE_2D:
1982 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1983 break;
1984 case RADEON_SURF_MODE_1D:
1985 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1986 case RADEON_SURF_MODE_LINEAR:
1987 default:
1988 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1989 break;
1990 }
1991 tile_split = rtex->surface.tile_split;
1992 stile_split = rtex->surface.stencil_tile_split;
1993 macro_aspect = rtex->surface.mtilea;
1994 bankw = rtex->surface.bankw;
1995 bankh = rtex->surface.bankh;
1996 tile_split = cik_tile_split(tile_split);
1997 stile_split = cik_tile_split(stile_split);
1998 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1999 bankw = cik_bank_wh(bankw);
2000 bankh = cik_bank_wh(bankh);
2001 nbanks = cik_num_banks(rscreen->tiling_info.num_banks);
2002 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
2003 rscreen->b.info.r600_num_backends);
2004
2005 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2006 S_02803C_PIPE_CONFIG(pipe_config) |
2007 S_02803C_BANK_WIDTH(bankw) |
2008 S_02803C_BANK_HEIGHT(bankh) |
2009 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2010 S_02803C_NUM_BANKS(nbanks);
2011 z_info |= S_028040_TILE_SPLIT(tile_split);
2012 s_info |= S_028044_TILE_SPLIT(stile_split);
2013 } else {
2014 tile_mode_index = si_tile_mode_index(rtex, level, false);
2015 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2016 tile_mode_index = si_tile_mode_index(rtex, level, true);
2017 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2018 }
2019
2020 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
2021 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
2022 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
2023
2024 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
2025 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
2026 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
2027
2028 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
2029 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
2030 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
2031 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
2032 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
2033
2034 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
2035 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
2036 }
2037
2038 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
2039 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
2040 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
2041 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
2042 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
2043
2044 /* 2xMSAA
2045 * There are two locations (-4, 4), (4, -4). */
2046 static uint32_t sample_locs_2x[] = {
2047 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2048 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2049 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2050 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2051 };
2052 static unsigned max_dist_2x = 4;
2053 /* 4xMSAA
2054 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
2055 static uint32_t sample_locs_4x[] = {
2056 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2057 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2058 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2059 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2060 };
2061 static unsigned max_dist_4x = 6;
2062 /* Cayman/SI 8xMSAA */
2063 static uint32_t cm_sample_locs_8x[] = {
2064 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2065 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2066 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2067 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2068 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2069 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2070 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2071 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2072 };
2073 static unsigned cm_max_dist_8x = 8;
2074 /* Cayman/SI 16xMSAA */
2075 static uint32_t cm_sample_locs_16x[] = {
2076 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2077 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2078 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2079 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2080 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2081 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2082 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2083 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2084 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2085 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2086 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2087 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2088 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2089 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2090 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2091 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2092 };
2093 static unsigned cm_max_dist_16x = 8;
2094
2095 static void si_get_sample_position(struct pipe_context *ctx,
2096 unsigned sample_count,
2097 unsigned sample_index,
2098 float *out_value)
2099 {
2100 int offset, index;
2101 struct {
2102 int idx:4;
2103 } val;
2104 switch (sample_count) {
2105 case 1:
2106 default:
2107 out_value[0] = out_value[1] = 0.5;
2108 break;
2109 case 2:
2110 offset = 4 * (sample_index * 2);
2111 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
2112 out_value[0] = (float)(val.idx + 8) / 16.0f;
2113 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
2114 out_value[1] = (float)(val.idx + 8) / 16.0f;
2115 break;
2116 case 4:
2117 offset = 4 * (sample_index * 2);
2118 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
2119 out_value[0] = (float)(val.idx + 8) / 16.0f;
2120 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
2121 out_value[1] = (float)(val.idx + 8) / 16.0f;
2122 break;
2123 case 8:
2124 offset = 4 * (sample_index % 4 * 2);
2125 index = (sample_index / 4) * 4;
2126 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
2127 out_value[0] = (float)(val.idx + 8) / 16.0f;
2128 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2129 out_value[1] = (float)(val.idx + 8) / 16.0f;
2130 break;
2131 case 16:
2132 offset = 4 * (sample_index % 4 * 2);
2133 index = (sample_index / 4) * 4;
2134 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2135 out_value[0] = (float)(val.idx + 8) / 16.0f;
2136 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2137 out_value[1] = (float)(val.idx + 8) / 16.0f;
2138 break;
2139 }
2140 }
2141
2142 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
2143 {
2144 unsigned max_dist = 0;
2145
2146 switch (nr_samples) {
2147 default:
2148 nr_samples = 0;
2149 break;
2150 case 2:
2151 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2152 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2153 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2154 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2155 max_dist = max_dist_2x;
2156 break;
2157 case 4:
2158 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2159 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2160 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2161 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2162 max_dist = max_dist_4x;
2163 break;
2164 case 8:
2165 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2166 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2167 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2168 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2169 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2170 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2171 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2172 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2173 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2174 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2175 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2176 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2177 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2178 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2179 max_dist = cm_max_dist_8x;
2180 break;
2181 case 16:
2182 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2183 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2184 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2185 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2186 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2187 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2188 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2189 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2190 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2191 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2192 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2193 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2194 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2195 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2196 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2197 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2198 max_dist = cm_max_dist_16x;
2199 break;
2200 }
2201
2202 if (nr_samples > 1) {
2203 unsigned log_samples = util_logbase2(nr_samples);
2204
2205 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2206 S_028BDC_LAST_PIXEL(1) |
2207 S_028BDC_EXPAND_LINE_WIDTH(1));
2208 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2209 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2210 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2211 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2212
2213 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2214 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2215 S_028804_PS_ITER_SAMPLES(log_samples) |
2216 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2217 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2218 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2219 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2220 } else {
2221 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2222 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2223
2224 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2225 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2226 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2227 }
2228 }
2229
2230 static void si_set_framebuffer_state(struct pipe_context *ctx,
2231 const struct pipe_framebuffer_state *state)
2232 {
2233 struct r600_context *rctx = (struct r600_context *)ctx;
2234 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2235 uint32_t tl, br;
2236 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2237
2238 if (pm4 == NULL)
2239 return;
2240
2241 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
2242 rctx->flush_and_inv_cb_meta = true;
2243
2244 if (state->zsbuf)
2245 si_pm4_inval_zsbuf_cache(pm4);
2246
2247 util_copy_framebuffer_state(&rctx->framebuffer, state);
2248
2249 /* build states */
2250 rctx->export_16bpc = 0;
2251 rctx->fb_compressed_cb_mask = 0;
2252 for (i = 0; i < state->nr_cbufs; i++) {
2253 struct r600_texture *rtex =
2254 (struct r600_texture*)state->cbufs[i]->texture;
2255
2256 si_cb(rctx, pm4, state, i);
2257
2258 if (rtex->fmask.size || rtex->cmask.size) {
2259 rctx->fb_compressed_cb_mask |= 1 << i;
2260 }
2261 }
2262 for (; i < 8; i++) {
2263 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2264 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2265 }
2266
2267 assert(!(rctx->export_16bpc & ~0xff));
2268 si_db(rctx, pm4, state);
2269
2270 tl_x = 0;
2271 tl_y = 0;
2272 br_x = state->width;
2273 br_y = state->height;
2274
2275 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2276 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2277
2278 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2279 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2280 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2281 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2282 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2283 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2284 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2285 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2286 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2287 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2288
2289 if (state->nr_cbufs)
2290 nr_samples = state->cbufs[0]->texture->nr_samples;
2291 else if (state->zsbuf)
2292 nr_samples = state->zsbuf->texture->nr_samples;
2293 else
2294 nr_samples = 0;
2295
2296 si_set_msaa_state(rctx, pm4, nr_samples);
2297 rctx->fb_log_samples = util_logbase2(nr_samples);
2298 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2299 util_format_is_pure_integer(state->cbufs[0]->format);
2300
2301 si_pm4_set_state(rctx, framebuffer, pm4);
2302 si_update_fb_rs_state(rctx);
2303 si_update_fb_blend_state(rctx);
2304 }
2305
2306 /*
2307 * shaders
2308 */
2309
2310 /* Compute the key for the hw shader variant */
2311 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2312 struct si_pipe_shader_selector *sel,
2313 union si_shader_key *key)
2314 {
2315 struct r600_context *rctx = (struct r600_context *)ctx;
2316 memset(key, 0, sizeof(*key));
2317
2318 if (sel->type == PIPE_SHADER_VERTEX) {
2319 unsigned i;
2320 if (!rctx->vertex_elements)
2321 return;
2322
2323 for (i = 0; i < rctx->vertex_elements->count; ++i)
2324 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2325
2326 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2327 key->vs.ucps_enabled |= 0x2;
2328 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2329 key->vs.ucps_enabled |= 0x1;
2330 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2331 if (sel->fs_write_all)
2332 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2333 key->ps.export_16bpc = rctx->export_16bpc;
2334
2335 if (rctx->queued.named.rasterizer) {
2336 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2337 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2338
2339 if (rctx->queued.named.blend) {
2340 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2341 rctx->queued.named.rasterizer->multisample_enable &&
2342 !rctx->fb_cb0_is_integer;
2343 }
2344 }
2345 if (rctx->queued.named.dsa) {
2346 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2347 key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
2348 } else {
2349 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2350 }
2351 }
2352 }
2353
2354 /* Select the hw shader variant depending on the current state.
2355 * (*dirty) is set to 1 if current variant was changed */
2356 int si_shader_select(struct pipe_context *ctx,
2357 struct si_pipe_shader_selector *sel,
2358 unsigned *dirty)
2359 {
2360 union si_shader_key key;
2361 struct si_pipe_shader * shader = NULL;
2362 int r;
2363
2364 si_shader_selector_key(ctx, sel, &key);
2365
2366 /* Check if we don't need to change anything.
2367 * This path is also used for most shaders that don't need multiple
2368 * variants, it will cost just a computation of the key and this
2369 * test. */
2370 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2371 return 0;
2372 }
2373
2374 /* lookup if we have other variants in the list */
2375 if (sel->num_shaders > 1) {
2376 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2377
2378 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2379 p = c;
2380 c = c->next_variant;
2381 }
2382
2383 if (c) {
2384 p->next_variant = c->next_variant;
2385 shader = c;
2386 }
2387 }
2388
2389 if (unlikely(!shader)) {
2390 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2391 shader->selector = sel;
2392 shader->key = key;
2393
2394 r = si_pipe_shader_create(ctx, shader);
2395 if (unlikely(r)) {
2396 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2397 sel->type, r);
2398 sel->current = NULL;
2399 FREE(shader);
2400 return r;
2401 }
2402
2403 /* We don't know the value of fs_write_all property until we built
2404 * at least one variant, so we may need to recompute the key (include
2405 * rctx->framebuffer.nr_cbufs) after building first variant. */
2406 if (sel->type == PIPE_SHADER_FRAGMENT &&
2407 sel->num_shaders == 0 &&
2408 shader->shader.fs_write_all) {
2409 sel->fs_write_all = 1;
2410 si_shader_selector_key(ctx, sel, &shader->key);
2411 }
2412
2413 sel->num_shaders++;
2414 }
2415
2416 if (dirty)
2417 *dirty = 1;
2418
2419 shader->next_variant = sel->current;
2420 sel->current = shader;
2421
2422 return 0;
2423 }
2424
2425 static void *si_create_shader_state(struct pipe_context *ctx,
2426 const struct pipe_shader_state *state,
2427 unsigned pipe_shader_type)
2428 {
2429 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2430 int r;
2431
2432 sel->type = pipe_shader_type;
2433 sel->tokens = tgsi_dup_tokens(state->tokens);
2434 sel->so = state->stream_output;
2435
2436 r = si_shader_select(ctx, sel, NULL);
2437 if (r) {
2438 free(sel);
2439 return NULL;
2440 }
2441
2442 return sel;
2443 }
2444
2445 static void *si_create_fs_state(struct pipe_context *ctx,
2446 const struct pipe_shader_state *state)
2447 {
2448 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2449 }
2450
2451 static void *si_create_vs_state(struct pipe_context *ctx,
2452 const struct pipe_shader_state *state)
2453 {
2454 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2455 }
2456
2457 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2458 {
2459 struct r600_context *rctx = (struct r600_context *)ctx;
2460 struct si_pipe_shader_selector *sel = state;
2461
2462 if (rctx->vs_shader == sel)
2463 return;
2464
2465 rctx->vs_shader = sel;
2466
2467 if (sel && sel->current)
2468 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2469 else
2470 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2471 }
2472
2473 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2474 {
2475 struct r600_context *rctx = (struct r600_context *)ctx;
2476 struct si_pipe_shader_selector *sel = state;
2477
2478 if (rctx->ps_shader == sel)
2479 return;
2480
2481 rctx->ps_shader = sel;
2482
2483 if (sel && sel->current)
2484 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2485 else
2486 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2487 }
2488
2489 static void si_delete_shader_selector(struct pipe_context *ctx,
2490 struct si_pipe_shader_selector *sel)
2491 {
2492 struct r600_context *rctx = (struct r600_context *)ctx;
2493 struct si_pipe_shader *p = sel->current, *c;
2494
2495 while (p) {
2496 c = p->next_variant;
2497 si_pm4_delete_state(rctx, vs, p->pm4);
2498 si_pipe_shader_destroy(ctx, p);
2499 free(p);
2500 p = c;
2501 }
2502
2503 free(sel->tokens);
2504 free(sel);
2505 }
2506
2507 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2508 {
2509 struct r600_context *rctx = (struct r600_context *)ctx;
2510 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2511
2512 if (rctx->vs_shader == sel) {
2513 rctx->vs_shader = NULL;
2514 }
2515
2516 si_delete_shader_selector(ctx, sel);
2517 }
2518
2519 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2520 {
2521 struct r600_context *rctx = (struct r600_context *)ctx;
2522 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2523
2524 if (rctx->ps_shader == sel) {
2525 rctx->ps_shader = NULL;
2526 }
2527
2528 si_delete_shader_selector(ctx, sel);
2529 }
2530
2531 /*
2532 * Samplers
2533 */
2534
2535 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2536 struct pipe_resource *texture,
2537 const struct pipe_sampler_view *state)
2538 {
2539 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2540 struct r600_texture *tmp = (struct r600_texture*)texture;
2541 const struct util_format_description *desc;
2542 unsigned format, num_format;
2543 uint32_t pitch = 0;
2544 unsigned char state_swizzle[4], swizzle[4];
2545 unsigned height, depth, width;
2546 enum pipe_format pipe_format = state->format;
2547 struct radeon_surface_level *surflevel;
2548 int first_non_void;
2549 uint64_t va;
2550
2551 if (view == NULL)
2552 return NULL;
2553
2554 /* initialize base object */
2555 view->base = *state;
2556 view->base.texture = NULL;
2557 pipe_reference(NULL, &texture->reference);
2558 view->base.texture = texture;
2559 view->base.reference.count = 1;
2560 view->base.context = ctx;
2561
2562 state_swizzle[0] = state->swizzle_r;
2563 state_swizzle[1] = state->swizzle_g;
2564 state_swizzle[2] = state->swizzle_b;
2565 state_swizzle[3] = state->swizzle_a;
2566
2567 surflevel = tmp->surface.level;
2568
2569 /* Texturing with separate depth and stencil. */
2570 if (tmp->is_depth && !tmp->is_flushing_texture) {
2571 switch (pipe_format) {
2572 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2573 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2574 break;
2575 case PIPE_FORMAT_X8Z24_UNORM:
2576 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2577 /* Z24 is always stored like this. */
2578 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2579 break;
2580 case PIPE_FORMAT_X24S8_UINT:
2581 case PIPE_FORMAT_S8X24_UINT:
2582 case PIPE_FORMAT_X32_S8X24_UINT:
2583 pipe_format = PIPE_FORMAT_S8_UINT;
2584 surflevel = tmp->surface.stencil_level;
2585 break;
2586 default:;
2587 }
2588 }
2589
2590 desc = util_format_description(pipe_format);
2591
2592 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2593 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2594 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2595
2596 switch (pipe_format) {
2597 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2598 case PIPE_FORMAT_X24S8_UINT:
2599 case PIPE_FORMAT_X32_S8X24_UINT:
2600 case PIPE_FORMAT_X8Z24_UNORM:
2601 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2602 break;
2603 default:
2604 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2605 }
2606 } else {
2607 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2608 }
2609
2610 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2611
2612 switch (pipe_format) {
2613 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2614 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2615 break;
2616 default:
2617 if (first_non_void < 0) {
2618 if (util_format_is_compressed(pipe_format)) {
2619 switch (pipe_format) {
2620 case PIPE_FORMAT_DXT1_SRGB:
2621 case PIPE_FORMAT_DXT1_SRGBA:
2622 case PIPE_FORMAT_DXT3_SRGBA:
2623 case PIPE_FORMAT_DXT5_SRGBA:
2624 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2625 break;
2626 case PIPE_FORMAT_RGTC1_SNORM:
2627 case PIPE_FORMAT_LATC1_SNORM:
2628 case PIPE_FORMAT_RGTC2_SNORM:
2629 case PIPE_FORMAT_LATC2_SNORM:
2630 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2631 break;
2632 default:
2633 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2634 break;
2635 }
2636 } else {
2637 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2638 }
2639 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2640 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2641 } else {
2642 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2643
2644 switch (desc->channel[first_non_void].type) {
2645 case UTIL_FORMAT_TYPE_FLOAT:
2646 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2647 break;
2648 case UTIL_FORMAT_TYPE_SIGNED:
2649 if (desc->channel[first_non_void].normalized)
2650 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2651 else if (desc->channel[first_non_void].pure_integer)
2652 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2653 else
2654 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2655 break;
2656 case UTIL_FORMAT_TYPE_UNSIGNED:
2657 if (desc->channel[first_non_void].normalized)
2658 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2659 else if (desc->channel[first_non_void].pure_integer)
2660 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2661 else
2662 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2663 }
2664 }
2665 }
2666
2667 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2668 if (format == ~0) {
2669 format = 0;
2670 }
2671
2672 view->resource = &tmp->resource;
2673
2674 /* not supported any more */
2675 //endian = si_colorformat_endian_swap(format);
2676
2677 width = surflevel[0].npix_x;
2678 height = surflevel[0].npix_y;
2679 depth = surflevel[0].npix_z;
2680 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2681
2682 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2683 height = 1;
2684 depth = texture->array_size;
2685 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2686 depth = texture->array_size;
2687 }
2688
2689 va = r600_resource_va(ctx->screen, texture);
2690 va += surflevel[0].offset;
2691 view->state[0] = va >> 8;
2692 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2693 S_008F14_DATA_FORMAT(format) |
2694 S_008F14_NUM_FORMAT(num_format));
2695 view->state[2] = (S_008F18_WIDTH(width - 1) |
2696 S_008F18_HEIGHT(height - 1));
2697 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2698 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2699 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2700 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2701 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2702 0 : state->u.tex.first_level) |
2703 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2704 util_logbase2(texture->nr_samples) :
2705 state->u.tex.last_level) |
2706 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2707 S_008F1C_POW2_PAD(texture->last_level > 0) |
2708 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2709 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2710 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2711 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2712 view->state[6] = 0;
2713 view->state[7] = 0;
2714
2715 /* Initialize the sampler view for FMASK. */
2716 if (tmp->fmask.size) {
2717 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2718 uint32_t fmask_format;
2719
2720 switch (texture->nr_samples) {
2721 case 2:
2722 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2723 break;
2724 case 4:
2725 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2726 break;
2727 case 8:
2728 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2729 break;
2730 default:
2731 assert(0);
2732 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2733 }
2734
2735 view->fmask_state[0] = va >> 8;
2736 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2737 S_008F14_DATA_FORMAT(fmask_format) |
2738 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2739 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2740 S_008F18_HEIGHT(height - 1);
2741 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2742 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2743 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2744 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2745 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2746 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2747 view->fmask_state[4] = S_008F20_PITCH(tmp->fmask.pitch - 1);
2748 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2749 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2750 view->fmask_state[6] = 0;
2751 view->fmask_state[7] = 0;
2752 }
2753
2754 return &view->base;
2755 }
2756
2757 static void si_sampler_view_destroy(struct pipe_context *ctx,
2758 struct pipe_sampler_view *state)
2759 {
2760 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2761
2762 pipe_resource_reference(&state->texture, NULL);
2763 FREE(resource);
2764 }
2765
2766 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2767 {
2768 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2769 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2770 (linear_filter &&
2771 (wrap == PIPE_TEX_WRAP_CLAMP ||
2772 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2773 }
2774
2775 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2776 {
2777 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2778 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2779
2780 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2781 state->border_color.ui[2] || state->border_color.ui[3]) &&
2782 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2783 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2784 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2785 }
2786
2787 static void *si_create_sampler_state(struct pipe_context *ctx,
2788 const struct pipe_sampler_state *state)
2789 {
2790 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2791 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2792 unsigned border_color_type;
2793
2794 if (rstate == NULL) {
2795 return NULL;
2796 }
2797
2798 if (sampler_state_needs_border_color(state))
2799 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2800 else
2801 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2802
2803 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2804 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2805 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2806 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2807 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2808 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2809 aniso_flag_offset << 16 | /* XXX */
2810 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2811 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2812 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2813 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2814 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2815 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2816 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2817 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2818
2819 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2820 memcpy(rstate->border_color, state->border_color.ui,
2821 sizeof(rstate->border_color));
2822 }
2823
2824 return rstate;
2825 }
2826
2827 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2828 * the si_set_sampler_view calls. LTO might help too. */
2829 static struct si_pm4_state *si_set_sampler_views(struct r600_context *rctx,
2830 unsigned shader, unsigned count,
2831 struct pipe_sampler_view **views)
2832 {
2833 struct r600_textures_info *samplers = &rctx->samplers[shader];
2834 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2835 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2836 int i;
2837
2838 si_pm4_inval_texture_cache(pm4);
2839
2840 for (i = 0; i < count; i++) {
2841 if (views[i]) {
2842 struct r600_texture *rtex =
2843 (struct r600_texture*)views[i]->texture;
2844
2845 if (rtex->is_depth && !rtex->is_flushing_texture) {
2846 samplers->depth_texture_mask |= 1 << i;
2847 } else {
2848 samplers->depth_texture_mask &= ~(1 << i);
2849 }
2850 if (rtex->cmask.size || rtex->fmask.size) {
2851 samplers->compressed_colortex_mask |= 1 << i;
2852 } else {
2853 samplers->compressed_colortex_mask &= ~(1 << i);
2854 }
2855
2856 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2857
2858 if (rtex->fmask.size) {
2859 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2860 views[i], rviews[i]->fmask_state);
2861 } else {
2862 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2863 NULL, NULL);
2864 }
2865 } else {
2866 samplers->depth_texture_mask &= ~(1 << i);
2867 samplers->compressed_colortex_mask &= ~(1 << i);
2868 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2869 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2870 NULL, NULL);
2871 }
2872 }
2873 for (; i < samplers->n_views; i++) {
2874 samplers->depth_texture_mask &= ~(1 << i);
2875 samplers->compressed_colortex_mask &= ~(1 << i);
2876 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2877 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2878 NULL, NULL);
2879 }
2880
2881 samplers->n_views = count;
2882 return pm4;
2883 }
2884
2885 static void si_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
2886 struct pipe_sampler_view **views)
2887 {
2888 struct r600_context *rctx = (struct r600_context *)ctx;
2889 struct si_pm4_state *pm4;
2890
2891 pm4 = si_set_sampler_views(rctx, PIPE_SHADER_VERTEX, count, views);
2892 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2893 }
2894
2895 static void si_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
2896 struct pipe_sampler_view **views)
2897 {
2898 struct r600_context *rctx = (struct r600_context *)ctx;
2899 struct si_pm4_state *pm4;
2900
2901 pm4 = si_set_sampler_views(rctx, PIPE_SHADER_FRAGMENT, count, views);
2902 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2903 }
2904
2905 static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx, unsigned count,
2906 void **states,
2907 struct r600_textures_info *samplers,
2908 unsigned user_data_reg)
2909 {
2910 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2911 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2912 uint32_t *border_color_table = NULL;
2913 int i, j;
2914
2915 if (!count)
2916 goto out;
2917
2918 si_pm4_inval_texture_cache(pm4);
2919
2920 si_pm4_sh_data_begin(pm4);
2921 for (i = 0; i < count; i++) {
2922 if (rstates[i] &&
2923 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2924 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2925 if (!rctx->border_color_table ||
2926 ((rctx->border_color_offset + count - i) &
2927 C_008F3C_BORDER_COLOR_PTR)) {
2928 r600_resource_reference(&rctx->border_color_table, NULL);
2929 rctx->border_color_offset = 0;
2930
2931 rctx->border_color_table =
2932 r600_resource_create_custom(&rctx->screen->b.b,
2933 PIPE_USAGE_STAGING,
2934 4096 * 4 * 4);
2935 }
2936
2937 if (!border_color_table) {
2938 border_color_table =
2939 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2940 rctx->b.rings.gfx.cs,
2941 PIPE_TRANSFER_WRITE |
2942 PIPE_TRANSFER_UNSYNCHRONIZED);
2943 }
2944
2945 for (j = 0; j < 4; j++) {
2946 border_color_table[4 * rctx->border_color_offset + j] =
2947 util_le32_to_cpu(rstates[i]->border_color[j]);
2948 }
2949
2950 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2951 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2952 }
2953
2954 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2955 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2956 }
2957 }
2958 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2959
2960 if (border_color_table) {
2961 uint64_t va_offset =
2962 r600_resource_va(&rctx->screen->b.b,
2963 (void*)rctx->border_color_table);
2964
2965 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2966 if (rctx->b.chip_class >= CIK)
2967 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2968 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2969 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2970 }
2971
2972 memcpy(samplers->samplers, states, sizeof(void*) * count);
2973
2974 out:
2975 samplers->n_samplers = count;
2976 return pm4;
2977 }
2978
2979 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2980 {
2981 struct r600_context *rctx = (struct r600_context *)ctx;
2982 struct si_pm4_state *pm4;
2983
2984 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2985 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2986 si_pm4_set_state(rctx, vs_sampler, pm4);
2987 }
2988
2989 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2990 {
2991 struct r600_context *rctx = (struct r600_context *)ctx;
2992 struct si_pm4_state *pm4;
2993
2994 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2995 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2996 si_pm4_set_state(rctx, ps_sampler, pm4);
2997 }
2998
2999 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3000 {
3001 struct r600_context *rctx = (struct r600_context *)ctx;
3002 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3003 uint16_t mask = sample_mask;
3004
3005 if (pm4 == NULL)
3006 return;
3007
3008 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
3009 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
3010
3011 si_pm4_set_state(rctx, sample_mask, pm4);
3012 }
3013
3014 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3015 {
3016 free(state);
3017 }
3018
3019 /*
3020 * Vertex elements & buffers
3021 */
3022
3023 static void *si_create_vertex_elements(struct pipe_context *ctx,
3024 unsigned count,
3025 const struct pipe_vertex_element *elements)
3026 {
3027 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3028 int i;
3029
3030 assert(count < PIPE_MAX_ATTRIBS);
3031 if (!v)
3032 return NULL;
3033
3034 v->count = count;
3035 for (i = 0; i < count; ++i) {
3036 const struct util_format_description *desc;
3037 unsigned data_format, num_format;
3038 int first_non_void;
3039
3040 desc = util_format_description(elements[i].src_format);
3041 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3042 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
3043 desc, first_non_void);
3044
3045 switch (desc->channel[first_non_void].type) {
3046 case UTIL_FORMAT_TYPE_FIXED:
3047 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
3048 break;
3049 case UTIL_FORMAT_TYPE_SIGNED:
3050 if (desc->channel[first_non_void].normalized)
3051 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
3052 else if (desc->channel[first_non_void].pure_integer)
3053 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
3054 else
3055 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
3056 break;
3057 case UTIL_FORMAT_TYPE_UNSIGNED:
3058 if (desc->channel[first_non_void].normalized)
3059 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
3060 else if (desc->channel[first_non_void].pure_integer)
3061 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
3062 else
3063 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
3064 break;
3065 case UTIL_FORMAT_TYPE_FLOAT:
3066 default:
3067 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3068 }
3069
3070 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3071 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3072 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3073 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3074 S_008F0C_NUM_FORMAT(num_format) |
3075 S_008F0C_DATA_FORMAT(data_format);
3076 }
3077 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3078
3079 return v;
3080 }
3081
3082 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3083 {
3084 struct r600_context *rctx = (struct r600_context *)ctx;
3085 struct si_vertex_element *v = (struct si_vertex_element*)state;
3086
3087 rctx->vertex_elements = v;
3088 }
3089
3090 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3091 {
3092 struct r600_context *rctx = (struct r600_context *)ctx;
3093
3094 if (rctx->vertex_elements == state)
3095 rctx->vertex_elements = NULL;
3096 FREE(state);
3097 }
3098
3099 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
3100 const struct pipe_vertex_buffer *buffers)
3101 {
3102 struct r600_context *rctx = (struct r600_context *)ctx;
3103
3104 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
3105 }
3106
3107 static void si_set_index_buffer(struct pipe_context *ctx,
3108 const struct pipe_index_buffer *ib)
3109 {
3110 struct r600_context *rctx = (struct r600_context *)ctx;
3111
3112 if (ib) {
3113 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
3114 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
3115 } else {
3116 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
3117 }
3118 }
3119
3120 /*
3121 * Misc
3122 */
3123 static void si_set_polygon_stipple(struct pipe_context *ctx,
3124 const struct pipe_poly_stipple *state)
3125 {
3126 }
3127
3128 static void si_texture_barrier(struct pipe_context *ctx)
3129 {
3130 struct r600_context *rctx = (struct r600_context *)ctx;
3131 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3132
3133 if (pm4 == NULL)
3134 return;
3135
3136 si_pm4_inval_texture_cache(pm4);
3137 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
3138 si_pm4_set_state(rctx, texture_barrier, pm4);
3139 }
3140
3141 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
3142 {
3143 struct pipe_blend_state blend;
3144
3145 memset(&blend, 0, sizeof(blend));
3146 blend.independent_blend_enable = true;
3147 blend.rt[0].colormask = 0xf;
3148 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
3149 }
3150
3151 void si_init_state_functions(struct r600_context *rctx)
3152 {
3153 int i;
3154
3155 rctx->b.b.create_blend_state = si_create_blend_state;
3156 rctx->b.b.bind_blend_state = si_bind_blend_state;
3157 rctx->b.b.delete_blend_state = si_delete_blend_state;
3158 rctx->b.b.set_blend_color = si_set_blend_color;
3159
3160 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3161 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3162 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3163
3164 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3165 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3166 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3167
3168 for (i = 0; i < 8; i++) {
3169 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3170 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3171 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3172 }
3173 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3174 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3175 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3176
3177 rctx->b.b.set_clip_state = si_set_clip_state;
3178 rctx->b.b.set_scissor_states = si_set_scissor_states;
3179 rctx->b.b.set_viewport_states = si_set_viewport_states;
3180 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3181
3182 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3183 rctx->b.b.get_sample_position = si_get_sample_position;
3184
3185 rctx->b.b.create_vs_state = si_create_vs_state;
3186 rctx->b.b.create_fs_state = si_create_fs_state;
3187 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3188 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3189 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3190 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3191
3192 rctx->b.b.create_sampler_state = si_create_sampler_state;
3193 rctx->b.b.bind_vertex_sampler_states = si_bind_vs_sampler_states;
3194 rctx->b.b.bind_fragment_sampler_states = si_bind_ps_sampler_states;
3195 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3196
3197 rctx->b.b.create_sampler_view = si_create_sampler_view;
3198 rctx->b.b.set_vertex_sampler_views = si_set_vs_sampler_views;
3199 rctx->b.b.set_fragment_sampler_views = si_set_ps_sampler_views;
3200 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3201
3202 rctx->b.b.set_sample_mask = si_set_sample_mask;
3203
3204 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3205 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3206 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3207 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3208 rctx->b.b.set_index_buffer = si_set_index_buffer;
3209
3210 rctx->b.b.texture_barrier = si_texture_barrier;
3211 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3212
3213 rctx->b.b.draw_vbo = si_draw_vbo;
3214 }
3215
3216 void si_init_config(struct r600_context *rctx)
3217 {
3218 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3219
3220 if (pm4 == NULL)
3221 return;
3222
3223 si_cmd_context_control(pm4);
3224
3225 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3226
3227 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3228 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3229 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3230 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3231 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3232 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3233 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3234 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3235 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3236 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3237 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3238 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3239 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3240 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3241 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3242 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3243 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3244 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3245 S_028AA8_SWITCH_ON_EOP(1) |
3246 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3247 S_028AA8_PRIMGROUP_SIZE(63));
3248 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3249 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3250 if (rctx->b.chip_class < CIK)
3251 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3252 S_008A14_CLIP_VTX_REORDER_ENA(1));
3253
3254 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3255 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3256 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3257
3258 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3259
3260 if (rctx->b.chip_class >= CIK) {
3261 switch (rctx->screen->b.family) {
3262 case CHIP_BONAIRE:
3263 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3264 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3265 break;
3266 case CHIP_KAVERI:
3267 /* XXX todo */
3268 case CHIP_KABINI:
3269 /* XXX todo */
3270 default:
3271 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3272 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3273 break;
3274 }
3275 } else {
3276 switch (rctx->screen->b.family) {
3277 case CHIP_TAHITI:
3278 case CHIP_PITCAIRN:
3279 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3280 break;
3281 case CHIP_VERDE:
3282 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3283 break;
3284 case CHIP_OLAND:
3285 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3286 break;
3287 case CHIP_HAINAN:
3288 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3289 break;
3290 default:
3291 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3292 break;
3293 }
3294 }
3295
3296 si_pm4_set_state(rctx, init, pm4);
3297 }