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radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_state
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* RB+ register settings. */
121 if (sctx->screen->b.rbplus_allowed) {
122 unsigned spi_shader_col_format =
123 sctx->ps_shader.cso ?
124 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
125 unsigned sx_ps_downconvert = 0;
126 unsigned sx_blend_opt_epsilon = 0;
127 unsigned sx_blend_opt_control = 0;
128
129 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
130 struct r600_surface *surf =
131 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
132 unsigned format, swap, spi_format, colormask;
133 bool has_alpha, has_rgb;
134
135 if (!surf)
136 continue;
137
138 format = G_028C70_FORMAT(surf->cb_color_info);
139 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
140 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
141 colormask = (cb_target_mask >> (i * 4)) & 0xf;
142
143 /* Set if RGB and A are present. */
144 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
145
146 if (format == V_028C70_COLOR_8 ||
147 format == V_028C70_COLOR_16 ||
148 format == V_028C70_COLOR_32)
149 has_rgb = !has_alpha;
150 else
151 has_rgb = true;
152
153 /* Check the colormask and export format. */
154 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
155 has_rgb = false;
156 if (!(colormask & PIPE_MASK_A))
157 has_alpha = false;
158
159 if (spi_format == V_028714_SPI_SHADER_ZERO) {
160 has_rgb = false;
161 has_alpha = false;
162 }
163
164 /* Disable value checking for disabled channels. */
165 if (!has_rgb)
166 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
167 if (!has_alpha)
168 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
169
170 /* Enable down-conversion for 32bpp and smaller formats. */
171 switch (format) {
172 case V_028C70_COLOR_8:
173 case V_028C70_COLOR_8_8:
174 case V_028C70_COLOR_8_8_8_8:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
178 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
180 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
181 }
182 break;
183
184 case V_028C70_COLOR_5_6_5:
185 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_1_5_5_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_4_4_4_4:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_32:
206 if (swap == V_0280A0_SWAP_STD &&
207 spi_format == V_028714_SPI_SHADER_32_R)
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
209 else if (swap == V_0280A0_SWAP_ALT_REV &&
210 spi_format == V_028714_SPI_SHADER_32_AR)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
212 break;
213
214 case V_028C70_COLOR_16:
215 case V_028C70_COLOR_16_16:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
221 if (swap == V_0280A0_SWAP_STD ||
222 swap == V_0280A0_SWAP_STD_REV)
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
224 else
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
226 }
227 break;
228
229 case V_028C70_COLOR_10_11_11:
230 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
232 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_2_10_10_10:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
240 }
241 break;
242 }
243 }
244
245 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
246 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
249 } else if (sctx->screen->b.has_rbplus) {
250 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
251 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
252 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
253 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
254 }
255 }
256
257 /*
258 * Blender functions
259 */
260
261 static uint32_t si_translate_blend_function(int blend_func)
262 {
263 switch (blend_func) {
264 case PIPE_BLEND_ADD:
265 return V_028780_COMB_DST_PLUS_SRC;
266 case PIPE_BLEND_SUBTRACT:
267 return V_028780_COMB_SRC_MINUS_DST;
268 case PIPE_BLEND_REVERSE_SUBTRACT:
269 return V_028780_COMB_DST_MINUS_SRC;
270 case PIPE_BLEND_MIN:
271 return V_028780_COMB_MIN_DST_SRC;
272 case PIPE_BLEND_MAX:
273 return V_028780_COMB_MAX_DST_SRC;
274 default:
275 R600_ERR("Unknown blend function %d\n", blend_func);
276 assert(0);
277 break;
278 }
279 return 0;
280 }
281
282 static uint32_t si_translate_blend_factor(int blend_fact)
283 {
284 switch (blend_fact) {
285 case PIPE_BLENDFACTOR_ONE:
286 return V_028780_BLEND_ONE;
287 case PIPE_BLENDFACTOR_SRC_COLOR:
288 return V_028780_BLEND_SRC_COLOR;
289 case PIPE_BLENDFACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case PIPE_BLENDFACTOR_DST_ALPHA:
292 return V_028780_BLEND_DST_ALPHA;
293 case PIPE_BLENDFACTOR_DST_COLOR:
294 return V_028780_BLEND_DST_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE;
297 case PIPE_BLENDFACTOR_CONST_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_CONST_ALPHA:
300 return V_028780_BLEND_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_ZERO:
302 return V_028780_BLEND_ZERO;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_SRC1_COLOR:
316 return V_028780_BLEND_SRC1_COLOR;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA:
318 return V_028780_BLEND_SRC1_ALPHA;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
322 return V_028780_BLEND_INV_SRC1_ALPHA;
323 default:
324 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
325 assert(0);
326 break;
327 }
328 return 0;
329 }
330
331 static uint32_t si_translate_blend_opt_function(int blend_func)
332 {
333 switch (blend_func) {
334 case PIPE_BLEND_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case PIPE_BLEND_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case PIPE_BLEND_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case PIPE_BLEND_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case PIPE_BLEND_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
350 {
351 switch (blend_fact) {
352 case PIPE_BLENDFACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case PIPE_BLENDFACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case PIPE_BLENDFACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case PIPE_BLENDFACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 /**
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 */
378 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
379 unsigned *dst_factor, unsigned expected_dst,
380 unsigned replacement_src)
381 {
382 if (*src_factor == expected_dst &&
383 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
384 *src_factor = PIPE_BLENDFACTOR_ZERO;
385 *dst_factor = replacement_src;
386
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func == PIPE_BLEND_SUBTRACT)
389 *func = PIPE_BLEND_REVERSE_SUBTRACT;
390 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
391 *func = PIPE_BLEND_SUBTRACT;
392 }
393 }
394
395 static bool si_blend_factor_uses_dst(unsigned factor)
396 {
397 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
398 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
399 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
400 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
401 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
402 }
403
404 static void *si_create_blend_state_mode(struct pipe_context *ctx,
405 const struct pipe_blend_state *state,
406 unsigned mode)
407 {
408 struct si_context *sctx = (struct si_context*)ctx;
409 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
410 struct si_pm4_state *pm4 = &blend->pm4;
411 uint32_t sx_mrt_blend_opt[8] = {0};
412 uint32_t color_control = 0;
413
414 if (!blend)
415 return NULL;
416
417 blend->alpha_to_coverage = state->alpha_to_coverage;
418 blend->alpha_to_one = state->alpha_to_one;
419 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
420
421 if (state->logicop_enable) {
422 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
423 } else {
424 color_control |= S_028808_ROP3(0xcc);
425 }
426
427 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
428 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
429 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433
434 if (state->alpha_to_coverage)
435 blend->need_src_alpha_4bit |= 0xf;
436
437 blend->cb_target_mask = 0;
438 for (int i = 0; i < 8; i++) {
439 /* state->rt entries > 0 only written if independent blending */
440 const int j = state->independent_blend_enable ? i : 0;
441
442 unsigned eqRGB = state->rt[j].rgb_func;
443 unsigned srcRGB = state->rt[j].rgb_src_factor;
444 unsigned dstRGB = state->rt[j].rgb_dst_factor;
445 unsigned eqA = state->rt[j].alpha_func;
446 unsigned srcA = state->rt[j].alpha_src_factor;
447 unsigned dstA = state->rt[j].alpha_dst_factor;
448
449 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
450 unsigned blend_cntl = 0;
451
452 sx_mrt_blend_opt[i] =
453 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
454 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
455
456 /* Only set dual source blending for MRT0 to avoid a hang. */
457 if (i >= 1 && blend->dual_src_blend) {
458 /* Vulkan does this for dual source blending. */
459 if (i == 1)
460 blend_cntl |= S_028780_ENABLE(1);
461
462 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
463 continue;
464 }
465
466 /* Only addition and subtraction equations are supported with
467 * dual source blending.
468 */
469 if (blend->dual_src_blend &&
470 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
471 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
472 assert(!"Unsupported equation for dual source blending");
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* cb_render_state will disable unused ones */
478 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
479
480 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
481 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
482 continue;
483 }
484
485 /* Blending optimizations for RB+.
486 * These transformations don't change the behavior.
487 *
488 * First, get rid of DST in the blend factors:
489 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
490 */
491 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
492 PIPE_BLENDFACTOR_DST_COLOR,
493 PIPE_BLENDFACTOR_SRC_COLOR);
494 si_blend_remove_dst(&eqA, &srcA, &dstA,
495 PIPE_BLENDFACTOR_DST_COLOR,
496 PIPE_BLENDFACTOR_SRC_COLOR);
497 si_blend_remove_dst(&eqA, &srcA, &dstA,
498 PIPE_BLENDFACTOR_DST_ALPHA,
499 PIPE_BLENDFACTOR_SRC_ALPHA);
500
501 /* Look up the ideal settings from tables. */
502 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
503 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
504 srcA_opt = si_translate_blend_opt_factor(srcA, true);
505 dstA_opt = si_translate_blend_opt_factor(dstA, true);
506
507 /* Handle interdependencies. */
508 if (si_blend_factor_uses_dst(srcRGB))
509 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
510 if (si_blend_factor_uses_dst(srcA))
511 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
512
513 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
514 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
516 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
517 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
518
519 /* Set the final value. */
520 sx_mrt_blend_opt[i] =
521 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
522 S_028760_COLOR_DST_OPT(dstRGB_opt) |
523 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
524 S_028760_ALPHA_SRC_OPT(srcA_opt) |
525 S_028760_ALPHA_DST_OPT(dstA_opt) |
526 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
527
528 /* Set blend state. */
529 blend_cntl |= S_028780_ENABLE(1);
530 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
531 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
532 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
533
534 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
535 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
536 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
537 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
538 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
539 }
540 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
541
542 blend->blend_enable_4bit |= 0xfu << (i * 4);
543
544 /* This is only important for formats without alpha. */
545 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
547 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
549 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
550 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
551 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
552 }
553
554 if (blend->cb_target_mask) {
555 color_control |= S_028808_MODE(mode);
556 } else {
557 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
558 }
559
560 if (sctx->screen->b.has_rbplus) {
561 /* Disable RB+ blend optimizations for dual source blending.
562 * Vulkan does this.
563 */
564 if (blend->dual_src_blend) {
565 for (int i = 0; i < 8; i++) {
566 sx_mrt_blend_opt[i] =
567 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
568 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
569 }
570 }
571
572 for (int i = 0; i < 8; i++)
573 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
574 sx_mrt_blend_opt[i]);
575
576 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
577 if (blend->dual_src_blend || state->logicop_enable ||
578 mode == V_028808_CB_RESOLVE)
579 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
580 }
581
582 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
583 return blend;
584 }
585
586 static void *si_create_blend_state(struct pipe_context *ctx,
587 const struct pipe_blend_state *state)
588 {
589 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
590 }
591
592 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
596 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
597 sctx->do_update_shaders = true;
598 }
599
600 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
601 {
602 struct si_context *sctx = (struct si_context *)ctx;
603 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
604 }
605
606 static void si_set_blend_color(struct pipe_context *ctx,
607 const struct pipe_blend_color *state)
608 {
609 struct si_context *sctx = (struct si_context *)ctx;
610
611 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
612 return;
613
614 sctx->blend_color.state = *state;
615 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
616 }
617
618 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
619 {
620 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
621
622 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
623 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
624 }
625
626 /*
627 * Clipping
628 */
629
630 static void si_set_clip_state(struct pipe_context *ctx,
631 const struct pipe_clip_state *state)
632 {
633 struct si_context *sctx = (struct si_context *)ctx;
634 struct pipe_constant_buffer cb;
635
636 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
637 return;
638
639 sctx->clip_state.state = *state;
640 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
641
642 cb.buffer = NULL;
643 cb.user_buffer = state->ucp;
644 cb.buffer_offset = 0;
645 cb.buffer_size = 4*4*8;
646 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
647 pipe_resource_reference(&cb.buffer, NULL);
648 }
649
650 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
651 {
652 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
653
654 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
655 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
656 }
657
658 #define SIX_BITS 0x3F
659
660 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
661 {
662 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
663 struct si_shader *vs = si_get_vs_state(sctx);
664 struct tgsi_shader_info *info = si_get_vs_info(sctx);
665 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
666 unsigned window_space =
667 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
668 unsigned clipdist_mask =
669 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
670 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
671 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
672 unsigned total_mask;
673 bool misc_vec_ena;
674
675 if (vs->key.opt.hw_vs.clip_disable) {
676 assert(!info->culldist_writemask);
677 clipdist_mask = 0;
678 culldist_mask = 0;
679 }
680 total_mask = clipdist_mask | culldist_mask;
681
682 /* Clip distances on points have no effect, so need to be implemented
683 * as cull distances. This applies for the clipvertex case as well.
684 *
685 * Setting this for primitives other than points should have no adverse
686 * effects.
687 */
688 clipdist_mask &= rs->clip_plane_enable;
689 culldist_mask |= clipdist_mask;
690
691 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
692 info->writes_layer || info->writes_viewport_index;
693
694 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
695 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
696 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
697 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
698 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
699 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
700 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
701 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
702 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
703 clipdist_mask | (culldist_mask << 8));
704 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
705 rs->pa_cl_clip_cntl |
706 ucp_mask |
707 S_028810_CLIP_DISABLE(window_space));
708
709 /* reuse needs to be set off if we write oViewport */
710 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
711 S_028AB4_REUSE_OFF(info->writes_viewport_index));
712 }
713
714 /*
715 * inferred state between framebuffer and rasterizer
716 */
717 static void si_update_poly_offset_state(struct si_context *sctx)
718 {
719 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
720
721 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
722 si_pm4_bind_state(sctx, poly_offset, NULL);
723 return;
724 }
725
726 /* Use the user format, not db_render_format, so that the polygon
727 * offset behaves as expected by applications.
728 */
729 switch (sctx->framebuffer.state.zsbuf->texture->format) {
730 case PIPE_FORMAT_Z16_UNORM:
731 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
732 break;
733 default: /* 24-bit */
734 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
735 break;
736 case PIPE_FORMAT_Z32_FLOAT:
737 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
738 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
739 break;
740 }
741 }
742
743 /*
744 * Rasterizer
745 */
746
747 static uint32_t si_translate_fill(uint32_t func)
748 {
749 switch(func) {
750 case PIPE_POLYGON_MODE_FILL:
751 return V_028814_X_DRAW_TRIANGLES;
752 case PIPE_POLYGON_MODE_LINE:
753 return V_028814_X_DRAW_LINES;
754 case PIPE_POLYGON_MODE_POINT:
755 return V_028814_X_DRAW_POINTS;
756 default:
757 assert(0);
758 return V_028814_X_DRAW_POINTS;
759 }
760 }
761
762 static void *si_create_rs_state(struct pipe_context *ctx,
763 const struct pipe_rasterizer_state *state)
764 {
765 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
766 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
767 struct si_pm4_state *pm4 = &rs->pm4;
768 unsigned tmp, i;
769 float psize_min, psize_max;
770
771 if (!rs) {
772 return NULL;
773 }
774
775 rs->scissor_enable = state->scissor;
776 rs->clip_halfz = state->clip_halfz;
777 rs->two_side = state->light_twoside;
778 rs->multisample_enable = state->multisample;
779 rs->force_persample_interp = state->force_persample_interp;
780 rs->clip_plane_enable = state->clip_plane_enable;
781 rs->line_stipple_enable = state->line_stipple_enable;
782 rs->poly_stipple_enable = state->poly_stipple_enable;
783 rs->line_smooth = state->line_smooth;
784 rs->poly_smooth = state->poly_smooth;
785 rs->uses_poly_offset = state->offset_point || state->offset_line ||
786 state->offset_tri;
787 rs->clamp_fragment_color = state->clamp_fragment_color;
788 rs->flatshade = state->flatshade;
789 rs->sprite_coord_enable = state->sprite_coord_enable;
790 rs->rasterizer_discard = state->rasterizer_discard;
791 rs->pa_sc_line_stipple = state->line_stipple_enable ?
792 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
793 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
794 rs->pa_cl_clip_cntl =
795 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
796 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
797 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
798 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
799 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
800
801 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
802 S_0286D4_FLAT_SHADE_ENA(1) |
803 S_0286D4_PNT_SPRITE_ENA(1) |
804 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
805 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
806 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
807 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
808 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
809
810 /* point size 12.4 fixed point */
811 tmp = (unsigned)(state->point_size * 8.0);
812 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
813
814 if (state->point_size_per_vertex) {
815 psize_min = util_get_min_point_size(state);
816 psize_max = 8192;
817 } else {
818 /* Force the point size to be as if the vertex output was disabled. */
819 psize_min = state->point_size;
820 psize_max = state->point_size;
821 }
822 /* Divide by two, because 0.5 = 1 pixel. */
823 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
824 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
825 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
826
827 tmp = (unsigned)state->line_width * 8;
828 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
829 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
830 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
831 S_028A48_MSAA_ENABLE(state->multisample ||
832 state->poly_smooth ||
833 state->line_smooth) |
834 S_028A48_VPORT_SCISSOR_ENABLE(1) |
835 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
836
837 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
838 S_028BE4_PIX_CENTER(state->half_pixel_center) |
839 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
840
841 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
842 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
843 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
844 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
845 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
846 S_028814_FACE(!state->front_ccw) |
847 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
848 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
849 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
850 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
851 state->fill_back != PIPE_POLYGON_MODE_FILL) |
852 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
853 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
854 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
855 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
856
857 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
858 for (i = 0; i < 3; i++) {
859 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
860 float offset_units = state->offset_units;
861 float offset_scale = state->offset_scale * 16.0f;
862 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
863
864 if (!state->offset_units_unscaled) {
865 switch (i) {
866 case 0: /* 16-bit zbuffer */
867 offset_units *= 4.0f;
868 pa_su_poly_offset_db_fmt_cntl =
869 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
870 break;
871 case 1: /* 24-bit zbuffer */
872 offset_units *= 2.0f;
873 pa_su_poly_offset_db_fmt_cntl =
874 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
875 break;
876 case 2: /* 32-bit zbuffer */
877 offset_units *= 1.0f;
878 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
879 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
880 break;
881 }
882 }
883
884 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
885 fui(offset_scale));
886 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
887 fui(offset_units));
888 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
889 fui(offset_scale));
890 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
891 fui(offset_units));
892 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
893 pa_su_poly_offset_db_fmt_cntl);
894 }
895
896 return rs;
897 }
898
899 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
900 {
901 struct si_context *sctx = (struct si_context *)ctx;
902 struct si_state_rasterizer *old_rs =
903 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
904 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
905
906 if (!state)
907 return;
908
909 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
910 si_mark_atom_dirty(sctx, &sctx->db_render_state);
911
912 /* Update the small primitive filter workaround if necessary. */
913 if (sctx->b.family >= CHIP_POLARIS10 &&
914 sctx->framebuffer.nr_samples > 1)
915 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
916 }
917
918 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
919
920 si_pm4_bind_state(sctx, rasterizer, rs);
921 si_update_poly_offset_state(sctx);
922
923 si_mark_atom_dirty(sctx, &sctx->clip_regs);
924 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
925 rs->line_stipple_enable;
926 sctx->do_update_shaders = true;
927 }
928
929 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
930 {
931 struct si_context *sctx = (struct si_context *)ctx;
932
933 if (sctx->queued.named.rasterizer == state)
934 si_pm4_bind_state(sctx, poly_offset, NULL);
935 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
936 }
937
938 /*
939 * infeered state between dsa and stencil ref
940 */
941 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
942 {
943 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
944 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
945 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
946
947 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
948 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
949 S_028430_STENCILMASK(dsa->valuemask[0]) |
950 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
951 S_028430_STENCILOPVAL(1));
952 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
953 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
954 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
955 S_028434_STENCILOPVAL_BF(1));
956 }
957
958 static void si_set_stencil_ref(struct pipe_context *ctx,
959 const struct pipe_stencil_ref *state)
960 {
961 struct si_context *sctx = (struct si_context *)ctx;
962
963 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
964 return;
965
966 sctx->stencil_ref.state = *state;
967 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
968 }
969
970
971 /*
972 * DSA
973 */
974
975 static uint32_t si_translate_stencil_op(int s_op)
976 {
977 switch (s_op) {
978 case PIPE_STENCIL_OP_KEEP:
979 return V_02842C_STENCIL_KEEP;
980 case PIPE_STENCIL_OP_ZERO:
981 return V_02842C_STENCIL_ZERO;
982 case PIPE_STENCIL_OP_REPLACE:
983 return V_02842C_STENCIL_REPLACE_TEST;
984 case PIPE_STENCIL_OP_INCR:
985 return V_02842C_STENCIL_ADD_CLAMP;
986 case PIPE_STENCIL_OP_DECR:
987 return V_02842C_STENCIL_SUB_CLAMP;
988 case PIPE_STENCIL_OP_INCR_WRAP:
989 return V_02842C_STENCIL_ADD_WRAP;
990 case PIPE_STENCIL_OP_DECR_WRAP:
991 return V_02842C_STENCIL_SUB_WRAP;
992 case PIPE_STENCIL_OP_INVERT:
993 return V_02842C_STENCIL_INVERT;
994 default:
995 R600_ERR("Unknown stencil op %d", s_op);
996 assert(0);
997 break;
998 }
999 return 0;
1000 }
1001
1002 static void *si_create_dsa_state(struct pipe_context *ctx,
1003 const struct pipe_depth_stencil_alpha_state *state)
1004 {
1005 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1006 struct si_pm4_state *pm4 = &dsa->pm4;
1007 unsigned db_depth_control;
1008 uint32_t db_stencil_control = 0;
1009
1010 if (!dsa) {
1011 return NULL;
1012 }
1013
1014 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1015 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1016 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1017 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1018
1019 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1020 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1021 S_028800_ZFUNC(state->depth.func) |
1022 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1023
1024 /* stencil */
1025 if (state->stencil[0].enabled) {
1026 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1027 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1028 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1029 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1030 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1031
1032 if (state->stencil[1].enabled) {
1033 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1034 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1035 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1036 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1037 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1038 }
1039 }
1040
1041 /* alpha */
1042 if (state->alpha.enabled) {
1043 dsa->alpha_func = state->alpha.func;
1044
1045 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1046 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1047 } else {
1048 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1049 }
1050
1051 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1052 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1053 if (state->depth.bounds_test) {
1054 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1055 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1056 }
1057
1058 return dsa;
1059 }
1060
1061 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1062 {
1063 struct si_context *sctx = (struct si_context *)ctx;
1064 struct si_state_dsa *dsa = state;
1065
1066 if (!state)
1067 return;
1068
1069 si_pm4_bind_state(sctx, dsa, dsa);
1070
1071 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1072 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1073 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1074 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1075 }
1076 sctx->do_update_shaders = true;
1077 }
1078
1079 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1080 {
1081 struct si_context *sctx = (struct si_context *)ctx;
1082 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1083 }
1084
1085 static void *si_create_db_flush_dsa(struct si_context *sctx)
1086 {
1087 struct pipe_depth_stencil_alpha_state dsa = {};
1088
1089 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1090 }
1091
1092 /* DB RENDER STATE */
1093
1094 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1095 {
1096 struct si_context *sctx = (struct si_context*)ctx;
1097
1098 /* Pipeline stat & streamout queries. */
1099 if (enable) {
1100 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1101 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1102 } else {
1103 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1104 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1105 }
1106
1107 /* Occlusion queries. */
1108 if (sctx->occlusion_queries_disabled != !enable) {
1109 sctx->occlusion_queries_disabled = !enable;
1110 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1111 }
1112 }
1113
1114 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1115 {
1116 struct si_context *sctx = (struct si_context*)ctx;
1117
1118 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1119 }
1120
1121 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1122 {
1123 struct si_context *sctx = (struct si_context*)ctx;
1124
1125 st->saved_compute = sctx->cs_shader_state.program;
1126
1127 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1128 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1129 }
1130
1131 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1132 {
1133 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1134 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1135 unsigned db_shader_control;
1136
1137 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1138
1139 /* DB_RENDER_CONTROL */
1140 if (sctx->dbcb_depth_copy_enabled ||
1141 sctx->dbcb_stencil_copy_enabled) {
1142 radeon_emit(cs,
1143 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1144 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1145 S_028000_COPY_CENTROID(1) |
1146 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1147 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1148 radeon_emit(cs,
1149 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1150 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1151 } else {
1152 radeon_emit(cs,
1153 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1154 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1155 }
1156
1157 /* DB_COUNT_CONTROL (occlusion queries) */
1158 if (sctx->b.num_occlusion_queries > 0 &&
1159 !sctx->occlusion_queries_disabled) {
1160 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1161
1162 if (sctx->b.chip_class >= CIK) {
1163 radeon_emit(cs,
1164 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1165 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1166 S_028004_ZPASS_ENABLE(1) |
1167 S_028004_SLICE_EVEN_ENABLE(1) |
1168 S_028004_SLICE_ODD_ENABLE(1));
1169 } else {
1170 radeon_emit(cs,
1171 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1172 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1173 }
1174 } else {
1175 /* Disable occlusion queries. */
1176 if (sctx->b.chip_class >= CIK) {
1177 radeon_emit(cs, 0);
1178 } else {
1179 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1180 }
1181 }
1182
1183 /* DB_RENDER_OVERRIDE2 */
1184 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1185 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1186 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1187 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1188
1189 db_shader_control = sctx->ps_db_shader_control;
1190
1191 /* Bug workaround for smoothing (overrasterization) on SI. */
1192 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1193 db_shader_control &= C_02880C_Z_ORDER;
1194 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1195 }
1196
1197 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1198 if (!rs || !rs->multisample_enable)
1199 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1200
1201 if (sctx->screen->b.has_rbplus &&
1202 !sctx->screen->b.rbplus_allowed)
1203 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1204
1205 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1206 db_shader_control);
1207 }
1208
1209 /*
1210 * format translation
1211 */
1212 static uint32_t si_translate_colorformat(enum pipe_format format)
1213 {
1214 const struct util_format_description *desc = util_format_description(format);
1215
1216 #define HAS_SIZE(x,y,z,w) \
1217 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1218 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1219
1220 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1221 return V_028C70_COLOR_10_11_11;
1222
1223 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1224 return V_028C70_COLOR_INVALID;
1225
1226 /* hw cannot support mixed formats (except depth/stencil, since
1227 * stencil is not written to). */
1228 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1229 return V_028C70_COLOR_INVALID;
1230
1231 switch (desc->nr_channels) {
1232 case 1:
1233 switch (desc->channel[0].size) {
1234 case 8:
1235 return V_028C70_COLOR_8;
1236 case 16:
1237 return V_028C70_COLOR_16;
1238 case 32:
1239 return V_028C70_COLOR_32;
1240 }
1241 break;
1242 case 2:
1243 if (desc->channel[0].size == desc->channel[1].size) {
1244 switch (desc->channel[0].size) {
1245 case 8:
1246 return V_028C70_COLOR_8_8;
1247 case 16:
1248 return V_028C70_COLOR_16_16;
1249 case 32:
1250 return V_028C70_COLOR_32_32;
1251 }
1252 } else if (HAS_SIZE(8,24,0,0)) {
1253 return V_028C70_COLOR_24_8;
1254 } else if (HAS_SIZE(24,8,0,0)) {
1255 return V_028C70_COLOR_8_24;
1256 }
1257 break;
1258 case 3:
1259 if (HAS_SIZE(5,6,5,0)) {
1260 return V_028C70_COLOR_5_6_5;
1261 } else if (HAS_SIZE(32,8,24,0)) {
1262 return V_028C70_COLOR_X24_8_32_FLOAT;
1263 }
1264 break;
1265 case 4:
1266 if (desc->channel[0].size == desc->channel[1].size &&
1267 desc->channel[0].size == desc->channel[2].size &&
1268 desc->channel[0].size == desc->channel[3].size) {
1269 switch (desc->channel[0].size) {
1270 case 4:
1271 return V_028C70_COLOR_4_4_4_4;
1272 case 8:
1273 return V_028C70_COLOR_8_8_8_8;
1274 case 16:
1275 return V_028C70_COLOR_16_16_16_16;
1276 case 32:
1277 return V_028C70_COLOR_32_32_32_32;
1278 }
1279 } else if (HAS_SIZE(5,5,5,1)) {
1280 return V_028C70_COLOR_1_5_5_5;
1281 } else if (HAS_SIZE(10,10,10,2)) {
1282 return V_028C70_COLOR_2_10_10_10;
1283 }
1284 break;
1285 }
1286 return V_028C70_COLOR_INVALID;
1287 }
1288
1289 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1290 {
1291 if (SI_BIG_ENDIAN) {
1292 switch(colorformat) {
1293 /* 8-bit buffers. */
1294 case V_028C70_COLOR_8:
1295 return V_028C70_ENDIAN_NONE;
1296
1297 /* 16-bit buffers. */
1298 case V_028C70_COLOR_5_6_5:
1299 case V_028C70_COLOR_1_5_5_5:
1300 case V_028C70_COLOR_4_4_4_4:
1301 case V_028C70_COLOR_16:
1302 case V_028C70_COLOR_8_8:
1303 return V_028C70_ENDIAN_8IN16;
1304
1305 /* 32-bit buffers. */
1306 case V_028C70_COLOR_8_8_8_8:
1307 case V_028C70_COLOR_2_10_10_10:
1308 case V_028C70_COLOR_8_24:
1309 case V_028C70_COLOR_24_8:
1310 case V_028C70_COLOR_16_16:
1311 return V_028C70_ENDIAN_8IN32;
1312
1313 /* 64-bit buffers. */
1314 case V_028C70_COLOR_16_16_16_16:
1315 return V_028C70_ENDIAN_8IN16;
1316
1317 case V_028C70_COLOR_32_32:
1318 return V_028C70_ENDIAN_8IN32;
1319
1320 /* 128-bit buffers. */
1321 case V_028C70_COLOR_32_32_32_32:
1322 return V_028C70_ENDIAN_8IN32;
1323 default:
1324 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1325 }
1326 } else {
1327 return V_028C70_ENDIAN_NONE;
1328 }
1329 }
1330
1331 static uint32_t si_translate_dbformat(enum pipe_format format)
1332 {
1333 switch (format) {
1334 case PIPE_FORMAT_Z16_UNORM:
1335 return V_028040_Z_16;
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1337 case PIPE_FORMAT_X8Z24_UNORM:
1338 case PIPE_FORMAT_Z24X8_UNORM:
1339 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1340 return V_028040_Z_24; /* deprecated on SI */
1341 case PIPE_FORMAT_Z32_FLOAT:
1342 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1343 return V_028040_Z_32_FLOAT;
1344 default:
1345 return V_028040_Z_INVALID;
1346 }
1347 }
1348
1349 /*
1350 * Texture translation
1351 */
1352
1353 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1354 enum pipe_format format,
1355 const struct util_format_description *desc,
1356 int first_non_void)
1357 {
1358 struct si_screen *sscreen = (struct si_screen*)screen;
1359 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1360 sscreen->b.info.drm_minor >= 31) ||
1361 sscreen->b.info.drm_major == 3;
1362 bool uniform = true;
1363 int i;
1364
1365 /* Colorspace (return non-RGB formats directly). */
1366 switch (desc->colorspace) {
1367 /* Depth stencil formats */
1368 case UTIL_FORMAT_COLORSPACE_ZS:
1369 switch (format) {
1370 case PIPE_FORMAT_Z16_UNORM:
1371 return V_008F14_IMG_DATA_FORMAT_16;
1372 case PIPE_FORMAT_X24S8_UINT:
1373 case PIPE_FORMAT_S8X24_UINT:
1374 /*
1375 * Implemented as an 8_8_8_8 data format to fix texture
1376 * gathers in stencil sampling. This affects at least
1377 * GL45-CTS.texture_cube_map_array.sampling on VI.
1378 */
1379 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1380 case PIPE_FORMAT_Z24X8_UNORM:
1381 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1382 return V_008F14_IMG_DATA_FORMAT_8_24;
1383 case PIPE_FORMAT_X8Z24_UNORM:
1384 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1385 return V_008F14_IMG_DATA_FORMAT_24_8;
1386 case PIPE_FORMAT_S8_UINT:
1387 return V_008F14_IMG_DATA_FORMAT_8;
1388 case PIPE_FORMAT_Z32_FLOAT:
1389 return V_008F14_IMG_DATA_FORMAT_32;
1390 case PIPE_FORMAT_X32_S8X24_UINT:
1391 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1392 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1393 default:
1394 goto out_unknown;
1395 }
1396
1397 case UTIL_FORMAT_COLORSPACE_YUV:
1398 goto out_unknown; /* TODO */
1399
1400 case UTIL_FORMAT_COLORSPACE_SRGB:
1401 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1402 goto out_unknown;
1403 break;
1404
1405 default:
1406 break;
1407 }
1408
1409 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1410 if (!enable_compressed_formats)
1411 goto out_unknown;
1412
1413 switch (format) {
1414 case PIPE_FORMAT_RGTC1_SNORM:
1415 case PIPE_FORMAT_LATC1_SNORM:
1416 case PIPE_FORMAT_RGTC1_UNORM:
1417 case PIPE_FORMAT_LATC1_UNORM:
1418 return V_008F14_IMG_DATA_FORMAT_BC4;
1419 case PIPE_FORMAT_RGTC2_SNORM:
1420 case PIPE_FORMAT_LATC2_SNORM:
1421 case PIPE_FORMAT_RGTC2_UNORM:
1422 case PIPE_FORMAT_LATC2_UNORM:
1423 return V_008F14_IMG_DATA_FORMAT_BC5;
1424 default:
1425 goto out_unknown;
1426 }
1427 }
1428
1429 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1430 (sscreen->b.family == CHIP_STONEY ||
1431 sscreen->b.chip_class >= GFX9)) {
1432 switch (format) {
1433 case PIPE_FORMAT_ETC1_RGB8:
1434 case PIPE_FORMAT_ETC2_RGB8:
1435 case PIPE_FORMAT_ETC2_SRGB8:
1436 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1437 case PIPE_FORMAT_ETC2_RGB8A1:
1438 case PIPE_FORMAT_ETC2_SRGB8A1:
1439 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1440 case PIPE_FORMAT_ETC2_RGBA8:
1441 case PIPE_FORMAT_ETC2_SRGBA8:
1442 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1443 case PIPE_FORMAT_ETC2_R11_UNORM:
1444 case PIPE_FORMAT_ETC2_R11_SNORM:
1445 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1446 case PIPE_FORMAT_ETC2_RG11_UNORM:
1447 case PIPE_FORMAT_ETC2_RG11_SNORM:
1448 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1449 default:
1450 goto out_unknown;
1451 }
1452 }
1453
1454 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1455 if (!enable_compressed_formats)
1456 goto out_unknown;
1457
1458 switch (format) {
1459 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1460 case PIPE_FORMAT_BPTC_SRGBA:
1461 return V_008F14_IMG_DATA_FORMAT_BC7;
1462 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1463 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1464 return V_008F14_IMG_DATA_FORMAT_BC6;
1465 default:
1466 goto out_unknown;
1467 }
1468 }
1469
1470 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1471 switch (format) {
1472 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1473 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1474 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1475 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1476 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1477 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1478 default:
1479 goto out_unknown;
1480 }
1481 }
1482
1483 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1484 if (!enable_compressed_formats)
1485 goto out_unknown;
1486
1487 if (!util_format_s3tc_enabled) {
1488 goto out_unknown;
1489 }
1490
1491 switch (format) {
1492 case PIPE_FORMAT_DXT1_RGB:
1493 case PIPE_FORMAT_DXT1_RGBA:
1494 case PIPE_FORMAT_DXT1_SRGB:
1495 case PIPE_FORMAT_DXT1_SRGBA:
1496 return V_008F14_IMG_DATA_FORMAT_BC1;
1497 case PIPE_FORMAT_DXT3_RGBA:
1498 case PIPE_FORMAT_DXT3_SRGBA:
1499 return V_008F14_IMG_DATA_FORMAT_BC2;
1500 case PIPE_FORMAT_DXT5_RGBA:
1501 case PIPE_FORMAT_DXT5_SRGBA:
1502 return V_008F14_IMG_DATA_FORMAT_BC3;
1503 default:
1504 goto out_unknown;
1505 }
1506 }
1507
1508 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1509 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1510 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1511 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1512 }
1513
1514 /* R8G8Bx_SNORM - TODO CxV8U8 */
1515
1516 /* hw cannot support mixed formats (except depth/stencil, since only
1517 * depth is read).*/
1518 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1519 goto out_unknown;
1520
1521 /* See whether the components are of the same size. */
1522 for (i = 1; i < desc->nr_channels; i++) {
1523 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1524 }
1525
1526 /* Non-uniform formats. */
1527 if (!uniform) {
1528 switch(desc->nr_channels) {
1529 case 3:
1530 if (desc->channel[0].size == 5 &&
1531 desc->channel[1].size == 6 &&
1532 desc->channel[2].size == 5) {
1533 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1534 }
1535 goto out_unknown;
1536 case 4:
1537 if (desc->channel[0].size == 5 &&
1538 desc->channel[1].size == 5 &&
1539 desc->channel[2].size == 5 &&
1540 desc->channel[3].size == 1) {
1541 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1542 }
1543 if (desc->channel[0].size == 10 &&
1544 desc->channel[1].size == 10 &&
1545 desc->channel[2].size == 10 &&
1546 desc->channel[3].size == 2) {
1547 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1548 }
1549 goto out_unknown;
1550 }
1551 goto out_unknown;
1552 }
1553
1554 if (first_non_void < 0 || first_non_void > 3)
1555 goto out_unknown;
1556
1557 /* uniform formats */
1558 switch (desc->channel[first_non_void].size) {
1559 case 4:
1560 switch (desc->nr_channels) {
1561 #if 0 /* Not supported for render targets */
1562 case 2:
1563 return V_008F14_IMG_DATA_FORMAT_4_4;
1564 #endif
1565 case 4:
1566 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1567 }
1568 break;
1569 case 8:
1570 switch (desc->nr_channels) {
1571 case 1:
1572 return V_008F14_IMG_DATA_FORMAT_8;
1573 case 2:
1574 return V_008F14_IMG_DATA_FORMAT_8_8;
1575 case 4:
1576 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1577 }
1578 break;
1579 case 16:
1580 switch (desc->nr_channels) {
1581 case 1:
1582 return V_008F14_IMG_DATA_FORMAT_16;
1583 case 2:
1584 return V_008F14_IMG_DATA_FORMAT_16_16;
1585 case 4:
1586 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1587 }
1588 break;
1589 case 32:
1590 switch (desc->nr_channels) {
1591 case 1:
1592 return V_008F14_IMG_DATA_FORMAT_32;
1593 case 2:
1594 return V_008F14_IMG_DATA_FORMAT_32_32;
1595 #if 0 /* Not supported for render targets */
1596 case 3:
1597 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1598 #endif
1599 case 4:
1600 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1601 }
1602 }
1603
1604 out_unknown:
1605 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1606 return ~0;
1607 }
1608
1609 static unsigned si_tex_wrap(unsigned wrap)
1610 {
1611 switch (wrap) {
1612 default:
1613 case PIPE_TEX_WRAP_REPEAT:
1614 return V_008F30_SQ_TEX_WRAP;
1615 case PIPE_TEX_WRAP_CLAMP:
1616 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1617 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1618 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1619 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1620 return V_008F30_SQ_TEX_CLAMP_BORDER;
1621 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1622 return V_008F30_SQ_TEX_MIRROR;
1623 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1624 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1625 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1626 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1627 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1628 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1629 }
1630 }
1631
1632 static unsigned si_tex_mipfilter(unsigned filter)
1633 {
1634 switch (filter) {
1635 case PIPE_TEX_MIPFILTER_NEAREST:
1636 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1637 case PIPE_TEX_MIPFILTER_LINEAR:
1638 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1639 default:
1640 case PIPE_TEX_MIPFILTER_NONE:
1641 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1642 }
1643 }
1644
1645 static unsigned si_tex_compare(unsigned compare)
1646 {
1647 switch (compare) {
1648 default:
1649 case PIPE_FUNC_NEVER:
1650 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1651 case PIPE_FUNC_LESS:
1652 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1653 case PIPE_FUNC_EQUAL:
1654 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1655 case PIPE_FUNC_LEQUAL:
1656 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1657 case PIPE_FUNC_GREATER:
1658 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1659 case PIPE_FUNC_NOTEQUAL:
1660 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1661 case PIPE_FUNC_GEQUAL:
1662 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1663 case PIPE_FUNC_ALWAYS:
1664 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1665 }
1666 }
1667
1668 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1669 unsigned view_target, unsigned nr_samples)
1670 {
1671 unsigned res_target = rtex->resource.b.b.target;
1672
1673 if (view_target == PIPE_TEXTURE_CUBE ||
1674 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1675 res_target = view_target;
1676 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1677 else if (res_target == PIPE_TEXTURE_CUBE ||
1678 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1679 res_target = PIPE_TEXTURE_2D_ARRAY;
1680
1681 /* GFX9 allocates 1D textures as 2D. */
1682 if ((res_target == PIPE_TEXTURE_1D ||
1683 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1684 sscreen->b.chip_class >= GFX9 &&
1685 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1686 if (res_target == PIPE_TEXTURE_1D)
1687 res_target = PIPE_TEXTURE_2D;
1688 else
1689 res_target = PIPE_TEXTURE_2D_ARRAY;
1690 }
1691
1692 switch (res_target) {
1693 default:
1694 case PIPE_TEXTURE_1D:
1695 return V_008F1C_SQ_RSRC_IMG_1D;
1696 case PIPE_TEXTURE_1D_ARRAY:
1697 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1698 case PIPE_TEXTURE_2D:
1699 case PIPE_TEXTURE_RECT:
1700 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1701 V_008F1C_SQ_RSRC_IMG_2D;
1702 case PIPE_TEXTURE_2D_ARRAY:
1703 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1704 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1705 case PIPE_TEXTURE_3D:
1706 return V_008F1C_SQ_RSRC_IMG_3D;
1707 case PIPE_TEXTURE_CUBE:
1708 case PIPE_TEXTURE_CUBE_ARRAY:
1709 return V_008F1C_SQ_RSRC_IMG_CUBE;
1710 }
1711 }
1712
1713 /*
1714 * Format support testing
1715 */
1716
1717 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1718 {
1719 return si_translate_texformat(screen, format, util_format_description(format),
1720 util_format_get_first_non_void_channel(format)) != ~0U;
1721 }
1722
1723 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1724 const struct util_format_description *desc,
1725 int first_non_void)
1726 {
1727 int i;
1728
1729 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1730 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1731
1732 assert(first_non_void >= 0);
1733
1734 if (desc->nr_channels == 4 &&
1735 desc->channel[0].size == 10 &&
1736 desc->channel[1].size == 10 &&
1737 desc->channel[2].size == 10 &&
1738 desc->channel[3].size == 2)
1739 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1740
1741 /* See whether the components are of the same size. */
1742 for (i = 0; i < desc->nr_channels; i++) {
1743 if (desc->channel[first_non_void].size != desc->channel[i].size)
1744 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1745 }
1746
1747 switch (desc->channel[first_non_void].size) {
1748 case 8:
1749 switch (desc->nr_channels) {
1750 case 1:
1751 case 3: /* 3 loads */
1752 return V_008F0C_BUF_DATA_FORMAT_8;
1753 case 2:
1754 return V_008F0C_BUF_DATA_FORMAT_8_8;
1755 case 4:
1756 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1757 }
1758 break;
1759 case 16:
1760 switch (desc->nr_channels) {
1761 case 1:
1762 case 3: /* 3 loads */
1763 return V_008F0C_BUF_DATA_FORMAT_16;
1764 case 2:
1765 return V_008F0C_BUF_DATA_FORMAT_16_16;
1766 case 4:
1767 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1768 }
1769 break;
1770 case 32:
1771 switch (desc->nr_channels) {
1772 case 1:
1773 return V_008F0C_BUF_DATA_FORMAT_32;
1774 case 2:
1775 return V_008F0C_BUF_DATA_FORMAT_32_32;
1776 case 3:
1777 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1778 case 4:
1779 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1780 }
1781 break;
1782 case 64:
1783 /* Legacy double formats. */
1784 switch (desc->nr_channels) {
1785 case 1: /* 1 load */
1786 return V_008F0C_BUF_DATA_FORMAT_32_32;
1787 case 2: /* 1 load */
1788 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1789 case 3: /* 3 loads */
1790 return V_008F0C_BUF_DATA_FORMAT_32_32;
1791 case 4: /* 2 loads */
1792 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1793 }
1794 break;
1795 }
1796
1797 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1798 }
1799
1800 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1801 const struct util_format_description *desc,
1802 int first_non_void)
1803 {
1804 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1805 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1806
1807 assert(first_non_void >= 0);
1808
1809 switch (desc->channel[first_non_void].type) {
1810 case UTIL_FORMAT_TYPE_SIGNED:
1811 case UTIL_FORMAT_TYPE_FIXED:
1812 if (desc->channel[first_non_void].size >= 32 ||
1813 desc->channel[first_non_void].pure_integer)
1814 return V_008F0C_BUF_NUM_FORMAT_SINT;
1815 else if (desc->channel[first_non_void].normalized)
1816 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1817 else
1818 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1819 break;
1820 case UTIL_FORMAT_TYPE_UNSIGNED:
1821 if (desc->channel[first_non_void].size >= 32 ||
1822 desc->channel[first_non_void].pure_integer)
1823 return V_008F0C_BUF_NUM_FORMAT_UINT;
1824 else if (desc->channel[first_non_void].normalized)
1825 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1826 else
1827 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1828 break;
1829 case UTIL_FORMAT_TYPE_FLOAT:
1830 default:
1831 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1832 }
1833 }
1834
1835 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1836 enum pipe_format format,
1837 unsigned usage)
1838 {
1839 const struct util_format_description *desc;
1840 int first_non_void;
1841 unsigned data_format;
1842
1843 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1844 PIPE_BIND_SAMPLER_VIEW |
1845 PIPE_BIND_VERTEX_BUFFER)) == 0);
1846
1847 desc = util_format_description(format);
1848
1849 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1850 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1851 * for read-only access (with caveats surrounding bounds checks), but
1852 * obviously fails for write access which we have to implement for
1853 * shader images. Luckily, OpenGL doesn't expect this to be supported
1854 * anyway, and so the only impact is on PBO uploads / downloads, which
1855 * shouldn't be expected to be fast for GL_RGB anyway.
1856 */
1857 if (desc->block.bits == 3 * 8 ||
1858 desc->block.bits == 3 * 16) {
1859 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1860 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1861 if (!usage)
1862 return 0;
1863 }
1864 }
1865
1866 first_non_void = util_format_get_first_non_void_channel(format);
1867 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1868 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1869 return 0;
1870
1871 return usage;
1872 }
1873
1874 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1875 {
1876 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1877 r600_translate_colorswap(format, false) != ~0U;
1878 }
1879
1880 static bool si_is_zs_format_supported(enum pipe_format format)
1881 {
1882 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1883 }
1884
1885 static boolean si_is_format_supported(struct pipe_screen *screen,
1886 enum pipe_format format,
1887 enum pipe_texture_target target,
1888 unsigned sample_count,
1889 unsigned usage)
1890 {
1891 unsigned retval = 0;
1892
1893 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1894 R600_ERR("r600: unsupported texture type %d\n", target);
1895 return false;
1896 }
1897
1898 if (!util_format_is_supported(format, usage))
1899 return false;
1900
1901 if (sample_count > 1) {
1902 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1903 return false;
1904
1905 if (usage & PIPE_BIND_SHADER_IMAGE)
1906 return false;
1907
1908 switch (sample_count) {
1909 case 2:
1910 case 4:
1911 case 8:
1912 break;
1913 case 16:
1914 if (format == PIPE_FORMAT_NONE)
1915 return true;
1916 else
1917 return false;
1918 default:
1919 return false;
1920 }
1921 }
1922
1923 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1924 PIPE_BIND_SHADER_IMAGE)) {
1925 if (target == PIPE_BUFFER) {
1926 retval |= si_is_vertex_format_supported(
1927 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1928 PIPE_BIND_SHADER_IMAGE));
1929 } else {
1930 if (si_is_sampler_format_supported(screen, format))
1931 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1932 PIPE_BIND_SHADER_IMAGE);
1933 }
1934 }
1935
1936 if ((usage & (PIPE_BIND_RENDER_TARGET |
1937 PIPE_BIND_DISPLAY_TARGET |
1938 PIPE_BIND_SCANOUT |
1939 PIPE_BIND_SHARED |
1940 PIPE_BIND_BLENDABLE)) &&
1941 si_is_colorbuffer_format_supported(format)) {
1942 retval |= usage &
1943 (PIPE_BIND_RENDER_TARGET |
1944 PIPE_BIND_DISPLAY_TARGET |
1945 PIPE_BIND_SCANOUT |
1946 PIPE_BIND_SHARED);
1947 if (!util_format_is_pure_integer(format) &&
1948 !util_format_is_depth_or_stencil(format))
1949 retval |= usage & PIPE_BIND_BLENDABLE;
1950 }
1951
1952 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1953 si_is_zs_format_supported(format)) {
1954 retval |= PIPE_BIND_DEPTH_STENCIL;
1955 }
1956
1957 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1958 retval |= si_is_vertex_format_supported(screen, format,
1959 PIPE_BIND_VERTEX_BUFFER);
1960 }
1961
1962 if ((usage & PIPE_BIND_LINEAR) &&
1963 !util_format_is_compressed(format) &&
1964 !(usage & PIPE_BIND_DEPTH_STENCIL))
1965 retval |= PIPE_BIND_LINEAR;
1966
1967 return retval == usage;
1968 }
1969
1970 /*
1971 * framebuffer handling
1972 */
1973
1974 static void si_choose_spi_color_formats(struct r600_surface *surf,
1975 unsigned format, unsigned swap,
1976 unsigned ntype, bool is_depth)
1977 {
1978 /* Alpha is needed for alpha-to-coverage.
1979 * Blending may be with or without alpha.
1980 */
1981 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1982 unsigned alpha = 0; /* exports alpha, but may not support blending */
1983 unsigned blend = 0; /* supports blending, but may not export alpha */
1984 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1985
1986 /* Choose the SPI color formats. These are required values for RB+.
1987 * Other chips have multiple choices, though they are not necessarily better.
1988 */
1989 switch (format) {
1990 case V_028C70_COLOR_5_6_5:
1991 case V_028C70_COLOR_1_5_5_5:
1992 case V_028C70_COLOR_5_5_5_1:
1993 case V_028C70_COLOR_4_4_4_4:
1994 case V_028C70_COLOR_10_11_11:
1995 case V_028C70_COLOR_11_11_10:
1996 case V_028C70_COLOR_8:
1997 case V_028C70_COLOR_8_8:
1998 case V_028C70_COLOR_8_8_8_8:
1999 case V_028C70_COLOR_10_10_10_2:
2000 case V_028C70_COLOR_2_10_10_10:
2001 if (ntype == V_028C70_NUMBER_UINT)
2002 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2003 else if (ntype == V_028C70_NUMBER_SINT)
2004 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2005 else
2006 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2007 break;
2008
2009 case V_028C70_COLOR_16:
2010 case V_028C70_COLOR_16_16:
2011 case V_028C70_COLOR_16_16_16_16:
2012 if (ntype == V_028C70_NUMBER_UNORM ||
2013 ntype == V_028C70_NUMBER_SNORM) {
2014 /* UNORM16 and SNORM16 don't support blending */
2015 if (ntype == V_028C70_NUMBER_UNORM)
2016 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2017 else
2018 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2019
2020 /* Use 32 bits per channel for blending. */
2021 if (format == V_028C70_COLOR_16) {
2022 if (swap == V_028C70_SWAP_STD) { /* R */
2023 blend = V_028714_SPI_SHADER_32_R;
2024 blend_alpha = V_028714_SPI_SHADER_32_AR;
2025 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2026 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2027 else
2028 assert(0);
2029 } else if (format == V_028C70_COLOR_16_16) {
2030 if (swap == V_028C70_SWAP_STD) { /* RG */
2031 blend = V_028714_SPI_SHADER_32_GR;
2032 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2033 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2034 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2035 else
2036 assert(0);
2037 } else /* 16_16_16_16 */
2038 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2039 } else if (ntype == V_028C70_NUMBER_UINT)
2040 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2041 else if (ntype == V_028C70_NUMBER_SINT)
2042 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2043 else if (ntype == V_028C70_NUMBER_FLOAT)
2044 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2045 else
2046 assert(0);
2047 break;
2048
2049 case V_028C70_COLOR_32:
2050 if (swap == V_028C70_SWAP_STD) { /* R */
2051 blend = normal = V_028714_SPI_SHADER_32_R;
2052 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2053 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2054 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2055 else
2056 assert(0);
2057 break;
2058
2059 case V_028C70_COLOR_32_32:
2060 if (swap == V_028C70_SWAP_STD) { /* RG */
2061 blend = normal = V_028714_SPI_SHADER_32_GR;
2062 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2063 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2064 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2065 else
2066 assert(0);
2067 break;
2068
2069 case V_028C70_COLOR_32_32_32_32:
2070 case V_028C70_COLOR_8_24:
2071 case V_028C70_COLOR_24_8:
2072 case V_028C70_COLOR_X24_8_32_FLOAT:
2073 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2074 break;
2075
2076 default:
2077 assert(0);
2078 return;
2079 }
2080
2081 /* The DB->CB copy needs 32_ABGR. */
2082 if (is_depth)
2083 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2084
2085 surf->spi_shader_col_format = normal;
2086 surf->spi_shader_col_format_alpha = alpha;
2087 surf->spi_shader_col_format_blend = blend;
2088 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2089 }
2090
2091 static void si_initialize_color_surface(struct si_context *sctx,
2092 struct r600_surface *surf)
2093 {
2094 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2095 unsigned color_info, color_attrib, color_view;
2096 unsigned format, swap, ntype, endian;
2097 const struct util_format_description *desc;
2098 int i;
2099 unsigned blend_clamp = 0, blend_bypass = 0;
2100
2101 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2102 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2103
2104 desc = util_format_description(surf->base.format);
2105 for (i = 0; i < 4; i++) {
2106 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2107 break;
2108 }
2109 }
2110 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2111 ntype = V_028C70_NUMBER_FLOAT;
2112 } else {
2113 ntype = V_028C70_NUMBER_UNORM;
2114 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2115 ntype = V_028C70_NUMBER_SRGB;
2116 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2117 if (desc->channel[i].pure_integer) {
2118 ntype = V_028C70_NUMBER_SINT;
2119 } else {
2120 assert(desc->channel[i].normalized);
2121 ntype = V_028C70_NUMBER_SNORM;
2122 }
2123 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2124 if (desc->channel[i].pure_integer) {
2125 ntype = V_028C70_NUMBER_UINT;
2126 } else {
2127 assert(desc->channel[i].normalized);
2128 ntype = V_028C70_NUMBER_UNORM;
2129 }
2130 }
2131 }
2132
2133 format = si_translate_colorformat(surf->base.format);
2134 if (format == V_028C70_COLOR_INVALID) {
2135 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2136 }
2137 assert(format != V_028C70_COLOR_INVALID);
2138 swap = r600_translate_colorswap(surf->base.format, false);
2139 endian = si_colorformat_endian_swap(format);
2140
2141 /* blend clamp should be set for all NORM/SRGB types */
2142 if (ntype == V_028C70_NUMBER_UNORM ||
2143 ntype == V_028C70_NUMBER_SNORM ||
2144 ntype == V_028C70_NUMBER_SRGB)
2145 blend_clamp = 1;
2146
2147 /* set blend bypass according to docs if SINT/UINT or
2148 8/24 COLOR variants */
2149 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2150 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2151 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2152 blend_clamp = 0;
2153 blend_bypass = 1;
2154 }
2155
2156 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2157 if (format == V_028C70_COLOR_8 ||
2158 format == V_028C70_COLOR_8_8 ||
2159 format == V_028C70_COLOR_8_8_8_8)
2160 surf->color_is_int8 = true;
2161 else if (format == V_028C70_COLOR_10_10_10_2 ||
2162 format == V_028C70_COLOR_2_10_10_10)
2163 surf->color_is_int10 = true;
2164 }
2165
2166 color_info = S_028C70_FORMAT(format) |
2167 S_028C70_COMP_SWAP(swap) |
2168 S_028C70_BLEND_CLAMP(blend_clamp) |
2169 S_028C70_BLEND_BYPASS(blend_bypass) |
2170 S_028C70_SIMPLE_FLOAT(1) |
2171 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2172 ntype != V_028C70_NUMBER_SNORM &&
2173 ntype != V_028C70_NUMBER_SRGB &&
2174 format != V_028C70_COLOR_8_24 &&
2175 format != V_028C70_COLOR_24_8) |
2176 S_028C70_NUMBER_TYPE(ntype) |
2177 S_028C70_ENDIAN(endian);
2178
2179 /* Intensity is implemented as Red, so treat it that way. */
2180 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2181 util_format_is_intensity(surf->base.format));
2182
2183 if (rtex->resource.b.b.nr_samples > 1) {
2184 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2185
2186 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2187 S_028C74_NUM_FRAGMENTS(log_samples);
2188
2189 if (rtex->fmask.size) {
2190 color_info |= S_028C70_COMPRESSION(1);
2191 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2192
2193 if (sctx->b.chip_class == SI) {
2194 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2195 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2196 }
2197 }
2198 }
2199
2200 surf->cb_color_view = color_view;
2201 surf->cb_color_info = color_info;
2202 surf->cb_color_attrib = color_attrib;
2203
2204 if (sctx->b.chip_class >= VI) {
2205 unsigned max_uncompressed_block_size = 2;
2206
2207 if (rtex->resource.b.b.nr_samples > 1) {
2208 if (rtex->surface.bpe == 1)
2209 max_uncompressed_block_size = 0;
2210 else if (rtex->surface.bpe == 2)
2211 max_uncompressed_block_size = 1;
2212 }
2213
2214 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2215 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2216 }
2217
2218 /* This must be set for fast clear to work without FMASK. */
2219 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2220 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2221 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2222 }
2223
2224 if (sctx->b.chip_class >= GFX9) {
2225 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2226
2227 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2228 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2229 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2230 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2231 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2232 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2233 }
2234
2235 /* Determine pixel shader export format */
2236 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2237
2238 surf->color_initialized = true;
2239 }
2240
2241 static void si_init_depth_surface(struct si_context *sctx,
2242 struct r600_surface *surf)
2243 {
2244 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2245 unsigned level = surf->base.u.tex.level;
2246 unsigned format, stencil_format;
2247 uint32_t z_info, s_info;
2248
2249 format = si_translate_dbformat(rtex->db_render_format);
2250 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2251 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2252
2253 assert(format != V_028040_Z_INVALID);
2254 if (format == V_028040_Z_INVALID)
2255 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2256
2257 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2258 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2259 surf->db_htile_data_base = 0;
2260 surf->db_htile_surface = 0;
2261
2262 if (sctx->b.chip_class >= GFX9) {
2263 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2264 surf->db_stencil_base = (rtex->resource.gpu_address +
2265 rtex->surface.u.gfx9.stencil_offset) >> 8;
2266 z_info = S_028038_FORMAT(format) |
2267 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2268 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2269 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2270 s_info = S_02803C_FORMAT(stencil_format) |
2271 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2272 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2273 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2274 surf->db_depth_view |= S_028008_MIPID(level);
2275 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2276 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2277
2278 /* Only use HTILE for the first level. */
2279 if (rtex->htile_buffer && !level) {
2280 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2281 S_028038_ALLOW_EXPCLEAR(1);
2282
2283 if (rtex->tc_compatible_htile) {
2284 unsigned max_zplanes = 4;
2285
2286 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2287 rtex->resource.b.b.nr_samples > 1)
2288 max_zplanes = 2;
2289
2290 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2291 S_028038_ITERATE_FLUSH(1);
2292 s_info |= S_02803C_ITERATE_FLUSH(1);
2293 }
2294
2295 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2296 /* Stencil buffer workaround ported from the SI-CI-VI code.
2297 * See that for explanation.
2298 */
2299 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2300 } else {
2301 /* Use all HTILE for depth if there's no stencil. */
2302 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2303 }
2304
2305 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2306 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2307 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2308 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2309 }
2310 } else {
2311 /* SI-CI-VI */
2312 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2313
2314 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2315
2316 surf->db_depth_base = (rtex->resource.gpu_address +
2317 rtex->surface.u.legacy.level[level].offset) >> 8;
2318 surf->db_stencil_base = (rtex->resource.gpu_address +
2319 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2320
2321 z_info = S_028040_FORMAT(format) |
2322 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2323 s_info = S_028044_FORMAT(stencil_format);
2324 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2325
2326 if (sctx->b.chip_class >= CIK) {
2327 struct radeon_info *info = &sctx->screen->b.info;
2328 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2329 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2330 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2331 unsigned tile_mode = info->si_tile_mode_array[index];
2332 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2333 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2334
2335 surf->db_depth_info |=
2336 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2337 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2338 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2339 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2340 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2341 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2342 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2343 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2344 } else {
2345 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2346 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2347 tile_mode_index = si_tile_mode_index(rtex, level, true);
2348 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2349 }
2350
2351 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2352 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2353 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2354 levelinfo->nblk_y) / 64 - 1);
2355
2356 /* Only use HTILE for the first level. */
2357 if (rtex->htile_buffer && !level) {
2358 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2359 S_028040_ALLOW_EXPCLEAR(1);
2360
2361 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2362 /* Workaround: For a not yet understood reason, the
2363 * combination of MSAA, fast stencil clear and stencil
2364 * decompress messes with subsequent stencil buffer
2365 * uses. Problem was reproduced on Verde, Bonaire,
2366 * Tonga, and Carrizo.
2367 *
2368 * Disabling EXPCLEAR works around the problem.
2369 *
2370 * Check piglit's arb_texture_multisample-stencil-clear
2371 * test if you want to try changing this.
2372 */
2373 if (rtex->resource.b.b.nr_samples <= 1)
2374 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2375 } else if (!rtex->tc_compatible_htile) {
2376 /* Use all of the htile_buffer for depth if there's no stencil.
2377 * This must not be set when TC-compatible HTILE is enabled
2378 * due to a hw bug.
2379 */
2380 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2381 }
2382
2383 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2384 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2385
2386 if (rtex->tc_compatible_htile) {
2387 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2388
2389 if (rtex->resource.b.b.nr_samples <= 1)
2390 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2391 else if (rtex->resource.b.b.nr_samples <= 4)
2392 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2393 else
2394 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2395 }
2396 }
2397 }
2398
2399 surf->db_z_info = z_info;
2400 surf->db_stencil_info = s_info;
2401
2402 surf->depth_initialized = true;
2403 }
2404
2405 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2406 {
2407 for (int i = 0; i < state->nr_cbufs; ++i) {
2408 struct r600_surface *surf = NULL;
2409 struct r600_texture *rtex;
2410
2411 if (!state->cbufs[i])
2412 continue;
2413 surf = (struct r600_surface*)state->cbufs[i];
2414 rtex = (struct r600_texture*)surf->base.texture;
2415
2416 p_atomic_dec(&rtex->framebuffers_bound);
2417 }
2418 }
2419
2420 static void si_set_framebuffer_state(struct pipe_context *ctx,
2421 const struct pipe_framebuffer_state *state)
2422 {
2423 struct si_context *sctx = (struct si_context *)ctx;
2424 struct pipe_constant_buffer constbuf = {0};
2425 struct r600_surface *surf = NULL;
2426 struct r600_texture *rtex;
2427 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2428 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2429 int i;
2430
2431 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2432 if (!sctx->framebuffer.state.cbufs[i])
2433 continue;
2434
2435 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2436 if (rtex->dcc_gather_statistics)
2437 vi_separate_dcc_stop_query(ctx, rtex);
2438 }
2439
2440 /* Only flush TC when changing the framebuffer state, because
2441 * the only client not using TC that can change textures is
2442 * the framebuffer.
2443 *
2444 * Flush all CB and DB caches here because all buffers can be used
2445 * for write by both TC (with shader image stores) and CB/DB.
2446 */
2447 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2448 SI_CONTEXT_INV_GLOBAL_L2 |
2449 SI_CONTEXT_FLUSH_AND_INV_CB |
2450 SI_CONTEXT_FLUSH_AND_INV_DB |
2451 SI_CONTEXT_CS_PARTIAL_FLUSH;
2452
2453 /* Take the maximum of the old and new count. If the new count is lower,
2454 * dirtying is needed to disable the unbound colorbuffers.
2455 */
2456 sctx->framebuffer.dirty_cbufs |=
2457 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2458 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2459
2460 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2461 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2462
2463 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2464 sctx->framebuffer.spi_shader_col_format = 0;
2465 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2466 sctx->framebuffer.spi_shader_col_format_blend = 0;
2467 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2468 sctx->framebuffer.color_is_int8 = 0;
2469 sctx->framebuffer.color_is_int10 = 0;
2470
2471 sctx->framebuffer.compressed_cb_mask = 0;
2472 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2473 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2474 sctx->framebuffer.any_dst_linear = false;
2475
2476 for (i = 0; i < state->nr_cbufs; i++) {
2477 if (!state->cbufs[i])
2478 continue;
2479
2480 surf = (struct r600_surface*)state->cbufs[i];
2481 rtex = (struct r600_texture*)surf->base.texture;
2482
2483 if (!surf->color_initialized) {
2484 si_initialize_color_surface(sctx, surf);
2485 }
2486
2487 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2488 sctx->framebuffer.spi_shader_col_format |=
2489 surf->spi_shader_col_format << (i * 4);
2490 sctx->framebuffer.spi_shader_col_format_alpha |=
2491 surf->spi_shader_col_format_alpha << (i * 4);
2492 sctx->framebuffer.spi_shader_col_format_blend |=
2493 surf->spi_shader_col_format_blend << (i * 4);
2494 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2495 surf->spi_shader_col_format_blend_alpha << (i * 4);
2496
2497 if (surf->color_is_int8)
2498 sctx->framebuffer.color_is_int8 |= 1 << i;
2499 if (surf->color_is_int10)
2500 sctx->framebuffer.color_is_int10 |= 1 << i;
2501
2502 if (rtex->fmask.size) {
2503 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2504 }
2505
2506 if (rtex->surface.is_linear)
2507 sctx->framebuffer.any_dst_linear = true;
2508
2509 r600_context_add_resource_size(ctx, surf->base.texture);
2510
2511 p_atomic_inc(&rtex->framebuffers_bound);
2512
2513 if (rtex->dcc_gather_statistics) {
2514 /* Dirty tracking must be enabled for DCC usage analysis. */
2515 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2516 vi_separate_dcc_start_query(ctx, rtex);
2517 }
2518 }
2519
2520 if (state->zsbuf) {
2521 surf = (struct r600_surface*)state->zsbuf;
2522 rtex = (struct r600_texture*)surf->base.texture;
2523
2524 if (!surf->depth_initialized) {
2525 si_init_depth_surface(sctx, surf);
2526 }
2527 r600_context_add_resource_size(ctx, surf->base.texture);
2528 }
2529
2530 si_update_poly_offset_state(sctx);
2531 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2532 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2533
2534 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2535 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2536
2537 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2538 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2539 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2540
2541 /* Set sample locations as fragment shader constants. */
2542 switch (sctx->framebuffer.nr_samples) {
2543 case 1:
2544 constbuf.user_buffer = sctx->b.sample_locations_1x;
2545 break;
2546 case 2:
2547 constbuf.user_buffer = sctx->b.sample_locations_2x;
2548 break;
2549 case 4:
2550 constbuf.user_buffer = sctx->b.sample_locations_4x;
2551 break;
2552 case 8:
2553 constbuf.user_buffer = sctx->b.sample_locations_8x;
2554 break;
2555 case 16:
2556 constbuf.user_buffer = sctx->b.sample_locations_16x;
2557 break;
2558 default:
2559 R600_ERR("Requested an invalid number of samples %i.\n",
2560 sctx->framebuffer.nr_samples);
2561 assert(0);
2562 }
2563 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2564 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2565
2566 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2567 }
2568
2569 sctx->need_check_render_feedback = true;
2570 sctx->do_update_shaders = true;
2571 sctx->framebuffer.do_update_surf_dirtiness = true;
2572 }
2573
2574 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2575 {
2576 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2577 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2578 unsigned i, nr_cbufs = state->nr_cbufs;
2579 struct r600_texture *tex = NULL;
2580 struct r600_surface *cb = NULL;
2581 unsigned cb_color_info = 0;
2582
2583 /* Colorbuffers. */
2584 for (i = 0; i < nr_cbufs; i++) {
2585 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2586 unsigned cb_color_attrib;
2587
2588 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2589 continue;
2590
2591 cb = (struct r600_surface*)state->cbufs[i];
2592 if (!cb) {
2593 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2594 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2595 continue;
2596 }
2597
2598 tex = (struct r600_texture *)cb->base.texture;
2599 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2600 &tex->resource, RADEON_USAGE_READWRITE,
2601 tex->resource.b.b.nr_samples > 1 ?
2602 RADEON_PRIO_COLOR_BUFFER_MSAA :
2603 RADEON_PRIO_COLOR_BUFFER);
2604
2605 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2606 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2607 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2608 RADEON_PRIO_CMASK);
2609 }
2610
2611 if (tex->dcc_separate_buffer)
2612 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2613 tex->dcc_separate_buffer,
2614 RADEON_USAGE_READWRITE,
2615 RADEON_PRIO_DCC);
2616
2617 /* Compute mutable surface parameters. */
2618 cb_color_base = tex->resource.gpu_address >> 8;
2619 cb_color_fmask = cb_color_base;
2620 cb_dcc_base = 0;
2621 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2622 cb_color_attrib = cb->cb_color_attrib;
2623
2624 if (tex->fmask.size)
2625 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2626
2627 /* Set up DCC. */
2628 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2629 bool is_msaa_resolve_dst = state->cbufs[0] &&
2630 state->cbufs[0]->texture->nr_samples > 1 &&
2631 state->cbufs[1] == &cb->base &&
2632 state->cbufs[1]->texture->nr_samples <= 1;
2633
2634 if (!is_msaa_resolve_dst)
2635 cb_color_info |= S_028C70_DCC_ENABLE(1);
2636
2637 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2638 tex->dcc_offset) >> 8;
2639 }
2640
2641 if (sctx->b.chip_class >= GFX9) {
2642 struct gfx9_surf_meta_flags meta;
2643
2644 if (tex->dcc_offset)
2645 meta = tex->surface.u.gfx9.dcc;
2646 else
2647 meta = tex->surface.u.gfx9.cmask;
2648
2649 /* Set mutable surface parameters. */
2650 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2651 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2652 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2653 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2654
2655 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2656 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2657 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2658 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2659 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2660 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2661 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2662 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2663 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2664 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2665 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2666 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2667 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2668 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2669 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2670 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2671
2672 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2673 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2674 } else {
2675 /* Compute mutable surface parameters (SI-CI-VI). */
2676 const struct legacy_surf_level *level_info =
2677 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2678 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2679 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2680
2681 cb_color_base += level_info->offset >> 8;
2682 if (cb_dcc_base)
2683 cb_dcc_base += level_info->dcc_offset >> 8;
2684
2685 pitch_tile_max = level_info->nblk_x / 8 - 1;
2686 slice_tile_max = level_info->nblk_x *
2687 level_info->nblk_y / 64 - 1;
2688 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2689
2690 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2691 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2692 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2693
2694 if (tex->fmask.size) {
2695 if (sctx->b.chip_class >= CIK)
2696 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2697 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2698 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2699 } else {
2700 /* This must be set for fast clear to work without FMASK. */
2701 if (sctx->b.chip_class >= CIK)
2702 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2703 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2704 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2705 }
2706
2707 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2708 sctx->b.chip_class >= VI ? 14 : 13);
2709 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2710 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2711 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2712 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2713 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2714 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2715 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2716 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2717 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2718 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2719 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2720 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2721 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2722
2723 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2724 radeon_emit(cs, cb_dcc_base);
2725 }
2726 }
2727 for (; i < 8 ; i++)
2728 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2729 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2730
2731 /* ZS buffer. */
2732 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2733 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2734 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2735
2736 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2737 &rtex->resource, RADEON_USAGE_READWRITE,
2738 zb->base.texture->nr_samples > 1 ?
2739 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2740 RADEON_PRIO_DEPTH_BUFFER);
2741
2742 if (zb->db_htile_data_base) {
2743 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2744 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2745 RADEON_PRIO_HTILE);
2746 }
2747
2748 if (sctx->b.chip_class >= GFX9) {
2749 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2750 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2751 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2752 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2753
2754 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2755 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2756 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2757 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2758 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2759 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2760 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2761 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2762 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2763 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2764 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2765 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2766
2767 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2768 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2769 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2770 } else {
2771 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2772
2773 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2774 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2775 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2776 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2777 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2778 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2779 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2780 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2781 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2782 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2783 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2784 }
2785
2786 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2787 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2788 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2789
2790 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2791 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2792 } else if (sctx->framebuffer.dirty_zsbuf) {
2793 if (sctx->b.chip_class >= GFX9)
2794 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2795 else
2796 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2797
2798 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2799 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2800 }
2801
2802 /* Framebuffer dimensions. */
2803 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2804 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2805 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2806
2807 if (sctx->b.chip_class >= GFX9) {
2808 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2809 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2810 }
2811
2812 sctx->framebuffer.dirty_cbufs = 0;
2813 sctx->framebuffer.dirty_zsbuf = false;
2814 }
2815
2816 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2817 struct r600_atom *atom)
2818 {
2819 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2820 unsigned nr_samples = sctx->framebuffer.nr_samples;
2821
2822 /* Smoothing (only possible with nr_samples == 1) uses the same
2823 * sample locations as the MSAA it simulates.
2824 */
2825 if (nr_samples <= 1 && sctx->smoothing_enabled)
2826 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2827
2828 /* On Polaris, the small primitive filter uses the sample locations
2829 * even when MSAA is off, so we need to make sure they're set to 0.
2830 */
2831 if (sctx->b.family >= CHIP_POLARIS10)
2832 nr_samples = MAX2(nr_samples, 1);
2833
2834 if (nr_samples >= 1 &&
2835 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2836 sctx->msaa_sample_locs.nr_samples = nr_samples;
2837 cayman_emit_msaa_sample_locs(cs, nr_samples);
2838 }
2839
2840 if (sctx->b.family >= CHIP_POLARIS10) {
2841 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2842 unsigned small_prim_filter_cntl =
2843 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2844 S_028830_LINE_FILTER_DISABLE(sctx->b.chip_class == VI); /* line bug */
2845
2846 /* The alternative of setting sample locations to 0 would
2847 * require a DB flush to avoid Z errors, see
2848 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2849 */
2850 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2851 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2852
2853 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2854 small_prim_filter_cntl);
2855 }
2856 }
2857
2858 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2859 {
2860 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2861 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2862 /* 33% faster rendering to linear color buffers */
2863 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2864 unsigned sc_mode_cntl_1 =
2865 S_028A4C_WALK_SIZE(dst_is_linear) |
2866 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2867 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2868 /* always 1: */
2869 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2870 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2871 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2872 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2873 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2874 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2875
2876 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2877 sctx->ps_iter_samples,
2878 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2879 sc_mode_cntl_1);
2880 }
2881
2882 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2883 {
2884 struct si_context *sctx = (struct si_context *)ctx;
2885
2886 if (sctx->ps_iter_samples == min_samples)
2887 return;
2888
2889 sctx->ps_iter_samples = min_samples;
2890 sctx->do_update_shaders = true;
2891
2892 if (sctx->framebuffer.nr_samples > 1)
2893 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2894 }
2895
2896 /*
2897 * Samplers
2898 */
2899
2900 /**
2901 * Build the sampler view descriptor for a buffer texture.
2902 * @param state 256-bit descriptor; only the high 128 bits are filled in
2903 */
2904 void
2905 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2906 enum pipe_format format,
2907 unsigned offset, unsigned size,
2908 uint32_t *state)
2909 {
2910 const struct util_format_description *desc;
2911 int first_non_void;
2912 unsigned stride;
2913 unsigned num_records;
2914 unsigned num_format, data_format;
2915
2916 desc = util_format_description(format);
2917 first_non_void = util_format_get_first_non_void_channel(format);
2918 stride = desc->block.bits / 8;
2919 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2920 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2921
2922 num_records = size / stride;
2923 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2924
2925 if (screen->b.chip_class == VI)
2926 num_records *= stride;
2927
2928 state[4] = 0;
2929 state[5] = S_008F04_STRIDE(stride);
2930 state[6] = num_records;
2931 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2932 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2933 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2934 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2935 S_008F0C_NUM_FORMAT(num_format) |
2936 S_008F0C_DATA_FORMAT(data_format);
2937 }
2938
2939 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
2940 {
2941 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2942
2943 if (swizzle[3] == PIPE_SWIZZLE_X) {
2944 /* For the pre-defined border color values (white, opaque
2945 * black, transparent black), the only thing that matters is
2946 * that the alpha channel winds up in the correct place
2947 * (because the RGB channels are all the same) so either of
2948 * these enumerations will work.
2949 */
2950 if (swizzle[2] == PIPE_SWIZZLE_Y)
2951 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
2952 else
2953 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
2954 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
2955 if (swizzle[1] == PIPE_SWIZZLE_Y)
2956 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2957 else
2958 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
2959 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
2960 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
2961 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
2962 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
2963 }
2964
2965 return bc_swizzle;
2966 }
2967
2968 /**
2969 * Build the sampler view descriptor for a texture.
2970 */
2971 void
2972 si_make_texture_descriptor(struct si_screen *screen,
2973 struct r600_texture *tex,
2974 bool sampler,
2975 enum pipe_texture_target target,
2976 enum pipe_format pipe_format,
2977 const unsigned char state_swizzle[4],
2978 unsigned first_level, unsigned last_level,
2979 unsigned first_layer, unsigned last_layer,
2980 unsigned width, unsigned height, unsigned depth,
2981 uint32_t *state,
2982 uint32_t *fmask_state)
2983 {
2984 struct pipe_resource *res = &tex->resource.b.b;
2985 const struct util_format_description *base_desc, *desc;
2986 unsigned char swizzle[4];
2987 int first_non_void;
2988 unsigned num_format, data_format, type;
2989 uint64_t va;
2990
2991 desc = util_format_description(pipe_format);
2992 base_desc = util_format_description(res->format);
2993
2994 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2995 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2996 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2997 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
2998
2999 switch (pipe_format) {
3000 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3001 case PIPE_FORMAT_X32_S8X24_UINT:
3002 case PIPE_FORMAT_X8Z24_UNORM:
3003 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3004 break;
3005 case PIPE_FORMAT_X24S8_UINT:
3006 /*
3007 * X24S8 is implemented as an 8_8_8_8 data format, to
3008 * fix texture gathers. This affects at least
3009 * GL45-CTS.texture_cube_map_array.sampling on VI.
3010 */
3011 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3012 break;
3013 default:
3014 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3015 }
3016 } else {
3017 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3018 }
3019
3020 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3021
3022 switch (pipe_format) {
3023 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3024 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3025 break;
3026 default:
3027 if (first_non_void < 0) {
3028 if (util_format_is_compressed(pipe_format)) {
3029 switch (pipe_format) {
3030 case PIPE_FORMAT_DXT1_SRGB:
3031 case PIPE_FORMAT_DXT1_SRGBA:
3032 case PIPE_FORMAT_DXT3_SRGBA:
3033 case PIPE_FORMAT_DXT5_SRGBA:
3034 case PIPE_FORMAT_BPTC_SRGBA:
3035 case PIPE_FORMAT_ETC2_SRGB8:
3036 case PIPE_FORMAT_ETC2_SRGB8A1:
3037 case PIPE_FORMAT_ETC2_SRGBA8:
3038 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3039 break;
3040 case PIPE_FORMAT_RGTC1_SNORM:
3041 case PIPE_FORMAT_LATC1_SNORM:
3042 case PIPE_FORMAT_RGTC2_SNORM:
3043 case PIPE_FORMAT_LATC2_SNORM:
3044 case PIPE_FORMAT_ETC2_R11_SNORM:
3045 case PIPE_FORMAT_ETC2_RG11_SNORM:
3046 /* implies float, so use SNORM/UNORM to determine
3047 whether data is signed or not */
3048 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3049 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3050 break;
3051 default:
3052 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3053 break;
3054 }
3055 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3056 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3057 } else {
3058 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3059 }
3060 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3061 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3062 } else {
3063 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3064
3065 switch (desc->channel[first_non_void].type) {
3066 case UTIL_FORMAT_TYPE_FLOAT:
3067 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3068 break;
3069 case UTIL_FORMAT_TYPE_SIGNED:
3070 if (desc->channel[first_non_void].normalized)
3071 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3072 else if (desc->channel[first_non_void].pure_integer)
3073 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3074 else
3075 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3076 break;
3077 case UTIL_FORMAT_TYPE_UNSIGNED:
3078 if (desc->channel[first_non_void].normalized)
3079 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3080 else if (desc->channel[first_non_void].pure_integer)
3081 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3082 else
3083 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3084 }
3085 }
3086 }
3087
3088 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3089 if (data_format == ~0) {
3090 data_format = 0;
3091 }
3092
3093 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3094 if (screen->b.chip_class >= GFX9 &&
3095 util_format_has_depth(desc) &&
3096 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3097 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3098 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3099 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3100 }
3101
3102 if (!sampler &&
3103 (res->target == PIPE_TEXTURE_CUBE ||
3104 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3105 res->target == PIPE_TEXTURE_3D)) {
3106 /* For the purpose of shader images, treat cube maps and 3D
3107 * textures as 2D arrays. For 3D textures, the address
3108 * calculations for mipmaps are different, so we rely on the
3109 * caller to effectively disable mipmaps.
3110 */
3111 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3112
3113 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3114 } else {
3115 type = si_tex_dim(screen, tex, target, res->nr_samples);
3116 }
3117
3118 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3119 height = 1;
3120 depth = res->array_size;
3121 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3122 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3123 if (sampler || res->target != PIPE_TEXTURE_3D)
3124 depth = res->array_size;
3125 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3126 depth = res->array_size / 6;
3127
3128 state[0] = 0;
3129 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3130 S_008F14_NUM_FORMAT_GFX6(num_format));
3131 state[2] = (S_008F18_WIDTH(width - 1) |
3132 S_008F18_HEIGHT(height - 1) |
3133 S_008F18_PERF_MOD(4));
3134 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3135 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3136 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3137 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3138 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3139 0 : first_level) |
3140 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3141 util_logbase2(res->nr_samples) :
3142 last_level) |
3143 S_008F1C_TYPE(type));
3144 state[4] = 0;
3145 state[5] = S_008F24_BASE_ARRAY(first_layer);
3146 state[6] = 0;
3147 state[7] = 0;
3148
3149 if (screen->b.chip_class >= GFX9) {
3150 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3151
3152 /* Depth is the the last accessible layer on Gfx9.
3153 * The hw doesn't need to know the total number of layers.
3154 */
3155 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3156 state[4] |= S_008F20_DEPTH(depth - 1);
3157 else
3158 state[4] |= S_008F20_DEPTH(last_layer);
3159
3160 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3161 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3162 util_logbase2(res->nr_samples) :
3163 tex->resource.b.b.last_level);
3164 } else {
3165 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3166 state[4] |= S_008F20_DEPTH(depth - 1);
3167 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3168 }
3169
3170 if (tex->dcc_offset) {
3171 unsigned swap = r600_translate_colorswap(pipe_format, false);
3172
3173 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3174 } else {
3175 /* The last dword is unused by hw. The shader uses it to clear
3176 * bits in the first dword of sampler state.
3177 */
3178 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3179 if (first_level == last_level)
3180 state[7] = C_008F30_MAX_ANISO_RATIO;
3181 else
3182 state[7] = 0xffffffff;
3183 }
3184 }
3185
3186 /* Initialize the sampler view for FMASK. */
3187 if (tex->fmask.size) {
3188 uint32_t data_format, num_format;
3189
3190 va = tex->resource.gpu_address + tex->fmask.offset;
3191
3192 if (screen->b.chip_class >= GFX9) {
3193 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3194 switch (res->nr_samples) {
3195 case 2:
3196 num_format = V_008F14_IMG_FMASK_8_2_2;
3197 break;
3198 case 4:
3199 num_format = V_008F14_IMG_FMASK_8_4_4;
3200 break;
3201 case 8:
3202 num_format = V_008F14_IMG_FMASK_32_8_8;
3203 break;
3204 default:
3205 assert(0);
3206 }
3207 } else {
3208 switch (res->nr_samples) {
3209 case 2:
3210 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3211 break;
3212 case 4:
3213 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3214 break;
3215 case 8:
3216 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3217 break;
3218 default:
3219 assert(0);
3220 }
3221 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3222 }
3223
3224 fmask_state[0] = va >> 8;
3225 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3226 S_008F14_DATA_FORMAT_GFX6(data_format) |
3227 S_008F14_NUM_FORMAT_GFX6(num_format);
3228 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3229 S_008F18_HEIGHT(height - 1);
3230 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3231 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3232 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3233 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3234 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3235 fmask_state[4] = 0;
3236 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3237 fmask_state[6] = 0;
3238 fmask_state[7] = 0;
3239
3240 if (screen->b.chip_class >= GFX9) {
3241 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3242 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3243 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3244 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3245 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3246 } else {
3247 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3248 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3249 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3250 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3251 }
3252 }
3253 }
3254
3255 /**
3256 * Create a sampler view.
3257 *
3258 * @param ctx context
3259 * @param texture texture
3260 * @param state sampler view template
3261 * @param width0 width0 override (for compressed textures as int)
3262 * @param height0 height0 override (for compressed textures as int)
3263 * @param force_level set the base address to the level (for compressed textures)
3264 */
3265 struct pipe_sampler_view *
3266 si_create_sampler_view_custom(struct pipe_context *ctx,
3267 struct pipe_resource *texture,
3268 const struct pipe_sampler_view *state,
3269 unsigned width0, unsigned height0,
3270 unsigned force_level)
3271 {
3272 struct si_context *sctx = (struct si_context*)ctx;
3273 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3274 struct r600_texture *tmp = (struct r600_texture*)texture;
3275 unsigned base_level, first_level, last_level;
3276 unsigned char state_swizzle[4];
3277 unsigned height, depth, width;
3278 unsigned last_layer = state->u.tex.last_layer;
3279 enum pipe_format pipe_format;
3280 const struct legacy_surf_level *surflevel;
3281
3282 if (!view)
3283 return NULL;
3284
3285 /* initialize base object */
3286 view->base = *state;
3287 view->base.texture = NULL;
3288 view->base.reference.count = 1;
3289 view->base.context = ctx;
3290
3291 assert(texture);
3292 pipe_resource_reference(&view->base.texture, texture);
3293
3294 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3295 state->format == PIPE_FORMAT_S8X24_UINT ||
3296 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3297 state->format == PIPE_FORMAT_S8_UINT)
3298 view->is_stencil_sampler = true;
3299
3300 /* Buffer resource. */
3301 if (texture->target == PIPE_BUFFER) {
3302 si_make_buffer_descriptor(sctx->screen,
3303 (struct r600_resource *)texture,
3304 state->format,
3305 state->u.buf.offset,
3306 state->u.buf.size,
3307 view->state);
3308 return &view->base;
3309 }
3310
3311 state_swizzle[0] = state->swizzle_r;
3312 state_swizzle[1] = state->swizzle_g;
3313 state_swizzle[2] = state->swizzle_b;
3314 state_swizzle[3] = state->swizzle_a;
3315
3316 base_level = 0;
3317 first_level = state->u.tex.first_level;
3318 last_level = state->u.tex.last_level;
3319 width = width0;
3320 height = height0;
3321 depth = texture->depth0;
3322
3323 if (sctx->b.chip_class <= VI && force_level) {
3324 assert(force_level == first_level &&
3325 force_level == last_level);
3326 base_level = force_level;
3327 first_level = 0;
3328 last_level = 0;
3329 width = u_minify(width, force_level);
3330 height = u_minify(height, force_level);
3331 depth = u_minify(depth, force_level);
3332 }
3333
3334 /* This is not needed if state trackers set last_layer correctly. */
3335 if (state->target == PIPE_TEXTURE_1D ||
3336 state->target == PIPE_TEXTURE_2D ||
3337 state->target == PIPE_TEXTURE_RECT ||
3338 state->target == PIPE_TEXTURE_CUBE)
3339 last_layer = state->u.tex.first_layer;
3340
3341 /* Texturing with separate depth and stencil. */
3342 pipe_format = state->format;
3343
3344 /* Depth/stencil texturing sometimes needs separate texture. */
3345 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3346 if (!tmp->flushed_depth_texture &&
3347 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3348 pipe_resource_reference(&view->base.texture, NULL);
3349 FREE(view);
3350 return NULL;
3351 }
3352
3353 assert(tmp->flushed_depth_texture);
3354
3355 /* Override format for the case where the flushed texture
3356 * contains only Z or only S.
3357 */
3358 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3359 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3360
3361 tmp = tmp->flushed_depth_texture;
3362 }
3363
3364 surflevel = tmp->surface.u.legacy.level;
3365
3366 if (tmp->db_compatible) {
3367 if (!view->is_stencil_sampler)
3368 pipe_format = tmp->db_render_format;
3369
3370 switch (pipe_format) {
3371 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3372 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3373 break;
3374 case PIPE_FORMAT_X8Z24_UNORM:
3375 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3376 /* Z24 is always stored like this for DB
3377 * compatibility.
3378 */
3379 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3380 break;
3381 case PIPE_FORMAT_X24S8_UINT:
3382 case PIPE_FORMAT_S8X24_UINT:
3383 case PIPE_FORMAT_X32_S8X24_UINT:
3384 pipe_format = PIPE_FORMAT_S8_UINT;
3385 surflevel = tmp->surface.u.legacy.stencil_level;
3386 break;
3387 default:;
3388 }
3389 }
3390
3391 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3392 state->u.tex.first_level,
3393 state->format);
3394
3395 si_make_texture_descriptor(sctx->screen, tmp, true,
3396 state->target, pipe_format, state_swizzle,
3397 first_level, last_level,
3398 state->u.tex.first_layer, last_layer,
3399 width, height, depth,
3400 view->state, view->fmask_state);
3401
3402 view->base_level_info = &surflevel[base_level];
3403 view->base_level = base_level;
3404 view->block_width = util_format_get_blockwidth(pipe_format);
3405 return &view->base;
3406 }
3407
3408 static struct pipe_sampler_view *
3409 si_create_sampler_view(struct pipe_context *ctx,
3410 struct pipe_resource *texture,
3411 const struct pipe_sampler_view *state)
3412 {
3413 return si_create_sampler_view_custom(ctx, texture, state,
3414 texture ? texture->width0 : 0,
3415 texture ? texture->height0 : 0, 0);
3416 }
3417
3418 static void si_sampler_view_destroy(struct pipe_context *ctx,
3419 struct pipe_sampler_view *state)
3420 {
3421 struct si_sampler_view *view = (struct si_sampler_view *)state;
3422
3423 pipe_resource_reference(&state->texture, NULL);
3424 FREE(view);
3425 }
3426
3427 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3428 {
3429 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3430 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3431 (linear_filter &&
3432 (wrap == PIPE_TEX_WRAP_CLAMP ||
3433 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3434 }
3435
3436 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3437 {
3438 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3439 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3440
3441 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3442 state->border_color.ui[2] || state->border_color.ui[3]) &&
3443 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3444 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3445 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3446 }
3447
3448 static void *si_create_sampler_state(struct pipe_context *ctx,
3449 const struct pipe_sampler_state *state)
3450 {
3451 struct si_context *sctx = (struct si_context *)ctx;
3452 struct r600_common_screen *rscreen = sctx->b.screen;
3453 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3454 unsigned border_color_type, border_color_index = 0;
3455 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3456 : state->max_anisotropy;
3457 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3458
3459 if (!rstate) {
3460 return NULL;
3461 }
3462
3463 if (!sampler_state_needs_border_color(state))
3464 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3465 else if (state->border_color.f[0] == 0 &&
3466 state->border_color.f[1] == 0 &&
3467 state->border_color.f[2] == 0 &&
3468 state->border_color.f[3] == 0)
3469 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3470 else if (state->border_color.f[0] == 0 &&
3471 state->border_color.f[1] == 0 &&
3472 state->border_color.f[2] == 0 &&
3473 state->border_color.f[3] == 1)
3474 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3475 else if (state->border_color.f[0] == 1 &&
3476 state->border_color.f[1] == 1 &&
3477 state->border_color.f[2] == 1 &&
3478 state->border_color.f[3] == 1)
3479 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3480 else {
3481 int i;
3482
3483 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3484
3485 /* Check if the border has been uploaded already. */
3486 for (i = 0; i < sctx->border_color_count; i++)
3487 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3488 sizeof(state->border_color)) == 0)
3489 break;
3490
3491 if (i >= SI_MAX_BORDER_COLORS) {
3492 /* Getting 4096 unique border colors is very unlikely. */
3493 fprintf(stderr, "radeonsi: The border color table is full. "
3494 "Any new border colors will be just black. "
3495 "Please file a bug.\n");
3496 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3497 } else {
3498 if (i == sctx->border_color_count) {
3499 /* Upload a new border color. */
3500 memcpy(&sctx->border_color_table[i], &state->border_color,
3501 sizeof(state->border_color));
3502 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3503 &state->border_color,
3504 sizeof(state->border_color));
3505 sctx->border_color_count++;
3506 }
3507
3508 border_color_index = i;
3509 }
3510 }
3511
3512 #ifdef DEBUG
3513 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3514 #endif
3515 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3516 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3517 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3518 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3519 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3520 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3521 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3522 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3523 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3524 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3525 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3526 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3527 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3528 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3529 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3530 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3531 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3532 S_008F38_MIP_POINT_PRECLAMP(1) |
3533 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3534 S_008F38_FILTER_PREC_FIX(1) |
3535 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3536 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3537 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3538 return rstate;
3539 }
3540
3541 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3542 {
3543 struct si_context *sctx = (struct si_context *)ctx;
3544
3545 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3546 return;
3547
3548 sctx->sample_mask.sample_mask = sample_mask;
3549 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3550 }
3551
3552 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3553 {
3554 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3555 unsigned mask = sctx->sample_mask.sample_mask;
3556
3557 /* Needed for line and polygon smoothing as well as for the Polaris
3558 * small primitive filter. We expect the state tracker to take care of
3559 * this for us.
3560 */
3561 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3562 (mask & 1 && sctx->blitter->running));
3563
3564 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3565 radeon_emit(cs, mask | (mask << 16));
3566 radeon_emit(cs, mask | (mask << 16));
3567 }
3568
3569 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3570 {
3571 #ifdef DEBUG
3572 struct si_sampler_state *s = state;
3573
3574 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3575 s->magic = 0;
3576 #endif
3577 free(state);
3578 }
3579
3580 /*
3581 * Vertex elements & buffers
3582 */
3583
3584 static void *si_create_vertex_elements(struct pipe_context *ctx,
3585 unsigned count,
3586 const struct pipe_vertex_element *elements)
3587 {
3588 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3589 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3590 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3591 int i;
3592
3593 assert(count <= SI_MAX_ATTRIBS);
3594 if (!v)
3595 return NULL;
3596
3597 v->count = count;
3598 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3599
3600 for (i = 0; i < count; ++i) {
3601 const struct util_format_description *desc;
3602 const struct util_format_channel_description *channel;
3603 unsigned data_format, num_format;
3604 int first_non_void;
3605 unsigned vbo_index = elements[i].vertex_buffer_index;
3606 unsigned char swizzle[4];
3607
3608 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3609 FREE(v);
3610 return NULL;
3611 }
3612
3613 if (!used[vbo_index]) {
3614 v->first_vb_use_mask |= 1 << i;
3615 used[vbo_index] = true;
3616 }
3617
3618 desc = util_format_description(elements[i].src_format);
3619 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3620 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3621 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3622 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3623 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3624
3625 v->format_size[i] = desc->block.bits / 8;
3626
3627 /* The hardware always treats the 2-bit alpha channel as
3628 * unsigned, so a shader workaround is needed. The affected
3629 * chips are VI and older except Stoney (GFX8.1).
3630 */
3631 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3632 sscreen->b.chip_class <= VI &&
3633 sscreen->b.family != CHIP_STONEY) {
3634 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3635 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3636 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3637 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3638 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3639 /* This isn't actually used in OpenGL. */
3640 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3641 }
3642 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3643 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3644 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3645 else
3646 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3647 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3648 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3649 if (channel->normalized) {
3650 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3651 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3652 else
3653 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3654 } else {
3655 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3656 }
3657 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3658 if (channel->normalized) {
3659 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3660 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3661 else
3662 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3663 } else {
3664 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3665 }
3666 }
3667 } else if (channel && channel->size == 64 &&
3668 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3669 switch (desc->nr_channels) {
3670 case 1:
3671 case 2:
3672 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3673 swizzle[0] = PIPE_SWIZZLE_X;
3674 swizzle[1] = PIPE_SWIZZLE_Y;
3675 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3676 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3677 break;
3678 case 3:
3679 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3680 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3681 swizzle[1] = PIPE_SWIZZLE_Y;
3682 swizzle[2] = PIPE_SWIZZLE_0;
3683 swizzle[3] = PIPE_SWIZZLE_0;
3684 break;
3685 case 4:
3686 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3687 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3688 swizzle[1] = PIPE_SWIZZLE_Y;
3689 swizzle[2] = PIPE_SWIZZLE_Z;
3690 swizzle[3] = PIPE_SWIZZLE_W;
3691 break;
3692 default:
3693 assert(0);
3694 }
3695 } else if (channel && desc->nr_channels == 3) {
3696 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3697
3698 if (channel->size == 8) {
3699 if (channel->pure_integer)
3700 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3701 else
3702 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3703 } else if (channel->size == 16) {
3704 if (channel->pure_integer)
3705 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3706 else
3707 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3708 }
3709 }
3710
3711 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3712 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3713 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3714 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3715 S_008F0C_NUM_FORMAT(num_format) |
3716 S_008F0C_DATA_FORMAT(data_format);
3717 }
3718 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3719
3720 return v;
3721 }
3722
3723 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3724 {
3725 struct si_context *sctx = (struct si_context *)ctx;
3726 struct si_vertex_element *v = (struct si_vertex_element*)state;
3727
3728 sctx->vertex_elements = v;
3729 sctx->vertex_buffers_dirty = true;
3730 sctx->do_update_shaders = true;
3731 }
3732
3733 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3734 {
3735 struct si_context *sctx = (struct si_context *)ctx;
3736
3737 if (sctx->vertex_elements == state)
3738 sctx->vertex_elements = NULL;
3739 FREE(state);
3740 }
3741
3742 static void si_set_vertex_buffers(struct pipe_context *ctx,
3743 unsigned start_slot, unsigned count,
3744 const struct pipe_vertex_buffer *buffers)
3745 {
3746 struct si_context *sctx = (struct si_context *)ctx;
3747 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3748 int i;
3749
3750 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3751
3752 if (buffers) {
3753 for (i = 0; i < count; i++) {
3754 const struct pipe_vertex_buffer *src = buffers + i;
3755 struct pipe_vertex_buffer *dsti = dst + i;
3756
3757 if (unlikely(src->user_buffer)) {
3758 /* Zero-stride attribs only. */
3759 assert(src->stride == 0);
3760
3761 /* Assume that the user_buffer comes from
3762 * gl_current_attrib, which implies it has
3763 * 4 * 8 bytes (for dvec4 attributes).
3764 *
3765 * Use const_uploader to upload into VRAM directly.
3766 */
3767 u_upload_data(sctx->b.b.const_uploader, 0, 32, 32,
3768 src->user_buffer,
3769 &dsti->buffer_offset,
3770 &dsti->buffer);
3771 dsti->stride = 0;
3772 } else {
3773 struct pipe_resource *buf = src->buffer;
3774
3775 pipe_resource_reference(&dsti->buffer, buf);
3776 dsti->buffer_offset = src->buffer_offset;
3777 dsti->stride = src->stride;
3778 r600_context_add_resource_size(ctx, buf);
3779 if (buf)
3780 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3781 }
3782 }
3783 } else {
3784 for (i = 0; i < count; i++) {
3785 pipe_resource_reference(&dst[i].buffer, NULL);
3786 }
3787 }
3788 sctx->vertex_buffers_dirty = true;
3789 }
3790
3791 static void si_set_index_buffer(struct pipe_context *ctx,
3792 const struct pipe_index_buffer *ib)
3793 {
3794 struct si_context *sctx = (struct si_context *)ctx;
3795
3796 if (ib) {
3797 struct pipe_resource *buf = ib->buffer;
3798
3799 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3800 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3801 r600_context_add_resource_size(ctx, buf);
3802 if (buf)
3803 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3804 } else {
3805 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3806 }
3807 }
3808
3809 /*
3810 * Misc
3811 */
3812
3813 static void si_set_tess_state(struct pipe_context *ctx,
3814 const float default_outer_level[4],
3815 const float default_inner_level[2])
3816 {
3817 struct si_context *sctx = (struct si_context *)ctx;
3818 struct pipe_constant_buffer cb;
3819 float array[8];
3820
3821 memcpy(array, default_outer_level, sizeof(float) * 4);
3822 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3823
3824 cb.buffer = NULL;
3825 cb.user_buffer = NULL;
3826 cb.buffer_size = sizeof(array);
3827
3828 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3829 (void*)array, sizeof(array),
3830 &cb.buffer_offset);
3831
3832 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3833 pipe_resource_reference(&cb.buffer, NULL);
3834 }
3835
3836 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3837 {
3838 struct si_context *sctx = (struct si_context *)ctx;
3839
3840 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3841 SI_CONTEXT_INV_GLOBAL_L2 |
3842 SI_CONTEXT_FLUSH_AND_INV_CB;
3843 sctx->framebuffer.do_update_surf_dirtiness = true;
3844 }
3845
3846 /* This only ensures coherency for shader image/buffer stores. */
3847 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3848 {
3849 struct si_context *sctx = (struct si_context *)ctx;
3850
3851 /* Subsequent commands must wait for all shader invocations to
3852 * complete. */
3853 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3854 SI_CONTEXT_CS_PARTIAL_FLUSH;
3855
3856 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3857 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3858 SI_CONTEXT_INV_VMEM_L1;
3859
3860 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3861 PIPE_BARRIER_SHADER_BUFFER |
3862 PIPE_BARRIER_TEXTURE |
3863 PIPE_BARRIER_IMAGE |
3864 PIPE_BARRIER_STREAMOUT_BUFFER |
3865 PIPE_BARRIER_GLOBAL_BUFFER)) {
3866 /* As far as I can tell, L1 contents are written back to L2
3867 * automatically at end of shader, but the contents of other
3868 * L1 caches might still be stale. */
3869 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3870 }
3871
3872 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3873 /* Indices are read through TC L2 since VI.
3874 * L1 isn't used.
3875 */
3876 if (sctx->screen->b.chip_class <= CIK)
3877 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3878 }
3879
3880 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3881 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3882 SI_CONTEXT_FLUSH_AND_INV_DB;
3883
3884 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3885 PIPE_BARRIER_INDIRECT_BUFFER))
3886 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3887 }
3888
3889 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3890 {
3891 struct pipe_blend_state blend;
3892
3893 memset(&blend, 0, sizeof(blend));
3894 blend.independent_blend_enable = true;
3895 blend.rt[0].colormask = 0xf;
3896 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3897 }
3898
3899 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3900 bool include_draw_vbo)
3901 {
3902 si_need_cs_space((struct si_context*)ctx);
3903 }
3904
3905 static void si_init_config(struct si_context *sctx);
3906
3907 void si_init_state_functions(struct si_context *sctx)
3908 {
3909 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3910 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3911 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3912 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3913 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3914
3915 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3916 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3917 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3918 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3919 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3920 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3921 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3922 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3923 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3924 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3925
3926 sctx->b.b.create_blend_state = si_create_blend_state;
3927 sctx->b.b.bind_blend_state = si_bind_blend_state;
3928 sctx->b.b.delete_blend_state = si_delete_blend_state;
3929 sctx->b.b.set_blend_color = si_set_blend_color;
3930
3931 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3932 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3933 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3934
3935 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3936 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3937 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3938
3939 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3940 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3941 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3942 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3943 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3944
3945 sctx->b.b.set_clip_state = si_set_clip_state;
3946 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3947
3948 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3949 sctx->b.b.get_sample_position = cayman_get_sample_position;
3950
3951 sctx->b.b.create_sampler_state = si_create_sampler_state;
3952 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3953
3954 sctx->b.b.create_sampler_view = si_create_sampler_view;
3955 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3956
3957 sctx->b.b.set_sample_mask = si_set_sample_mask;
3958
3959 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3960 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3961 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3962 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3963 sctx->b.b.set_index_buffer = si_set_index_buffer;
3964
3965 sctx->b.b.texture_barrier = si_texture_barrier;
3966 sctx->b.b.memory_barrier = si_memory_barrier;
3967 sctx->b.b.set_min_samples = si_set_min_samples;
3968 sctx->b.b.set_tess_state = si_set_tess_state;
3969
3970 sctx->b.b.set_active_query_state = si_set_active_query_state;
3971 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3972 sctx->b.save_qbo_state = si_save_qbo_state;
3973 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3974
3975 sctx->b.b.draw_vbo = si_draw_vbo;
3976
3977 si_init_config(sctx);
3978 }
3979
3980 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3981 {
3982 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3983 }
3984
3985 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3986 struct r600_texture *rtex,
3987 struct radeon_bo_metadata *md)
3988 {
3989 struct si_screen *sscreen = (struct si_screen*)rscreen;
3990 struct pipe_resource *res = &rtex->resource.b.b;
3991 static const unsigned char swizzle[] = {
3992 PIPE_SWIZZLE_X,
3993 PIPE_SWIZZLE_Y,
3994 PIPE_SWIZZLE_Z,
3995 PIPE_SWIZZLE_W
3996 };
3997 uint32_t desc[8], i;
3998 bool is_array = util_resource_is_array_texture(res);
3999
4000 /* DRM 2.x.x doesn't support this. */
4001 if (rscreen->info.drm_major != 3)
4002 return;
4003
4004 assert(rtex->dcc_separate_buffer == NULL);
4005 assert(rtex->fmask.size == 0);
4006
4007 /* Metadata image format format version 1:
4008 * [0] = 1 (metadata format identifier)
4009 * [1] = (VENDOR_ID << 16) | PCI_ID
4010 * [2:9] = image descriptor for the whole resource
4011 * [2] is always 0, because the base address is cleared
4012 * [9] is the DCC offset bits [39:8] from the beginning of
4013 * the buffer
4014 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4015 */
4016
4017 md->metadata[0] = 1; /* metadata image format version 1 */
4018
4019 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4020 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4021
4022 si_make_texture_descriptor(sscreen, rtex, true,
4023 res->target, res->format,
4024 swizzle, 0, res->last_level, 0,
4025 is_array ? res->array_size - 1 : 0,
4026 res->width0, res->height0, res->depth0,
4027 desc, NULL);
4028
4029 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4030 0, 0, rtex->surface.blk_w, false, desc);
4031
4032 /* Clear the base address and set the relative DCC offset. */
4033 desc[0] = 0;
4034 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4035 desc[7] = rtex->dcc_offset >> 8;
4036
4037 /* Dwords [2:9] contain the image descriptor. */
4038 memcpy(&md->metadata[2], desc, sizeof(desc));
4039
4040 /* Dwords [10:..] contain the mipmap level offsets. */
4041 for (i = 0; i <= res->last_level; i++)
4042 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4043
4044 md->size_metadata = (11 + res->last_level) * 4;
4045 }
4046
4047 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4048 struct r600_texture *rtex,
4049 struct radeon_bo_metadata *md)
4050 {
4051 uint32_t *desc = &md->metadata[2];
4052
4053 if (rscreen->chip_class < VI)
4054 return;
4055
4056 /* Return if DCC is enabled. The texture should be set up with it
4057 * already.
4058 */
4059 if (md->size_metadata >= 11 * 4 &&
4060 md->metadata[0] != 0 &&
4061 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4062 G_008F28_COMPRESSION_EN(desc[6])) {
4063 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4064 return;
4065 }
4066
4067 /* Disable DCC. These are always set by texture_from_handle and must
4068 * be cleared here.
4069 */
4070 rtex->dcc_offset = 0;
4071 }
4072
4073 void si_init_screen_state_functions(struct si_screen *sscreen)
4074 {
4075 sscreen->b.b.is_format_supported = si_is_format_supported;
4076 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4077 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4078 }
4079
4080 static void
4081 si_write_harvested_raster_configs(struct si_context *sctx,
4082 struct si_pm4_state *pm4,
4083 unsigned raster_config,
4084 unsigned raster_config_1)
4085 {
4086 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4087 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4088 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4089 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4090 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4091 unsigned rb_per_se = num_rb / num_se;
4092 unsigned se_mask[4];
4093 unsigned se;
4094
4095 se_mask[0] = ((1 << rb_per_se) - 1);
4096 se_mask[1] = (se_mask[0] << rb_per_se);
4097 se_mask[2] = (se_mask[1] << rb_per_se);
4098 se_mask[3] = (se_mask[2] << rb_per_se);
4099
4100 se_mask[0] &= rb_mask;
4101 se_mask[1] &= rb_mask;
4102 se_mask[2] &= rb_mask;
4103 se_mask[3] &= rb_mask;
4104
4105 assert(num_se == 1 || num_se == 2 || num_se == 4);
4106 assert(sh_per_se == 1 || sh_per_se == 2);
4107 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4108
4109 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4110 * fields are for, so I'm leaving them as their default
4111 * values. */
4112
4113 for (se = 0; se < num_se; se++) {
4114 unsigned raster_config_se = raster_config;
4115 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4116 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4117 int idx = (se / 2) * 2;
4118
4119 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4120 raster_config_se &= C_028350_SE_MAP;
4121
4122 if (!se_mask[idx]) {
4123 raster_config_se |=
4124 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4125 } else {
4126 raster_config_se |=
4127 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4128 }
4129 }
4130
4131 pkr0_mask &= rb_mask;
4132 pkr1_mask &= rb_mask;
4133 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4134 raster_config_se &= C_028350_PKR_MAP;
4135
4136 if (!pkr0_mask) {
4137 raster_config_se |=
4138 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4139 } else {
4140 raster_config_se |=
4141 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4142 }
4143 }
4144
4145 if (rb_per_se >= 2) {
4146 unsigned rb0_mask = 1 << (se * rb_per_se);
4147 unsigned rb1_mask = rb0_mask << 1;
4148
4149 rb0_mask &= rb_mask;
4150 rb1_mask &= rb_mask;
4151 if (!rb0_mask || !rb1_mask) {
4152 raster_config_se &= C_028350_RB_MAP_PKR0;
4153
4154 if (!rb0_mask) {
4155 raster_config_se |=
4156 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4157 } else {
4158 raster_config_se |=
4159 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4160 }
4161 }
4162
4163 if (rb_per_se > 2) {
4164 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4165 rb1_mask = rb0_mask << 1;
4166 rb0_mask &= rb_mask;
4167 rb1_mask &= rb_mask;
4168 if (!rb0_mask || !rb1_mask) {
4169 raster_config_se &= C_028350_RB_MAP_PKR1;
4170
4171 if (!rb0_mask) {
4172 raster_config_se |=
4173 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4174 } else {
4175 raster_config_se |=
4176 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4177 }
4178 }
4179 }
4180 }
4181
4182 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4183 if (sctx->b.chip_class < CIK)
4184 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4185 SE_INDEX(se) | SH_BROADCAST_WRITES |
4186 INSTANCE_BROADCAST_WRITES);
4187 else
4188 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4189 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4190 S_030800_INSTANCE_BROADCAST_WRITES(1));
4191 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4192 }
4193
4194 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4195 if (sctx->b.chip_class < CIK)
4196 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4197 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4198 INSTANCE_BROADCAST_WRITES);
4199 else {
4200 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4201 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4202 S_030800_INSTANCE_BROADCAST_WRITES(1));
4203
4204 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4205 (!se_mask[2] && !se_mask[3]))) {
4206 raster_config_1 &= C_028354_SE_PAIR_MAP;
4207
4208 if (!se_mask[0] && !se_mask[1]) {
4209 raster_config_1 |=
4210 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4211 } else {
4212 raster_config_1 |=
4213 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4214 }
4215 }
4216
4217 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4218 }
4219 }
4220
4221 static void si_init_config(struct si_context *sctx)
4222 {
4223 struct si_screen *sscreen = sctx->screen;
4224 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4225 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4226 unsigned raster_config, raster_config_1;
4227 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4228 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4229
4230 if (!pm4)
4231 return;
4232
4233 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4234 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4235 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4236 si_pm4_cmd_end(pm4, false);
4237
4238 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4239 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4240
4241 /* FIXME calculate these values somehow ??? */
4242 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4243 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4244 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4245
4246 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4247 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4248
4249 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4250 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4251 if (sctx->b.chip_class < CIK)
4252 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4253 S_008A14_CLIP_VTX_REORDER_ENA(1));
4254
4255 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4256 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4257
4258 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4259
4260 switch (sctx->screen->b.family) {
4261 case CHIP_TAHITI:
4262 case CHIP_PITCAIRN:
4263 raster_config = 0x2a00126a;
4264 raster_config_1 = 0x00000000;
4265 break;
4266 case CHIP_VERDE:
4267 raster_config = 0x0000124a;
4268 raster_config_1 = 0x00000000;
4269 break;
4270 case CHIP_OLAND:
4271 raster_config = 0x00000082;
4272 raster_config_1 = 0x00000000;
4273 break;
4274 case CHIP_HAINAN:
4275 raster_config = 0x00000000;
4276 raster_config_1 = 0x00000000;
4277 break;
4278 case CHIP_BONAIRE:
4279 raster_config = 0x16000012;
4280 raster_config_1 = 0x00000000;
4281 break;
4282 case CHIP_HAWAII:
4283 raster_config = 0x3a00161a;
4284 raster_config_1 = 0x0000002e;
4285 break;
4286 case CHIP_FIJI:
4287 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4288 /* old kernels with old tiling config */
4289 raster_config = 0x16000012;
4290 raster_config_1 = 0x0000002a;
4291 } else {
4292 raster_config = 0x3a00161a;
4293 raster_config_1 = 0x0000002e;
4294 }
4295 break;
4296 case CHIP_POLARIS10:
4297 raster_config = 0x16000012;
4298 raster_config_1 = 0x0000002a;
4299 break;
4300 case CHIP_POLARIS11:
4301 case CHIP_POLARIS12:
4302 raster_config = 0x16000012;
4303 raster_config_1 = 0x00000000;
4304 break;
4305 case CHIP_TONGA:
4306 raster_config = 0x16000012;
4307 raster_config_1 = 0x0000002a;
4308 break;
4309 case CHIP_ICELAND:
4310 if (num_rb == 1)
4311 raster_config = 0x00000000;
4312 else
4313 raster_config = 0x00000002;
4314 raster_config_1 = 0x00000000;
4315 break;
4316 case CHIP_CARRIZO:
4317 raster_config = 0x00000002;
4318 raster_config_1 = 0x00000000;
4319 break;
4320 case CHIP_KAVERI:
4321 /* KV should be 0x00000002, but that causes problems with radeon */
4322 raster_config = 0x00000000; /* 0x00000002 */
4323 raster_config_1 = 0x00000000;
4324 break;
4325 case CHIP_KABINI:
4326 case CHIP_MULLINS:
4327 case CHIP_STONEY:
4328 raster_config = 0x00000000;
4329 raster_config_1 = 0x00000000;
4330 break;
4331 default:
4332 if (sctx->b.chip_class <= VI) {
4333 fprintf(stderr,
4334 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4335 raster_config = 0x00000000;
4336 raster_config_1 = 0x00000000;
4337 }
4338 break;
4339 }
4340
4341 if (sctx->b.chip_class <= VI) {
4342 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4343 /* Always use the default config when all backends are enabled
4344 * (or when we failed to determine the enabled backends).
4345 */
4346 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4347 raster_config);
4348 if (sctx->b.chip_class >= CIK)
4349 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4350 raster_config_1);
4351 } else {
4352 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4353 }
4354 }
4355
4356 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4357 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4358 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4359 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4360 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4361 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4362 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4363
4364 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4365 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4366 S_028230_ER_TRI(0xA) |
4367 S_028230_ER_POINT(0xA) |
4368 S_028230_ER_RECT(0xA) |
4369 /* Required by DX10_DIAMOND_TEST_ENA: */
4370 S_028230_ER_LINE_LR(0x1A) |
4371 S_028230_ER_LINE_RL(0x26) |
4372 S_028230_ER_LINE_TB(0xA) |
4373 S_028230_ER_LINE_BT(0xA));
4374 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4375 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4376 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4377 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4378 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4379 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4380 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4381
4382 if (sctx->b.chip_class >= GFX9) {
4383 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4384 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4385 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4386 } else {
4387 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4388 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4389 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4390 }
4391
4392 if (sctx->b.chip_class >= CIK) {
4393 /* If this is 0, Bonaire can hang even if GS isn't being used.
4394 * Other chips are unaffected. These are suboptimal values,
4395 * but we don't use on-chip GS.
4396 */
4397 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4398 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4399 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4400
4401 if (sctx->b.chip_class >= GFX9) {
4402 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4403 } else {
4404 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4405 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4406 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4407 }
4408 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4409
4410 if (sscreen->b.info.num_good_compute_units /
4411 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4412 /* Too few available compute units per SH. Disallowing
4413 * VS to run on CU0 could hurt us more than late VS
4414 * allocation would help.
4415 *
4416 * LATE_ALLOC_VS = 2 is the highest safe number.
4417 */
4418 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4419 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4420 } else {
4421 /* Set LATE_ALLOC_VS == 31. It should be less than
4422 * the number of scratch waves. Limitations:
4423 * - VS can't execute on CU0.
4424 * - If HS writes outputs to LDS, LS can't execute on CU0.
4425 */
4426 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4427 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4428 }
4429
4430 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4431 }
4432
4433 if (sctx->b.chip_class >= VI) {
4434 unsigned vgt_tess_distribution;
4435
4436 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4437 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4438 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4439 if (sctx->b.family < CHIP_POLARIS10)
4440 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4441 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4442
4443 vgt_tess_distribution =
4444 S_028B50_ACCUM_ISOLINE(32) |
4445 S_028B50_ACCUM_TRI(11) |
4446 S_028B50_ACCUM_QUAD(11) |
4447 S_028B50_DONUT_SPLIT(16);
4448
4449 /* Testing with Unigine Heaven extreme tesselation yielded best results
4450 * with TRAP_SPLIT = 3.
4451 */
4452 if (sctx->b.family == CHIP_FIJI ||
4453 sctx->b.family >= CHIP_POLARIS10)
4454 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4455
4456 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4457 } else {
4458 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4459 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4460 }
4461
4462 if (sctx->screen->b.has_rbplus)
4463 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4464
4465 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4466 if (sctx->b.chip_class >= CIK)
4467 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4468 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4469 RADEON_PRIO_BORDER_COLORS);
4470
4471 if (sctx->b.chip_class >= GFX9) {
4472 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
4473 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4474 /* TODO: We can use this to disable RBs for rendering to GART: */
4475 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4476 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4477 /* TODO: Enable the binner: */
4478 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4479 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
4480 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
4481 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4482 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4483 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4484 }
4485
4486 si_pm4_upload_indirect_buffer(sctx, pm4);
4487 sctx->init_config = pm4;
4488 }