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radeonsi: add si_set_rw_buffer to be used for internal descriptors
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 if (!state->rt[j].colormask)
464 continue;
465
466 /* cb_render_state will disable unused ones */
467 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
468
469 if (!state->rt[j].blend_enable) {
470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
471 continue;
472 }
473
474 /* Blending optimizations for Stoney.
475 * These transformations don't change the behavior.
476 *
477 * First, get rid of DST in the blend factors:
478 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
479 */
480 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
481 PIPE_BLENDFACTOR_DST_COLOR,
482 PIPE_BLENDFACTOR_SRC_COLOR);
483 si_blend_remove_dst(&eqA, &srcA, &dstA,
484 PIPE_BLENDFACTOR_DST_COLOR,
485 PIPE_BLENDFACTOR_SRC_COLOR);
486 si_blend_remove_dst(&eqA, &srcA, &dstA,
487 PIPE_BLENDFACTOR_DST_ALPHA,
488 PIPE_BLENDFACTOR_SRC_ALPHA);
489
490 /* Look up the ideal settings from tables. */
491 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
492 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
493 srcA_opt = si_translate_blend_opt_factor(srcA, true);
494 dstA_opt = si_translate_blend_opt_factor(dstA, true);
495
496 /* Handle interdependencies. */
497 if (si_blend_factor_uses_dst(srcRGB))
498 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
499 if (si_blend_factor_uses_dst(srcA))
500 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
501
502 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
503 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
504 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
505 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
507
508 /* Set the final value. */
509 sx_mrt_blend_opt[i] =
510 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
511 S_028760_COLOR_DST_OPT(dstRGB_opt) |
512 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
513 S_028760_ALPHA_SRC_OPT(srcA_opt) |
514 S_028760_ALPHA_DST_OPT(dstA_opt) |
515 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
516
517 /* Set blend state. */
518 blend_cntl |= S_028780_ENABLE(1);
519 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
520 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
521 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
522
523 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
524 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
525 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
526 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
527 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
528 }
529 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
530
531 blend->blend_enable_4bit |= 0xfu << (i * 4);
532
533 /* This is only important for formats without alpha. */
534 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
535 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
536 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
537 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
538 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
539 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
540 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
541 }
542
543 if (blend->cb_target_mask) {
544 color_control |= S_028808_MODE(mode);
545 } else {
546 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
547 }
548
549 if (sctx->b.family == CHIP_STONEY) {
550 for (int i = 0; i < 8; i++)
551 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
552 sx_mrt_blend_opt[i]);
553
554 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
555 if (blend->dual_src_blend || state->logicop_enable ||
556 mode == V_028808_CB_RESOLVE)
557 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
558 }
559
560 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
561 return blend;
562 }
563
564 static void *si_create_blend_state(struct pipe_context *ctx,
565 const struct pipe_blend_state *state)
566 {
567 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
568 }
569
570 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
571 {
572 struct si_context *sctx = (struct si_context *)ctx;
573 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
574 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
575 }
576
577 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
578 {
579 struct si_context *sctx = (struct si_context *)ctx;
580 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
581 }
582
583 static void si_set_blend_color(struct pipe_context *ctx,
584 const struct pipe_blend_color *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587
588 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
589 return;
590
591 sctx->blend_color.state = *state;
592 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
593 }
594
595 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
596 {
597 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
598
599 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
600 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
601 }
602
603 /*
604 * Clipping
605 */
606
607 static void si_set_clip_state(struct pipe_context *ctx,
608 const struct pipe_clip_state *state)
609 {
610 struct si_context *sctx = (struct si_context *)ctx;
611 struct pipe_constant_buffer cb;
612
613 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
614 return;
615
616 sctx->clip_state.state = *state;
617 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
618
619 cb.buffer = NULL;
620 cb.user_buffer = state->ucp;
621 cb.buffer_offset = 0;
622 cb.buffer_size = 4*4*8;
623 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
624 pipe_resource_reference(&cb.buffer, NULL);
625 }
626
627 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
628 {
629 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
630
631 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
632 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
633 }
634
635 #define SIX_BITS 0x3F
636
637 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
638 {
639 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
640 struct tgsi_shader_info *info = si_get_vs_info(sctx);
641 unsigned window_space =
642 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
643 unsigned clipdist_mask =
644 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
645
646 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
647 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
648 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
649 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
650 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
651 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
652 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
653 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
654 info->writes_edgeflag ||
655 info->writes_layer ||
656 info->writes_viewport_index) |
657 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
658 (sctx->queued.named.rasterizer->clip_plane_enable &
659 clipdist_mask));
660 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
661 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
662 (clipdist_mask ? 0 :
663 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
664 S_028810_CLIP_DISABLE(window_space));
665
666 /* reuse needs to be set off if we write oViewport */
667 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
668 S_028AB4_REUSE_OFF(info->writes_viewport_index));
669 }
670
671 /*
672 * inferred state between framebuffer and rasterizer
673 */
674 static void si_update_poly_offset_state(struct si_context *sctx)
675 {
676 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
677
678 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
679 return;
680
681 switch (sctx->framebuffer.state.zsbuf->texture->format) {
682 case PIPE_FORMAT_Z16_UNORM:
683 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
684 break;
685 default: /* 24-bit */
686 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
687 break;
688 case PIPE_FORMAT_Z32_FLOAT:
689 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
690 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
691 break;
692 }
693 }
694
695 /*
696 * Rasterizer
697 */
698
699 static uint32_t si_translate_fill(uint32_t func)
700 {
701 switch(func) {
702 case PIPE_POLYGON_MODE_FILL:
703 return V_028814_X_DRAW_TRIANGLES;
704 case PIPE_POLYGON_MODE_LINE:
705 return V_028814_X_DRAW_LINES;
706 case PIPE_POLYGON_MODE_POINT:
707 return V_028814_X_DRAW_POINTS;
708 default:
709 assert(0);
710 return V_028814_X_DRAW_POINTS;
711 }
712 }
713
714 static void *si_create_rs_state(struct pipe_context *ctx,
715 const struct pipe_rasterizer_state *state)
716 {
717 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
718 struct si_pm4_state *pm4 = &rs->pm4;
719 unsigned tmp, i;
720 float psize_min, psize_max;
721
722 if (!rs) {
723 return NULL;
724 }
725
726 rs->scissor_enable = state->scissor;
727 rs->two_side = state->light_twoside;
728 rs->multisample_enable = state->multisample;
729 rs->force_persample_interp = state->force_persample_interp;
730 rs->clip_plane_enable = state->clip_plane_enable;
731 rs->line_stipple_enable = state->line_stipple_enable;
732 rs->poly_stipple_enable = state->poly_stipple_enable;
733 rs->line_smooth = state->line_smooth;
734 rs->poly_smooth = state->poly_smooth;
735 rs->uses_poly_offset = state->offset_point || state->offset_line ||
736 state->offset_tri;
737 rs->clamp_fragment_color = state->clamp_fragment_color;
738 rs->flatshade = state->flatshade;
739 rs->sprite_coord_enable = state->sprite_coord_enable;
740 rs->rasterizer_discard = state->rasterizer_discard;
741 rs->pa_sc_line_stipple = state->line_stipple_enable ?
742 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
743 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
744 rs->pa_cl_clip_cntl =
745 S_028810_PS_UCP_MODE(3) |
746 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
747 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
748 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
749 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
750 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
751
752 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
753 S_0286D4_FLAT_SHADE_ENA(1) |
754 S_0286D4_PNT_SPRITE_ENA(1) |
755 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
756 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
757 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
758 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
759 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
760
761 /* point size 12.4 fixed point */
762 tmp = (unsigned)(state->point_size * 8.0);
763 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
764
765 if (state->point_size_per_vertex) {
766 psize_min = util_get_min_point_size(state);
767 psize_max = 8192;
768 } else {
769 /* Force the point size to be as if the vertex output was disabled. */
770 psize_min = state->point_size;
771 psize_max = state->point_size;
772 }
773 /* Divide by two, because 0.5 = 1 pixel. */
774 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
775 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
776 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
777
778 tmp = (unsigned)state->line_width * 8;
779 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
780 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
781 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
782 S_028A48_MSAA_ENABLE(state->multisample ||
783 state->poly_smooth ||
784 state->line_smooth) |
785 S_028A48_VPORT_SCISSOR_ENABLE(1));
786
787 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
788 S_028BE4_PIX_CENTER(state->half_pixel_center) |
789 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
790
791 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
792 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
793 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
794 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
795 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
796 S_028814_FACE(!state->front_ccw) |
797 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
798 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
799 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
800 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
801 state->fill_back != PIPE_POLYGON_MODE_FILL) |
802 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
803 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
804 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
805 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
806
807 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
808 for (i = 0; i < 3; i++) {
809 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
810 float offset_units = state->offset_units;
811 float offset_scale = state->offset_scale * 16.0f;
812
813 switch (i) {
814 case 0: /* 16-bit zbuffer */
815 offset_units *= 4.0f;
816 break;
817 case 1: /* 24-bit zbuffer */
818 offset_units *= 2.0f;
819 break;
820 case 2: /* 32-bit zbuffer */
821 offset_units *= 1.0f;
822 break;
823 }
824
825 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
826 fui(offset_scale));
827 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
828 fui(offset_units));
829 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
830 fui(offset_scale));
831 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
832 fui(offset_units));
833 }
834
835 return rs;
836 }
837
838 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
839 {
840 struct si_context *sctx = (struct si_context *)ctx;
841 struct si_state_rasterizer *old_rs =
842 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
843 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
844
845 if (!state)
846 return;
847
848 if (sctx->framebuffer.nr_samples > 1 &&
849 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
850 si_mark_atom_dirty(sctx, &sctx->db_render_state);
851
852 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
853
854 si_pm4_bind_state(sctx, rasterizer, rs);
855 si_update_poly_offset_state(sctx);
856
857 si_mark_atom_dirty(sctx, &sctx->clip_regs);
858 }
859
860 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
861 {
862 struct si_context *sctx = (struct si_context *)ctx;
863
864 if (sctx->queued.named.rasterizer == state)
865 si_pm4_bind_state(sctx, poly_offset, NULL);
866 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
867 }
868
869 /*
870 * infeered state between dsa and stencil ref
871 */
872 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
873 {
874 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
875 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
876 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
877
878 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
879 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
880 S_028430_STENCILMASK(dsa->valuemask[0]) |
881 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
882 S_028430_STENCILOPVAL(1));
883 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
884 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
885 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
886 S_028434_STENCILOPVAL_BF(1));
887 }
888
889 static void si_set_stencil_ref(struct pipe_context *ctx,
890 const struct pipe_stencil_ref *state)
891 {
892 struct si_context *sctx = (struct si_context *)ctx;
893
894 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
895 return;
896
897 sctx->stencil_ref.state = *state;
898 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
899 }
900
901
902 /*
903 * DSA
904 */
905
906 static uint32_t si_translate_stencil_op(int s_op)
907 {
908 switch (s_op) {
909 case PIPE_STENCIL_OP_KEEP:
910 return V_02842C_STENCIL_KEEP;
911 case PIPE_STENCIL_OP_ZERO:
912 return V_02842C_STENCIL_ZERO;
913 case PIPE_STENCIL_OP_REPLACE:
914 return V_02842C_STENCIL_REPLACE_TEST;
915 case PIPE_STENCIL_OP_INCR:
916 return V_02842C_STENCIL_ADD_CLAMP;
917 case PIPE_STENCIL_OP_DECR:
918 return V_02842C_STENCIL_SUB_CLAMP;
919 case PIPE_STENCIL_OP_INCR_WRAP:
920 return V_02842C_STENCIL_ADD_WRAP;
921 case PIPE_STENCIL_OP_DECR_WRAP:
922 return V_02842C_STENCIL_SUB_WRAP;
923 case PIPE_STENCIL_OP_INVERT:
924 return V_02842C_STENCIL_INVERT;
925 default:
926 R600_ERR("Unknown stencil op %d", s_op);
927 assert(0);
928 break;
929 }
930 return 0;
931 }
932
933 static void *si_create_dsa_state(struct pipe_context *ctx,
934 const struct pipe_depth_stencil_alpha_state *state)
935 {
936 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
937 struct si_pm4_state *pm4 = &dsa->pm4;
938 unsigned db_depth_control;
939 uint32_t db_stencil_control = 0;
940
941 if (!dsa) {
942 return NULL;
943 }
944
945 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
946 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
947 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
948 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
949
950 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
951 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
952 S_028800_ZFUNC(state->depth.func) |
953 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
954
955 /* stencil */
956 if (state->stencil[0].enabled) {
957 db_depth_control |= S_028800_STENCIL_ENABLE(1);
958 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
959 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
960 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
961 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
962
963 if (state->stencil[1].enabled) {
964 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
965 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
966 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
967 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
968 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
969 }
970 }
971
972 /* alpha */
973 if (state->alpha.enabled) {
974 dsa->alpha_func = state->alpha.func;
975
976 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
977 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
978 } else {
979 dsa->alpha_func = PIPE_FUNC_ALWAYS;
980 }
981
982 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
983 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
984 if (state->depth.bounds_test) {
985 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
986 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
987 }
988
989 return dsa;
990 }
991
992 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
993 {
994 struct si_context *sctx = (struct si_context *)ctx;
995 struct si_state_dsa *dsa = state;
996
997 if (!state)
998 return;
999
1000 si_pm4_bind_state(sctx, dsa, dsa);
1001
1002 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1003 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1004 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1005 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1006 }
1007 }
1008
1009 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1010 {
1011 struct si_context *sctx = (struct si_context *)ctx;
1012 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1013 }
1014
1015 static void *si_create_db_flush_dsa(struct si_context *sctx)
1016 {
1017 struct pipe_depth_stencil_alpha_state dsa = {};
1018
1019 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1020 }
1021
1022 /* DB RENDER STATE */
1023
1024 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1025 {
1026 struct si_context *sctx = (struct si_context*)ctx;
1027
1028 /* Pipeline stat & streamout queries. */
1029 if (enable) {
1030 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1031 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1032 } else {
1033 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1034 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1035 }
1036
1037 /* Occlusion queries. */
1038 if (sctx->occlusion_queries_disabled != !enable) {
1039 sctx->occlusion_queries_disabled = !enable;
1040 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1041 }
1042 }
1043
1044 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1045 {
1046 struct si_context *sctx = (struct si_context*)ctx;
1047
1048 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1049 }
1050
1051 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1052 {
1053 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1054 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1055 unsigned db_shader_control;
1056
1057 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1058
1059 /* DB_RENDER_CONTROL */
1060 if (sctx->dbcb_depth_copy_enabled ||
1061 sctx->dbcb_stencil_copy_enabled) {
1062 radeon_emit(cs,
1063 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1064 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1065 S_028000_COPY_CENTROID(1) |
1066 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1067 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1068 radeon_emit(cs,
1069 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1070 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1071 } else {
1072 radeon_emit(cs,
1073 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1074 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1075 }
1076
1077 /* DB_COUNT_CONTROL (occlusion queries) */
1078 if (sctx->b.num_occlusion_queries > 0 &&
1079 !sctx->occlusion_queries_disabled) {
1080 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1081
1082 if (sctx->b.chip_class >= CIK) {
1083 radeon_emit(cs,
1084 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1085 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1086 S_028004_ZPASS_ENABLE(1) |
1087 S_028004_SLICE_EVEN_ENABLE(1) |
1088 S_028004_SLICE_ODD_ENABLE(1));
1089 } else {
1090 radeon_emit(cs,
1091 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1092 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1093 }
1094 } else {
1095 /* Disable occlusion queries. */
1096 if (sctx->b.chip_class >= CIK) {
1097 radeon_emit(cs, 0);
1098 } else {
1099 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1100 }
1101 }
1102
1103 /* DB_RENDER_OVERRIDE2 */
1104 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1105 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1106 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1107 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1108
1109 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1110 sctx->ps_db_shader_control;
1111
1112 /* Bug workaround for smoothing (overrasterization) on SI. */
1113 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1114 db_shader_control &= C_02880C_Z_ORDER;
1115 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1116 }
1117
1118 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1119 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1120 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1121
1122 if (sctx->b.family == CHIP_STONEY &&
1123 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1124 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1125
1126 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1127 db_shader_control);
1128 }
1129
1130 /*
1131 * format translation
1132 */
1133 static uint32_t si_translate_colorformat(enum pipe_format format)
1134 {
1135 const struct util_format_description *desc = util_format_description(format);
1136
1137 #define HAS_SIZE(x,y,z,w) \
1138 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1139 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1140
1141 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1142 return V_028C70_COLOR_10_11_11;
1143
1144 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1145 return V_028C70_COLOR_INVALID;
1146
1147 /* hw cannot support mixed formats (except depth/stencil, since
1148 * stencil is not written to). */
1149 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1150 return V_028C70_COLOR_INVALID;
1151
1152 switch (desc->nr_channels) {
1153 case 1:
1154 switch (desc->channel[0].size) {
1155 case 8:
1156 return V_028C70_COLOR_8;
1157 case 16:
1158 return V_028C70_COLOR_16;
1159 case 32:
1160 return V_028C70_COLOR_32;
1161 }
1162 break;
1163 case 2:
1164 if (desc->channel[0].size == desc->channel[1].size) {
1165 switch (desc->channel[0].size) {
1166 case 8:
1167 return V_028C70_COLOR_8_8;
1168 case 16:
1169 return V_028C70_COLOR_16_16;
1170 case 32:
1171 return V_028C70_COLOR_32_32;
1172 }
1173 } else if (HAS_SIZE(8,24,0,0)) {
1174 return V_028C70_COLOR_24_8;
1175 } else if (HAS_SIZE(24,8,0,0)) {
1176 return V_028C70_COLOR_8_24;
1177 }
1178 break;
1179 case 3:
1180 if (HAS_SIZE(5,6,5,0)) {
1181 return V_028C70_COLOR_5_6_5;
1182 } else if (HAS_SIZE(32,8,24,0)) {
1183 return V_028C70_COLOR_X24_8_32_FLOAT;
1184 }
1185 break;
1186 case 4:
1187 if (desc->channel[0].size == desc->channel[1].size &&
1188 desc->channel[0].size == desc->channel[2].size &&
1189 desc->channel[0].size == desc->channel[3].size) {
1190 switch (desc->channel[0].size) {
1191 case 4:
1192 return V_028C70_COLOR_4_4_4_4;
1193 case 8:
1194 return V_028C70_COLOR_8_8_8_8;
1195 case 16:
1196 return V_028C70_COLOR_16_16_16_16;
1197 case 32:
1198 return V_028C70_COLOR_32_32_32_32;
1199 }
1200 } else if (HAS_SIZE(5,5,5,1)) {
1201 return V_028C70_COLOR_1_5_5_5;
1202 } else if (HAS_SIZE(10,10,10,2)) {
1203 return V_028C70_COLOR_2_10_10_10;
1204 }
1205 break;
1206 }
1207 return V_028C70_COLOR_INVALID;
1208 }
1209
1210 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1211 {
1212 if (SI_BIG_ENDIAN) {
1213 switch(colorformat) {
1214 /* 8-bit buffers. */
1215 case V_028C70_COLOR_8:
1216 return V_028C70_ENDIAN_NONE;
1217
1218 /* 16-bit buffers. */
1219 case V_028C70_COLOR_5_6_5:
1220 case V_028C70_COLOR_1_5_5_5:
1221 case V_028C70_COLOR_4_4_4_4:
1222 case V_028C70_COLOR_16:
1223 case V_028C70_COLOR_8_8:
1224 return V_028C70_ENDIAN_8IN16;
1225
1226 /* 32-bit buffers. */
1227 case V_028C70_COLOR_8_8_8_8:
1228 case V_028C70_COLOR_2_10_10_10:
1229 case V_028C70_COLOR_8_24:
1230 case V_028C70_COLOR_24_8:
1231 case V_028C70_COLOR_16_16:
1232 return V_028C70_ENDIAN_8IN32;
1233
1234 /* 64-bit buffers. */
1235 case V_028C70_COLOR_16_16_16_16:
1236 return V_028C70_ENDIAN_8IN16;
1237
1238 case V_028C70_COLOR_32_32:
1239 return V_028C70_ENDIAN_8IN32;
1240
1241 /* 128-bit buffers. */
1242 case V_028C70_COLOR_32_32_32_32:
1243 return V_028C70_ENDIAN_8IN32;
1244 default:
1245 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1246 }
1247 } else {
1248 return V_028C70_ENDIAN_NONE;
1249 }
1250 }
1251
1252 static uint32_t si_translate_dbformat(enum pipe_format format)
1253 {
1254 switch (format) {
1255 case PIPE_FORMAT_Z16_UNORM:
1256 return V_028040_Z_16;
1257 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1258 case PIPE_FORMAT_X8Z24_UNORM:
1259 case PIPE_FORMAT_Z24X8_UNORM:
1260 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1261 return V_028040_Z_24; /* deprecated on SI */
1262 case PIPE_FORMAT_Z32_FLOAT:
1263 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1264 return V_028040_Z_32_FLOAT;
1265 default:
1266 return V_028040_Z_INVALID;
1267 }
1268 }
1269
1270 /*
1271 * Texture translation
1272 */
1273
1274 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1275 enum pipe_format format,
1276 const struct util_format_description *desc,
1277 int first_non_void)
1278 {
1279 struct si_screen *sscreen = (struct si_screen*)screen;
1280 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1281 sscreen->b.info.drm_minor >= 31) ||
1282 sscreen->b.info.drm_major == 3;
1283 boolean uniform = TRUE;
1284 int i;
1285
1286 /* Colorspace (return non-RGB formats directly). */
1287 switch (desc->colorspace) {
1288 /* Depth stencil formats */
1289 case UTIL_FORMAT_COLORSPACE_ZS:
1290 switch (format) {
1291 case PIPE_FORMAT_Z16_UNORM:
1292 return V_008F14_IMG_DATA_FORMAT_16;
1293 case PIPE_FORMAT_X24S8_UINT:
1294 case PIPE_FORMAT_Z24X8_UNORM:
1295 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1296 return V_008F14_IMG_DATA_FORMAT_8_24;
1297 case PIPE_FORMAT_X8Z24_UNORM:
1298 case PIPE_FORMAT_S8X24_UINT:
1299 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1300 return V_008F14_IMG_DATA_FORMAT_24_8;
1301 case PIPE_FORMAT_S8_UINT:
1302 return V_008F14_IMG_DATA_FORMAT_8;
1303 case PIPE_FORMAT_Z32_FLOAT:
1304 return V_008F14_IMG_DATA_FORMAT_32;
1305 case PIPE_FORMAT_X32_S8X24_UINT:
1306 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1307 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1308 default:
1309 goto out_unknown;
1310 }
1311
1312 case UTIL_FORMAT_COLORSPACE_YUV:
1313 goto out_unknown; /* TODO */
1314
1315 case UTIL_FORMAT_COLORSPACE_SRGB:
1316 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1317 goto out_unknown;
1318 break;
1319
1320 default:
1321 break;
1322 }
1323
1324 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1325 if (!enable_compressed_formats)
1326 goto out_unknown;
1327
1328 switch (format) {
1329 case PIPE_FORMAT_RGTC1_SNORM:
1330 case PIPE_FORMAT_LATC1_SNORM:
1331 case PIPE_FORMAT_RGTC1_UNORM:
1332 case PIPE_FORMAT_LATC1_UNORM:
1333 return V_008F14_IMG_DATA_FORMAT_BC4;
1334 case PIPE_FORMAT_RGTC2_SNORM:
1335 case PIPE_FORMAT_LATC2_SNORM:
1336 case PIPE_FORMAT_RGTC2_UNORM:
1337 case PIPE_FORMAT_LATC2_UNORM:
1338 return V_008F14_IMG_DATA_FORMAT_BC5;
1339 default:
1340 goto out_unknown;
1341 }
1342 }
1343
1344 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1345 sscreen->b.family == CHIP_STONEY) {
1346 switch (format) {
1347 case PIPE_FORMAT_ETC1_RGB8:
1348 case PIPE_FORMAT_ETC2_RGB8:
1349 case PIPE_FORMAT_ETC2_SRGB8:
1350 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1351 case PIPE_FORMAT_ETC2_RGB8A1:
1352 case PIPE_FORMAT_ETC2_SRGB8A1:
1353 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1354 case PIPE_FORMAT_ETC2_RGBA8:
1355 case PIPE_FORMAT_ETC2_SRGBA8:
1356 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1357 case PIPE_FORMAT_ETC2_R11_UNORM:
1358 case PIPE_FORMAT_ETC2_R11_SNORM:
1359 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1360 case PIPE_FORMAT_ETC2_RG11_UNORM:
1361 case PIPE_FORMAT_ETC2_RG11_SNORM:
1362 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1363 default:
1364 goto out_unknown;
1365 }
1366 }
1367
1368 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1369 if (!enable_compressed_formats)
1370 goto out_unknown;
1371
1372 switch (format) {
1373 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1374 case PIPE_FORMAT_BPTC_SRGBA:
1375 return V_008F14_IMG_DATA_FORMAT_BC7;
1376 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1377 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1378 return V_008F14_IMG_DATA_FORMAT_BC6;
1379 default:
1380 goto out_unknown;
1381 }
1382 }
1383
1384 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1385 switch (format) {
1386 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1387 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1388 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1389 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1390 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1391 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1392 default:
1393 goto out_unknown;
1394 }
1395 }
1396
1397 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1398 if (!enable_compressed_formats)
1399 goto out_unknown;
1400
1401 if (!util_format_s3tc_enabled) {
1402 goto out_unknown;
1403 }
1404
1405 switch (format) {
1406 case PIPE_FORMAT_DXT1_RGB:
1407 case PIPE_FORMAT_DXT1_RGBA:
1408 case PIPE_FORMAT_DXT1_SRGB:
1409 case PIPE_FORMAT_DXT1_SRGBA:
1410 return V_008F14_IMG_DATA_FORMAT_BC1;
1411 case PIPE_FORMAT_DXT3_RGBA:
1412 case PIPE_FORMAT_DXT3_SRGBA:
1413 return V_008F14_IMG_DATA_FORMAT_BC2;
1414 case PIPE_FORMAT_DXT5_RGBA:
1415 case PIPE_FORMAT_DXT5_SRGBA:
1416 return V_008F14_IMG_DATA_FORMAT_BC3;
1417 default:
1418 goto out_unknown;
1419 }
1420 }
1421
1422 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1423 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1424 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1425 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1426 }
1427
1428 /* R8G8Bx_SNORM - TODO CxV8U8 */
1429
1430 /* hw cannot support mixed formats (except depth/stencil, since only
1431 * depth is read).*/
1432 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1433 goto out_unknown;
1434
1435 /* See whether the components are of the same size. */
1436 for (i = 1; i < desc->nr_channels; i++) {
1437 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1438 }
1439
1440 /* Non-uniform formats. */
1441 if (!uniform) {
1442 switch(desc->nr_channels) {
1443 case 3:
1444 if (desc->channel[0].size == 5 &&
1445 desc->channel[1].size == 6 &&
1446 desc->channel[2].size == 5) {
1447 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1448 }
1449 goto out_unknown;
1450 case 4:
1451 if (desc->channel[0].size == 5 &&
1452 desc->channel[1].size == 5 &&
1453 desc->channel[2].size == 5 &&
1454 desc->channel[3].size == 1) {
1455 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1456 }
1457 if (desc->channel[0].size == 10 &&
1458 desc->channel[1].size == 10 &&
1459 desc->channel[2].size == 10 &&
1460 desc->channel[3].size == 2) {
1461 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1462 }
1463 goto out_unknown;
1464 }
1465 goto out_unknown;
1466 }
1467
1468 if (first_non_void < 0 || first_non_void > 3)
1469 goto out_unknown;
1470
1471 /* uniform formats */
1472 switch (desc->channel[first_non_void].size) {
1473 case 4:
1474 switch (desc->nr_channels) {
1475 #if 0 /* Not supported for render targets */
1476 case 2:
1477 return V_008F14_IMG_DATA_FORMAT_4_4;
1478 #endif
1479 case 4:
1480 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1481 }
1482 break;
1483 case 8:
1484 switch (desc->nr_channels) {
1485 case 1:
1486 return V_008F14_IMG_DATA_FORMAT_8;
1487 case 2:
1488 return V_008F14_IMG_DATA_FORMAT_8_8;
1489 case 4:
1490 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1491 }
1492 break;
1493 case 16:
1494 switch (desc->nr_channels) {
1495 case 1:
1496 return V_008F14_IMG_DATA_FORMAT_16;
1497 case 2:
1498 return V_008F14_IMG_DATA_FORMAT_16_16;
1499 case 4:
1500 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1501 }
1502 break;
1503 case 32:
1504 switch (desc->nr_channels) {
1505 case 1:
1506 return V_008F14_IMG_DATA_FORMAT_32;
1507 case 2:
1508 return V_008F14_IMG_DATA_FORMAT_32_32;
1509 #if 0 /* Not supported for render targets */
1510 case 3:
1511 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1512 #endif
1513 case 4:
1514 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1515 }
1516 }
1517
1518 out_unknown:
1519 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1520 return ~0;
1521 }
1522
1523 static unsigned si_tex_wrap(unsigned wrap)
1524 {
1525 switch (wrap) {
1526 default:
1527 case PIPE_TEX_WRAP_REPEAT:
1528 return V_008F30_SQ_TEX_WRAP;
1529 case PIPE_TEX_WRAP_CLAMP:
1530 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1531 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1532 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1533 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1534 return V_008F30_SQ_TEX_CLAMP_BORDER;
1535 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1536 return V_008F30_SQ_TEX_MIRROR;
1537 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1538 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1539 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1540 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1541 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1542 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1543 }
1544 }
1545
1546 static unsigned si_tex_mipfilter(unsigned filter)
1547 {
1548 switch (filter) {
1549 case PIPE_TEX_MIPFILTER_NEAREST:
1550 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1551 case PIPE_TEX_MIPFILTER_LINEAR:
1552 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1553 default:
1554 case PIPE_TEX_MIPFILTER_NONE:
1555 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1556 }
1557 }
1558
1559 static unsigned si_tex_compare(unsigned compare)
1560 {
1561 switch (compare) {
1562 default:
1563 case PIPE_FUNC_NEVER:
1564 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1565 case PIPE_FUNC_LESS:
1566 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1567 case PIPE_FUNC_EQUAL:
1568 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1569 case PIPE_FUNC_LEQUAL:
1570 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1571 case PIPE_FUNC_GREATER:
1572 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1573 case PIPE_FUNC_NOTEQUAL:
1574 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1575 case PIPE_FUNC_GEQUAL:
1576 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1577 case PIPE_FUNC_ALWAYS:
1578 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1579 }
1580 }
1581
1582 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1583 unsigned nr_samples)
1584 {
1585 if (view_target == PIPE_TEXTURE_CUBE ||
1586 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1587 res_target = view_target;
1588
1589 switch (res_target) {
1590 default:
1591 case PIPE_TEXTURE_1D:
1592 return V_008F1C_SQ_RSRC_IMG_1D;
1593 case PIPE_TEXTURE_1D_ARRAY:
1594 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1595 case PIPE_TEXTURE_2D:
1596 case PIPE_TEXTURE_RECT:
1597 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1598 V_008F1C_SQ_RSRC_IMG_2D;
1599 case PIPE_TEXTURE_2D_ARRAY:
1600 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1601 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1602 case PIPE_TEXTURE_3D:
1603 return V_008F1C_SQ_RSRC_IMG_3D;
1604 case PIPE_TEXTURE_CUBE:
1605 case PIPE_TEXTURE_CUBE_ARRAY:
1606 return V_008F1C_SQ_RSRC_IMG_CUBE;
1607 }
1608 }
1609
1610 /*
1611 * Format support testing
1612 */
1613
1614 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1615 {
1616 return si_translate_texformat(screen, format, util_format_description(format),
1617 util_format_get_first_non_void_channel(format)) != ~0U;
1618 }
1619
1620 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1621 const struct util_format_description *desc,
1622 int first_non_void)
1623 {
1624 unsigned type;
1625 int i;
1626
1627 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1628 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1629
1630 assert(first_non_void >= 0);
1631 type = desc->channel[first_non_void].type;
1632
1633 if (type == UTIL_FORMAT_TYPE_FIXED)
1634 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1635
1636 if (desc->nr_channels == 4 &&
1637 desc->channel[0].size == 10 &&
1638 desc->channel[1].size == 10 &&
1639 desc->channel[2].size == 10 &&
1640 desc->channel[3].size == 2)
1641 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1642
1643 /* See whether the components are of the same size. */
1644 for (i = 0; i < desc->nr_channels; i++) {
1645 if (desc->channel[first_non_void].size != desc->channel[i].size)
1646 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1647 }
1648
1649 switch (desc->channel[first_non_void].size) {
1650 case 8:
1651 switch (desc->nr_channels) {
1652 case 1:
1653 return V_008F0C_BUF_DATA_FORMAT_8;
1654 case 2:
1655 return V_008F0C_BUF_DATA_FORMAT_8_8;
1656 case 3:
1657 case 4:
1658 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1659 }
1660 break;
1661 case 16:
1662 switch (desc->nr_channels) {
1663 case 1:
1664 return V_008F0C_BUF_DATA_FORMAT_16;
1665 case 2:
1666 return V_008F0C_BUF_DATA_FORMAT_16_16;
1667 case 3:
1668 case 4:
1669 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1670 }
1671 break;
1672 case 32:
1673 /* From the Southern Islands ISA documentation about MTBUF:
1674 * 'Memory reads of data in memory that is 32 or 64 bits do not
1675 * undergo any format conversion.'
1676 */
1677 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1678 !desc->channel[first_non_void].pure_integer)
1679 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1680
1681 switch (desc->nr_channels) {
1682 case 1:
1683 return V_008F0C_BUF_DATA_FORMAT_32;
1684 case 2:
1685 return V_008F0C_BUF_DATA_FORMAT_32_32;
1686 case 3:
1687 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1688 case 4:
1689 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1690 }
1691 break;
1692 }
1693
1694 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1695 }
1696
1697 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1698 const struct util_format_description *desc,
1699 int first_non_void)
1700 {
1701 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1702 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1703
1704 assert(first_non_void >= 0);
1705
1706 switch (desc->channel[first_non_void].type) {
1707 case UTIL_FORMAT_TYPE_SIGNED:
1708 if (desc->channel[first_non_void].normalized)
1709 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1710 else if (desc->channel[first_non_void].pure_integer)
1711 return V_008F0C_BUF_NUM_FORMAT_SINT;
1712 else
1713 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1714 break;
1715 case UTIL_FORMAT_TYPE_UNSIGNED:
1716 if (desc->channel[first_non_void].normalized)
1717 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1718 else if (desc->channel[first_non_void].pure_integer)
1719 return V_008F0C_BUF_NUM_FORMAT_UINT;
1720 else
1721 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1722 break;
1723 case UTIL_FORMAT_TYPE_FLOAT:
1724 default:
1725 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1726 }
1727 }
1728
1729 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1730 {
1731 const struct util_format_description *desc;
1732 int first_non_void;
1733 unsigned data_format;
1734
1735 desc = util_format_description(format);
1736 first_non_void = util_format_get_first_non_void_channel(format);
1737 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1738 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1739 }
1740
1741 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1742 {
1743 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1744 r600_translate_colorswap(format, FALSE) != ~0U;
1745 }
1746
1747 static bool si_is_zs_format_supported(enum pipe_format format)
1748 {
1749 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1750 }
1751
1752 boolean si_is_format_supported(struct pipe_screen *screen,
1753 enum pipe_format format,
1754 enum pipe_texture_target target,
1755 unsigned sample_count,
1756 unsigned usage)
1757 {
1758 unsigned retval = 0;
1759
1760 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1761 R600_ERR("r600: unsupported texture type %d\n", target);
1762 return FALSE;
1763 }
1764
1765 if (!util_format_is_supported(format, usage))
1766 return FALSE;
1767
1768 if (sample_count > 1) {
1769 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1770 return FALSE;
1771
1772 switch (sample_count) {
1773 case 2:
1774 case 4:
1775 case 8:
1776 break;
1777 case 16:
1778 if (format == PIPE_FORMAT_NONE)
1779 return TRUE;
1780 else
1781 return FALSE;
1782 default:
1783 return FALSE;
1784 }
1785 }
1786
1787 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1788 if (target == PIPE_BUFFER) {
1789 if (si_is_vertex_format_supported(screen, format))
1790 retval |= PIPE_BIND_SAMPLER_VIEW;
1791 } else {
1792 if (si_is_sampler_format_supported(screen, format))
1793 retval |= PIPE_BIND_SAMPLER_VIEW;
1794 }
1795 }
1796
1797 if ((usage & (PIPE_BIND_RENDER_TARGET |
1798 PIPE_BIND_DISPLAY_TARGET |
1799 PIPE_BIND_SCANOUT |
1800 PIPE_BIND_SHARED |
1801 PIPE_BIND_BLENDABLE)) &&
1802 si_is_colorbuffer_format_supported(format)) {
1803 retval |= usage &
1804 (PIPE_BIND_RENDER_TARGET |
1805 PIPE_BIND_DISPLAY_TARGET |
1806 PIPE_BIND_SCANOUT |
1807 PIPE_BIND_SHARED);
1808 if (!util_format_is_pure_integer(format) &&
1809 !util_format_is_depth_or_stencil(format))
1810 retval |= usage & PIPE_BIND_BLENDABLE;
1811 }
1812
1813 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1814 si_is_zs_format_supported(format)) {
1815 retval |= PIPE_BIND_DEPTH_STENCIL;
1816 }
1817
1818 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1819 si_is_vertex_format_supported(screen, format)) {
1820 retval |= PIPE_BIND_VERTEX_BUFFER;
1821 }
1822
1823 if (usage & PIPE_BIND_TRANSFER_READ)
1824 retval |= PIPE_BIND_TRANSFER_READ;
1825 if (usage & PIPE_BIND_TRANSFER_WRITE)
1826 retval |= PIPE_BIND_TRANSFER_WRITE;
1827
1828 if ((usage & PIPE_BIND_LINEAR) &&
1829 !util_format_is_compressed(format) &&
1830 !(usage & PIPE_BIND_DEPTH_STENCIL))
1831 retval |= PIPE_BIND_LINEAR;
1832
1833 return retval == usage;
1834 }
1835
1836 /*
1837 * framebuffer handling
1838 */
1839
1840 static void si_choose_spi_color_formats(struct r600_surface *surf,
1841 unsigned format, unsigned swap,
1842 unsigned ntype, bool is_depth)
1843 {
1844 /* Alpha is needed for alpha-to-coverage.
1845 * Blending may be with or without alpha.
1846 */
1847 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1848 unsigned alpha = 0; /* exports alpha, but may not support blending */
1849 unsigned blend = 0; /* supports blending, but may not export alpha */
1850 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1851
1852 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1853 * Other chips have multiple choices, though they are not necessarily better.
1854 */
1855 switch (format) {
1856 case V_028C70_COLOR_5_6_5:
1857 case V_028C70_COLOR_1_5_5_5:
1858 case V_028C70_COLOR_5_5_5_1:
1859 case V_028C70_COLOR_4_4_4_4:
1860 case V_028C70_COLOR_10_11_11:
1861 case V_028C70_COLOR_11_11_10:
1862 case V_028C70_COLOR_8:
1863 case V_028C70_COLOR_8_8:
1864 case V_028C70_COLOR_8_8_8_8:
1865 case V_028C70_COLOR_10_10_10_2:
1866 case V_028C70_COLOR_2_10_10_10:
1867 if (ntype == V_028C70_NUMBER_UINT)
1868 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1869 else if (ntype == V_028C70_NUMBER_SINT)
1870 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1871 else
1872 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1873 break;
1874
1875 case V_028C70_COLOR_16:
1876 case V_028C70_COLOR_16_16:
1877 case V_028C70_COLOR_16_16_16_16:
1878 if (ntype == V_028C70_NUMBER_UNORM ||
1879 ntype == V_028C70_NUMBER_SNORM) {
1880 /* UNORM16 and SNORM16 don't support blending */
1881 if (ntype == V_028C70_NUMBER_UNORM)
1882 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1883 else
1884 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1885
1886 /* Use 32 bits per channel for blending. */
1887 if (format == V_028C70_COLOR_16) {
1888 if (swap == V_028C70_SWAP_STD) { /* R */
1889 blend = V_028714_SPI_SHADER_32_R;
1890 blend_alpha = V_028714_SPI_SHADER_32_AR;
1891 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1892 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1893 else
1894 assert(0);
1895 } else if (format == V_028C70_COLOR_16_16) {
1896 if (swap == V_028C70_SWAP_STD) { /* RG */
1897 blend = V_028714_SPI_SHADER_32_GR;
1898 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1899 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1900 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1901 else
1902 assert(0);
1903 } else /* 16_16_16_16 */
1904 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1905 } else if (ntype == V_028C70_NUMBER_UINT)
1906 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1907 else if (ntype == V_028C70_NUMBER_SINT)
1908 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1909 else if (ntype == V_028C70_NUMBER_FLOAT)
1910 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1911 else
1912 assert(0);
1913 break;
1914
1915 case V_028C70_COLOR_32:
1916 if (swap == V_028C70_SWAP_STD) { /* R */
1917 blend = normal = V_028714_SPI_SHADER_32_R;
1918 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1919 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1920 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1921 else
1922 assert(0);
1923 break;
1924
1925 case V_028C70_COLOR_32_32:
1926 if (swap == V_028C70_SWAP_STD) { /* RG */
1927 blend = normal = V_028714_SPI_SHADER_32_GR;
1928 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1929 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1930 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1931 else
1932 assert(0);
1933 break;
1934
1935 case V_028C70_COLOR_32_32_32_32:
1936 case V_028C70_COLOR_8_24:
1937 case V_028C70_COLOR_24_8:
1938 case V_028C70_COLOR_X24_8_32_FLOAT:
1939 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1940 break;
1941
1942 default:
1943 assert(0);
1944 return;
1945 }
1946
1947 /* The DB->CB copy needs 32_ABGR. */
1948 if (is_depth)
1949 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1950
1951 surf->spi_shader_col_format = normal;
1952 surf->spi_shader_col_format_alpha = alpha;
1953 surf->spi_shader_col_format_blend = blend;
1954 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1955 }
1956
1957 static void si_initialize_color_surface(struct si_context *sctx,
1958 struct r600_surface *surf)
1959 {
1960 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1961 unsigned level = surf->base.u.tex.level;
1962 unsigned color_info, color_attrib, color_view;
1963 unsigned format, swap, ntype, endian;
1964 const struct util_format_description *desc;
1965 int i;
1966 unsigned blend_clamp = 0, blend_bypass = 0;
1967
1968 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1969 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1970
1971 desc = util_format_description(surf->base.format);
1972 for (i = 0; i < 4; i++) {
1973 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1974 break;
1975 }
1976 }
1977 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1978 ntype = V_028C70_NUMBER_FLOAT;
1979 } else {
1980 ntype = V_028C70_NUMBER_UNORM;
1981 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1982 ntype = V_028C70_NUMBER_SRGB;
1983 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1984 if (desc->channel[i].pure_integer) {
1985 ntype = V_028C70_NUMBER_SINT;
1986 } else {
1987 assert(desc->channel[i].normalized);
1988 ntype = V_028C70_NUMBER_SNORM;
1989 }
1990 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1991 if (desc->channel[i].pure_integer) {
1992 ntype = V_028C70_NUMBER_UINT;
1993 } else {
1994 assert(desc->channel[i].normalized);
1995 ntype = V_028C70_NUMBER_UNORM;
1996 }
1997 }
1998 }
1999
2000 format = si_translate_colorformat(surf->base.format);
2001 if (format == V_028C70_COLOR_INVALID) {
2002 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2003 }
2004 assert(format != V_028C70_COLOR_INVALID);
2005 swap = r600_translate_colorswap(surf->base.format, FALSE);
2006 endian = si_colorformat_endian_swap(format);
2007
2008 /* blend clamp should be set for all NORM/SRGB types */
2009 if (ntype == V_028C70_NUMBER_UNORM ||
2010 ntype == V_028C70_NUMBER_SNORM ||
2011 ntype == V_028C70_NUMBER_SRGB)
2012 blend_clamp = 1;
2013
2014 /* set blend bypass according to docs if SINT/UINT or
2015 8/24 COLOR variants */
2016 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2017 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2018 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2019 blend_clamp = 0;
2020 blend_bypass = 1;
2021 }
2022
2023 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2024 (format == V_028C70_COLOR_8 ||
2025 format == V_028C70_COLOR_8_8 ||
2026 format == V_028C70_COLOR_8_8_8_8))
2027 surf->color_is_int8 = true;
2028
2029 color_info = S_028C70_FORMAT(format) |
2030 S_028C70_COMP_SWAP(swap) |
2031 S_028C70_BLEND_CLAMP(blend_clamp) |
2032 S_028C70_BLEND_BYPASS(blend_bypass) |
2033 S_028C70_NUMBER_TYPE(ntype) |
2034 S_028C70_ENDIAN(endian);
2035
2036 /* Intensity is implemented as Red, so treat it that way. */
2037 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2038 util_format_is_intensity(surf->base.format));
2039
2040 if (rtex->resource.b.b.nr_samples > 1) {
2041 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2042
2043 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2044 S_028C74_NUM_FRAGMENTS(log_samples);
2045
2046 if (rtex->fmask.size) {
2047 color_info |= S_028C70_COMPRESSION(1);
2048 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2049
2050 if (sctx->b.chip_class == SI) {
2051 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2052 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2053 }
2054 }
2055 }
2056
2057 surf->cb_color_view = color_view;
2058 surf->cb_color_info = color_info;
2059 surf->cb_color_attrib = color_attrib;
2060
2061 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2062 unsigned max_uncompressed_block_size = 2;
2063
2064 if (rtex->surface.nsamples > 1) {
2065 if (rtex->surface.bpe == 1)
2066 max_uncompressed_block_size = 0;
2067 else if (rtex->surface.bpe == 2)
2068 max_uncompressed_block_size = 1;
2069 }
2070
2071 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2072 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2073 surf->cb_dcc_base = (rtex->resource.gpu_address +
2074 rtex->dcc_offset +
2075 rtex->surface.level[level].dcc_offset) >> 8;
2076 }
2077
2078 /* This must be set for fast clear to work without FMASK. */
2079 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2080 unsigned bankh = util_logbase2(rtex->surface.bankh);
2081 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2082 }
2083
2084 /* Determine pixel shader export format */
2085 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2086
2087 surf->color_initialized = true;
2088 }
2089
2090 static void si_init_depth_surface(struct si_context *sctx,
2091 struct r600_surface *surf)
2092 {
2093 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2094 unsigned level = surf->base.u.tex.level;
2095 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2096 unsigned format;
2097 uint32_t z_info, s_info, db_depth_info;
2098 uint64_t z_offs, s_offs;
2099 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2100
2101 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2102 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2103 case PIPE_FORMAT_X8Z24_UNORM:
2104 case PIPE_FORMAT_Z24X8_UNORM:
2105 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2106 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2107 break;
2108 case PIPE_FORMAT_Z32_FLOAT:
2109 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2110 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2111 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2112 break;
2113 case PIPE_FORMAT_Z16_UNORM:
2114 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2115 break;
2116 default:
2117 assert(0);
2118 }
2119
2120 format = si_translate_dbformat(rtex->resource.b.b.format);
2121
2122 if (format == V_028040_Z_INVALID) {
2123 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2124 }
2125 assert(format != V_028040_Z_INVALID);
2126
2127 s_offs = z_offs = rtex->resource.gpu_address;
2128 z_offs += rtex->surface.level[level].offset;
2129 s_offs += rtex->surface.stencil_level[level].offset;
2130
2131 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2132
2133 z_info = S_028040_FORMAT(format);
2134 if (rtex->resource.b.b.nr_samples > 1) {
2135 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2136 }
2137
2138 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2139 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2140 else
2141 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2142
2143 if (sctx->b.chip_class >= CIK) {
2144 struct radeon_info *info = &sctx->screen->b.info;
2145 unsigned index = rtex->surface.tiling_index[level];
2146 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2147 unsigned macro_index = rtex->surface.macro_tile_index;
2148 unsigned tile_mode = info->si_tile_mode_array[index];
2149 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2150 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2151
2152 db_depth_info |=
2153 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2154 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2155 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2156 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2157 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2158 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2159 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2160 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2161 } else {
2162 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2163 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2164 tile_mode_index = si_tile_mode_index(rtex, level, true);
2165 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2166 }
2167
2168 /* HiZ aka depth buffer htile */
2169 /* use htile only for first level */
2170 if (rtex->htile_buffer && !level) {
2171 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2172 S_028040_ALLOW_EXPCLEAR(1);
2173
2174 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2175 /* Workaround: For a not yet understood reason, the
2176 * combination of MSAA, fast stencil clear and stencil
2177 * decompress messes with subsequent stencil buffer
2178 * uses. Problem was reproduced on Verde, Bonaire,
2179 * Tonga, and Carrizo.
2180 *
2181 * Disabling EXPCLEAR works around the problem.
2182 *
2183 * Check piglit's arb_texture_multisample-stencil-clear
2184 * test if you want to try changing this.
2185 */
2186 if (rtex->resource.b.b.nr_samples <= 1)
2187 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2188 } else
2189 /* Use all of the htile_buffer for depth if there's no stencil. */
2190 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2191
2192 uint64_t va = rtex->htile_buffer->gpu_address;
2193 db_htile_data_base = va >> 8;
2194 db_htile_surface = S_028ABC_FULL_CACHE(1);
2195 } else {
2196 db_htile_data_base = 0;
2197 db_htile_surface = 0;
2198 }
2199
2200 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2201
2202 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2203 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2204 surf->db_htile_data_base = db_htile_data_base;
2205 surf->db_depth_info = db_depth_info;
2206 surf->db_z_info = z_info;
2207 surf->db_stencil_info = s_info;
2208 surf->db_depth_base = z_offs >> 8;
2209 surf->db_stencil_base = s_offs >> 8;
2210 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2211 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2212 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2213 levelinfo->nblk_y) / 64 - 1);
2214 surf->db_htile_surface = db_htile_surface;
2215 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2216
2217 surf->depth_initialized = true;
2218 }
2219
2220 void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2221 {
2222 for (int i = 0; i < state->nr_cbufs; ++i) {
2223 struct r600_surface *surf = NULL;
2224 struct r600_texture *rtex;
2225
2226 if (!state->cbufs[i])
2227 continue;
2228 surf = (struct r600_surface*)state->cbufs[i];
2229 rtex = (struct r600_texture*)surf->base.texture;
2230
2231 p_atomic_dec(&rtex->framebuffers_bound);
2232 }
2233 }
2234
2235 static void si_set_framebuffer_state(struct pipe_context *ctx,
2236 const struct pipe_framebuffer_state *state)
2237 {
2238 struct si_context *sctx = (struct si_context *)ctx;
2239 struct pipe_constant_buffer constbuf = {0};
2240 struct r600_surface *surf = NULL;
2241 struct r600_texture *rtex;
2242 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2243 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2244 int i;
2245
2246 /* Only flush TC when changing the framebuffer state, because
2247 * the only client not using TC that can change textures is
2248 * the framebuffer.
2249 *
2250 * Flush all CB and DB caches here because all buffers can be used
2251 * for write by both TC (with shader image stores) and CB/DB.
2252 */
2253 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2254 SI_CONTEXT_INV_GLOBAL_L2 |
2255 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2256 SI_CONTEXT_CS_PARTIAL_FLUSH;
2257
2258 /* Take the maximum of the old and new count. If the new count is lower,
2259 * dirtying is needed to disable the unbound colorbuffers.
2260 */
2261 sctx->framebuffer.dirty_cbufs |=
2262 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2263 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2264
2265 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2266 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2267
2268 sctx->framebuffer.spi_shader_col_format = 0;
2269 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2270 sctx->framebuffer.spi_shader_col_format_blend = 0;
2271 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2272 sctx->framebuffer.color_is_int8 = 0;
2273
2274 sctx->framebuffer.compressed_cb_mask = 0;
2275 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2276 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2277 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2278 util_format_is_pure_integer(state->cbufs[0]->format);
2279
2280 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2281 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2282
2283 for (i = 0; i < state->nr_cbufs; i++) {
2284 if (!state->cbufs[i])
2285 continue;
2286
2287 surf = (struct r600_surface*)state->cbufs[i];
2288 rtex = (struct r600_texture*)surf->base.texture;
2289
2290 if (!surf->color_initialized) {
2291 si_initialize_color_surface(sctx, surf);
2292 }
2293
2294 sctx->framebuffer.spi_shader_col_format |=
2295 surf->spi_shader_col_format << (i * 4);
2296 sctx->framebuffer.spi_shader_col_format_alpha |=
2297 surf->spi_shader_col_format_alpha << (i * 4);
2298 sctx->framebuffer.spi_shader_col_format_blend |=
2299 surf->spi_shader_col_format_blend << (i * 4);
2300 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2301 surf->spi_shader_col_format_blend_alpha << (i * 4);
2302
2303 if (surf->color_is_int8)
2304 sctx->framebuffer.color_is_int8 |= 1 << i;
2305
2306 if (rtex->fmask.size && rtex->cmask.size) {
2307 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2308 }
2309 r600_context_add_resource_size(ctx, surf->base.texture);
2310
2311 p_atomic_inc(&rtex->framebuffers_bound);
2312 }
2313 /* Set the second SPI format for possible dual-src blending. */
2314 if (i == 1 && surf) {
2315 sctx->framebuffer.spi_shader_col_format |=
2316 surf->spi_shader_col_format << (i * 4);
2317 sctx->framebuffer.spi_shader_col_format_alpha |=
2318 surf->spi_shader_col_format_alpha << (i * 4);
2319 sctx->framebuffer.spi_shader_col_format_blend |=
2320 surf->spi_shader_col_format_blend << (i * 4);
2321 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2322 surf->spi_shader_col_format_blend_alpha << (i * 4);
2323 }
2324
2325 if (state->zsbuf) {
2326 surf = (struct r600_surface*)state->zsbuf;
2327
2328 if (!surf->depth_initialized) {
2329 si_init_depth_surface(sctx, surf);
2330 }
2331 r600_context_add_resource_size(ctx, surf->base.texture);
2332 }
2333
2334 si_update_poly_offset_state(sctx);
2335 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2336 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2337
2338 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2339 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2340 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2341
2342 /* Set sample locations as fragment shader constants. */
2343 switch (sctx->framebuffer.nr_samples) {
2344 case 1:
2345 constbuf.user_buffer = sctx->b.sample_locations_1x;
2346 break;
2347 case 2:
2348 constbuf.user_buffer = sctx->b.sample_locations_2x;
2349 break;
2350 case 4:
2351 constbuf.user_buffer = sctx->b.sample_locations_4x;
2352 break;
2353 case 8:
2354 constbuf.user_buffer = sctx->b.sample_locations_8x;
2355 break;
2356 case 16:
2357 constbuf.user_buffer = sctx->b.sample_locations_16x;
2358 break;
2359 default:
2360 R600_ERR("Requested an invalid number of samples %i.\n",
2361 sctx->framebuffer.nr_samples);
2362 assert(0);
2363 }
2364 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2365 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2366
2367 /* Smoothing (only possible with nr_samples == 1) uses the same
2368 * sample locations as the MSAA it simulates.
2369 *
2370 * Therefore, don't update the sample locations when
2371 * transitioning from no AA to smoothing-equivalent AA, and
2372 * vice versa.
2373 */
2374 if ((sctx->framebuffer.nr_samples != 1 ||
2375 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2376 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2377 old_nr_samples != 1))
2378 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2379 }
2380
2381 sctx->need_check_render_feedback = true;
2382 }
2383
2384 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2385 {
2386 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2387 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2388 unsigned i, nr_cbufs = state->nr_cbufs;
2389 struct r600_texture *tex = NULL;
2390 struct r600_surface *cb = NULL;
2391
2392 /* Colorbuffers. */
2393 for (i = 0; i < nr_cbufs; i++) {
2394 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2395 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2396 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2397
2398 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2399 continue;
2400
2401 cb = (struct r600_surface*)state->cbufs[i];
2402 if (!cb) {
2403 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2404 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2405 continue;
2406 }
2407
2408 tex = (struct r600_texture *)cb->base.texture;
2409 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2410 &tex->resource, RADEON_USAGE_READWRITE,
2411 tex->surface.nsamples > 1 ?
2412 RADEON_PRIO_COLOR_BUFFER_MSAA :
2413 RADEON_PRIO_COLOR_BUFFER);
2414
2415 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2416 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2417 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2418 RADEON_PRIO_CMASK);
2419 }
2420
2421 /* Compute mutable surface parameters. */
2422 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2423 slice_tile_max = cb->level_info->nblk_x *
2424 cb->level_info->nblk_y / 64 - 1;
2425 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2426
2427 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2428 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2429 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2430 cb_color_attrib = cb->cb_color_attrib |
2431 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2432
2433 if (tex->fmask.size) {
2434 if (sctx->b.chip_class >= CIK)
2435 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2436 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2437 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2438 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2439 } else {
2440 /* This must be set for fast clear to work without FMASK. */
2441 if (sctx->b.chip_class >= CIK)
2442 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2443 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2444 cb_color_fmask = cb_color_base;
2445 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2446 }
2447
2448 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2449 sctx->b.chip_class >= VI ? 14 : 13);
2450 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2451 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2452 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2453 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2454 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2455 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2456 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2457 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2458 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2459 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2460 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2461 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2462 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2463
2464 if (sctx->b.chip_class >= VI)
2465 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2466 }
2467 /* set CB_COLOR1_INFO for possible dual-src blending */
2468 if (i == 1 && state->cbufs[0] &&
2469 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2470 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2471 cb->cb_color_info | tex->cb_color_info);
2472 i++;
2473 }
2474 for (; i < 8 ; i++)
2475 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2476 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2477
2478 /* ZS buffer. */
2479 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2480 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2481 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2482
2483 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2484 &rtex->resource, RADEON_USAGE_READWRITE,
2485 zb->base.texture->nr_samples > 1 ?
2486 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2487 RADEON_PRIO_DEPTH_BUFFER);
2488
2489 if (zb->db_htile_data_base) {
2490 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2491 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2492 RADEON_PRIO_HTILE);
2493 }
2494
2495 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2496 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2497
2498 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2499 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2500 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2501 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2502 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2503 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2504 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2505 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2506 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2507 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2508 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2509
2510 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2511 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2512 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2513
2514 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2515 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2516 zb->pa_su_poly_offset_db_fmt_cntl);
2517 } else if (sctx->framebuffer.dirty_zsbuf) {
2518 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2519 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2520 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2521 }
2522
2523 /* Framebuffer dimensions. */
2524 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2525 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2526 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2527
2528 sctx->framebuffer.dirty_cbufs = 0;
2529 sctx->framebuffer.dirty_zsbuf = false;
2530 }
2531
2532 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2533 struct r600_atom *atom)
2534 {
2535 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2536 unsigned nr_samples = sctx->framebuffer.nr_samples;
2537
2538 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2539 SI_NUM_SMOOTH_AA_SAMPLES);
2540 }
2541
2542 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2543 {
2544 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2545
2546 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2547 sctx->ps_iter_samples,
2548 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2549 }
2550
2551
2552 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2553 {
2554 struct si_context *sctx = (struct si_context *)ctx;
2555
2556 if (sctx->ps_iter_samples == min_samples)
2557 return;
2558
2559 sctx->ps_iter_samples = min_samples;
2560
2561 if (sctx->framebuffer.nr_samples > 1)
2562 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2563 }
2564
2565 /*
2566 * Samplers
2567 */
2568
2569 /**
2570 * Build the sampler view descriptor for a buffer texture.
2571 * @param state 256-bit descriptor; only the high 128 bits are filled in
2572 */
2573 void
2574 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2575 enum pipe_format format,
2576 unsigned first_element, unsigned last_element,
2577 uint32_t *state)
2578 {
2579 const struct util_format_description *desc;
2580 int first_non_void;
2581 uint64_t va;
2582 unsigned stride;
2583 unsigned num_records;
2584 unsigned num_format, data_format;
2585
2586 desc = util_format_description(format);
2587 first_non_void = util_format_get_first_non_void_channel(format);
2588 stride = desc->block.bits / 8;
2589 va = buf->gpu_address + first_element * stride;
2590 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2591 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2592
2593 num_records = last_element + 1 - first_element;
2594 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2595
2596 if (screen->b.chip_class >= VI)
2597 num_records *= stride;
2598
2599 state[4] = va;
2600 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2601 S_008F04_STRIDE(stride);
2602 state[6] = num_records;
2603 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2604 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2605 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2606 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2607 S_008F0C_NUM_FORMAT(num_format) |
2608 S_008F0C_DATA_FORMAT(data_format);
2609 }
2610
2611 /**
2612 * Build the sampler view descriptor for a texture.
2613 */
2614 void
2615 si_make_texture_descriptor(struct si_screen *screen,
2616 struct r600_texture *tex,
2617 bool sampler,
2618 enum pipe_texture_target target,
2619 enum pipe_format pipe_format,
2620 const unsigned char state_swizzle[4],
2621 unsigned first_level, unsigned last_level,
2622 unsigned first_layer, unsigned last_layer,
2623 unsigned width, unsigned height, unsigned depth,
2624 uint32_t *state,
2625 uint32_t *fmask_state)
2626 {
2627 struct pipe_resource *res = &tex->resource.b.b;
2628 const struct util_format_description *desc;
2629 unsigned char swizzle[4];
2630 int first_non_void;
2631 unsigned num_format, data_format, type;
2632 uint64_t va;
2633
2634 desc = util_format_description(pipe_format);
2635
2636 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2637 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2638 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2639
2640 switch (pipe_format) {
2641 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2642 case PIPE_FORMAT_X24S8_UINT:
2643 case PIPE_FORMAT_X32_S8X24_UINT:
2644 case PIPE_FORMAT_X8Z24_UNORM:
2645 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2646 break;
2647 default:
2648 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2649 }
2650 } else {
2651 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2652 }
2653
2654 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2655
2656 switch (pipe_format) {
2657 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2658 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2659 break;
2660 default:
2661 if (first_non_void < 0) {
2662 if (util_format_is_compressed(pipe_format)) {
2663 switch (pipe_format) {
2664 case PIPE_FORMAT_DXT1_SRGB:
2665 case PIPE_FORMAT_DXT1_SRGBA:
2666 case PIPE_FORMAT_DXT3_SRGBA:
2667 case PIPE_FORMAT_DXT5_SRGBA:
2668 case PIPE_FORMAT_BPTC_SRGBA:
2669 case PIPE_FORMAT_ETC2_SRGB8:
2670 case PIPE_FORMAT_ETC2_SRGB8A1:
2671 case PIPE_FORMAT_ETC2_SRGBA8:
2672 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2673 break;
2674 case PIPE_FORMAT_RGTC1_SNORM:
2675 case PIPE_FORMAT_LATC1_SNORM:
2676 case PIPE_FORMAT_RGTC2_SNORM:
2677 case PIPE_FORMAT_LATC2_SNORM:
2678 case PIPE_FORMAT_ETC2_R11_SNORM:
2679 case PIPE_FORMAT_ETC2_RG11_SNORM:
2680 /* implies float, so use SNORM/UNORM to determine
2681 whether data is signed or not */
2682 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2683 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2684 break;
2685 default:
2686 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2687 break;
2688 }
2689 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2690 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2691 } else {
2692 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2693 }
2694 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2695 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2696 } else {
2697 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2698
2699 switch (desc->channel[first_non_void].type) {
2700 case UTIL_FORMAT_TYPE_FLOAT:
2701 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2702 break;
2703 case UTIL_FORMAT_TYPE_SIGNED:
2704 if (desc->channel[first_non_void].normalized)
2705 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2706 else if (desc->channel[first_non_void].pure_integer)
2707 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2708 else
2709 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2710 break;
2711 case UTIL_FORMAT_TYPE_UNSIGNED:
2712 if (desc->channel[first_non_void].normalized)
2713 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2714 else if (desc->channel[first_non_void].pure_integer)
2715 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2716 else
2717 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2718 }
2719 }
2720 }
2721
2722 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2723 if (data_format == ~0) {
2724 data_format = 0;
2725 }
2726
2727 if (!sampler &&
2728 (res->target == PIPE_TEXTURE_CUBE ||
2729 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2730 res->target == PIPE_TEXTURE_3D)) {
2731 /* For the purpose of shader images, treat cube maps and 3D
2732 * textures as 2D arrays. For 3D textures, the address
2733 * calculations for mipmaps are different, so we rely on the
2734 * caller to effectively disable mipmaps.
2735 */
2736 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2737
2738 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2739 } else {
2740 type = si_tex_dim(res->target, target, res->nr_samples);
2741 }
2742
2743 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2744 height = 1;
2745 depth = res->array_size;
2746 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2747 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2748 if (sampler || res->target != PIPE_TEXTURE_3D)
2749 depth = res->array_size;
2750 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2751 depth = res->array_size / 6;
2752
2753 state[0] = 0;
2754 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2755 S_008F14_NUM_FORMAT(num_format));
2756 state[2] = (S_008F18_WIDTH(width - 1) |
2757 S_008F18_HEIGHT(height - 1));
2758 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2759 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2760 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2761 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2762 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2763 0 : first_level) |
2764 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2765 util_logbase2(res->nr_samples) :
2766 last_level) |
2767 S_008F1C_POW2_PAD(res->last_level > 0) |
2768 S_008F1C_TYPE(type));
2769 state[4] = S_008F20_DEPTH(depth - 1);
2770 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2771 S_008F24_LAST_ARRAY(last_layer));
2772 state[6] = 0;
2773 state[7] = 0;
2774
2775 if (tex->dcc_offset) {
2776 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2777
2778 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2779 } else {
2780 /* The last dword is unused by hw. The shader uses it to clear
2781 * bits in the first dword of sampler state.
2782 */
2783 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2784 if (first_level == last_level)
2785 state[7] = C_008F30_MAX_ANISO_RATIO;
2786 else
2787 state[7] = 0xffffffff;
2788 }
2789 }
2790
2791 /* Initialize the sampler view for FMASK. */
2792 if (tex->fmask.size) {
2793 uint32_t fmask_format;
2794
2795 va = tex->resource.gpu_address + tex->fmask.offset;
2796
2797 switch (res->nr_samples) {
2798 case 2:
2799 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2800 break;
2801 case 4:
2802 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2803 break;
2804 case 8:
2805 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2806 break;
2807 default:
2808 assert(0);
2809 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2810 }
2811
2812 fmask_state[0] = va >> 8;
2813 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2814 S_008F14_DATA_FORMAT(fmask_format) |
2815 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2816 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2817 S_008F18_HEIGHT(height - 1);
2818 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2819 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2820 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2821 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2822 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2823 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2824 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2825 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2826 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2827 S_008F24_LAST_ARRAY(last_layer);
2828 fmask_state[6] = 0;
2829 fmask_state[7] = 0;
2830 }
2831 }
2832
2833 /**
2834 * Create a sampler view.
2835 *
2836 * @param ctx context
2837 * @param texture texture
2838 * @param state sampler view template
2839 * @param width0 width0 override (for compressed textures as int)
2840 * @param height0 height0 override (for compressed textures as int)
2841 * @param force_level set the base address to the level (for compressed textures)
2842 */
2843 struct pipe_sampler_view *
2844 si_create_sampler_view_custom(struct pipe_context *ctx,
2845 struct pipe_resource *texture,
2846 const struct pipe_sampler_view *state,
2847 unsigned width0, unsigned height0,
2848 unsigned force_level)
2849 {
2850 struct si_context *sctx = (struct si_context*)ctx;
2851 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2852 struct r600_texture *tmp = (struct r600_texture*)texture;
2853 unsigned base_level, first_level, last_level;
2854 unsigned char state_swizzle[4];
2855 unsigned height, depth, width;
2856 unsigned last_layer = state->u.tex.last_layer;
2857 enum pipe_format pipe_format;
2858 const struct radeon_surf_level *surflevel;
2859
2860 if (!view)
2861 return NULL;
2862
2863 /* initialize base object */
2864 view->base = *state;
2865 view->base.texture = NULL;
2866 view->base.reference.count = 1;
2867 view->base.context = ctx;
2868
2869 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2870 if (!texture) {
2871 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2872 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2873 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2874 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2875 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2876 return &view->base;
2877 }
2878
2879 pipe_resource_reference(&view->base.texture, texture);
2880
2881 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2882 state->format == PIPE_FORMAT_S8X24_UINT ||
2883 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2884 state->format == PIPE_FORMAT_S8_UINT)
2885 view->is_stencil_sampler = true;
2886
2887 /* Buffer resource. */
2888 if (texture->target == PIPE_BUFFER) {
2889 si_make_buffer_descriptor(sctx->screen,
2890 (struct r600_resource *)texture,
2891 state->format,
2892 state->u.buf.first_element,
2893 state->u.buf.last_element,
2894 view->state);
2895
2896 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2897 return &view->base;
2898 }
2899
2900 state_swizzle[0] = state->swizzle_r;
2901 state_swizzle[1] = state->swizzle_g;
2902 state_swizzle[2] = state->swizzle_b;
2903 state_swizzle[3] = state->swizzle_a;
2904
2905 base_level = 0;
2906 first_level = state->u.tex.first_level;
2907 last_level = state->u.tex.last_level;
2908 width = width0;
2909 height = height0;
2910 depth = texture->depth0;
2911
2912 if (force_level) {
2913 assert(force_level == first_level &&
2914 force_level == last_level);
2915 base_level = force_level;
2916 first_level = 0;
2917 last_level = 0;
2918 width = u_minify(width, force_level);
2919 height = u_minify(height, force_level);
2920 depth = u_minify(depth, force_level);
2921 }
2922
2923 /* This is not needed if state trackers set last_layer correctly. */
2924 if (state->target == PIPE_TEXTURE_1D ||
2925 state->target == PIPE_TEXTURE_2D ||
2926 state->target == PIPE_TEXTURE_RECT ||
2927 state->target == PIPE_TEXTURE_CUBE)
2928 last_layer = state->u.tex.first_layer;
2929
2930 /* Texturing with separate depth and stencil. */
2931 pipe_format = state->format;
2932 surflevel = tmp->surface.level;
2933
2934 if (tmp->is_depth && !tmp->is_flushing_texture) {
2935 switch (pipe_format) {
2936 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2937 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2938 break;
2939 case PIPE_FORMAT_X8Z24_UNORM:
2940 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2941 /* Z24 is always stored like this. */
2942 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2943 break;
2944 case PIPE_FORMAT_X24S8_UINT:
2945 case PIPE_FORMAT_S8X24_UINT:
2946 case PIPE_FORMAT_X32_S8X24_UINT:
2947 pipe_format = PIPE_FORMAT_S8_UINT;
2948 surflevel = tmp->surface.stencil_level;
2949 break;
2950 default:;
2951 }
2952 }
2953
2954 si_make_texture_descriptor(sctx->screen, tmp, true,
2955 state->target, pipe_format, state_swizzle,
2956 first_level, last_level,
2957 state->u.tex.first_layer, last_layer,
2958 width, height, depth,
2959 view->state, view->fmask_state);
2960
2961 view->base_level_info = &surflevel[base_level];
2962 view->base_level = base_level;
2963 view->block_width = util_format_get_blockwidth(pipe_format);
2964 return &view->base;
2965 }
2966
2967 static struct pipe_sampler_view *
2968 si_create_sampler_view(struct pipe_context *ctx,
2969 struct pipe_resource *texture,
2970 const struct pipe_sampler_view *state)
2971 {
2972 return si_create_sampler_view_custom(ctx, texture, state,
2973 texture ? texture->width0 : 0,
2974 texture ? texture->height0 : 0, 0);
2975 }
2976
2977 static void si_sampler_view_destroy(struct pipe_context *ctx,
2978 struct pipe_sampler_view *state)
2979 {
2980 struct si_sampler_view *view = (struct si_sampler_view *)state;
2981
2982 if (state->texture && state->texture->target == PIPE_BUFFER)
2983 LIST_DELINIT(&view->list);
2984
2985 pipe_resource_reference(&state->texture, NULL);
2986 FREE(view);
2987 }
2988
2989 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2990 {
2991 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2992 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2993 (linear_filter &&
2994 (wrap == PIPE_TEX_WRAP_CLAMP ||
2995 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2996 }
2997
2998 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2999 {
3000 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3001 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3002
3003 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3004 state->border_color.ui[2] || state->border_color.ui[3]) &&
3005 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3006 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3007 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3008 }
3009
3010 static void *si_create_sampler_state(struct pipe_context *ctx,
3011 const struct pipe_sampler_state *state)
3012 {
3013 struct si_context *sctx = (struct si_context *)ctx;
3014 struct r600_common_screen *rscreen = sctx->b.screen;
3015 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3016 unsigned border_color_type, border_color_index = 0;
3017 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3018 : state->max_anisotropy;
3019 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3020
3021 if (!rstate) {
3022 return NULL;
3023 }
3024
3025 if (!sampler_state_needs_border_color(state))
3026 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3027 else if (state->border_color.f[0] == 0 &&
3028 state->border_color.f[1] == 0 &&
3029 state->border_color.f[2] == 0 &&
3030 state->border_color.f[3] == 0)
3031 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3032 else if (state->border_color.f[0] == 0 &&
3033 state->border_color.f[1] == 0 &&
3034 state->border_color.f[2] == 0 &&
3035 state->border_color.f[3] == 1)
3036 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3037 else if (state->border_color.f[0] == 1 &&
3038 state->border_color.f[1] == 1 &&
3039 state->border_color.f[2] == 1 &&
3040 state->border_color.f[3] == 1)
3041 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3042 else {
3043 int i;
3044
3045 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3046
3047 /* Check if the border has been uploaded already. */
3048 for (i = 0; i < sctx->border_color_count; i++)
3049 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3050 sizeof(state->border_color)) == 0)
3051 break;
3052
3053 if (i >= SI_MAX_BORDER_COLORS) {
3054 /* Getting 4096 unique border colors is very unlikely. */
3055 fprintf(stderr, "radeonsi: The border color table is full. "
3056 "Any new border colors will be just black. "
3057 "Please file a bug.\n");
3058 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3059 } else {
3060 if (i == sctx->border_color_count) {
3061 /* Upload a new border color. */
3062 memcpy(&sctx->border_color_table[i], &state->border_color,
3063 sizeof(state->border_color));
3064 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3065 &state->border_color,
3066 sizeof(state->border_color));
3067 sctx->border_color_count++;
3068 }
3069
3070 border_color_index = i;
3071 }
3072 }
3073
3074 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3075 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3076 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3077 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3078 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3079 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3080 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3081 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3082 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3083 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3084 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3085 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3086 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3087 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3088 S_008F38_MIP_POINT_PRECLAMP(1) |
3089 S_008F38_DISABLE_LSB_CEIL(1) |
3090 S_008F38_FILTER_PREC_FIX(1) |
3091 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3092 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3093 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3094 return rstate;
3095 }
3096
3097 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3098 {
3099 struct si_context *sctx = (struct si_context *)ctx;
3100
3101 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3102 return;
3103
3104 sctx->sample_mask.sample_mask = sample_mask;
3105 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3106 }
3107
3108 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3109 {
3110 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3111 unsigned mask = sctx->sample_mask.sample_mask;
3112
3113 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3114 radeon_emit(cs, mask | (mask << 16));
3115 radeon_emit(cs, mask | (mask << 16));
3116 }
3117
3118 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3119 {
3120 free(state);
3121 }
3122
3123 /*
3124 * Vertex elements & buffers
3125 */
3126
3127 static void *si_create_vertex_elements(struct pipe_context *ctx,
3128 unsigned count,
3129 const struct pipe_vertex_element *elements)
3130 {
3131 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3132 int i;
3133
3134 assert(count <= SI_MAX_ATTRIBS);
3135 if (!v)
3136 return NULL;
3137
3138 v->count = count;
3139 for (i = 0; i < count; ++i) {
3140 const struct util_format_description *desc;
3141 unsigned data_format, num_format;
3142 int first_non_void;
3143
3144 desc = util_format_description(elements[i].src_format);
3145 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3146 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3147 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3148
3149 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3150 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3151 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3152 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3153 S_008F0C_NUM_FORMAT(num_format) |
3154 S_008F0C_DATA_FORMAT(data_format);
3155 v->format_size[i] = desc->block.bits / 8;
3156 }
3157 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3158
3159 return v;
3160 }
3161
3162 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3163 {
3164 struct si_context *sctx = (struct si_context *)ctx;
3165 struct si_vertex_element *v = (struct si_vertex_element*)state;
3166
3167 sctx->vertex_elements = v;
3168 sctx->vertex_buffers_dirty = true;
3169 }
3170
3171 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3172 {
3173 struct si_context *sctx = (struct si_context *)ctx;
3174
3175 if (sctx->vertex_elements == state)
3176 sctx->vertex_elements = NULL;
3177 FREE(state);
3178 }
3179
3180 static void si_set_vertex_buffers(struct pipe_context *ctx,
3181 unsigned start_slot, unsigned count,
3182 const struct pipe_vertex_buffer *buffers)
3183 {
3184 struct si_context *sctx = (struct si_context *)ctx;
3185 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3186 int i;
3187
3188 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3189
3190 if (buffers) {
3191 for (i = 0; i < count; i++) {
3192 const struct pipe_vertex_buffer *src = buffers + i;
3193 struct pipe_vertex_buffer *dsti = dst + i;
3194
3195 pipe_resource_reference(&dsti->buffer, src->buffer);
3196 dsti->buffer_offset = src->buffer_offset;
3197 dsti->stride = src->stride;
3198 r600_context_add_resource_size(ctx, src->buffer);
3199 }
3200 } else {
3201 for (i = 0; i < count; i++) {
3202 pipe_resource_reference(&dst[i].buffer, NULL);
3203 }
3204 }
3205 sctx->vertex_buffers_dirty = true;
3206 }
3207
3208 static void si_set_index_buffer(struct pipe_context *ctx,
3209 const struct pipe_index_buffer *ib)
3210 {
3211 struct si_context *sctx = (struct si_context *)ctx;
3212
3213 if (ib) {
3214 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3215 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3216 r600_context_add_resource_size(ctx, ib->buffer);
3217 } else {
3218 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3219 }
3220 }
3221
3222 /*
3223 * Misc
3224 */
3225
3226 static void si_set_tess_state(struct pipe_context *ctx,
3227 const float default_outer_level[4],
3228 const float default_inner_level[2])
3229 {
3230 struct si_context *sctx = (struct si_context *)ctx;
3231 struct pipe_constant_buffer cb;
3232 float array[8];
3233
3234 memcpy(array, default_outer_level, sizeof(float) * 4);
3235 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3236
3237 cb.buffer = NULL;
3238 cb.user_buffer = NULL;
3239 cb.buffer_size = sizeof(array);
3240
3241 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3242 (void*)array, sizeof(array),
3243 &cb.buffer_offset);
3244
3245 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3246 pipe_resource_reference(&cb.buffer, NULL);
3247 }
3248
3249 static void si_texture_barrier(struct pipe_context *ctx)
3250 {
3251 struct si_context *sctx = (struct si_context *)ctx;
3252
3253 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3254 SI_CONTEXT_INV_GLOBAL_L2 |
3255 SI_CONTEXT_FLUSH_AND_INV_CB |
3256 SI_CONTEXT_CS_PARTIAL_FLUSH;
3257 }
3258
3259 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3260 {
3261 struct si_context *sctx = (struct si_context *)ctx;
3262
3263 /* Subsequent commands must wait for all shader invocations to
3264 * complete. */
3265 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3266 SI_CONTEXT_CS_PARTIAL_FLUSH;
3267
3268 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3269 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3270 SI_CONTEXT_INV_VMEM_L1;
3271
3272 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3273 PIPE_BARRIER_SHADER_BUFFER |
3274 PIPE_BARRIER_TEXTURE |
3275 PIPE_BARRIER_IMAGE |
3276 PIPE_BARRIER_STREAMOUT_BUFFER |
3277 PIPE_BARRIER_GLOBAL_BUFFER)) {
3278 /* As far as I can tell, L1 contents are written back to L2
3279 * automatically at end of shader, but the contents of other
3280 * L1 caches might still be stale. */
3281 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3282 }
3283
3284 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3285 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3286
3287 /* Indices are read through TC L2 since VI. */
3288 if (sctx->screen->b.chip_class <= CIK)
3289 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3290 }
3291
3292 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3293 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3294
3295 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3296 PIPE_BARRIER_FRAMEBUFFER |
3297 PIPE_BARRIER_INDIRECT_BUFFER)) {
3298 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3299 *
3300 * We need to make sure that TC L1 & L2 are written back to
3301 * memory, because neither CPU accesses nor CB fetches consider
3302 * TC, but there's no need to invalidate any TC cache lines. */
3303 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3304 }
3305 }
3306
3307 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3308 {
3309 struct pipe_blend_state blend;
3310
3311 memset(&blend, 0, sizeof(blend));
3312 blend.independent_blend_enable = true;
3313 blend.rt[0].colormask = 0xf;
3314 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3315 }
3316
3317 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3318 bool include_draw_vbo)
3319 {
3320 si_need_cs_space((struct si_context*)ctx);
3321 }
3322
3323 static void si_init_config(struct si_context *sctx);
3324
3325 void si_init_state_functions(struct si_context *sctx)
3326 {
3327 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3328 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3329 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3330 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3331 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3332
3333 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3334 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3335 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3336 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3337 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3338 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3339 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3340 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3341 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3342 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3343 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3344
3345 sctx->b.b.create_blend_state = si_create_blend_state;
3346 sctx->b.b.bind_blend_state = si_bind_blend_state;
3347 sctx->b.b.delete_blend_state = si_delete_blend_state;
3348 sctx->b.b.set_blend_color = si_set_blend_color;
3349
3350 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3351 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3352 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3353
3354 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3355 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3356 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3357
3358 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3359 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3360 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3361 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3362 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3363
3364 sctx->b.b.set_clip_state = si_set_clip_state;
3365 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3366
3367 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3368 sctx->b.b.get_sample_position = cayman_get_sample_position;
3369
3370 sctx->b.b.create_sampler_state = si_create_sampler_state;
3371 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3372
3373 sctx->b.b.create_sampler_view = si_create_sampler_view;
3374 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3375
3376 sctx->b.b.set_sample_mask = si_set_sample_mask;
3377
3378 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3379 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3380 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3381 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3382 sctx->b.b.set_index_buffer = si_set_index_buffer;
3383
3384 sctx->b.b.texture_barrier = si_texture_barrier;
3385 sctx->b.b.memory_barrier = si_memory_barrier;
3386 sctx->b.b.set_min_samples = si_set_min_samples;
3387 sctx->b.b.set_tess_state = si_set_tess_state;
3388
3389 sctx->b.b.set_active_query_state = si_set_active_query_state;
3390 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3391 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3392
3393 sctx->b.b.draw_vbo = si_draw_vbo;
3394
3395 si_init_config(sctx);
3396 }
3397
3398 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3399 {
3400 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3401 }
3402
3403 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3404 struct r600_texture *rtex,
3405 struct radeon_bo_metadata *md)
3406 {
3407 struct si_screen *sscreen = (struct si_screen*)rscreen;
3408 struct pipe_resource *res = &rtex->resource.b.b;
3409 static const unsigned char swizzle[] = {
3410 PIPE_SWIZZLE_X,
3411 PIPE_SWIZZLE_Y,
3412 PIPE_SWIZZLE_Z,
3413 PIPE_SWIZZLE_W
3414 };
3415 uint32_t desc[8], i;
3416 bool is_array = util_resource_is_array_texture(res);
3417
3418 /* DRM 2.x.x doesn't support this. */
3419 if (rscreen->info.drm_major != 3)
3420 return;
3421
3422 assert(rtex->fmask.size == 0);
3423
3424 /* Metadata image format format version 1:
3425 * [0] = 1 (metadata format identifier)
3426 * [1] = (VENDOR_ID << 16) | PCI_ID
3427 * [2:9] = image descriptor for the whole resource
3428 * [2] is always 0, because the base address is cleared
3429 * [9] is the DCC offset bits [39:8] from the beginning of
3430 * the buffer
3431 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3432 */
3433
3434 md->metadata[0] = 1; /* metadata image format version 1 */
3435
3436 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3437 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3438
3439 si_make_texture_descriptor(sscreen, rtex, true,
3440 res->target, res->format,
3441 swizzle, 0, res->last_level, 0,
3442 is_array ? res->array_size - 1 : 0,
3443 res->width0, res->height0, res->depth0,
3444 desc, NULL);
3445
3446 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0,
3447 rtex->surface.blk_w, false, desc);
3448
3449 /* Clear the base address and set the relative DCC offset. */
3450 desc[0] = 0;
3451 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3452 desc[7] = rtex->dcc_offset >> 8;
3453
3454 /* Dwords [2:9] contain the image descriptor. */
3455 memcpy(&md->metadata[2], desc, sizeof(desc));
3456
3457 /* Dwords [10:..] contain the mipmap level offsets. */
3458 for (i = 0; i <= res->last_level; i++)
3459 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3460
3461 md->size_metadata = (11 + res->last_level) * 4;
3462 }
3463
3464 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3465 struct r600_texture *rtex,
3466 struct radeon_bo_metadata *md)
3467 {
3468 uint32_t *desc = &md->metadata[2];
3469
3470 if (rscreen->chip_class < VI)
3471 return;
3472
3473 /* Return if DCC is enabled. The texture should be set up with it
3474 * already.
3475 */
3476 if (md->size_metadata >= 11 * 4 &&
3477 md->metadata[0] != 0 &&
3478 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3479 G_008F28_COMPRESSION_EN(desc[6])) {
3480 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3481 return;
3482 }
3483
3484 /* Disable DCC. These are always set by texture_from_handle and must
3485 * be cleared here.
3486 */
3487 rtex->dcc_offset = 0;
3488 rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
3489 }
3490
3491 void si_init_screen_state_functions(struct si_screen *sscreen)
3492 {
3493 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3494 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3495 }
3496
3497 static void
3498 si_write_harvested_raster_configs(struct si_context *sctx,
3499 struct si_pm4_state *pm4,
3500 unsigned raster_config,
3501 unsigned raster_config_1)
3502 {
3503 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3504 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3505 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3506 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3507 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3508 unsigned rb_per_se = num_rb / num_se;
3509 unsigned se_mask[4];
3510 unsigned se;
3511
3512 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3513 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3514 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3515 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3516
3517 assert(num_se == 1 || num_se == 2 || num_se == 4);
3518 assert(sh_per_se == 1 || sh_per_se == 2);
3519 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3520
3521 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3522 * fields are for, so I'm leaving them as their default
3523 * values. */
3524
3525 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3526 (!se_mask[2] && !se_mask[3]))) {
3527 raster_config_1 &= C_028354_SE_PAIR_MAP;
3528
3529 if (!se_mask[0] && !se_mask[1]) {
3530 raster_config_1 |=
3531 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3532 } else {
3533 raster_config_1 |=
3534 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3535 }
3536 }
3537
3538 for (se = 0; se < num_se; se++) {
3539 unsigned raster_config_se = raster_config;
3540 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3541 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3542 int idx = (se / 2) * 2;
3543
3544 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3545 raster_config_se &= C_028350_SE_MAP;
3546
3547 if (!se_mask[idx]) {
3548 raster_config_se |=
3549 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3550 } else {
3551 raster_config_se |=
3552 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3553 }
3554 }
3555
3556 pkr0_mask &= rb_mask;
3557 pkr1_mask &= rb_mask;
3558 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3559 raster_config_se &= C_028350_PKR_MAP;
3560
3561 if (!pkr0_mask) {
3562 raster_config_se |=
3563 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3564 } else {
3565 raster_config_se |=
3566 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3567 }
3568 }
3569
3570 if (rb_per_se >= 2) {
3571 unsigned rb0_mask = 1 << (se * rb_per_se);
3572 unsigned rb1_mask = rb0_mask << 1;
3573
3574 rb0_mask &= rb_mask;
3575 rb1_mask &= rb_mask;
3576 if (!rb0_mask || !rb1_mask) {
3577 raster_config_se &= C_028350_RB_MAP_PKR0;
3578
3579 if (!rb0_mask) {
3580 raster_config_se |=
3581 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3582 } else {
3583 raster_config_se |=
3584 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3585 }
3586 }
3587
3588 if (rb_per_se > 2) {
3589 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3590 rb1_mask = rb0_mask << 1;
3591 rb0_mask &= rb_mask;
3592 rb1_mask &= rb_mask;
3593 if (!rb0_mask || !rb1_mask) {
3594 raster_config_se &= C_028350_RB_MAP_PKR1;
3595
3596 if (!rb0_mask) {
3597 raster_config_se |=
3598 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3599 } else {
3600 raster_config_se |=
3601 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3602 }
3603 }
3604 }
3605 }
3606
3607 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3608 if (sctx->b.chip_class < CIK)
3609 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3610 SE_INDEX(se) | SH_BROADCAST_WRITES |
3611 INSTANCE_BROADCAST_WRITES);
3612 else
3613 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3614 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3615 S_030800_INSTANCE_BROADCAST_WRITES(1));
3616 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3617 if (sctx->b.chip_class >= CIK)
3618 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3619 }
3620
3621 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3622 if (sctx->b.chip_class < CIK)
3623 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3624 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3625 INSTANCE_BROADCAST_WRITES);
3626 else
3627 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3628 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3629 S_030800_INSTANCE_BROADCAST_WRITES(1));
3630 }
3631
3632 static void si_init_config(struct si_context *sctx)
3633 {
3634 struct si_screen *sscreen = sctx->screen;
3635 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3636 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3637 unsigned raster_config, raster_config_1;
3638 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3639 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3640 int i;
3641
3642 if (!pm4)
3643 return;
3644
3645 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3646 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3647 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3648 si_pm4_cmd_end(pm4, false);
3649
3650 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3651 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3652
3653 /* FIXME calculate these values somehow ??? */
3654 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3655 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3656 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3657
3658 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3659 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3660
3661 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3662 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3663 if (sctx->b.chip_class < CIK)
3664 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3665 S_008A14_CLIP_VTX_REORDER_ENA(1));
3666
3667 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3668 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3669
3670 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3671
3672 for (i = 0; i < 16; i++) {
3673 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3674 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3675 }
3676
3677 switch (sctx->screen->b.family) {
3678 case CHIP_TAHITI:
3679 case CHIP_PITCAIRN:
3680 raster_config = 0x2a00126a;
3681 raster_config_1 = 0x00000000;
3682 break;
3683 case CHIP_VERDE:
3684 raster_config = 0x0000124a;
3685 raster_config_1 = 0x00000000;
3686 break;
3687 case CHIP_OLAND:
3688 raster_config = 0x00000082;
3689 raster_config_1 = 0x00000000;
3690 break;
3691 case CHIP_HAINAN:
3692 raster_config = 0x00000000;
3693 raster_config_1 = 0x00000000;
3694 break;
3695 case CHIP_BONAIRE:
3696 raster_config = 0x16000012;
3697 raster_config_1 = 0x00000000;
3698 break;
3699 case CHIP_HAWAII:
3700 raster_config = 0x3a00161a;
3701 raster_config_1 = 0x0000002e;
3702 break;
3703 case CHIP_FIJI:
3704 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3705 /* old kernels with old tiling config */
3706 raster_config = 0x16000012;
3707 raster_config_1 = 0x0000002a;
3708 } else {
3709 raster_config = 0x3a00161a;
3710 raster_config_1 = 0x0000002e;
3711 }
3712 break;
3713 case CHIP_POLARIS10:
3714 raster_config = 0x16000012;
3715 raster_config_1 = 0x0000002a;
3716 break;
3717 case CHIP_POLARIS11:
3718 raster_config = 0x16000012;
3719 raster_config_1 = 0x00000000;
3720 break;
3721 case CHIP_TONGA:
3722 raster_config = 0x16000012;
3723 raster_config_1 = 0x0000002a;
3724 break;
3725 case CHIP_ICELAND:
3726 if (num_rb == 1)
3727 raster_config = 0x00000000;
3728 else
3729 raster_config = 0x00000002;
3730 raster_config_1 = 0x00000000;
3731 break;
3732 case CHIP_CARRIZO:
3733 raster_config = 0x00000002;
3734 raster_config_1 = 0x00000000;
3735 break;
3736 case CHIP_KAVERI:
3737 /* KV should be 0x00000002, but that causes problems with radeon */
3738 raster_config = 0x00000000; /* 0x00000002 */
3739 raster_config_1 = 0x00000000;
3740 break;
3741 case CHIP_KABINI:
3742 case CHIP_MULLINS:
3743 case CHIP_STONEY:
3744 raster_config = 0x00000000;
3745 raster_config_1 = 0x00000000;
3746 break;
3747 default:
3748 fprintf(stderr,
3749 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3750 raster_config = 0x00000000;
3751 raster_config_1 = 0x00000000;
3752 break;
3753 }
3754
3755 /* Always use the default config when all backends are enabled
3756 * (or when we failed to determine the enabled backends).
3757 */
3758 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3759 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3760 raster_config);
3761 if (sctx->b.chip_class >= CIK)
3762 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3763 raster_config_1);
3764 } else {
3765 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3766 }
3767
3768 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3769 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3770 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3771 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3772 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3773 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3774 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3775
3776 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3777 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3778 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3779 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3780 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3781 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3782 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3783 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3784 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3785 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3786 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3787
3788 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3789 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3790 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3791
3792 if (sctx->b.chip_class >= CIK) {
3793 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3794 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3795 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3796
3797 if (sscreen->b.info.num_good_compute_units /
3798 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3799 /* Too few available compute units per SH. Disallowing
3800 * VS to run on CU0 could hurt us more than late VS
3801 * allocation would help.
3802 *
3803 * LATE_ALLOC_VS = 2 is the highest safe number.
3804 */
3805 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3806 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3807 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3808 } else {
3809 /* Set LATE_ALLOC_VS == 31. It should be less than
3810 * the number of scratch waves. Limitations:
3811 * - VS can't execute on CU0.
3812 * - If HS writes outputs to LDS, LS can't execute on CU0.
3813 */
3814 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3815 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3816 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3817 }
3818
3819 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3820 }
3821
3822 if (sctx->b.chip_class >= VI) {
3823 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3824 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3825 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3826 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3827 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3828 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
3829 S_028B50_ACCUM_ISOLINE(32) |
3830 S_028B50_ACCUM_TRI(11) |
3831 S_028B50_ACCUM_QUAD(11) |
3832 S_028B50_DONUT_SPLIT(16));
3833 }
3834
3835 if (sctx->b.family == CHIP_STONEY)
3836 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3837
3838 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3839 if (sctx->b.chip_class >= CIK)
3840 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3841 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3842 RADEON_PRIO_BORDER_COLORS);
3843
3844 si_pm4_upload_indirect_buffer(sctx, pm4);
3845 sctx->init_config = pm4;
3846 }