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radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORM
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x)
79 {
80 return x <= 0 ? 0 :
81 x >= 4096 ? 0xffff : x * 16;
82 }
83
84 /*
85 * Inferred framebuffer and blender state.
86 *
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
89 */
90 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
91 {
92 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
93 struct si_state_blend *blend = sctx->queued.named.blend;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
97 unsigned i;
98
99 if (blend)
100 cb_target_mask &= blend->cb_target_mask;
101
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
105 *
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
107 */
108 if (blend && blend->dual_src_blend &&
109 sctx->ps_shader.cso &&
110 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
111 cb_target_mask = 0;
112
113 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
114
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
117 */
118 if (sctx->screen->dfsm_allowed &&
119 sctx->last_cb_target_mask != cb_target_mask) {
120 sctx->last_cb_target_mask = cb_target_mask;
121
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->b.rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_028C70_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_028C70_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_028C70_SWAP_STD ||
228 swap == V_028C70_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx->screen->b.has_rbplus) {
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 }
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 R600_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 static void si_blend_check_commutativity(struct si_screen *sscreen,
381 struct si_state_blend *blend,
382 enum pipe_blend_func func,
383 enum pipe_blendfactor src,
384 enum pipe_blendfactor dst,
385 unsigned chanmask)
386 {
387 /* Src factor is allowed when it does not depend on Dst */
388 static const uint32_t src_allowed =
389 (1u << PIPE_BLENDFACTOR_ONE) |
390 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
392 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
393 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
397 (1u << PIPE_BLENDFACTOR_ZERO) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
399 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
401 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
403 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
404
405 if (dst == PIPE_BLENDFACTOR_ONE &&
406 (src_allowed & (1u << src))) {
407 /* Addition is commutative, but floating point addition isn't
408 * associative: subtle changes can be introduced via different
409 * rounding.
410 *
411 * Out-of-order is also non-deterministic, which means that
412 * this breaks OpenGL invariance requirements. So only enable
413 * out-of-order additive blending if explicitly allowed by a
414 * setting.
415 */
416 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
417 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
418 blend->commutative_4bit |= chanmask;
419 }
420 }
421
422 /**
423 * Get rid of DST in the blend factors by commuting the operands:
424 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
425 */
426 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
427 unsigned *dst_factor, unsigned expected_dst,
428 unsigned replacement_src)
429 {
430 if (*src_factor == expected_dst &&
431 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
432 *src_factor = PIPE_BLENDFACTOR_ZERO;
433 *dst_factor = replacement_src;
434
435 /* Commuting the operands requires reversing subtractions. */
436 if (*func == PIPE_BLEND_SUBTRACT)
437 *func = PIPE_BLEND_REVERSE_SUBTRACT;
438 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
439 *func = PIPE_BLEND_SUBTRACT;
440 }
441 }
442
443 static bool si_blend_factor_uses_dst(unsigned factor)
444 {
445 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
446 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
447 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
448 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
449 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
450 }
451
452 static void *si_create_blend_state_mode(struct pipe_context *ctx,
453 const struct pipe_blend_state *state,
454 unsigned mode)
455 {
456 struct si_context *sctx = (struct si_context*)ctx;
457 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
458 struct si_pm4_state *pm4 = &blend->pm4;
459 uint32_t sx_mrt_blend_opt[8] = {0};
460 uint32_t color_control = 0;
461
462 if (!blend)
463 return NULL;
464
465 blend->alpha_to_coverage = state->alpha_to_coverage;
466 blend->alpha_to_one = state->alpha_to_one;
467 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
468 blend->logicop_enable = state->logicop_enable;
469
470 if (state->logicop_enable) {
471 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
472 } else {
473 color_control |= S_028808_ROP3(0xcc);
474 }
475
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
477 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
478 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
480 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
481 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < 8; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
506
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i >= 1 && blend->dual_src_blend) {
509 /* Vulkan does this for dual source blending. */
510 if (i == 1)
511 blend_cntl |= S_028780_ENABLE(1);
512
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
519 */
520 if (blend->dual_src_blend &&
521 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
522 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* cb_render_state will disable unused ones */
529 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
530 if (state->rt[j].colormask)
531 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
532
533 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
535 continue;
536 }
537
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
540 si_blend_check_commutativity(sctx->screen, blend,
541 eqA, srcA, dstA, 0x8 << (4 * i));
542
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
545 *
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 */
549 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_COLOR,
554 PIPE_BLENDFACTOR_SRC_COLOR);
555 si_blend_remove_dst(&eqA, &srcA, &dstA,
556 PIPE_BLENDFACTOR_DST_ALPHA,
557 PIPE_BLENDFACTOR_SRC_ALPHA);
558
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
561 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
562 srcA_opt = si_translate_blend_opt_factor(srcA, true);
563 dstA_opt = si_translate_blend_opt_factor(dstA, true);
564
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568 if (si_blend_factor_uses_dst(srcA))
569 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
570
571 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
572 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
574 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
576
577 /* Set the final value. */
578 sx_mrt_blend_opt[i] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt) |
583 S_028760_ALPHA_DST_OPT(dstA_opt) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
585
586 /* Set blend state. */
587 blend_cntl |= S_028780_ENABLE(1);
588 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
589 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
590 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
591
592 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
593 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
595 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
596 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
597 }
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599
600 blend->blend_enable_4bit |= 0xfu << (i * 4);
601
602 /* This is only important for formats without alpha. */
603 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
605 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
607 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
608 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
609 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
610 }
611
612 if (blend->cb_target_mask) {
613 color_control |= S_028808_MODE(mode);
614 } else {
615 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
616 }
617
618 if (sctx->screen->b.has_rbplus) {
619 /* Disable RB+ blend optimizations for dual source blending.
620 * Vulkan does this.
621 */
622 if (blend->dual_src_blend) {
623 for (int i = 0; i < 8; i++) {
624 sx_mrt_blend_opt[i] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
627 }
628 }
629
630 for (int i = 0; i < 8; i++)
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
632 sx_mrt_blend_opt[i]);
633
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend->dual_src_blend || state->logicop_enable ||
636 mode == V_028808_CB_RESOLVE)
637 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
638 }
639
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
641 return blend;
642 }
643
644 static void *si_create_blend_state(struct pipe_context *ctx,
645 const struct pipe_blend_state *state)
646 {
647 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
648 }
649
650 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 struct si_state_blend *old_blend = sctx->queued.named.blend;
654 struct si_state_blend *blend = (struct si_state_blend *)state;
655
656 if (!state)
657 return;
658
659 if (!old_blend ||
660 old_blend->cb_target_mask != blend->cb_target_mask ||
661 old_blend->dual_src_blend != blend->dual_src_blend)
662 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
663
664 si_pm4_bind_state(sctx, blend, state);
665
666 if (!old_blend ||
667 old_blend->cb_target_mask != blend->cb_target_mask ||
668 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
669 old_blend->alpha_to_one != blend->alpha_to_one ||
670 old_blend->dual_src_blend != blend->dual_src_blend ||
671 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
672 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
673 sctx->do_update_shaders = true;
674
675 if (sctx->screen->dpbb_allowed &&
676 (!old_blend ||
677 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
678 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
679 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
680 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
681
682 if (sctx->screen->has_out_of_order_rast &&
683 (!old_blend ||
684 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
685 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
686 old_blend->commutative_4bit != blend->commutative_4bit ||
687 old_blend->logicop_enable != blend->logicop_enable)))
688 si_mark_atom_dirty(sctx, &sctx->msaa_config);
689 }
690
691 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
692 {
693 struct si_context *sctx = (struct si_context *)ctx;
694 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
695 }
696
697 static void si_set_blend_color(struct pipe_context *ctx,
698 const struct pipe_blend_color *state)
699 {
700 struct si_context *sctx = (struct si_context *)ctx;
701 static const struct pipe_blend_color zeros;
702
703 sctx->blend_color.state = *state;
704 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
705 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
706 }
707
708 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
709 {
710 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
711
712 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
713 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
714 }
715
716 /*
717 * Clipping
718 */
719
720 static void si_set_clip_state(struct pipe_context *ctx,
721 const struct pipe_clip_state *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 struct pipe_constant_buffer cb;
725 static const struct pipe_clip_state zeros;
726
727 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
728 return;
729
730 sctx->clip_state.state = *state;
731 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
732 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
733
734 cb.buffer = NULL;
735 cb.user_buffer = state->ucp;
736 cb.buffer_offset = 0;
737 cb.buffer_size = 4*4*8;
738 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
739 pipe_resource_reference(&cb.buffer, NULL);
740 }
741
742 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
743 {
744 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
745
746 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
747 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
748 }
749
750 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
751 {
752 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
753 struct si_shader *vs = si_get_vs_state(sctx);
754 struct si_shader_selector *vs_sel = vs->selector;
755 struct tgsi_shader_info *info = &vs_sel->info;
756 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
757 unsigned window_space =
758 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
759 unsigned clipdist_mask = vs_sel->clipdist_mask;
760 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
761 unsigned culldist_mask = vs_sel->culldist_mask;
762 unsigned total_mask;
763
764 if (vs->key.opt.clip_disable) {
765 assert(!info->culldist_writemask);
766 clipdist_mask = 0;
767 culldist_mask = 0;
768 }
769 total_mask = clipdist_mask | culldist_mask;
770
771 /* Clip distances on points have no effect, so need to be implemented
772 * as cull distances. This applies for the clipvertex case as well.
773 *
774 * Setting this for primitives other than points should have no adverse
775 * effects.
776 */
777 clipdist_mask &= rs->clip_plane_enable;
778 culldist_mask |= clipdist_mask;
779
780 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
781 vs_sel->pa_cl_vs_out_cntl |
782 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
783 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
784 clipdist_mask | (culldist_mask << 8));
785 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
786 rs->pa_cl_clip_cntl |
787 ucp_mask |
788 S_028810_CLIP_DISABLE(window_space));
789 }
790
791 /*
792 * inferred state between framebuffer and rasterizer
793 */
794 static void si_update_poly_offset_state(struct si_context *sctx)
795 {
796 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
797
798 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
799 si_pm4_bind_state(sctx, poly_offset, NULL);
800 return;
801 }
802
803 /* Use the user format, not db_render_format, so that the polygon
804 * offset behaves as expected by applications.
805 */
806 switch (sctx->framebuffer.state.zsbuf->texture->format) {
807 case PIPE_FORMAT_Z16_UNORM:
808 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
809 break;
810 default: /* 24-bit */
811 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
812 break;
813 case PIPE_FORMAT_Z32_FLOAT:
814 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
815 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
816 break;
817 }
818 }
819
820 /*
821 * Rasterizer
822 */
823
824 static uint32_t si_translate_fill(uint32_t func)
825 {
826 switch(func) {
827 case PIPE_POLYGON_MODE_FILL:
828 return V_028814_X_DRAW_TRIANGLES;
829 case PIPE_POLYGON_MODE_LINE:
830 return V_028814_X_DRAW_LINES;
831 case PIPE_POLYGON_MODE_POINT:
832 return V_028814_X_DRAW_POINTS;
833 default:
834 assert(0);
835 return V_028814_X_DRAW_POINTS;
836 }
837 }
838
839 static void *si_create_rs_state(struct pipe_context *ctx,
840 const struct pipe_rasterizer_state *state)
841 {
842 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
843 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
844 struct si_pm4_state *pm4 = &rs->pm4;
845 unsigned tmp, i;
846 float psize_min, psize_max;
847
848 if (!rs) {
849 return NULL;
850 }
851
852 rs->scissor_enable = state->scissor;
853 rs->clip_halfz = state->clip_halfz;
854 rs->two_side = state->light_twoside;
855 rs->multisample_enable = state->multisample;
856 rs->force_persample_interp = state->force_persample_interp;
857 rs->clip_plane_enable = state->clip_plane_enable;
858 rs->line_stipple_enable = state->line_stipple_enable;
859 rs->poly_stipple_enable = state->poly_stipple_enable;
860 rs->line_smooth = state->line_smooth;
861 rs->line_width = state->line_width;
862 rs->poly_smooth = state->poly_smooth;
863 rs->uses_poly_offset = state->offset_point || state->offset_line ||
864 state->offset_tri;
865 rs->clamp_fragment_color = state->clamp_fragment_color;
866 rs->clamp_vertex_color = state->clamp_vertex_color;
867 rs->flatshade = state->flatshade;
868 rs->sprite_coord_enable = state->sprite_coord_enable;
869 rs->rasterizer_discard = state->rasterizer_discard;
870 rs->pa_sc_line_stipple = state->line_stipple_enable ?
871 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
872 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
873 rs->pa_cl_clip_cntl =
874 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
875 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
876 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
877 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
878 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
879
880 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
881 S_0286D4_FLAT_SHADE_ENA(1) |
882 S_0286D4_PNT_SPRITE_ENA(1) |
883 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
884 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
885 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
886 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
887 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
888
889 /* point size 12.4 fixed point */
890 tmp = (unsigned)(state->point_size * 8.0);
891 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
892
893 if (state->point_size_per_vertex) {
894 psize_min = util_get_min_point_size(state);
895 psize_max = 8192;
896 } else {
897 /* Force the point size to be as if the vertex output was disabled. */
898 psize_min = state->point_size;
899 psize_max = state->point_size;
900 }
901 rs->max_point_size = psize_max;
902
903 /* Divide by two, because 0.5 = 1 pixel. */
904 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
905 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
906 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
907
908 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
909 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
910 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
911 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
912 S_028A48_MSAA_ENABLE(state->multisample ||
913 state->poly_smooth ||
914 state->line_smooth) |
915 S_028A48_VPORT_SCISSOR_ENABLE(1) |
916 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
917
918 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
919 S_028BE4_PIX_CENTER(state->half_pixel_center) |
920 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
921
922 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
923 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
924 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
925 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
926 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
927 S_028814_FACE(!state->front_ccw) |
928 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
929 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
930 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
931 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
932 state->fill_back != PIPE_POLYGON_MODE_FILL) |
933 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
934 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
935
936 if (!rs->uses_poly_offset)
937 return rs;
938
939 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
940 if (!rs->pm4_poly_offset) {
941 FREE(rs);
942 return NULL;
943 }
944
945 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
946 for (i = 0; i < 3; i++) {
947 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
948 float offset_units = state->offset_units;
949 float offset_scale = state->offset_scale * 16.0f;
950 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
951
952 if (!state->offset_units_unscaled) {
953 switch (i) {
954 case 0: /* 16-bit zbuffer */
955 offset_units *= 4.0f;
956 pa_su_poly_offset_db_fmt_cntl =
957 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
958 break;
959 case 1: /* 24-bit zbuffer */
960 offset_units *= 2.0f;
961 pa_su_poly_offset_db_fmt_cntl =
962 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
963 break;
964 case 2: /* 32-bit zbuffer */
965 offset_units *= 1.0f;
966 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
967 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
968 break;
969 }
970 }
971
972 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
973 fui(offset_scale));
974 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
975 fui(offset_units));
976 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
977 fui(offset_scale));
978 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
979 fui(offset_units));
980 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
981 pa_su_poly_offset_db_fmt_cntl);
982 }
983
984 return rs;
985 }
986
987 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
988 {
989 struct si_context *sctx = (struct si_context *)ctx;
990 struct si_state_rasterizer *old_rs =
991 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
992 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
993
994 if (!state)
995 return;
996
997 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
998 si_mark_atom_dirty(sctx, &sctx->db_render_state);
999
1000 /* Update the small primitive filter workaround if necessary. */
1001 if (sctx->screen->has_msaa_sample_loc_bug &&
1002 sctx->framebuffer.nr_samples > 1)
1003 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1004 }
1005
1006 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1007 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1008
1009 si_pm4_bind_state(sctx, rasterizer, rs);
1010 si_update_poly_offset_state(sctx);
1011
1012 if (!old_rs ||
1013 (old_rs->scissor_enable != rs->scissor_enable ||
1014 old_rs->line_width != rs->line_width ||
1015 old_rs->max_point_size != rs->max_point_size)) {
1016 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1017 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1018 }
1019
1020 if (!old_rs ||
1021 old_rs->clip_halfz != rs->clip_halfz) {
1022 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1023 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1024 }
1025
1026 if (!old_rs ||
1027 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1028 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1029 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1030
1031 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1032 rs->line_stipple_enable;
1033
1034 if (!old_rs ||
1035 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1036 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1037 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1038 old_rs->flatshade != rs->flatshade ||
1039 old_rs->two_side != rs->two_side ||
1040 old_rs->multisample_enable != rs->multisample_enable ||
1041 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1042 old_rs->poly_smooth != rs->poly_smooth ||
1043 old_rs->line_smooth != rs->line_smooth ||
1044 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1045 old_rs->force_persample_interp != rs->force_persample_interp)
1046 sctx->do_update_shaders = true;
1047 }
1048
1049 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1050 {
1051 struct si_context *sctx = (struct si_context *)ctx;
1052 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1053
1054 if (sctx->queued.named.rasterizer == state)
1055 si_pm4_bind_state(sctx, poly_offset, NULL);
1056
1057 FREE(rs->pm4_poly_offset);
1058 si_pm4_delete_state(sctx, rasterizer, rs);
1059 }
1060
1061 /*
1062 * infeered state between dsa and stencil ref
1063 */
1064 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1065 {
1066 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1067 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1068 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1069
1070 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1071 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1072 S_028430_STENCILMASK(dsa->valuemask[0]) |
1073 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1074 S_028430_STENCILOPVAL(1));
1075 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1076 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1077 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1078 S_028434_STENCILOPVAL_BF(1));
1079 }
1080
1081 static void si_set_stencil_ref(struct pipe_context *ctx,
1082 const struct pipe_stencil_ref *state)
1083 {
1084 struct si_context *sctx = (struct si_context *)ctx;
1085
1086 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1087 return;
1088
1089 sctx->stencil_ref.state = *state;
1090 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1091 }
1092
1093
1094 /*
1095 * DSA
1096 */
1097
1098 static uint32_t si_translate_stencil_op(int s_op)
1099 {
1100 switch (s_op) {
1101 case PIPE_STENCIL_OP_KEEP:
1102 return V_02842C_STENCIL_KEEP;
1103 case PIPE_STENCIL_OP_ZERO:
1104 return V_02842C_STENCIL_ZERO;
1105 case PIPE_STENCIL_OP_REPLACE:
1106 return V_02842C_STENCIL_REPLACE_TEST;
1107 case PIPE_STENCIL_OP_INCR:
1108 return V_02842C_STENCIL_ADD_CLAMP;
1109 case PIPE_STENCIL_OP_DECR:
1110 return V_02842C_STENCIL_SUB_CLAMP;
1111 case PIPE_STENCIL_OP_INCR_WRAP:
1112 return V_02842C_STENCIL_ADD_WRAP;
1113 case PIPE_STENCIL_OP_DECR_WRAP:
1114 return V_02842C_STENCIL_SUB_WRAP;
1115 case PIPE_STENCIL_OP_INVERT:
1116 return V_02842C_STENCIL_INVERT;
1117 default:
1118 R600_ERR("Unknown stencil op %d", s_op);
1119 assert(0);
1120 break;
1121 }
1122 return 0;
1123 }
1124
1125 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1126 {
1127 return s->enabled && s->writemask &&
1128 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1129 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1130 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1131 }
1132
1133 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1134 {
1135 /* REPLACE is normally order invariant, except when the stencil
1136 * reference value is written by the fragment shader. Tracking this
1137 * interaction does not seem worth the effort, so be conservative. */
1138 return op != PIPE_STENCIL_OP_INCR &&
1139 op != PIPE_STENCIL_OP_DECR &&
1140 op != PIPE_STENCIL_OP_REPLACE;
1141 }
1142
1143 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1144 * invariant in the sense that the set of passing fragments as well as the
1145 * final stencil buffer result does not depend on the order of fragments. */
1146 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1147 {
1148 return !state->enabled || !state->writemask ||
1149 /* The following assumes that Z writes are disabled. */
1150 (state->func == PIPE_FUNC_ALWAYS &&
1151 si_order_invariant_stencil_op(state->zpass_op) &&
1152 si_order_invariant_stencil_op(state->zfail_op)) ||
1153 (state->func == PIPE_FUNC_NEVER &&
1154 si_order_invariant_stencil_op(state->fail_op));
1155 }
1156
1157 static void *si_create_dsa_state(struct pipe_context *ctx,
1158 const struct pipe_depth_stencil_alpha_state *state)
1159 {
1160 struct si_context *sctx = (struct si_context *)ctx;
1161 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1162 struct si_pm4_state *pm4 = &dsa->pm4;
1163 unsigned db_depth_control;
1164 uint32_t db_stencil_control = 0;
1165
1166 if (!dsa) {
1167 return NULL;
1168 }
1169
1170 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1171 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1172 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1173 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1174
1175 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1176 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1177 S_028800_ZFUNC(state->depth.func) |
1178 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1179
1180 /* stencil */
1181 if (state->stencil[0].enabled) {
1182 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1183 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1184 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1185 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1186 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1187
1188 if (state->stencil[1].enabled) {
1189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1190 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1191 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1192 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1193 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1194 }
1195 }
1196
1197 /* alpha */
1198 if (state->alpha.enabled) {
1199 dsa->alpha_func = state->alpha.func;
1200
1201 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1202 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1203 } else {
1204 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1205 }
1206
1207 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1208 if (state->stencil[0].enabled)
1209 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1210 if (state->depth.bounds_test) {
1211 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1212 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1213 }
1214
1215 dsa->depth_enabled = state->depth.enabled;
1216 dsa->depth_write_enabled = state->depth.enabled &&
1217 state->depth.writemask;
1218 dsa->stencil_enabled = state->stencil[0].enabled;
1219 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1220 (si_dsa_writes_stencil(&state->stencil[0]) ||
1221 si_dsa_writes_stencil(&state->stencil[1]));
1222 dsa->db_can_write = dsa->depth_write_enabled ||
1223 dsa->stencil_write_enabled;
1224
1225 bool zfunc_is_ordered =
1226 state->depth.func == PIPE_FUNC_NEVER ||
1227 state->depth.func == PIPE_FUNC_LESS ||
1228 state->depth.func == PIPE_FUNC_LEQUAL ||
1229 state->depth.func == PIPE_FUNC_GREATER ||
1230 state->depth.func == PIPE_FUNC_GEQUAL;
1231
1232 bool nozwrite_and_order_invariant_stencil =
1233 !dsa->db_can_write ||
1234 (!dsa->depth_write_enabled &&
1235 si_order_invariant_stencil_state(&state->stencil[0]) &&
1236 si_order_invariant_stencil_state(&state->stencil[1]));
1237
1238 dsa->order_invariance[1].zs =
1239 nozwrite_and_order_invariant_stencil ||
1240 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1241 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1242
1243 dsa->order_invariance[1].pass_set =
1244 nozwrite_and_order_invariant_stencil ||
1245 (!dsa->stencil_write_enabled &&
1246 (state->depth.func == PIPE_FUNC_ALWAYS ||
1247 state->depth.func == PIPE_FUNC_NEVER));
1248 dsa->order_invariance[0].pass_set =
1249 !dsa->depth_write_enabled ||
1250 (state->depth.func == PIPE_FUNC_ALWAYS ||
1251 state->depth.func == PIPE_FUNC_NEVER);
1252
1253 dsa->order_invariance[1].pass_last =
1254 sctx->screen->assume_no_z_fights &&
1255 !dsa->stencil_write_enabled &&
1256 dsa->depth_write_enabled && zfunc_is_ordered;
1257 dsa->order_invariance[0].pass_last =
1258 sctx->screen->assume_no_z_fights &&
1259 dsa->depth_write_enabled && zfunc_is_ordered;
1260
1261 return dsa;
1262 }
1263
1264 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1268 struct si_state_dsa *dsa = state;
1269
1270 if (!state)
1271 return;
1272
1273 si_pm4_bind_state(sctx, dsa, dsa);
1274
1275 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1276 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1277 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1278 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1279 }
1280
1281 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1282 sctx->do_update_shaders = true;
1283
1284 if (sctx->screen->dpbb_allowed &&
1285 (!old_dsa ||
1286 (old_dsa->depth_enabled != dsa->depth_enabled ||
1287 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1288 old_dsa->db_can_write != dsa->db_can_write)))
1289 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1290
1291 if (sctx->screen->has_out_of_order_rast &&
1292 (!old_dsa ||
1293 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1294 sizeof(old_dsa->order_invariance))))
1295 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1296 }
1297
1298 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1299 {
1300 struct si_context *sctx = (struct si_context *)ctx;
1301 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1302 }
1303
1304 static void *si_create_db_flush_dsa(struct si_context *sctx)
1305 {
1306 struct pipe_depth_stencil_alpha_state dsa = {};
1307
1308 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1309 }
1310
1311 /* DB RENDER STATE */
1312
1313 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1314 {
1315 struct si_context *sctx = (struct si_context*)ctx;
1316
1317 /* Pipeline stat & streamout queries. */
1318 if (enable) {
1319 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1320 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1321 } else {
1322 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1323 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1324 }
1325
1326 /* Occlusion queries. */
1327 if (sctx->occlusion_queries_disabled != !enable) {
1328 sctx->occlusion_queries_disabled = !enable;
1329 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1330 }
1331 }
1332
1333 static void si_set_occlusion_query_state(struct pipe_context *ctx,
1334 bool old_enable,
1335 bool old_perfect_enable)
1336 {
1337 struct si_context *sctx = (struct si_context*)ctx;
1338
1339 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1340
1341 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
1342
1343 if (perfect_enable != old_perfect_enable)
1344 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1345 }
1346
1347 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1348 {
1349 struct si_context *sctx = (struct si_context*)ctx;
1350
1351 st->saved_compute = sctx->cs_shader_state.program;
1352
1353 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1354 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1355 }
1356
1357 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1358 {
1359 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1360 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1361 unsigned db_shader_control;
1362
1363 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1364
1365 /* DB_RENDER_CONTROL */
1366 if (sctx->dbcb_depth_copy_enabled ||
1367 sctx->dbcb_stencil_copy_enabled) {
1368 radeon_emit(cs,
1369 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1370 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1371 S_028000_COPY_CENTROID(1) |
1372 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1373 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1374 radeon_emit(cs,
1375 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1376 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1377 } else {
1378 radeon_emit(cs,
1379 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1380 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1381 }
1382
1383 /* DB_COUNT_CONTROL (occlusion queries) */
1384 if (sctx->b.num_occlusion_queries > 0 &&
1385 !sctx->occlusion_queries_disabled) {
1386 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1387
1388 if (sctx->b.chip_class >= CIK) {
1389 radeon_emit(cs,
1390 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1391 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1392 S_028004_ZPASS_ENABLE(1) |
1393 S_028004_SLICE_EVEN_ENABLE(1) |
1394 S_028004_SLICE_ODD_ENABLE(1));
1395 } else {
1396 radeon_emit(cs,
1397 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1398 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1399 }
1400 } else {
1401 /* Disable occlusion queries. */
1402 if (sctx->b.chip_class >= CIK) {
1403 radeon_emit(cs, 0);
1404 } else {
1405 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1406 }
1407 }
1408
1409 /* DB_RENDER_OVERRIDE2 */
1410 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1411 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1412 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1413 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1414
1415 db_shader_control = sctx->ps_db_shader_control;
1416
1417 /* Bug workaround for smoothing (overrasterization) on SI. */
1418 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1419 db_shader_control &= C_02880C_Z_ORDER;
1420 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1421 }
1422
1423 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1424 if (!rs || !rs->multisample_enable)
1425 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1426
1427 if (sctx->screen->b.has_rbplus &&
1428 !sctx->screen->b.rbplus_allowed)
1429 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1430
1431 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1432 db_shader_control);
1433 }
1434
1435 /*
1436 * format translation
1437 */
1438 static uint32_t si_translate_colorformat(enum pipe_format format)
1439 {
1440 const struct util_format_description *desc = util_format_description(format);
1441 if (!desc)
1442 return V_028C70_COLOR_INVALID;
1443
1444 #define HAS_SIZE(x,y,z,w) \
1445 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1446 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1447
1448 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1449 return V_028C70_COLOR_10_11_11;
1450
1451 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1452 return V_028C70_COLOR_INVALID;
1453
1454 /* hw cannot support mixed formats (except depth/stencil, since
1455 * stencil is not written to). */
1456 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1457 return V_028C70_COLOR_INVALID;
1458
1459 switch (desc->nr_channels) {
1460 case 1:
1461 switch (desc->channel[0].size) {
1462 case 8:
1463 return V_028C70_COLOR_8;
1464 case 16:
1465 return V_028C70_COLOR_16;
1466 case 32:
1467 return V_028C70_COLOR_32;
1468 }
1469 break;
1470 case 2:
1471 if (desc->channel[0].size == desc->channel[1].size) {
1472 switch (desc->channel[0].size) {
1473 case 8:
1474 return V_028C70_COLOR_8_8;
1475 case 16:
1476 return V_028C70_COLOR_16_16;
1477 case 32:
1478 return V_028C70_COLOR_32_32;
1479 }
1480 } else if (HAS_SIZE(8,24,0,0)) {
1481 return V_028C70_COLOR_24_8;
1482 } else if (HAS_SIZE(24,8,0,0)) {
1483 return V_028C70_COLOR_8_24;
1484 }
1485 break;
1486 case 3:
1487 if (HAS_SIZE(5,6,5,0)) {
1488 return V_028C70_COLOR_5_6_5;
1489 } else if (HAS_SIZE(32,8,24,0)) {
1490 return V_028C70_COLOR_X24_8_32_FLOAT;
1491 }
1492 break;
1493 case 4:
1494 if (desc->channel[0].size == desc->channel[1].size &&
1495 desc->channel[0].size == desc->channel[2].size &&
1496 desc->channel[0].size == desc->channel[3].size) {
1497 switch (desc->channel[0].size) {
1498 case 4:
1499 return V_028C70_COLOR_4_4_4_4;
1500 case 8:
1501 return V_028C70_COLOR_8_8_8_8;
1502 case 16:
1503 return V_028C70_COLOR_16_16_16_16;
1504 case 32:
1505 return V_028C70_COLOR_32_32_32_32;
1506 }
1507 } else if (HAS_SIZE(5,5,5,1)) {
1508 return V_028C70_COLOR_1_5_5_5;
1509 } else if (HAS_SIZE(1,5,5,5)) {
1510 return V_028C70_COLOR_5_5_5_1;
1511 } else if (HAS_SIZE(10,10,10,2)) {
1512 return V_028C70_COLOR_2_10_10_10;
1513 }
1514 break;
1515 }
1516 return V_028C70_COLOR_INVALID;
1517 }
1518
1519 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1520 {
1521 if (SI_BIG_ENDIAN) {
1522 switch(colorformat) {
1523 /* 8-bit buffers. */
1524 case V_028C70_COLOR_8:
1525 return V_028C70_ENDIAN_NONE;
1526
1527 /* 16-bit buffers. */
1528 case V_028C70_COLOR_5_6_5:
1529 case V_028C70_COLOR_1_5_5_5:
1530 case V_028C70_COLOR_4_4_4_4:
1531 case V_028C70_COLOR_16:
1532 case V_028C70_COLOR_8_8:
1533 return V_028C70_ENDIAN_8IN16;
1534
1535 /* 32-bit buffers. */
1536 case V_028C70_COLOR_8_8_8_8:
1537 case V_028C70_COLOR_2_10_10_10:
1538 case V_028C70_COLOR_8_24:
1539 case V_028C70_COLOR_24_8:
1540 case V_028C70_COLOR_16_16:
1541 return V_028C70_ENDIAN_8IN32;
1542
1543 /* 64-bit buffers. */
1544 case V_028C70_COLOR_16_16_16_16:
1545 return V_028C70_ENDIAN_8IN16;
1546
1547 case V_028C70_COLOR_32_32:
1548 return V_028C70_ENDIAN_8IN32;
1549
1550 /* 128-bit buffers. */
1551 case V_028C70_COLOR_32_32_32_32:
1552 return V_028C70_ENDIAN_8IN32;
1553 default:
1554 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1555 }
1556 } else {
1557 return V_028C70_ENDIAN_NONE;
1558 }
1559 }
1560
1561 static uint32_t si_translate_dbformat(enum pipe_format format)
1562 {
1563 switch (format) {
1564 case PIPE_FORMAT_Z16_UNORM:
1565 return V_028040_Z_16;
1566 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1567 case PIPE_FORMAT_X8Z24_UNORM:
1568 case PIPE_FORMAT_Z24X8_UNORM:
1569 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1570 return V_028040_Z_24; /* deprecated on SI */
1571 case PIPE_FORMAT_Z32_FLOAT:
1572 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1573 return V_028040_Z_32_FLOAT;
1574 default:
1575 return V_028040_Z_INVALID;
1576 }
1577 }
1578
1579 /*
1580 * Texture translation
1581 */
1582
1583 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1584 enum pipe_format format,
1585 const struct util_format_description *desc,
1586 int first_non_void)
1587 {
1588 struct si_screen *sscreen = (struct si_screen*)screen;
1589 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1590 sscreen->b.info.drm_minor >= 31) ||
1591 sscreen->b.info.drm_major == 3;
1592 bool uniform = true;
1593 int i;
1594
1595 /* Colorspace (return non-RGB formats directly). */
1596 switch (desc->colorspace) {
1597 /* Depth stencil formats */
1598 case UTIL_FORMAT_COLORSPACE_ZS:
1599 switch (format) {
1600 case PIPE_FORMAT_Z16_UNORM:
1601 return V_008F14_IMG_DATA_FORMAT_16;
1602 case PIPE_FORMAT_X24S8_UINT:
1603 case PIPE_FORMAT_S8X24_UINT:
1604 /*
1605 * Implemented as an 8_8_8_8 data format to fix texture
1606 * gathers in stencil sampling. This affects at least
1607 * GL45-CTS.texture_cube_map_array.sampling on VI.
1608 */
1609 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1610 case PIPE_FORMAT_Z24X8_UNORM:
1611 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1612 return V_008F14_IMG_DATA_FORMAT_8_24;
1613 case PIPE_FORMAT_X8Z24_UNORM:
1614 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1615 return V_008F14_IMG_DATA_FORMAT_24_8;
1616 case PIPE_FORMAT_S8_UINT:
1617 return V_008F14_IMG_DATA_FORMAT_8;
1618 case PIPE_FORMAT_Z32_FLOAT:
1619 return V_008F14_IMG_DATA_FORMAT_32;
1620 case PIPE_FORMAT_X32_S8X24_UINT:
1621 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1622 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1623 default:
1624 goto out_unknown;
1625 }
1626
1627 case UTIL_FORMAT_COLORSPACE_YUV:
1628 goto out_unknown; /* TODO */
1629
1630 case UTIL_FORMAT_COLORSPACE_SRGB:
1631 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1632 goto out_unknown;
1633 break;
1634
1635 default:
1636 break;
1637 }
1638
1639 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1640 if (!enable_compressed_formats)
1641 goto out_unknown;
1642
1643 switch (format) {
1644 case PIPE_FORMAT_RGTC1_SNORM:
1645 case PIPE_FORMAT_LATC1_SNORM:
1646 case PIPE_FORMAT_RGTC1_UNORM:
1647 case PIPE_FORMAT_LATC1_UNORM:
1648 return V_008F14_IMG_DATA_FORMAT_BC4;
1649 case PIPE_FORMAT_RGTC2_SNORM:
1650 case PIPE_FORMAT_LATC2_SNORM:
1651 case PIPE_FORMAT_RGTC2_UNORM:
1652 case PIPE_FORMAT_LATC2_UNORM:
1653 return V_008F14_IMG_DATA_FORMAT_BC5;
1654 default:
1655 goto out_unknown;
1656 }
1657 }
1658
1659 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1660 (sscreen->b.family == CHIP_STONEY ||
1661 sscreen->b.chip_class >= GFX9)) {
1662 switch (format) {
1663 case PIPE_FORMAT_ETC1_RGB8:
1664 case PIPE_FORMAT_ETC2_RGB8:
1665 case PIPE_FORMAT_ETC2_SRGB8:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1667 case PIPE_FORMAT_ETC2_RGB8A1:
1668 case PIPE_FORMAT_ETC2_SRGB8A1:
1669 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1670 case PIPE_FORMAT_ETC2_RGBA8:
1671 case PIPE_FORMAT_ETC2_SRGBA8:
1672 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1673 case PIPE_FORMAT_ETC2_R11_UNORM:
1674 case PIPE_FORMAT_ETC2_R11_SNORM:
1675 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1676 case PIPE_FORMAT_ETC2_RG11_UNORM:
1677 case PIPE_FORMAT_ETC2_RG11_SNORM:
1678 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1679 default:
1680 goto out_unknown;
1681 }
1682 }
1683
1684 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1685 if (!enable_compressed_formats)
1686 goto out_unknown;
1687
1688 switch (format) {
1689 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1690 case PIPE_FORMAT_BPTC_SRGBA:
1691 return V_008F14_IMG_DATA_FORMAT_BC7;
1692 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1693 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1694 return V_008F14_IMG_DATA_FORMAT_BC6;
1695 default:
1696 goto out_unknown;
1697 }
1698 }
1699
1700 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1701 switch (format) {
1702 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1703 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1704 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1705 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1706 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1707 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1708 default:
1709 goto out_unknown;
1710 }
1711 }
1712
1713 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1714 if (!enable_compressed_formats)
1715 goto out_unknown;
1716
1717 switch (format) {
1718 case PIPE_FORMAT_DXT1_RGB:
1719 case PIPE_FORMAT_DXT1_RGBA:
1720 case PIPE_FORMAT_DXT1_SRGB:
1721 case PIPE_FORMAT_DXT1_SRGBA:
1722 return V_008F14_IMG_DATA_FORMAT_BC1;
1723 case PIPE_FORMAT_DXT3_RGBA:
1724 case PIPE_FORMAT_DXT3_SRGBA:
1725 return V_008F14_IMG_DATA_FORMAT_BC2;
1726 case PIPE_FORMAT_DXT5_RGBA:
1727 case PIPE_FORMAT_DXT5_SRGBA:
1728 return V_008F14_IMG_DATA_FORMAT_BC3;
1729 default:
1730 goto out_unknown;
1731 }
1732 }
1733
1734 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1735 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1736 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1737 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1738 }
1739
1740 /* R8G8Bx_SNORM - TODO CxV8U8 */
1741
1742 /* hw cannot support mixed formats (except depth/stencil, since only
1743 * depth is read).*/
1744 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1745 goto out_unknown;
1746
1747 /* See whether the components are of the same size. */
1748 for (i = 1; i < desc->nr_channels; i++) {
1749 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1750 }
1751
1752 /* Non-uniform formats. */
1753 if (!uniform) {
1754 switch(desc->nr_channels) {
1755 case 3:
1756 if (desc->channel[0].size == 5 &&
1757 desc->channel[1].size == 6 &&
1758 desc->channel[2].size == 5) {
1759 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1760 }
1761 goto out_unknown;
1762 case 4:
1763 if (desc->channel[0].size == 5 &&
1764 desc->channel[1].size == 5 &&
1765 desc->channel[2].size == 5 &&
1766 desc->channel[3].size == 1) {
1767 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1768 }
1769 if (desc->channel[0].size == 1 &&
1770 desc->channel[1].size == 5 &&
1771 desc->channel[2].size == 5 &&
1772 desc->channel[3].size == 5) {
1773 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1774 }
1775 if (desc->channel[0].size == 10 &&
1776 desc->channel[1].size == 10 &&
1777 desc->channel[2].size == 10 &&
1778 desc->channel[3].size == 2) {
1779 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1780 }
1781 goto out_unknown;
1782 }
1783 goto out_unknown;
1784 }
1785
1786 if (first_non_void < 0 || first_non_void > 3)
1787 goto out_unknown;
1788
1789 /* uniform formats */
1790 switch (desc->channel[first_non_void].size) {
1791 case 4:
1792 switch (desc->nr_channels) {
1793 #if 0 /* Not supported for render targets */
1794 case 2:
1795 return V_008F14_IMG_DATA_FORMAT_4_4;
1796 #endif
1797 case 4:
1798 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1799 }
1800 break;
1801 case 8:
1802 switch (desc->nr_channels) {
1803 case 1:
1804 return V_008F14_IMG_DATA_FORMAT_8;
1805 case 2:
1806 return V_008F14_IMG_DATA_FORMAT_8_8;
1807 case 4:
1808 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1809 }
1810 break;
1811 case 16:
1812 switch (desc->nr_channels) {
1813 case 1:
1814 return V_008F14_IMG_DATA_FORMAT_16;
1815 case 2:
1816 return V_008F14_IMG_DATA_FORMAT_16_16;
1817 case 4:
1818 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1819 }
1820 break;
1821 case 32:
1822 switch (desc->nr_channels) {
1823 case 1:
1824 return V_008F14_IMG_DATA_FORMAT_32;
1825 case 2:
1826 return V_008F14_IMG_DATA_FORMAT_32_32;
1827 #if 0 /* Not supported for render targets */
1828 case 3:
1829 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1830 #endif
1831 case 4:
1832 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1833 }
1834 }
1835
1836 out_unknown:
1837 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1838 return ~0;
1839 }
1840
1841 static unsigned si_tex_wrap(unsigned wrap)
1842 {
1843 switch (wrap) {
1844 default:
1845 case PIPE_TEX_WRAP_REPEAT:
1846 return V_008F30_SQ_TEX_WRAP;
1847 case PIPE_TEX_WRAP_CLAMP:
1848 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1849 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1850 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1851 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1852 return V_008F30_SQ_TEX_CLAMP_BORDER;
1853 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1854 return V_008F30_SQ_TEX_MIRROR;
1855 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1856 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1857 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1858 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1859 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1860 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1861 }
1862 }
1863
1864 static unsigned si_tex_mipfilter(unsigned filter)
1865 {
1866 switch (filter) {
1867 case PIPE_TEX_MIPFILTER_NEAREST:
1868 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1869 case PIPE_TEX_MIPFILTER_LINEAR:
1870 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1871 default:
1872 case PIPE_TEX_MIPFILTER_NONE:
1873 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1874 }
1875 }
1876
1877 static unsigned si_tex_compare(unsigned compare)
1878 {
1879 switch (compare) {
1880 default:
1881 case PIPE_FUNC_NEVER:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1883 case PIPE_FUNC_LESS:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1885 case PIPE_FUNC_EQUAL:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1887 case PIPE_FUNC_LEQUAL:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1889 case PIPE_FUNC_GREATER:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1891 case PIPE_FUNC_NOTEQUAL:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1893 case PIPE_FUNC_GEQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1895 case PIPE_FUNC_ALWAYS:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1897 }
1898 }
1899
1900 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1901 unsigned view_target, unsigned nr_samples)
1902 {
1903 unsigned res_target = rtex->resource.b.b.target;
1904
1905 if (view_target == PIPE_TEXTURE_CUBE ||
1906 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1907 res_target = view_target;
1908 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1909 else if (res_target == PIPE_TEXTURE_CUBE ||
1910 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1911 res_target = PIPE_TEXTURE_2D_ARRAY;
1912
1913 /* GFX9 allocates 1D textures as 2D. */
1914 if ((res_target == PIPE_TEXTURE_1D ||
1915 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1916 sscreen->b.chip_class >= GFX9 &&
1917 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1918 if (res_target == PIPE_TEXTURE_1D)
1919 res_target = PIPE_TEXTURE_2D;
1920 else
1921 res_target = PIPE_TEXTURE_2D_ARRAY;
1922 }
1923
1924 switch (res_target) {
1925 default:
1926 case PIPE_TEXTURE_1D:
1927 return V_008F1C_SQ_RSRC_IMG_1D;
1928 case PIPE_TEXTURE_1D_ARRAY:
1929 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1930 case PIPE_TEXTURE_2D:
1931 case PIPE_TEXTURE_RECT:
1932 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1933 V_008F1C_SQ_RSRC_IMG_2D;
1934 case PIPE_TEXTURE_2D_ARRAY:
1935 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1936 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1937 case PIPE_TEXTURE_3D:
1938 return V_008F1C_SQ_RSRC_IMG_3D;
1939 case PIPE_TEXTURE_CUBE:
1940 case PIPE_TEXTURE_CUBE_ARRAY:
1941 return V_008F1C_SQ_RSRC_IMG_CUBE;
1942 }
1943 }
1944
1945 /*
1946 * Format support testing
1947 */
1948
1949 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1950 {
1951 const struct util_format_description *desc = util_format_description(format);
1952 if (!desc)
1953 return false;
1954
1955 return si_translate_texformat(screen, format, desc,
1956 util_format_get_first_non_void_channel(format)) != ~0U;
1957 }
1958
1959 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1960 const struct util_format_description *desc,
1961 int first_non_void)
1962 {
1963 int i;
1964
1965 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1966 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1967
1968 assert(first_non_void >= 0);
1969
1970 if (desc->nr_channels == 4 &&
1971 desc->channel[0].size == 10 &&
1972 desc->channel[1].size == 10 &&
1973 desc->channel[2].size == 10 &&
1974 desc->channel[3].size == 2)
1975 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1976
1977 /* See whether the components are of the same size. */
1978 for (i = 0; i < desc->nr_channels; i++) {
1979 if (desc->channel[first_non_void].size != desc->channel[i].size)
1980 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1981 }
1982
1983 switch (desc->channel[first_non_void].size) {
1984 case 8:
1985 switch (desc->nr_channels) {
1986 case 1:
1987 case 3: /* 3 loads */
1988 return V_008F0C_BUF_DATA_FORMAT_8;
1989 case 2:
1990 return V_008F0C_BUF_DATA_FORMAT_8_8;
1991 case 4:
1992 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1993 }
1994 break;
1995 case 16:
1996 switch (desc->nr_channels) {
1997 case 1:
1998 case 3: /* 3 loads */
1999 return V_008F0C_BUF_DATA_FORMAT_16;
2000 case 2:
2001 return V_008F0C_BUF_DATA_FORMAT_16_16;
2002 case 4:
2003 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2004 }
2005 break;
2006 case 32:
2007 switch (desc->nr_channels) {
2008 case 1:
2009 return V_008F0C_BUF_DATA_FORMAT_32;
2010 case 2:
2011 return V_008F0C_BUF_DATA_FORMAT_32_32;
2012 case 3:
2013 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2014 case 4:
2015 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2016 }
2017 break;
2018 case 64:
2019 /* Legacy double formats. */
2020 switch (desc->nr_channels) {
2021 case 1: /* 1 load */
2022 return V_008F0C_BUF_DATA_FORMAT_32_32;
2023 case 2: /* 1 load */
2024 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2025 case 3: /* 3 loads */
2026 return V_008F0C_BUF_DATA_FORMAT_32_32;
2027 case 4: /* 2 loads */
2028 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2029 }
2030 break;
2031 }
2032
2033 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2034 }
2035
2036 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2037 const struct util_format_description *desc,
2038 int first_non_void)
2039 {
2040 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2041 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2042
2043 assert(first_non_void >= 0);
2044
2045 switch (desc->channel[first_non_void].type) {
2046 case UTIL_FORMAT_TYPE_SIGNED:
2047 case UTIL_FORMAT_TYPE_FIXED:
2048 if (desc->channel[first_non_void].size >= 32 ||
2049 desc->channel[first_non_void].pure_integer)
2050 return V_008F0C_BUF_NUM_FORMAT_SINT;
2051 else if (desc->channel[first_non_void].normalized)
2052 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2053 else
2054 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2055 break;
2056 case UTIL_FORMAT_TYPE_UNSIGNED:
2057 if (desc->channel[first_non_void].size >= 32 ||
2058 desc->channel[first_non_void].pure_integer)
2059 return V_008F0C_BUF_NUM_FORMAT_UINT;
2060 else if (desc->channel[first_non_void].normalized)
2061 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2062 else
2063 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2064 break;
2065 case UTIL_FORMAT_TYPE_FLOAT:
2066 default:
2067 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2068 }
2069 }
2070
2071 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2072 enum pipe_format format,
2073 unsigned usage)
2074 {
2075 const struct util_format_description *desc;
2076 int first_non_void;
2077 unsigned data_format;
2078
2079 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2080 PIPE_BIND_SAMPLER_VIEW |
2081 PIPE_BIND_VERTEX_BUFFER)) == 0);
2082
2083 desc = util_format_description(format);
2084 if (!desc)
2085 return 0;
2086
2087 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2088 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2089 * for read-only access (with caveats surrounding bounds checks), but
2090 * obviously fails for write access which we have to implement for
2091 * shader images. Luckily, OpenGL doesn't expect this to be supported
2092 * anyway, and so the only impact is on PBO uploads / downloads, which
2093 * shouldn't be expected to be fast for GL_RGB anyway.
2094 */
2095 if (desc->block.bits == 3 * 8 ||
2096 desc->block.bits == 3 * 16) {
2097 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2098 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2099 if (!usage)
2100 return 0;
2101 }
2102 }
2103
2104 first_non_void = util_format_get_first_non_void_channel(format);
2105 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2106 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2107 return 0;
2108
2109 return usage;
2110 }
2111
2112 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2113 {
2114 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2115 si_translate_colorswap(format, false) != ~0U;
2116 }
2117
2118 static bool si_is_zs_format_supported(enum pipe_format format)
2119 {
2120 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2121 }
2122
2123 static boolean si_is_format_supported(struct pipe_screen *screen,
2124 enum pipe_format format,
2125 enum pipe_texture_target target,
2126 unsigned sample_count,
2127 unsigned usage)
2128 {
2129 unsigned retval = 0;
2130
2131 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2132 R600_ERR("r600: unsupported texture type %d\n", target);
2133 return false;
2134 }
2135
2136 if (!util_format_is_supported(format, usage))
2137 return false;
2138
2139 if (sample_count > 1) {
2140 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2141 return false;
2142
2143 if (usage & PIPE_BIND_SHADER_IMAGE)
2144 return false;
2145
2146 switch (sample_count) {
2147 case 2:
2148 case 4:
2149 case 8:
2150 break;
2151 case 16:
2152 if (format == PIPE_FORMAT_NONE)
2153 return true;
2154 else
2155 return false;
2156 default:
2157 return false;
2158 }
2159 }
2160
2161 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2162 PIPE_BIND_SHADER_IMAGE)) {
2163 if (target == PIPE_BUFFER) {
2164 retval |= si_is_vertex_format_supported(
2165 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2166 PIPE_BIND_SHADER_IMAGE));
2167 } else {
2168 if (si_is_sampler_format_supported(screen, format))
2169 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2170 PIPE_BIND_SHADER_IMAGE);
2171 }
2172 }
2173
2174 if ((usage & (PIPE_BIND_RENDER_TARGET |
2175 PIPE_BIND_DISPLAY_TARGET |
2176 PIPE_BIND_SCANOUT |
2177 PIPE_BIND_SHARED |
2178 PIPE_BIND_BLENDABLE)) &&
2179 si_is_colorbuffer_format_supported(format)) {
2180 retval |= usage &
2181 (PIPE_BIND_RENDER_TARGET |
2182 PIPE_BIND_DISPLAY_TARGET |
2183 PIPE_BIND_SCANOUT |
2184 PIPE_BIND_SHARED);
2185 if (!util_format_is_pure_integer(format) &&
2186 !util_format_is_depth_or_stencil(format))
2187 retval |= usage & PIPE_BIND_BLENDABLE;
2188 }
2189
2190 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2191 si_is_zs_format_supported(format)) {
2192 retval |= PIPE_BIND_DEPTH_STENCIL;
2193 }
2194
2195 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2196 retval |= si_is_vertex_format_supported(screen, format,
2197 PIPE_BIND_VERTEX_BUFFER);
2198 }
2199
2200 if ((usage & PIPE_BIND_LINEAR) &&
2201 !util_format_is_compressed(format) &&
2202 !(usage & PIPE_BIND_DEPTH_STENCIL))
2203 retval |= PIPE_BIND_LINEAR;
2204
2205 return retval == usage;
2206 }
2207
2208 /*
2209 * framebuffer handling
2210 */
2211
2212 static void si_choose_spi_color_formats(struct r600_surface *surf,
2213 unsigned format, unsigned swap,
2214 unsigned ntype, bool is_depth)
2215 {
2216 /* Alpha is needed for alpha-to-coverage.
2217 * Blending may be with or without alpha.
2218 */
2219 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2220 unsigned alpha = 0; /* exports alpha, but may not support blending */
2221 unsigned blend = 0; /* supports blending, but may not export alpha */
2222 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2223
2224 /* Choose the SPI color formats. These are required values for RB+.
2225 * Other chips have multiple choices, though they are not necessarily better.
2226 */
2227 switch (format) {
2228 case V_028C70_COLOR_5_6_5:
2229 case V_028C70_COLOR_1_5_5_5:
2230 case V_028C70_COLOR_5_5_5_1:
2231 case V_028C70_COLOR_4_4_4_4:
2232 case V_028C70_COLOR_10_11_11:
2233 case V_028C70_COLOR_11_11_10:
2234 case V_028C70_COLOR_8:
2235 case V_028C70_COLOR_8_8:
2236 case V_028C70_COLOR_8_8_8_8:
2237 case V_028C70_COLOR_10_10_10_2:
2238 case V_028C70_COLOR_2_10_10_10:
2239 if (ntype == V_028C70_NUMBER_UINT)
2240 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2241 else if (ntype == V_028C70_NUMBER_SINT)
2242 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2243 else
2244 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2245 break;
2246
2247 case V_028C70_COLOR_16:
2248 case V_028C70_COLOR_16_16:
2249 case V_028C70_COLOR_16_16_16_16:
2250 if (ntype == V_028C70_NUMBER_UNORM ||
2251 ntype == V_028C70_NUMBER_SNORM) {
2252 /* UNORM16 and SNORM16 don't support blending */
2253 if (ntype == V_028C70_NUMBER_UNORM)
2254 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2255 else
2256 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2257
2258 /* Use 32 bits per channel for blending. */
2259 if (format == V_028C70_COLOR_16) {
2260 if (swap == V_028C70_SWAP_STD) { /* R */
2261 blend = V_028714_SPI_SHADER_32_R;
2262 blend_alpha = V_028714_SPI_SHADER_32_AR;
2263 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2264 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2265 else
2266 assert(0);
2267 } else if (format == V_028C70_COLOR_16_16) {
2268 if (swap == V_028C70_SWAP_STD) { /* RG */
2269 blend = V_028714_SPI_SHADER_32_GR;
2270 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2271 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2272 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2273 else
2274 assert(0);
2275 } else /* 16_16_16_16 */
2276 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2277 } else if (ntype == V_028C70_NUMBER_UINT)
2278 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2279 else if (ntype == V_028C70_NUMBER_SINT)
2280 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2281 else if (ntype == V_028C70_NUMBER_FLOAT)
2282 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2283 else
2284 assert(0);
2285 break;
2286
2287 case V_028C70_COLOR_32:
2288 if (swap == V_028C70_SWAP_STD) { /* R */
2289 blend = normal = V_028714_SPI_SHADER_32_R;
2290 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2291 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2292 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2293 else
2294 assert(0);
2295 break;
2296
2297 case V_028C70_COLOR_32_32:
2298 if (swap == V_028C70_SWAP_STD) { /* RG */
2299 blend = normal = V_028714_SPI_SHADER_32_GR;
2300 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2301 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2302 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2303 else
2304 assert(0);
2305 break;
2306
2307 case V_028C70_COLOR_32_32_32_32:
2308 case V_028C70_COLOR_8_24:
2309 case V_028C70_COLOR_24_8:
2310 case V_028C70_COLOR_X24_8_32_FLOAT:
2311 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2312 break;
2313
2314 default:
2315 assert(0);
2316 return;
2317 }
2318
2319 /* The DB->CB copy needs 32_ABGR. */
2320 if (is_depth)
2321 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2322
2323 surf->spi_shader_col_format = normal;
2324 surf->spi_shader_col_format_alpha = alpha;
2325 surf->spi_shader_col_format_blend = blend;
2326 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2327 }
2328
2329 static void si_initialize_color_surface(struct si_context *sctx,
2330 struct r600_surface *surf)
2331 {
2332 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2333 unsigned color_info, color_attrib, color_view;
2334 unsigned format, swap, ntype, endian;
2335 const struct util_format_description *desc;
2336 int firstchan;
2337 unsigned blend_clamp = 0, blend_bypass = 0;
2338
2339 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2340 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2341
2342 desc = util_format_description(surf->base.format);
2343 for (firstchan = 0; firstchan < 4; firstchan++) {
2344 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2345 break;
2346 }
2347 }
2348 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2349 ntype = V_028C70_NUMBER_FLOAT;
2350 } else {
2351 ntype = V_028C70_NUMBER_UNORM;
2352 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2353 ntype = V_028C70_NUMBER_SRGB;
2354 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2355 if (desc->channel[firstchan].pure_integer) {
2356 ntype = V_028C70_NUMBER_SINT;
2357 } else {
2358 assert(desc->channel[firstchan].normalized);
2359 ntype = V_028C70_NUMBER_SNORM;
2360 }
2361 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2362 if (desc->channel[firstchan].pure_integer) {
2363 ntype = V_028C70_NUMBER_UINT;
2364 } else {
2365 assert(desc->channel[firstchan].normalized);
2366 ntype = V_028C70_NUMBER_UNORM;
2367 }
2368 }
2369 }
2370
2371 format = si_translate_colorformat(surf->base.format);
2372 if (format == V_028C70_COLOR_INVALID) {
2373 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2374 }
2375 assert(format != V_028C70_COLOR_INVALID);
2376 swap = si_translate_colorswap(surf->base.format, false);
2377 endian = si_colorformat_endian_swap(format);
2378
2379 /* blend clamp should be set for all NORM/SRGB types */
2380 if (ntype == V_028C70_NUMBER_UNORM ||
2381 ntype == V_028C70_NUMBER_SNORM ||
2382 ntype == V_028C70_NUMBER_SRGB)
2383 blend_clamp = 1;
2384
2385 /* set blend bypass according to docs if SINT/UINT or
2386 8/24 COLOR variants */
2387 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2388 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2389 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2390 blend_clamp = 0;
2391 blend_bypass = 1;
2392 }
2393
2394 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2395 if (format == V_028C70_COLOR_8 ||
2396 format == V_028C70_COLOR_8_8 ||
2397 format == V_028C70_COLOR_8_8_8_8)
2398 surf->color_is_int8 = true;
2399 else if (format == V_028C70_COLOR_10_10_10_2 ||
2400 format == V_028C70_COLOR_2_10_10_10)
2401 surf->color_is_int10 = true;
2402 }
2403
2404 color_info = S_028C70_FORMAT(format) |
2405 S_028C70_COMP_SWAP(swap) |
2406 S_028C70_BLEND_CLAMP(blend_clamp) |
2407 S_028C70_BLEND_BYPASS(blend_bypass) |
2408 S_028C70_SIMPLE_FLOAT(1) |
2409 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2410 ntype != V_028C70_NUMBER_SNORM &&
2411 ntype != V_028C70_NUMBER_SRGB &&
2412 format != V_028C70_COLOR_8_24 &&
2413 format != V_028C70_COLOR_24_8) |
2414 S_028C70_NUMBER_TYPE(ntype) |
2415 S_028C70_ENDIAN(endian);
2416
2417 /* Intensity is implemented as Red, so treat it that way. */
2418 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2419 util_format_is_intensity(surf->base.format));
2420
2421 if (rtex->resource.b.b.nr_samples > 1) {
2422 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2423
2424 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2425 S_028C74_NUM_FRAGMENTS(log_samples);
2426
2427 if (rtex->fmask.size) {
2428 color_info |= S_028C70_COMPRESSION(1);
2429 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2430
2431 if (sctx->b.chip_class == SI) {
2432 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2433 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2434 }
2435 }
2436 }
2437
2438 surf->cb_color_view = color_view;
2439 surf->cb_color_info = color_info;
2440 surf->cb_color_attrib = color_attrib;
2441
2442 if (sctx->b.chip_class >= VI) {
2443 unsigned max_uncompressed_block_size = 2;
2444
2445 if (rtex->resource.b.b.nr_samples > 1) {
2446 if (rtex->surface.bpe == 1)
2447 max_uncompressed_block_size = 0;
2448 else if (rtex->surface.bpe == 2)
2449 max_uncompressed_block_size = 1;
2450 }
2451
2452 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2453 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2454 }
2455
2456 /* This must be set for fast clear to work without FMASK. */
2457 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2458 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2459 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2460 }
2461
2462 if (sctx->b.chip_class >= GFX9) {
2463 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2464
2465 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2466 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2467 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2468 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2469 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2470 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2471 }
2472
2473 /* Determine pixel shader export format */
2474 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2475
2476 surf->color_initialized = true;
2477 }
2478
2479 static void si_init_depth_surface(struct si_context *sctx,
2480 struct r600_surface *surf)
2481 {
2482 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2483 unsigned level = surf->base.u.tex.level;
2484 unsigned format, stencil_format;
2485 uint32_t z_info, s_info;
2486
2487 format = si_translate_dbformat(rtex->db_render_format);
2488 stencil_format = rtex->surface.has_stencil ?
2489 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2490
2491 assert(format != V_028040_Z_INVALID);
2492 if (format == V_028040_Z_INVALID)
2493 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2494
2495 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2496 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2497 surf->db_htile_data_base = 0;
2498 surf->db_htile_surface = 0;
2499
2500 if (sctx->b.chip_class >= GFX9) {
2501 assert(rtex->surface.u.gfx9.surf_offset == 0);
2502 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2503 surf->db_stencil_base = (rtex->resource.gpu_address +
2504 rtex->surface.u.gfx9.stencil_offset) >> 8;
2505 z_info = S_028038_FORMAT(format) |
2506 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2507 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2508 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2509 s_info = S_02803C_FORMAT(stencil_format) |
2510 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2511 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2512 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2513 surf->db_depth_view |= S_028008_MIPID(level);
2514 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2515 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2516
2517 if (r600_htile_enabled(rtex, level)) {
2518 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2519 S_028038_ALLOW_EXPCLEAR(1);
2520
2521 if (rtex->tc_compatible_htile) {
2522 unsigned max_zplanes = 4;
2523
2524 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2525 rtex->resource.b.b.nr_samples > 1)
2526 max_zplanes = 2;
2527
2528 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2529 S_028038_ITERATE_FLUSH(1);
2530 s_info |= S_02803C_ITERATE_FLUSH(1);
2531 }
2532
2533 if (rtex->surface.has_stencil) {
2534 /* Stencil buffer workaround ported from the SI-CI-VI code.
2535 * See that for explanation.
2536 */
2537 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2538 } else {
2539 /* Use all HTILE for depth if there's no stencil. */
2540 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2541 }
2542
2543 surf->db_htile_data_base = (rtex->resource.gpu_address +
2544 rtex->htile_offset) >> 8;
2545 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2546 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2547 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2548 }
2549 } else {
2550 /* SI-CI-VI */
2551 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2552
2553 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2554
2555 surf->db_depth_base = (rtex->resource.gpu_address +
2556 rtex->surface.u.legacy.level[level].offset) >> 8;
2557 surf->db_stencil_base = (rtex->resource.gpu_address +
2558 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2559
2560 z_info = S_028040_FORMAT(format) |
2561 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2562 s_info = S_028044_FORMAT(stencil_format);
2563 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2564
2565 if (sctx->b.chip_class >= CIK) {
2566 struct radeon_info *info = &sctx->screen->b.info;
2567 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2568 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2569 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2570 unsigned tile_mode = info->si_tile_mode_array[index];
2571 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2572 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2573
2574 surf->db_depth_info |=
2575 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2576 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2577 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2578 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2579 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2580 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2581 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2582 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2583 } else {
2584 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2585 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2586 tile_mode_index = si_tile_mode_index(rtex, level, true);
2587 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2588 }
2589
2590 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2591 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2592 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2593 levelinfo->nblk_y) / 64 - 1);
2594
2595 if (r600_htile_enabled(rtex, level)) {
2596 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2597 S_028040_ALLOW_EXPCLEAR(1);
2598
2599 if (rtex->surface.has_stencil) {
2600 /* Workaround: For a not yet understood reason, the
2601 * combination of MSAA, fast stencil clear and stencil
2602 * decompress messes with subsequent stencil buffer
2603 * uses. Problem was reproduced on Verde, Bonaire,
2604 * Tonga, and Carrizo.
2605 *
2606 * Disabling EXPCLEAR works around the problem.
2607 *
2608 * Check piglit's arb_texture_multisample-stencil-clear
2609 * test if you want to try changing this.
2610 */
2611 if (rtex->resource.b.b.nr_samples <= 1)
2612 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2613 } else if (!rtex->tc_compatible_htile) {
2614 /* Use all of the htile_buffer for depth if there's no stencil.
2615 * This must not be set when TC-compatible HTILE is enabled
2616 * due to a hw bug.
2617 */
2618 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2619 }
2620
2621 surf->db_htile_data_base = (rtex->resource.gpu_address +
2622 rtex->htile_offset) >> 8;
2623 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2624
2625 if (rtex->tc_compatible_htile) {
2626 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2627
2628 if (rtex->resource.b.b.nr_samples <= 1)
2629 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2630 else if (rtex->resource.b.b.nr_samples <= 4)
2631 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2632 else
2633 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2634 }
2635 }
2636 }
2637
2638 surf->db_z_info = z_info;
2639 surf->db_stencil_info = s_info;
2640
2641 surf->depth_initialized = true;
2642 }
2643
2644 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2645 {
2646 if (sctx->decompression_enabled)
2647 return;
2648
2649 if (sctx->framebuffer.state.zsbuf) {
2650 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2651 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2652
2653 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2654
2655 if (rtex->surface.has_stencil)
2656 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2657 }
2658
2659 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2660 while (compressed_cb_mask) {
2661 unsigned i = u_bit_scan(&compressed_cb_mask);
2662 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2663 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2664
2665 if (rtex->fmask.size)
2666 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2667 if (rtex->dcc_gather_statistics)
2668 rtex->separate_dcc_dirty = true;
2669 }
2670 }
2671
2672 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2673 {
2674 for (int i = 0; i < state->nr_cbufs; ++i) {
2675 struct r600_surface *surf = NULL;
2676 struct r600_texture *rtex;
2677
2678 if (!state->cbufs[i])
2679 continue;
2680 surf = (struct r600_surface*)state->cbufs[i];
2681 rtex = (struct r600_texture*)surf->base.texture;
2682
2683 p_atomic_dec(&rtex->framebuffers_bound);
2684 }
2685 }
2686
2687 static void si_set_framebuffer_state(struct pipe_context *ctx,
2688 const struct pipe_framebuffer_state *state)
2689 {
2690 struct si_context *sctx = (struct si_context *)ctx;
2691 struct pipe_constant_buffer constbuf = {0};
2692 struct r600_surface *surf = NULL;
2693 struct r600_texture *rtex;
2694 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2695 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2696 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2697 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2698 bool old_has_stencil =
2699 old_has_zsbuf &&
2700 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2701 bool unbound = false;
2702 int i;
2703
2704 si_update_fb_dirtiness_after_rendering(sctx);
2705
2706 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2707 if (!sctx->framebuffer.state.cbufs[i])
2708 continue;
2709
2710 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2711 if (rtex->dcc_gather_statistics)
2712 vi_separate_dcc_stop_query(ctx, rtex);
2713 }
2714
2715 /* Disable DCC if the formats are incompatible. */
2716 for (i = 0; i < state->nr_cbufs; i++) {
2717 if (!state->cbufs[i])
2718 continue;
2719
2720 surf = (struct r600_surface*)state->cbufs[i];
2721 rtex = (struct r600_texture*)surf->base.texture;
2722
2723 if (!surf->dcc_incompatible)
2724 continue;
2725
2726 /* Since the DCC decompression calls back into set_framebuffer-
2727 * _state, we need to unbind the framebuffer, so that
2728 * vi_separate_dcc_stop_query isn't called twice with the same
2729 * color buffer.
2730 */
2731 if (!unbound) {
2732 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2733 unbound = true;
2734 }
2735
2736 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2737 if (!si_texture_disable_dcc(&sctx->b, rtex))
2738 sctx->b.decompress_dcc(ctx, rtex);
2739
2740 surf->dcc_incompatible = false;
2741 }
2742
2743 /* Only flush TC when changing the framebuffer state, because
2744 * the only client not using TC that can change textures is
2745 * the framebuffer.
2746 *
2747 * Wait for compute shaders because of possible transitions:
2748 * - FB write -> shader read
2749 * - shader write -> FB read
2750 *
2751 * DB caches are flushed on demand (using si_decompress_textures).
2752 *
2753 * When MSAA is enabled, CB and TC caches are flushed on demand
2754 * (after FMASK decompression). Shader write -> FB read transitions
2755 * cannot happen for MSAA textures, because MSAA shader images are
2756 * not supported.
2757 *
2758 * Only flush and wait for CB if there is actually a bound color buffer.
2759 */
2760 if (sctx->framebuffer.nr_samples <= 1 &&
2761 sctx->framebuffer.state.nr_cbufs)
2762 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2763 sctx->framebuffer.CB_has_shader_readable_metadata);
2764
2765 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2766
2767 /* u_blitter doesn't invoke depth decompression when it does multiple
2768 * blits in a row, but the only case when it matters for DB is when
2769 * doing generate_mipmap. So here we flush DB manually between
2770 * individual generate_mipmap blits.
2771 * Note that lower mipmap levels aren't compressed.
2772 */
2773 if (sctx->generate_mipmap_for_depth) {
2774 si_make_DB_shader_coherent(sctx, 1, false,
2775 sctx->framebuffer.DB_has_shader_readable_metadata);
2776 } else if (sctx->b.chip_class == GFX9) {
2777 /* It appears that DB metadata "leaks" in a sequence of:
2778 * - depth clear
2779 * - DCC decompress for shader image writes (with DB disabled)
2780 * - render with DEPTH_BEFORE_SHADER=1
2781 * Flushing DB metadata works around the problem.
2782 */
2783 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2784 }
2785
2786 /* Take the maximum of the old and new count. If the new count is lower,
2787 * dirtying is needed to disable the unbound colorbuffers.
2788 */
2789 sctx->framebuffer.dirty_cbufs |=
2790 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2791 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2792
2793 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2794 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2795
2796 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2797 sctx->framebuffer.spi_shader_col_format = 0;
2798 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2799 sctx->framebuffer.spi_shader_col_format_blend = 0;
2800 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2801 sctx->framebuffer.color_is_int8 = 0;
2802 sctx->framebuffer.color_is_int10 = 0;
2803
2804 sctx->framebuffer.compressed_cb_mask = 0;
2805 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2806 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2807 sctx->framebuffer.any_dst_linear = false;
2808 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2809 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2810
2811 for (i = 0; i < state->nr_cbufs; i++) {
2812 if (!state->cbufs[i])
2813 continue;
2814
2815 surf = (struct r600_surface*)state->cbufs[i];
2816 rtex = (struct r600_texture*)surf->base.texture;
2817
2818 if (!surf->color_initialized) {
2819 si_initialize_color_surface(sctx, surf);
2820 }
2821
2822 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2823 sctx->framebuffer.spi_shader_col_format |=
2824 surf->spi_shader_col_format << (i * 4);
2825 sctx->framebuffer.spi_shader_col_format_alpha |=
2826 surf->spi_shader_col_format_alpha << (i * 4);
2827 sctx->framebuffer.spi_shader_col_format_blend |=
2828 surf->spi_shader_col_format_blend << (i * 4);
2829 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2830 surf->spi_shader_col_format_blend_alpha << (i * 4);
2831
2832 if (surf->color_is_int8)
2833 sctx->framebuffer.color_is_int8 |= 1 << i;
2834 if (surf->color_is_int10)
2835 sctx->framebuffer.color_is_int10 |= 1 << i;
2836
2837 if (rtex->fmask.size) {
2838 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2839 }
2840
2841 if (rtex->surface.is_linear)
2842 sctx->framebuffer.any_dst_linear = true;
2843
2844 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2845 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2846
2847 r600_context_add_resource_size(ctx, surf->base.texture);
2848
2849 p_atomic_inc(&rtex->framebuffers_bound);
2850
2851 if (rtex->dcc_gather_statistics) {
2852 /* Dirty tracking must be enabled for DCC usage analysis. */
2853 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2854 vi_separate_dcc_start_query(ctx, rtex);
2855 }
2856 }
2857
2858 struct r600_texture *zstex = NULL;
2859
2860 if (state->zsbuf) {
2861 surf = (struct r600_surface*)state->zsbuf;
2862 zstex = (struct r600_texture*)surf->base.texture;
2863
2864 if (!surf->depth_initialized) {
2865 si_init_depth_surface(sctx, surf);
2866 }
2867
2868 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2869 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2870
2871 r600_context_add_resource_size(ctx, surf->base.texture);
2872 }
2873
2874 si_update_poly_offset_state(sctx);
2875 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2876 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2877
2878 if (sctx->screen->dpbb_allowed)
2879 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2880
2881 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2882 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2883
2884 if (sctx->screen->has_out_of_order_rast &&
2885 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2886 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2887 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2888 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2889
2890 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2891 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2892 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2893
2894 /* Set sample locations as fragment shader constants. */
2895 switch (sctx->framebuffer.nr_samples) {
2896 case 1:
2897 constbuf.user_buffer = sctx->sample_locations_1x;
2898 break;
2899 case 2:
2900 constbuf.user_buffer = sctx->sample_locations_2x;
2901 break;
2902 case 4:
2903 constbuf.user_buffer = sctx->sample_locations_4x;
2904 break;
2905 case 8:
2906 constbuf.user_buffer = sctx->sample_locations_8x;
2907 break;
2908 case 16:
2909 constbuf.user_buffer = sctx->sample_locations_16x;
2910 break;
2911 default:
2912 R600_ERR("Requested an invalid number of samples %i.\n",
2913 sctx->framebuffer.nr_samples);
2914 assert(0);
2915 }
2916 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2917 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2918
2919 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2920 }
2921
2922 sctx->do_update_shaders = true;
2923
2924 if (!sctx->decompression_enabled) {
2925 /* Prevent textures decompression when the framebuffer state
2926 * changes come from the decompression passes themselves.
2927 */
2928 sctx->need_check_render_feedback = true;
2929 }
2930 }
2931
2932 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2933 {
2934 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2935 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2936 unsigned i, nr_cbufs = state->nr_cbufs;
2937 struct r600_texture *tex = NULL;
2938 struct r600_surface *cb = NULL;
2939 unsigned cb_color_info = 0;
2940
2941 /* Colorbuffers. */
2942 for (i = 0; i < nr_cbufs; i++) {
2943 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2944 unsigned cb_color_attrib;
2945
2946 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2947 continue;
2948
2949 cb = (struct r600_surface*)state->cbufs[i];
2950 if (!cb) {
2951 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2952 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2953 continue;
2954 }
2955
2956 tex = (struct r600_texture *)cb->base.texture;
2957 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2958 &tex->resource, RADEON_USAGE_READWRITE,
2959 tex->resource.b.b.nr_samples > 1 ?
2960 RADEON_PRIO_COLOR_BUFFER_MSAA :
2961 RADEON_PRIO_COLOR_BUFFER);
2962
2963 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2964 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2965 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2966 RADEON_PRIO_CMASK);
2967 }
2968
2969 if (tex->dcc_separate_buffer)
2970 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2971 tex->dcc_separate_buffer,
2972 RADEON_USAGE_READWRITE,
2973 RADEON_PRIO_DCC);
2974
2975 /* Compute mutable surface parameters. */
2976 cb_color_base = tex->resource.gpu_address >> 8;
2977 cb_color_fmask = 0;
2978 cb_dcc_base = 0;
2979 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2980 cb_color_attrib = cb->cb_color_attrib;
2981
2982 if (tex->fmask.size) {
2983 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2984 cb_color_fmask |= tex->fmask.tile_swizzle;
2985 }
2986
2987 /* Set up DCC. */
2988 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2989 bool is_msaa_resolve_dst = state->cbufs[0] &&
2990 state->cbufs[0]->texture->nr_samples > 1 &&
2991 state->cbufs[1] == &cb->base &&
2992 state->cbufs[1]->texture->nr_samples <= 1;
2993
2994 if (!is_msaa_resolve_dst)
2995 cb_color_info |= S_028C70_DCC_ENABLE(1);
2996
2997 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2998 tex->dcc_offset) >> 8;
2999 cb_dcc_base |= tex->surface.tile_swizzle;
3000 }
3001
3002 if (sctx->b.chip_class >= GFX9) {
3003 struct gfx9_surf_meta_flags meta;
3004
3005 if (tex->dcc_offset)
3006 meta = tex->surface.u.gfx9.dcc;
3007 else
3008 meta = tex->surface.u.gfx9.cmask;
3009
3010 /* Set mutable surface parameters. */
3011 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3012 cb_color_base |= tex->surface.tile_swizzle;
3013 if (!tex->fmask.size)
3014 cb_color_fmask = cb_color_base;
3015 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3016 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3017 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3018 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3019
3020 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3021 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3022 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
3023 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3024 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3025 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3026 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3027 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3028 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3029 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
3030 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3031 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
3032 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3033 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3034 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3035 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
3036
3037 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3038 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3039 } else {
3040 /* Compute mutable surface parameters (SI-CI-VI). */
3041 const struct legacy_surf_level *level_info =
3042 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3043 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3044 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3045
3046 cb_color_base += level_info->offset >> 8;
3047 /* Only macrotiled modes can set tile swizzle. */
3048 if (level_info->mode == RADEON_SURF_MODE_2D)
3049 cb_color_base |= tex->surface.tile_swizzle;
3050
3051 if (!tex->fmask.size)
3052 cb_color_fmask = cb_color_base;
3053 if (cb_dcc_base)
3054 cb_dcc_base += level_info->dcc_offset >> 8;
3055
3056 pitch_tile_max = level_info->nblk_x / 8 - 1;
3057 slice_tile_max = level_info->nblk_x *
3058 level_info->nblk_y / 64 - 1;
3059 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3060
3061 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3062 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3063 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3064
3065 if (tex->fmask.size) {
3066 if (sctx->b.chip_class >= CIK)
3067 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3068 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3069 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3070 } else {
3071 /* This must be set for fast clear to work without FMASK. */
3072 if (sctx->b.chip_class >= CIK)
3073 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3074 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3075 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3076 }
3077
3078 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3079 sctx->b.chip_class >= VI ? 14 : 13);
3080 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3081 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3082 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3083 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3084 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3085 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3086 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3087 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3088 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3089 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3090 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3091 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3092 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3093
3094 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3095 radeon_emit(cs, cb_dcc_base);
3096 }
3097 }
3098 for (; i < 8 ; i++)
3099 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3100 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3101
3102 /* ZS buffer. */
3103 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3104 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3105 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3106
3107 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3108 &rtex->resource, RADEON_USAGE_READWRITE,
3109 zb->base.texture->nr_samples > 1 ?
3110 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3111 RADEON_PRIO_DEPTH_BUFFER);
3112
3113 if (sctx->b.chip_class >= GFX9) {
3114 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3115 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3116 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3117 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3118
3119 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3120 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3121 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3122 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3123 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3124 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3125 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3126 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3127 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3128 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3129 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3130 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3131
3132 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3133 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3134 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3135 } else {
3136 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3137
3138 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3139 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3140 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3141 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3142 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3143 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3144 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3145 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3146 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3147 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3148 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3149 }
3150
3151 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3152 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3153 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3154
3155 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3156 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3157 } else if (sctx->framebuffer.dirty_zsbuf) {
3158 if (sctx->b.chip_class >= GFX9)
3159 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3160 else
3161 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3162
3163 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3164 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3165 }
3166
3167 /* Framebuffer dimensions. */
3168 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3169 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3170 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3171
3172 if (sctx->screen->dfsm_allowed) {
3173 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3174 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3175 }
3176
3177 sctx->framebuffer.dirty_cbufs = 0;
3178 sctx->framebuffer.dirty_zsbuf = false;
3179 }
3180
3181 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3182 struct r600_atom *atom)
3183 {
3184 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3185 unsigned nr_samples = sctx->framebuffer.nr_samples;
3186 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3187
3188 /* Smoothing (only possible with nr_samples == 1) uses the same
3189 * sample locations as the MSAA it simulates.
3190 */
3191 if (nr_samples <= 1 && sctx->smoothing_enabled)
3192 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3193
3194 /* On Polaris, the small primitive filter uses the sample locations
3195 * even when MSAA is off, so we need to make sure they're set to 0.
3196 */
3197 if (has_msaa_sample_loc_bug)
3198 nr_samples = MAX2(nr_samples, 1);
3199
3200 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3201 sctx->msaa_sample_locs.nr_samples = nr_samples;
3202 si_emit_sample_locations(cs, nr_samples);
3203 }
3204
3205 if (sctx->b.family >= CHIP_POLARIS10) {
3206 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3207 unsigned small_prim_filter_cntl =
3208 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3209 /* line bug */
3210 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3211
3212 /* The alternative of setting sample locations to 0 would
3213 * require a DB flush to avoid Z errors, see
3214 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3215 */
3216 if (has_msaa_sample_loc_bug &&
3217 sctx->framebuffer.nr_samples > 1 &&
3218 rs && !rs->multisample_enable)
3219 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3220
3221 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3222 small_prim_filter_cntl);
3223 }
3224 }
3225
3226 static bool si_out_of_order_rasterization(struct si_context *sctx)
3227 {
3228 struct si_state_blend *blend = sctx->queued.named.blend;
3229 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3230
3231 if (!sctx->screen->has_out_of_order_rast)
3232 return false;
3233
3234 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3235
3236 if (blend) {
3237 colormask &= blend->cb_target_enabled_4bit;
3238 } else {
3239 colormask = 0;
3240 }
3241
3242 /* Conservative: No logic op. */
3243 if (colormask && blend->logicop_enable)
3244 return false;
3245
3246 struct si_dsa_order_invariance dsa_order_invariant = {
3247 .zs = true, .pass_set = true, .pass_last = false
3248 };
3249
3250 if (sctx->framebuffer.state.zsbuf) {
3251 struct r600_texture *zstex =
3252 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3253 bool has_stencil = zstex->surface.has_stencil;
3254 dsa_order_invariant = dsa->order_invariance[has_stencil];
3255 if (!dsa_order_invariant.zs)
3256 return false;
3257
3258 /* The set of PS invocations is always order invariant,
3259 * except when early Z/S tests are requested. */
3260 if (sctx->ps_shader.cso &&
3261 sctx->ps_shader.cso->info.writes_memory &&
3262 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3263 !dsa_order_invariant.pass_set)
3264 return false;
3265
3266 if (sctx->b.num_perfect_occlusion_queries != 0 &&
3267 !dsa_order_invariant.pass_set)
3268 return false;
3269 }
3270
3271 if (!colormask)
3272 return true;
3273
3274 unsigned blendmask = colormask & blend->blend_enable_4bit;
3275
3276 if (blendmask) {
3277 /* Only commutative blending. */
3278 if (blendmask & ~blend->commutative_4bit)
3279 return false;
3280
3281 if (!dsa_order_invariant.pass_set)
3282 return false;
3283 }
3284
3285 if (colormask & ~blendmask) {
3286 if (!dsa_order_invariant.pass_last)
3287 return false;
3288 }
3289
3290 return true;
3291 }
3292
3293 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3294 {
3295 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3296 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
3297 /* 33% faster rendering to linear color buffers */
3298 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3299 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3300 unsigned sc_mode_cntl_1 =
3301 S_028A4C_WALK_SIZE(dst_is_linear) |
3302 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3303 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3304 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3305 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3306 /* always 1: */
3307 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3308 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3309 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3310 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3311 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3312 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3313
3314 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3315 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3316
3317 /* Required by OpenGL line rasterization.
3318 *
3319 * TODO: We should also enable perpendicular endcaps for AA lines,
3320 * but that requires implementing line stippling in the pixel
3321 * shader. SC can only do line stippling with axis-aligned
3322 * endcaps.
3323 */
3324 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3325
3326 if (setup_samples > 1) {
3327 /* distance from the pixel center, indexed by log2(nr_samples) */
3328 static unsigned max_dist[] = {
3329 0, /* unused */
3330 4, /* 2x MSAA */
3331 6, /* 4x MSAA */
3332 7, /* 8x MSAA */
3333 8, /* 16x MSAA */
3334 };
3335 unsigned log_samples = util_logbase2(setup_samples);
3336 unsigned log_ps_iter_samples =
3337 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
3338
3339 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3340 radeon_emit(cs, sc_line_cntl |
3341 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3342 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3343 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3344 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3345
3346 if (sctx->framebuffer.nr_samples > 1) {
3347 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3348 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3349 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3350 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3351 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3352 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3353 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3354 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3355 S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
3356 sc_mode_cntl_1);
3357 } else if (sctx->smoothing_enabled) {
3358 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3359 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3360 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3361 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3362 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3363 sc_mode_cntl_1);
3364 }
3365 } else {
3366 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3367 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3368 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3369
3370 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3371 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3372 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3373 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3374 sc_mode_cntl_1);
3375 }
3376
3377 /* GFX9: Flush DFSM when the AA mode changes. */
3378 if (sctx->screen->dfsm_allowed) {
3379 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3380 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3381 }
3382 }
3383
3384 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3385 {
3386 struct si_context *sctx = (struct si_context *)ctx;
3387
3388 if (sctx->ps_iter_samples == min_samples)
3389 return;
3390
3391 sctx->ps_iter_samples = min_samples;
3392 sctx->do_update_shaders = true;
3393
3394 if (sctx->framebuffer.nr_samples > 1)
3395 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3396 if (sctx->screen->dpbb_allowed)
3397 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3398 }
3399
3400 /*
3401 * Samplers
3402 */
3403
3404 /**
3405 * Build the sampler view descriptor for a buffer texture.
3406 * @param state 256-bit descriptor; only the high 128 bits are filled in
3407 */
3408 void
3409 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3410 enum pipe_format format,
3411 unsigned offset, unsigned size,
3412 uint32_t *state)
3413 {
3414 const struct util_format_description *desc;
3415 int first_non_void;
3416 unsigned stride;
3417 unsigned num_records;
3418 unsigned num_format, data_format;
3419
3420 desc = util_format_description(format);
3421 first_non_void = util_format_get_first_non_void_channel(format);
3422 stride = desc->block.bits / 8;
3423 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3424 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3425
3426 num_records = size / stride;
3427 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3428
3429 /* The NUM_RECORDS field has a different meaning depending on the chip,
3430 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3431 *
3432 * SI-CIK:
3433 * - If STRIDE == 0, it's in byte units.
3434 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3435 *
3436 * VI:
3437 * - For SMEM and STRIDE == 0, it's in byte units.
3438 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3439 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3440 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3441 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3442 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3443 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3444 * That way the same descriptor can be used by both SMEM and VMEM.
3445 *
3446 * GFX9:
3447 * - For SMEM and STRIDE == 0, it's in byte units.
3448 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3449 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3450 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3451 */
3452 if (screen->b.chip_class >= GFX9)
3453 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3454 * from STRIDE to bytes. This works around it by setting
3455 * NUM_RECORDS to at least the size of one element, so that
3456 * the first element is readable when IDXEN == 0.
3457 *
3458 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3459 * IDXEN is enforced?
3460 */
3461 num_records = num_records ? MAX2(num_records, stride) : 0;
3462 else if (screen->b.chip_class == VI)
3463 num_records *= stride;
3464
3465 state[4] = 0;
3466 state[5] = S_008F04_STRIDE(stride);
3467 state[6] = num_records;
3468 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3469 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3470 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3471 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3472 S_008F0C_NUM_FORMAT(num_format) |
3473 S_008F0C_DATA_FORMAT(data_format);
3474 }
3475
3476 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3477 {
3478 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3479
3480 if (swizzle[3] == PIPE_SWIZZLE_X) {
3481 /* For the pre-defined border color values (white, opaque
3482 * black, transparent black), the only thing that matters is
3483 * that the alpha channel winds up in the correct place
3484 * (because the RGB channels are all the same) so either of
3485 * these enumerations will work.
3486 */
3487 if (swizzle[2] == PIPE_SWIZZLE_Y)
3488 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3489 else
3490 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3491 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3492 if (swizzle[1] == PIPE_SWIZZLE_Y)
3493 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3494 else
3495 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3496 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3497 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3498 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3499 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3500 }
3501
3502 return bc_swizzle;
3503 }
3504
3505 /**
3506 * Build the sampler view descriptor for a texture.
3507 */
3508 void
3509 si_make_texture_descriptor(struct si_screen *screen,
3510 struct r600_texture *tex,
3511 bool sampler,
3512 enum pipe_texture_target target,
3513 enum pipe_format pipe_format,
3514 const unsigned char state_swizzle[4],
3515 unsigned first_level, unsigned last_level,
3516 unsigned first_layer, unsigned last_layer,
3517 unsigned width, unsigned height, unsigned depth,
3518 uint32_t *state,
3519 uint32_t *fmask_state)
3520 {
3521 struct pipe_resource *res = &tex->resource.b.b;
3522 const struct util_format_description *desc;
3523 unsigned char swizzle[4];
3524 int first_non_void;
3525 unsigned num_format, data_format, type;
3526 uint64_t va;
3527
3528 desc = util_format_description(pipe_format);
3529
3530 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3531 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3532 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3533 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3534
3535 switch (pipe_format) {
3536 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3537 case PIPE_FORMAT_X32_S8X24_UINT:
3538 case PIPE_FORMAT_X8Z24_UNORM:
3539 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3540 break;
3541 case PIPE_FORMAT_X24S8_UINT:
3542 /*
3543 * X24S8 is implemented as an 8_8_8_8 data format, to
3544 * fix texture gathers. This affects at least
3545 * GL45-CTS.texture_cube_map_array.sampling on VI.
3546 */
3547 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3548 break;
3549 default:
3550 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3551 }
3552 } else {
3553 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3554 }
3555
3556 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3557
3558 switch (pipe_format) {
3559 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3560 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3561 break;
3562 default:
3563 if (first_non_void < 0) {
3564 if (util_format_is_compressed(pipe_format)) {
3565 switch (pipe_format) {
3566 case PIPE_FORMAT_DXT1_SRGB:
3567 case PIPE_FORMAT_DXT1_SRGBA:
3568 case PIPE_FORMAT_DXT3_SRGBA:
3569 case PIPE_FORMAT_DXT5_SRGBA:
3570 case PIPE_FORMAT_BPTC_SRGBA:
3571 case PIPE_FORMAT_ETC2_SRGB8:
3572 case PIPE_FORMAT_ETC2_SRGB8A1:
3573 case PIPE_FORMAT_ETC2_SRGBA8:
3574 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3575 break;
3576 case PIPE_FORMAT_RGTC1_SNORM:
3577 case PIPE_FORMAT_LATC1_SNORM:
3578 case PIPE_FORMAT_RGTC2_SNORM:
3579 case PIPE_FORMAT_LATC2_SNORM:
3580 case PIPE_FORMAT_ETC2_R11_SNORM:
3581 case PIPE_FORMAT_ETC2_RG11_SNORM:
3582 /* implies float, so use SNORM/UNORM to determine
3583 whether data is signed or not */
3584 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3585 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3586 break;
3587 default:
3588 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3589 break;
3590 }
3591 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3592 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3593 } else {
3594 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3595 }
3596 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3597 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3598 } else {
3599 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3600
3601 switch (desc->channel[first_non_void].type) {
3602 case UTIL_FORMAT_TYPE_FLOAT:
3603 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3604 break;
3605 case UTIL_FORMAT_TYPE_SIGNED:
3606 if (desc->channel[first_non_void].normalized)
3607 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3608 else if (desc->channel[first_non_void].pure_integer)
3609 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3610 else
3611 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3612 break;
3613 case UTIL_FORMAT_TYPE_UNSIGNED:
3614 if (desc->channel[first_non_void].normalized)
3615 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3616 else if (desc->channel[first_non_void].pure_integer)
3617 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3618 else
3619 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3620 }
3621 }
3622 }
3623
3624 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3625 if (data_format == ~0) {
3626 data_format = 0;
3627 }
3628
3629 /* S8 with Z32 HTILE needs a special format. */
3630 if (screen->b.chip_class >= GFX9 &&
3631 pipe_format == PIPE_FORMAT_S8_UINT &&
3632 tex->tc_compatible_htile)
3633 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3634
3635 if (!sampler &&
3636 (res->target == PIPE_TEXTURE_CUBE ||
3637 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3638 (screen->b.chip_class <= VI &&
3639 res->target == PIPE_TEXTURE_3D))) {
3640 /* For the purpose of shader images, treat cube maps and 3D
3641 * textures as 2D arrays. For 3D textures, the address
3642 * calculations for mipmaps are different, so we rely on the
3643 * caller to effectively disable mipmaps.
3644 */
3645 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3646
3647 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3648 } else {
3649 type = si_tex_dim(screen, tex, target, res->nr_samples);
3650 }
3651
3652 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3653 height = 1;
3654 depth = res->array_size;
3655 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3656 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3657 if (sampler || res->target != PIPE_TEXTURE_3D)
3658 depth = res->array_size;
3659 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3660 depth = res->array_size / 6;
3661
3662 state[0] = 0;
3663 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3664 S_008F14_NUM_FORMAT_GFX6(num_format));
3665 state[2] = (S_008F18_WIDTH(width - 1) |
3666 S_008F18_HEIGHT(height - 1) |
3667 S_008F18_PERF_MOD(4));
3668 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3669 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3670 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3671 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3672 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3673 0 : first_level) |
3674 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3675 util_logbase2(res->nr_samples) :
3676 last_level) |
3677 S_008F1C_TYPE(type));
3678 state[4] = 0;
3679 state[5] = S_008F24_BASE_ARRAY(first_layer);
3680 state[6] = 0;
3681 state[7] = 0;
3682
3683 if (screen->b.chip_class >= GFX9) {
3684 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3685
3686 /* Depth is the the last accessible layer on Gfx9.
3687 * The hw doesn't need to know the total number of layers.
3688 */
3689 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3690 state[4] |= S_008F20_DEPTH(depth - 1);
3691 else
3692 state[4] |= S_008F20_DEPTH(last_layer);
3693
3694 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3695 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3696 util_logbase2(res->nr_samples) :
3697 tex->resource.b.b.last_level);
3698 } else {
3699 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3700 state[4] |= S_008F20_DEPTH(depth - 1);
3701 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3702 }
3703
3704 if (tex->dcc_offset) {
3705 unsigned swap = si_translate_colorswap(pipe_format, false);
3706
3707 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3708 } else {
3709 /* The last dword is unused by hw. The shader uses it to clear
3710 * bits in the first dword of sampler state.
3711 */
3712 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3713 if (first_level == last_level)
3714 state[7] = C_008F30_MAX_ANISO_RATIO;
3715 else
3716 state[7] = 0xffffffff;
3717 }
3718 }
3719
3720 /* Initialize the sampler view for FMASK. */
3721 if (tex->fmask.size) {
3722 uint32_t data_format, num_format;
3723
3724 va = tex->resource.gpu_address + tex->fmask.offset;
3725
3726 if (screen->b.chip_class >= GFX9) {
3727 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3728 switch (res->nr_samples) {
3729 case 2:
3730 num_format = V_008F14_IMG_FMASK_8_2_2;
3731 break;
3732 case 4:
3733 num_format = V_008F14_IMG_FMASK_8_4_4;
3734 break;
3735 case 8:
3736 num_format = V_008F14_IMG_FMASK_32_8_8;
3737 break;
3738 default:
3739 unreachable("invalid nr_samples");
3740 }
3741 } else {
3742 switch (res->nr_samples) {
3743 case 2:
3744 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3745 break;
3746 case 4:
3747 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3748 break;
3749 case 8:
3750 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3751 break;
3752 default:
3753 unreachable("invalid nr_samples");
3754 }
3755 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3756 }
3757
3758 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3759 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3760 S_008F14_DATA_FORMAT_GFX6(data_format) |
3761 S_008F14_NUM_FORMAT_GFX6(num_format);
3762 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3763 S_008F18_HEIGHT(height - 1);
3764 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3765 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3766 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3767 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3768 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3769 fmask_state[4] = 0;
3770 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3771 fmask_state[6] = 0;
3772 fmask_state[7] = 0;
3773
3774 if (screen->b.chip_class >= GFX9) {
3775 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3776 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3777 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3778 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3779 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3780 } else {
3781 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3782 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3783 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3784 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3785 }
3786 }
3787 }
3788
3789 /**
3790 * Create a sampler view.
3791 *
3792 * @param ctx context
3793 * @param texture texture
3794 * @param state sampler view template
3795 * @param width0 width0 override (for compressed textures as int)
3796 * @param height0 height0 override (for compressed textures as int)
3797 * @param force_level set the base address to the level (for compressed textures)
3798 */
3799 struct pipe_sampler_view *
3800 si_create_sampler_view_custom(struct pipe_context *ctx,
3801 struct pipe_resource *texture,
3802 const struct pipe_sampler_view *state,
3803 unsigned width0, unsigned height0,
3804 unsigned force_level)
3805 {
3806 struct si_context *sctx = (struct si_context*)ctx;
3807 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3808 struct r600_texture *tmp = (struct r600_texture*)texture;
3809 unsigned base_level, first_level, last_level;
3810 unsigned char state_swizzle[4];
3811 unsigned height, depth, width;
3812 unsigned last_layer = state->u.tex.last_layer;
3813 enum pipe_format pipe_format;
3814 const struct legacy_surf_level *surflevel;
3815
3816 if (!view)
3817 return NULL;
3818
3819 /* initialize base object */
3820 view->base = *state;
3821 view->base.texture = NULL;
3822 view->base.reference.count = 1;
3823 view->base.context = ctx;
3824
3825 assert(texture);
3826 pipe_resource_reference(&view->base.texture, texture);
3827
3828 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3829 state->format == PIPE_FORMAT_S8X24_UINT ||
3830 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3831 state->format == PIPE_FORMAT_S8_UINT)
3832 view->is_stencil_sampler = true;
3833
3834 /* Buffer resource. */
3835 if (texture->target == PIPE_BUFFER) {
3836 si_make_buffer_descriptor(sctx->screen,
3837 (struct r600_resource *)texture,
3838 state->format,
3839 state->u.buf.offset,
3840 state->u.buf.size,
3841 view->state);
3842 return &view->base;
3843 }
3844
3845 state_swizzle[0] = state->swizzle_r;
3846 state_swizzle[1] = state->swizzle_g;
3847 state_swizzle[2] = state->swizzle_b;
3848 state_swizzle[3] = state->swizzle_a;
3849
3850 base_level = 0;
3851 first_level = state->u.tex.first_level;
3852 last_level = state->u.tex.last_level;
3853 width = width0;
3854 height = height0;
3855 depth = texture->depth0;
3856
3857 if (sctx->b.chip_class <= VI && force_level) {
3858 assert(force_level == first_level &&
3859 force_level == last_level);
3860 base_level = force_level;
3861 first_level = 0;
3862 last_level = 0;
3863 width = u_minify(width, force_level);
3864 height = u_minify(height, force_level);
3865 depth = u_minify(depth, force_level);
3866 }
3867
3868 /* This is not needed if state trackers set last_layer correctly. */
3869 if (state->target == PIPE_TEXTURE_1D ||
3870 state->target == PIPE_TEXTURE_2D ||
3871 state->target == PIPE_TEXTURE_RECT ||
3872 state->target == PIPE_TEXTURE_CUBE)
3873 last_layer = state->u.tex.first_layer;
3874
3875 /* Texturing with separate depth and stencil. */
3876 pipe_format = state->format;
3877
3878 /* Depth/stencil texturing sometimes needs separate texture. */
3879 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3880 if (!tmp->flushed_depth_texture &&
3881 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3882 pipe_resource_reference(&view->base.texture, NULL);
3883 FREE(view);
3884 return NULL;
3885 }
3886
3887 assert(tmp->flushed_depth_texture);
3888
3889 /* Override format for the case where the flushed texture
3890 * contains only Z or only S.
3891 */
3892 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3893 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3894
3895 tmp = tmp->flushed_depth_texture;
3896 }
3897
3898 surflevel = tmp->surface.u.legacy.level;
3899
3900 if (tmp->db_compatible) {
3901 if (!view->is_stencil_sampler)
3902 pipe_format = tmp->db_render_format;
3903
3904 switch (pipe_format) {
3905 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3906 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3907 break;
3908 case PIPE_FORMAT_X8Z24_UNORM:
3909 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3910 /* Z24 is always stored like this for DB
3911 * compatibility.
3912 */
3913 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3914 break;
3915 case PIPE_FORMAT_X24S8_UINT:
3916 case PIPE_FORMAT_S8X24_UINT:
3917 case PIPE_FORMAT_X32_S8X24_UINT:
3918 pipe_format = PIPE_FORMAT_S8_UINT;
3919 surflevel = tmp->surface.u.legacy.stencil_level;
3920 break;
3921 default:;
3922 }
3923 }
3924
3925 view->dcc_incompatible =
3926 vi_dcc_formats_are_incompatible(texture,
3927 state->u.tex.first_level,
3928 state->format);
3929
3930 si_make_texture_descriptor(sctx->screen, tmp, true,
3931 state->target, pipe_format, state_swizzle,
3932 first_level, last_level,
3933 state->u.tex.first_layer, last_layer,
3934 width, height, depth,
3935 view->state, view->fmask_state);
3936
3937 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3938 view->is_integer =
3939 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3940 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3941 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3942 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3943 view->base_level_info = &surflevel[base_level];
3944 view->base_level = base_level;
3945 view->block_width = util_format_get_blockwidth(pipe_format);
3946 return &view->base;
3947 }
3948
3949 static struct pipe_sampler_view *
3950 si_create_sampler_view(struct pipe_context *ctx,
3951 struct pipe_resource *texture,
3952 const struct pipe_sampler_view *state)
3953 {
3954 return si_create_sampler_view_custom(ctx, texture, state,
3955 texture ? texture->width0 : 0,
3956 texture ? texture->height0 : 0, 0);
3957 }
3958
3959 static void si_sampler_view_destroy(struct pipe_context *ctx,
3960 struct pipe_sampler_view *state)
3961 {
3962 struct si_sampler_view *view = (struct si_sampler_view *)state;
3963
3964 pipe_resource_reference(&state->texture, NULL);
3965 FREE(view);
3966 }
3967
3968 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3969 {
3970 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3971 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3972 (linear_filter &&
3973 (wrap == PIPE_TEX_WRAP_CLAMP ||
3974 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3975 }
3976
3977 static uint32_t si_translate_border_color(struct si_context *sctx,
3978 const struct pipe_sampler_state *state,
3979 const union pipe_color_union *color,
3980 bool is_integer)
3981 {
3982 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3983 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3984
3985 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
3986 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
3987 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
3988 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
3989
3990 #define simple_border_types(elt) \
3991 do { \
3992 if (color->elt[0] == 0 && color->elt[1] == 0 && \
3993 color->elt[2] == 0 && color->elt[3] == 0) \
3994 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
3995 if (color->elt[0] == 0 && color->elt[1] == 0 && \
3996 color->elt[2] == 0 && color->elt[3] == 1) \
3997 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
3998 if (color->elt[0] == 1 && color->elt[1] == 1 && \
3999 color->elt[2] == 1 && color->elt[3] == 1) \
4000 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4001 } while (false)
4002
4003 if (is_integer)
4004 simple_border_types(ui);
4005 else
4006 simple_border_types(f);
4007
4008 #undef simple_border_types
4009
4010 int i;
4011
4012 /* Check if the border has been uploaded already. */
4013 for (i = 0; i < sctx->border_color_count; i++)
4014 if (memcmp(&sctx->border_color_table[i], color,
4015 sizeof(*color)) == 0)
4016 break;
4017
4018 if (i >= SI_MAX_BORDER_COLORS) {
4019 /* Getting 4096 unique border colors is very unlikely. */
4020 fprintf(stderr, "radeonsi: The border color table is full. "
4021 "Any new border colors will be just black. "
4022 "Please file a bug.\n");
4023 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4024 }
4025
4026 if (i == sctx->border_color_count) {
4027 /* Upload a new border color. */
4028 memcpy(&sctx->border_color_table[i], color,
4029 sizeof(*color));
4030 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4031 color, sizeof(*color));
4032 sctx->border_color_count++;
4033 }
4034
4035 return S_008F3C_BORDER_COLOR_PTR(i) |
4036 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4037 }
4038
4039 static void *si_create_sampler_state(struct pipe_context *ctx,
4040 const struct pipe_sampler_state *state)
4041 {
4042 struct si_context *sctx = (struct si_context *)ctx;
4043 struct r600_common_screen *rscreen = sctx->b.screen;
4044 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4045 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
4046 : state->max_anisotropy;
4047 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
4048 union pipe_color_union clamped_border_color;
4049
4050 if (!rstate) {
4051 return NULL;
4052 }
4053
4054 #ifdef DEBUG
4055 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4056 #endif
4057 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4058 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4059 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4060 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4061 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4062 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4063 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4064 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4065 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4066 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
4067 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4068 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4069 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4070 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4071 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
4072 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
4073 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4074 S_008F38_MIP_POINT_PRECLAMP(0) |
4075 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
4076 S_008F38_FILTER_PREC_FIX(1) |
4077 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
4078 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4079
4080 /* Create sampler resource for integer textures. */
4081 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4082 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4083
4084 /* Create sampler resource for upgraded depth textures. */
4085 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4086
4087 for (unsigned i = 0; i < 4; ++i) {
4088 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4089 * when the border color is 1.0. */
4090 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4091 }
4092
4093 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4094 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4095 else
4096 rstate->upgraded_depth_val[3] =
4097 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4098 S_008F3C_UPGRADED_DEPTH(1);
4099
4100 return rstate;
4101 }
4102
4103 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4104 {
4105 struct si_context *sctx = (struct si_context *)ctx;
4106
4107 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4108 return;
4109
4110 sctx->sample_mask.sample_mask = sample_mask;
4111 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4112 }
4113
4114 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4115 {
4116 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
4117 unsigned mask = sctx->sample_mask.sample_mask;
4118
4119 /* Needed for line and polygon smoothing as well as for the Polaris
4120 * small primitive filter. We expect the state tracker to take care of
4121 * this for us.
4122 */
4123 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4124 (mask & 1 && sctx->blitter->running));
4125
4126 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4127 radeon_emit(cs, mask | (mask << 16));
4128 radeon_emit(cs, mask | (mask << 16));
4129 }
4130
4131 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4132 {
4133 #ifdef DEBUG
4134 struct si_sampler_state *s = state;
4135
4136 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4137 s->magic = 0;
4138 #endif
4139 free(state);
4140 }
4141
4142 /*
4143 * Vertex elements & buffers
4144 */
4145
4146 static void *si_create_vertex_elements(struct pipe_context *ctx,
4147 unsigned count,
4148 const struct pipe_vertex_element *elements)
4149 {
4150 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4151 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4152 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4153 int i;
4154
4155 assert(count <= SI_MAX_ATTRIBS);
4156 if (!v)
4157 return NULL;
4158
4159 v->count = count;
4160 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4161
4162 for (i = 0; i < count; ++i) {
4163 const struct util_format_description *desc;
4164 const struct util_format_channel_description *channel;
4165 unsigned data_format, num_format;
4166 int first_non_void;
4167 unsigned vbo_index = elements[i].vertex_buffer_index;
4168 unsigned char swizzle[4];
4169
4170 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4171 FREE(v);
4172 return NULL;
4173 }
4174
4175 if (elements[i].instance_divisor) {
4176 v->uses_instance_divisors = true;
4177 v->instance_divisors[i] = elements[i].instance_divisor;
4178
4179 if (v->instance_divisors[i] == 1)
4180 v->instance_divisor_is_one |= 1u << i;
4181 else
4182 v->instance_divisor_is_fetched |= 1u << i;
4183 }
4184
4185 if (!used[vbo_index]) {
4186 v->first_vb_use_mask |= 1 << i;
4187 used[vbo_index] = true;
4188 }
4189
4190 desc = util_format_description(elements[i].src_format);
4191 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4192 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4193 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4194 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4195 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4196
4197 v->format_size[i] = desc->block.bits / 8;
4198 v->src_offset[i] = elements[i].src_offset;
4199 v->vertex_buffer_index[i] = vbo_index;
4200
4201 /* The hardware always treats the 2-bit alpha channel as
4202 * unsigned, so a shader workaround is needed. The affected
4203 * chips are VI and older except Stoney (GFX8.1).
4204 */
4205 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4206 sscreen->b.chip_class <= VI &&
4207 sscreen->b.family != CHIP_STONEY) {
4208 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4209 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4210 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4211 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4212 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4213 /* This isn't actually used in OpenGL. */
4214 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4215 }
4216 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4217 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4218 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4219 else
4220 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4221 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4222 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4223 if (channel->normalized) {
4224 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4225 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4226 else
4227 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4228 } else {
4229 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4230 }
4231 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4232 if (channel->normalized) {
4233 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4234 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4235 else
4236 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4237 } else {
4238 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4239 }
4240 }
4241 } else if (channel && channel->size == 64 &&
4242 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4243 switch (desc->nr_channels) {
4244 case 1:
4245 case 2:
4246 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4247 swizzle[0] = PIPE_SWIZZLE_X;
4248 swizzle[1] = PIPE_SWIZZLE_Y;
4249 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4250 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4251 break;
4252 case 3:
4253 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4254 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4255 swizzle[1] = PIPE_SWIZZLE_Y;
4256 swizzle[2] = PIPE_SWIZZLE_0;
4257 swizzle[3] = PIPE_SWIZZLE_0;
4258 break;
4259 case 4:
4260 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4261 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4262 swizzle[1] = PIPE_SWIZZLE_Y;
4263 swizzle[2] = PIPE_SWIZZLE_Z;
4264 swizzle[3] = PIPE_SWIZZLE_W;
4265 break;
4266 default:
4267 assert(0);
4268 }
4269 } else if (channel && desc->nr_channels == 3) {
4270 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4271
4272 if (channel->size == 8) {
4273 if (channel->pure_integer)
4274 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4275 else
4276 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4277 } else if (channel->size == 16) {
4278 if (channel->pure_integer)
4279 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4280 else
4281 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4282 }
4283 }
4284
4285 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4286 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4287 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4288 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4289 S_008F0C_NUM_FORMAT(num_format) |
4290 S_008F0C_DATA_FORMAT(data_format);
4291 }
4292 return v;
4293 }
4294
4295 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4296 {
4297 struct si_context *sctx = (struct si_context *)ctx;
4298 struct si_vertex_elements *old = sctx->vertex_elements;
4299 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4300
4301 sctx->vertex_elements = v;
4302 sctx->vertex_buffers_dirty = true;
4303
4304 if (v &&
4305 (!old ||
4306 old->count != v->count ||
4307 old->uses_instance_divisors != v->uses_instance_divisors ||
4308 v->uses_instance_divisors || /* we don't check which divisors changed */
4309 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4310 sctx->do_update_shaders = true;
4311
4312 if (v && v->instance_divisor_is_fetched) {
4313 struct pipe_constant_buffer cb;
4314
4315 cb.buffer = NULL;
4316 cb.user_buffer = v->instance_divisors;
4317 cb.buffer_offset = 0;
4318 cb.buffer_size = sizeof(uint32_t) * v->count;
4319 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4320 }
4321 }
4322
4323 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4324 {
4325 struct si_context *sctx = (struct si_context *)ctx;
4326
4327 if (sctx->vertex_elements == state)
4328 sctx->vertex_elements = NULL;
4329 FREE(state);
4330 }
4331
4332 static void si_set_vertex_buffers(struct pipe_context *ctx,
4333 unsigned start_slot, unsigned count,
4334 const struct pipe_vertex_buffer *buffers)
4335 {
4336 struct si_context *sctx = (struct si_context *)ctx;
4337 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4338 int i;
4339
4340 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4341
4342 if (buffers) {
4343 for (i = 0; i < count; i++) {
4344 const struct pipe_vertex_buffer *src = buffers + i;
4345 struct pipe_vertex_buffer *dsti = dst + i;
4346 struct pipe_resource *buf = src->buffer.resource;
4347
4348 pipe_resource_reference(&dsti->buffer.resource, buf);
4349 dsti->buffer_offset = src->buffer_offset;
4350 dsti->stride = src->stride;
4351 r600_context_add_resource_size(ctx, buf);
4352 if (buf)
4353 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4354 }
4355 } else {
4356 for (i = 0; i < count; i++) {
4357 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4358 }
4359 }
4360 sctx->vertex_buffers_dirty = true;
4361 }
4362
4363 /*
4364 * Misc
4365 */
4366
4367 static void si_set_tess_state(struct pipe_context *ctx,
4368 const float default_outer_level[4],
4369 const float default_inner_level[2])
4370 {
4371 struct si_context *sctx = (struct si_context *)ctx;
4372 struct pipe_constant_buffer cb;
4373 float array[8];
4374
4375 memcpy(array, default_outer_level, sizeof(float) * 4);
4376 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4377
4378 cb.buffer = NULL;
4379 cb.user_buffer = NULL;
4380 cb.buffer_size = sizeof(array);
4381
4382 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4383 (void*)array, sizeof(array),
4384 &cb.buffer_offset);
4385
4386 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4387 pipe_resource_reference(&cb.buffer, NULL);
4388 }
4389
4390 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4391 {
4392 struct si_context *sctx = (struct si_context *)ctx;
4393
4394 si_update_fb_dirtiness_after_rendering(sctx);
4395
4396 /* Multisample surfaces are flushed in si_decompress_textures. */
4397 if (sctx->framebuffer.nr_samples <= 1 &&
4398 sctx->framebuffer.state.nr_cbufs)
4399 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4400 sctx->framebuffer.CB_has_shader_readable_metadata);
4401 }
4402
4403 /* This only ensures coherency for shader image/buffer stores. */
4404 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4405 {
4406 struct si_context *sctx = (struct si_context *)ctx;
4407
4408 /* Subsequent commands must wait for all shader invocations to
4409 * complete. */
4410 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4411 SI_CONTEXT_CS_PARTIAL_FLUSH;
4412
4413 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4414 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4415 SI_CONTEXT_INV_VMEM_L1;
4416
4417 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4418 PIPE_BARRIER_SHADER_BUFFER |
4419 PIPE_BARRIER_TEXTURE |
4420 PIPE_BARRIER_IMAGE |
4421 PIPE_BARRIER_STREAMOUT_BUFFER |
4422 PIPE_BARRIER_GLOBAL_BUFFER)) {
4423 /* As far as I can tell, L1 contents are written back to L2
4424 * automatically at end of shader, but the contents of other
4425 * L1 caches might still be stale. */
4426 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4427 }
4428
4429 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4430 /* Indices are read through TC L2 since VI.
4431 * L1 isn't used.
4432 */
4433 if (sctx->screen->b.chip_class <= CIK)
4434 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4435 }
4436
4437 /* MSAA color, any depth and any stencil are flushed in
4438 * si_decompress_textures when needed.
4439 */
4440 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4441 sctx->framebuffer.nr_samples <= 1 &&
4442 sctx->framebuffer.state.nr_cbufs) {
4443 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4444
4445 if (sctx->b.chip_class <= VI)
4446 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4447 }
4448
4449 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4450 if (sctx->screen->b.chip_class <= VI &&
4451 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4452 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4453 }
4454
4455 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4456 {
4457 struct pipe_blend_state blend;
4458
4459 memset(&blend, 0, sizeof(blend));
4460 blend.independent_blend_enable = true;
4461 blend.rt[0].colormask = 0xf;
4462 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4463 }
4464
4465 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4466 bool include_draw_vbo)
4467 {
4468 si_need_cs_space((struct si_context*)ctx);
4469 }
4470
4471 static void si_init_config(struct si_context *sctx);
4472
4473 void si_init_state_functions(struct si_context *sctx)
4474 {
4475 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4476 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4477 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4478 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4479 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4480
4481 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4482 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4483 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4484 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4485 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4486 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4487 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4488 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4489 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4490 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4491 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4492
4493 sctx->b.b.create_blend_state = si_create_blend_state;
4494 sctx->b.b.bind_blend_state = si_bind_blend_state;
4495 sctx->b.b.delete_blend_state = si_delete_blend_state;
4496 sctx->b.b.set_blend_color = si_set_blend_color;
4497
4498 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4499 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4500 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4501
4502 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4503 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4504 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4505
4506 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4507 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4508 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4509 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4510 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4511
4512 sctx->b.b.set_clip_state = si_set_clip_state;
4513 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4514
4515 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4516
4517 sctx->b.b.create_sampler_state = si_create_sampler_state;
4518 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4519
4520 sctx->b.b.create_sampler_view = si_create_sampler_view;
4521 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4522
4523 sctx->b.b.set_sample_mask = si_set_sample_mask;
4524
4525 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4526 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4527 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4528 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4529
4530 sctx->b.b.texture_barrier = si_texture_barrier;
4531 sctx->b.b.memory_barrier = si_memory_barrier;
4532 sctx->b.b.set_min_samples = si_set_min_samples;
4533 sctx->b.b.set_tess_state = si_set_tess_state;
4534
4535 sctx->b.b.set_active_query_state = si_set_active_query_state;
4536 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4537 sctx->b.save_qbo_state = si_save_qbo_state;
4538 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4539
4540 sctx->b.b.draw_vbo = si_draw_vbo;
4541
4542 si_init_config(sctx);
4543 }
4544
4545 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4546 {
4547 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4548 }
4549
4550 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4551 struct r600_texture *rtex,
4552 struct radeon_bo_metadata *md)
4553 {
4554 struct si_screen *sscreen = (struct si_screen*)rscreen;
4555 struct pipe_resource *res = &rtex->resource.b.b;
4556 static const unsigned char swizzle[] = {
4557 PIPE_SWIZZLE_X,
4558 PIPE_SWIZZLE_Y,
4559 PIPE_SWIZZLE_Z,
4560 PIPE_SWIZZLE_W
4561 };
4562 uint32_t desc[8], i;
4563 bool is_array = util_resource_is_array_texture(res);
4564
4565 /* DRM 2.x.x doesn't support this. */
4566 if (rscreen->info.drm_major != 3)
4567 return;
4568
4569 assert(rtex->dcc_separate_buffer == NULL);
4570 assert(rtex->fmask.size == 0);
4571
4572 /* Metadata image format format version 1:
4573 * [0] = 1 (metadata format identifier)
4574 * [1] = (VENDOR_ID << 16) | PCI_ID
4575 * [2:9] = image descriptor for the whole resource
4576 * [2] is always 0, because the base address is cleared
4577 * [9] is the DCC offset bits [39:8] from the beginning of
4578 * the buffer
4579 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4580 */
4581
4582 md->metadata[0] = 1; /* metadata image format version 1 */
4583
4584 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4585 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4586
4587 si_make_texture_descriptor(sscreen, rtex, true,
4588 res->target, res->format,
4589 swizzle, 0, res->last_level, 0,
4590 is_array ? res->array_size - 1 : 0,
4591 res->width0, res->height0, res->depth0,
4592 desc, NULL);
4593
4594 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4595 0, 0, rtex->surface.blk_w, false, desc);
4596
4597 /* Clear the base address and set the relative DCC offset. */
4598 desc[0] = 0;
4599 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4600 desc[7] = rtex->dcc_offset >> 8;
4601
4602 /* Dwords [2:9] contain the image descriptor. */
4603 memcpy(&md->metadata[2], desc, sizeof(desc));
4604 md->size_metadata = 10 * 4;
4605
4606 /* Dwords [10:..] contain the mipmap level offsets. */
4607 if (rscreen->chip_class <= VI) {
4608 for (i = 0; i <= res->last_level; i++)
4609 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4610
4611 md->size_metadata += (1 + res->last_level) * 4;
4612 }
4613 }
4614
4615 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4616 struct r600_texture *rtex,
4617 struct radeon_bo_metadata *md)
4618 {
4619 uint32_t *desc = &md->metadata[2];
4620
4621 if (rscreen->chip_class < VI)
4622 return;
4623
4624 /* Return if DCC is enabled. The texture should be set up with it
4625 * already.
4626 */
4627 if (md->size_metadata >= 11 * 4 &&
4628 md->metadata[0] != 0 &&
4629 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4630 G_008F28_COMPRESSION_EN(desc[6])) {
4631 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4632 return;
4633 }
4634
4635 /* Disable DCC. These are always set by texture_from_handle and must
4636 * be cleared here.
4637 */
4638 rtex->dcc_offset = 0;
4639 }
4640
4641 void si_init_screen_state_functions(struct si_screen *sscreen)
4642 {
4643 sscreen->b.b.is_format_supported = si_is_format_supported;
4644 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4645 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4646 }
4647
4648 static void si_set_grbm_gfx_index(struct si_context *sctx,
4649 struct si_pm4_state *pm4, unsigned value)
4650 {
4651 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4652 GRBM_GFX_INDEX;
4653 si_pm4_set_reg(pm4, reg, value);
4654 }
4655
4656 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4657 struct si_pm4_state *pm4, unsigned se)
4658 {
4659 assert(se == ~0 || se < sctx->screen->b.info.max_se);
4660 si_set_grbm_gfx_index(sctx, pm4,
4661 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4662 S_030800_SE_INDEX(se)) |
4663 S_030800_SH_BROADCAST_WRITES(1) |
4664 S_030800_INSTANCE_BROADCAST_WRITES(1));
4665 }
4666
4667 static void
4668 si_write_harvested_raster_configs(struct si_context *sctx,
4669 struct si_pm4_state *pm4,
4670 unsigned raster_config,
4671 unsigned raster_config_1)
4672 {
4673 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4674 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4675 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4676 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4677 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4678 unsigned rb_per_se = num_rb / num_se;
4679 unsigned se_mask[4];
4680 unsigned se;
4681
4682 se_mask[0] = ((1 << rb_per_se) - 1);
4683 se_mask[1] = (se_mask[0] << rb_per_se);
4684 se_mask[2] = (se_mask[1] << rb_per_se);
4685 se_mask[3] = (se_mask[2] << rb_per_se);
4686
4687 se_mask[0] &= rb_mask;
4688 se_mask[1] &= rb_mask;
4689 se_mask[2] &= rb_mask;
4690 se_mask[3] &= rb_mask;
4691
4692 assert(num_se == 1 || num_se == 2 || num_se == 4);
4693 assert(sh_per_se == 1 || sh_per_se == 2);
4694 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4695
4696 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4697 * fields are for, so I'm leaving them as their default
4698 * values. */
4699
4700 for (se = 0; se < num_se; se++) {
4701 unsigned raster_config_se = raster_config;
4702 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4703 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4704 int idx = (se / 2) * 2;
4705
4706 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4707 raster_config_se &= C_028350_SE_MAP;
4708
4709 if (!se_mask[idx]) {
4710 raster_config_se |=
4711 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4712 } else {
4713 raster_config_se |=
4714 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4715 }
4716 }
4717
4718 pkr0_mask &= rb_mask;
4719 pkr1_mask &= rb_mask;
4720 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4721 raster_config_se &= C_028350_PKR_MAP;
4722
4723 if (!pkr0_mask) {
4724 raster_config_se |=
4725 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4726 } else {
4727 raster_config_se |=
4728 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4729 }
4730 }
4731
4732 if (rb_per_se >= 2) {
4733 unsigned rb0_mask = 1 << (se * rb_per_se);
4734 unsigned rb1_mask = rb0_mask << 1;
4735
4736 rb0_mask &= rb_mask;
4737 rb1_mask &= rb_mask;
4738 if (!rb0_mask || !rb1_mask) {
4739 raster_config_se &= C_028350_RB_MAP_PKR0;
4740
4741 if (!rb0_mask) {
4742 raster_config_se |=
4743 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4744 } else {
4745 raster_config_se |=
4746 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4747 }
4748 }
4749
4750 if (rb_per_se > 2) {
4751 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4752 rb1_mask = rb0_mask << 1;
4753 rb0_mask &= rb_mask;
4754 rb1_mask &= rb_mask;
4755 if (!rb0_mask || !rb1_mask) {
4756 raster_config_se &= C_028350_RB_MAP_PKR1;
4757
4758 if (!rb0_mask) {
4759 raster_config_se |=
4760 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4761 } else {
4762 raster_config_se |=
4763 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4764 }
4765 }
4766 }
4767 }
4768
4769 si_set_grbm_gfx_index_se(sctx, pm4, se);
4770 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4771 }
4772 si_set_grbm_gfx_index(sctx, pm4, ~0);
4773
4774 if (sctx->b.chip_class >= CIK) {
4775 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4776 (!se_mask[2] && !se_mask[3]))) {
4777 raster_config_1 &= C_028354_SE_PAIR_MAP;
4778
4779 if (!se_mask[0] && !se_mask[1]) {
4780 raster_config_1 |=
4781 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4782 } else {
4783 raster_config_1 |=
4784 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4785 }
4786 }
4787
4788 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4789 }
4790 }
4791
4792 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4793 {
4794 struct si_screen *sscreen = sctx->screen;
4795 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4796 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4797 unsigned raster_config, raster_config_1;
4798
4799 switch (sctx->b.family) {
4800 case CHIP_TAHITI:
4801 case CHIP_PITCAIRN:
4802 raster_config = 0x2a00126a;
4803 raster_config_1 = 0x00000000;
4804 break;
4805 case CHIP_VERDE:
4806 raster_config = 0x0000124a;
4807 raster_config_1 = 0x00000000;
4808 break;
4809 case CHIP_OLAND:
4810 raster_config = 0x00000082;
4811 raster_config_1 = 0x00000000;
4812 break;
4813 case CHIP_HAINAN:
4814 raster_config = 0x00000000;
4815 raster_config_1 = 0x00000000;
4816 break;
4817 case CHIP_BONAIRE:
4818 raster_config = 0x16000012;
4819 raster_config_1 = 0x00000000;
4820 break;
4821 case CHIP_HAWAII:
4822 raster_config = 0x3a00161a;
4823 raster_config_1 = 0x0000002e;
4824 break;
4825 case CHIP_FIJI:
4826 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4827 /* old kernels with old tiling config */
4828 raster_config = 0x16000012;
4829 raster_config_1 = 0x0000002a;
4830 } else {
4831 raster_config = 0x3a00161a;
4832 raster_config_1 = 0x0000002e;
4833 }
4834 break;
4835 case CHIP_POLARIS10:
4836 raster_config = 0x16000012;
4837 raster_config_1 = 0x0000002a;
4838 break;
4839 case CHIP_POLARIS11:
4840 case CHIP_POLARIS12:
4841 raster_config = 0x16000012;
4842 raster_config_1 = 0x00000000;
4843 break;
4844 case CHIP_TONGA:
4845 raster_config = 0x16000012;
4846 raster_config_1 = 0x0000002a;
4847 break;
4848 case CHIP_ICELAND:
4849 if (num_rb == 1)
4850 raster_config = 0x00000000;
4851 else
4852 raster_config = 0x00000002;
4853 raster_config_1 = 0x00000000;
4854 break;
4855 case CHIP_CARRIZO:
4856 raster_config = 0x00000002;
4857 raster_config_1 = 0x00000000;
4858 break;
4859 case CHIP_KAVERI:
4860 /* KV should be 0x00000002, but that causes problems with radeon */
4861 raster_config = 0x00000000; /* 0x00000002 */
4862 raster_config_1 = 0x00000000;
4863 break;
4864 case CHIP_KABINI:
4865 case CHIP_MULLINS:
4866 case CHIP_STONEY:
4867 raster_config = 0x00000000;
4868 raster_config_1 = 0x00000000;
4869 break;
4870 default:
4871 fprintf(stderr,
4872 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4873 raster_config = 0x00000000;
4874 raster_config_1 = 0x00000000;
4875 }
4876
4877 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4878 /* Always use the default config when all backends are enabled
4879 * (or when we failed to determine the enabled backends).
4880 */
4881 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4882 raster_config);
4883 if (sctx->b.chip_class >= CIK)
4884 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4885 raster_config_1);
4886 } else {
4887 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4888 }
4889 }
4890
4891 static void si_init_config(struct si_context *sctx)
4892 {
4893 struct si_screen *sscreen = sctx->screen;
4894 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4895 bool has_clear_state = sscreen->has_clear_state;
4896 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4897
4898 /* Only SI can disable CLEAR_STATE for now. */
4899 assert(has_clear_state || sscreen->b.chip_class == SI);
4900
4901 if (!pm4)
4902 return;
4903
4904 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4905 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4906 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4907 si_pm4_cmd_end(pm4, false);
4908
4909 if (has_clear_state) {
4910 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4911 si_pm4_cmd_add(pm4, 0);
4912 si_pm4_cmd_end(pm4, false);
4913 }
4914
4915 if (sctx->b.chip_class <= VI)
4916 si_set_raster_config(sctx, pm4);
4917
4918 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4919 if (!has_clear_state)
4920 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4921
4922 /* FIXME calculate these values somehow ??? */
4923 if (sctx->b.chip_class <= VI) {
4924 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4925 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4926 }
4927
4928 if (!has_clear_state) {
4929 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4930 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4931 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4932 }
4933
4934 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4935 if (!has_clear_state)
4936 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4937 if (sctx->b.chip_class < CIK)
4938 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4939 S_008A14_CLIP_VTX_REORDER_ENA(1));
4940
4941 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4942 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4943
4944 if (!has_clear_state)
4945 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4946
4947 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4948 * I don't know why. Deduced by trial and error.
4949 */
4950 if (sctx->b.chip_class <= CIK) {
4951 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4952 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4953 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4954 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4955 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4956 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4957 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4958 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4959 }
4960
4961 if (!has_clear_state) {
4962 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4963 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4964 S_028230_ER_TRI(0xA) |
4965 S_028230_ER_POINT(0xA) |
4966 S_028230_ER_RECT(0xA) |
4967 /* Required by DX10_DIAMOND_TEST_ENA: */
4968 S_028230_ER_LINE_LR(0x1A) |
4969 S_028230_ER_LINE_RL(0x26) |
4970 S_028230_ER_LINE_TB(0xA) |
4971 S_028230_ER_LINE_BT(0xA));
4972 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4973 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4974 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4975 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4976 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4977 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4978 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4979 }
4980
4981 if (sctx->b.chip_class >= GFX9) {
4982 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4983 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4984 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4985 } else {
4986 /* These registers, when written, also overwrite the CLEAR_STATE
4987 * context, so we can't rely on CLEAR_STATE setting them.
4988 * It would be an issue if there was another UMD changing them.
4989 */
4990 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4991 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4992 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4993 }
4994
4995 if (sctx->b.chip_class >= CIK) {
4996 if (sctx->b.chip_class >= GFX9) {
4997 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4998 } else {
4999 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
5000 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
5001 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
5002
5003 /* If this is 0, Bonaire can hang even if GS isn't being used.
5004 * Other chips are unaffected. These are suboptimal values,
5005 * but we don't use on-chip GS.
5006 */
5007 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5008 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5009 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5010 }
5011 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
5012
5013 /* Compute LATE_ALLOC_VS.LIMIT. */
5014 unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
5015 (sscreen->b.info.max_se *
5016 sscreen->b.info.max_sh_per_se);
5017 unsigned late_alloc_limit; /* The limit is per SH. */
5018
5019 if (sctx->b.family == CHIP_KABINI) {
5020 late_alloc_limit = 0; /* Potential hang on Kabini. */
5021 } else if (num_cu_per_sh <= 4) {
5022 /* Too few available compute units per SH. Disallowing
5023 * VS to run on one CU could hurt us more than late VS
5024 * allocation would help.
5025 *
5026 * 2 is the highest safe number that allows us to keep
5027 * all CUs enabled.
5028 */
5029 late_alloc_limit = 2;
5030 } else {
5031 /* This is a good initial value, allowing 1 late_alloc
5032 * wave per SIMD on num_cu - 2.
5033 */
5034 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5035
5036 /* The limit is 0-based, so 0 means 1. */
5037 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5038 late_alloc_limit -= 1;
5039 }
5040
5041 /* VS can't execute on one CU if the limit is > 2. */
5042 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5043 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff));
5044 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5045 S_00B11C_LIMIT(late_alloc_limit));
5046 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
5047 }
5048
5049 if (sctx->b.chip_class >= VI) {
5050 unsigned vgt_tess_distribution;
5051
5052 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
5053 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
5054 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
5055
5056 vgt_tess_distribution =
5057 S_028B50_ACCUM_ISOLINE(32) |
5058 S_028B50_ACCUM_TRI(11) |
5059 S_028B50_ACCUM_QUAD(11) |
5060 S_028B50_DONUT_SPLIT(16);
5061
5062 /* Testing with Unigine Heaven extreme tesselation yielded best results
5063 * with TRAP_SPLIT = 3.
5064 */
5065 if (sctx->b.family == CHIP_FIJI ||
5066 sctx->b.family >= CHIP_POLARIS10)
5067 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5068
5069 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5070 } else if (!has_clear_state) {
5071 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5072 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5073 }
5074
5075 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5076 if (sctx->b.chip_class >= CIK)
5077 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
5078 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5079 RADEON_PRIO_BORDER_COLORS);
5080
5081 if (sctx->b.chip_class >= GFX9) {
5082 unsigned num_se = sscreen->b.info.max_se;
5083 unsigned pc_lines = 0;
5084
5085 switch (sctx->b.family) {
5086 case CHIP_VEGA10:
5087 pc_lines = 4096;
5088 break;
5089 case CHIP_RAVEN:
5090 pc_lines = 1024;
5091 break;
5092 default:
5093 assert(0);
5094 }
5095
5096 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5097 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5098 S_028C48_MAX_PRIM_PER_BATCH(1023));
5099 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5100 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5101 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5102 }
5103
5104 si_pm4_upload_indirect_buffer(sctx, pm4);
5105 sctx->init_config = pm4;
5106 }