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radeonsi: remove all varyings for depth-only rendering or rasterization off
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
76 {
77 return value * (1 << frac_bits);
78 }
79
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x)
82 {
83 return x <= 0 ? 0 :
84 x >= 4096 ? 0xffff : x * 16;
85 }
86
87 /*
88 * Inferred framebuffer and blender state.
89 *
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
92 */
93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_state_blend *blend = sctx->queued.named.blend;
97 uint32_t cb_target_mask, i;
98
99 /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
100 if (blend)
101 cb_target_mask = blend->cb_target_mask;
102 else
103 cb_target_mask = 0xffffffff;
104
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
108 *
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
110 */
111 if (blend && blend->dual_src_blend &&
112 sctx->ps_shader.cso &&
113 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
114 cb_target_mask = 0;
115
116 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
117
118 /* STONEY-specific register settings. */
119 if (sctx->b.family == CHIP_STONEY) {
120 unsigned spi_shader_col_format =
121 sctx->ps_shader.cso ?
122 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
123 unsigned sx_ps_downconvert = 0;
124 unsigned sx_blend_opt_epsilon = 0;
125 unsigned sx_blend_opt_control = 0;
126
127 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
128 struct r600_surface *surf =
129 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf)
134 continue;
135
136 format = G_028C70_FORMAT(surf->cb_color_info);
137 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
138 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
139 colormask = (cb_target_mask >> (i * 4)) & 0xf;
140
141 /* Set if RGB and A are present. */
142 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
143
144 if (format == V_028C70_COLOR_8 ||
145 format == V_028C70_COLOR_16 ||
146 format == V_028C70_COLOR_32)
147 has_rgb = !has_alpha;
148 else
149 has_rgb = true;
150
151 /* Check the colormask and export format. */
152 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
153 has_rgb = false;
154 if (!(colormask & PIPE_MASK_A))
155 has_alpha = false;
156
157 if (spi_format == V_028714_SPI_SHADER_ZERO) {
158 has_rgb = false;
159 has_alpha = false;
160 }
161
162 /* Disable value checking for disabled channels. */
163 if (!has_rgb)
164 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
165 if (!has_alpha)
166 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
167
168 /* Enable down-conversion for 32bpp and smaller formats. */
169 switch (format) {
170 case V_028C70_COLOR_8:
171 case V_028C70_COLOR_8_8:
172 case V_028C70_COLOR_8_8_8_8:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
175 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_5_6_5:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_1_5_5_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_4_4_4_4:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_32:
204 if (swap == V_0280A0_SWAP_STD &&
205 spi_format == V_028714_SPI_SHADER_32_R)
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
207 else if (swap == V_0280A0_SWAP_ALT_REV &&
208 spi_format == V_028714_SPI_SHADER_32_AR)
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
210 break;
211
212 case V_028C70_COLOR_16:
213 case V_028C70_COLOR_16_16:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
216 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
219 if (swap == V_0280A0_SWAP_STD ||
220 swap == V_0280A0_SWAP_STD_REV)
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
222 else
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
224 }
225 break;
226
227 case V_028C70_COLOR_10_11_11:
228 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
230 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_2_10_10_10:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
238 }
239 break;
240 }
241 }
242
243 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
244 sx_ps_downconvert = 0;
245 sx_blend_opt_epsilon = 0;
246 sx_blend_opt_control = 0;
247 }
248
249 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 R600_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
383 *src_factor = PIPE_BLENDFACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == PIPE_BLEND_SUBTRACT)
388 *func = PIPE_BLEND_REVERSE_SUBTRACT;
389 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
390 *func = PIPE_BLEND_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
397 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
398 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
399 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
401 }
402
403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
404 const struct pipe_blend_state *state,
405 unsigned mode)
406 {
407 struct si_context *sctx = (struct si_context*)ctx;
408 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
409 struct si_pm4_state *pm4 = &blend->pm4;
410 uint32_t sx_mrt_blend_opt[8] = {0};
411 uint32_t color_control = 0;
412
413 if (!blend)
414 return NULL;
415
416 blend->alpha_to_coverage = state->alpha_to_coverage;
417 blend->alpha_to_one = state->alpha_to_one;
418 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
419
420 if (state->logicop_enable) {
421 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
422 } else {
423 color_control |= S_028808_ROP3(0xcc);
424 }
425
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
432
433 if (state->alpha_to_coverage)
434 blend->need_src_alpha_4bit |= 0xf;
435
436 blend->cb_target_mask = 0;
437 for (int i = 0; i < 8; i++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j = state->independent_blend_enable ? i : 0;
440
441 unsigned eqRGB = state->rt[j].rgb_func;
442 unsigned srcRGB = state->rt[j].rgb_src_factor;
443 unsigned dstRGB = state->rt[j].rgb_dst_factor;
444 unsigned eqA = state->rt[j].alpha_func;
445 unsigned srcA = state->rt[j].alpha_src_factor;
446 unsigned dstA = state->rt[j].alpha_dst_factor;
447
448 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
449 unsigned blend_cntl = 0;
450
451 sx_mrt_blend_opt[i] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
454
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i >= 1 && blend->dual_src_blend)
457 continue;
458
459 /* Only addition and subtraction equations are supported with
460 * dual source blending.
461 */
462 if (blend->dual_src_blend &&
463 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
464 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
465 assert(!"Unsupported equation for dual source blending");
466 continue;
467 }
468
469 if (!state->rt[j].colormask)
470 continue;
471
472 /* cb_render_state will disable unused ones */
473 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
474
475 if (!state->rt[j].blend_enable) {
476 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
477 continue;
478 }
479
480 /* Blending optimizations for Stoney.
481 * These transformations don't change the behavior.
482 *
483 * First, get rid of DST in the blend factors:
484 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
485 */
486 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
487 PIPE_BLENDFACTOR_DST_COLOR,
488 PIPE_BLENDFACTOR_SRC_COLOR);
489 si_blend_remove_dst(&eqA, &srcA, &dstA,
490 PIPE_BLENDFACTOR_DST_COLOR,
491 PIPE_BLENDFACTOR_SRC_COLOR);
492 si_blend_remove_dst(&eqA, &srcA, &dstA,
493 PIPE_BLENDFACTOR_DST_ALPHA,
494 PIPE_BLENDFACTOR_SRC_ALPHA);
495
496 /* Look up the ideal settings from tables. */
497 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
498 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
499 srcA_opt = si_translate_blend_opt_factor(srcA, true);
500 dstA_opt = si_translate_blend_opt_factor(dstA, true);
501
502 /* Handle interdependencies. */
503 if (si_blend_factor_uses_dst(srcRGB))
504 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
505 if (si_blend_factor_uses_dst(srcA))
506 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
507
508 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
509 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
510 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
511 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
512 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
513
514 /* Set the final value. */
515 sx_mrt_blend_opt[i] =
516 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
517 S_028760_COLOR_DST_OPT(dstRGB_opt) |
518 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
519 S_028760_ALPHA_SRC_OPT(srcA_opt) |
520 S_028760_ALPHA_DST_OPT(dstA_opt) |
521 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
522
523 /* Set blend state. */
524 blend_cntl |= S_028780_ENABLE(1);
525 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
526 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
527 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
528
529 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
530 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
531 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
532 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
533 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
534 }
535 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536
537 blend->blend_enable_4bit |= 0xfu << (i * 4);
538
539 /* This is only important for formats without alpha. */
540 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
541 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
542 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
543 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
544 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
545 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
546 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
547 }
548
549 if (blend->cb_target_mask) {
550 color_control |= S_028808_MODE(mode);
551 } else {
552 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
553 }
554
555 if (sctx->b.family == CHIP_STONEY) {
556 for (int i = 0; i < 8; i++)
557 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
558 sx_mrt_blend_opt[i]);
559
560 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
561 if (blend->dual_src_blend || state->logicop_enable ||
562 mode == V_028808_CB_RESOLVE)
563 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
564 }
565
566 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
567 return blend;
568 }
569
570 static void *si_create_blend_state(struct pipe_context *ctx,
571 const struct pipe_blend_state *state)
572 {
573 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
574 }
575
576 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
577 {
578 struct si_context *sctx = (struct si_context *)ctx;
579 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
580 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
581 sctx->do_update_shaders = true;
582 }
583
584 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
588 }
589
590 static void si_set_blend_color(struct pipe_context *ctx,
591 const struct pipe_blend_color *state)
592 {
593 struct si_context *sctx = (struct si_context *)ctx;
594
595 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
596 return;
597
598 sctx->blend_color.state = *state;
599 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
600 }
601
602 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
603 {
604 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
605
606 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
607 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
608 }
609
610 /*
611 * Clipping
612 */
613
614 static void si_set_clip_state(struct pipe_context *ctx,
615 const struct pipe_clip_state *state)
616 {
617 struct si_context *sctx = (struct si_context *)ctx;
618 struct pipe_constant_buffer cb;
619
620 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
621 return;
622
623 sctx->clip_state.state = *state;
624 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
625
626 cb.buffer = NULL;
627 cb.user_buffer = state->ucp;
628 cb.buffer_offset = 0;
629 cb.buffer_size = 4*4*8;
630 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
631 pipe_resource_reference(&cb.buffer, NULL);
632 }
633
634 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
635 {
636 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
637
638 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
639 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
640 }
641
642 #define SIX_BITS 0x3F
643
644 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
645 {
646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
647 struct si_shader *vs = si_get_vs_state(sctx);
648 struct tgsi_shader_info *info = si_get_vs_info(sctx);
649 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
650 unsigned window_space =
651 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
652 unsigned clipdist_mask =
653 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
654 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
655 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
656 unsigned total_mask;
657
658 if (vs->key.opt.hw_vs.clip_disable) {
659 assert(!info->culldist_writemask);
660 clipdist_mask = 0;
661 culldist_mask = 0;
662 }
663 total_mask = clipdist_mask | culldist_mask;
664
665 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
666 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
667 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
668 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
669 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
670 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
671 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
672 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
673 info->writes_edgeflag ||
674 info->writes_layer ||
675 info->writes_viewport_index) |
676 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
677 (rs->clip_plane_enable &
678 clipdist_mask) | (culldist_mask << 8));
679 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
680 rs->pa_cl_clip_cntl |
681 ucp_mask |
682 S_028810_CLIP_DISABLE(window_space));
683
684 /* reuse needs to be set off if we write oViewport */
685 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
686 S_028AB4_REUSE_OFF(info->writes_viewport_index));
687 }
688
689 /*
690 * inferred state between framebuffer and rasterizer
691 */
692 static void si_update_poly_offset_state(struct si_context *sctx)
693 {
694 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
695
696 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
697 return;
698
699 /* Use the user format, not db_render_format, so that the polygon
700 * offset behaves as expected by applications.
701 */
702 switch (sctx->framebuffer.state.zsbuf->texture->format) {
703 case PIPE_FORMAT_Z16_UNORM:
704 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
705 break;
706 default: /* 24-bit */
707 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
708 break;
709 case PIPE_FORMAT_Z32_FLOAT:
710 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
711 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
712 break;
713 }
714 }
715
716 /*
717 * Rasterizer
718 */
719
720 static uint32_t si_translate_fill(uint32_t func)
721 {
722 switch(func) {
723 case PIPE_POLYGON_MODE_FILL:
724 return V_028814_X_DRAW_TRIANGLES;
725 case PIPE_POLYGON_MODE_LINE:
726 return V_028814_X_DRAW_LINES;
727 case PIPE_POLYGON_MODE_POINT:
728 return V_028814_X_DRAW_POINTS;
729 default:
730 assert(0);
731 return V_028814_X_DRAW_POINTS;
732 }
733 }
734
735 static void *si_create_rs_state(struct pipe_context *ctx,
736 const struct pipe_rasterizer_state *state)
737 {
738 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
739 struct si_pm4_state *pm4 = &rs->pm4;
740 unsigned tmp, i;
741 float psize_min, psize_max;
742
743 if (!rs) {
744 return NULL;
745 }
746
747 rs->scissor_enable = state->scissor;
748 rs->clip_halfz = state->clip_halfz;
749 rs->two_side = state->light_twoside;
750 rs->multisample_enable = state->multisample;
751 rs->force_persample_interp = state->force_persample_interp;
752 rs->clip_plane_enable = state->clip_plane_enable;
753 rs->line_stipple_enable = state->line_stipple_enable;
754 rs->poly_stipple_enable = state->poly_stipple_enable;
755 rs->line_smooth = state->line_smooth;
756 rs->poly_smooth = state->poly_smooth;
757 rs->uses_poly_offset = state->offset_point || state->offset_line ||
758 state->offset_tri;
759 rs->clamp_fragment_color = state->clamp_fragment_color;
760 rs->flatshade = state->flatshade;
761 rs->sprite_coord_enable = state->sprite_coord_enable;
762 rs->rasterizer_discard = state->rasterizer_discard;
763 rs->pa_sc_line_stipple = state->line_stipple_enable ?
764 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
765 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
766 rs->pa_cl_clip_cntl =
767 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
768 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
769 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
770 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
771 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
772
773 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
774 S_0286D4_FLAT_SHADE_ENA(1) |
775 S_0286D4_PNT_SPRITE_ENA(1) |
776 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
777 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
778 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
779 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
780 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
781
782 /* point size 12.4 fixed point */
783 tmp = (unsigned)(state->point_size * 8.0);
784 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
785
786 if (state->point_size_per_vertex) {
787 psize_min = util_get_min_point_size(state);
788 psize_max = 8192;
789 } else {
790 /* Force the point size to be as if the vertex output was disabled. */
791 psize_min = state->point_size;
792 psize_max = state->point_size;
793 }
794 /* Divide by two, because 0.5 = 1 pixel. */
795 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
796 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
797 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
798
799 tmp = (unsigned)state->line_width * 8;
800 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
801 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
802 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
803 S_028A48_MSAA_ENABLE(state->multisample ||
804 state->poly_smooth ||
805 state->line_smooth) |
806 S_028A48_VPORT_SCISSOR_ENABLE(1));
807
808 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
809 S_028BE4_PIX_CENTER(state->half_pixel_center) |
810 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
811
812 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
813 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
814 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
815 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
816 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
817 S_028814_FACE(!state->front_ccw) |
818 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
819 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
820 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
821 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
822 state->fill_back != PIPE_POLYGON_MODE_FILL) |
823 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
824 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
825 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
826 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
827
828 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
829 for (i = 0; i < 3; i++) {
830 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
831 float offset_units = state->offset_units;
832 float offset_scale = state->offset_scale * 16.0f;
833 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
834
835 if (!state->offset_units_unscaled) {
836 switch (i) {
837 case 0: /* 16-bit zbuffer */
838 offset_units *= 4.0f;
839 pa_su_poly_offset_db_fmt_cntl =
840 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
841 break;
842 case 1: /* 24-bit zbuffer */
843 offset_units *= 2.0f;
844 pa_su_poly_offset_db_fmt_cntl =
845 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
846 break;
847 case 2: /* 32-bit zbuffer */
848 offset_units *= 1.0f;
849 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
850 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
851 break;
852 }
853 }
854
855 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
856 fui(offset_scale));
857 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
858 fui(offset_units));
859 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
860 fui(offset_scale));
861 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
862 fui(offset_units));
863 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
864 pa_su_poly_offset_db_fmt_cntl);
865 }
866
867 return rs;
868 }
869
870 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
871 {
872 struct si_context *sctx = (struct si_context *)ctx;
873 struct si_state_rasterizer *old_rs =
874 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
875 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
876
877 if (!state)
878 return;
879
880 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
881 si_mark_atom_dirty(sctx, &sctx->db_render_state);
882
883 /* Update the small primitive filter workaround if necessary. */
884 if (sctx->b.family >= CHIP_POLARIS10 &&
885 sctx->framebuffer.nr_samples > 1)
886 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
887 }
888
889 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
890
891 si_pm4_bind_state(sctx, rasterizer, rs);
892 si_update_poly_offset_state(sctx);
893
894 si_mark_atom_dirty(sctx, &sctx->clip_regs);
895 sctx->do_update_shaders = true;
896 }
897
898 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
899 {
900 struct si_context *sctx = (struct si_context *)ctx;
901
902 if (sctx->queued.named.rasterizer == state)
903 si_pm4_bind_state(sctx, poly_offset, NULL);
904 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
905 }
906
907 /*
908 * infeered state between dsa and stencil ref
909 */
910 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
911 {
912 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
913 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
914 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
915
916 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
917 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
918 S_028430_STENCILMASK(dsa->valuemask[0]) |
919 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
920 S_028430_STENCILOPVAL(1));
921 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
922 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
923 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
924 S_028434_STENCILOPVAL_BF(1));
925 }
926
927 static void si_set_stencil_ref(struct pipe_context *ctx,
928 const struct pipe_stencil_ref *state)
929 {
930 struct si_context *sctx = (struct si_context *)ctx;
931
932 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
933 return;
934
935 sctx->stencil_ref.state = *state;
936 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
937 }
938
939
940 /*
941 * DSA
942 */
943
944 static uint32_t si_translate_stencil_op(int s_op)
945 {
946 switch (s_op) {
947 case PIPE_STENCIL_OP_KEEP:
948 return V_02842C_STENCIL_KEEP;
949 case PIPE_STENCIL_OP_ZERO:
950 return V_02842C_STENCIL_ZERO;
951 case PIPE_STENCIL_OP_REPLACE:
952 return V_02842C_STENCIL_REPLACE_TEST;
953 case PIPE_STENCIL_OP_INCR:
954 return V_02842C_STENCIL_ADD_CLAMP;
955 case PIPE_STENCIL_OP_DECR:
956 return V_02842C_STENCIL_SUB_CLAMP;
957 case PIPE_STENCIL_OP_INCR_WRAP:
958 return V_02842C_STENCIL_ADD_WRAP;
959 case PIPE_STENCIL_OP_DECR_WRAP:
960 return V_02842C_STENCIL_SUB_WRAP;
961 case PIPE_STENCIL_OP_INVERT:
962 return V_02842C_STENCIL_INVERT;
963 default:
964 R600_ERR("Unknown stencil op %d", s_op);
965 assert(0);
966 break;
967 }
968 return 0;
969 }
970
971 static void *si_create_dsa_state(struct pipe_context *ctx,
972 const struct pipe_depth_stencil_alpha_state *state)
973 {
974 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
975 struct si_pm4_state *pm4 = &dsa->pm4;
976 unsigned db_depth_control;
977 uint32_t db_stencil_control = 0;
978
979 if (!dsa) {
980 return NULL;
981 }
982
983 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
984 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
985 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
986 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
987
988 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
989 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
990 S_028800_ZFUNC(state->depth.func) |
991 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
992
993 /* stencil */
994 if (state->stencil[0].enabled) {
995 db_depth_control |= S_028800_STENCIL_ENABLE(1);
996 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
997 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
998 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
999 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1000
1001 if (state->stencil[1].enabled) {
1002 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1003 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1004 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1005 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1006 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1007 }
1008 }
1009
1010 /* alpha */
1011 if (state->alpha.enabled) {
1012 dsa->alpha_func = state->alpha.func;
1013
1014 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1015 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1016 } else {
1017 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1018 }
1019
1020 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1021 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1022 if (state->depth.bounds_test) {
1023 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1024 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1025 }
1026
1027 return dsa;
1028 }
1029
1030 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1031 {
1032 struct si_context *sctx = (struct si_context *)ctx;
1033 struct si_state_dsa *dsa = state;
1034
1035 if (!state)
1036 return;
1037
1038 si_pm4_bind_state(sctx, dsa, dsa);
1039
1040 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1041 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1042 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1043 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1044 }
1045 sctx->do_update_shaders = true;
1046 }
1047
1048 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1049 {
1050 struct si_context *sctx = (struct si_context *)ctx;
1051 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1052 }
1053
1054 static void *si_create_db_flush_dsa(struct si_context *sctx)
1055 {
1056 struct pipe_depth_stencil_alpha_state dsa = {};
1057
1058 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1059 }
1060
1061 /* DB RENDER STATE */
1062
1063 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1064 {
1065 struct si_context *sctx = (struct si_context*)ctx;
1066
1067 /* Pipeline stat & streamout queries. */
1068 if (enable) {
1069 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1070 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1071 } else {
1072 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1073 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1074 }
1075
1076 /* Occlusion queries. */
1077 if (sctx->occlusion_queries_disabled != !enable) {
1078 sctx->occlusion_queries_disabled = !enable;
1079 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1080 }
1081 }
1082
1083 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1084 {
1085 struct si_context *sctx = (struct si_context*)ctx;
1086
1087 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1088 }
1089
1090 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1091 {
1092 struct si_context *sctx = (struct si_context*)ctx;
1093
1094 st->saved_compute = sctx->cs_shader_state.program;
1095
1096 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1097 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1098 }
1099
1100 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1101 {
1102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1103 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1104 unsigned db_shader_control;
1105
1106 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1107
1108 /* DB_RENDER_CONTROL */
1109 if (sctx->dbcb_depth_copy_enabled ||
1110 sctx->dbcb_stencil_copy_enabled) {
1111 radeon_emit(cs,
1112 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1113 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1114 S_028000_COPY_CENTROID(1) |
1115 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1116 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1117 radeon_emit(cs,
1118 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1119 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1120 } else {
1121 radeon_emit(cs,
1122 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1123 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1124 }
1125
1126 /* DB_COUNT_CONTROL (occlusion queries) */
1127 if (sctx->b.num_occlusion_queries > 0 &&
1128 !sctx->occlusion_queries_disabled) {
1129 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1130
1131 if (sctx->b.chip_class >= CIK) {
1132 radeon_emit(cs,
1133 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1134 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1135 S_028004_ZPASS_ENABLE(1) |
1136 S_028004_SLICE_EVEN_ENABLE(1) |
1137 S_028004_SLICE_ODD_ENABLE(1));
1138 } else {
1139 radeon_emit(cs,
1140 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1141 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1142 }
1143 } else {
1144 /* Disable occlusion queries. */
1145 if (sctx->b.chip_class >= CIK) {
1146 radeon_emit(cs, 0);
1147 } else {
1148 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1149 }
1150 }
1151
1152 /* DB_RENDER_OVERRIDE2 */
1153 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1154 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1155 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1156 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1157
1158 db_shader_control = sctx->ps_db_shader_control;
1159
1160 /* Bug workaround for smoothing (overrasterization) on SI. */
1161 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1162 db_shader_control &= C_02880C_Z_ORDER;
1163 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1164 }
1165
1166 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1167 if (!rs || !rs->multisample_enable)
1168 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1169
1170 if (sctx->b.family == CHIP_STONEY &&
1171 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1172 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1173
1174 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1175 db_shader_control);
1176 }
1177
1178 /*
1179 * format translation
1180 */
1181 static uint32_t si_translate_colorformat(enum pipe_format format)
1182 {
1183 const struct util_format_description *desc = util_format_description(format);
1184
1185 #define HAS_SIZE(x,y,z,w) \
1186 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1187 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1188
1189 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1190 return V_028C70_COLOR_10_11_11;
1191
1192 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1193 return V_028C70_COLOR_INVALID;
1194
1195 /* hw cannot support mixed formats (except depth/stencil, since
1196 * stencil is not written to). */
1197 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1198 return V_028C70_COLOR_INVALID;
1199
1200 switch (desc->nr_channels) {
1201 case 1:
1202 switch (desc->channel[0].size) {
1203 case 8:
1204 return V_028C70_COLOR_8;
1205 case 16:
1206 return V_028C70_COLOR_16;
1207 case 32:
1208 return V_028C70_COLOR_32;
1209 }
1210 break;
1211 case 2:
1212 if (desc->channel[0].size == desc->channel[1].size) {
1213 switch (desc->channel[0].size) {
1214 case 8:
1215 return V_028C70_COLOR_8_8;
1216 case 16:
1217 return V_028C70_COLOR_16_16;
1218 case 32:
1219 return V_028C70_COLOR_32_32;
1220 }
1221 } else if (HAS_SIZE(8,24,0,0)) {
1222 return V_028C70_COLOR_24_8;
1223 } else if (HAS_SIZE(24,8,0,0)) {
1224 return V_028C70_COLOR_8_24;
1225 }
1226 break;
1227 case 3:
1228 if (HAS_SIZE(5,6,5,0)) {
1229 return V_028C70_COLOR_5_6_5;
1230 } else if (HAS_SIZE(32,8,24,0)) {
1231 return V_028C70_COLOR_X24_8_32_FLOAT;
1232 }
1233 break;
1234 case 4:
1235 if (desc->channel[0].size == desc->channel[1].size &&
1236 desc->channel[0].size == desc->channel[2].size &&
1237 desc->channel[0].size == desc->channel[3].size) {
1238 switch (desc->channel[0].size) {
1239 case 4:
1240 return V_028C70_COLOR_4_4_4_4;
1241 case 8:
1242 return V_028C70_COLOR_8_8_8_8;
1243 case 16:
1244 return V_028C70_COLOR_16_16_16_16;
1245 case 32:
1246 return V_028C70_COLOR_32_32_32_32;
1247 }
1248 } else if (HAS_SIZE(5,5,5,1)) {
1249 return V_028C70_COLOR_1_5_5_5;
1250 } else if (HAS_SIZE(10,10,10,2)) {
1251 return V_028C70_COLOR_2_10_10_10;
1252 }
1253 break;
1254 }
1255 return V_028C70_COLOR_INVALID;
1256 }
1257
1258 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1259 {
1260 if (SI_BIG_ENDIAN) {
1261 switch(colorformat) {
1262 /* 8-bit buffers. */
1263 case V_028C70_COLOR_8:
1264 return V_028C70_ENDIAN_NONE;
1265
1266 /* 16-bit buffers. */
1267 case V_028C70_COLOR_5_6_5:
1268 case V_028C70_COLOR_1_5_5_5:
1269 case V_028C70_COLOR_4_4_4_4:
1270 case V_028C70_COLOR_16:
1271 case V_028C70_COLOR_8_8:
1272 return V_028C70_ENDIAN_8IN16;
1273
1274 /* 32-bit buffers. */
1275 case V_028C70_COLOR_8_8_8_8:
1276 case V_028C70_COLOR_2_10_10_10:
1277 case V_028C70_COLOR_8_24:
1278 case V_028C70_COLOR_24_8:
1279 case V_028C70_COLOR_16_16:
1280 return V_028C70_ENDIAN_8IN32;
1281
1282 /* 64-bit buffers. */
1283 case V_028C70_COLOR_16_16_16_16:
1284 return V_028C70_ENDIAN_8IN16;
1285
1286 case V_028C70_COLOR_32_32:
1287 return V_028C70_ENDIAN_8IN32;
1288
1289 /* 128-bit buffers. */
1290 case V_028C70_COLOR_32_32_32_32:
1291 return V_028C70_ENDIAN_8IN32;
1292 default:
1293 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1294 }
1295 } else {
1296 return V_028C70_ENDIAN_NONE;
1297 }
1298 }
1299
1300 static uint32_t si_translate_dbformat(enum pipe_format format)
1301 {
1302 switch (format) {
1303 case PIPE_FORMAT_Z16_UNORM:
1304 return V_028040_Z_16;
1305 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1306 case PIPE_FORMAT_X8Z24_UNORM:
1307 case PIPE_FORMAT_Z24X8_UNORM:
1308 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1309 return V_028040_Z_24; /* deprecated on SI */
1310 case PIPE_FORMAT_Z32_FLOAT:
1311 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1312 return V_028040_Z_32_FLOAT;
1313 default:
1314 return V_028040_Z_INVALID;
1315 }
1316 }
1317
1318 /*
1319 * Texture translation
1320 */
1321
1322 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1323 enum pipe_format format,
1324 const struct util_format_description *desc,
1325 int first_non_void)
1326 {
1327 struct si_screen *sscreen = (struct si_screen*)screen;
1328 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1329 sscreen->b.info.drm_minor >= 31) ||
1330 sscreen->b.info.drm_major == 3;
1331 bool uniform = true;
1332 int i;
1333
1334 /* Colorspace (return non-RGB formats directly). */
1335 switch (desc->colorspace) {
1336 /* Depth stencil formats */
1337 case UTIL_FORMAT_COLORSPACE_ZS:
1338 switch (format) {
1339 case PIPE_FORMAT_Z16_UNORM:
1340 return V_008F14_IMG_DATA_FORMAT_16;
1341 case PIPE_FORMAT_X24S8_UINT:
1342 case PIPE_FORMAT_Z24X8_UNORM:
1343 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1344 return V_008F14_IMG_DATA_FORMAT_8_24;
1345 case PIPE_FORMAT_X8Z24_UNORM:
1346 case PIPE_FORMAT_S8X24_UINT:
1347 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1348 return V_008F14_IMG_DATA_FORMAT_24_8;
1349 case PIPE_FORMAT_S8_UINT:
1350 return V_008F14_IMG_DATA_FORMAT_8;
1351 case PIPE_FORMAT_Z32_FLOAT:
1352 return V_008F14_IMG_DATA_FORMAT_32;
1353 case PIPE_FORMAT_X32_S8X24_UINT:
1354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1355 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1356 default:
1357 goto out_unknown;
1358 }
1359
1360 case UTIL_FORMAT_COLORSPACE_YUV:
1361 goto out_unknown; /* TODO */
1362
1363 case UTIL_FORMAT_COLORSPACE_SRGB:
1364 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1365 goto out_unknown;
1366 break;
1367
1368 default:
1369 break;
1370 }
1371
1372 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1373 if (!enable_compressed_formats)
1374 goto out_unknown;
1375
1376 switch (format) {
1377 case PIPE_FORMAT_RGTC1_SNORM:
1378 case PIPE_FORMAT_LATC1_SNORM:
1379 case PIPE_FORMAT_RGTC1_UNORM:
1380 case PIPE_FORMAT_LATC1_UNORM:
1381 return V_008F14_IMG_DATA_FORMAT_BC4;
1382 case PIPE_FORMAT_RGTC2_SNORM:
1383 case PIPE_FORMAT_LATC2_SNORM:
1384 case PIPE_FORMAT_RGTC2_UNORM:
1385 case PIPE_FORMAT_LATC2_UNORM:
1386 return V_008F14_IMG_DATA_FORMAT_BC5;
1387 default:
1388 goto out_unknown;
1389 }
1390 }
1391
1392 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1393 sscreen->b.family == CHIP_STONEY) {
1394 switch (format) {
1395 case PIPE_FORMAT_ETC1_RGB8:
1396 case PIPE_FORMAT_ETC2_RGB8:
1397 case PIPE_FORMAT_ETC2_SRGB8:
1398 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1399 case PIPE_FORMAT_ETC2_RGB8A1:
1400 case PIPE_FORMAT_ETC2_SRGB8A1:
1401 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1402 case PIPE_FORMAT_ETC2_RGBA8:
1403 case PIPE_FORMAT_ETC2_SRGBA8:
1404 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1405 case PIPE_FORMAT_ETC2_R11_UNORM:
1406 case PIPE_FORMAT_ETC2_R11_SNORM:
1407 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1408 case PIPE_FORMAT_ETC2_RG11_UNORM:
1409 case PIPE_FORMAT_ETC2_RG11_SNORM:
1410 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1411 default:
1412 goto out_unknown;
1413 }
1414 }
1415
1416 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1417 if (!enable_compressed_formats)
1418 goto out_unknown;
1419
1420 switch (format) {
1421 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1422 case PIPE_FORMAT_BPTC_SRGBA:
1423 return V_008F14_IMG_DATA_FORMAT_BC7;
1424 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1425 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1426 return V_008F14_IMG_DATA_FORMAT_BC6;
1427 default:
1428 goto out_unknown;
1429 }
1430 }
1431
1432 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1433 switch (format) {
1434 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1435 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1436 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1437 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1438 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1439 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1440 default:
1441 goto out_unknown;
1442 }
1443 }
1444
1445 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1446 if (!enable_compressed_formats)
1447 goto out_unknown;
1448
1449 if (!util_format_s3tc_enabled) {
1450 goto out_unknown;
1451 }
1452
1453 switch (format) {
1454 case PIPE_FORMAT_DXT1_RGB:
1455 case PIPE_FORMAT_DXT1_RGBA:
1456 case PIPE_FORMAT_DXT1_SRGB:
1457 case PIPE_FORMAT_DXT1_SRGBA:
1458 return V_008F14_IMG_DATA_FORMAT_BC1;
1459 case PIPE_FORMAT_DXT3_RGBA:
1460 case PIPE_FORMAT_DXT3_SRGBA:
1461 return V_008F14_IMG_DATA_FORMAT_BC2;
1462 case PIPE_FORMAT_DXT5_RGBA:
1463 case PIPE_FORMAT_DXT5_SRGBA:
1464 return V_008F14_IMG_DATA_FORMAT_BC3;
1465 default:
1466 goto out_unknown;
1467 }
1468 }
1469
1470 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1471 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1472 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1473 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1474 }
1475
1476 /* R8G8Bx_SNORM - TODO CxV8U8 */
1477
1478 /* hw cannot support mixed formats (except depth/stencil, since only
1479 * depth is read).*/
1480 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1481 goto out_unknown;
1482
1483 /* See whether the components are of the same size. */
1484 for (i = 1; i < desc->nr_channels; i++) {
1485 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1486 }
1487
1488 /* Non-uniform formats. */
1489 if (!uniform) {
1490 switch(desc->nr_channels) {
1491 case 3:
1492 if (desc->channel[0].size == 5 &&
1493 desc->channel[1].size == 6 &&
1494 desc->channel[2].size == 5) {
1495 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1496 }
1497 goto out_unknown;
1498 case 4:
1499 if (desc->channel[0].size == 5 &&
1500 desc->channel[1].size == 5 &&
1501 desc->channel[2].size == 5 &&
1502 desc->channel[3].size == 1) {
1503 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1504 }
1505 if (desc->channel[0].size == 10 &&
1506 desc->channel[1].size == 10 &&
1507 desc->channel[2].size == 10 &&
1508 desc->channel[3].size == 2) {
1509 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1510 }
1511 goto out_unknown;
1512 }
1513 goto out_unknown;
1514 }
1515
1516 if (first_non_void < 0 || first_non_void > 3)
1517 goto out_unknown;
1518
1519 /* uniform formats */
1520 switch (desc->channel[first_non_void].size) {
1521 case 4:
1522 switch (desc->nr_channels) {
1523 #if 0 /* Not supported for render targets */
1524 case 2:
1525 return V_008F14_IMG_DATA_FORMAT_4_4;
1526 #endif
1527 case 4:
1528 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1529 }
1530 break;
1531 case 8:
1532 switch (desc->nr_channels) {
1533 case 1:
1534 return V_008F14_IMG_DATA_FORMAT_8;
1535 case 2:
1536 return V_008F14_IMG_DATA_FORMAT_8_8;
1537 case 4:
1538 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1539 }
1540 break;
1541 case 16:
1542 switch (desc->nr_channels) {
1543 case 1:
1544 return V_008F14_IMG_DATA_FORMAT_16;
1545 case 2:
1546 return V_008F14_IMG_DATA_FORMAT_16_16;
1547 case 4:
1548 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1549 }
1550 break;
1551 case 32:
1552 switch (desc->nr_channels) {
1553 case 1:
1554 return V_008F14_IMG_DATA_FORMAT_32;
1555 case 2:
1556 return V_008F14_IMG_DATA_FORMAT_32_32;
1557 #if 0 /* Not supported for render targets */
1558 case 3:
1559 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1560 #endif
1561 case 4:
1562 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1563 }
1564 }
1565
1566 out_unknown:
1567 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1568 return ~0;
1569 }
1570
1571 static unsigned si_tex_wrap(unsigned wrap)
1572 {
1573 switch (wrap) {
1574 default:
1575 case PIPE_TEX_WRAP_REPEAT:
1576 return V_008F30_SQ_TEX_WRAP;
1577 case PIPE_TEX_WRAP_CLAMP:
1578 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1579 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1580 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1581 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1582 return V_008F30_SQ_TEX_CLAMP_BORDER;
1583 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1584 return V_008F30_SQ_TEX_MIRROR;
1585 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1586 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1587 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1588 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1589 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1590 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1591 }
1592 }
1593
1594 static unsigned si_tex_mipfilter(unsigned filter)
1595 {
1596 switch (filter) {
1597 case PIPE_TEX_MIPFILTER_NEAREST:
1598 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1599 case PIPE_TEX_MIPFILTER_LINEAR:
1600 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1601 default:
1602 case PIPE_TEX_MIPFILTER_NONE:
1603 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1604 }
1605 }
1606
1607 static unsigned si_tex_compare(unsigned compare)
1608 {
1609 switch (compare) {
1610 default:
1611 case PIPE_FUNC_NEVER:
1612 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1613 case PIPE_FUNC_LESS:
1614 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1615 case PIPE_FUNC_EQUAL:
1616 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1617 case PIPE_FUNC_LEQUAL:
1618 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1619 case PIPE_FUNC_GREATER:
1620 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1621 case PIPE_FUNC_NOTEQUAL:
1622 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1623 case PIPE_FUNC_GEQUAL:
1624 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1625 case PIPE_FUNC_ALWAYS:
1626 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1627 }
1628 }
1629
1630 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1631 unsigned nr_samples)
1632 {
1633 if (view_target == PIPE_TEXTURE_CUBE ||
1634 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1635 res_target = view_target;
1636 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1637 else if (res_target == PIPE_TEXTURE_CUBE ||
1638 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1639 res_target = PIPE_TEXTURE_2D_ARRAY;
1640
1641 switch (res_target) {
1642 default:
1643 case PIPE_TEXTURE_1D:
1644 return V_008F1C_SQ_RSRC_IMG_1D;
1645 case PIPE_TEXTURE_1D_ARRAY:
1646 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1647 case PIPE_TEXTURE_2D:
1648 case PIPE_TEXTURE_RECT:
1649 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1650 V_008F1C_SQ_RSRC_IMG_2D;
1651 case PIPE_TEXTURE_2D_ARRAY:
1652 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1653 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1654 case PIPE_TEXTURE_3D:
1655 return V_008F1C_SQ_RSRC_IMG_3D;
1656 case PIPE_TEXTURE_CUBE:
1657 case PIPE_TEXTURE_CUBE_ARRAY:
1658 return V_008F1C_SQ_RSRC_IMG_CUBE;
1659 }
1660 }
1661
1662 /*
1663 * Format support testing
1664 */
1665
1666 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1667 {
1668 return si_translate_texformat(screen, format, util_format_description(format),
1669 util_format_get_first_non_void_channel(format)) != ~0U;
1670 }
1671
1672 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1673 const struct util_format_description *desc,
1674 int first_non_void)
1675 {
1676 unsigned type;
1677 int i;
1678
1679 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1680 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1681
1682 assert(first_non_void >= 0);
1683 type = desc->channel[first_non_void].type;
1684
1685 if (type == UTIL_FORMAT_TYPE_FIXED)
1686 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1687
1688 if (desc->nr_channels == 4 &&
1689 desc->channel[0].size == 10 &&
1690 desc->channel[1].size == 10 &&
1691 desc->channel[2].size == 10 &&
1692 desc->channel[3].size == 2)
1693 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1694
1695 /* See whether the components are of the same size. */
1696 for (i = 0; i < desc->nr_channels; i++) {
1697 if (desc->channel[first_non_void].size != desc->channel[i].size)
1698 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1699 }
1700
1701 switch (desc->channel[first_non_void].size) {
1702 case 8:
1703 switch (desc->nr_channels) {
1704 case 1:
1705 return V_008F0C_BUF_DATA_FORMAT_8;
1706 case 2:
1707 return V_008F0C_BUF_DATA_FORMAT_8_8;
1708 case 3:
1709 case 4:
1710 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1711 }
1712 break;
1713 case 16:
1714 switch (desc->nr_channels) {
1715 case 1:
1716 return V_008F0C_BUF_DATA_FORMAT_16;
1717 case 2:
1718 return V_008F0C_BUF_DATA_FORMAT_16_16;
1719 case 3:
1720 case 4:
1721 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1722 }
1723 break;
1724 case 32:
1725 /* From the Southern Islands ISA documentation about MTBUF:
1726 * 'Memory reads of data in memory that is 32 or 64 bits do not
1727 * undergo any format conversion.'
1728 */
1729 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1730 !desc->channel[first_non_void].pure_integer)
1731 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1732
1733 switch (desc->nr_channels) {
1734 case 1:
1735 return V_008F0C_BUF_DATA_FORMAT_32;
1736 case 2:
1737 return V_008F0C_BUF_DATA_FORMAT_32_32;
1738 case 3:
1739 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1740 case 4:
1741 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1742 }
1743 break;
1744 }
1745
1746 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1747 }
1748
1749 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1750 const struct util_format_description *desc,
1751 int first_non_void)
1752 {
1753 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1754 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1755
1756 assert(first_non_void >= 0);
1757
1758 switch (desc->channel[first_non_void].type) {
1759 case UTIL_FORMAT_TYPE_SIGNED:
1760 if (desc->channel[first_non_void].normalized)
1761 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1762 else if (desc->channel[first_non_void].pure_integer)
1763 return V_008F0C_BUF_NUM_FORMAT_SINT;
1764 else
1765 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1766 break;
1767 case UTIL_FORMAT_TYPE_UNSIGNED:
1768 if (desc->channel[first_non_void].normalized)
1769 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1770 else if (desc->channel[first_non_void].pure_integer)
1771 return V_008F0C_BUF_NUM_FORMAT_UINT;
1772 else
1773 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1774 break;
1775 case UTIL_FORMAT_TYPE_FLOAT:
1776 default:
1777 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1778 }
1779 }
1780
1781 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1782 enum pipe_format format,
1783 unsigned usage)
1784 {
1785 const struct util_format_description *desc;
1786 int first_non_void;
1787 unsigned data_format;
1788
1789 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1790 PIPE_BIND_SAMPLER_VIEW |
1791 PIPE_BIND_VERTEX_BUFFER)) == 0);
1792
1793 desc = util_format_description(format);
1794
1795 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1796 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1797 * for read-only access (with caveats surrounding bounds checks), but
1798 * obviously fails for write access which we have to implement for
1799 * shader images. Luckily, OpenGL doesn't expect this to be supported
1800 * anyway, and so the only impact is on PBO uploads / downloads, which
1801 * shouldn't be expected to be fast for GL_RGB anyway.
1802 */
1803 if (desc->block.bits == 3 * 8 ||
1804 desc->block.bits == 3 * 16) {
1805 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1806 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1807 if (!usage)
1808 return 0;
1809 }
1810 }
1811
1812 first_non_void = util_format_get_first_non_void_channel(format);
1813 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1814 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1815 return 0;
1816
1817 return usage;
1818 }
1819
1820 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1821 {
1822 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1823 r600_translate_colorswap(format, false) != ~0U;
1824 }
1825
1826 static bool si_is_zs_format_supported(enum pipe_format format)
1827 {
1828 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1829 }
1830
1831 static boolean si_is_format_supported(struct pipe_screen *screen,
1832 enum pipe_format format,
1833 enum pipe_texture_target target,
1834 unsigned sample_count,
1835 unsigned usage)
1836 {
1837 unsigned retval = 0;
1838
1839 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1840 R600_ERR("r600: unsupported texture type %d\n", target);
1841 return false;
1842 }
1843
1844 if (!util_format_is_supported(format, usage))
1845 return false;
1846
1847 if (sample_count > 1) {
1848 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1849 return false;
1850
1851 if (usage & PIPE_BIND_SHADER_IMAGE)
1852 return false;
1853
1854 switch (sample_count) {
1855 case 2:
1856 case 4:
1857 case 8:
1858 break;
1859 case 16:
1860 if (format == PIPE_FORMAT_NONE)
1861 return true;
1862 else
1863 return false;
1864 default:
1865 return false;
1866 }
1867 }
1868
1869 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1870 PIPE_BIND_SHADER_IMAGE)) {
1871 if (target == PIPE_BUFFER) {
1872 retval |= si_is_vertex_format_supported(
1873 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1874 PIPE_BIND_SHADER_IMAGE));
1875 } else {
1876 if (si_is_sampler_format_supported(screen, format))
1877 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1878 PIPE_BIND_SHADER_IMAGE);
1879 }
1880 }
1881
1882 if ((usage & (PIPE_BIND_RENDER_TARGET |
1883 PIPE_BIND_DISPLAY_TARGET |
1884 PIPE_BIND_SCANOUT |
1885 PIPE_BIND_SHARED |
1886 PIPE_BIND_BLENDABLE)) &&
1887 si_is_colorbuffer_format_supported(format)) {
1888 retval |= usage &
1889 (PIPE_BIND_RENDER_TARGET |
1890 PIPE_BIND_DISPLAY_TARGET |
1891 PIPE_BIND_SCANOUT |
1892 PIPE_BIND_SHARED);
1893 if (!util_format_is_pure_integer(format) &&
1894 !util_format_is_depth_or_stencil(format))
1895 retval |= usage & PIPE_BIND_BLENDABLE;
1896 }
1897
1898 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1899 si_is_zs_format_supported(format)) {
1900 retval |= PIPE_BIND_DEPTH_STENCIL;
1901 }
1902
1903 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1904 retval |= si_is_vertex_format_supported(screen, format,
1905 PIPE_BIND_VERTEX_BUFFER);
1906 }
1907
1908 if ((usage & PIPE_BIND_LINEAR) &&
1909 !util_format_is_compressed(format) &&
1910 !(usage & PIPE_BIND_DEPTH_STENCIL))
1911 retval |= PIPE_BIND_LINEAR;
1912
1913 return retval == usage;
1914 }
1915
1916 /*
1917 * framebuffer handling
1918 */
1919
1920 static void si_choose_spi_color_formats(struct r600_surface *surf,
1921 unsigned format, unsigned swap,
1922 unsigned ntype, bool is_depth)
1923 {
1924 /* Alpha is needed for alpha-to-coverage.
1925 * Blending may be with or without alpha.
1926 */
1927 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1928 unsigned alpha = 0; /* exports alpha, but may not support blending */
1929 unsigned blend = 0; /* supports blending, but may not export alpha */
1930 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1931
1932 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1933 * Other chips have multiple choices, though they are not necessarily better.
1934 */
1935 switch (format) {
1936 case V_028C70_COLOR_5_6_5:
1937 case V_028C70_COLOR_1_5_5_5:
1938 case V_028C70_COLOR_5_5_5_1:
1939 case V_028C70_COLOR_4_4_4_4:
1940 case V_028C70_COLOR_10_11_11:
1941 case V_028C70_COLOR_11_11_10:
1942 case V_028C70_COLOR_8:
1943 case V_028C70_COLOR_8_8:
1944 case V_028C70_COLOR_8_8_8_8:
1945 case V_028C70_COLOR_10_10_10_2:
1946 case V_028C70_COLOR_2_10_10_10:
1947 if (ntype == V_028C70_NUMBER_UINT)
1948 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1949 else if (ntype == V_028C70_NUMBER_SINT)
1950 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1951 else
1952 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1953 break;
1954
1955 case V_028C70_COLOR_16:
1956 case V_028C70_COLOR_16_16:
1957 case V_028C70_COLOR_16_16_16_16:
1958 if (ntype == V_028C70_NUMBER_UNORM ||
1959 ntype == V_028C70_NUMBER_SNORM) {
1960 /* UNORM16 and SNORM16 don't support blending */
1961 if (ntype == V_028C70_NUMBER_UNORM)
1962 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1963 else
1964 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1965
1966 /* Use 32 bits per channel for blending. */
1967 if (format == V_028C70_COLOR_16) {
1968 if (swap == V_028C70_SWAP_STD) { /* R */
1969 blend = V_028714_SPI_SHADER_32_R;
1970 blend_alpha = V_028714_SPI_SHADER_32_AR;
1971 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1972 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1973 else
1974 assert(0);
1975 } else if (format == V_028C70_COLOR_16_16) {
1976 if (swap == V_028C70_SWAP_STD) { /* RG */
1977 blend = V_028714_SPI_SHADER_32_GR;
1978 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1979 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1980 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1981 else
1982 assert(0);
1983 } else /* 16_16_16_16 */
1984 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1985 } else if (ntype == V_028C70_NUMBER_UINT)
1986 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1987 else if (ntype == V_028C70_NUMBER_SINT)
1988 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1989 else if (ntype == V_028C70_NUMBER_FLOAT)
1990 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1991 else
1992 assert(0);
1993 break;
1994
1995 case V_028C70_COLOR_32:
1996 if (swap == V_028C70_SWAP_STD) { /* R */
1997 blend = normal = V_028714_SPI_SHADER_32_R;
1998 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1999 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2000 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2001 else
2002 assert(0);
2003 break;
2004
2005 case V_028C70_COLOR_32_32:
2006 if (swap == V_028C70_SWAP_STD) { /* RG */
2007 blend = normal = V_028714_SPI_SHADER_32_GR;
2008 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2009 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2010 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2011 else
2012 assert(0);
2013 break;
2014
2015 case V_028C70_COLOR_32_32_32_32:
2016 case V_028C70_COLOR_8_24:
2017 case V_028C70_COLOR_24_8:
2018 case V_028C70_COLOR_X24_8_32_FLOAT:
2019 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2020 break;
2021
2022 default:
2023 assert(0);
2024 return;
2025 }
2026
2027 /* The DB->CB copy needs 32_ABGR. */
2028 if (is_depth)
2029 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2030
2031 surf->spi_shader_col_format = normal;
2032 surf->spi_shader_col_format_alpha = alpha;
2033 surf->spi_shader_col_format_blend = blend;
2034 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2035 }
2036
2037 static void si_initialize_color_surface(struct si_context *sctx,
2038 struct r600_surface *surf)
2039 {
2040 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2041 unsigned color_info, color_attrib, color_view;
2042 unsigned format, swap, ntype, endian;
2043 const struct util_format_description *desc;
2044 int i;
2045 unsigned blend_clamp = 0, blend_bypass = 0;
2046
2047 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2048 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2049
2050 desc = util_format_description(surf->base.format);
2051 for (i = 0; i < 4; i++) {
2052 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2053 break;
2054 }
2055 }
2056 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2057 ntype = V_028C70_NUMBER_FLOAT;
2058 } else {
2059 ntype = V_028C70_NUMBER_UNORM;
2060 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2061 ntype = V_028C70_NUMBER_SRGB;
2062 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2063 if (desc->channel[i].pure_integer) {
2064 ntype = V_028C70_NUMBER_SINT;
2065 } else {
2066 assert(desc->channel[i].normalized);
2067 ntype = V_028C70_NUMBER_SNORM;
2068 }
2069 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2070 if (desc->channel[i].pure_integer) {
2071 ntype = V_028C70_NUMBER_UINT;
2072 } else {
2073 assert(desc->channel[i].normalized);
2074 ntype = V_028C70_NUMBER_UNORM;
2075 }
2076 }
2077 }
2078
2079 format = si_translate_colorformat(surf->base.format);
2080 if (format == V_028C70_COLOR_INVALID) {
2081 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2082 }
2083 assert(format != V_028C70_COLOR_INVALID);
2084 swap = r600_translate_colorswap(surf->base.format, false);
2085 endian = si_colorformat_endian_swap(format);
2086
2087 /* blend clamp should be set for all NORM/SRGB types */
2088 if (ntype == V_028C70_NUMBER_UNORM ||
2089 ntype == V_028C70_NUMBER_SNORM ||
2090 ntype == V_028C70_NUMBER_SRGB)
2091 blend_clamp = 1;
2092
2093 /* set blend bypass according to docs if SINT/UINT or
2094 8/24 COLOR variants */
2095 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2096 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2097 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2098 blend_clamp = 0;
2099 blend_bypass = 1;
2100 }
2101
2102 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2103 (format == V_028C70_COLOR_8 ||
2104 format == V_028C70_COLOR_8_8 ||
2105 format == V_028C70_COLOR_8_8_8_8))
2106 surf->color_is_int8 = true;
2107
2108 color_info = S_028C70_FORMAT(format) |
2109 S_028C70_COMP_SWAP(swap) |
2110 S_028C70_BLEND_CLAMP(blend_clamp) |
2111 S_028C70_BLEND_BYPASS(blend_bypass) |
2112 S_028C70_SIMPLE_FLOAT(1) |
2113 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2114 ntype != V_028C70_NUMBER_SNORM &&
2115 ntype != V_028C70_NUMBER_SRGB &&
2116 format != V_028C70_COLOR_8_24 &&
2117 format != V_028C70_COLOR_24_8) |
2118 S_028C70_NUMBER_TYPE(ntype) |
2119 S_028C70_ENDIAN(endian);
2120
2121 /* Intensity is implemented as Red, so treat it that way. */
2122 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2123 util_format_is_intensity(surf->base.format));
2124
2125 if (rtex->resource.b.b.nr_samples > 1) {
2126 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2127
2128 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2129 S_028C74_NUM_FRAGMENTS(log_samples);
2130
2131 if (rtex->fmask.size) {
2132 color_info |= S_028C70_COMPRESSION(1);
2133 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2134
2135 if (sctx->b.chip_class == SI) {
2136 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2137 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2138 }
2139 }
2140 }
2141
2142 surf->cb_color_view = color_view;
2143 surf->cb_color_info = color_info;
2144 surf->cb_color_attrib = color_attrib;
2145
2146 if (sctx->b.chip_class >= VI) {
2147 unsigned max_uncompressed_block_size = 2;
2148
2149 if (rtex->resource.b.b.nr_samples > 1) {
2150 if (rtex->surface.bpe == 1)
2151 max_uncompressed_block_size = 0;
2152 else if (rtex->surface.bpe == 2)
2153 max_uncompressed_block_size = 1;
2154 }
2155
2156 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2157 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2158 }
2159
2160 /* This must be set for fast clear to work without FMASK. */
2161 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2162 unsigned bankh = util_logbase2(rtex->surface.bankh);
2163 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2164 }
2165
2166 /* Determine pixel shader export format */
2167 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2168
2169 surf->color_initialized = true;
2170 }
2171
2172 static void si_init_depth_surface(struct si_context *sctx,
2173 struct r600_surface *surf)
2174 {
2175 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2176 unsigned level = surf->base.u.tex.level;
2177 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2178 unsigned format;
2179 uint32_t z_info, s_info, db_depth_info;
2180 uint64_t z_offs, s_offs;
2181 uint32_t db_htile_data_base, db_htile_surface;
2182
2183 format = si_translate_dbformat(rtex->db_render_format);
2184
2185 if (format == V_028040_Z_INVALID) {
2186 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2187 }
2188 assert(format != V_028040_Z_INVALID);
2189
2190 s_offs = z_offs = rtex->resource.gpu_address;
2191 z_offs += rtex->surface.level[level].offset;
2192 s_offs += rtex->surface.stencil_level[level].offset;
2193
2194 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2195
2196 z_info = S_028040_FORMAT(format);
2197 if (rtex->resource.b.b.nr_samples > 1) {
2198 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2199 }
2200
2201 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2202 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2203 else
2204 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2205
2206 if (sctx->b.chip_class >= CIK) {
2207 struct radeon_info *info = &sctx->screen->b.info;
2208 unsigned index = rtex->surface.tiling_index[level];
2209 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2210 unsigned macro_index = rtex->surface.macro_tile_index;
2211 unsigned tile_mode = info->si_tile_mode_array[index];
2212 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2213 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2214
2215 db_depth_info |=
2216 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2217 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2218 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2219 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2220 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2221 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2222 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2223 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2224 } else {
2225 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2226 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2227 tile_mode_index = si_tile_mode_index(rtex, level, true);
2228 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2229 }
2230
2231 /* HiZ aka depth buffer htile */
2232 /* use htile only for first level */
2233 if (rtex->htile_buffer && !level) {
2234 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2235 S_028040_ALLOW_EXPCLEAR(1);
2236
2237 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2238 /* Workaround: For a not yet understood reason, the
2239 * combination of MSAA, fast stencil clear and stencil
2240 * decompress messes with subsequent stencil buffer
2241 * uses. Problem was reproduced on Verde, Bonaire,
2242 * Tonga, and Carrizo.
2243 *
2244 * Disabling EXPCLEAR works around the problem.
2245 *
2246 * Check piglit's arb_texture_multisample-stencil-clear
2247 * test if you want to try changing this.
2248 */
2249 if (rtex->resource.b.b.nr_samples <= 1)
2250 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2251 } else if (!rtex->tc_compatible_htile) {
2252 /* Use all of the htile_buffer for depth if there's no stencil.
2253 * This must not be set when TC-compatible HTILE is enabled
2254 * due to a hw bug.
2255 */
2256 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2257 }
2258
2259 uint64_t va = rtex->htile_buffer->gpu_address;
2260 db_htile_data_base = va >> 8;
2261 db_htile_surface = S_028ABC_FULL_CACHE(1);
2262
2263 if (rtex->tc_compatible_htile) {
2264 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2265
2266 switch (rtex->resource.b.b.nr_samples) {
2267 case 0:
2268 case 1:
2269 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2270 break;
2271 case 2:
2272 case 4:
2273 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2274 break;
2275 case 8:
2276 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2277 break;
2278 default:
2279 assert(0);
2280 }
2281 }
2282 } else {
2283 db_htile_data_base = 0;
2284 db_htile_surface = 0;
2285 }
2286
2287 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2288
2289 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2290 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2291 surf->db_htile_data_base = db_htile_data_base;
2292 surf->db_depth_info = db_depth_info;
2293 surf->db_z_info = z_info;
2294 surf->db_stencil_info = s_info;
2295 surf->db_depth_base = z_offs >> 8;
2296 surf->db_stencil_base = s_offs >> 8;
2297 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2298 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2299 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2300 levelinfo->nblk_y) / 64 - 1);
2301 surf->db_htile_surface = db_htile_surface;
2302
2303 surf->depth_initialized = true;
2304 }
2305
2306 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2307 {
2308 for (int i = 0; i < state->nr_cbufs; ++i) {
2309 struct r600_surface *surf = NULL;
2310 struct r600_texture *rtex;
2311
2312 if (!state->cbufs[i])
2313 continue;
2314 surf = (struct r600_surface*)state->cbufs[i];
2315 rtex = (struct r600_texture*)surf->base.texture;
2316
2317 p_atomic_dec(&rtex->framebuffers_bound);
2318 }
2319 }
2320
2321 static void si_set_framebuffer_state(struct pipe_context *ctx,
2322 const struct pipe_framebuffer_state *state)
2323 {
2324 struct si_context *sctx = (struct si_context *)ctx;
2325 struct pipe_constant_buffer constbuf = {0};
2326 struct r600_surface *surf = NULL;
2327 struct r600_texture *rtex;
2328 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2329 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2330 int i;
2331
2332 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2333 if (!sctx->framebuffer.state.cbufs[i])
2334 continue;
2335
2336 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2337 if (rtex->dcc_gather_statistics)
2338 vi_separate_dcc_stop_query(ctx, rtex);
2339 }
2340
2341 /* Only flush TC when changing the framebuffer state, because
2342 * the only client not using TC that can change textures is
2343 * the framebuffer.
2344 *
2345 * Flush all CB and DB caches here because all buffers can be used
2346 * for write by both TC (with shader image stores) and CB/DB.
2347 */
2348 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2349 SI_CONTEXT_INV_GLOBAL_L2 |
2350 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2351 SI_CONTEXT_CS_PARTIAL_FLUSH;
2352
2353 /* Take the maximum of the old and new count. If the new count is lower,
2354 * dirtying is needed to disable the unbound colorbuffers.
2355 */
2356 sctx->framebuffer.dirty_cbufs |=
2357 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2358 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2359
2360 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2361 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2362
2363 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2364 sctx->framebuffer.spi_shader_col_format = 0;
2365 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2366 sctx->framebuffer.spi_shader_col_format_blend = 0;
2367 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2368 sctx->framebuffer.color_is_int8 = 0;
2369
2370 sctx->framebuffer.compressed_cb_mask = 0;
2371 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2372 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2373 sctx->framebuffer.any_dst_linear = false;
2374
2375 for (i = 0; i < state->nr_cbufs; i++) {
2376 if (!state->cbufs[i])
2377 continue;
2378
2379 surf = (struct r600_surface*)state->cbufs[i];
2380 rtex = (struct r600_texture*)surf->base.texture;
2381
2382 if (!surf->color_initialized) {
2383 si_initialize_color_surface(sctx, surf);
2384 }
2385
2386 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2387 sctx->framebuffer.spi_shader_col_format |=
2388 surf->spi_shader_col_format << (i * 4);
2389 sctx->framebuffer.spi_shader_col_format_alpha |=
2390 surf->spi_shader_col_format_alpha << (i * 4);
2391 sctx->framebuffer.spi_shader_col_format_blend |=
2392 surf->spi_shader_col_format_blend << (i * 4);
2393 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2394 surf->spi_shader_col_format_blend_alpha << (i * 4);
2395
2396 if (surf->color_is_int8)
2397 sctx->framebuffer.color_is_int8 |= 1 << i;
2398
2399 if (rtex->fmask.size) {
2400 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2401 }
2402
2403 if (rtex->surface.is_linear)
2404 sctx->framebuffer.any_dst_linear = true;
2405
2406 r600_context_add_resource_size(ctx, surf->base.texture);
2407
2408 p_atomic_inc(&rtex->framebuffers_bound);
2409
2410 if (rtex->dcc_gather_statistics) {
2411 /* Dirty tracking must be enabled for DCC usage analysis. */
2412 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2413 vi_separate_dcc_start_query(ctx, rtex);
2414 }
2415 }
2416
2417 if (state->zsbuf) {
2418 surf = (struct r600_surface*)state->zsbuf;
2419 rtex = (struct r600_texture*)surf->base.texture;
2420
2421 if (!surf->depth_initialized) {
2422 si_init_depth_surface(sctx, surf);
2423 }
2424 r600_context_add_resource_size(ctx, surf->base.texture);
2425 }
2426
2427 si_update_poly_offset_state(sctx);
2428 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2429 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2430
2431 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2432 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2433
2434 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2435 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2436 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2437
2438 /* Set sample locations as fragment shader constants. */
2439 switch (sctx->framebuffer.nr_samples) {
2440 case 1:
2441 constbuf.user_buffer = sctx->b.sample_locations_1x;
2442 break;
2443 case 2:
2444 constbuf.user_buffer = sctx->b.sample_locations_2x;
2445 break;
2446 case 4:
2447 constbuf.user_buffer = sctx->b.sample_locations_4x;
2448 break;
2449 case 8:
2450 constbuf.user_buffer = sctx->b.sample_locations_8x;
2451 break;
2452 case 16:
2453 constbuf.user_buffer = sctx->b.sample_locations_16x;
2454 break;
2455 default:
2456 R600_ERR("Requested an invalid number of samples %i.\n",
2457 sctx->framebuffer.nr_samples);
2458 assert(0);
2459 }
2460 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2461 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2462
2463 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2464 }
2465
2466 sctx->need_check_render_feedback = true;
2467 sctx->do_update_shaders = true;
2468 }
2469
2470 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2471 {
2472 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2473 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2474 unsigned i, nr_cbufs = state->nr_cbufs;
2475 struct r600_texture *tex = NULL;
2476 struct r600_surface *cb = NULL;
2477 unsigned cb_color_info = 0;
2478
2479 /* Colorbuffers. */
2480 for (i = 0; i < nr_cbufs; i++) {
2481 const struct radeon_surf_level *level_info;
2482 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2483 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2484 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2485
2486 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2487 continue;
2488
2489 cb = (struct r600_surface*)state->cbufs[i];
2490 if (!cb) {
2491 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2492 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2493 continue;
2494 }
2495
2496 tex = (struct r600_texture *)cb->base.texture;
2497 level_info = &tex->surface.level[cb->base.u.tex.level];
2498 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2499 &tex->resource, RADEON_USAGE_READWRITE,
2500 tex->resource.b.b.nr_samples > 1 ?
2501 RADEON_PRIO_COLOR_BUFFER_MSAA :
2502 RADEON_PRIO_COLOR_BUFFER);
2503
2504 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2505 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2506 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2507 RADEON_PRIO_CMASK);
2508 }
2509
2510 if (tex->dcc_separate_buffer)
2511 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2512 tex->dcc_separate_buffer,
2513 RADEON_USAGE_READWRITE,
2514 RADEON_PRIO_DCC);
2515
2516 /* Compute mutable surface parameters. */
2517 pitch_tile_max = level_info->nblk_x / 8 - 1;
2518 slice_tile_max = level_info->nblk_x *
2519 level_info->nblk_y / 64 - 1;
2520 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2521
2522 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2523 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2524 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2525 cb_color_attrib = cb->cb_color_attrib |
2526 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2527
2528 if (tex->fmask.size) {
2529 if (sctx->b.chip_class >= CIK)
2530 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2531 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2532 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2533 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2534 } else {
2535 /* This must be set for fast clear to work without FMASK. */
2536 if (sctx->b.chip_class >= CIK)
2537 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2538 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2539 cb_color_fmask = cb_color_base;
2540 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2541 }
2542
2543 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2544
2545 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2546 bool is_msaa_resolve_dst = state->cbufs[0] &&
2547 state->cbufs[0]->texture->nr_samples > 1 &&
2548 state->cbufs[1] == &cb->base &&
2549 state->cbufs[1]->texture->nr_samples <= 1;
2550
2551 if (!is_msaa_resolve_dst)
2552 cb_color_info |= S_028C70_DCC_ENABLE(1);
2553 }
2554
2555 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2556 sctx->b.chip_class >= VI ? 14 : 13);
2557 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2558 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2559 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2560 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2561 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2562 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2563 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2564 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2565 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2566 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2567 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2568 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2569 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2570
2571 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2572 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2573 tex->dcc_offset +
2574 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2575 }
2576 for (; i < 8 ; i++)
2577 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2578 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2579
2580 /* ZS buffer. */
2581 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2582 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2583 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2584
2585 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2586 &rtex->resource, RADEON_USAGE_READWRITE,
2587 zb->base.texture->nr_samples > 1 ?
2588 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2589 RADEON_PRIO_DEPTH_BUFFER);
2590
2591 if (zb->db_htile_data_base) {
2592 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2593 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2594 RADEON_PRIO_HTILE);
2595 }
2596
2597 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2598 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2599
2600 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2601 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2602 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2603 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2604 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2605 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2606 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2607 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2608 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2609 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2610 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2611
2612 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2613 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2614 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2615
2616 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2617 } else if (sctx->framebuffer.dirty_zsbuf) {
2618 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2619 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2620 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2621 }
2622
2623 /* Framebuffer dimensions. */
2624 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2625 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2626 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2627
2628 sctx->framebuffer.dirty_cbufs = 0;
2629 sctx->framebuffer.dirty_zsbuf = false;
2630 }
2631
2632 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2633 struct r600_atom *atom)
2634 {
2635 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2636 unsigned nr_samples = sctx->framebuffer.nr_samples;
2637
2638 /* Smoothing (only possible with nr_samples == 1) uses the same
2639 * sample locations as the MSAA it simulates.
2640 */
2641 if (nr_samples <= 1 && sctx->smoothing_enabled)
2642 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2643
2644 /* On Polaris, the small primitive filter uses the sample locations
2645 * even when MSAA is off, so we need to make sure they're set to 0.
2646 */
2647 if (sctx->b.family >= CHIP_POLARIS10)
2648 nr_samples = MAX2(nr_samples, 1);
2649
2650 if (nr_samples >= 1 &&
2651 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2652 sctx->msaa_sample_locs.nr_samples = nr_samples;
2653 cayman_emit_msaa_sample_locs(cs, nr_samples);
2654 }
2655
2656 if (sctx->b.family >= CHIP_POLARIS10) {
2657 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2658 unsigned small_prim_filter_cntl =
2659 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2660 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2661
2662 /* The alternative of setting sample locations to 0 would
2663 * require a DB flush to avoid Z errors, see
2664 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2665 */
2666 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2667 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2668
2669 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2670 small_prim_filter_cntl);
2671 }
2672 }
2673
2674 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2675 {
2676 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2677 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2678 /* 33% faster rendering to linear color buffers */
2679 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2680 unsigned sc_mode_cntl_1 =
2681 S_028A4C_WALK_SIZE(dst_is_linear) |
2682 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2683 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2684 /* always 1: */
2685 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2686 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2687 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2688 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2689 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2690 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2691
2692 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2693 sctx->ps_iter_samples,
2694 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2695 sc_mode_cntl_1);
2696 }
2697
2698 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2699 {
2700 struct si_context *sctx = (struct si_context *)ctx;
2701
2702 if (sctx->ps_iter_samples == min_samples)
2703 return;
2704
2705 sctx->ps_iter_samples = min_samples;
2706 sctx->do_update_shaders = true;
2707
2708 if (sctx->framebuffer.nr_samples > 1)
2709 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2710 }
2711
2712 /*
2713 * Samplers
2714 */
2715
2716 /**
2717 * Build the sampler view descriptor for a buffer texture.
2718 * @param state 256-bit descriptor; only the high 128 bits are filled in
2719 */
2720 void
2721 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2722 enum pipe_format format,
2723 unsigned offset, unsigned size,
2724 uint32_t *state)
2725 {
2726 const struct util_format_description *desc;
2727 int first_non_void;
2728 unsigned stride;
2729 unsigned num_records;
2730 unsigned num_format, data_format;
2731
2732 desc = util_format_description(format);
2733 first_non_void = util_format_get_first_non_void_channel(format);
2734 stride = desc->block.bits / 8;
2735 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2736 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2737
2738 num_records = size / stride;
2739 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2740
2741 if (screen->b.chip_class >= VI)
2742 num_records *= stride;
2743
2744 state[4] = 0;
2745 state[5] = S_008F04_STRIDE(stride);
2746 state[6] = num_records;
2747 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2748 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2749 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2750 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2751 S_008F0C_NUM_FORMAT(num_format) |
2752 S_008F0C_DATA_FORMAT(data_format);
2753 }
2754
2755 /**
2756 * Build the sampler view descriptor for a texture.
2757 */
2758 void
2759 si_make_texture_descriptor(struct si_screen *screen,
2760 struct r600_texture *tex,
2761 bool sampler,
2762 enum pipe_texture_target target,
2763 enum pipe_format pipe_format,
2764 const unsigned char state_swizzle[4],
2765 unsigned first_level, unsigned last_level,
2766 unsigned first_layer, unsigned last_layer,
2767 unsigned width, unsigned height, unsigned depth,
2768 uint32_t *state,
2769 uint32_t *fmask_state)
2770 {
2771 struct pipe_resource *res = &tex->resource.b.b;
2772 const struct util_format_description *desc;
2773 unsigned char swizzle[4];
2774 int first_non_void;
2775 unsigned num_format, data_format, type;
2776 uint64_t va;
2777
2778 desc = util_format_description(pipe_format);
2779
2780 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2781 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2782 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2783
2784 switch (pipe_format) {
2785 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2786 case PIPE_FORMAT_X24S8_UINT:
2787 case PIPE_FORMAT_X32_S8X24_UINT:
2788 case PIPE_FORMAT_X8Z24_UNORM:
2789 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2790 break;
2791 default:
2792 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2793 }
2794 } else {
2795 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2796 }
2797
2798 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2799
2800 switch (pipe_format) {
2801 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2802 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2803 break;
2804 default:
2805 if (first_non_void < 0) {
2806 if (util_format_is_compressed(pipe_format)) {
2807 switch (pipe_format) {
2808 case PIPE_FORMAT_DXT1_SRGB:
2809 case PIPE_FORMAT_DXT1_SRGBA:
2810 case PIPE_FORMAT_DXT3_SRGBA:
2811 case PIPE_FORMAT_DXT5_SRGBA:
2812 case PIPE_FORMAT_BPTC_SRGBA:
2813 case PIPE_FORMAT_ETC2_SRGB8:
2814 case PIPE_FORMAT_ETC2_SRGB8A1:
2815 case PIPE_FORMAT_ETC2_SRGBA8:
2816 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2817 break;
2818 case PIPE_FORMAT_RGTC1_SNORM:
2819 case PIPE_FORMAT_LATC1_SNORM:
2820 case PIPE_FORMAT_RGTC2_SNORM:
2821 case PIPE_FORMAT_LATC2_SNORM:
2822 case PIPE_FORMAT_ETC2_R11_SNORM:
2823 case PIPE_FORMAT_ETC2_RG11_SNORM:
2824 /* implies float, so use SNORM/UNORM to determine
2825 whether data is signed or not */
2826 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2827 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2828 break;
2829 default:
2830 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2831 break;
2832 }
2833 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2834 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2835 } else {
2836 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2837 }
2838 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2839 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2840 } else {
2841 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2842
2843 switch (desc->channel[first_non_void].type) {
2844 case UTIL_FORMAT_TYPE_FLOAT:
2845 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2846 break;
2847 case UTIL_FORMAT_TYPE_SIGNED:
2848 if (desc->channel[first_non_void].normalized)
2849 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2850 else if (desc->channel[first_non_void].pure_integer)
2851 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2852 else
2853 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2854 break;
2855 case UTIL_FORMAT_TYPE_UNSIGNED:
2856 if (desc->channel[first_non_void].normalized)
2857 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2858 else if (desc->channel[first_non_void].pure_integer)
2859 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2860 else
2861 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2862 }
2863 }
2864 }
2865
2866 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2867 if (data_format == ~0) {
2868 data_format = 0;
2869 }
2870
2871 if (!sampler &&
2872 (res->target == PIPE_TEXTURE_CUBE ||
2873 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2874 res->target == PIPE_TEXTURE_3D)) {
2875 /* For the purpose of shader images, treat cube maps and 3D
2876 * textures as 2D arrays. For 3D textures, the address
2877 * calculations for mipmaps are different, so we rely on the
2878 * caller to effectively disable mipmaps.
2879 */
2880 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2881
2882 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2883 } else {
2884 type = si_tex_dim(res->target, target, res->nr_samples);
2885 }
2886
2887 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2888 height = 1;
2889 depth = res->array_size;
2890 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2891 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2892 if (sampler || res->target != PIPE_TEXTURE_3D)
2893 depth = res->array_size;
2894 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2895 depth = res->array_size / 6;
2896
2897 state[0] = 0;
2898 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2899 S_008F14_NUM_FORMAT(num_format));
2900 state[2] = (S_008F18_WIDTH(width - 1) |
2901 S_008F18_HEIGHT(height - 1) |
2902 S_008F18_PERF_MOD(4));
2903 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2904 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2905 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2906 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2907 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2908 0 : first_level) |
2909 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2910 util_logbase2(res->nr_samples) :
2911 last_level) |
2912 S_008F1C_POW2_PAD(res->last_level > 0) |
2913 S_008F1C_TYPE(type));
2914 state[4] = S_008F20_DEPTH(depth - 1);
2915 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2916 S_008F24_LAST_ARRAY(last_layer));
2917 state[6] = 0;
2918 state[7] = 0;
2919
2920 if (tex->dcc_offset) {
2921 unsigned swap = r600_translate_colorswap(pipe_format, false);
2922
2923 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2924 } else {
2925 /* The last dword is unused by hw. The shader uses it to clear
2926 * bits in the first dword of sampler state.
2927 */
2928 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2929 if (first_level == last_level)
2930 state[7] = C_008F30_MAX_ANISO_RATIO;
2931 else
2932 state[7] = 0xffffffff;
2933 }
2934 }
2935
2936 /* Initialize the sampler view for FMASK. */
2937 if (tex->fmask.size) {
2938 uint32_t fmask_format;
2939
2940 va = tex->resource.gpu_address + tex->fmask.offset;
2941
2942 switch (res->nr_samples) {
2943 case 2:
2944 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2945 break;
2946 case 4:
2947 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2948 break;
2949 case 8:
2950 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2951 break;
2952 default:
2953 assert(0);
2954 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2955 }
2956
2957 fmask_state[0] = va >> 8;
2958 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2959 S_008F14_DATA_FORMAT(fmask_format) |
2960 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2961 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2962 S_008F18_HEIGHT(height - 1);
2963 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2964 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2965 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2966 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2967 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2968 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2969 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2970 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2971 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2972 S_008F24_LAST_ARRAY(last_layer);
2973 fmask_state[6] = 0;
2974 fmask_state[7] = 0;
2975 }
2976 }
2977
2978 /**
2979 * Create a sampler view.
2980 *
2981 * @param ctx context
2982 * @param texture texture
2983 * @param state sampler view template
2984 * @param width0 width0 override (for compressed textures as int)
2985 * @param height0 height0 override (for compressed textures as int)
2986 * @param force_level set the base address to the level (for compressed textures)
2987 */
2988 struct pipe_sampler_view *
2989 si_create_sampler_view_custom(struct pipe_context *ctx,
2990 struct pipe_resource *texture,
2991 const struct pipe_sampler_view *state,
2992 unsigned width0, unsigned height0,
2993 unsigned force_level)
2994 {
2995 struct si_context *sctx = (struct si_context*)ctx;
2996 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2997 struct r600_texture *tmp = (struct r600_texture*)texture;
2998 unsigned base_level, first_level, last_level;
2999 unsigned char state_swizzle[4];
3000 unsigned height, depth, width;
3001 unsigned last_layer = state->u.tex.last_layer;
3002 enum pipe_format pipe_format;
3003 const struct radeon_surf_level *surflevel;
3004
3005 if (!view)
3006 return NULL;
3007
3008 /* initialize base object */
3009 view->base = *state;
3010 view->base.texture = NULL;
3011 view->base.reference.count = 1;
3012 view->base.context = ctx;
3013
3014 assert(texture);
3015 pipe_resource_reference(&view->base.texture, texture);
3016
3017 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3018 state->format == PIPE_FORMAT_S8X24_UINT ||
3019 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3020 state->format == PIPE_FORMAT_S8_UINT)
3021 view->is_stencil_sampler = true;
3022
3023 /* Buffer resource. */
3024 if (texture->target == PIPE_BUFFER) {
3025 si_make_buffer_descriptor(sctx->screen,
3026 (struct r600_resource *)texture,
3027 state->format,
3028 state->u.buf.offset,
3029 state->u.buf.size,
3030 view->state);
3031 return &view->base;
3032 }
3033
3034 state_swizzle[0] = state->swizzle_r;
3035 state_swizzle[1] = state->swizzle_g;
3036 state_swizzle[2] = state->swizzle_b;
3037 state_swizzle[3] = state->swizzle_a;
3038
3039 base_level = 0;
3040 first_level = state->u.tex.first_level;
3041 last_level = state->u.tex.last_level;
3042 width = width0;
3043 height = height0;
3044 depth = texture->depth0;
3045
3046 if (force_level) {
3047 assert(force_level == first_level &&
3048 force_level == last_level);
3049 base_level = force_level;
3050 first_level = 0;
3051 last_level = 0;
3052 width = u_minify(width, force_level);
3053 height = u_minify(height, force_level);
3054 depth = u_minify(depth, force_level);
3055 }
3056
3057 /* This is not needed if state trackers set last_layer correctly. */
3058 if (state->target == PIPE_TEXTURE_1D ||
3059 state->target == PIPE_TEXTURE_2D ||
3060 state->target == PIPE_TEXTURE_RECT ||
3061 state->target == PIPE_TEXTURE_CUBE)
3062 last_layer = state->u.tex.first_layer;
3063
3064 /* Texturing with separate depth and stencil. */
3065 pipe_format = state->format;
3066
3067 /* Depth/stencil texturing sometimes needs separate texture. */
3068 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3069 if (!tmp->flushed_depth_texture &&
3070 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3071 pipe_resource_reference(&view->base.texture, NULL);
3072 FREE(view);
3073 return NULL;
3074 }
3075
3076 assert(tmp->flushed_depth_texture);
3077
3078 /* Override format for the case where the flushed texture
3079 * contains only Z or only S.
3080 */
3081 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3082 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3083
3084 tmp = tmp->flushed_depth_texture;
3085 }
3086
3087 surflevel = tmp->surface.level;
3088
3089 if (tmp->db_compatible) {
3090 if (!view->is_stencil_sampler)
3091 pipe_format = tmp->db_render_format;
3092
3093 switch (pipe_format) {
3094 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3095 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3096 break;
3097 case PIPE_FORMAT_X8Z24_UNORM:
3098 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3099 /* Z24 is always stored like this for DB
3100 * compatibility.
3101 */
3102 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3103 break;
3104 case PIPE_FORMAT_X24S8_UINT:
3105 case PIPE_FORMAT_S8X24_UINT:
3106 case PIPE_FORMAT_X32_S8X24_UINT:
3107 pipe_format = PIPE_FORMAT_S8_UINT;
3108 surflevel = tmp->surface.stencil_level;
3109 break;
3110 default:;
3111 }
3112 }
3113
3114 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3115 state->u.tex.first_level,
3116 state->format);
3117
3118 si_make_texture_descriptor(sctx->screen, tmp, true,
3119 state->target, pipe_format, state_swizzle,
3120 first_level, last_level,
3121 state->u.tex.first_layer, last_layer,
3122 width, height, depth,
3123 view->state, view->fmask_state);
3124
3125 view->base_level_info = &surflevel[base_level];
3126 view->base_level = base_level;
3127 view->block_width = util_format_get_blockwidth(pipe_format);
3128 return &view->base;
3129 }
3130
3131 static struct pipe_sampler_view *
3132 si_create_sampler_view(struct pipe_context *ctx,
3133 struct pipe_resource *texture,
3134 const struct pipe_sampler_view *state)
3135 {
3136 return si_create_sampler_view_custom(ctx, texture, state,
3137 texture ? texture->width0 : 0,
3138 texture ? texture->height0 : 0, 0);
3139 }
3140
3141 static void si_sampler_view_destroy(struct pipe_context *ctx,
3142 struct pipe_sampler_view *state)
3143 {
3144 struct si_sampler_view *view = (struct si_sampler_view *)state;
3145
3146 pipe_resource_reference(&state->texture, NULL);
3147 FREE(view);
3148 }
3149
3150 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3151 {
3152 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3153 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3154 (linear_filter &&
3155 (wrap == PIPE_TEX_WRAP_CLAMP ||
3156 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3157 }
3158
3159 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3160 {
3161 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3162 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3163
3164 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3165 state->border_color.ui[2] || state->border_color.ui[3]) &&
3166 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3167 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3168 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3169 }
3170
3171 static void *si_create_sampler_state(struct pipe_context *ctx,
3172 const struct pipe_sampler_state *state)
3173 {
3174 struct si_context *sctx = (struct si_context *)ctx;
3175 struct r600_common_screen *rscreen = sctx->b.screen;
3176 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3177 unsigned border_color_type, border_color_index = 0;
3178 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3179 : state->max_anisotropy;
3180 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3181
3182 if (!rstate) {
3183 return NULL;
3184 }
3185
3186 if (!sampler_state_needs_border_color(state))
3187 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3188 else if (state->border_color.f[0] == 0 &&
3189 state->border_color.f[1] == 0 &&
3190 state->border_color.f[2] == 0 &&
3191 state->border_color.f[3] == 0)
3192 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3193 else if (state->border_color.f[0] == 0 &&
3194 state->border_color.f[1] == 0 &&
3195 state->border_color.f[2] == 0 &&
3196 state->border_color.f[3] == 1)
3197 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3198 else if (state->border_color.f[0] == 1 &&
3199 state->border_color.f[1] == 1 &&
3200 state->border_color.f[2] == 1 &&
3201 state->border_color.f[3] == 1)
3202 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3203 else {
3204 int i;
3205
3206 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3207
3208 /* Check if the border has been uploaded already. */
3209 for (i = 0; i < sctx->border_color_count; i++)
3210 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3211 sizeof(state->border_color)) == 0)
3212 break;
3213
3214 if (i >= SI_MAX_BORDER_COLORS) {
3215 /* Getting 4096 unique border colors is very unlikely. */
3216 fprintf(stderr, "radeonsi: The border color table is full. "
3217 "Any new border colors will be just black. "
3218 "Please file a bug.\n");
3219 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3220 } else {
3221 if (i == sctx->border_color_count) {
3222 /* Upload a new border color. */
3223 memcpy(&sctx->border_color_table[i], &state->border_color,
3224 sizeof(state->border_color));
3225 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3226 &state->border_color,
3227 sizeof(state->border_color));
3228 sctx->border_color_count++;
3229 }
3230
3231 border_color_index = i;
3232 }
3233 }
3234
3235 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3236 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3237 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3238 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3239 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3240 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3241 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3242 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3243 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3244 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3245 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3246 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3247 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3248 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3249 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3250 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3251 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3252 S_008F38_MIP_POINT_PRECLAMP(1) |
3253 S_008F38_DISABLE_LSB_CEIL(1) |
3254 S_008F38_FILTER_PREC_FIX(1) |
3255 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3256 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3257 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3258 return rstate;
3259 }
3260
3261 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3262 {
3263 struct si_context *sctx = (struct si_context *)ctx;
3264
3265 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3266 return;
3267
3268 sctx->sample_mask.sample_mask = sample_mask;
3269 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3270 }
3271
3272 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3273 {
3274 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3275 unsigned mask = sctx->sample_mask.sample_mask;
3276
3277 /* Needed for line and polygon smoothing as well as for the Polaris
3278 * small primitive filter. We expect the state tracker to take care of
3279 * this for us.
3280 */
3281 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3282 (mask & 1 && sctx->blitter->running));
3283
3284 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3285 radeon_emit(cs, mask | (mask << 16));
3286 radeon_emit(cs, mask | (mask << 16));
3287 }
3288
3289 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3290 {
3291 free(state);
3292 }
3293
3294 /*
3295 * Vertex elements & buffers
3296 */
3297
3298 static void *si_create_vertex_elements(struct pipe_context *ctx,
3299 unsigned count,
3300 const struct pipe_vertex_element *elements)
3301 {
3302 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3303 int i;
3304
3305 assert(count <= SI_MAX_ATTRIBS);
3306 if (!v)
3307 return NULL;
3308
3309 v->count = count;
3310 for (i = 0; i < count; ++i) {
3311 const struct util_format_description *desc;
3312 unsigned data_format, num_format;
3313 int first_non_void;
3314
3315 desc = util_format_description(elements[i].src_format);
3316 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3317 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3318 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3319
3320 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3321 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3322 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3323 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3324 S_008F0C_NUM_FORMAT(num_format) |
3325 S_008F0C_DATA_FORMAT(data_format);
3326 v->format_size[i] = desc->block.bits / 8;
3327
3328 /* The hardware always treats the 2-bit alpha channel as
3329 * unsigned, so a shader workaround is needed.
3330 */
3331 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3332 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3333 v->fix_fetch |= SI_FIX_FETCH_A2_SNORM << (2 * i);
3334 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3335 v->fix_fetch |= SI_FIX_FETCH_A2_SSCALED << (2 * i);
3336 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3337 /* This isn't actually used in OpenGL. */
3338 v->fix_fetch |= SI_FIX_FETCH_A2_SINT << (2 * i);
3339 }
3340 }
3341
3342 /* We work around the fact that 8_8_8 and 16_16_16 data formats
3343 * do not exist by using the corresponding 4-component formats.
3344 * This requires a fixup of the descriptor for bounds checks.
3345 */
3346 if (desc->block.bits == 3 * 8 ||
3347 desc->block.bits == 3 * 16) {
3348 v->fix_size3 |= (desc->block.bits / 24) << (2 * i);
3349 }
3350 }
3351 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3352
3353 return v;
3354 }
3355
3356 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3357 {
3358 struct si_context *sctx = (struct si_context *)ctx;
3359 struct si_vertex_element *v = (struct si_vertex_element*)state;
3360
3361 sctx->vertex_elements = v;
3362 sctx->vertex_buffers_dirty = true;
3363 sctx->do_update_shaders = true;
3364 }
3365
3366 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3367 {
3368 struct si_context *sctx = (struct si_context *)ctx;
3369
3370 if (sctx->vertex_elements == state)
3371 sctx->vertex_elements = NULL;
3372 FREE(state);
3373 }
3374
3375 static void si_set_vertex_buffers(struct pipe_context *ctx,
3376 unsigned start_slot, unsigned count,
3377 const struct pipe_vertex_buffer *buffers)
3378 {
3379 struct si_context *sctx = (struct si_context *)ctx;
3380 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3381 int i;
3382
3383 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3384
3385 if (buffers) {
3386 for (i = 0; i < count; i++) {
3387 const struct pipe_vertex_buffer *src = buffers + i;
3388 struct pipe_vertex_buffer *dsti = dst + i;
3389 struct pipe_resource *buf = src->buffer;
3390
3391 pipe_resource_reference(&dsti->buffer, buf);
3392 dsti->buffer_offset = src->buffer_offset;
3393 dsti->stride = src->stride;
3394 r600_context_add_resource_size(ctx, buf);
3395 if (buf)
3396 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3397 }
3398 } else {
3399 for (i = 0; i < count; i++) {
3400 pipe_resource_reference(&dst[i].buffer, NULL);
3401 }
3402 }
3403 sctx->vertex_buffers_dirty = true;
3404 }
3405
3406 static void si_set_index_buffer(struct pipe_context *ctx,
3407 const struct pipe_index_buffer *ib)
3408 {
3409 struct si_context *sctx = (struct si_context *)ctx;
3410
3411 if (ib) {
3412 struct pipe_resource *buf = ib->buffer;
3413
3414 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3415 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3416 r600_context_add_resource_size(ctx, buf);
3417 if (buf)
3418 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3419 } else {
3420 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3421 }
3422 }
3423
3424 /*
3425 * Misc
3426 */
3427
3428 static void si_set_tess_state(struct pipe_context *ctx,
3429 const float default_outer_level[4],
3430 const float default_inner_level[2])
3431 {
3432 struct si_context *sctx = (struct si_context *)ctx;
3433 struct pipe_constant_buffer cb;
3434 float array[8];
3435
3436 memcpy(array, default_outer_level, sizeof(float) * 4);
3437 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3438
3439 cb.buffer = NULL;
3440 cb.user_buffer = NULL;
3441 cb.buffer_size = sizeof(array);
3442
3443 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3444 (void*)array, sizeof(array),
3445 &cb.buffer_offset);
3446
3447 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3448 pipe_resource_reference(&cb.buffer, NULL);
3449 }
3450
3451 static void si_texture_barrier(struct pipe_context *ctx)
3452 {
3453 struct si_context *sctx = (struct si_context *)ctx;
3454
3455 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3456 SI_CONTEXT_INV_GLOBAL_L2 |
3457 SI_CONTEXT_FLUSH_AND_INV_CB |
3458 SI_CONTEXT_CS_PARTIAL_FLUSH;
3459 }
3460
3461 /* This only ensures coherency for shader image/buffer stores. */
3462 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3463 {
3464 struct si_context *sctx = (struct si_context *)ctx;
3465
3466 /* Subsequent commands must wait for all shader invocations to
3467 * complete. */
3468 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3469 SI_CONTEXT_CS_PARTIAL_FLUSH;
3470
3471 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3472 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3473 SI_CONTEXT_INV_VMEM_L1;
3474
3475 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3476 PIPE_BARRIER_SHADER_BUFFER |
3477 PIPE_BARRIER_TEXTURE |
3478 PIPE_BARRIER_IMAGE |
3479 PIPE_BARRIER_STREAMOUT_BUFFER |
3480 PIPE_BARRIER_GLOBAL_BUFFER)) {
3481 /* As far as I can tell, L1 contents are written back to L2
3482 * automatically at end of shader, but the contents of other
3483 * L1 caches might still be stale. */
3484 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3485 }
3486
3487 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3488 /* Indices are read through TC L2 since VI.
3489 * L1 isn't used.
3490 */
3491 if (sctx->screen->b.chip_class <= CIK)
3492 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3493 }
3494
3495 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3496 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3497
3498 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3499 PIPE_BARRIER_INDIRECT_BUFFER))
3500 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3501 }
3502
3503 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3504 {
3505 struct pipe_blend_state blend;
3506
3507 memset(&blend, 0, sizeof(blend));
3508 blend.independent_blend_enable = true;
3509 blend.rt[0].colormask = 0xf;
3510 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3511 }
3512
3513 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3514 bool include_draw_vbo)
3515 {
3516 si_need_cs_space((struct si_context*)ctx);
3517 }
3518
3519 static void si_init_config(struct si_context *sctx);
3520
3521 void si_init_state_functions(struct si_context *sctx)
3522 {
3523 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3524 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3525 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3526 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3527 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3528
3529 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3530 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3531 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3532 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3533 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3534 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3535 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3536 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3537 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3538 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3539
3540 sctx->b.b.create_blend_state = si_create_blend_state;
3541 sctx->b.b.bind_blend_state = si_bind_blend_state;
3542 sctx->b.b.delete_blend_state = si_delete_blend_state;
3543 sctx->b.b.set_blend_color = si_set_blend_color;
3544
3545 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3546 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3547 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3548
3549 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3550 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3551 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3552
3553 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3554 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3555 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3556 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3557 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3558
3559 sctx->b.b.set_clip_state = si_set_clip_state;
3560 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3561
3562 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3563 sctx->b.b.get_sample_position = cayman_get_sample_position;
3564
3565 sctx->b.b.create_sampler_state = si_create_sampler_state;
3566 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3567
3568 sctx->b.b.create_sampler_view = si_create_sampler_view;
3569 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3570
3571 sctx->b.b.set_sample_mask = si_set_sample_mask;
3572
3573 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3574 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3575 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3576 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3577 sctx->b.b.set_index_buffer = si_set_index_buffer;
3578
3579 sctx->b.b.texture_barrier = si_texture_barrier;
3580 sctx->b.b.memory_barrier = si_memory_barrier;
3581 sctx->b.b.set_min_samples = si_set_min_samples;
3582 sctx->b.b.set_tess_state = si_set_tess_state;
3583
3584 sctx->b.b.set_active_query_state = si_set_active_query_state;
3585 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3586 sctx->b.save_qbo_state = si_save_qbo_state;
3587 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3588
3589 sctx->b.b.draw_vbo = si_draw_vbo;
3590
3591 si_init_config(sctx);
3592 }
3593
3594 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3595 {
3596 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3597 }
3598
3599 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3600 struct r600_texture *rtex,
3601 struct radeon_bo_metadata *md)
3602 {
3603 struct si_screen *sscreen = (struct si_screen*)rscreen;
3604 struct pipe_resource *res = &rtex->resource.b.b;
3605 static const unsigned char swizzle[] = {
3606 PIPE_SWIZZLE_X,
3607 PIPE_SWIZZLE_Y,
3608 PIPE_SWIZZLE_Z,
3609 PIPE_SWIZZLE_W
3610 };
3611 uint32_t desc[8], i;
3612 bool is_array = util_resource_is_array_texture(res);
3613
3614 /* DRM 2.x.x doesn't support this. */
3615 if (rscreen->info.drm_major != 3)
3616 return;
3617
3618 assert(rtex->dcc_separate_buffer == NULL);
3619 assert(rtex->fmask.size == 0);
3620
3621 /* Metadata image format format version 1:
3622 * [0] = 1 (metadata format identifier)
3623 * [1] = (VENDOR_ID << 16) | PCI_ID
3624 * [2:9] = image descriptor for the whole resource
3625 * [2] is always 0, because the base address is cleared
3626 * [9] is the DCC offset bits [39:8] from the beginning of
3627 * the buffer
3628 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3629 */
3630
3631 md->metadata[0] = 1; /* metadata image format version 1 */
3632
3633 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3634 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3635
3636 si_make_texture_descriptor(sscreen, rtex, true,
3637 res->target, res->format,
3638 swizzle, 0, res->last_level, 0,
3639 is_array ? res->array_size - 1 : 0,
3640 res->width0, res->height0, res->depth0,
3641 desc, NULL);
3642
3643 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3644 rtex->surface.blk_w, false, desc);
3645
3646 /* Clear the base address and set the relative DCC offset. */
3647 desc[0] = 0;
3648 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3649 desc[7] = rtex->dcc_offset >> 8;
3650
3651 /* Dwords [2:9] contain the image descriptor. */
3652 memcpy(&md->metadata[2], desc, sizeof(desc));
3653
3654 /* Dwords [10:..] contain the mipmap level offsets. */
3655 for (i = 0; i <= res->last_level; i++)
3656 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3657
3658 md->size_metadata = (11 + res->last_level) * 4;
3659 }
3660
3661 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3662 struct r600_texture *rtex,
3663 struct radeon_bo_metadata *md)
3664 {
3665 uint32_t *desc = &md->metadata[2];
3666
3667 if (rscreen->chip_class < VI)
3668 return;
3669
3670 /* Return if DCC is enabled. The texture should be set up with it
3671 * already.
3672 */
3673 if (md->size_metadata >= 11 * 4 &&
3674 md->metadata[0] != 0 &&
3675 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3676 G_008F28_COMPRESSION_EN(desc[6])) {
3677 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3678 return;
3679 }
3680
3681 /* Disable DCC. These are always set by texture_from_handle and must
3682 * be cleared here.
3683 */
3684 rtex->dcc_offset = 0;
3685 }
3686
3687 void si_init_screen_state_functions(struct si_screen *sscreen)
3688 {
3689 sscreen->b.b.is_format_supported = si_is_format_supported;
3690 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3691 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3692 }
3693
3694 static void
3695 si_write_harvested_raster_configs(struct si_context *sctx,
3696 struct si_pm4_state *pm4,
3697 unsigned raster_config,
3698 unsigned raster_config_1)
3699 {
3700 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3701 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3702 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3703 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3704 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3705 unsigned rb_per_se = num_rb / num_se;
3706 unsigned se_mask[4];
3707 unsigned se;
3708
3709 se_mask[0] = ((1 << rb_per_se) - 1);
3710 se_mask[1] = (se_mask[0] << rb_per_se);
3711 se_mask[2] = (se_mask[1] << rb_per_se);
3712 se_mask[3] = (se_mask[2] << rb_per_se);
3713
3714 se_mask[0] &= rb_mask;
3715 se_mask[1] &= rb_mask;
3716 se_mask[2] &= rb_mask;
3717 se_mask[3] &= rb_mask;
3718
3719 assert(num_se == 1 || num_se == 2 || num_se == 4);
3720 assert(sh_per_se == 1 || sh_per_se == 2);
3721 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3722
3723 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3724 * fields are for, so I'm leaving them as their default
3725 * values. */
3726
3727 for (se = 0; se < num_se; se++) {
3728 unsigned raster_config_se = raster_config;
3729 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3730 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3731 int idx = (se / 2) * 2;
3732
3733 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3734 raster_config_se &= C_028350_SE_MAP;
3735
3736 if (!se_mask[idx]) {
3737 raster_config_se |=
3738 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3739 } else {
3740 raster_config_se |=
3741 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3742 }
3743 }
3744
3745 pkr0_mask &= rb_mask;
3746 pkr1_mask &= rb_mask;
3747 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3748 raster_config_se &= C_028350_PKR_MAP;
3749
3750 if (!pkr0_mask) {
3751 raster_config_se |=
3752 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3753 } else {
3754 raster_config_se |=
3755 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3756 }
3757 }
3758
3759 if (rb_per_se >= 2) {
3760 unsigned rb0_mask = 1 << (se * rb_per_se);
3761 unsigned rb1_mask = rb0_mask << 1;
3762
3763 rb0_mask &= rb_mask;
3764 rb1_mask &= rb_mask;
3765 if (!rb0_mask || !rb1_mask) {
3766 raster_config_se &= C_028350_RB_MAP_PKR0;
3767
3768 if (!rb0_mask) {
3769 raster_config_se |=
3770 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3771 } else {
3772 raster_config_se |=
3773 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3774 }
3775 }
3776
3777 if (rb_per_se > 2) {
3778 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3779 rb1_mask = rb0_mask << 1;
3780 rb0_mask &= rb_mask;
3781 rb1_mask &= rb_mask;
3782 if (!rb0_mask || !rb1_mask) {
3783 raster_config_se &= C_028350_RB_MAP_PKR1;
3784
3785 if (!rb0_mask) {
3786 raster_config_se |=
3787 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3788 } else {
3789 raster_config_se |=
3790 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3791 }
3792 }
3793 }
3794 }
3795
3796 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3797 if (sctx->b.chip_class < CIK)
3798 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3799 SE_INDEX(se) | SH_BROADCAST_WRITES |
3800 INSTANCE_BROADCAST_WRITES);
3801 else
3802 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3803 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3804 S_030800_INSTANCE_BROADCAST_WRITES(1));
3805 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3806 }
3807
3808 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3809 if (sctx->b.chip_class < CIK)
3810 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3811 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3812 INSTANCE_BROADCAST_WRITES);
3813 else {
3814 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3815 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3816 S_030800_INSTANCE_BROADCAST_WRITES(1));
3817
3818 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3819 (!se_mask[2] && !se_mask[3]))) {
3820 raster_config_1 &= C_028354_SE_PAIR_MAP;
3821
3822 if (!se_mask[0] && !se_mask[1]) {
3823 raster_config_1 |=
3824 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3825 } else {
3826 raster_config_1 |=
3827 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3828 }
3829 }
3830
3831 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3832 }
3833 }
3834
3835 static void si_init_config(struct si_context *sctx)
3836 {
3837 struct si_screen *sscreen = sctx->screen;
3838 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3839 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3840 unsigned raster_config, raster_config_1;
3841 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3842 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3843
3844 if (!pm4)
3845 return;
3846
3847 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3848 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3849 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3850 si_pm4_cmd_end(pm4, false);
3851
3852 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3853 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3854
3855 /* FIXME calculate these values somehow ??? */
3856 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3857 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3858 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3859
3860 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3861 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3862
3863 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3864 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3865 if (sctx->b.chip_class < CIK)
3866 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3867 S_008A14_CLIP_VTX_REORDER_ENA(1));
3868
3869 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3870 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3871
3872 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3873
3874 switch (sctx->screen->b.family) {
3875 case CHIP_TAHITI:
3876 case CHIP_PITCAIRN:
3877 raster_config = 0x2a00126a;
3878 raster_config_1 = 0x00000000;
3879 break;
3880 case CHIP_VERDE:
3881 raster_config = 0x0000124a;
3882 raster_config_1 = 0x00000000;
3883 break;
3884 case CHIP_OLAND:
3885 raster_config = 0x00000082;
3886 raster_config_1 = 0x00000000;
3887 break;
3888 case CHIP_HAINAN:
3889 raster_config = 0x00000000;
3890 raster_config_1 = 0x00000000;
3891 break;
3892 case CHIP_BONAIRE:
3893 raster_config = 0x16000012;
3894 raster_config_1 = 0x00000000;
3895 break;
3896 case CHIP_HAWAII:
3897 raster_config = 0x3a00161a;
3898 raster_config_1 = 0x0000002e;
3899 break;
3900 case CHIP_FIJI:
3901 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3902 /* old kernels with old tiling config */
3903 raster_config = 0x16000012;
3904 raster_config_1 = 0x0000002a;
3905 } else {
3906 raster_config = 0x3a00161a;
3907 raster_config_1 = 0x0000002e;
3908 }
3909 break;
3910 case CHIP_POLARIS10:
3911 raster_config = 0x16000012;
3912 raster_config_1 = 0x0000002a;
3913 break;
3914 case CHIP_POLARIS11:
3915 raster_config = 0x16000012;
3916 raster_config_1 = 0x00000000;
3917 break;
3918 case CHIP_TONGA:
3919 raster_config = 0x16000012;
3920 raster_config_1 = 0x0000002a;
3921 break;
3922 case CHIP_ICELAND:
3923 if (num_rb == 1)
3924 raster_config = 0x00000000;
3925 else
3926 raster_config = 0x00000002;
3927 raster_config_1 = 0x00000000;
3928 break;
3929 case CHIP_CARRIZO:
3930 raster_config = 0x00000002;
3931 raster_config_1 = 0x00000000;
3932 break;
3933 case CHIP_KAVERI:
3934 /* KV should be 0x00000002, but that causes problems with radeon */
3935 raster_config = 0x00000000; /* 0x00000002 */
3936 raster_config_1 = 0x00000000;
3937 break;
3938 case CHIP_KABINI:
3939 case CHIP_MULLINS:
3940 case CHIP_STONEY:
3941 raster_config = 0x00000000;
3942 raster_config_1 = 0x00000000;
3943 break;
3944 default:
3945 fprintf(stderr,
3946 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3947 raster_config = 0x00000000;
3948 raster_config_1 = 0x00000000;
3949 break;
3950 }
3951
3952 /* Always use the default config when all backends are enabled
3953 * (or when we failed to determine the enabled backends).
3954 */
3955 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3956 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3957 raster_config);
3958 if (sctx->b.chip_class >= CIK)
3959 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3960 raster_config_1);
3961 } else {
3962 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3963 }
3964
3965 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3966 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3967 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3968 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3969 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3970 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3971 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3972
3973 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3974 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3975 S_028230_ER_TRI(0xA) |
3976 S_028230_ER_POINT(0xA) |
3977 S_028230_ER_RECT(0xA) |
3978 /* Required by DX10_DIAMOND_TEST_ENA: */
3979 S_028230_ER_LINE_LR(0x1A) |
3980 S_028230_ER_LINE_RL(0x26) |
3981 S_028230_ER_LINE_TB(0xA) |
3982 S_028230_ER_LINE_BT(0xA));
3983 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3984 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3985 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3986 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3987 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3988 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3989 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
3990
3991 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3992 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3993 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3994
3995 if (sctx->b.chip_class >= CIK) {
3996 /* If this is 0, Bonaire can hang even if GS isn't being used.
3997 * Other chips are unaffected. These are suboptimal values,
3998 * but we don't use on-chip GS.
3999 */
4000 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4001 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4002 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4003
4004 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4005 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4006 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4007 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4008
4009 if (sscreen->b.info.num_good_compute_units /
4010 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4011 /* Too few available compute units per SH. Disallowing
4012 * VS to run on CU0 could hurt us more than late VS
4013 * allocation would help.
4014 *
4015 * LATE_ALLOC_VS = 2 is the highest safe number.
4016 */
4017 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4018 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4019 } else {
4020 /* Set LATE_ALLOC_VS == 31. It should be less than
4021 * the number of scratch waves. Limitations:
4022 * - VS can't execute on CU0.
4023 * - If HS writes outputs to LDS, LS can't execute on CU0.
4024 */
4025 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4026 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4027 }
4028
4029 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4030 }
4031
4032 if (sctx->b.chip_class >= VI) {
4033 unsigned vgt_tess_distribution;
4034
4035 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4036 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4037 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4038 if (sctx->b.family < CHIP_POLARIS10)
4039 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4040 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4041
4042 vgt_tess_distribution =
4043 S_028B50_ACCUM_ISOLINE(32) |
4044 S_028B50_ACCUM_TRI(11) |
4045 S_028B50_ACCUM_QUAD(11) |
4046 S_028B50_DONUT_SPLIT(16);
4047
4048 /* Testing with Unigine Heaven extreme tesselation yielded best results
4049 * with TRAP_SPLIT = 3.
4050 */
4051 if (sctx->b.family == CHIP_FIJI ||
4052 sctx->b.family >= CHIP_POLARIS10)
4053 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4054
4055 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4056 } else {
4057 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4058 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4059 }
4060
4061 if (sctx->b.family == CHIP_STONEY)
4062 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4063
4064 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4065 if (sctx->b.chip_class >= CIK)
4066 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4067 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4068 RADEON_PRIO_BORDER_COLORS);
4069
4070 si_pm4_upload_indirect_buffer(sctx, pm4);
4071 sctx->init_config = pm4;
4072 }