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radeonsi: just read tile mode arrays in DB setup
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 default:
62 case RADEON_SURF_MODE_LINEAR_ALIGNED:
63 return V_009910_ARRAY_LINEAR_ALIGNED;
64 case RADEON_SURF_MODE_1D:
65 return V_009910_ARRAY_1D_TILED_THIN1;
66 case RADEON_SURF_MODE_2D:
67 return V_009910_ARRAY_2D_TILED_THIN1;
68 }
69 }
70
71 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
72 {
73 if (sscreen->b.chip_class >= CIK &&
74 sscreen->b.info.cik_macrotile_mode_array_valid) {
75 unsigned index, tileb;
76
77 tileb = 8 * 8 * tex->surface.bpe;
78 tileb = MIN2(tex->surface.tile_split, tileb);
79
80 for (index = 0; tileb > 64; index++) {
81 tileb >>= 1;
82 }
83 assert(index < 16);
84
85 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
86 }
87
88 if (sscreen->b.chip_class == SI &&
89 sscreen->b.info.si_tile_mode_array_valid) {
90 /* Don't use stencil_tiling_index, because num_banks is always
91 * read from the depth mode. */
92 unsigned tile_mode_index = tex->surface.tiling_index[0];
93 assert(tile_mode_index < 32);
94
95 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
96 }
97
98 /* The old way. */
99 switch (sscreen->b.info.r600_num_banks) {
100 case 2:
101 return V_02803C_ADDR_SURF_2_BANK;
102 case 4:
103 return V_02803C_ADDR_SURF_4_BANK;
104 case 8:
105 default:
106 return V_02803C_ADDR_SURF_8_BANK;
107 case 16:
108 return V_02803C_ADDR_SURF_16_BANK;
109 }
110 }
111
112 unsigned cik_tile_split(unsigned tile_split)
113 {
114 switch (tile_split) {
115 case 64:
116 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
117 break;
118 case 128:
119 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
120 break;
121 case 256:
122 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
123 break;
124 case 512:
125 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
126 break;
127 default:
128 case 1024:
129 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
130 break;
131 case 2048:
132 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
133 break;
134 case 4096:
135 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
136 break;
137 }
138 return tile_split;
139 }
140
141 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
142 {
143 switch (macro_tile_aspect) {
144 default:
145 case 1:
146 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
147 break;
148 case 2:
149 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
150 break;
151 case 4:
152 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
153 break;
154 case 8:
155 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
156 break;
157 }
158 return macro_tile_aspect;
159 }
160
161 unsigned cik_bank_wh(unsigned bankwh)
162 {
163 switch (bankwh) {
164 default:
165 case 1:
166 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
167 break;
168 case 2:
169 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
170 break;
171 case 4:
172 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
173 break;
174 case 8:
175 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
176 break;
177 }
178 return bankwh;
179 }
180
181 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
182 {
183 if (sscreen->b.info.si_tile_mode_array_valid) {
184 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
185
186 return G_009910_PIPE_CONFIG(gb_tile_mode);
187 }
188
189 /* This is probably broken for a lot of chips, but it's only used
190 * if the kernel cannot return the tile mode array for CIK. */
191 switch (sscreen->b.info.num_tile_pipes) {
192 case 16:
193 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
194 case 8:
195 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
196 case 4:
197 default:
198 if (sscreen->b.info.num_render_backends == 4)
199 return V_02803C_X_ADDR_SURF_P4_16X16;
200 else
201 return V_02803C_X_ADDR_SURF_P4_8X16;
202 case 2:
203 return V_02803C_ADDR_SURF_P2;
204 }
205 }
206
207 static unsigned si_map_swizzle(unsigned swizzle)
208 {
209 switch (swizzle) {
210 case PIPE_SWIZZLE_Y:
211 return V_008F0C_SQ_SEL_Y;
212 case PIPE_SWIZZLE_Z:
213 return V_008F0C_SQ_SEL_Z;
214 case PIPE_SWIZZLE_W:
215 return V_008F0C_SQ_SEL_W;
216 case PIPE_SWIZZLE_0:
217 return V_008F0C_SQ_SEL_0;
218 case PIPE_SWIZZLE_1:
219 return V_008F0C_SQ_SEL_1;
220 default: /* PIPE_SWIZZLE_X */
221 return V_008F0C_SQ_SEL_X;
222 }
223 }
224
225 static uint32_t S_FIXED(float value, uint32_t frac_bits)
226 {
227 return value * (1 << frac_bits);
228 }
229
230 /* 12.4 fixed-point */
231 static unsigned si_pack_float_12p4(float x)
232 {
233 return x <= 0 ? 0 :
234 x >= 4096 ? 0xffff : x * 16;
235 }
236
237 /*
238 * Inferred framebuffer and blender state.
239 *
240 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
241 * is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t cb_target_mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 cb_target_mask |= 0xf << (4*i);
258
259 if (blend)
260 cb_target_mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend && blend->dual_src_blend &&
269 sctx->ps_shader.cso &&
270 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
271 cb_target_mask = 0;
272
273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
274
275 /* STONEY-specific register settings. */
276 if (sctx->b.family == CHIP_STONEY) {
277 unsigned spi_shader_col_format =
278 sctx->ps_shader.cso ?
279 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
280 unsigned sx_ps_downconvert = 0;
281 unsigned sx_blend_opt_epsilon = 0;
282 unsigned sx_blend_opt_control = 0;
283
284 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
285 struct r600_surface *surf =
286 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
287 unsigned format, swap, spi_format, colormask;
288 bool has_alpha, has_rgb;
289
290 if (!surf)
291 continue;
292
293 format = G_028C70_FORMAT(surf->cb_color_info);
294 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
295 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
296 colormask = (cb_target_mask >> (i * 4)) & 0xf;
297
298 /* Set if RGB and A are present. */
299 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
300
301 if (format == V_028C70_COLOR_8 ||
302 format == V_028C70_COLOR_16 ||
303 format == V_028C70_COLOR_32)
304 has_rgb = !has_alpha;
305 else
306 has_rgb = true;
307
308 /* Check the colormask and export format. */
309 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
310 has_rgb = false;
311 if (!(colormask & PIPE_MASK_A))
312 has_alpha = false;
313
314 if (spi_format == V_028714_SPI_SHADER_ZERO) {
315 has_rgb = false;
316 has_alpha = false;
317 }
318
319 /* Disable value checking for disabled channels. */
320 if (!has_rgb)
321 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
322 if (!has_alpha)
323 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
324
325 /* Enable down-conversion for 32bpp and smaller formats. */
326 switch (format) {
327 case V_028C70_COLOR_8:
328 case V_028C70_COLOR_8_8:
329 case V_028C70_COLOR_8_8_8_8:
330 /* For 1 and 2-channel formats, use the superset thereof. */
331 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
332 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
333 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
334 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
335 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
336 }
337 break;
338
339 case V_028C70_COLOR_5_6_5:
340 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
341 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
342 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
343 }
344 break;
345
346 case V_028C70_COLOR_1_5_5_5:
347 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
348 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
349 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
350 }
351 break;
352
353 case V_028C70_COLOR_4_4_4_4:
354 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
355 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
356 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
357 }
358 break;
359
360 case V_028C70_COLOR_32:
361 if (swap == V_0280A0_SWAP_STD &&
362 spi_format == V_028714_SPI_SHADER_32_R)
363 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
364 else if (swap == V_0280A0_SWAP_ALT_REV &&
365 spi_format == V_028714_SPI_SHADER_32_AR)
366 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
367 break;
368
369 case V_028C70_COLOR_16:
370 case V_028C70_COLOR_16_16:
371 /* For 1-channel formats, use the superset thereof. */
372 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
373 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
374 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
376 if (swap == V_0280A0_SWAP_STD ||
377 swap == V_0280A0_SWAP_STD_REV)
378 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
379 else
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
381 }
382 break;
383
384 case V_028C70_COLOR_10_11_11:
385 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
386 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
387 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
388 }
389 break;
390
391 case V_028C70_COLOR_2_10_10_10:
392 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
393 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
394 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
395 }
396 break;
397 }
398 }
399
400 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
401 sx_ps_downconvert = 0;
402 sx_blend_opt_epsilon = 0;
403 sx_blend_opt_control = 0;
404 }
405
406 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
407 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
408 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
409 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
410 }
411 }
412
413 /*
414 * Blender functions
415 */
416
417 static uint32_t si_translate_blend_function(int blend_func)
418 {
419 switch (blend_func) {
420 case PIPE_BLEND_ADD:
421 return V_028780_COMB_DST_PLUS_SRC;
422 case PIPE_BLEND_SUBTRACT:
423 return V_028780_COMB_SRC_MINUS_DST;
424 case PIPE_BLEND_REVERSE_SUBTRACT:
425 return V_028780_COMB_DST_MINUS_SRC;
426 case PIPE_BLEND_MIN:
427 return V_028780_COMB_MIN_DST_SRC;
428 case PIPE_BLEND_MAX:
429 return V_028780_COMB_MAX_DST_SRC;
430 default:
431 R600_ERR("Unknown blend function %d\n", blend_func);
432 assert(0);
433 break;
434 }
435 return 0;
436 }
437
438 static uint32_t si_translate_blend_factor(int blend_fact)
439 {
440 switch (blend_fact) {
441 case PIPE_BLENDFACTOR_ONE:
442 return V_028780_BLEND_ONE;
443 case PIPE_BLENDFACTOR_SRC_COLOR:
444 return V_028780_BLEND_SRC_COLOR;
445 case PIPE_BLENDFACTOR_SRC_ALPHA:
446 return V_028780_BLEND_SRC_ALPHA;
447 case PIPE_BLENDFACTOR_DST_ALPHA:
448 return V_028780_BLEND_DST_ALPHA;
449 case PIPE_BLENDFACTOR_DST_COLOR:
450 return V_028780_BLEND_DST_COLOR;
451 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
452 return V_028780_BLEND_SRC_ALPHA_SATURATE;
453 case PIPE_BLENDFACTOR_CONST_COLOR:
454 return V_028780_BLEND_CONSTANT_COLOR;
455 case PIPE_BLENDFACTOR_CONST_ALPHA:
456 return V_028780_BLEND_CONSTANT_ALPHA;
457 case PIPE_BLENDFACTOR_ZERO:
458 return V_028780_BLEND_ZERO;
459 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
460 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
461 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
462 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
463 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_COLOR:
466 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
467 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
471 case PIPE_BLENDFACTOR_SRC1_COLOR:
472 return V_028780_BLEND_SRC1_COLOR;
473 case PIPE_BLENDFACTOR_SRC1_ALPHA:
474 return V_028780_BLEND_SRC1_ALPHA;
475 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
476 return V_028780_BLEND_INV_SRC1_COLOR;
477 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
478 return V_028780_BLEND_INV_SRC1_ALPHA;
479 default:
480 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
481 assert(0);
482 break;
483 }
484 return 0;
485 }
486
487 static uint32_t si_translate_blend_opt_function(int blend_func)
488 {
489 switch (blend_func) {
490 case PIPE_BLEND_ADD:
491 return V_028760_OPT_COMB_ADD;
492 case PIPE_BLEND_SUBTRACT:
493 return V_028760_OPT_COMB_SUBTRACT;
494 case PIPE_BLEND_REVERSE_SUBTRACT:
495 return V_028760_OPT_COMB_REVSUBTRACT;
496 case PIPE_BLEND_MIN:
497 return V_028760_OPT_COMB_MIN;
498 case PIPE_BLEND_MAX:
499 return V_028760_OPT_COMB_MAX;
500 default:
501 return V_028760_OPT_COMB_BLEND_DISABLED;
502 }
503 }
504
505 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
506 {
507 switch (blend_fact) {
508 case PIPE_BLENDFACTOR_ZERO:
509 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
510 case PIPE_BLENDFACTOR_ONE:
511 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
512 case PIPE_BLENDFACTOR_SRC_COLOR:
513 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
514 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
515 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
516 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
517 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
518 case PIPE_BLENDFACTOR_SRC_ALPHA:
519 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
520 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
522 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
523 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
524 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
525 default:
526 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
527 }
528 }
529
530 /**
531 * Get rid of DST in the blend factors by commuting the operands:
532 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
533 */
534 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
535 unsigned *dst_factor, unsigned expected_dst,
536 unsigned replacement_src)
537 {
538 if (*src_factor == expected_dst &&
539 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
540 *src_factor = PIPE_BLENDFACTOR_ZERO;
541 *dst_factor = replacement_src;
542
543 /* Commuting the operands requires reversing subtractions. */
544 if (*func == PIPE_BLEND_SUBTRACT)
545 *func = PIPE_BLEND_REVERSE_SUBTRACT;
546 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
547 *func = PIPE_BLEND_SUBTRACT;
548 }
549 }
550
551 static bool si_blend_factor_uses_dst(unsigned factor)
552 {
553 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
554 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
555 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
556 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
558 }
559
560 static void *si_create_blend_state_mode(struct pipe_context *ctx,
561 const struct pipe_blend_state *state,
562 unsigned mode)
563 {
564 struct si_context *sctx = (struct si_context*)ctx;
565 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
566 struct si_pm4_state *pm4 = &blend->pm4;
567 uint32_t sx_mrt_blend_opt[8] = {0};
568 uint32_t color_control = 0;
569
570 if (!blend)
571 return NULL;
572
573 blend->alpha_to_coverage = state->alpha_to_coverage;
574 blend->alpha_to_one = state->alpha_to_one;
575 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
576
577 if (state->logicop_enable) {
578 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
579 } else {
580 color_control |= S_028808_ROP3(0xcc);
581 }
582
583 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
584 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
585 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
586 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
587 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
589
590 if (state->alpha_to_coverage)
591 blend->need_src_alpha_4bit |= 0xf;
592
593 blend->cb_target_mask = 0;
594 for (int i = 0; i < 8; i++) {
595 /* state->rt entries > 0 only written if independent blending */
596 const int j = state->independent_blend_enable ? i : 0;
597
598 unsigned eqRGB = state->rt[j].rgb_func;
599 unsigned srcRGB = state->rt[j].rgb_src_factor;
600 unsigned dstRGB = state->rt[j].rgb_dst_factor;
601 unsigned eqA = state->rt[j].alpha_func;
602 unsigned srcA = state->rt[j].alpha_src_factor;
603 unsigned dstA = state->rt[j].alpha_dst_factor;
604
605 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
606 unsigned blend_cntl = 0;
607
608 sx_mrt_blend_opt[i] =
609 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
610 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
611
612 if (!state->rt[j].colormask)
613 continue;
614
615 /* cb_render_state will disable unused ones */
616 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
617
618 if (!state->rt[j].blend_enable) {
619 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
620 continue;
621 }
622
623 /* Blending optimizations for Stoney.
624 * These transformations don't change the behavior.
625 *
626 * First, get rid of DST in the blend factors:
627 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
628 */
629 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
630 PIPE_BLENDFACTOR_DST_COLOR,
631 PIPE_BLENDFACTOR_SRC_COLOR);
632 si_blend_remove_dst(&eqA, &srcA, &dstA,
633 PIPE_BLENDFACTOR_DST_COLOR,
634 PIPE_BLENDFACTOR_SRC_COLOR);
635 si_blend_remove_dst(&eqA, &srcA, &dstA,
636 PIPE_BLENDFACTOR_DST_ALPHA,
637 PIPE_BLENDFACTOR_SRC_ALPHA);
638
639 /* Look up the ideal settings from tables. */
640 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
641 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
642 srcA_opt = si_translate_blend_opt_factor(srcA, true);
643 dstA_opt = si_translate_blend_opt_factor(dstA, true);
644
645 /* Handle interdependencies. */
646 if (si_blend_factor_uses_dst(srcRGB))
647 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
648 if (si_blend_factor_uses_dst(srcA))
649 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650
651 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
652 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
653 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
654 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
655 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
656
657 /* Set the final value. */
658 sx_mrt_blend_opt[i] =
659 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
660 S_028760_COLOR_DST_OPT(dstRGB_opt) |
661 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
662 S_028760_ALPHA_SRC_OPT(srcA_opt) |
663 S_028760_ALPHA_DST_OPT(dstA_opt) |
664 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
665
666 /* Set blend state. */
667 blend_cntl |= S_028780_ENABLE(1);
668 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
669 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
670 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
671
672 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
673 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
674 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
675 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
676 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
677 }
678 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
679
680 blend->blend_enable_4bit |= 0xf << (i * 4);
681
682 /* This is only important for formats without alpha. */
683 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
684 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
685 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
687 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
688 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
689 blend->need_src_alpha_4bit |= 0xf << (i * 4);
690 }
691
692 if (blend->cb_target_mask) {
693 color_control |= S_028808_MODE(mode);
694 } else {
695 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
696 }
697
698 if (sctx->b.family == CHIP_STONEY) {
699 for (int i = 0; i < 8; i++)
700 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
701 sx_mrt_blend_opt[i]);
702
703 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
704 if (blend->dual_src_blend || state->logicop_enable ||
705 mode == V_028808_CB_RESOLVE)
706 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
707 }
708
709 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
710 return blend;
711 }
712
713 static void *si_create_blend_state(struct pipe_context *ctx,
714 const struct pipe_blend_state *state)
715 {
716 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
717 }
718
719 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
720 {
721 struct si_context *sctx = (struct si_context *)ctx;
722 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
723 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
724 }
725
726 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
727 {
728 struct si_context *sctx = (struct si_context *)ctx;
729 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
730 }
731
732 static void si_set_blend_color(struct pipe_context *ctx,
733 const struct pipe_blend_color *state)
734 {
735 struct si_context *sctx = (struct si_context *)ctx;
736
737 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
738 return;
739
740 sctx->blend_color.state = *state;
741 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
742 }
743
744 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
745 {
746 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
747
748 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
749 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
750 }
751
752 /*
753 * Clipping
754 */
755
756 static void si_set_clip_state(struct pipe_context *ctx,
757 const struct pipe_clip_state *state)
758 {
759 struct si_context *sctx = (struct si_context *)ctx;
760 struct pipe_constant_buffer cb;
761
762 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
763 return;
764
765 sctx->clip_state.state = *state;
766 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
767
768 cb.buffer = NULL;
769 cb.user_buffer = state->ucp;
770 cb.buffer_offset = 0;
771 cb.buffer_size = 4*4*8;
772 si_set_constant_buffer(sctx, &sctx->rw_buffers,
773 SI_VS_CONST_CLIP_PLANES, &cb);
774 pipe_resource_reference(&cb.buffer, NULL);
775 }
776
777 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
778 {
779 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
780
781 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
782 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
783 }
784
785 #define SIX_BITS 0x3F
786
787 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
788 {
789 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
790 struct tgsi_shader_info *info = si_get_vs_info(sctx);
791 unsigned window_space =
792 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
793 unsigned clipdist_mask =
794 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
795
796 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
797 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
798 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
799 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
800 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
801 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
802 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
803 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
804 info->writes_edgeflag ||
805 info->writes_layer ||
806 info->writes_viewport_index) |
807 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
808 (sctx->queued.named.rasterizer->clip_plane_enable &
809 clipdist_mask));
810 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
811 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
812 (clipdist_mask ? 0 :
813 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
814 S_028810_CLIP_DISABLE(window_space));
815
816 /* reuse needs to be set off if we write oViewport */
817 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
818 S_028AB4_REUSE_OFF(info->writes_viewport_index));
819 }
820
821 /*
822 * inferred state between framebuffer and rasterizer
823 */
824 static void si_update_poly_offset_state(struct si_context *sctx)
825 {
826 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
827
828 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
829 return;
830
831 switch (sctx->framebuffer.state.zsbuf->texture->format) {
832 case PIPE_FORMAT_Z16_UNORM:
833 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
834 break;
835 default: /* 24-bit */
836 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
837 break;
838 case PIPE_FORMAT_Z32_FLOAT:
839 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
840 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
841 break;
842 }
843 }
844
845 /*
846 * Rasterizer
847 */
848
849 static uint32_t si_translate_fill(uint32_t func)
850 {
851 switch(func) {
852 case PIPE_POLYGON_MODE_FILL:
853 return V_028814_X_DRAW_TRIANGLES;
854 case PIPE_POLYGON_MODE_LINE:
855 return V_028814_X_DRAW_LINES;
856 case PIPE_POLYGON_MODE_POINT:
857 return V_028814_X_DRAW_POINTS;
858 default:
859 assert(0);
860 return V_028814_X_DRAW_POINTS;
861 }
862 }
863
864 static void *si_create_rs_state(struct pipe_context *ctx,
865 const struct pipe_rasterizer_state *state)
866 {
867 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
868 struct si_pm4_state *pm4 = &rs->pm4;
869 unsigned tmp, i;
870 float psize_min, psize_max;
871
872 if (!rs) {
873 return NULL;
874 }
875
876 rs->scissor_enable = state->scissor;
877 rs->two_side = state->light_twoside;
878 rs->multisample_enable = state->multisample;
879 rs->force_persample_interp = state->force_persample_interp;
880 rs->clip_plane_enable = state->clip_plane_enable;
881 rs->line_stipple_enable = state->line_stipple_enable;
882 rs->poly_stipple_enable = state->poly_stipple_enable;
883 rs->line_smooth = state->line_smooth;
884 rs->poly_smooth = state->poly_smooth;
885 rs->uses_poly_offset = state->offset_point || state->offset_line ||
886 state->offset_tri;
887 rs->clamp_fragment_color = state->clamp_fragment_color;
888 rs->flatshade = state->flatshade;
889 rs->sprite_coord_enable = state->sprite_coord_enable;
890 rs->rasterizer_discard = state->rasterizer_discard;
891 rs->pa_sc_line_stipple = state->line_stipple_enable ?
892 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
893 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
894 rs->pa_cl_clip_cntl =
895 S_028810_PS_UCP_MODE(3) |
896 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
897 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
898 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
899 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
900 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
901
902 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
903 S_0286D4_FLAT_SHADE_ENA(1) |
904 S_0286D4_PNT_SPRITE_ENA(1) |
905 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
906 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
907 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
908 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
909 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
910
911 /* point size 12.4 fixed point */
912 tmp = (unsigned)(state->point_size * 8.0);
913 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
914
915 if (state->point_size_per_vertex) {
916 psize_min = util_get_min_point_size(state);
917 psize_max = 8192;
918 } else {
919 /* Force the point size to be as if the vertex output was disabled. */
920 psize_min = state->point_size;
921 psize_max = state->point_size;
922 }
923 /* Divide by two, because 0.5 = 1 pixel. */
924 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
925 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
926 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
927
928 tmp = (unsigned)state->line_width * 8;
929 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
930 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
931 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
932 S_028A48_MSAA_ENABLE(state->multisample ||
933 state->poly_smooth ||
934 state->line_smooth) |
935 S_028A48_VPORT_SCISSOR_ENABLE(1));
936
937 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
938 S_028BE4_PIX_CENTER(state->half_pixel_center) |
939 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
940
941 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
942 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
943 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
944 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
945 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
946 S_028814_FACE(!state->front_ccw) |
947 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
948 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
949 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
950 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
951 state->fill_back != PIPE_POLYGON_MODE_FILL) |
952 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
953 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
954 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
955 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
956
957 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
958 for (i = 0; i < 3; i++) {
959 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
960 float offset_units = state->offset_units;
961 float offset_scale = state->offset_scale * 16.0f;
962
963 switch (i) {
964 case 0: /* 16-bit zbuffer */
965 offset_units *= 4.0f;
966 break;
967 case 1: /* 24-bit zbuffer */
968 offset_units *= 2.0f;
969 break;
970 case 2: /* 32-bit zbuffer */
971 offset_units *= 1.0f;
972 break;
973 }
974
975 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
976 fui(offset_scale));
977 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
978 fui(offset_units));
979 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
980 fui(offset_scale));
981 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
982 fui(offset_units));
983 }
984
985 return rs;
986 }
987
988 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
989 {
990 struct si_context *sctx = (struct si_context *)ctx;
991 struct si_state_rasterizer *old_rs =
992 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
993 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
994
995 if (!state)
996 return;
997
998 if (sctx->framebuffer.nr_samples > 1 &&
999 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1000 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1001
1002 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
1003
1004 si_pm4_bind_state(sctx, rasterizer, rs);
1005 si_update_poly_offset_state(sctx);
1006
1007 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1008 }
1009
1010 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1011 {
1012 struct si_context *sctx = (struct si_context *)ctx;
1013
1014 if (sctx->queued.named.rasterizer == state)
1015 si_pm4_bind_state(sctx, poly_offset, NULL);
1016 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1017 }
1018
1019 /*
1020 * infeered state between dsa and stencil ref
1021 */
1022 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1023 {
1024 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1025 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1026 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1027
1028 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1029 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1030 S_028430_STENCILMASK(dsa->valuemask[0]) |
1031 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1032 S_028430_STENCILOPVAL(1));
1033 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1034 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1035 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1036 S_028434_STENCILOPVAL_BF(1));
1037 }
1038
1039 static void si_set_stencil_ref(struct pipe_context *ctx,
1040 const struct pipe_stencil_ref *state)
1041 {
1042 struct si_context *sctx = (struct si_context *)ctx;
1043
1044 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1045 return;
1046
1047 sctx->stencil_ref.state = *state;
1048 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1049 }
1050
1051
1052 /*
1053 * DSA
1054 */
1055
1056 static uint32_t si_translate_stencil_op(int s_op)
1057 {
1058 switch (s_op) {
1059 case PIPE_STENCIL_OP_KEEP:
1060 return V_02842C_STENCIL_KEEP;
1061 case PIPE_STENCIL_OP_ZERO:
1062 return V_02842C_STENCIL_ZERO;
1063 case PIPE_STENCIL_OP_REPLACE:
1064 return V_02842C_STENCIL_REPLACE_TEST;
1065 case PIPE_STENCIL_OP_INCR:
1066 return V_02842C_STENCIL_ADD_CLAMP;
1067 case PIPE_STENCIL_OP_DECR:
1068 return V_02842C_STENCIL_SUB_CLAMP;
1069 case PIPE_STENCIL_OP_INCR_WRAP:
1070 return V_02842C_STENCIL_ADD_WRAP;
1071 case PIPE_STENCIL_OP_DECR_WRAP:
1072 return V_02842C_STENCIL_SUB_WRAP;
1073 case PIPE_STENCIL_OP_INVERT:
1074 return V_02842C_STENCIL_INVERT;
1075 default:
1076 R600_ERR("Unknown stencil op %d", s_op);
1077 assert(0);
1078 break;
1079 }
1080 return 0;
1081 }
1082
1083 static void *si_create_dsa_state(struct pipe_context *ctx,
1084 const struct pipe_depth_stencil_alpha_state *state)
1085 {
1086 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1087 struct si_pm4_state *pm4 = &dsa->pm4;
1088 unsigned db_depth_control;
1089 uint32_t db_stencil_control = 0;
1090
1091 if (!dsa) {
1092 return NULL;
1093 }
1094
1095 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1096 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1097 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1098 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1099
1100 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1101 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1102 S_028800_ZFUNC(state->depth.func) |
1103 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1104
1105 /* stencil */
1106 if (state->stencil[0].enabled) {
1107 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1108 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1109 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1110 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1111 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1112
1113 if (state->stencil[1].enabled) {
1114 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1115 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1116 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1117 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1118 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1119 }
1120 }
1121
1122 /* alpha */
1123 if (state->alpha.enabled) {
1124 dsa->alpha_func = state->alpha.func;
1125
1126 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1127 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1128 } else {
1129 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1130 }
1131
1132 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1133 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1134 if (state->depth.bounds_test) {
1135 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1136 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1137 }
1138
1139 return dsa;
1140 }
1141
1142 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1143 {
1144 struct si_context *sctx = (struct si_context *)ctx;
1145 struct si_state_dsa *dsa = state;
1146
1147 if (!state)
1148 return;
1149
1150 si_pm4_bind_state(sctx, dsa, dsa);
1151
1152 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1153 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1154 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1155 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1156 }
1157 }
1158
1159 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1160 {
1161 struct si_context *sctx = (struct si_context *)ctx;
1162 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1163 }
1164
1165 static void *si_create_db_flush_dsa(struct si_context *sctx)
1166 {
1167 struct pipe_depth_stencil_alpha_state dsa = {};
1168
1169 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1170 }
1171
1172 /* DB RENDER STATE */
1173
1174 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1175 {
1176 struct si_context *sctx = (struct si_context*)ctx;
1177
1178 /* Pipeline stat & streamout queries. */
1179 if (enable) {
1180 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1181 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1182 } else {
1183 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1184 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1185 }
1186
1187 /* Occlusion queries. */
1188 if (sctx->occlusion_queries_disabled != !enable) {
1189 sctx->occlusion_queries_disabled = !enable;
1190 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1191 }
1192 }
1193
1194 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1195 {
1196 struct si_context *sctx = (struct si_context*)ctx;
1197
1198 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1199 }
1200
1201 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1202 {
1203 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1204 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1205 unsigned db_shader_control;
1206
1207 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1208
1209 /* DB_RENDER_CONTROL */
1210 if (sctx->dbcb_depth_copy_enabled ||
1211 sctx->dbcb_stencil_copy_enabled) {
1212 radeon_emit(cs,
1213 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1214 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1215 S_028000_COPY_CENTROID(1) |
1216 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1217 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1218 radeon_emit(cs,
1219 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1220 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1221 } else {
1222 radeon_emit(cs,
1223 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1224 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1225 }
1226
1227 /* DB_COUNT_CONTROL (occlusion queries) */
1228 if (sctx->b.num_occlusion_queries > 0 &&
1229 !sctx->occlusion_queries_disabled) {
1230 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1231
1232 if (sctx->b.chip_class >= CIK) {
1233 radeon_emit(cs,
1234 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1235 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1236 S_028004_ZPASS_ENABLE(1) |
1237 S_028004_SLICE_EVEN_ENABLE(1) |
1238 S_028004_SLICE_ODD_ENABLE(1));
1239 } else {
1240 radeon_emit(cs,
1241 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1242 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1243 }
1244 } else {
1245 /* Disable occlusion queries. */
1246 if (sctx->b.chip_class >= CIK) {
1247 radeon_emit(cs, 0);
1248 } else {
1249 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1250 }
1251 }
1252
1253 /* DB_RENDER_OVERRIDE2 */
1254 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1255 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1256 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1257
1258 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1259 sctx->ps_db_shader_control;
1260
1261 /* Bug workaround for smoothing (overrasterization) on SI. */
1262 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1263 db_shader_control &= C_02880C_Z_ORDER;
1264 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1265 }
1266
1267 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1268 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1269 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1270
1271 if (sctx->b.family == CHIP_STONEY &&
1272 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1273 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1274
1275 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1276 db_shader_control);
1277 }
1278
1279 /*
1280 * format translation
1281 */
1282 static uint32_t si_translate_colorformat(enum pipe_format format)
1283 {
1284 const struct util_format_description *desc = util_format_description(format);
1285
1286 #define HAS_SIZE(x,y,z,w) \
1287 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1288 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1289
1290 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1291 return V_028C70_COLOR_10_11_11;
1292
1293 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1294 return V_028C70_COLOR_INVALID;
1295
1296 switch (desc->nr_channels) {
1297 case 1:
1298 switch (desc->channel[0].size) {
1299 case 8:
1300 return V_028C70_COLOR_8;
1301 case 16:
1302 return V_028C70_COLOR_16;
1303 case 32:
1304 return V_028C70_COLOR_32;
1305 }
1306 break;
1307 case 2:
1308 if (desc->channel[0].size == desc->channel[1].size) {
1309 switch (desc->channel[0].size) {
1310 case 8:
1311 return V_028C70_COLOR_8_8;
1312 case 16:
1313 return V_028C70_COLOR_16_16;
1314 case 32:
1315 return V_028C70_COLOR_32_32;
1316 }
1317 } else if (HAS_SIZE(8,24,0,0)) {
1318 return V_028C70_COLOR_24_8;
1319 } else if (HAS_SIZE(24,8,0,0)) {
1320 return V_028C70_COLOR_8_24;
1321 }
1322 break;
1323 case 3:
1324 if (HAS_SIZE(5,6,5,0)) {
1325 return V_028C70_COLOR_5_6_5;
1326 } else if (HAS_SIZE(32,8,24,0)) {
1327 return V_028C70_COLOR_X24_8_32_FLOAT;
1328 }
1329 break;
1330 case 4:
1331 if (desc->channel[0].size == desc->channel[1].size &&
1332 desc->channel[0].size == desc->channel[2].size &&
1333 desc->channel[0].size == desc->channel[3].size) {
1334 switch (desc->channel[0].size) {
1335 case 4:
1336 return V_028C70_COLOR_4_4_4_4;
1337 case 8:
1338 return V_028C70_COLOR_8_8_8_8;
1339 case 16:
1340 return V_028C70_COLOR_16_16_16_16;
1341 case 32:
1342 return V_028C70_COLOR_32_32_32_32;
1343 }
1344 } else if (HAS_SIZE(5,5,5,1)) {
1345 return V_028C70_COLOR_1_5_5_5;
1346 } else if (HAS_SIZE(10,10,10,2)) {
1347 return V_028C70_COLOR_2_10_10_10;
1348 }
1349 break;
1350 }
1351 return V_028C70_COLOR_INVALID;
1352 }
1353
1354 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1355 {
1356 if (SI_BIG_ENDIAN) {
1357 switch(colorformat) {
1358 /* 8-bit buffers. */
1359 case V_028C70_COLOR_8:
1360 return V_028C70_ENDIAN_NONE;
1361
1362 /* 16-bit buffers. */
1363 case V_028C70_COLOR_5_6_5:
1364 case V_028C70_COLOR_1_5_5_5:
1365 case V_028C70_COLOR_4_4_4_4:
1366 case V_028C70_COLOR_16:
1367 case V_028C70_COLOR_8_8:
1368 return V_028C70_ENDIAN_8IN16;
1369
1370 /* 32-bit buffers. */
1371 case V_028C70_COLOR_8_8_8_8:
1372 case V_028C70_COLOR_2_10_10_10:
1373 case V_028C70_COLOR_8_24:
1374 case V_028C70_COLOR_24_8:
1375 case V_028C70_COLOR_16_16:
1376 return V_028C70_ENDIAN_8IN32;
1377
1378 /* 64-bit buffers. */
1379 case V_028C70_COLOR_16_16_16_16:
1380 return V_028C70_ENDIAN_8IN16;
1381
1382 case V_028C70_COLOR_32_32:
1383 return V_028C70_ENDIAN_8IN32;
1384
1385 /* 128-bit buffers. */
1386 case V_028C70_COLOR_32_32_32_32:
1387 return V_028C70_ENDIAN_8IN32;
1388 default:
1389 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1390 }
1391 } else {
1392 return V_028C70_ENDIAN_NONE;
1393 }
1394 }
1395
1396 static uint32_t si_translate_dbformat(enum pipe_format format)
1397 {
1398 switch (format) {
1399 case PIPE_FORMAT_Z16_UNORM:
1400 return V_028040_Z_16;
1401 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1402 case PIPE_FORMAT_X8Z24_UNORM:
1403 case PIPE_FORMAT_Z24X8_UNORM:
1404 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1405 return V_028040_Z_24; /* deprecated on SI */
1406 case PIPE_FORMAT_Z32_FLOAT:
1407 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1408 return V_028040_Z_32_FLOAT;
1409 default:
1410 return V_028040_Z_INVALID;
1411 }
1412 }
1413
1414 /*
1415 * Texture translation
1416 */
1417
1418 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1419 enum pipe_format format,
1420 const struct util_format_description *desc,
1421 int first_non_void)
1422 {
1423 struct si_screen *sscreen = (struct si_screen*)screen;
1424 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1425 sscreen->b.info.drm_minor >= 31) ||
1426 sscreen->b.info.drm_major == 3;
1427 boolean uniform = TRUE;
1428 int i;
1429
1430 /* Colorspace (return non-RGB formats directly). */
1431 switch (desc->colorspace) {
1432 /* Depth stencil formats */
1433 case UTIL_FORMAT_COLORSPACE_ZS:
1434 switch (format) {
1435 case PIPE_FORMAT_Z16_UNORM:
1436 return V_008F14_IMG_DATA_FORMAT_16;
1437 case PIPE_FORMAT_X24S8_UINT:
1438 case PIPE_FORMAT_Z24X8_UNORM:
1439 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1440 return V_008F14_IMG_DATA_FORMAT_8_24;
1441 case PIPE_FORMAT_X8Z24_UNORM:
1442 case PIPE_FORMAT_S8X24_UINT:
1443 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1444 return V_008F14_IMG_DATA_FORMAT_24_8;
1445 case PIPE_FORMAT_S8_UINT:
1446 return V_008F14_IMG_DATA_FORMAT_8;
1447 case PIPE_FORMAT_Z32_FLOAT:
1448 return V_008F14_IMG_DATA_FORMAT_32;
1449 case PIPE_FORMAT_X32_S8X24_UINT:
1450 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1451 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1452 default:
1453 goto out_unknown;
1454 }
1455
1456 case UTIL_FORMAT_COLORSPACE_YUV:
1457 goto out_unknown; /* TODO */
1458
1459 case UTIL_FORMAT_COLORSPACE_SRGB:
1460 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1461 goto out_unknown;
1462 break;
1463
1464 default:
1465 break;
1466 }
1467
1468 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1469 if (!enable_compressed_formats)
1470 goto out_unknown;
1471
1472 switch (format) {
1473 case PIPE_FORMAT_RGTC1_SNORM:
1474 case PIPE_FORMAT_LATC1_SNORM:
1475 case PIPE_FORMAT_RGTC1_UNORM:
1476 case PIPE_FORMAT_LATC1_UNORM:
1477 return V_008F14_IMG_DATA_FORMAT_BC4;
1478 case PIPE_FORMAT_RGTC2_SNORM:
1479 case PIPE_FORMAT_LATC2_SNORM:
1480 case PIPE_FORMAT_RGTC2_UNORM:
1481 case PIPE_FORMAT_LATC2_UNORM:
1482 return V_008F14_IMG_DATA_FORMAT_BC5;
1483 default:
1484 goto out_unknown;
1485 }
1486 }
1487
1488 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1489 sscreen->b.family == CHIP_STONEY) {
1490 switch (format) {
1491 case PIPE_FORMAT_ETC1_RGB8:
1492 case PIPE_FORMAT_ETC2_RGB8:
1493 case PIPE_FORMAT_ETC2_SRGB8:
1494 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1495 case PIPE_FORMAT_ETC2_RGB8A1:
1496 case PIPE_FORMAT_ETC2_SRGB8A1:
1497 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1498 case PIPE_FORMAT_ETC2_RGBA8:
1499 case PIPE_FORMAT_ETC2_SRGBA8:
1500 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1501 case PIPE_FORMAT_ETC2_R11_UNORM:
1502 case PIPE_FORMAT_ETC2_R11_SNORM:
1503 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1504 case PIPE_FORMAT_ETC2_RG11_UNORM:
1505 case PIPE_FORMAT_ETC2_RG11_SNORM:
1506 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1507 default:
1508 goto out_unknown;
1509 }
1510 }
1511
1512 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1513 if (!enable_compressed_formats)
1514 goto out_unknown;
1515
1516 switch (format) {
1517 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1518 case PIPE_FORMAT_BPTC_SRGBA:
1519 return V_008F14_IMG_DATA_FORMAT_BC7;
1520 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1521 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1522 return V_008F14_IMG_DATA_FORMAT_BC6;
1523 default:
1524 goto out_unknown;
1525 }
1526 }
1527
1528 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1529 switch (format) {
1530 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1531 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1532 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1533 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1534 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1535 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1536 default:
1537 goto out_unknown;
1538 }
1539 }
1540
1541 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1542 if (!enable_compressed_formats)
1543 goto out_unknown;
1544
1545 if (!util_format_s3tc_enabled) {
1546 goto out_unknown;
1547 }
1548
1549 switch (format) {
1550 case PIPE_FORMAT_DXT1_RGB:
1551 case PIPE_FORMAT_DXT1_RGBA:
1552 case PIPE_FORMAT_DXT1_SRGB:
1553 case PIPE_FORMAT_DXT1_SRGBA:
1554 return V_008F14_IMG_DATA_FORMAT_BC1;
1555 case PIPE_FORMAT_DXT3_RGBA:
1556 case PIPE_FORMAT_DXT3_SRGBA:
1557 return V_008F14_IMG_DATA_FORMAT_BC2;
1558 case PIPE_FORMAT_DXT5_RGBA:
1559 case PIPE_FORMAT_DXT5_SRGBA:
1560 return V_008F14_IMG_DATA_FORMAT_BC3;
1561 default:
1562 goto out_unknown;
1563 }
1564 }
1565
1566 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1567 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1568 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1569 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1570 }
1571
1572 /* R8G8Bx_SNORM - TODO CxV8U8 */
1573
1574 /* See whether the components are of the same size. */
1575 for (i = 1; i < desc->nr_channels; i++) {
1576 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1577 }
1578
1579 /* Non-uniform formats. */
1580 if (!uniform) {
1581 switch(desc->nr_channels) {
1582 case 3:
1583 if (desc->channel[0].size == 5 &&
1584 desc->channel[1].size == 6 &&
1585 desc->channel[2].size == 5) {
1586 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1587 }
1588 goto out_unknown;
1589 case 4:
1590 if (desc->channel[0].size == 5 &&
1591 desc->channel[1].size == 5 &&
1592 desc->channel[2].size == 5 &&
1593 desc->channel[3].size == 1) {
1594 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1595 }
1596 if (desc->channel[0].size == 10 &&
1597 desc->channel[1].size == 10 &&
1598 desc->channel[2].size == 10 &&
1599 desc->channel[3].size == 2) {
1600 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1601 }
1602 goto out_unknown;
1603 }
1604 goto out_unknown;
1605 }
1606
1607 if (first_non_void < 0 || first_non_void > 3)
1608 goto out_unknown;
1609
1610 /* uniform formats */
1611 switch (desc->channel[first_non_void].size) {
1612 case 4:
1613 switch (desc->nr_channels) {
1614 #if 0 /* Not supported for render targets */
1615 case 2:
1616 return V_008F14_IMG_DATA_FORMAT_4_4;
1617 #endif
1618 case 4:
1619 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1620 }
1621 break;
1622 case 8:
1623 switch (desc->nr_channels) {
1624 case 1:
1625 return V_008F14_IMG_DATA_FORMAT_8;
1626 case 2:
1627 return V_008F14_IMG_DATA_FORMAT_8_8;
1628 case 4:
1629 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1630 }
1631 break;
1632 case 16:
1633 switch (desc->nr_channels) {
1634 case 1:
1635 return V_008F14_IMG_DATA_FORMAT_16;
1636 case 2:
1637 return V_008F14_IMG_DATA_FORMAT_16_16;
1638 case 4:
1639 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1640 }
1641 break;
1642 case 32:
1643 switch (desc->nr_channels) {
1644 case 1:
1645 return V_008F14_IMG_DATA_FORMAT_32;
1646 case 2:
1647 return V_008F14_IMG_DATA_FORMAT_32_32;
1648 #if 0 /* Not supported for render targets */
1649 case 3:
1650 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1651 #endif
1652 case 4:
1653 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1654 }
1655 }
1656
1657 out_unknown:
1658 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1659 return ~0;
1660 }
1661
1662 static unsigned si_tex_wrap(unsigned wrap)
1663 {
1664 switch (wrap) {
1665 default:
1666 case PIPE_TEX_WRAP_REPEAT:
1667 return V_008F30_SQ_TEX_WRAP;
1668 case PIPE_TEX_WRAP_CLAMP:
1669 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1670 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1671 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1672 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1673 return V_008F30_SQ_TEX_CLAMP_BORDER;
1674 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1675 return V_008F30_SQ_TEX_MIRROR;
1676 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1677 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1678 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1679 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1680 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1681 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1682 }
1683 }
1684
1685 static unsigned si_tex_mipfilter(unsigned filter)
1686 {
1687 switch (filter) {
1688 case PIPE_TEX_MIPFILTER_NEAREST:
1689 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1690 case PIPE_TEX_MIPFILTER_LINEAR:
1691 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1692 default:
1693 case PIPE_TEX_MIPFILTER_NONE:
1694 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1695 }
1696 }
1697
1698 static unsigned si_tex_compare(unsigned compare)
1699 {
1700 switch (compare) {
1701 default:
1702 case PIPE_FUNC_NEVER:
1703 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1704 case PIPE_FUNC_LESS:
1705 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1706 case PIPE_FUNC_EQUAL:
1707 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1708 case PIPE_FUNC_LEQUAL:
1709 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1710 case PIPE_FUNC_GREATER:
1711 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1712 case PIPE_FUNC_NOTEQUAL:
1713 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1714 case PIPE_FUNC_GEQUAL:
1715 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1716 case PIPE_FUNC_ALWAYS:
1717 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1718 }
1719 }
1720
1721 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1722 unsigned nr_samples)
1723 {
1724 if (view_target == PIPE_TEXTURE_CUBE ||
1725 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1726 res_target = view_target;
1727
1728 switch (res_target) {
1729 default:
1730 case PIPE_TEXTURE_1D:
1731 return V_008F1C_SQ_RSRC_IMG_1D;
1732 case PIPE_TEXTURE_1D_ARRAY:
1733 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1734 case PIPE_TEXTURE_2D:
1735 case PIPE_TEXTURE_RECT:
1736 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1737 V_008F1C_SQ_RSRC_IMG_2D;
1738 case PIPE_TEXTURE_2D_ARRAY:
1739 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1740 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1741 case PIPE_TEXTURE_3D:
1742 return V_008F1C_SQ_RSRC_IMG_3D;
1743 case PIPE_TEXTURE_CUBE:
1744 case PIPE_TEXTURE_CUBE_ARRAY:
1745 return V_008F1C_SQ_RSRC_IMG_CUBE;
1746 }
1747 }
1748
1749 /*
1750 * Format support testing
1751 */
1752
1753 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1754 {
1755 return si_translate_texformat(screen, format, util_format_description(format),
1756 util_format_get_first_non_void_channel(format)) != ~0U;
1757 }
1758
1759 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1760 const struct util_format_description *desc,
1761 int first_non_void)
1762 {
1763 unsigned type;
1764 int i;
1765
1766 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1767 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1768
1769 assert(first_non_void >= 0);
1770 type = desc->channel[first_non_void].type;
1771
1772 if (type == UTIL_FORMAT_TYPE_FIXED)
1773 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1774
1775 if (desc->nr_channels == 4 &&
1776 desc->channel[0].size == 10 &&
1777 desc->channel[1].size == 10 &&
1778 desc->channel[2].size == 10 &&
1779 desc->channel[3].size == 2)
1780 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1781
1782 /* See whether the components are of the same size. */
1783 for (i = 0; i < desc->nr_channels; i++) {
1784 if (desc->channel[first_non_void].size != desc->channel[i].size)
1785 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1786 }
1787
1788 switch (desc->channel[first_non_void].size) {
1789 case 8:
1790 switch (desc->nr_channels) {
1791 case 1:
1792 return V_008F0C_BUF_DATA_FORMAT_8;
1793 case 2:
1794 return V_008F0C_BUF_DATA_FORMAT_8_8;
1795 case 3:
1796 case 4:
1797 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1798 }
1799 break;
1800 case 16:
1801 switch (desc->nr_channels) {
1802 case 1:
1803 return V_008F0C_BUF_DATA_FORMAT_16;
1804 case 2:
1805 return V_008F0C_BUF_DATA_FORMAT_16_16;
1806 case 3:
1807 case 4:
1808 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1809 }
1810 break;
1811 case 32:
1812 /* From the Southern Islands ISA documentation about MTBUF:
1813 * 'Memory reads of data in memory that is 32 or 64 bits do not
1814 * undergo any format conversion.'
1815 */
1816 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1817 !desc->channel[first_non_void].pure_integer)
1818 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1819
1820 switch (desc->nr_channels) {
1821 case 1:
1822 return V_008F0C_BUF_DATA_FORMAT_32;
1823 case 2:
1824 return V_008F0C_BUF_DATA_FORMAT_32_32;
1825 case 3:
1826 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1827 case 4:
1828 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1829 }
1830 break;
1831 }
1832
1833 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1834 }
1835
1836 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1837 const struct util_format_description *desc,
1838 int first_non_void)
1839 {
1840 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1841 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1842
1843 assert(first_non_void >= 0);
1844
1845 switch (desc->channel[first_non_void].type) {
1846 case UTIL_FORMAT_TYPE_SIGNED:
1847 if (desc->channel[first_non_void].normalized)
1848 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1849 else if (desc->channel[first_non_void].pure_integer)
1850 return V_008F0C_BUF_NUM_FORMAT_SINT;
1851 else
1852 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1853 break;
1854 case UTIL_FORMAT_TYPE_UNSIGNED:
1855 if (desc->channel[first_non_void].normalized)
1856 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1857 else if (desc->channel[first_non_void].pure_integer)
1858 return V_008F0C_BUF_NUM_FORMAT_UINT;
1859 else
1860 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1861 break;
1862 case UTIL_FORMAT_TYPE_FLOAT:
1863 default:
1864 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1865 }
1866 }
1867
1868 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1869 {
1870 const struct util_format_description *desc;
1871 int first_non_void;
1872 unsigned data_format;
1873
1874 desc = util_format_description(format);
1875 first_non_void = util_format_get_first_non_void_channel(format);
1876 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1877 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1878 }
1879
1880 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1881 {
1882 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1883 r600_translate_colorswap(format, FALSE) != ~0U;
1884 }
1885
1886 static bool si_is_zs_format_supported(enum pipe_format format)
1887 {
1888 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1889 }
1890
1891 boolean si_is_format_supported(struct pipe_screen *screen,
1892 enum pipe_format format,
1893 enum pipe_texture_target target,
1894 unsigned sample_count,
1895 unsigned usage)
1896 {
1897 unsigned retval = 0;
1898
1899 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1900 R600_ERR("r600: unsupported texture type %d\n", target);
1901 return FALSE;
1902 }
1903
1904 if (!util_format_is_supported(format, usage))
1905 return FALSE;
1906
1907 if (sample_count > 1) {
1908 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1909 return FALSE;
1910
1911 switch (sample_count) {
1912 case 2:
1913 case 4:
1914 case 8:
1915 break;
1916 case 16:
1917 if (format == PIPE_FORMAT_NONE)
1918 return TRUE;
1919 else
1920 return FALSE;
1921 default:
1922 return FALSE;
1923 }
1924 }
1925
1926 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1927 if (target == PIPE_BUFFER) {
1928 if (si_is_vertex_format_supported(screen, format))
1929 retval |= PIPE_BIND_SAMPLER_VIEW;
1930 } else {
1931 if (si_is_sampler_format_supported(screen, format))
1932 retval |= PIPE_BIND_SAMPLER_VIEW;
1933 }
1934 }
1935
1936 if ((usage & (PIPE_BIND_RENDER_TARGET |
1937 PIPE_BIND_DISPLAY_TARGET |
1938 PIPE_BIND_SCANOUT |
1939 PIPE_BIND_SHARED |
1940 PIPE_BIND_BLENDABLE)) &&
1941 si_is_colorbuffer_format_supported(format)) {
1942 retval |= usage &
1943 (PIPE_BIND_RENDER_TARGET |
1944 PIPE_BIND_DISPLAY_TARGET |
1945 PIPE_BIND_SCANOUT |
1946 PIPE_BIND_SHARED);
1947 if (!util_format_is_pure_integer(format) &&
1948 !util_format_is_depth_or_stencil(format))
1949 retval |= usage & PIPE_BIND_BLENDABLE;
1950 }
1951
1952 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1953 si_is_zs_format_supported(format)) {
1954 retval |= PIPE_BIND_DEPTH_STENCIL;
1955 }
1956
1957 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1958 si_is_vertex_format_supported(screen, format)) {
1959 retval |= PIPE_BIND_VERTEX_BUFFER;
1960 }
1961
1962 if (usage & PIPE_BIND_TRANSFER_READ)
1963 retval |= PIPE_BIND_TRANSFER_READ;
1964 if (usage & PIPE_BIND_TRANSFER_WRITE)
1965 retval |= PIPE_BIND_TRANSFER_WRITE;
1966
1967 if ((usage & PIPE_BIND_LINEAR) &&
1968 !util_format_is_compressed(format) &&
1969 !(usage & PIPE_BIND_DEPTH_STENCIL))
1970 retval |= PIPE_BIND_LINEAR;
1971
1972 return retval == usage;
1973 }
1974
1975 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1976 {
1977 unsigned tile_mode_index = 0;
1978
1979 if (stencil) {
1980 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1981 } else {
1982 tile_mode_index = rtex->surface.tiling_index[level];
1983 }
1984 return tile_mode_index;
1985 }
1986
1987 /*
1988 * framebuffer handling
1989 */
1990
1991 static void si_choose_spi_color_formats(struct r600_surface *surf,
1992 unsigned format, unsigned swap,
1993 unsigned ntype, bool is_depth)
1994 {
1995 /* Alpha is needed for alpha-to-coverage.
1996 * Blending may be with or without alpha.
1997 */
1998 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1999 unsigned alpha = 0; /* exports alpha, but may not support blending */
2000 unsigned blend = 0; /* supports blending, but may not export alpha */
2001 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2002
2003 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2004 * Other chips have multiple choices, though they are not necessarily better.
2005 */
2006 switch (format) {
2007 case V_028C70_COLOR_5_6_5:
2008 case V_028C70_COLOR_1_5_5_5:
2009 case V_028C70_COLOR_5_5_5_1:
2010 case V_028C70_COLOR_4_4_4_4:
2011 case V_028C70_COLOR_10_11_11:
2012 case V_028C70_COLOR_11_11_10:
2013 case V_028C70_COLOR_8:
2014 case V_028C70_COLOR_8_8:
2015 case V_028C70_COLOR_8_8_8_8:
2016 case V_028C70_COLOR_10_10_10_2:
2017 case V_028C70_COLOR_2_10_10_10:
2018 if (ntype == V_028C70_NUMBER_UINT)
2019 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2020 else if (ntype == V_028C70_NUMBER_SINT)
2021 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2022 else
2023 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2024 break;
2025
2026 case V_028C70_COLOR_16:
2027 case V_028C70_COLOR_16_16:
2028 case V_028C70_COLOR_16_16_16_16:
2029 if (ntype == V_028C70_NUMBER_UNORM ||
2030 ntype == V_028C70_NUMBER_SNORM) {
2031 /* UNORM16 and SNORM16 don't support blending */
2032 if (ntype == V_028C70_NUMBER_UNORM)
2033 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2034 else
2035 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2036
2037 /* Use 32 bits per channel for blending. */
2038 if (format == V_028C70_COLOR_16) {
2039 if (swap == V_028C70_SWAP_STD) { /* R */
2040 blend = V_028714_SPI_SHADER_32_R;
2041 blend_alpha = V_028714_SPI_SHADER_32_AR;
2042 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2043 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2044 else
2045 assert(0);
2046 } else if (format == V_028C70_COLOR_16_16) {
2047 if (swap == V_028C70_SWAP_STD) { /* RG */
2048 blend = V_028714_SPI_SHADER_32_GR;
2049 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2050 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2051 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2052 else
2053 assert(0);
2054 } else /* 16_16_16_16 */
2055 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2056 } else if (ntype == V_028C70_NUMBER_UINT)
2057 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2058 else if (ntype == V_028C70_NUMBER_SINT)
2059 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2060 else if (ntype == V_028C70_NUMBER_FLOAT)
2061 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2062 else
2063 assert(0);
2064 break;
2065
2066 case V_028C70_COLOR_32:
2067 if (swap == V_028C70_SWAP_STD) { /* R */
2068 blend = normal = V_028714_SPI_SHADER_32_R;
2069 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2070 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2071 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2072 else
2073 assert(0);
2074 break;
2075
2076 case V_028C70_COLOR_32_32:
2077 if (swap == V_028C70_SWAP_STD) { /* RG */
2078 blend = normal = V_028714_SPI_SHADER_32_GR;
2079 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2080 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2081 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2082 else
2083 assert(0);
2084 break;
2085
2086 case V_028C70_COLOR_32_32_32_32:
2087 case V_028C70_COLOR_8_24:
2088 case V_028C70_COLOR_24_8:
2089 case V_028C70_COLOR_X24_8_32_FLOAT:
2090 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2091 break;
2092
2093 default:
2094 assert(0);
2095 return;
2096 }
2097
2098 /* The DB->CB copy needs 32_ABGR. */
2099 if (is_depth)
2100 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2101
2102 surf->spi_shader_col_format = normal;
2103 surf->spi_shader_col_format_alpha = alpha;
2104 surf->spi_shader_col_format_blend = blend;
2105 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2106 }
2107
2108 static void si_initialize_color_surface(struct si_context *sctx,
2109 struct r600_surface *surf)
2110 {
2111 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2112 unsigned level = surf->base.u.tex.level;
2113 uint64_t offset = rtex->surface.level[level].offset;
2114 unsigned pitch, slice;
2115 unsigned color_info, color_attrib, color_pitch, color_view;
2116 unsigned tile_mode_index;
2117 unsigned format, swap, ntype, endian;
2118 const struct util_format_description *desc;
2119 int i;
2120 unsigned blend_clamp = 0, blend_bypass = 0;
2121
2122 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2123 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2124
2125 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2126 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2127 if (slice) {
2128 slice = slice - 1;
2129 }
2130
2131 tile_mode_index = si_tile_mode_index(rtex, level, false);
2132
2133 desc = util_format_description(surf->base.format);
2134 for (i = 0; i < 4; i++) {
2135 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2136 break;
2137 }
2138 }
2139 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2140 ntype = V_028C70_NUMBER_FLOAT;
2141 } else {
2142 ntype = V_028C70_NUMBER_UNORM;
2143 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2144 ntype = V_028C70_NUMBER_SRGB;
2145 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2146 if (desc->channel[i].pure_integer) {
2147 ntype = V_028C70_NUMBER_SINT;
2148 } else {
2149 assert(desc->channel[i].normalized);
2150 ntype = V_028C70_NUMBER_SNORM;
2151 }
2152 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2153 if (desc->channel[i].pure_integer) {
2154 ntype = V_028C70_NUMBER_UINT;
2155 } else {
2156 assert(desc->channel[i].normalized);
2157 ntype = V_028C70_NUMBER_UNORM;
2158 }
2159 }
2160 }
2161
2162 format = si_translate_colorformat(surf->base.format);
2163 if (format == V_028C70_COLOR_INVALID) {
2164 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2165 }
2166 assert(format != V_028C70_COLOR_INVALID);
2167 swap = r600_translate_colorswap(surf->base.format, FALSE);
2168 endian = si_colorformat_endian_swap(format);
2169
2170 /* blend clamp should be set for all NORM/SRGB types */
2171 if (ntype == V_028C70_NUMBER_UNORM ||
2172 ntype == V_028C70_NUMBER_SNORM ||
2173 ntype == V_028C70_NUMBER_SRGB)
2174 blend_clamp = 1;
2175
2176 /* set blend bypass according to docs if SINT/UINT or
2177 8/24 COLOR variants */
2178 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2179 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2180 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2181 blend_clamp = 0;
2182 blend_bypass = 1;
2183 }
2184
2185 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2186 (format == V_028C70_COLOR_8 ||
2187 format == V_028C70_COLOR_8_8 ||
2188 format == V_028C70_COLOR_8_8_8_8))
2189 surf->color_is_int8 = true;
2190
2191 color_info = S_028C70_FORMAT(format) |
2192 S_028C70_COMP_SWAP(swap) |
2193 S_028C70_BLEND_CLAMP(blend_clamp) |
2194 S_028C70_BLEND_BYPASS(blend_bypass) |
2195 S_028C70_NUMBER_TYPE(ntype) |
2196 S_028C70_ENDIAN(endian);
2197
2198 color_pitch = S_028C64_TILE_MAX(pitch);
2199
2200 /* Intensity is implemented as Red, so treat it that way. */
2201 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2202 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2203 util_format_is_intensity(surf->base.format));
2204
2205 if (rtex->resource.b.b.nr_samples > 1) {
2206 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2207
2208 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2209 S_028C74_NUM_FRAGMENTS(log_samples);
2210
2211 if (rtex->fmask.size) {
2212 color_info |= S_028C70_COMPRESSION(1);
2213 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2214
2215 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2216
2217 if (sctx->b.chip_class == SI) {
2218 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2219 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2220 }
2221 if (sctx->b.chip_class >= CIK) {
2222 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2223 }
2224 }
2225 }
2226
2227 offset += rtex->resource.gpu_address;
2228
2229 surf->cb_color_base = offset >> 8;
2230 surf->cb_color_pitch = color_pitch;
2231 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2232 surf->cb_color_view = color_view;
2233 surf->cb_color_info = color_info;
2234 surf->cb_color_attrib = color_attrib;
2235
2236 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2237 unsigned max_uncompressed_block_size = 2;
2238
2239 if (rtex->surface.nsamples > 1) {
2240 if (rtex->surface.bpe == 1)
2241 max_uncompressed_block_size = 0;
2242 else if (rtex->surface.bpe == 2)
2243 max_uncompressed_block_size = 1;
2244 }
2245
2246 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2247 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2248 surf->cb_dcc_base = (rtex->resource.gpu_address +
2249 rtex->dcc_offset +
2250 rtex->surface.level[level].dcc_offset) >> 8;
2251 }
2252
2253 if (rtex->fmask.size) {
2254 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2255 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2256 } else {
2257 /* This must be set for fast clear to work without FMASK. */
2258 surf->cb_color_fmask = surf->cb_color_base;
2259 surf->cb_color_fmask_slice = surf->cb_color_slice;
2260 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2261
2262 if (sctx->b.chip_class == SI) {
2263 unsigned bankh = util_logbase2(rtex->surface.bankh);
2264 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2265 }
2266
2267 if (sctx->b.chip_class >= CIK) {
2268 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2269 }
2270 }
2271
2272 /* Determine pixel shader export format */
2273 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2274
2275 surf->color_initialized = true;
2276 }
2277
2278 static void si_init_depth_surface(struct si_context *sctx,
2279 struct r600_surface *surf)
2280 {
2281 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2282 unsigned level = surf->base.u.tex.level;
2283 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2284 unsigned format;
2285 uint32_t z_info, s_info, db_depth_info;
2286 uint64_t z_offs, s_offs;
2287 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2288
2289 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2290 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2291 case PIPE_FORMAT_X8Z24_UNORM:
2292 case PIPE_FORMAT_Z24X8_UNORM:
2293 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2294 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2295 break;
2296 case PIPE_FORMAT_Z32_FLOAT:
2297 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2298 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2299 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2300 break;
2301 case PIPE_FORMAT_Z16_UNORM:
2302 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2303 break;
2304 default:
2305 assert(0);
2306 }
2307
2308 format = si_translate_dbformat(rtex->resource.b.b.format);
2309
2310 if (format == V_028040_Z_INVALID) {
2311 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2312 }
2313 assert(format != V_028040_Z_INVALID);
2314
2315 s_offs = z_offs = rtex->resource.gpu_address;
2316 z_offs += rtex->surface.level[level].offset;
2317 s_offs += rtex->surface.stencil_level[level].offset;
2318
2319 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2320
2321 z_info = S_028040_FORMAT(format);
2322 if (rtex->resource.b.b.nr_samples > 1) {
2323 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2324 }
2325
2326 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2327 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2328 else
2329 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2330
2331 if (sctx->b.chip_class >= CIK) {
2332 struct radeon_info *info = &sctx->screen->b.info;
2333 unsigned index = rtex->surface.tiling_index[level];
2334 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2335 unsigned macro_index = rtex->surface.macro_tile_index;
2336 unsigned tile_mode = info->si_tile_mode_array[index];
2337 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2338 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2339
2340 db_depth_info |=
2341 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2342 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2343 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2344 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2345 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2346 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2347 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2348 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2349 } else {
2350 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2351 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2352 tile_mode_index = si_tile_mode_index(rtex, level, true);
2353 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2354 }
2355
2356 /* HiZ aka depth buffer htile */
2357 /* use htile only for first level */
2358 if (rtex->htile_buffer && !level) {
2359 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2360 S_028040_ALLOW_EXPCLEAR(1);
2361
2362 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2363 /* Workaround: For a not yet understood reason, the
2364 * combination of MSAA, fast stencil clear and stencil
2365 * decompress messes with subsequent stencil buffer
2366 * uses. Problem was reproduced on Verde, Bonaire,
2367 * Tonga, and Carrizo.
2368 *
2369 * Disabling EXPCLEAR works around the problem.
2370 *
2371 * Check piglit's arb_texture_multisample-stencil-clear
2372 * test if you want to try changing this.
2373 */
2374 if (rtex->resource.b.b.nr_samples <= 1)
2375 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2376 } else
2377 /* Use all of the htile_buffer for depth if there's no stencil. */
2378 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2379
2380 uint64_t va = rtex->htile_buffer->gpu_address;
2381 db_htile_data_base = va >> 8;
2382 db_htile_surface = S_028ABC_FULL_CACHE(1);
2383 } else {
2384 db_htile_data_base = 0;
2385 db_htile_surface = 0;
2386 }
2387
2388 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2389
2390 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2391 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2392 surf->db_htile_data_base = db_htile_data_base;
2393 surf->db_depth_info = db_depth_info;
2394 surf->db_z_info = z_info;
2395 surf->db_stencil_info = s_info;
2396 surf->db_depth_base = z_offs >> 8;
2397 surf->db_stencil_base = s_offs >> 8;
2398 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2399 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2400 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2401 levelinfo->nblk_y) / 64 - 1);
2402 surf->db_htile_surface = db_htile_surface;
2403 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2404
2405 surf->depth_initialized = true;
2406 }
2407
2408 static void si_set_framebuffer_state(struct pipe_context *ctx,
2409 const struct pipe_framebuffer_state *state)
2410 {
2411 struct si_context *sctx = (struct si_context *)ctx;
2412 struct pipe_constant_buffer constbuf = {0};
2413 struct r600_surface *surf = NULL;
2414 struct r600_texture *rtex;
2415 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2416 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2417 int i;
2418
2419 /* Only flush TC when changing the framebuffer state, because
2420 * the only client not using TC that can change textures is
2421 * the framebuffer.
2422 *
2423 * Flush all CB and DB caches here because all buffers can be used
2424 * for write by both TC (with shader image stores) and CB/DB.
2425 */
2426 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2427 SI_CONTEXT_INV_GLOBAL_L2 |
2428 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2429 SI_CONTEXT_CS_PARTIAL_FLUSH;
2430
2431 /* Take the maximum of the old and new count. If the new count is lower,
2432 * dirtying is needed to disable the unbound colorbuffers.
2433 */
2434 sctx->framebuffer.dirty_cbufs |=
2435 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2436 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2437
2438 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2439
2440 sctx->framebuffer.spi_shader_col_format = 0;
2441 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2442 sctx->framebuffer.spi_shader_col_format_blend = 0;
2443 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2444 sctx->framebuffer.color_is_int8 = 0;
2445
2446 sctx->framebuffer.compressed_cb_mask = 0;
2447 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2448 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2449 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2450 util_format_is_pure_integer(state->cbufs[0]->format);
2451
2452 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2453 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2454
2455 for (i = 0; i < state->nr_cbufs; i++) {
2456 if (!state->cbufs[i])
2457 continue;
2458
2459 surf = (struct r600_surface*)state->cbufs[i];
2460 rtex = (struct r600_texture*)surf->base.texture;
2461
2462 if (!surf->color_initialized) {
2463 si_initialize_color_surface(sctx, surf);
2464 }
2465
2466 sctx->framebuffer.spi_shader_col_format |=
2467 surf->spi_shader_col_format << (i * 4);
2468 sctx->framebuffer.spi_shader_col_format_alpha |=
2469 surf->spi_shader_col_format_alpha << (i * 4);
2470 sctx->framebuffer.spi_shader_col_format_blend |=
2471 surf->spi_shader_col_format_blend << (i * 4);
2472 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2473 surf->spi_shader_col_format_blend_alpha << (i * 4);
2474
2475 if (surf->color_is_int8)
2476 sctx->framebuffer.color_is_int8 |= 1 << i;
2477
2478 if (rtex->fmask.size && rtex->cmask.size) {
2479 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2480 }
2481 r600_context_add_resource_size(ctx, surf->base.texture);
2482 }
2483 /* Set the second SPI format for possible dual-src blending. */
2484 if (i == 1 && surf) {
2485 sctx->framebuffer.spi_shader_col_format |=
2486 surf->spi_shader_col_format << (i * 4);
2487 sctx->framebuffer.spi_shader_col_format_alpha |=
2488 surf->spi_shader_col_format_alpha << (i * 4);
2489 sctx->framebuffer.spi_shader_col_format_blend |=
2490 surf->spi_shader_col_format_blend << (i * 4);
2491 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2492 surf->spi_shader_col_format_blend_alpha << (i * 4);
2493 }
2494
2495 if (state->zsbuf) {
2496 surf = (struct r600_surface*)state->zsbuf;
2497
2498 if (!surf->depth_initialized) {
2499 si_init_depth_surface(sctx, surf);
2500 }
2501 r600_context_add_resource_size(ctx, surf->base.texture);
2502 }
2503
2504 si_update_poly_offset_state(sctx);
2505 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2506 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2507
2508 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2509 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2510 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2511
2512 /* Set sample locations as fragment shader constants. */
2513 switch (sctx->framebuffer.nr_samples) {
2514 case 1:
2515 constbuf.user_buffer = sctx->b.sample_locations_1x;
2516 break;
2517 case 2:
2518 constbuf.user_buffer = sctx->b.sample_locations_2x;
2519 break;
2520 case 4:
2521 constbuf.user_buffer = sctx->b.sample_locations_4x;
2522 break;
2523 case 8:
2524 constbuf.user_buffer = sctx->b.sample_locations_8x;
2525 break;
2526 case 16:
2527 constbuf.user_buffer = sctx->b.sample_locations_16x;
2528 break;
2529 default:
2530 R600_ERR("Requested an invalid number of samples %i.\n",
2531 sctx->framebuffer.nr_samples);
2532 assert(0);
2533 }
2534 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2535 si_set_constant_buffer(sctx, &sctx->rw_buffers,
2536 SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2537
2538 /* Smoothing (only possible with nr_samples == 1) uses the same
2539 * sample locations as the MSAA it simulates.
2540 *
2541 * Therefore, don't update the sample locations when
2542 * transitioning from no AA to smoothing-equivalent AA, and
2543 * vice versa.
2544 */
2545 if ((sctx->framebuffer.nr_samples != 1 ||
2546 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2547 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2548 old_nr_samples != 1))
2549 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2550 }
2551 }
2552
2553 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2554 {
2555 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2556 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2557 unsigned i, nr_cbufs = state->nr_cbufs;
2558 struct r600_texture *tex = NULL;
2559 struct r600_surface *cb = NULL;
2560
2561 /* Colorbuffers. */
2562 for (i = 0; i < nr_cbufs; i++) {
2563 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2564 continue;
2565
2566 cb = (struct r600_surface*)state->cbufs[i];
2567 if (!cb) {
2568 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2569 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2570 continue;
2571 }
2572
2573 tex = (struct r600_texture *)cb->base.texture;
2574 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2575 &tex->resource, RADEON_USAGE_READWRITE,
2576 tex->surface.nsamples > 1 ?
2577 RADEON_PRIO_COLOR_BUFFER_MSAA :
2578 RADEON_PRIO_COLOR_BUFFER);
2579
2580 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2581 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2582 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2583 RADEON_PRIO_CMASK);
2584 }
2585
2586 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2587 sctx->b.chip_class >= VI ? 14 : 13);
2588 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2589 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2590 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2591 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2592 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2593 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2594 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2595 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2596 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2597 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2598 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2599 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2600 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2601
2602 if (sctx->b.chip_class >= VI)
2603 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2604 }
2605 /* set CB_COLOR1_INFO for possible dual-src blending */
2606 if (i == 1 && state->cbufs[0] &&
2607 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2608 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2609 cb->cb_color_info | tex->cb_color_info);
2610 i++;
2611 }
2612 for (; i < 8 ; i++)
2613 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2614 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2615
2616 /* ZS buffer. */
2617 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2618 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2619 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2620
2621 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2622 &rtex->resource, RADEON_USAGE_READWRITE,
2623 zb->base.texture->nr_samples > 1 ?
2624 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2625 RADEON_PRIO_DEPTH_BUFFER);
2626
2627 if (zb->db_htile_data_base) {
2628 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2629 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2630 RADEON_PRIO_HTILE);
2631 }
2632
2633 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2634 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2635
2636 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2637 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2638 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2639 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2640 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2641 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2642 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2643 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2644 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2645 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2646 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2647
2648 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2649 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2650 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2651
2652 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2653 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2654 zb->pa_su_poly_offset_db_fmt_cntl);
2655 } else if (sctx->framebuffer.dirty_zsbuf) {
2656 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2657 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2658 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2659 }
2660
2661 /* Framebuffer dimensions. */
2662 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2663 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2664 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2665
2666 sctx->framebuffer.dirty_cbufs = 0;
2667 sctx->framebuffer.dirty_zsbuf = false;
2668 }
2669
2670 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2671 struct r600_atom *atom)
2672 {
2673 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2674 unsigned nr_samples = sctx->framebuffer.nr_samples;
2675
2676 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2677 SI_NUM_SMOOTH_AA_SAMPLES);
2678 }
2679
2680 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2681 {
2682 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2683
2684 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2685 sctx->ps_iter_samples,
2686 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2687 }
2688
2689
2690 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2691 {
2692 struct si_context *sctx = (struct si_context *)ctx;
2693
2694 if (sctx->ps_iter_samples == min_samples)
2695 return;
2696
2697 sctx->ps_iter_samples = min_samples;
2698
2699 if (sctx->framebuffer.nr_samples > 1)
2700 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2701 }
2702
2703 /*
2704 * Samplers
2705 */
2706
2707 /**
2708 * Build the sampler view descriptor for a buffer texture.
2709 * @param state 256-bit descriptor; only the high 128 bits are filled in
2710 */
2711 void
2712 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2713 enum pipe_format format,
2714 unsigned first_element, unsigned last_element,
2715 uint32_t *state)
2716 {
2717 const struct util_format_description *desc;
2718 int first_non_void;
2719 uint64_t va;
2720 unsigned stride;
2721 unsigned num_records;
2722 unsigned num_format, data_format;
2723
2724 desc = util_format_description(format);
2725 first_non_void = util_format_get_first_non_void_channel(format);
2726 stride = desc->block.bits / 8;
2727 va = buf->gpu_address + first_element * stride;
2728 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2729 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2730
2731 num_records = last_element + 1 - first_element;
2732 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2733
2734 if (screen->b.chip_class >= VI)
2735 num_records *= stride;
2736
2737 state[4] = va;
2738 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2739 S_008F04_STRIDE(stride);
2740 state[6] = num_records;
2741 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2742 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2743 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2744 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2745 S_008F0C_NUM_FORMAT(num_format) |
2746 S_008F0C_DATA_FORMAT(data_format);
2747 }
2748
2749 /**
2750 * Build the sampler view descriptor for a texture.
2751 */
2752 void
2753 si_make_texture_descriptor(struct si_screen *screen,
2754 struct r600_texture *tex,
2755 bool sampler,
2756 enum pipe_texture_target target,
2757 enum pipe_format pipe_format,
2758 const unsigned char state_swizzle[4],
2759 unsigned base_level, unsigned first_level, unsigned last_level,
2760 unsigned first_layer, unsigned last_layer,
2761 unsigned width, unsigned height, unsigned depth,
2762 uint32_t *state,
2763 uint32_t *fmask_state)
2764 {
2765 struct pipe_resource *res = &tex->resource.b.b;
2766 const struct radeon_surf_level *surflevel = tex->surface.level;
2767 const struct util_format_description *desc;
2768 unsigned char swizzle[4];
2769 int first_non_void;
2770 unsigned num_format, data_format, type;
2771 uint32_t pitch;
2772 uint64_t va;
2773
2774 /* Texturing with separate depth and stencil. */
2775 if (tex->is_depth && !tex->is_flushing_texture) {
2776 switch (pipe_format) {
2777 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2778 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2779 break;
2780 case PIPE_FORMAT_X8Z24_UNORM:
2781 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2782 /* Z24 is always stored like this. */
2783 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2784 break;
2785 case PIPE_FORMAT_X24S8_UINT:
2786 case PIPE_FORMAT_S8X24_UINT:
2787 case PIPE_FORMAT_X32_S8X24_UINT:
2788 pipe_format = PIPE_FORMAT_S8_UINT;
2789 surflevel = tex->surface.stencil_level;
2790 break;
2791 default:;
2792 }
2793 }
2794
2795 desc = util_format_description(pipe_format);
2796
2797 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2798 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2799 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2800
2801 switch (pipe_format) {
2802 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2803 case PIPE_FORMAT_X24S8_UINT:
2804 case PIPE_FORMAT_X32_S8X24_UINT:
2805 case PIPE_FORMAT_X8Z24_UNORM:
2806 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2807 break;
2808 default:
2809 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2810 }
2811 } else {
2812 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2813 }
2814
2815 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2816
2817 switch (pipe_format) {
2818 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2819 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2820 break;
2821 default:
2822 if (first_non_void < 0) {
2823 if (util_format_is_compressed(pipe_format)) {
2824 switch (pipe_format) {
2825 case PIPE_FORMAT_DXT1_SRGB:
2826 case PIPE_FORMAT_DXT1_SRGBA:
2827 case PIPE_FORMAT_DXT3_SRGBA:
2828 case PIPE_FORMAT_DXT5_SRGBA:
2829 case PIPE_FORMAT_BPTC_SRGBA:
2830 case PIPE_FORMAT_ETC2_SRGB8:
2831 case PIPE_FORMAT_ETC2_SRGB8A1:
2832 case PIPE_FORMAT_ETC2_SRGBA8:
2833 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2834 break;
2835 case PIPE_FORMAT_RGTC1_SNORM:
2836 case PIPE_FORMAT_LATC1_SNORM:
2837 case PIPE_FORMAT_RGTC2_SNORM:
2838 case PIPE_FORMAT_LATC2_SNORM:
2839 case PIPE_FORMAT_ETC2_R11_SNORM:
2840 case PIPE_FORMAT_ETC2_RG11_SNORM:
2841 /* implies float, so use SNORM/UNORM to determine
2842 whether data is signed or not */
2843 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2844 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2845 break;
2846 default:
2847 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2848 break;
2849 }
2850 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2851 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2852 } else {
2853 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2854 }
2855 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2856 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2857 } else {
2858 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2859
2860 switch (desc->channel[first_non_void].type) {
2861 case UTIL_FORMAT_TYPE_FLOAT:
2862 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2863 break;
2864 case UTIL_FORMAT_TYPE_SIGNED:
2865 if (desc->channel[first_non_void].normalized)
2866 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2867 else if (desc->channel[first_non_void].pure_integer)
2868 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2869 else
2870 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2871 break;
2872 case UTIL_FORMAT_TYPE_UNSIGNED:
2873 if (desc->channel[first_non_void].normalized)
2874 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2875 else if (desc->channel[first_non_void].pure_integer)
2876 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2877 else
2878 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2879 }
2880 }
2881 }
2882
2883 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2884 if (data_format == ~0) {
2885 data_format = 0;
2886 }
2887
2888 if (!sampler &&
2889 (res->target == PIPE_TEXTURE_CUBE ||
2890 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2891 res->target == PIPE_TEXTURE_3D)) {
2892 /* For the purpose of shader images, treat cube maps and 3D
2893 * textures as 2D arrays. For 3D textures, the address
2894 * calculations for mipmaps are different, so we rely on the
2895 * caller to effectively disable mipmaps.
2896 */
2897 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2898
2899 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2900 } else {
2901 type = si_tex_dim(res->target, target, res->nr_samples);
2902 }
2903
2904 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2905 height = 1;
2906 depth = res->array_size;
2907 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2908 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2909 if (sampler || res->target != PIPE_TEXTURE_3D)
2910 depth = res->array_size;
2911 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2912 depth = res->array_size / 6;
2913
2914 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2915 va = tex->resource.gpu_address + surflevel[base_level].offset;
2916
2917 state[0] = va >> 8;
2918 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2919 S_008F14_DATA_FORMAT(data_format) |
2920 S_008F14_NUM_FORMAT(num_format));
2921 state[2] = (S_008F18_WIDTH(width - 1) |
2922 S_008F18_HEIGHT(height - 1));
2923 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2924 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2925 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2926 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2927 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2928 0 : first_level) |
2929 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2930 util_logbase2(res->nr_samples) :
2931 last_level) |
2932 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
2933 S_008F1C_POW2_PAD(res->last_level > 0) |
2934 S_008F1C_TYPE(type));
2935 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2936 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2937 S_008F24_LAST_ARRAY(last_layer));
2938
2939 if (tex->dcc_offset) {
2940 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2941
2942 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2943 state[7] = (tex->resource.gpu_address +
2944 tex->dcc_offset +
2945 surflevel[base_level].dcc_offset) >> 8;
2946 } else {
2947 state[6] = 0;
2948 state[7] = 0;
2949
2950 /* The last dword is unused by hw. The shader uses it to clear
2951 * bits in the first dword of sampler state.
2952 */
2953 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2954 if (first_level == last_level)
2955 state[7] = C_008F30_MAX_ANISO_RATIO;
2956 else
2957 state[7] = 0xffffffff;
2958 }
2959 }
2960
2961 /* Initialize the sampler view for FMASK. */
2962 if (tex->fmask.size) {
2963 uint32_t fmask_format;
2964
2965 va = tex->resource.gpu_address + tex->fmask.offset;
2966
2967 switch (res->nr_samples) {
2968 case 2:
2969 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2970 break;
2971 case 4:
2972 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2973 break;
2974 case 8:
2975 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2976 break;
2977 default:
2978 assert(0);
2979 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2980 }
2981
2982 fmask_state[0] = va >> 8;
2983 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2984 S_008F14_DATA_FORMAT(fmask_format) |
2985 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2986 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2987 S_008F18_HEIGHT(height - 1);
2988 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2989 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2990 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2991 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2992 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2993 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2994 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2995 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2996 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2997 S_008F24_LAST_ARRAY(last_layer);
2998 fmask_state[6] = 0;
2999 fmask_state[7] = 0;
3000 }
3001 }
3002
3003 /**
3004 * Create a sampler view.
3005 *
3006 * @param ctx context
3007 * @param texture texture
3008 * @param state sampler view template
3009 * @param width0 width0 override (for compressed textures as int)
3010 * @param height0 height0 override (for compressed textures as int)
3011 * @param force_level set the base address to the level (for compressed textures)
3012 */
3013 struct pipe_sampler_view *
3014 si_create_sampler_view_custom(struct pipe_context *ctx,
3015 struct pipe_resource *texture,
3016 const struct pipe_sampler_view *state,
3017 unsigned width0, unsigned height0,
3018 unsigned force_level)
3019 {
3020 struct si_context *sctx = (struct si_context*)ctx;
3021 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3022 struct r600_texture *tmp = (struct r600_texture*)texture;
3023 unsigned base_level, first_level, last_level;
3024 unsigned char state_swizzle[4];
3025 unsigned height, depth, width;
3026 unsigned last_layer = state->u.tex.last_layer;
3027
3028 if (!view)
3029 return NULL;
3030
3031 /* initialize base object */
3032 view->base = *state;
3033 view->base.texture = NULL;
3034 view->base.reference.count = 1;
3035 view->base.context = ctx;
3036
3037 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3038 if (!texture) {
3039 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3040 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3041 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3042 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3043 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3044 return &view->base;
3045 }
3046
3047 pipe_resource_reference(&view->base.texture, texture);
3048
3049 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3050 state->format == PIPE_FORMAT_S8X24_UINT ||
3051 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3052 state->format == PIPE_FORMAT_S8_UINT)
3053 view->is_stencil_sampler = true;
3054
3055 /* Buffer resource. */
3056 if (texture->target == PIPE_BUFFER) {
3057 si_make_buffer_descriptor(sctx->screen,
3058 (struct r600_resource *)texture,
3059 state->format,
3060 state->u.buf.first_element,
3061 state->u.buf.last_element,
3062 view->state);
3063
3064 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3065 return &view->base;
3066 }
3067
3068 state_swizzle[0] = state->swizzle_r;
3069 state_swizzle[1] = state->swizzle_g;
3070 state_swizzle[2] = state->swizzle_b;
3071 state_swizzle[3] = state->swizzle_a;
3072
3073 base_level = 0;
3074 first_level = state->u.tex.first_level;
3075 last_level = state->u.tex.last_level;
3076 width = width0;
3077 height = height0;
3078 depth = texture->depth0;
3079
3080 if (force_level) {
3081 assert(force_level == first_level &&
3082 force_level == last_level);
3083 base_level = force_level;
3084 first_level = 0;
3085 last_level = 0;
3086 width = u_minify(width, force_level);
3087 height = u_minify(height, force_level);
3088 depth = u_minify(depth, force_level);
3089 }
3090
3091 /* This is not needed if state trackers set last_layer correctly. */
3092 if (state->target == PIPE_TEXTURE_1D ||
3093 state->target == PIPE_TEXTURE_2D ||
3094 state->target == PIPE_TEXTURE_RECT ||
3095 state->target == PIPE_TEXTURE_CUBE)
3096 last_layer = state->u.tex.first_layer;
3097
3098 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3099 state->format, state_swizzle,
3100 base_level, first_level, last_level,
3101 state->u.tex.first_layer, last_layer,
3102 width, height, depth,
3103 view->state, view->fmask_state);
3104
3105 return &view->base;
3106 }
3107
3108 static struct pipe_sampler_view *
3109 si_create_sampler_view(struct pipe_context *ctx,
3110 struct pipe_resource *texture,
3111 const struct pipe_sampler_view *state)
3112 {
3113 return si_create_sampler_view_custom(ctx, texture, state,
3114 texture ? texture->width0 : 0,
3115 texture ? texture->height0 : 0, 0);
3116 }
3117
3118 static void si_sampler_view_destroy(struct pipe_context *ctx,
3119 struct pipe_sampler_view *state)
3120 {
3121 struct si_sampler_view *view = (struct si_sampler_view *)state;
3122
3123 if (state->texture && state->texture->target == PIPE_BUFFER)
3124 LIST_DELINIT(&view->list);
3125
3126 pipe_resource_reference(&state->texture, NULL);
3127 FREE(view);
3128 }
3129
3130 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3131 {
3132 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3133 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3134 (linear_filter &&
3135 (wrap == PIPE_TEX_WRAP_CLAMP ||
3136 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3137 }
3138
3139 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3140 {
3141 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3142 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3143
3144 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3145 state->border_color.ui[2] || state->border_color.ui[3]) &&
3146 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3147 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3148 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3149 }
3150
3151 static void *si_create_sampler_state(struct pipe_context *ctx,
3152 const struct pipe_sampler_state *state)
3153 {
3154 struct si_context *sctx = (struct si_context *)ctx;
3155 struct r600_common_screen *rscreen = sctx->b.screen;
3156 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3157 unsigned border_color_type, border_color_index = 0;
3158 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3159 : state->max_anisotropy;
3160 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3161
3162 if (!rstate) {
3163 return NULL;
3164 }
3165
3166 if (!sampler_state_needs_border_color(state))
3167 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3168 else if (state->border_color.f[0] == 0 &&
3169 state->border_color.f[1] == 0 &&
3170 state->border_color.f[2] == 0 &&
3171 state->border_color.f[3] == 0)
3172 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3173 else if (state->border_color.f[0] == 0 &&
3174 state->border_color.f[1] == 0 &&
3175 state->border_color.f[2] == 0 &&
3176 state->border_color.f[3] == 1)
3177 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3178 else if (state->border_color.f[0] == 1 &&
3179 state->border_color.f[1] == 1 &&
3180 state->border_color.f[2] == 1 &&
3181 state->border_color.f[3] == 1)
3182 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3183 else {
3184 int i;
3185
3186 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3187
3188 /* Check if the border has been uploaded already. */
3189 for (i = 0; i < sctx->border_color_count; i++)
3190 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3191 sizeof(state->border_color)) == 0)
3192 break;
3193
3194 if (i >= SI_MAX_BORDER_COLORS) {
3195 /* Getting 4096 unique border colors is very unlikely. */
3196 fprintf(stderr, "radeonsi: The border color table is full. "
3197 "Any new border colors will be just black. "
3198 "Please file a bug.\n");
3199 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3200 } else {
3201 if (i == sctx->border_color_count) {
3202 /* Upload a new border color. */
3203 memcpy(&sctx->border_color_table[i], &state->border_color,
3204 sizeof(state->border_color));
3205 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3206 &state->border_color,
3207 sizeof(state->border_color));
3208 sctx->border_color_count++;
3209 }
3210
3211 border_color_index = i;
3212 }
3213 }
3214
3215 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3216 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3217 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3218 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3219 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3220 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3221 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3222 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3223 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3224 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3225 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3226 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3227 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3228 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3229 S_008F38_MIP_POINT_PRECLAMP(1) |
3230 S_008F38_DISABLE_LSB_CEIL(1) |
3231 S_008F38_FILTER_PREC_FIX(1) |
3232 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3233 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3234 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3235 return rstate;
3236 }
3237
3238 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3239 {
3240 struct si_context *sctx = (struct si_context *)ctx;
3241
3242 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3243 return;
3244
3245 sctx->sample_mask.sample_mask = sample_mask;
3246 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3247 }
3248
3249 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3250 {
3251 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3252 unsigned mask = sctx->sample_mask.sample_mask;
3253
3254 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3255 radeon_emit(cs, mask | (mask << 16));
3256 radeon_emit(cs, mask | (mask << 16));
3257 }
3258
3259 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3260 {
3261 free(state);
3262 }
3263
3264 /*
3265 * Vertex elements & buffers
3266 */
3267
3268 static void *si_create_vertex_elements(struct pipe_context *ctx,
3269 unsigned count,
3270 const struct pipe_vertex_element *elements)
3271 {
3272 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3273 int i;
3274
3275 assert(count <= SI_MAX_ATTRIBS);
3276 if (!v)
3277 return NULL;
3278
3279 v->count = count;
3280 for (i = 0; i < count; ++i) {
3281 const struct util_format_description *desc;
3282 unsigned data_format, num_format;
3283 int first_non_void;
3284
3285 desc = util_format_description(elements[i].src_format);
3286 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3287 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3288 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3289
3290 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3291 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3292 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3293 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3294 S_008F0C_NUM_FORMAT(num_format) |
3295 S_008F0C_DATA_FORMAT(data_format);
3296 v->format_size[i] = desc->block.bits / 8;
3297 }
3298 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3299
3300 return v;
3301 }
3302
3303 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3304 {
3305 struct si_context *sctx = (struct si_context *)ctx;
3306 struct si_vertex_element *v = (struct si_vertex_element*)state;
3307
3308 sctx->vertex_elements = v;
3309 sctx->vertex_buffers_dirty = true;
3310 }
3311
3312 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3313 {
3314 struct si_context *sctx = (struct si_context *)ctx;
3315
3316 if (sctx->vertex_elements == state)
3317 sctx->vertex_elements = NULL;
3318 FREE(state);
3319 }
3320
3321 static void si_set_vertex_buffers(struct pipe_context *ctx,
3322 unsigned start_slot, unsigned count,
3323 const struct pipe_vertex_buffer *buffers)
3324 {
3325 struct si_context *sctx = (struct si_context *)ctx;
3326 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3327 int i;
3328
3329 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3330
3331 if (buffers) {
3332 for (i = 0; i < count; i++) {
3333 const struct pipe_vertex_buffer *src = buffers + i;
3334 struct pipe_vertex_buffer *dsti = dst + i;
3335
3336 pipe_resource_reference(&dsti->buffer, src->buffer);
3337 dsti->buffer_offset = src->buffer_offset;
3338 dsti->stride = src->stride;
3339 r600_context_add_resource_size(ctx, src->buffer);
3340 }
3341 } else {
3342 for (i = 0; i < count; i++) {
3343 pipe_resource_reference(&dst[i].buffer, NULL);
3344 }
3345 }
3346 sctx->vertex_buffers_dirty = true;
3347 }
3348
3349 static void si_set_index_buffer(struct pipe_context *ctx,
3350 const struct pipe_index_buffer *ib)
3351 {
3352 struct si_context *sctx = (struct si_context *)ctx;
3353
3354 if (ib) {
3355 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3356 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3357 r600_context_add_resource_size(ctx, ib->buffer);
3358 } else {
3359 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3360 }
3361 }
3362
3363 /*
3364 * Misc
3365 */
3366
3367 static void si_set_tess_state(struct pipe_context *ctx,
3368 const float default_outer_level[4],
3369 const float default_inner_level[2])
3370 {
3371 struct si_context *sctx = (struct si_context *)ctx;
3372 struct pipe_constant_buffer cb;
3373 float array[8];
3374
3375 memcpy(array, default_outer_level, sizeof(float) * 4);
3376 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3377
3378 cb.buffer = NULL;
3379 cb.user_buffer = NULL;
3380 cb.buffer_size = sizeof(array);
3381
3382 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3383 (void*)array, sizeof(array),
3384 &cb.buffer_offset);
3385
3386 si_set_constant_buffer(sctx, &sctx->rw_buffers,
3387 SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3388 pipe_resource_reference(&cb.buffer, NULL);
3389 }
3390
3391 static void si_texture_barrier(struct pipe_context *ctx)
3392 {
3393 struct si_context *sctx = (struct si_context *)ctx;
3394
3395 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3396 SI_CONTEXT_INV_GLOBAL_L2 |
3397 SI_CONTEXT_FLUSH_AND_INV_CB |
3398 SI_CONTEXT_CS_PARTIAL_FLUSH;
3399 }
3400
3401 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3402 {
3403 struct si_context *sctx = (struct si_context *)ctx;
3404
3405 /* Subsequent commands must wait for all shader invocations to
3406 * complete. */
3407 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3408 SI_CONTEXT_CS_PARTIAL_FLUSH;
3409
3410 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3411 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3412 SI_CONTEXT_INV_VMEM_L1;
3413
3414 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3415 PIPE_BARRIER_SHADER_BUFFER |
3416 PIPE_BARRIER_TEXTURE |
3417 PIPE_BARRIER_IMAGE |
3418 PIPE_BARRIER_STREAMOUT_BUFFER |
3419 PIPE_BARRIER_GLOBAL_BUFFER)) {
3420 /* As far as I can tell, L1 contents are written back to L2
3421 * automatically at end of shader, but the contents of other
3422 * L1 caches might still be stale. */
3423 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3424 }
3425
3426 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3427 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3428
3429 /* Indices are read through TC L2 since VI. */
3430 if (sctx->screen->b.chip_class <= CIK)
3431 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3432 }
3433
3434 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3435 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3436
3437 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3438 PIPE_BARRIER_FRAMEBUFFER |
3439 PIPE_BARRIER_INDIRECT_BUFFER)) {
3440 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3441 *
3442 * We need to make sure that TC L1 & L2 are written back to
3443 * memory, because neither CPU accesses nor CB fetches consider
3444 * TC, but there's no need to invalidate any TC cache lines. */
3445 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3446 }
3447 }
3448
3449 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3450 {
3451 struct pipe_blend_state blend;
3452
3453 memset(&blend, 0, sizeof(blend));
3454 blend.independent_blend_enable = true;
3455 blend.rt[0].colormask = 0xf;
3456 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3457 }
3458
3459 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3460 bool include_draw_vbo)
3461 {
3462 si_need_cs_space((struct si_context*)ctx);
3463 }
3464
3465 static void si_init_config(struct si_context *sctx);
3466
3467 void si_init_state_functions(struct si_context *sctx)
3468 {
3469 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3470 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3471 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3472 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3473 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3474
3475 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3476 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3477 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3478 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3479 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3480 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3481 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3482 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3483 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3484 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3485 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3486
3487 sctx->b.b.create_blend_state = si_create_blend_state;
3488 sctx->b.b.bind_blend_state = si_bind_blend_state;
3489 sctx->b.b.delete_blend_state = si_delete_blend_state;
3490 sctx->b.b.set_blend_color = si_set_blend_color;
3491
3492 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3493 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3494 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3495
3496 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3497 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3498 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3499
3500 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3501 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3502 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3503 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3504 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3505
3506 sctx->b.b.set_clip_state = si_set_clip_state;
3507 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3508
3509 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3510 sctx->b.b.get_sample_position = cayman_get_sample_position;
3511
3512 sctx->b.b.create_sampler_state = si_create_sampler_state;
3513 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3514
3515 sctx->b.b.create_sampler_view = si_create_sampler_view;
3516 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3517
3518 sctx->b.b.set_sample_mask = si_set_sample_mask;
3519
3520 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3521 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3522 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3523 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3524 sctx->b.b.set_index_buffer = si_set_index_buffer;
3525
3526 sctx->b.b.texture_barrier = si_texture_barrier;
3527 sctx->b.b.memory_barrier = si_memory_barrier;
3528 sctx->b.b.set_min_samples = si_set_min_samples;
3529 sctx->b.b.set_tess_state = si_set_tess_state;
3530
3531 sctx->b.b.set_active_query_state = si_set_active_query_state;
3532 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3533 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3534
3535 sctx->b.b.draw_vbo = si_draw_vbo;
3536
3537 if (sctx->b.chip_class >= CIK) {
3538 sctx->b.dma_copy = cik_sdma_copy;
3539 } else {
3540 sctx->b.dma_copy = si_dma_copy;
3541 }
3542
3543 si_init_config(sctx);
3544 }
3545
3546 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3547 struct r600_texture *rtex,
3548 struct radeon_bo_metadata *md)
3549 {
3550 struct si_screen *sscreen = (struct si_screen*)rscreen;
3551 struct pipe_resource *res = &rtex->resource.b.b;
3552 static const unsigned char swizzle[] = {
3553 PIPE_SWIZZLE_X,
3554 PIPE_SWIZZLE_Y,
3555 PIPE_SWIZZLE_Z,
3556 PIPE_SWIZZLE_W
3557 };
3558 uint32_t desc[8], i;
3559 bool is_array = util_resource_is_array_texture(res);
3560
3561 /* DRM 2.x.x doesn't support this. */
3562 if (rscreen->info.drm_major != 3)
3563 return;
3564
3565 assert(rtex->fmask.size == 0);
3566
3567 /* Metadata image format format version 1:
3568 * [0] = 1 (metadata format identifier)
3569 * [1] = (VENDOR_ID << 16) | PCI_ID
3570 * [2:9] = image descriptor for the whole resource
3571 * [2] is always 0, because the base address is cleared
3572 * [9] is the DCC offset bits [39:8] from the beginning of
3573 * the buffer
3574 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3575 */
3576
3577 md->metadata[0] = 1; /* metadata image format version 1 */
3578
3579 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3580 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3581
3582 si_make_texture_descriptor(sscreen, rtex, true,
3583 res->target, res->format,
3584 swizzle, 0, 0, res->last_level, 0,
3585 is_array ? res->array_size - 1 : 0,
3586 res->width0, res->height0, res->depth0,
3587 desc, NULL);
3588
3589 /* Clear the base address and set the relative DCC offset. */
3590 desc[0] = 0;
3591 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3592 desc[7] = rtex->dcc_offset >> 8;
3593
3594 /* Dwords [2:9] contain the image descriptor. */
3595 memcpy(&md->metadata[2], desc, sizeof(desc));
3596
3597 /* Dwords [10:..] contain the mipmap level offsets. */
3598 for (i = 0; i <= res->last_level; i++)
3599 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3600
3601 md->size_metadata = (11 + res->last_level) * 4;
3602 }
3603
3604 void si_init_screen_state_functions(struct si_screen *sscreen)
3605 {
3606 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3607 }
3608
3609 static void
3610 si_write_harvested_raster_configs(struct si_context *sctx,
3611 struct si_pm4_state *pm4,
3612 unsigned raster_config,
3613 unsigned raster_config_1)
3614 {
3615 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3616 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3617 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3618 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3619 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3620 unsigned rb_per_se = num_rb / num_se;
3621 unsigned se_mask[4];
3622 unsigned se;
3623
3624 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3625 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3626 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3627 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3628
3629 assert(num_se == 1 || num_se == 2 || num_se == 4);
3630 assert(sh_per_se == 1 || sh_per_se == 2);
3631 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3632
3633 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3634 * fields are for, so I'm leaving them as their default
3635 * values. */
3636
3637 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3638 (!se_mask[2] && !se_mask[3]))) {
3639 raster_config_1 &= C_028354_SE_PAIR_MAP;
3640
3641 if (!se_mask[0] && !se_mask[1]) {
3642 raster_config_1 |=
3643 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3644 } else {
3645 raster_config_1 |=
3646 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3647 }
3648 }
3649
3650 for (se = 0; se < num_se; se++) {
3651 unsigned raster_config_se = raster_config;
3652 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3653 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3654 int idx = (se / 2) * 2;
3655
3656 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3657 raster_config_se &= C_028350_SE_MAP;
3658
3659 if (!se_mask[idx]) {
3660 raster_config_se |=
3661 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3662 } else {
3663 raster_config_se |=
3664 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3665 }
3666 }
3667
3668 pkr0_mask &= rb_mask;
3669 pkr1_mask &= rb_mask;
3670 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3671 raster_config_se &= C_028350_PKR_MAP;
3672
3673 if (!pkr0_mask) {
3674 raster_config_se |=
3675 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3676 } else {
3677 raster_config_se |=
3678 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3679 }
3680 }
3681
3682 if (rb_per_se >= 2) {
3683 unsigned rb0_mask = 1 << (se * rb_per_se);
3684 unsigned rb1_mask = rb0_mask << 1;
3685
3686 rb0_mask &= rb_mask;
3687 rb1_mask &= rb_mask;
3688 if (!rb0_mask || !rb1_mask) {
3689 raster_config_se &= C_028350_RB_MAP_PKR0;
3690
3691 if (!rb0_mask) {
3692 raster_config_se |=
3693 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3694 } else {
3695 raster_config_se |=
3696 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3697 }
3698 }
3699
3700 if (rb_per_se > 2) {
3701 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3702 rb1_mask = rb0_mask << 1;
3703 rb0_mask &= rb_mask;
3704 rb1_mask &= rb_mask;
3705 if (!rb0_mask || !rb1_mask) {
3706 raster_config_se &= C_028350_RB_MAP_PKR1;
3707
3708 if (!rb0_mask) {
3709 raster_config_se |=
3710 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3711 } else {
3712 raster_config_se |=
3713 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3714 }
3715 }
3716 }
3717 }
3718
3719 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3720 if (sctx->b.chip_class < CIK)
3721 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3722 SE_INDEX(se) | SH_BROADCAST_WRITES |
3723 INSTANCE_BROADCAST_WRITES);
3724 else
3725 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3726 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3727 S_030800_INSTANCE_BROADCAST_WRITES(1));
3728 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3729 if (sctx->b.chip_class >= CIK)
3730 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3731 }
3732
3733 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3734 if (sctx->b.chip_class < CIK)
3735 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3736 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3737 INSTANCE_BROADCAST_WRITES);
3738 else
3739 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3740 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3741 S_030800_INSTANCE_BROADCAST_WRITES(1));
3742 }
3743
3744 static void si_init_config(struct si_context *sctx)
3745 {
3746 struct si_screen *sscreen = sctx->screen;
3747 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3748 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3749 unsigned raster_config, raster_config_1;
3750 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3751 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3752 int i;
3753
3754 if (!pm4)
3755 return;
3756
3757 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3758 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3759 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3760 si_pm4_cmd_end(pm4, false);
3761
3762 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3763 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3764
3765 /* FIXME calculate these values somehow ??? */
3766 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3767 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3768 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3769
3770 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3771 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3772
3773 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3774 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3775 if (sctx->b.chip_class < CIK)
3776 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3777 S_008A14_CLIP_VTX_REORDER_ENA(1));
3778
3779 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3780 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3781
3782 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3783
3784 for (i = 0; i < 16; i++) {
3785 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3786 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3787 }
3788
3789 switch (sctx->screen->b.family) {
3790 case CHIP_TAHITI:
3791 case CHIP_PITCAIRN:
3792 raster_config = 0x2a00126a;
3793 raster_config_1 = 0x00000000;
3794 break;
3795 case CHIP_VERDE:
3796 raster_config = 0x0000124a;
3797 raster_config_1 = 0x00000000;
3798 break;
3799 case CHIP_OLAND:
3800 raster_config = 0x00000082;
3801 raster_config_1 = 0x00000000;
3802 break;
3803 case CHIP_HAINAN:
3804 raster_config = 0x00000000;
3805 raster_config_1 = 0x00000000;
3806 break;
3807 case CHIP_BONAIRE:
3808 raster_config = 0x16000012;
3809 raster_config_1 = 0x00000000;
3810 break;
3811 case CHIP_HAWAII:
3812 raster_config = 0x3a00161a;
3813 raster_config_1 = 0x0000002e;
3814 break;
3815 case CHIP_FIJI:
3816 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3817 /* old kernels with old tiling config */
3818 raster_config = 0x16000012;
3819 raster_config_1 = 0x0000002a;
3820 } else {
3821 raster_config = 0x3a00161a;
3822 raster_config_1 = 0x0000002e;
3823 }
3824 break;
3825 case CHIP_POLARIS10:
3826 raster_config = 0x16000012;
3827 raster_config_1 = 0x0000002a;
3828 break;
3829 case CHIP_POLARIS11:
3830 raster_config = 0x16000012;
3831 raster_config_1 = 0x00000000;
3832 break;
3833 case CHIP_TONGA:
3834 raster_config = 0x16000012;
3835 raster_config_1 = 0x0000002a;
3836 break;
3837 case CHIP_ICELAND:
3838 raster_config = 0x00000002;
3839 raster_config_1 = 0x00000000;
3840 break;
3841 case CHIP_CARRIZO:
3842 raster_config = 0x00000002;
3843 raster_config_1 = 0x00000000;
3844 break;
3845 case CHIP_KAVERI:
3846 /* KV should be 0x00000002, but that causes problems with radeon */
3847 raster_config = 0x00000000; /* 0x00000002 */
3848 raster_config_1 = 0x00000000;
3849 break;
3850 case CHIP_KABINI:
3851 case CHIP_MULLINS:
3852 case CHIP_STONEY:
3853 raster_config = 0x00000000;
3854 raster_config_1 = 0x00000000;
3855 break;
3856 default:
3857 fprintf(stderr,
3858 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3859 raster_config = 0x00000000;
3860 raster_config_1 = 0x00000000;
3861 break;
3862 }
3863
3864 /* Always use the default config when all backends are enabled
3865 * (or when we failed to determine the enabled backends).
3866 */
3867 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3868 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3869 raster_config);
3870 if (sctx->b.chip_class >= CIK)
3871 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3872 raster_config_1);
3873 } else {
3874 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3875 }
3876
3877 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3878 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3879 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3880 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3881 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3882 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3883 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3884
3885 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3886 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3887 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3888 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3889 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3890 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3891 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3892 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3893 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3894 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3895 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3896
3897 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3898 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3899 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3900
3901 if (sctx->b.chip_class >= CIK) {
3902 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3903 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3904 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3905
3906 if (sscreen->b.info.num_good_compute_units /
3907 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3908 /* Too few available compute units per SH. Disallowing
3909 * VS to run on CU0 could hurt us more than late VS
3910 * allocation would help.
3911 *
3912 * LATE_ALLOC_VS = 2 is the highest safe number.
3913 */
3914 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3915 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3916 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3917 } else {
3918 /* Set LATE_ALLOC_VS == 31. It should be less than
3919 * the number of scratch waves. Limitations:
3920 * - VS can't execute on CU0.
3921 * - If HS writes outputs to LDS, LS can't execute on CU0.
3922 */
3923 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3924 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3925 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3926 }
3927
3928 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3929 }
3930
3931 if (sctx->b.chip_class >= VI) {
3932 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3933 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3934 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3935 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3936 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3937 }
3938
3939 if (sctx->b.family == CHIP_STONEY)
3940 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3941
3942 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3943 if (sctx->b.chip_class >= CIK)
3944 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3945 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3946 RADEON_PRIO_BORDER_COLORS);
3947
3948 si_pm4_upload_indirect_buffer(sctx, pm4);
3949 sctx->init_config = pm4;
3950 }