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radeonsi/gfx9: FMASK image descriptor changes
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* RB+ register settings. */
121 if (sctx->screen->b.rbplus_allowed) {
122 unsigned spi_shader_col_format =
123 sctx->ps_shader.cso ?
124 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
125 unsigned sx_ps_downconvert = 0;
126 unsigned sx_blend_opt_epsilon = 0;
127 unsigned sx_blend_opt_control = 0;
128
129 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
130 struct r600_surface *surf =
131 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
132 unsigned format, swap, spi_format, colormask;
133 bool has_alpha, has_rgb;
134
135 if (!surf)
136 continue;
137
138 format = G_028C70_FORMAT(surf->cb_color_info);
139 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
140 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
141 colormask = (cb_target_mask >> (i * 4)) & 0xf;
142
143 /* Set if RGB and A are present. */
144 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
145
146 if (format == V_028C70_COLOR_8 ||
147 format == V_028C70_COLOR_16 ||
148 format == V_028C70_COLOR_32)
149 has_rgb = !has_alpha;
150 else
151 has_rgb = true;
152
153 /* Check the colormask and export format. */
154 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
155 has_rgb = false;
156 if (!(colormask & PIPE_MASK_A))
157 has_alpha = false;
158
159 if (spi_format == V_028714_SPI_SHADER_ZERO) {
160 has_rgb = false;
161 has_alpha = false;
162 }
163
164 /* Disable value checking for disabled channels. */
165 if (!has_rgb)
166 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
167 if (!has_alpha)
168 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
169
170 /* Enable down-conversion for 32bpp and smaller formats. */
171 switch (format) {
172 case V_028C70_COLOR_8:
173 case V_028C70_COLOR_8_8:
174 case V_028C70_COLOR_8_8_8_8:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
178 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
180 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
181 }
182 break;
183
184 case V_028C70_COLOR_5_6_5:
185 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_1_5_5_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_4_4_4_4:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_32:
206 if (swap == V_0280A0_SWAP_STD &&
207 spi_format == V_028714_SPI_SHADER_32_R)
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
209 else if (swap == V_0280A0_SWAP_ALT_REV &&
210 spi_format == V_028714_SPI_SHADER_32_AR)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
212 break;
213
214 case V_028C70_COLOR_16:
215 case V_028C70_COLOR_16_16:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
221 if (swap == V_0280A0_SWAP_STD ||
222 swap == V_0280A0_SWAP_STD_REV)
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
224 else
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
226 }
227 break;
228
229 case V_028C70_COLOR_10_11_11:
230 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
232 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_2_10_10_10:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
240 }
241 break;
242 }
243 }
244
245 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
246 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
249 } else if (sctx->screen->b.has_rbplus) {
250 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
251 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
252 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
253 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
254 }
255 }
256
257 /*
258 * Blender functions
259 */
260
261 static uint32_t si_translate_blend_function(int blend_func)
262 {
263 switch (blend_func) {
264 case PIPE_BLEND_ADD:
265 return V_028780_COMB_DST_PLUS_SRC;
266 case PIPE_BLEND_SUBTRACT:
267 return V_028780_COMB_SRC_MINUS_DST;
268 case PIPE_BLEND_REVERSE_SUBTRACT:
269 return V_028780_COMB_DST_MINUS_SRC;
270 case PIPE_BLEND_MIN:
271 return V_028780_COMB_MIN_DST_SRC;
272 case PIPE_BLEND_MAX:
273 return V_028780_COMB_MAX_DST_SRC;
274 default:
275 R600_ERR("Unknown blend function %d\n", blend_func);
276 assert(0);
277 break;
278 }
279 return 0;
280 }
281
282 static uint32_t si_translate_blend_factor(int blend_fact)
283 {
284 switch (blend_fact) {
285 case PIPE_BLENDFACTOR_ONE:
286 return V_028780_BLEND_ONE;
287 case PIPE_BLENDFACTOR_SRC_COLOR:
288 return V_028780_BLEND_SRC_COLOR;
289 case PIPE_BLENDFACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case PIPE_BLENDFACTOR_DST_ALPHA:
292 return V_028780_BLEND_DST_ALPHA;
293 case PIPE_BLENDFACTOR_DST_COLOR:
294 return V_028780_BLEND_DST_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE;
297 case PIPE_BLENDFACTOR_CONST_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_CONST_ALPHA:
300 return V_028780_BLEND_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_ZERO:
302 return V_028780_BLEND_ZERO;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_SRC1_COLOR:
316 return V_028780_BLEND_SRC1_COLOR;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA:
318 return V_028780_BLEND_SRC1_ALPHA;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
322 return V_028780_BLEND_INV_SRC1_ALPHA;
323 default:
324 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
325 assert(0);
326 break;
327 }
328 return 0;
329 }
330
331 static uint32_t si_translate_blend_opt_function(int blend_func)
332 {
333 switch (blend_func) {
334 case PIPE_BLEND_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case PIPE_BLEND_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case PIPE_BLEND_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case PIPE_BLEND_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case PIPE_BLEND_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
350 {
351 switch (blend_fact) {
352 case PIPE_BLENDFACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case PIPE_BLENDFACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case PIPE_BLENDFACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case PIPE_BLENDFACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 /**
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 */
378 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
379 unsigned *dst_factor, unsigned expected_dst,
380 unsigned replacement_src)
381 {
382 if (*src_factor == expected_dst &&
383 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
384 *src_factor = PIPE_BLENDFACTOR_ZERO;
385 *dst_factor = replacement_src;
386
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func == PIPE_BLEND_SUBTRACT)
389 *func = PIPE_BLEND_REVERSE_SUBTRACT;
390 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
391 *func = PIPE_BLEND_SUBTRACT;
392 }
393 }
394
395 static bool si_blend_factor_uses_dst(unsigned factor)
396 {
397 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
398 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
399 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
400 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
401 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
402 }
403
404 static void *si_create_blend_state_mode(struct pipe_context *ctx,
405 const struct pipe_blend_state *state,
406 unsigned mode)
407 {
408 struct si_context *sctx = (struct si_context*)ctx;
409 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
410 struct si_pm4_state *pm4 = &blend->pm4;
411 uint32_t sx_mrt_blend_opt[8] = {0};
412 uint32_t color_control = 0;
413
414 if (!blend)
415 return NULL;
416
417 blend->alpha_to_coverage = state->alpha_to_coverage;
418 blend->alpha_to_one = state->alpha_to_one;
419 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
420
421 if (state->logicop_enable) {
422 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
423 } else {
424 color_control |= S_028808_ROP3(0xcc);
425 }
426
427 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
428 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
429 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433
434 if (state->alpha_to_coverage)
435 blend->need_src_alpha_4bit |= 0xf;
436
437 blend->cb_target_mask = 0;
438 for (int i = 0; i < 8; i++) {
439 /* state->rt entries > 0 only written if independent blending */
440 const int j = state->independent_blend_enable ? i : 0;
441
442 unsigned eqRGB = state->rt[j].rgb_func;
443 unsigned srcRGB = state->rt[j].rgb_src_factor;
444 unsigned dstRGB = state->rt[j].rgb_dst_factor;
445 unsigned eqA = state->rt[j].alpha_func;
446 unsigned srcA = state->rt[j].alpha_src_factor;
447 unsigned dstA = state->rt[j].alpha_dst_factor;
448
449 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
450 unsigned blend_cntl = 0;
451
452 sx_mrt_blend_opt[i] =
453 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
454 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
455
456 /* Only set dual source blending for MRT0 to avoid a hang. */
457 if (i >= 1 && blend->dual_src_blend) {
458 /* Vulkan does this for dual source blending. */
459 if (i == 1)
460 blend_cntl |= S_028780_ENABLE(1);
461
462 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
463 continue;
464 }
465
466 /* Only addition and subtraction equations are supported with
467 * dual source blending.
468 */
469 if (blend->dual_src_blend &&
470 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
471 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
472 assert(!"Unsupported equation for dual source blending");
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* cb_render_state will disable unused ones */
478 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
479
480 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
481 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
482 continue;
483 }
484
485 /* Blending optimizations for RB+.
486 * These transformations don't change the behavior.
487 *
488 * First, get rid of DST in the blend factors:
489 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
490 */
491 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
492 PIPE_BLENDFACTOR_DST_COLOR,
493 PIPE_BLENDFACTOR_SRC_COLOR);
494 si_blend_remove_dst(&eqA, &srcA, &dstA,
495 PIPE_BLENDFACTOR_DST_COLOR,
496 PIPE_BLENDFACTOR_SRC_COLOR);
497 si_blend_remove_dst(&eqA, &srcA, &dstA,
498 PIPE_BLENDFACTOR_DST_ALPHA,
499 PIPE_BLENDFACTOR_SRC_ALPHA);
500
501 /* Look up the ideal settings from tables. */
502 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
503 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
504 srcA_opt = si_translate_blend_opt_factor(srcA, true);
505 dstA_opt = si_translate_blend_opt_factor(dstA, true);
506
507 /* Handle interdependencies. */
508 if (si_blend_factor_uses_dst(srcRGB))
509 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
510 if (si_blend_factor_uses_dst(srcA))
511 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
512
513 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
514 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
516 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
517 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
518
519 /* Set the final value. */
520 sx_mrt_blend_opt[i] =
521 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
522 S_028760_COLOR_DST_OPT(dstRGB_opt) |
523 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
524 S_028760_ALPHA_SRC_OPT(srcA_opt) |
525 S_028760_ALPHA_DST_OPT(dstA_opt) |
526 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
527
528 /* Set blend state. */
529 blend_cntl |= S_028780_ENABLE(1);
530 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
531 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
532 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
533
534 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
535 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
536 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
537 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
538 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
539 }
540 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
541
542 blend->blend_enable_4bit |= 0xfu << (i * 4);
543
544 /* This is only important for formats without alpha. */
545 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
547 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
549 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
550 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
551 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
552 }
553
554 if (blend->cb_target_mask) {
555 color_control |= S_028808_MODE(mode);
556 } else {
557 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
558 }
559
560 if (sctx->screen->b.has_rbplus) {
561 /* Disable RB+ blend optimizations for dual source blending.
562 * Vulkan does this.
563 */
564 if (blend->dual_src_blend) {
565 for (int i = 0; i < 8; i++) {
566 sx_mrt_blend_opt[i] =
567 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
568 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
569 }
570 }
571
572 for (int i = 0; i < 8; i++)
573 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
574 sx_mrt_blend_opt[i]);
575
576 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
577 if (blend->dual_src_blend || state->logicop_enable ||
578 mode == V_028808_CB_RESOLVE)
579 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
580 }
581
582 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
583 return blend;
584 }
585
586 static void *si_create_blend_state(struct pipe_context *ctx,
587 const struct pipe_blend_state *state)
588 {
589 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
590 }
591
592 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
596 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
597 sctx->do_update_shaders = true;
598 }
599
600 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
601 {
602 struct si_context *sctx = (struct si_context *)ctx;
603 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
604 }
605
606 static void si_set_blend_color(struct pipe_context *ctx,
607 const struct pipe_blend_color *state)
608 {
609 struct si_context *sctx = (struct si_context *)ctx;
610
611 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
612 return;
613
614 sctx->blend_color.state = *state;
615 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
616 }
617
618 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
619 {
620 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
621
622 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
623 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
624 }
625
626 /*
627 * Clipping
628 */
629
630 static void si_set_clip_state(struct pipe_context *ctx,
631 const struct pipe_clip_state *state)
632 {
633 struct si_context *sctx = (struct si_context *)ctx;
634 struct pipe_constant_buffer cb;
635
636 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
637 return;
638
639 sctx->clip_state.state = *state;
640 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
641
642 cb.buffer = NULL;
643 cb.user_buffer = state->ucp;
644 cb.buffer_offset = 0;
645 cb.buffer_size = 4*4*8;
646 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
647 pipe_resource_reference(&cb.buffer, NULL);
648 }
649
650 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
651 {
652 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
653
654 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
655 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
656 }
657
658 #define SIX_BITS 0x3F
659
660 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
661 {
662 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
663 struct si_shader *vs = si_get_vs_state(sctx);
664 struct tgsi_shader_info *info = si_get_vs_info(sctx);
665 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
666 unsigned window_space =
667 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
668 unsigned clipdist_mask =
669 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
670 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
671 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
672 unsigned total_mask;
673 bool misc_vec_ena;
674
675 if (vs->key.opt.hw_vs.clip_disable) {
676 assert(!info->culldist_writemask);
677 clipdist_mask = 0;
678 culldist_mask = 0;
679 }
680 total_mask = clipdist_mask | culldist_mask;
681
682 /* Clip distances on points have no effect, so need to be implemented
683 * as cull distances. This applies for the clipvertex case as well.
684 *
685 * Setting this for primitives other than points should have no adverse
686 * effects.
687 */
688 clipdist_mask &= rs->clip_plane_enable;
689 culldist_mask |= clipdist_mask;
690
691 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
692 info->writes_layer || info->writes_viewport_index;
693
694 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
695 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
696 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
697 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
698 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
699 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
700 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
701 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
702 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
703 clipdist_mask | (culldist_mask << 8));
704 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
705 rs->pa_cl_clip_cntl |
706 ucp_mask |
707 S_028810_CLIP_DISABLE(window_space));
708
709 /* reuse needs to be set off if we write oViewport */
710 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
711 S_028AB4_REUSE_OFF(info->writes_viewport_index));
712 }
713
714 /*
715 * inferred state between framebuffer and rasterizer
716 */
717 static void si_update_poly_offset_state(struct si_context *sctx)
718 {
719 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
720
721 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
722 si_pm4_bind_state(sctx, poly_offset, NULL);
723 return;
724 }
725
726 /* Use the user format, not db_render_format, so that the polygon
727 * offset behaves as expected by applications.
728 */
729 switch (sctx->framebuffer.state.zsbuf->texture->format) {
730 case PIPE_FORMAT_Z16_UNORM:
731 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
732 break;
733 default: /* 24-bit */
734 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
735 break;
736 case PIPE_FORMAT_Z32_FLOAT:
737 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
738 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
739 break;
740 }
741 }
742
743 /*
744 * Rasterizer
745 */
746
747 static uint32_t si_translate_fill(uint32_t func)
748 {
749 switch(func) {
750 case PIPE_POLYGON_MODE_FILL:
751 return V_028814_X_DRAW_TRIANGLES;
752 case PIPE_POLYGON_MODE_LINE:
753 return V_028814_X_DRAW_LINES;
754 case PIPE_POLYGON_MODE_POINT:
755 return V_028814_X_DRAW_POINTS;
756 default:
757 assert(0);
758 return V_028814_X_DRAW_POINTS;
759 }
760 }
761
762 static void *si_create_rs_state(struct pipe_context *ctx,
763 const struct pipe_rasterizer_state *state)
764 {
765 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
766 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
767 struct si_pm4_state *pm4 = &rs->pm4;
768 unsigned tmp, i;
769 float psize_min, psize_max;
770
771 if (!rs) {
772 return NULL;
773 }
774
775 rs->scissor_enable = state->scissor;
776 rs->clip_halfz = state->clip_halfz;
777 rs->two_side = state->light_twoside;
778 rs->multisample_enable = state->multisample;
779 rs->force_persample_interp = state->force_persample_interp;
780 rs->clip_plane_enable = state->clip_plane_enable;
781 rs->line_stipple_enable = state->line_stipple_enable;
782 rs->poly_stipple_enable = state->poly_stipple_enable;
783 rs->line_smooth = state->line_smooth;
784 rs->poly_smooth = state->poly_smooth;
785 rs->uses_poly_offset = state->offset_point || state->offset_line ||
786 state->offset_tri;
787 rs->clamp_fragment_color = state->clamp_fragment_color;
788 rs->flatshade = state->flatshade;
789 rs->sprite_coord_enable = state->sprite_coord_enable;
790 rs->rasterizer_discard = state->rasterizer_discard;
791 rs->pa_sc_line_stipple = state->line_stipple_enable ?
792 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
793 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
794 rs->pa_cl_clip_cntl =
795 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
796 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
797 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
798 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
799 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
800
801 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
802 S_0286D4_FLAT_SHADE_ENA(1) |
803 S_0286D4_PNT_SPRITE_ENA(1) |
804 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
805 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
806 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
807 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
808 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
809
810 /* point size 12.4 fixed point */
811 tmp = (unsigned)(state->point_size * 8.0);
812 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
813
814 if (state->point_size_per_vertex) {
815 psize_min = util_get_min_point_size(state);
816 psize_max = 8192;
817 } else {
818 /* Force the point size to be as if the vertex output was disabled. */
819 psize_min = state->point_size;
820 psize_max = state->point_size;
821 }
822 /* Divide by two, because 0.5 = 1 pixel. */
823 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
824 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
825 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
826
827 tmp = (unsigned)state->line_width * 8;
828 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
829 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
830 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
831 S_028A48_MSAA_ENABLE(state->multisample ||
832 state->poly_smooth ||
833 state->line_smooth) |
834 S_028A48_VPORT_SCISSOR_ENABLE(1) |
835 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
836
837 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
838 S_028BE4_PIX_CENTER(state->half_pixel_center) |
839 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
840
841 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
842 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
843 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
844 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
845 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
846 S_028814_FACE(!state->front_ccw) |
847 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
848 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
849 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
850 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
851 state->fill_back != PIPE_POLYGON_MODE_FILL) |
852 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
853 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
854 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
855 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
856
857 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
858 for (i = 0; i < 3; i++) {
859 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
860 float offset_units = state->offset_units;
861 float offset_scale = state->offset_scale * 16.0f;
862 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
863
864 if (!state->offset_units_unscaled) {
865 switch (i) {
866 case 0: /* 16-bit zbuffer */
867 offset_units *= 4.0f;
868 pa_su_poly_offset_db_fmt_cntl =
869 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
870 break;
871 case 1: /* 24-bit zbuffer */
872 offset_units *= 2.0f;
873 pa_su_poly_offset_db_fmt_cntl =
874 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
875 break;
876 case 2: /* 32-bit zbuffer */
877 offset_units *= 1.0f;
878 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
879 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
880 break;
881 }
882 }
883
884 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
885 fui(offset_scale));
886 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
887 fui(offset_units));
888 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
889 fui(offset_scale));
890 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
891 fui(offset_units));
892 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
893 pa_su_poly_offset_db_fmt_cntl);
894 }
895
896 return rs;
897 }
898
899 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
900 {
901 struct si_context *sctx = (struct si_context *)ctx;
902 struct si_state_rasterizer *old_rs =
903 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
904 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
905
906 if (!state)
907 return;
908
909 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
910 si_mark_atom_dirty(sctx, &sctx->db_render_state);
911
912 /* Update the small primitive filter workaround if necessary. */
913 if (sctx->b.family >= CHIP_POLARIS10 &&
914 sctx->framebuffer.nr_samples > 1)
915 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
916 }
917
918 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
919
920 si_pm4_bind_state(sctx, rasterizer, rs);
921 si_update_poly_offset_state(sctx);
922
923 si_mark_atom_dirty(sctx, &sctx->clip_regs);
924 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
925 rs->line_stipple_enable;
926 sctx->do_update_shaders = true;
927 }
928
929 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
930 {
931 struct si_context *sctx = (struct si_context *)ctx;
932
933 if (sctx->queued.named.rasterizer == state)
934 si_pm4_bind_state(sctx, poly_offset, NULL);
935 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
936 }
937
938 /*
939 * infeered state between dsa and stencil ref
940 */
941 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
942 {
943 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
944 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
945 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
946
947 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
948 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
949 S_028430_STENCILMASK(dsa->valuemask[0]) |
950 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
951 S_028430_STENCILOPVAL(1));
952 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
953 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
954 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
955 S_028434_STENCILOPVAL_BF(1));
956 }
957
958 static void si_set_stencil_ref(struct pipe_context *ctx,
959 const struct pipe_stencil_ref *state)
960 {
961 struct si_context *sctx = (struct si_context *)ctx;
962
963 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
964 return;
965
966 sctx->stencil_ref.state = *state;
967 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
968 }
969
970
971 /*
972 * DSA
973 */
974
975 static uint32_t si_translate_stencil_op(int s_op)
976 {
977 switch (s_op) {
978 case PIPE_STENCIL_OP_KEEP:
979 return V_02842C_STENCIL_KEEP;
980 case PIPE_STENCIL_OP_ZERO:
981 return V_02842C_STENCIL_ZERO;
982 case PIPE_STENCIL_OP_REPLACE:
983 return V_02842C_STENCIL_REPLACE_TEST;
984 case PIPE_STENCIL_OP_INCR:
985 return V_02842C_STENCIL_ADD_CLAMP;
986 case PIPE_STENCIL_OP_DECR:
987 return V_02842C_STENCIL_SUB_CLAMP;
988 case PIPE_STENCIL_OP_INCR_WRAP:
989 return V_02842C_STENCIL_ADD_WRAP;
990 case PIPE_STENCIL_OP_DECR_WRAP:
991 return V_02842C_STENCIL_SUB_WRAP;
992 case PIPE_STENCIL_OP_INVERT:
993 return V_02842C_STENCIL_INVERT;
994 default:
995 R600_ERR("Unknown stencil op %d", s_op);
996 assert(0);
997 break;
998 }
999 return 0;
1000 }
1001
1002 static void *si_create_dsa_state(struct pipe_context *ctx,
1003 const struct pipe_depth_stencil_alpha_state *state)
1004 {
1005 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1006 struct si_pm4_state *pm4 = &dsa->pm4;
1007 unsigned db_depth_control;
1008 uint32_t db_stencil_control = 0;
1009
1010 if (!dsa) {
1011 return NULL;
1012 }
1013
1014 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1015 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1016 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1017 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1018
1019 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1020 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1021 S_028800_ZFUNC(state->depth.func) |
1022 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1023
1024 /* stencil */
1025 if (state->stencil[0].enabled) {
1026 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1027 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1028 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1029 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1030 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1031
1032 if (state->stencil[1].enabled) {
1033 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1034 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1035 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1036 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1037 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1038 }
1039 }
1040
1041 /* alpha */
1042 if (state->alpha.enabled) {
1043 dsa->alpha_func = state->alpha.func;
1044
1045 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1046 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1047 } else {
1048 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1049 }
1050
1051 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1052 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1053 if (state->depth.bounds_test) {
1054 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1055 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1056 }
1057
1058 return dsa;
1059 }
1060
1061 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1062 {
1063 struct si_context *sctx = (struct si_context *)ctx;
1064 struct si_state_dsa *dsa = state;
1065
1066 if (!state)
1067 return;
1068
1069 si_pm4_bind_state(sctx, dsa, dsa);
1070
1071 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1072 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1073 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1074 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1075 }
1076 sctx->do_update_shaders = true;
1077 }
1078
1079 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1080 {
1081 struct si_context *sctx = (struct si_context *)ctx;
1082 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1083 }
1084
1085 static void *si_create_db_flush_dsa(struct si_context *sctx)
1086 {
1087 struct pipe_depth_stencil_alpha_state dsa = {};
1088
1089 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1090 }
1091
1092 /* DB RENDER STATE */
1093
1094 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1095 {
1096 struct si_context *sctx = (struct si_context*)ctx;
1097
1098 /* Pipeline stat & streamout queries. */
1099 if (enable) {
1100 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1101 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1102 } else {
1103 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1104 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1105 }
1106
1107 /* Occlusion queries. */
1108 if (sctx->occlusion_queries_disabled != !enable) {
1109 sctx->occlusion_queries_disabled = !enable;
1110 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1111 }
1112 }
1113
1114 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1115 {
1116 struct si_context *sctx = (struct si_context*)ctx;
1117
1118 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1119 }
1120
1121 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1122 {
1123 struct si_context *sctx = (struct si_context*)ctx;
1124
1125 st->saved_compute = sctx->cs_shader_state.program;
1126
1127 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1128 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1129 }
1130
1131 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1132 {
1133 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1134 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1135 unsigned db_shader_control;
1136
1137 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1138
1139 /* DB_RENDER_CONTROL */
1140 if (sctx->dbcb_depth_copy_enabled ||
1141 sctx->dbcb_stencil_copy_enabled) {
1142 radeon_emit(cs,
1143 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1144 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1145 S_028000_COPY_CENTROID(1) |
1146 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1147 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1148 radeon_emit(cs,
1149 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1150 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1151 } else {
1152 radeon_emit(cs,
1153 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1154 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1155 }
1156
1157 /* DB_COUNT_CONTROL (occlusion queries) */
1158 if (sctx->b.num_occlusion_queries > 0 &&
1159 !sctx->occlusion_queries_disabled) {
1160 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1161
1162 if (sctx->b.chip_class >= CIK) {
1163 radeon_emit(cs,
1164 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1165 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1166 S_028004_ZPASS_ENABLE(1) |
1167 S_028004_SLICE_EVEN_ENABLE(1) |
1168 S_028004_SLICE_ODD_ENABLE(1));
1169 } else {
1170 radeon_emit(cs,
1171 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1172 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1173 }
1174 } else {
1175 /* Disable occlusion queries. */
1176 if (sctx->b.chip_class >= CIK) {
1177 radeon_emit(cs, 0);
1178 } else {
1179 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1180 }
1181 }
1182
1183 /* DB_RENDER_OVERRIDE2 */
1184 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1185 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1186 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1187 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1188
1189 db_shader_control = sctx->ps_db_shader_control;
1190
1191 /* Bug workaround for smoothing (overrasterization) on SI. */
1192 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1193 db_shader_control &= C_02880C_Z_ORDER;
1194 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1195 }
1196
1197 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1198 if (!rs || !rs->multisample_enable)
1199 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1200
1201 if (sctx->screen->b.has_rbplus &&
1202 !sctx->screen->b.rbplus_allowed)
1203 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1204
1205 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1206 db_shader_control);
1207 }
1208
1209 /*
1210 * format translation
1211 */
1212 static uint32_t si_translate_colorformat(enum pipe_format format)
1213 {
1214 const struct util_format_description *desc = util_format_description(format);
1215
1216 #define HAS_SIZE(x,y,z,w) \
1217 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1218 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1219
1220 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1221 return V_028C70_COLOR_10_11_11;
1222
1223 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1224 return V_028C70_COLOR_INVALID;
1225
1226 /* hw cannot support mixed formats (except depth/stencil, since
1227 * stencil is not written to). */
1228 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1229 return V_028C70_COLOR_INVALID;
1230
1231 switch (desc->nr_channels) {
1232 case 1:
1233 switch (desc->channel[0].size) {
1234 case 8:
1235 return V_028C70_COLOR_8;
1236 case 16:
1237 return V_028C70_COLOR_16;
1238 case 32:
1239 return V_028C70_COLOR_32;
1240 }
1241 break;
1242 case 2:
1243 if (desc->channel[0].size == desc->channel[1].size) {
1244 switch (desc->channel[0].size) {
1245 case 8:
1246 return V_028C70_COLOR_8_8;
1247 case 16:
1248 return V_028C70_COLOR_16_16;
1249 case 32:
1250 return V_028C70_COLOR_32_32;
1251 }
1252 } else if (HAS_SIZE(8,24,0,0)) {
1253 return V_028C70_COLOR_24_8;
1254 } else if (HAS_SIZE(24,8,0,0)) {
1255 return V_028C70_COLOR_8_24;
1256 }
1257 break;
1258 case 3:
1259 if (HAS_SIZE(5,6,5,0)) {
1260 return V_028C70_COLOR_5_6_5;
1261 } else if (HAS_SIZE(32,8,24,0)) {
1262 return V_028C70_COLOR_X24_8_32_FLOAT;
1263 }
1264 break;
1265 case 4:
1266 if (desc->channel[0].size == desc->channel[1].size &&
1267 desc->channel[0].size == desc->channel[2].size &&
1268 desc->channel[0].size == desc->channel[3].size) {
1269 switch (desc->channel[0].size) {
1270 case 4:
1271 return V_028C70_COLOR_4_4_4_4;
1272 case 8:
1273 return V_028C70_COLOR_8_8_8_8;
1274 case 16:
1275 return V_028C70_COLOR_16_16_16_16;
1276 case 32:
1277 return V_028C70_COLOR_32_32_32_32;
1278 }
1279 } else if (HAS_SIZE(5,5,5,1)) {
1280 return V_028C70_COLOR_1_5_5_5;
1281 } else if (HAS_SIZE(10,10,10,2)) {
1282 return V_028C70_COLOR_2_10_10_10;
1283 }
1284 break;
1285 }
1286 return V_028C70_COLOR_INVALID;
1287 }
1288
1289 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1290 {
1291 if (SI_BIG_ENDIAN) {
1292 switch(colorformat) {
1293 /* 8-bit buffers. */
1294 case V_028C70_COLOR_8:
1295 return V_028C70_ENDIAN_NONE;
1296
1297 /* 16-bit buffers. */
1298 case V_028C70_COLOR_5_6_5:
1299 case V_028C70_COLOR_1_5_5_5:
1300 case V_028C70_COLOR_4_4_4_4:
1301 case V_028C70_COLOR_16:
1302 case V_028C70_COLOR_8_8:
1303 return V_028C70_ENDIAN_8IN16;
1304
1305 /* 32-bit buffers. */
1306 case V_028C70_COLOR_8_8_8_8:
1307 case V_028C70_COLOR_2_10_10_10:
1308 case V_028C70_COLOR_8_24:
1309 case V_028C70_COLOR_24_8:
1310 case V_028C70_COLOR_16_16:
1311 return V_028C70_ENDIAN_8IN32;
1312
1313 /* 64-bit buffers. */
1314 case V_028C70_COLOR_16_16_16_16:
1315 return V_028C70_ENDIAN_8IN16;
1316
1317 case V_028C70_COLOR_32_32:
1318 return V_028C70_ENDIAN_8IN32;
1319
1320 /* 128-bit buffers. */
1321 case V_028C70_COLOR_32_32_32_32:
1322 return V_028C70_ENDIAN_8IN32;
1323 default:
1324 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1325 }
1326 } else {
1327 return V_028C70_ENDIAN_NONE;
1328 }
1329 }
1330
1331 static uint32_t si_translate_dbformat(enum pipe_format format)
1332 {
1333 switch (format) {
1334 case PIPE_FORMAT_Z16_UNORM:
1335 return V_028040_Z_16;
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1337 case PIPE_FORMAT_X8Z24_UNORM:
1338 case PIPE_FORMAT_Z24X8_UNORM:
1339 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1340 return V_028040_Z_24; /* deprecated on SI */
1341 case PIPE_FORMAT_Z32_FLOAT:
1342 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1343 return V_028040_Z_32_FLOAT;
1344 default:
1345 return V_028040_Z_INVALID;
1346 }
1347 }
1348
1349 /*
1350 * Texture translation
1351 */
1352
1353 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1354 enum pipe_format format,
1355 const struct util_format_description *desc,
1356 int first_non_void)
1357 {
1358 struct si_screen *sscreen = (struct si_screen*)screen;
1359 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1360 sscreen->b.info.drm_minor >= 31) ||
1361 sscreen->b.info.drm_major == 3;
1362 bool uniform = true;
1363 int i;
1364
1365 /* Colorspace (return non-RGB formats directly). */
1366 switch (desc->colorspace) {
1367 /* Depth stencil formats */
1368 case UTIL_FORMAT_COLORSPACE_ZS:
1369 switch (format) {
1370 case PIPE_FORMAT_Z16_UNORM:
1371 return V_008F14_IMG_DATA_FORMAT_16;
1372 case PIPE_FORMAT_X24S8_UINT:
1373 case PIPE_FORMAT_S8X24_UINT:
1374 /*
1375 * Implemented as an 8_8_8_8 data format to fix texture
1376 * gathers in stencil sampling. This affects at least
1377 * GL45-CTS.texture_cube_map_array.sampling on VI.
1378 */
1379 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1380 case PIPE_FORMAT_Z24X8_UNORM:
1381 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1382 return V_008F14_IMG_DATA_FORMAT_8_24;
1383 case PIPE_FORMAT_X8Z24_UNORM:
1384 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1385 return V_008F14_IMG_DATA_FORMAT_24_8;
1386 case PIPE_FORMAT_S8_UINT:
1387 return V_008F14_IMG_DATA_FORMAT_8;
1388 case PIPE_FORMAT_Z32_FLOAT:
1389 return V_008F14_IMG_DATA_FORMAT_32;
1390 case PIPE_FORMAT_X32_S8X24_UINT:
1391 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1392 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1393 default:
1394 goto out_unknown;
1395 }
1396
1397 case UTIL_FORMAT_COLORSPACE_YUV:
1398 goto out_unknown; /* TODO */
1399
1400 case UTIL_FORMAT_COLORSPACE_SRGB:
1401 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1402 goto out_unknown;
1403 break;
1404
1405 default:
1406 break;
1407 }
1408
1409 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1410 if (!enable_compressed_formats)
1411 goto out_unknown;
1412
1413 switch (format) {
1414 case PIPE_FORMAT_RGTC1_SNORM:
1415 case PIPE_FORMAT_LATC1_SNORM:
1416 case PIPE_FORMAT_RGTC1_UNORM:
1417 case PIPE_FORMAT_LATC1_UNORM:
1418 return V_008F14_IMG_DATA_FORMAT_BC4;
1419 case PIPE_FORMAT_RGTC2_SNORM:
1420 case PIPE_FORMAT_LATC2_SNORM:
1421 case PIPE_FORMAT_RGTC2_UNORM:
1422 case PIPE_FORMAT_LATC2_UNORM:
1423 return V_008F14_IMG_DATA_FORMAT_BC5;
1424 default:
1425 goto out_unknown;
1426 }
1427 }
1428
1429 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1430 (sscreen->b.family == CHIP_STONEY ||
1431 sscreen->b.chip_class >= GFX9)) {
1432 switch (format) {
1433 case PIPE_FORMAT_ETC1_RGB8:
1434 case PIPE_FORMAT_ETC2_RGB8:
1435 case PIPE_FORMAT_ETC2_SRGB8:
1436 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1437 case PIPE_FORMAT_ETC2_RGB8A1:
1438 case PIPE_FORMAT_ETC2_SRGB8A1:
1439 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1440 case PIPE_FORMAT_ETC2_RGBA8:
1441 case PIPE_FORMAT_ETC2_SRGBA8:
1442 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1443 case PIPE_FORMAT_ETC2_R11_UNORM:
1444 case PIPE_FORMAT_ETC2_R11_SNORM:
1445 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1446 case PIPE_FORMAT_ETC2_RG11_UNORM:
1447 case PIPE_FORMAT_ETC2_RG11_SNORM:
1448 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1449 default:
1450 goto out_unknown;
1451 }
1452 }
1453
1454 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1455 if (!enable_compressed_formats)
1456 goto out_unknown;
1457
1458 switch (format) {
1459 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1460 case PIPE_FORMAT_BPTC_SRGBA:
1461 return V_008F14_IMG_DATA_FORMAT_BC7;
1462 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1463 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1464 return V_008F14_IMG_DATA_FORMAT_BC6;
1465 default:
1466 goto out_unknown;
1467 }
1468 }
1469
1470 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1471 switch (format) {
1472 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1473 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1474 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1475 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1476 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1477 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1478 default:
1479 goto out_unknown;
1480 }
1481 }
1482
1483 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1484 if (!enable_compressed_formats)
1485 goto out_unknown;
1486
1487 if (!util_format_s3tc_enabled) {
1488 goto out_unknown;
1489 }
1490
1491 switch (format) {
1492 case PIPE_FORMAT_DXT1_RGB:
1493 case PIPE_FORMAT_DXT1_RGBA:
1494 case PIPE_FORMAT_DXT1_SRGB:
1495 case PIPE_FORMAT_DXT1_SRGBA:
1496 return V_008F14_IMG_DATA_FORMAT_BC1;
1497 case PIPE_FORMAT_DXT3_RGBA:
1498 case PIPE_FORMAT_DXT3_SRGBA:
1499 return V_008F14_IMG_DATA_FORMAT_BC2;
1500 case PIPE_FORMAT_DXT5_RGBA:
1501 case PIPE_FORMAT_DXT5_SRGBA:
1502 return V_008F14_IMG_DATA_FORMAT_BC3;
1503 default:
1504 goto out_unknown;
1505 }
1506 }
1507
1508 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1509 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1510 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1511 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1512 }
1513
1514 /* R8G8Bx_SNORM - TODO CxV8U8 */
1515
1516 /* hw cannot support mixed formats (except depth/stencil, since only
1517 * depth is read).*/
1518 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1519 goto out_unknown;
1520
1521 /* See whether the components are of the same size. */
1522 for (i = 1; i < desc->nr_channels; i++) {
1523 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1524 }
1525
1526 /* Non-uniform formats. */
1527 if (!uniform) {
1528 switch(desc->nr_channels) {
1529 case 3:
1530 if (desc->channel[0].size == 5 &&
1531 desc->channel[1].size == 6 &&
1532 desc->channel[2].size == 5) {
1533 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1534 }
1535 goto out_unknown;
1536 case 4:
1537 if (desc->channel[0].size == 5 &&
1538 desc->channel[1].size == 5 &&
1539 desc->channel[2].size == 5 &&
1540 desc->channel[3].size == 1) {
1541 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1542 }
1543 if (desc->channel[0].size == 10 &&
1544 desc->channel[1].size == 10 &&
1545 desc->channel[2].size == 10 &&
1546 desc->channel[3].size == 2) {
1547 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1548 }
1549 goto out_unknown;
1550 }
1551 goto out_unknown;
1552 }
1553
1554 if (first_non_void < 0 || first_non_void > 3)
1555 goto out_unknown;
1556
1557 /* uniform formats */
1558 switch (desc->channel[first_non_void].size) {
1559 case 4:
1560 switch (desc->nr_channels) {
1561 #if 0 /* Not supported for render targets */
1562 case 2:
1563 return V_008F14_IMG_DATA_FORMAT_4_4;
1564 #endif
1565 case 4:
1566 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1567 }
1568 break;
1569 case 8:
1570 switch (desc->nr_channels) {
1571 case 1:
1572 return V_008F14_IMG_DATA_FORMAT_8;
1573 case 2:
1574 return V_008F14_IMG_DATA_FORMAT_8_8;
1575 case 4:
1576 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1577 }
1578 break;
1579 case 16:
1580 switch (desc->nr_channels) {
1581 case 1:
1582 return V_008F14_IMG_DATA_FORMAT_16;
1583 case 2:
1584 return V_008F14_IMG_DATA_FORMAT_16_16;
1585 case 4:
1586 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1587 }
1588 break;
1589 case 32:
1590 switch (desc->nr_channels) {
1591 case 1:
1592 return V_008F14_IMG_DATA_FORMAT_32;
1593 case 2:
1594 return V_008F14_IMG_DATA_FORMAT_32_32;
1595 #if 0 /* Not supported for render targets */
1596 case 3:
1597 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1598 #endif
1599 case 4:
1600 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1601 }
1602 }
1603
1604 out_unknown:
1605 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1606 return ~0;
1607 }
1608
1609 static unsigned si_tex_wrap(unsigned wrap)
1610 {
1611 switch (wrap) {
1612 default:
1613 case PIPE_TEX_WRAP_REPEAT:
1614 return V_008F30_SQ_TEX_WRAP;
1615 case PIPE_TEX_WRAP_CLAMP:
1616 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1617 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1618 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1619 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1620 return V_008F30_SQ_TEX_CLAMP_BORDER;
1621 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1622 return V_008F30_SQ_TEX_MIRROR;
1623 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1624 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1625 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1626 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1627 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1628 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1629 }
1630 }
1631
1632 static unsigned si_tex_mipfilter(unsigned filter)
1633 {
1634 switch (filter) {
1635 case PIPE_TEX_MIPFILTER_NEAREST:
1636 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1637 case PIPE_TEX_MIPFILTER_LINEAR:
1638 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1639 default:
1640 case PIPE_TEX_MIPFILTER_NONE:
1641 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1642 }
1643 }
1644
1645 static unsigned si_tex_compare(unsigned compare)
1646 {
1647 switch (compare) {
1648 default:
1649 case PIPE_FUNC_NEVER:
1650 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1651 case PIPE_FUNC_LESS:
1652 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1653 case PIPE_FUNC_EQUAL:
1654 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1655 case PIPE_FUNC_LEQUAL:
1656 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1657 case PIPE_FUNC_GREATER:
1658 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1659 case PIPE_FUNC_NOTEQUAL:
1660 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1661 case PIPE_FUNC_GEQUAL:
1662 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1663 case PIPE_FUNC_ALWAYS:
1664 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1665 }
1666 }
1667
1668 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1669 unsigned nr_samples)
1670 {
1671 if (view_target == PIPE_TEXTURE_CUBE ||
1672 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1673 res_target = view_target;
1674 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1675 else if (res_target == PIPE_TEXTURE_CUBE ||
1676 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1677 res_target = PIPE_TEXTURE_2D_ARRAY;
1678
1679 switch (res_target) {
1680 default:
1681 case PIPE_TEXTURE_1D:
1682 return V_008F1C_SQ_RSRC_IMG_1D;
1683 case PIPE_TEXTURE_1D_ARRAY:
1684 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1685 case PIPE_TEXTURE_2D:
1686 case PIPE_TEXTURE_RECT:
1687 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1688 V_008F1C_SQ_RSRC_IMG_2D;
1689 case PIPE_TEXTURE_2D_ARRAY:
1690 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1691 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1692 case PIPE_TEXTURE_3D:
1693 return V_008F1C_SQ_RSRC_IMG_3D;
1694 case PIPE_TEXTURE_CUBE:
1695 case PIPE_TEXTURE_CUBE_ARRAY:
1696 return V_008F1C_SQ_RSRC_IMG_CUBE;
1697 }
1698 }
1699
1700 /*
1701 * Format support testing
1702 */
1703
1704 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1705 {
1706 return si_translate_texformat(screen, format, util_format_description(format),
1707 util_format_get_first_non_void_channel(format)) != ~0U;
1708 }
1709
1710 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1711 const struct util_format_description *desc,
1712 int first_non_void)
1713 {
1714 int i;
1715
1716 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1717 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1718
1719 assert(first_non_void >= 0);
1720
1721 if (desc->nr_channels == 4 &&
1722 desc->channel[0].size == 10 &&
1723 desc->channel[1].size == 10 &&
1724 desc->channel[2].size == 10 &&
1725 desc->channel[3].size == 2)
1726 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1727
1728 /* See whether the components are of the same size. */
1729 for (i = 0; i < desc->nr_channels; i++) {
1730 if (desc->channel[first_non_void].size != desc->channel[i].size)
1731 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1732 }
1733
1734 switch (desc->channel[first_non_void].size) {
1735 case 8:
1736 switch (desc->nr_channels) {
1737 case 1:
1738 case 3: /* 3 loads */
1739 return V_008F0C_BUF_DATA_FORMAT_8;
1740 case 2:
1741 return V_008F0C_BUF_DATA_FORMAT_8_8;
1742 case 4:
1743 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1744 }
1745 break;
1746 case 16:
1747 switch (desc->nr_channels) {
1748 case 1:
1749 case 3: /* 3 loads */
1750 return V_008F0C_BUF_DATA_FORMAT_16;
1751 case 2:
1752 return V_008F0C_BUF_DATA_FORMAT_16_16;
1753 case 4:
1754 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1755 }
1756 break;
1757 case 32:
1758 switch (desc->nr_channels) {
1759 case 1:
1760 return V_008F0C_BUF_DATA_FORMAT_32;
1761 case 2:
1762 return V_008F0C_BUF_DATA_FORMAT_32_32;
1763 case 3:
1764 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1765 case 4:
1766 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1767 }
1768 break;
1769 case 64:
1770 /* Legacy double formats. */
1771 switch (desc->nr_channels) {
1772 case 1: /* 1 load */
1773 return V_008F0C_BUF_DATA_FORMAT_32_32;
1774 case 2: /* 1 load */
1775 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1776 case 3: /* 3 loads */
1777 return V_008F0C_BUF_DATA_FORMAT_32_32;
1778 case 4: /* 2 loads */
1779 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1780 }
1781 break;
1782 }
1783
1784 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1785 }
1786
1787 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1788 const struct util_format_description *desc,
1789 int first_non_void)
1790 {
1791 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1792 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1793
1794 assert(first_non_void >= 0);
1795
1796 switch (desc->channel[first_non_void].type) {
1797 case UTIL_FORMAT_TYPE_SIGNED:
1798 case UTIL_FORMAT_TYPE_FIXED:
1799 if (desc->channel[first_non_void].size >= 32 ||
1800 desc->channel[first_non_void].pure_integer)
1801 return V_008F0C_BUF_NUM_FORMAT_SINT;
1802 else if (desc->channel[first_non_void].normalized)
1803 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1804 else
1805 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1806 break;
1807 case UTIL_FORMAT_TYPE_UNSIGNED:
1808 if (desc->channel[first_non_void].size >= 32 ||
1809 desc->channel[first_non_void].pure_integer)
1810 return V_008F0C_BUF_NUM_FORMAT_UINT;
1811 else if (desc->channel[first_non_void].normalized)
1812 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1813 else
1814 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1815 break;
1816 case UTIL_FORMAT_TYPE_FLOAT:
1817 default:
1818 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1819 }
1820 }
1821
1822 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1823 enum pipe_format format,
1824 unsigned usage)
1825 {
1826 const struct util_format_description *desc;
1827 int first_non_void;
1828 unsigned data_format;
1829
1830 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1831 PIPE_BIND_SAMPLER_VIEW |
1832 PIPE_BIND_VERTEX_BUFFER)) == 0);
1833
1834 desc = util_format_description(format);
1835
1836 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1837 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1838 * for read-only access (with caveats surrounding bounds checks), but
1839 * obviously fails for write access which we have to implement for
1840 * shader images. Luckily, OpenGL doesn't expect this to be supported
1841 * anyway, and so the only impact is on PBO uploads / downloads, which
1842 * shouldn't be expected to be fast for GL_RGB anyway.
1843 */
1844 if (desc->block.bits == 3 * 8 ||
1845 desc->block.bits == 3 * 16) {
1846 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1847 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1848 if (!usage)
1849 return 0;
1850 }
1851 }
1852
1853 first_non_void = util_format_get_first_non_void_channel(format);
1854 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1855 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1856 return 0;
1857
1858 return usage;
1859 }
1860
1861 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1862 {
1863 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1864 r600_translate_colorswap(format, false) != ~0U;
1865 }
1866
1867 static bool si_is_zs_format_supported(enum pipe_format format)
1868 {
1869 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1870 }
1871
1872 static boolean si_is_format_supported(struct pipe_screen *screen,
1873 enum pipe_format format,
1874 enum pipe_texture_target target,
1875 unsigned sample_count,
1876 unsigned usage)
1877 {
1878 unsigned retval = 0;
1879
1880 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1881 R600_ERR("r600: unsupported texture type %d\n", target);
1882 return false;
1883 }
1884
1885 if (!util_format_is_supported(format, usage))
1886 return false;
1887
1888 if (sample_count > 1) {
1889 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1890 return false;
1891
1892 if (usage & PIPE_BIND_SHADER_IMAGE)
1893 return false;
1894
1895 switch (sample_count) {
1896 case 2:
1897 case 4:
1898 case 8:
1899 break;
1900 case 16:
1901 if (format == PIPE_FORMAT_NONE)
1902 return true;
1903 else
1904 return false;
1905 default:
1906 return false;
1907 }
1908 }
1909
1910 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1911 PIPE_BIND_SHADER_IMAGE)) {
1912 if (target == PIPE_BUFFER) {
1913 retval |= si_is_vertex_format_supported(
1914 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1915 PIPE_BIND_SHADER_IMAGE));
1916 } else {
1917 if (si_is_sampler_format_supported(screen, format))
1918 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1919 PIPE_BIND_SHADER_IMAGE);
1920 }
1921 }
1922
1923 if ((usage & (PIPE_BIND_RENDER_TARGET |
1924 PIPE_BIND_DISPLAY_TARGET |
1925 PIPE_BIND_SCANOUT |
1926 PIPE_BIND_SHARED |
1927 PIPE_BIND_BLENDABLE)) &&
1928 si_is_colorbuffer_format_supported(format)) {
1929 retval |= usage &
1930 (PIPE_BIND_RENDER_TARGET |
1931 PIPE_BIND_DISPLAY_TARGET |
1932 PIPE_BIND_SCANOUT |
1933 PIPE_BIND_SHARED);
1934 if (!util_format_is_pure_integer(format) &&
1935 !util_format_is_depth_or_stencil(format))
1936 retval |= usage & PIPE_BIND_BLENDABLE;
1937 }
1938
1939 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1940 si_is_zs_format_supported(format)) {
1941 retval |= PIPE_BIND_DEPTH_STENCIL;
1942 }
1943
1944 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1945 retval |= si_is_vertex_format_supported(screen, format,
1946 PIPE_BIND_VERTEX_BUFFER);
1947 }
1948
1949 if ((usage & PIPE_BIND_LINEAR) &&
1950 !util_format_is_compressed(format) &&
1951 !(usage & PIPE_BIND_DEPTH_STENCIL))
1952 retval |= PIPE_BIND_LINEAR;
1953
1954 return retval == usage;
1955 }
1956
1957 /*
1958 * framebuffer handling
1959 */
1960
1961 static void si_choose_spi_color_formats(struct r600_surface *surf,
1962 unsigned format, unsigned swap,
1963 unsigned ntype, bool is_depth)
1964 {
1965 /* Alpha is needed for alpha-to-coverage.
1966 * Blending may be with or without alpha.
1967 */
1968 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1969 unsigned alpha = 0; /* exports alpha, but may not support blending */
1970 unsigned blend = 0; /* supports blending, but may not export alpha */
1971 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1972
1973 /* Choose the SPI color formats. These are required values for RB+.
1974 * Other chips have multiple choices, though they are not necessarily better.
1975 */
1976 switch (format) {
1977 case V_028C70_COLOR_5_6_5:
1978 case V_028C70_COLOR_1_5_5_5:
1979 case V_028C70_COLOR_5_5_5_1:
1980 case V_028C70_COLOR_4_4_4_4:
1981 case V_028C70_COLOR_10_11_11:
1982 case V_028C70_COLOR_11_11_10:
1983 case V_028C70_COLOR_8:
1984 case V_028C70_COLOR_8_8:
1985 case V_028C70_COLOR_8_8_8_8:
1986 case V_028C70_COLOR_10_10_10_2:
1987 case V_028C70_COLOR_2_10_10_10:
1988 if (ntype == V_028C70_NUMBER_UINT)
1989 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1990 else if (ntype == V_028C70_NUMBER_SINT)
1991 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1992 else
1993 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1994 break;
1995
1996 case V_028C70_COLOR_16:
1997 case V_028C70_COLOR_16_16:
1998 case V_028C70_COLOR_16_16_16_16:
1999 if (ntype == V_028C70_NUMBER_UNORM ||
2000 ntype == V_028C70_NUMBER_SNORM) {
2001 /* UNORM16 and SNORM16 don't support blending */
2002 if (ntype == V_028C70_NUMBER_UNORM)
2003 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2004 else
2005 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2006
2007 /* Use 32 bits per channel for blending. */
2008 if (format == V_028C70_COLOR_16) {
2009 if (swap == V_028C70_SWAP_STD) { /* R */
2010 blend = V_028714_SPI_SHADER_32_R;
2011 blend_alpha = V_028714_SPI_SHADER_32_AR;
2012 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2013 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2014 else
2015 assert(0);
2016 } else if (format == V_028C70_COLOR_16_16) {
2017 if (swap == V_028C70_SWAP_STD) { /* RG */
2018 blend = V_028714_SPI_SHADER_32_GR;
2019 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2020 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2021 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2022 else
2023 assert(0);
2024 } else /* 16_16_16_16 */
2025 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2026 } else if (ntype == V_028C70_NUMBER_UINT)
2027 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2028 else if (ntype == V_028C70_NUMBER_SINT)
2029 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2030 else if (ntype == V_028C70_NUMBER_FLOAT)
2031 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2032 else
2033 assert(0);
2034 break;
2035
2036 case V_028C70_COLOR_32:
2037 if (swap == V_028C70_SWAP_STD) { /* R */
2038 blend = normal = V_028714_SPI_SHADER_32_R;
2039 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2040 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2041 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2042 else
2043 assert(0);
2044 break;
2045
2046 case V_028C70_COLOR_32_32:
2047 if (swap == V_028C70_SWAP_STD) { /* RG */
2048 blend = normal = V_028714_SPI_SHADER_32_GR;
2049 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2050 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2051 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2052 else
2053 assert(0);
2054 break;
2055
2056 case V_028C70_COLOR_32_32_32_32:
2057 case V_028C70_COLOR_8_24:
2058 case V_028C70_COLOR_24_8:
2059 case V_028C70_COLOR_X24_8_32_FLOAT:
2060 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2061 break;
2062
2063 default:
2064 assert(0);
2065 return;
2066 }
2067
2068 /* The DB->CB copy needs 32_ABGR. */
2069 if (is_depth)
2070 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2071
2072 surf->spi_shader_col_format = normal;
2073 surf->spi_shader_col_format_alpha = alpha;
2074 surf->spi_shader_col_format_blend = blend;
2075 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2076 }
2077
2078 static void si_initialize_color_surface(struct si_context *sctx,
2079 struct r600_surface *surf)
2080 {
2081 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2082 unsigned color_info, color_attrib, color_view;
2083 unsigned format, swap, ntype, endian;
2084 const struct util_format_description *desc;
2085 int i;
2086 unsigned blend_clamp = 0, blend_bypass = 0;
2087
2088 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2089 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2090
2091 desc = util_format_description(surf->base.format);
2092 for (i = 0; i < 4; i++) {
2093 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2094 break;
2095 }
2096 }
2097 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2098 ntype = V_028C70_NUMBER_FLOAT;
2099 } else {
2100 ntype = V_028C70_NUMBER_UNORM;
2101 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2102 ntype = V_028C70_NUMBER_SRGB;
2103 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2104 if (desc->channel[i].pure_integer) {
2105 ntype = V_028C70_NUMBER_SINT;
2106 } else {
2107 assert(desc->channel[i].normalized);
2108 ntype = V_028C70_NUMBER_SNORM;
2109 }
2110 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2111 if (desc->channel[i].pure_integer) {
2112 ntype = V_028C70_NUMBER_UINT;
2113 } else {
2114 assert(desc->channel[i].normalized);
2115 ntype = V_028C70_NUMBER_UNORM;
2116 }
2117 }
2118 }
2119
2120 format = si_translate_colorformat(surf->base.format);
2121 if (format == V_028C70_COLOR_INVALID) {
2122 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2123 }
2124 assert(format != V_028C70_COLOR_INVALID);
2125 swap = r600_translate_colorswap(surf->base.format, false);
2126 endian = si_colorformat_endian_swap(format);
2127
2128 /* blend clamp should be set for all NORM/SRGB types */
2129 if (ntype == V_028C70_NUMBER_UNORM ||
2130 ntype == V_028C70_NUMBER_SNORM ||
2131 ntype == V_028C70_NUMBER_SRGB)
2132 blend_clamp = 1;
2133
2134 /* set blend bypass according to docs if SINT/UINT or
2135 8/24 COLOR variants */
2136 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2137 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2138 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2139 blend_clamp = 0;
2140 blend_bypass = 1;
2141 }
2142
2143 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2144 if (format == V_028C70_COLOR_8 ||
2145 format == V_028C70_COLOR_8_8 ||
2146 format == V_028C70_COLOR_8_8_8_8)
2147 surf->color_is_int8 = true;
2148 else if (format == V_028C70_COLOR_10_10_10_2 ||
2149 format == V_028C70_COLOR_2_10_10_10)
2150 surf->color_is_int10 = true;
2151 }
2152
2153 color_info = S_028C70_FORMAT(format) |
2154 S_028C70_COMP_SWAP(swap) |
2155 S_028C70_BLEND_CLAMP(blend_clamp) |
2156 S_028C70_BLEND_BYPASS(blend_bypass) |
2157 S_028C70_SIMPLE_FLOAT(1) |
2158 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2159 ntype != V_028C70_NUMBER_SNORM &&
2160 ntype != V_028C70_NUMBER_SRGB &&
2161 format != V_028C70_COLOR_8_24 &&
2162 format != V_028C70_COLOR_24_8) |
2163 S_028C70_NUMBER_TYPE(ntype) |
2164 S_028C70_ENDIAN(endian);
2165
2166 /* Intensity is implemented as Red, so treat it that way. */
2167 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2168 util_format_is_intensity(surf->base.format));
2169
2170 if (rtex->resource.b.b.nr_samples > 1) {
2171 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2172
2173 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2174 S_028C74_NUM_FRAGMENTS(log_samples);
2175
2176 if (rtex->fmask.size) {
2177 color_info |= S_028C70_COMPRESSION(1);
2178 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2179
2180 if (sctx->b.chip_class == SI) {
2181 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2182 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2183 }
2184 }
2185 }
2186
2187 surf->cb_color_view = color_view;
2188 surf->cb_color_info = color_info;
2189 surf->cb_color_attrib = color_attrib;
2190
2191 if (sctx->b.chip_class >= VI) {
2192 unsigned max_uncompressed_block_size = 2;
2193
2194 if (rtex->resource.b.b.nr_samples > 1) {
2195 if (rtex->surface.bpe == 1)
2196 max_uncompressed_block_size = 0;
2197 else if (rtex->surface.bpe == 2)
2198 max_uncompressed_block_size = 1;
2199 }
2200
2201 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2202 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2203 }
2204
2205 /* This must be set for fast clear to work without FMASK. */
2206 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2207 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2208 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2209 }
2210
2211 if (sctx->b.chip_class >= GFX9) {
2212 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2213 unsigned type;
2214
2215 switch (rtex->resource.b.b.target) {
2216 case PIPE_TEXTURE_1D:
2217 case PIPE_TEXTURE_1D_ARRAY:
2218 type = V_028C74_1D;
2219 break;
2220 default:
2221 type = V_028C74_2D;
2222 break;
2223 case PIPE_TEXTURE_3D:
2224 type = V_028C74_3D;
2225 break;
2226 }
2227
2228 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2229 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2230 S_028C74_RESOURCE_TYPE(type);
2231 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(rtex->resource.b.b.width0 - 1) |
2232 S_028C68_MIP0_HEIGHT(rtex->resource.b.b.height0 - 1) |
2233 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2234 }
2235
2236 /* Determine pixel shader export format */
2237 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2238
2239 surf->color_initialized = true;
2240 }
2241
2242 static void si_init_depth_surface(struct si_context *sctx,
2243 struct r600_surface *surf)
2244 {
2245 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2246 unsigned level = surf->base.u.tex.level;
2247 unsigned format, stencil_format;
2248 uint32_t z_info, s_info;
2249
2250 format = si_translate_dbformat(rtex->db_render_format);
2251 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2252 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2253
2254 assert(format != V_028040_Z_INVALID);
2255 if (format == V_028040_Z_INVALID)
2256 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2257
2258 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2259 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2260 surf->db_htile_data_base = 0;
2261 surf->db_htile_surface = 0;
2262
2263 if (sctx->b.chip_class >= GFX9) {
2264 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2265 surf->db_stencil_base = (rtex->resource.gpu_address +
2266 rtex->surface.u.gfx9.stencil_offset) >> 8;
2267 z_info = S_028038_FORMAT(format) |
2268 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2269 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2270 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2271 s_info = S_02803C_FORMAT(stencil_format) |
2272 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2273 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2274 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2275 surf->db_depth_view |= S_028008_MIPID(level);
2276 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2277 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2278
2279 /* Only use HTILE for the first level. */
2280 if (rtex->htile_buffer && !level) {
2281 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2282 S_028038_ALLOW_EXPCLEAR(1);
2283
2284 if (rtex->tc_compatible_htile) {
2285 unsigned max_zplanes = 4;
2286
2287 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2288 rtex->resource.b.b.nr_samples > 1)
2289 max_zplanes = 2;
2290
2291 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2292 S_028038_ITERATE_FLUSH(1);
2293 s_info |= S_02803C_ITERATE_FLUSH(1);
2294 }
2295
2296 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2297 /* Stencil buffer workaround ported from the SI-CI-VI code.
2298 * See that for explanation.
2299 */
2300 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2301 } else {
2302 /* Use all HTILE for depth if there's no stencil. */
2303 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2304 }
2305
2306 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2307 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2308 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2309 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2310 }
2311 } else {
2312 /* SI-CI-VI */
2313 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2314
2315 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2316
2317 surf->db_depth_base = (rtex->resource.gpu_address +
2318 rtex->surface.u.legacy.level[level].offset) >> 8;
2319 surf->db_stencil_base = (rtex->resource.gpu_address +
2320 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2321
2322 z_info = S_028040_FORMAT(format) |
2323 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2324 s_info = S_028044_FORMAT(stencil_format);
2325 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2326
2327 if (sctx->b.chip_class >= CIK) {
2328 struct radeon_info *info = &sctx->screen->b.info;
2329 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2330 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2331 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2332 unsigned tile_mode = info->si_tile_mode_array[index];
2333 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2334 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2335
2336 surf->db_depth_info |=
2337 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2338 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2339 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2340 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2341 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2342 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2343 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2344 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2345 } else {
2346 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2347 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2348 tile_mode_index = si_tile_mode_index(rtex, level, true);
2349 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2350 }
2351
2352 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2353 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2354 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2355 levelinfo->nblk_y) / 64 - 1);
2356
2357 /* Only use HTILE for the first level. */
2358 if (rtex->htile_buffer && !level) {
2359 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2360 S_028040_ALLOW_EXPCLEAR(1);
2361
2362 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2363 /* Workaround: For a not yet understood reason, the
2364 * combination of MSAA, fast stencil clear and stencil
2365 * decompress messes with subsequent stencil buffer
2366 * uses. Problem was reproduced on Verde, Bonaire,
2367 * Tonga, and Carrizo.
2368 *
2369 * Disabling EXPCLEAR works around the problem.
2370 *
2371 * Check piglit's arb_texture_multisample-stencil-clear
2372 * test if you want to try changing this.
2373 */
2374 if (rtex->resource.b.b.nr_samples <= 1)
2375 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2376 } else if (!rtex->tc_compatible_htile) {
2377 /* Use all of the htile_buffer for depth if there's no stencil.
2378 * This must not be set when TC-compatible HTILE is enabled
2379 * due to a hw bug.
2380 */
2381 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2382 }
2383
2384 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2385 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2386
2387 if (rtex->tc_compatible_htile) {
2388 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2389
2390 if (rtex->resource.b.b.nr_samples <= 1)
2391 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2392 else if (rtex->resource.b.b.nr_samples <= 4)
2393 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2394 else
2395 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2396 }
2397 }
2398 }
2399
2400 surf->db_z_info = z_info;
2401 surf->db_stencil_info = s_info;
2402
2403 surf->depth_initialized = true;
2404 }
2405
2406 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2407 {
2408 for (int i = 0; i < state->nr_cbufs; ++i) {
2409 struct r600_surface *surf = NULL;
2410 struct r600_texture *rtex;
2411
2412 if (!state->cbufs[i])
2413 continue;
2414 surf = (struct r600_surface*)state->cbufs[i];
2415 rtex = (struct r600_texture*)surf->base.texture;
2416
2417 p_atomic_dec(&rtex->framebuffers_bound);
2418 }
2419 }
2420
2421 static void si_set_framebuffer_state(struct pipe_context *ctx,
2422 const struct pipe_framebuffer_state *state)
2423 {
2424 struct si_context *sctx = (struct si_context *)ctx;
2425 struct pipe_constant_buffer constbuf = {0};
2426 struct r600_surface *surf = NULL;
2427 struct r600_texture *rtex;
2428 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2429 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2430 int i;
2431
2432 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2433 if (!sctx->framebuffer.state.cbufs[i])
2434 continue;
2435
2436 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2437 if (rtex->dcc_gather_statistics)
2438 vi_separate_dcc_stop_query(ctx, rtex);
2439 }
2440
2441 /* Only flush TC when changing the framebuffer state, because
2442 * the only client not using TC that can change textures is
2443 * the framebuffer.
2444 *
2445 * Flush all CB and DB caches here because all buffers can be used
2446 * for write by both TC (with shader image stores) and CB/DB.
2447 */
2448 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2449 SI_CONTEXT_INV_GLOBAL_L2 |
2450 SI_CONTEXT_FLUSH_AND_INV_CB |
2451 SI_CONTEXT_FLUSH_AND_INV_DB |
2452 SI_CONTEXT_CS_PARTIAL_FLUSH;
2453
2454 /* Take the maximum of the old and new count. If the new count is lower,
2455 * dirtying is needed to disable the unbound colorbuffers.
2456 */
2457 sctx->framebuffer.dirty_cbufs |=
2458 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2459 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2460
2461 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2462 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2463
2464 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2465 sctx->framebuffer.spi_shader_col_format = 0;
2466 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2467 sctx->framebuffer.spi_shader_col_format_blend = 0;
2468 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2469 sctx->framebuffer.color_is_int8 = 0;
2470 sctx->framebuffer.color_is_int10 = 0;
2471
2472 sctx->framebuffer.compressed_cb_mask = 0;
2473 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2474 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2475 sctx->framebuffer.any_dst_linear = false;
2476
2477 for (i = 0; i < state->nr_cbufs; i++) {
2478 if (!state->cbufs[i])
2479 continue;
2480
2481 surf = (struct r600_surface*)state->cbufs[i];
2482 rtex = (struct r600_texture*)surf->base.texture;
2483
2484 if (!surf->color_initialized) {
2485 si_initialize_color_surface(sctx, surf);
2486 }
2487
2488 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2489 sctx->framebuffer.spi_shader_col_format |=
2490 surf->spi_shader_col_format << (i * 4);
2491 sctx->framebuffer.spi_shader_col_format_alpha |=
2492 surf->spi_shader_col_format_alpha << (i * 4);
2493 sctx->framebuffer.spi_shader_col_format_blend |=
2494 surf->spi_shader_col_format_blend << (i * 4);
2495 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2496 surf->spi_shader_col_format_blend_alpha << (i * 4);
2497
2498 if (surf->color_is_int8)
2499 sctx->framebuffer.color_is_int8 |= 1 << i;
2500 if (surf->color_is_int10)
2501 sctx->framebuffer.color_is_int10 |= 1 << i;
2502
2503 if (rtex->fmask.size) {
2504 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2505 }
2506
2507 if (rtex->surface.is_linear)
2508 sctx->framebuffer.any_dst_linear = true;
2509
2510 r600_context_add_resource_size(ctx, surf->base.texture);
2511
2512 p_atomic_inc(&rtex->framebuffers_bound);
2513
2514 if (rtex->dcc_gather_statistics) {
2515 /* Dirty tracking must be enabled for DCC usage analysis. */
2516 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2517 vi_separate_dcc_start_query(ctx, rtex);
2518 }
2519 }
2520
2521 if (state->zsbuf) {
2522 surf = (struct r600_surface*)state->zsbuf;
2523 rtex = (struct r600_texture*)surf->base.texture;
2524
2525 if (!surf->depth_initialized) {
2526 si_init_depth_surface(sctx, surf);
2527 }
2528 r600_context_add_resource_size(ctx, surf->base.texture);
2529 }
2530
2531 si_update_poly_offset_state(sctx);
2532 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2533 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2534
2535 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2536 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2537
2538 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2539 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2540 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2541
2542 /* Set sample locations as fragment shader constants. */
2543 switch (sctx->framebuffer.nr_samples) {
2544 case 1:
2545 constbuf.user_buffer = sctx->b.sample_locations_1x;
2546 break;
2547 case 2:
2548 constbuf.user_buffer = sctx->b.sample_locations_2x;
2549 break;
2550 case 4:
2551 constbuf.user_buffer = sctx->b.sample_locations_4x;
2552 break;
2553 case 8:
2554 constbuf.user_buffer = sctx->b.sample_locations_8x;
2555 break;
2556 case 16:
2557 constbuf.user_buffer = sctx->b.sample_locations_16x;
2558 break;
2559 default:
2560 R600_ERR("Requested an invalid number of samples %i.\n",
2561 sctx->framebuffer.nr_samples);
2562 assert(0);
2563 }
2564 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2565 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2566
2567 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2568 }
2569
2570 sctx->need_check_render_feedback = true;
2571 sctx->do_update_shaders = true;
2572 sctx->framebuffer.do_update_surf_dirtiness = true;
2573 }
2574
2575 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2576 {
2577 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2578 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2579 unsigned i, nr_cbufs = state->nr_cbufs;
2580 struct r600_texture *tex = NULL;
2581 struct r600_surface *cb = NULL;
2582 unsigned cb_color_info = 0;
2583
2584 /* Colorbuffers. */
2585 for (i = 0; i < nr_cbufs; i++) {
2586 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2587 unsigned cb_color_attrib;
2588
2589 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2590 continue;
2591
2592 cb = (struct r600_surface*)state->cbufs[i];
2593 if (!cb) {
2594 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2595 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2596 continue;
2597 }
2598
2599 tex = (struct r600_texture *)cb->base.texture;
2600 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2601 &tex->resource, RADEON_USAGE_READWRITE,
2602 tex->resource.b.b.nr_samples > 1 ?
2603 RADEON_PRIO_COLOR_BUFFER_MSAA :
2604 RADEON_PRIO_COLOR_BUFFER);
2605
2606 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2607 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2608 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2609 RADEON_PRIO_CMASK);
2610 }
2611
2612 if (tex->dcc_separate_buffer)
2613 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2614 tex->dcc_separate_buffer,
2615 RADEON_USAGE_READWRITE,
2616 RADEON_PRIO_DCC);
2617
2618 /* Compute mutable surface parameters. */
2619 cb_color_base = tex->resource.gpu_address >> 8;
2620 cb_color_fmask = cb_color_base;
2621 cb_dcc_base = 0;
2622 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2623 cb_color_attrib = cb->cb_color_attrib;
2624
2625 if (tex->fmask.size)
2626 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2627
2628 /* Set up DCC. */
2629 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2630 bool is_msaa_resolve_dst = state->cbufs[0] &&
2631 state->cbufs[0]->texture->nr_samples > 1 &&
2632 state->cbufs[1] == &cb->base &&
2633 state->cbufs[1]->texture->nr_samples <= 1;
2634
2635 if (!is_msaa_resolve_dst)
2636 cb_color_info |= S_028C70_DCC_ENABLE(1);
2637
2638 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2639 tex->dcc_offset) >> 8;
2640 }
2641
2642 if (sctx->b.chip_class >= GFX9) {
2643 struct gfx9_surf_meta_flags meta;
2644
2645 if (tex->dcc_offset)
2646 meta = tex->surface.u.gfx9.dcc;
2647 else
2648 meta = tex->surface.u.gfx9.cmask;
2649
2650 /* Set mutable surface parameters. */
2651 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2652 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2653 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2654 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2655
2656 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2657 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2658 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2659 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2660 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2661 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2662 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2663 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2664 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2665 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2666 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2667 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2668 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2669 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2670 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2671 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2672
2673 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2674 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2675 } else {
2676 /* Compute mutable surface parameters (SI-CI-VI). */
2677 const struct legacy_surf_level *level_info =
2678 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2679 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2680 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2681
2682 cb_color_base += level_info->offset >> 8;
2683 if (cb_dcc_base)
2684 cb_dcc_base += level_info->dcc_offset >> 8;
2685
2686 pitch_tile_max = level_info->nblk_x / 8 - 1;
2687 slice_tile_max = level_info->nblk_x *
2688 level_info->nblk_y / 64 - 1;
2689 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2690
2691 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2692 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2693 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2694
2695 if (tex->fmask.size) {
2696 if (sctx->b.chip_class >= CIK)
2697 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2698 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2699 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2700 } else {
2701 /* This must be set for fast clear to work without FMASK. */
2702 if (sctx->b.chip_class >= CIK)
2703 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2704 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2705 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2706 }
2707
2708 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2709 sctx->b.chip_class >= VI ? 14 : 13);
2710 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2711 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2712 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2713 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2714 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2715 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2716 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2717 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2718 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2719 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2720 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2721 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2722 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2723
2724 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2725 radeon_emit(cs, cb_dcc_base);
2726 }
2727 }
2728 for (; i < 8 ; i++)
2729 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2730 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2731
2732 /* ZS buffer. */
2733 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2734 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2735 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2736
2737 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2738 &rtex->resource, RADEON_USAGE_READWRITE,
2739 zb->base.texture->nr_samples > 1 ?
2740 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2741 RADEON_PRIO_DEPTH_BUFFER);
2742
2743 if (zb->db_htile_data_base) {
2744 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2745 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2746 RADEON_PRIO_HTILE);
2747 }
2748
2749 if (sctx->b.chip_class >= GFX9) {
2750 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2751 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2752 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2753 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2754
2755 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2756 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2757 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2758 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2759 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2760 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2761 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2762 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2763 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2764 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2765 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2766 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2767
2768 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2769 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2770 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2771 } else {
2772 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2773
2774 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2775 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2776 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2777 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2778 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2779 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2780 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2781 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2782 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2783 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2784 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2785 }
2786
2787 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2788 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2789 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2790
2791 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2792 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2793 } else if (sctx->framebuffer.dirty_zsbuf) {
2794 if (sctx->b.chip_class >= GFX9)
2795 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2796 else
2797 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2798
2799 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2800 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2801 }
2802
2803 /* Framebuffer dimensions. */
2804 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2805 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2806 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2807
2808 sctx->framebuffer.dirty_cbufs = 0;
2809 sctx->framebuffer.dirty_zsbuf = false;
2810 }
2811
2812 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2813 struct r600_atom *atom)
2814 {
2815 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2816 unsigned nr_samples = sctx->framebuffer.nr_samples;
2817
2818 /* Smoothing (only possible with nr_samples == 1) uses the same
2819 * sample locations as the MSAA it simulates.
2820 */
2821 if (nr_samples <= 1 && sctx->smoothing_enabled)
2822 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2823
2824 /* On Polaris, the small primitive filter uses the sample locations
2825 * even when MSAA is off, so we need to make sure they're set to 0.
2826 */
2827 if (sctx->b.family >= CHIP_POLARIS10)
2828 nr_samples = MAX2(nr_samples, 1);
2829
2830 if (nr_samples >= 1 &&
2831 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2832 sctx->msaa_sample_locs.nr_samples = nr_samples;
2833 cayman_emit_msaa_sample_locs(cs, nr_samples);
2834 }
2835
2836 if (sctx->b.family >= CHIP_POLARIS10) {
2837 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2838 unsigned small_prim_filter_cntl =
2839 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2840 S_028830_LINE_FILTER_DISABLE(sctx->b.chip_class == VI); /* line bug */
2841
2842 /* The alternative of setting sample locations to 0 would
2843 * require a DB flush to avoid Z errors, see
2844 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2845 */
2846 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2847 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2848
2849 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2850 small_prim_filter_cntl);
2851 }
2852 }
2853
2854 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2855 {
2856 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2857 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2858 /* 33% faster rendering to linear color buffers */
2859 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2860 unsigned sc_mode_cntl_1 =
2861 S_028A4C_WALK_SIZE(dst_is_linear) |
2862 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2863 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2864 /* always 1: */
2865 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2866 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2867 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2868 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2869 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2870 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2871
2872 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2873 sctx->ps_iter_samples,
2874 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2875 sc_mode_cntl_1);
2876 }
2877
2878 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2879 {
2880 struct si_context *sctx = (struct si_context *)ctx;
2881
2882 if (sctx->ps_iter_samples == min_samples)
2883 return;
2884
2885 sctx->ps_iter_samples = min_samples;
2886 sctx->do_update_shaders = true;
2887
2888 if (sctx->framebuffer.nr_samples > 1)
2889 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2890 }
2891
2892 /*
2893 * Samplers
2894 */
2895
2896 /**
2897 * Build the sampler view descriptor for a buffer texture.
2898 * @param state 256-bit descriptor; only the high 128 bits are filled in
2899 */
2900 void
2901 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2902 enum pipe_format format,
2903 unsigned offset, unsigned size,
2904 uint32_t *state)
2905 {
2906 const struct util_format_description *desc;
2907 int first_non_void;
2908 unsigned stride;
2909 unsigned num_records;
2910 unsigned num_format, data_format;
2911
2912 desc = util_format_description(format);
2913 first_non_void = util_format_get_first_non_void_channel(format);
2914 stride = desc->block.bits / 8;
2915 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2916 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2917
2918 num_records = size / stride;
2919 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2920
2921 if (screen->b.chip_class == VI)
2922 num_records *= stride;
2923
2924 state[4] = 0;
2925 state[5] = S_008F04_STRIDE(stride);
2926 state[6] = num_records;
2927 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2928 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2929 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2930 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2931 S_008F0C_NUM_FORMAT(num_format) |
2932 S_008F0C_DATA_FORMAT(data_format);
2933 }
2934
2935 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
2936 {
2937 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2938
2939 if (swizzle[3] == PIPE_SWIZZLE_X) {
2940 /* For the pre-defined border color values (white, opaque
2941 * black, transparent black), the only thing that matters is
2942 * that the alpha channel winds up in the correct place
2943 * (because the RGB channels are all the same) so either of
2944 * these enumerations will work.
2945 */
2946 if (swizzle[2] == PIPE_SWIZZLE_Y)
2947 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
2948 else
2949 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
2950 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
2951 if (swizzle[1] == PIPE_SWIZZLE_Y)
2952 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2953 else
2954 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
2955 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
2956 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
2957 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
2958 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
2959 }
2960
2961 return bc_swizzle;
2962 }
2963
2964 /**
2965 * Build the sampler view descriptor for a texture.
2966 */
2967 void
2968 si_make_texture_descriptor(struct si_screen *screen,
2969 struct r600_texture *tex,
2970 bool sampler,
2971 enum pipe_texture_target target,
2972 enum pipe_format pipe_format,
2973 const unsigned char state_swizzle[4],
2974 unsigned first_level, unsigned last_level,
2975 unsigned first_layer, unsigned last_layer,
2976 unsigned width, unsigned height, unsigned depth,
2977 uint32_t *state,
2978 uint32_t *fmask_state)
2979 {
2980 struct pipe_resource *res = &tex->resource.b.b;
2981 const struct util_format_description *desc;
2982 unsigned char swizzle[4];
2983 int first_non_void;
2984 unsigned num_format, data_format, type;
2985 uint64_t va;
2986
2987 desc = util_format_description(pipe_format);
2988
2989 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2990 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2991 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2992 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
2993
2994 switch (pipe_format) {
2995 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2996 case PIPE_FORMAT_X32_S8X24_UINT:
2997 case PIPE_FORMAT_X8Z24_UNORM:
2998 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2999 break;
3000 case PIPE_FORMAT_X24S8_UINT:
3001 /*
3002 * X24S8 is implemented as an 8_8_8_8 data format, to
3003 * fix texture gathers. This affects at least
3004 * GL45-CTS.texture_cube_map_array.sampling on VI.
3005 */
3006 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3007 break;
3008 default:
3009 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3010 }
3011 } else {
3012 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3013 }
3014
3015 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3016
3017 switch (pipe_format) {
3018 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3019 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3020 break;
3021 default:
3022 if (first_non_void < 0) {
3023 if (util_format_is_compressed(pipe_format)) {
3024 switch (pipe_format) {
3025 case PIPE_FORMAT_DXT1_SRGB:
3026 case PIPE_FORMAT_DXT1_SRGBA:
3027 case PIPE_FORMAT_DXT3_SRGBA:
3028 case PIPE_FORMAT_DXT5_SRGBA:
3029 case PIPE_FORMAT_BPTC_SRGBA:
3030 case PIPE_FORMAT_ETC2_SRGB8:
3031 case PIPE_FORMAT_ETC2_SRGB8A1:
3032 case PIPE_FORMAT_ETC2_SRGBA8:
3033 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3034 break;
3035 case PIPE_FORMAT_RGTC1_SNORM:
3036 case PIPE_FORMAT_LATC1_SNORM:
3037 case PIPE_FORMAT_RGTC2_SNORM:
3038 case PIPE_FORMAT_LATC2_SNORM:
3039 case PIPE_FORMAT_ETC2_R11_SNORM:
3040 case PIPE_FORMAT_ETC2_RG11_SNORM:
3041 /* implies float, so use SNORM/UNORM to determine
3042 whether data is signed or not */
3043 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3044 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3045 break;
3046 default:
3047 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3048 break;
3049 }
3050 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3051 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3052 } else {
3053 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3054 }
3055 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3056 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3057 } else {
3058 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3059
3060 switch (desc->channel[first_non_void].type) {
3061 case UTIL_FORMAT_TYPE_FLOAT:
3062 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3063 break;
3064 case UTIL_FORMAT_TYPE_SIGNED:
3065 if (desc->channel[first_non_void].normalized)
3066 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3067 else if (desc->channel[first_non_void].pure_integer)
3068 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3069 else
3070 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3071 break;
3072 case UTIL_FORMAT_TYPE_UNSIGNED:
3073 if (desc->channel[first_non_void].normalized)
3074 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3075 else if (desc->channel[first_non_void].pure_integer)
3076 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3077 else
3078 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3079 }
3080 }
3081 }
3082
3083 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3084 if (data_format == ~0) {
3085 data_format = 0;
3086 }
3087
3088 if (!sampler &&
3089 (res->target == PIPE_TEXTURE_CUBE ||
3090 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3091 res->target == PIPE_TEXTURE_3D)) {
3092 /* For the purpose of shader images, treat cube maps and 3D
3093 * textures as 2D arrays. For 3D textures, the address
3094 * calculations for mipmaps are different, so we rely on the
3095 * caller to effectively disable mipmaps.
3096 */
3097 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3098
3099 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3100 } else {
3101 type = si_tex_dim(res->target, target, res->nr_samples);
3102 }
3103
3104 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3105 height = 1;
3106 depth = res->array_size;
3107 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3108 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3109 if (sampler || res->target != PIPE_TEXTURE_3D)
3110 depth = res->array_size;
3111 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3112 depth = res->array_size / 6;
3113
3114 state[0] = 0;
3115 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3116 S_008F14_NUM_FORMAT_GFX6(num_format));
3117 state[2] = (S_008F18_WIDTH(width - 1) |
3118 S_008F18_HEIGHT(height - 1) |
3119 S_008F18_PERF_MOD(4));
3120 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3121 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3122 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3123 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3124 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3125 0 : first_level) |
3126 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3127 util_logbase2(res->nr_samples) :
3128 last_level) |
3129 S_008F1C_TYPE(type));
3130 state[4] = 0;
3131 state[5] = S_008F24_BASE_ARRAY(first_layer);
3132 state[6] = 0;
3133 state[7] = 0;
3134
3135 if (screen->b.chip_class >= GFX9) {
3136 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3137
3138 /* Depth is the the last accessible layer on Gfx9.
3139 * The hw doesn't need to know the total number of layers.
3140 */
3141 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3142 state[4] |= S_008F20_DEPTH(depth - 1);
3143 else
3144 state[4] |= S_008F20_DEPTH(last_layer);
3145
3146 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3147 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3148 util_logbase2(res->nr_samples) :
3149 tex->resource.b.b.last_level);
3150 } else {
3151 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3152 state[4] |= S_008F20_DEPTH(depth - 1);
3153 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3154 }
3155
3156 if (tex->dcc_offset) {
3157 unsigned swap = r600_translate_colorswap(pipe_format, false);
3158
3159 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3160 } else {
3161 /* The last dword is unused by hw. The shader uses it to clear
3162 * bits in the first dword of sampler state.
3163 */
3164 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3165 if (first_level == last_level)
3166 state[7] = C_008F30_MAX_ANISO_RATIO;
3167 else
3168 state[7] = 0xffffffff;
3169 }
3170 }
3171
3172 /* Initialize the sampler view for FMASK. */
3173 if (tex->fmask.size) {
3174 uint32_t data_format, num_format;
3175
3176 va = tex->resource.gpu_address + tex->fmask.offset;
3177
3178 if (screen->b.chip_class >= GFX9) {
3179 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3180 switch (res->nr_samples) {
3181 case 2:
3182 num_format = V_008F14_IMG_FMASK_8_2_2;
3183 break;
3184 case 4:
3185 num_format = V_008F14_IMG_FMASK_8_4_4;
3186 break;
3187 case 8:
3188 num_format = V_008F14_IMG_FMASK_32_8_8;
3189 break;
3190 default:
3191 assert(0);
3192 }
3193 } else {
3194 switch (res->nr_samples) {
3195 case 2:
3196 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3197 break;
3198 case 4:
3199 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3200 break;
3201 case 8:
3202 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3203 break;
3204 default:
3205 assert(0);
3206 }
3207 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3208 }
3209
3210 fmask_state[0] = va >> 8;
3211 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3212 S_008F14_DATA_FORMAT_GFX6(data_format) |
3213 S_008F14_NUM_FORMAT_GFX6(num_format);
3214 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3215 S_008F18_HEIGHT(height - 1);
3216 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3217 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3218 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3219 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3220 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3221 fmask_state[4] = 0;
3222 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3223 fmask_state[6] = 0;
3224 fmask_state[7] = 0;
3225
3226 if (screen->b.chip_class >= GFX9) {
3227 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3228 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3229 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3230 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3231 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3232 } else {
3233 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3234 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3235 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3236 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3237 }
3238 }
3239 }
3240
3241 /**
3242 * Create a sampler view.
3243 *
3244 * @param ctx context
3245 * @param texture texture
3246 * @param state sampler view template
3247 * @param width0 width0 override (for compressed textures as int)
3248 * @param height0 height0 override (for compressed textures as int)
3249 * @param force_level set the base address to the level (for compressed textures)
3250 */
3251 struct pipe_sampler_view *
3252 si_create_sampler_view_custom(struct pipe_context *ctx,
3253 struct pipe_resource *texture,
3254 const struct pipe_sampler_view *state,
3255 unsigned width0, unsigned height0,
3256 unsigned force_level)
3257 {
3258 struct si_context *sctx = (struct si_context*)ctx;
3259 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3260 struct r600_texture *tmp = (struct r600_texture*)texture;
3261 unsigned base_level, first_level, last_level;
3262 unsigned char state_swizzle[4];
3263 unsigned height, depth, width;
3264 unsigned last_layer = state->u.tex.last_layer;
3265 enum pipe_format pipe_format;
3266 const struct legacy_surf_level *surflevel;
3267
3268 if (!view)
3269 return NULL;
3270
3271 /* initialize base object */
3272 view->base = *state;
3273 view->base.texture = NULL;
3274 view->base.reference.count = 1;
3275 view->base.context = ctx;
3276
3277 assert(texture);
3278 pipe_resource_reference(&view->base.texture, texture);
3279
3280 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3281 state->format == PIPE_FORMAT_S8X24_UINT ||
3282 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3283 state->format == PIPE_FORMAT_S8_UINT)
3284 view->is_stencil_sampler = true;
3285
3286 /* Buffer resource. */
3287 if (texture->target == PIPE_BUFFER) {
3288 si_make_buffer_descriptor(sctx->screen,
3289 (struct r600_resource *)texture,
3290 state->format,
3291 state->u.buf.offset,
3292 state->u.buf.size,
3293 view->state);
3294 return &view->base;
3295 }
3296
3297 state_swizzle[0] = state->swizzle_r;
3298 state_swizzle[1] = state->swizzle_g;
3299 state_swizzle[2] = state->swizzle_b;
3300 state_swizzle[3] = state->swizzle_a;
3301
3302 base_level = 0;
3303 first_level = state->u.tex.first_level;
3304 last_level = state->u.tex.last_level;
3305 width = width0;
3306 height = height0;
3307 depth = texture->depth0;
3308
3309 if (force_level) {
3310 assert(force_level == first_level &&
3311 force_level == last_level);
3312 base_level = force_level;
3313 first_level = 0;
3314 last_level = 0;
3315 width = u_minify(width, force_level);
3316 height = u_minify(height, force_level);
3317 depth = u_minify(depth, force_level);
3318 }
3319
3320 /* This is not needed if state trackers set last_layer correctly. */
3321 if (state->target == PIPE_TEXTURE_1D ||
3322 state->target == PIPE_TEXTURE_2D ||
3323 state->target == PIPE_TEXTURE_RECT ||
3324 state->target == PIPE_TEXTURE_CUBE)
3325 last_layer = state->u.tex.first_layer;
3326
3327 /* Texturing with separate depth and stencil. */
3328 pipe_format = state->format;
3329
3330 /* Depth/stencil texturing sometimes needs separate texture. */
3331 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3332 if (!tmp->flushed_depth_texture &&
3333 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3334 pipe_resource_reference(&view->base.texture, NULL);
3335 FREE(view);
3336 return NULL;
3337 }
3338
3339 assert(tmp->flushed_depth_texture);
3340
3341 /* Override format for the case where the flushed texture
3342 * contains only Z or only S.
3343 */
3344 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3345 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3346
3347 tmp = tmp->flushed_depth_texture;
3348 }
3349
3350 surflevel = tmp->surface.u.legacy.level;
3351
3352 if (tmp->db_compatible) {
3353 if (!view->is_stencil_sampler)
3354 pipe_format = tmp->db_render_format;
3355
3356 switch (pipe_format) {
3357 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3358 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3359 break;
3360 case PIPE_FORMAT_X8Z24_UNORM:
3361 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3362 /* Z24 is always stored like this for DB
3363 * compatibility.
3364 */
3365 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3366 break;
3367 case PIPE_FORMAT_X24S8_UINT:
3368 case PIPE_FORMAT_S8X24_UINT:
3369 case PIPE_FORMAT_X32_S8X24_UINT:
3370 pipe_format = PIPE_FORMAT_S8_UINT;
3371 surflevel = tmp->surface.u.legacy.stencil_level;
3372 break;
3373 default:;
3374 }
3375 }
3376
3377 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3378 state->u.tex.first_level,
3379 state->format);
3380
3381 si_make_texture_descriptor(sctx->screen, tmp, true,
3382 state->target, pipe_format, state_swizzle,
3383 first_level, last_level,
3384 state->u.tex.first_layer, last_layer,
3385 width, height, depth,
3386 view->state, view->fmask_state);
3387
3388 view->base_level_info = &surflevel[base_level];
3389 view->base_level = base_level;
3390 view->block_width = util_format_get_blockwidth(pipe_format);
3391 return &view->base;
3392 }
3393
3394 static struct pipe_sampler_view *
3395 si_create_sampler_view(struct pipe_context *ctx,
3396 struct pipe_resource *texture,
3397 const struct pipe_sampler_view *state)
3398 {
3399 return si_create_sampler_view_custom(ctx, texture, state,
3400 texture ? texture->width0 : 0,
3401 texture ? texture->height0 : 0, 0);
3402 }
3403
3404 static void si_sampler_view_destroy(struct pipe_context *ctx,
3405 struct pipe_sampler_view *state)
3406 {
3407 struct si_sampler_view *view = (struct si_sampler_view *)state;
3408
3409 pipe_resource_reference(&state->texture, NULL);
3410 FREE(view);
3411 }
3412
3413 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3414 {
3415 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3416 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3417 (linear_filter &&
3418 (wrap == PIPE_TEX_WRAP_CLAMP ||
3419 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3420 }
3421
3422 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3423 {
3424 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3425 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3426
3427 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3428 state->border_color.ui[2] || state->border_color.ui[3]) &&
3429 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3430 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3431 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3432 }
3433
3434 static void *si_create_sampler_state(struct pipe_context *ctx,
3435 const struct pipe_sampler_state *state)
3436 {
3437 struct si_context *sctx = (struct si_context *)ctx;
3438 struct r600_common_screen *rscreen = sctx->b.screen;
3439 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3440 unsigned border_color_type, border_color_index = 0;
3441 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3442 : state->max_anisotropy;
3443 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3444
3445 if (!rstate) {
3446 return NULL;
3447 }
3448
3449 if (!sampler_state_needs_border_color(state))
3450 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3451 else if (state->border_color.f[0] == 0 &&
3452 state->border_color.f[1] == 0 &&
3453 state->border_color.f[2] == 0 &&
3454 state->border_color.f[3] == 0)
3455 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3456 else if (state->border_color.f[0] == 0 &&
3457 state->border_color.f[1] == 0 &&
3458 state->border_color.f[2] == 0 &&
3459 state->border_color.f[3] == 1)
3460 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3461 else if (state->border_color.f[0] == 1 &&
3462 state->border_color.f[1] == 1 &&
3463 state->border_color.f[2] == 1 &&
3464 state->border_color.f[3] == 1)
3465 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3466 else {
3467 int i;
3468
3469 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3470
3471 /* Check if the border has been uploaded already. */
3472 for (i = 0; i < sctx->border_color_count; i++)
3473 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3474 sizeof(state->border_color)) == 0)
3475 break;
3476
3477 if (i >= SI_MAX_BORDER_COLORS) {
3478 /* Getting 4096 unique border colors is very unlikely. */
3479 fprintf(stderr, "radeonsi: The border color table is full. "
3480 "Any new border colors will be just black. "
3481 "Please file a bug.\n");
3482 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3483 } else {
3484 if (i == sctx->border_color_count) {
3485 /* Upload a new border color. */
3486 memcpy(&sctx->border_color_table[i], &state->border_color,
3487 sizeof(state->border_color));
3488 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3489 &state->border_color,
3490 sizeof(state->border_color));
3491 sctx->border_color_count++;
3492 }
3493
3494 border_color_index = i;
3495 }
3496 }
3497
3498 #ifdef DEBUG
3499 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3500 #endif
3501 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3502 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3503 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3504 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3505 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3506 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3507 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3508 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3509 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3510 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3511 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3512 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3513 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3514 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3515 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3516 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3517 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3518 S_008F38_MIP_POINT_PRECLAMP(1) |
3519 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3520 S_008F38_FILTER_PREC_FIX(1) |
3521 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3522 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3523 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3524 return rstate;
3525 }
3526
3527 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3528 {
3529 struct si_context *sctx = (struct si_context *)ctx;
3530
3531 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3532 return;
3533
3534 sctx->sample_mask.sample_mask = sample_mask;
3535 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3536 }
3537
3538 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3539 {
3540 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3541 unsigned mask = sctx->sample_mask.sample_mask;
3542
3543 /* Needed for line and polygon smoothing as well as for the Polaris
3544 * small primitive filter. We expect the state tracker to take care of
3545 * this for us.
3546 */
3547 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3548 (mask & 1 && sctx->blitter->running));
3549
3550 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3551 radeon_emit(cs, mask | (mask << 16));
3552 radeon_emit(cs, mask | (mask << 16));
3553 }
3554
3555 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3556 {
3557 #ifdef DEBUG
3558 struct si_sampler_state *s = state;
3559
3560 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3561 s->magic = 0;
3562 #endif
3563 free(state);
3564 }
3565
3566 /*
3567 * Vertex elements & buffers
3568 */
3569
3570 static void *si_create_vertex_elements(struct pipe_context *ctx,
3571 unsigned count,
3572 const struct pipe_vertex_element *elements)
3573 {
3574 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3575 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3576 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3577 int i;
3578
3579 assert(count <= SI_MAX_ATTRIBS);
3580 if (!v)
3581 return NULL;
3582
3583 v->count = count;
3584 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3585
3586 for (i = 0; i < count; ++i) {
3587 const struct util_format_description *desc;
3588 const struct util_format_channel_description *channel;
3589 unsigned data_format, num_format;
3590 int first_non_void;
3591 unsigned vbo_index = elements[i].vertex_buffer_index;
3592 unsigned char swizzle[4];
3593
3594 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3595 FREE(v);
3596 return NULL;
3597 }
3598
3599 if (!used[vbo_index]) {
3600 v->first_vb_use_mask |= 1 << i;
3601 used[vbo_index] = true;
3602 }
3603
3604 desc = util_format_description(elements[i].src_format);
3605 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3606 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3607 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3608 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3609 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3610
3611 v->format_size[i] = desc->block.bits / 8;
3612
3613 /* The hardware always treats the 2-bit alpha channel as
3614 * unsigned, so a shader workaround is needed. The affected
3615 * chips are VI and older except Stoney (GFX8.1).
3616 */
3617 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3618 sscreen->b.chip_class <= VI &&
3619 sscreen->b.family != CHIP_STONEY) {
3620 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3621 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3622 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3623 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3624 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3625 /* This isn't actually used in OpenGL. */
3626 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3627 }
3628 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3629 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3630 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3631 else
3632 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3633 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3634 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3635 if (channel->normalized) {
3636 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3637 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3638 else
3639 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3640 } else {
3641 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3642 }
3643 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3644 if (channel->normalized) {
3645 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3646 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3647 else
3648 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3649 } else {
3650 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3651 }
3652 }
3653 } else if (channel && channel->size == 64 &&
3654 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3655 switch (desc->nr_channels) {
3656 case 1:
3657 case 2:
3658 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3659 swizzle[0] = PIPE_SWIZZLE_X;
3660 swizzle[1] = PIPE_SWIZZLE_Y;
3661 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3662 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3663 break;
3664 case 3:
3665 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3666 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3667 swizzle[1] = PIPE_SWIZZLE_Y;
3668 swizzle[2] = PIPE_SWIZZLE_0;
3669 swizzle[3] = PIPE_SWIZZLE_0;
3670 break;
3671 case 4:
3672 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3673 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3674 swizzle[1] = PIPE_SWIZZLE_Y;
3675 swizzle[2] = PIPE_SWIZZLE_Z;
3676 swizzle[3] = PIPE_SWIZZLE_W;
3677 break;
3678 default:
3679 assert(0);
3680 }
3681 } else if (channel && desc->nr_channels == 3) {
3682 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3683
3684 if (channel->size == 8) {
3685 if (channel->pure_integer)
3686 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3687 else
3688 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3689 } else if (channel->size == 16) {
3690 if (channel->pure_integer)
3691 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3692 else
3693 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3694 }
3695 }
3696
3697 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3698 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3699 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3700 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3701 S_008F0C_NUM_FORMAT(num_format) |
3702 S_008F0C_DATA_FORMAT(data_format);
3703 }
3704 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3705
3706 return v;
3707 }
3708
3709 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3710 {
3711 struct si_context *sctx = (struct si_context *)ctx;
3712 struct si_vertex_element *v = (struct si_vertex_element*)state;
3713
3714 sctx->vertex_elements = v;
3715 sctx->vertex_buffers_dirty = true;
3716 sctx->do_update_shaders = true;
3717 }
3718
3719 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3720 {
3721 struct si_context *sctx = (struct si_context *)ctx;
3722
3723 if (sctx->vertex_elements == state)
3724 sctx->vertex_elements = NULL;
3725 FREE(state);
3726 }
3727
3728 static void si_set_vertex_buffers(struct pipe_context *ctx,
3729 unsigned start_slot, unsigned count,
3730 const struct pipe_vertex_buffer *buffers)
3731 {
3732 struct si_context *sctx = (struct si_context *)ctx;
3733 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3734 int i;
3735
3736 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3737
3738 if (buffers) {
3739 for (i = 0; i < count; i++) {
3740 const struct pipe_vertex_buffer *src = buffers + i;
3741 struct pipe_vertex_buffer *dsti = dst + i;
3742
3743 if (unlikely(src->user_buffer)) {
3744 /* Zero-stride attribs only. */
3745 assert(src->stride == 0);
3746
3747 /* Assume that the user_buffer comes from
3748 * gl_current_attrib, which implies it has
3749 * 4 * 8 bytes (for dvec4 attributes).
3750 *
3751 * Use const_uploader to upload into VRAM directly.
3752 */
3753 u_upload_data(sctx->b.b.const_uploader, 0, 32, 32,
3754 src->user_buffer,
3755 &dsti->buffer_offset,
3756 &dsti->buffer);
3757 dsti->stride = 0;
3758 } else {
3759 struct pipe_resource *buf = src->buffer;
3760
3761 pipe_resource_reference(&dsti->buffer, buf);
3762 dsti->buffer_offset = src->buffer_offset;
3763 dsti->stride = src->stride;
3764 r600_context_add_resource_size(ctx, buf);
3765 if (buf)
3766 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3767 }
3768 }
3769 } else {
3770 for (i = 0; i < count; i++) {
3771 pipe_resource_reference(&dst[i].buffer, NULL);
3772 }
3773 }
3774 sctx->vertex_buffers_dirty = true;
3775 }
3776
3777 static void si_set_index_buffer(struct pipe_context *ctx,
3778 const struct pipe_index_buffer *ib)
3779 {
3780 struct si_context *sctx = (struct si_context *)ctx;
3781
3782 if (ib) {
3783 struct pipe_resource *buf = ib->buffer;
3784
3785 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3786 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3787 r600_context_add_resource_size(ctx, buf);
3788 if (buf)
3789 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3790 } else {
3791 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3792 }
3793 }
3794
3795 /*
3796 * Misc
3797 */
3798
3799 static void si_set_tess_state(struct pipe_context *ctx,
3800 const float default_outer_level[4],
3801 const float default_inner_level[2])
3802 {
3803 struct si_context *sctx = (struct si_context *)ctx;
3804 struct pipe_constant_buffer cb;
3805 float array[8];
3806
3807 memcpy(array, default_outer_level, sizeof(float) * 4);
3808 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3809
3810 cb.buffer = NULL;
3811 cb.user_buffer = NULL;
3812 cb.buffer_size = sizeof(array);
3813
3814 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3815 (void*)array, sizeof(array),
3816 &cb.buffer_offset);
3817
3818 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3819 pipe_resource_reference(&cb.buffer, NULL);
3820 }
3821
3822 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3823 {
3824 struct si_context *sctx = (struct si_context *)ctx;
3825
3826 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3827 SI_CONTEXT_INV_GLOBAL_L2 |
3828 SI_CONTEXT_FLUSH_AND_INV_CB;
3829 sctx->framebuffer.do_update_surf_dirtiness = true;
3830 }
3831
3832 /* This only ensures coherency for shader image/buffer stores. */
3833 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3834 {
3835 struct si_context *sctx = (struct si_context *)ctx;
3836
3837 /* Subsequent commands must wait for all shader invocations to
3838 * complete. */
3839 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3840 SI_CONTEXT_CS_PARTIAL_FLUSH;
3841
3842 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3843 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3844 SI_CONTEXT_INV_VMEM_L1;
3845
3846 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3847 PIPE_BARRIER_SHADER_BUFFER |
3848 PIPE_BARRIER_TEXTURE |
3849 PIPE_BARRIER_IMAGE |
3850 PIPE_BARRIER_STREAMOUT_BUFFER |
3851 PIPE_BARRIER_GLOBAL_BUFFER)) {
3852 /* As far as I can tell, L1 contents are written back to L2
3853 * automatically at end of shader, but the contents of other
3854 * L1 caches might still be stale. */
3855 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3856 }
3857
3858 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3859 /* Indices are read through TC L2 since VI.
3860 * L1 isn't used.
3861 */
3862 if (sctx->screen->b.chip_class <= CIK)
3863 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3864 }
3865
3866 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3867 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3868 SI_CONTEXT_FLUSH_AND_INV_DB;
3869
3870 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3871 PIPE_BARRIER_INDIRECT_BUFFER))
3872 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3873 }
3874
3875 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3876 {
3877 struct pipe_blend_state blend;
3878
3879 memset(&blend, 0, sizeof(blend));
3880 blend.independent_blend_enable = true;
3881 blend.rt[0].colormask = 0xf;
3882 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3883 }
3884
3885 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3886 bool include_draw_vbo)
3887 {
3888 si_need_cs_space((struct si_context*)ctx);
3889 }
3890
3891 static void si_init_config(struct si_context *sctx);
3892
3893 void si_init_state_functions(struct si_context *sctx)
3894 {
3895 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3896 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3897 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3898 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3899 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3900
3901 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3902 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3903 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3904 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3905 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3906 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3907 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3908 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3909 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3910 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3911
3912 sctx->b.b.create_blend_state = si_create_blend_state;
3913 sctx->b.b.bind_blend_state = si_bind_blend_state;
3914 sctx->b.b.delete_blend_state = si_delete_blend_state;
3915 sctx->b.b.set_blend_color = si_set_blend_color;
3916
3917 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3918 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3919 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3920
3921 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3922 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3923 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3924
3925 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3926 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3927 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3928 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3929 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3930
3931 sctx->b.b.set_clip_state = si_set_clip_state;
3932 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3933
3934 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3935 sctx->b.b.get_sample_position = cayman_get_sample_position;
3936
3937 sctx->b.b.create_sampler_state = si_create_sampler_state;
3938 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3939
3940 sctx->b.b.create_sampler_view = si_create_sampler_view;
3941 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3942
3943 sctx->b.b.set_sample_mask = si_set_sample_mask;
3944
3945 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3946 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3947 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3948 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3949 sctx->b.b.set_index_buffer = si_set_index_buffer;
3950
3951 sctx->b.b.texture_barrier = si_texture_barrier;
3952 sctx->b.b.memory_barrier = si_memory_barrier;
3953 sctx->b.b.set_min_samples = si_set_min_samples;
3954 sctx->b.b.set_tess_state = si_set_tess_state;
3955
3956 sctx->b.b.set_active_query_state = si_set_active_query_state;
3957 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3958 sctx->b.save_qbo_state = si_save_qbo_state;
3959 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3960
3961 sctx->b.b.draw_vbo = si_draw_vbo;
3962
3963 si_init_config(sctx);
3964 }
3965
3966 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3967 {
3968 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3969 }
3970
3971 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3972 struct r600_texture *rtex,
3973 struct radeon_bo_metadata *md)
3974 {
3975 struct si_screen *sscreen = (struct si_screen*)rscreen;
3976 struct pipe_resource *res = &rtex->resource.b.b;
3977 static const unsigned char swizzle[] = {
3978 PIPE_SWIZZLE_X,
3979 PIPE_SWIZZLE_Y,
3980 PIPE_SWIZZLE_Z,
3981 PIPE_SWIZZLE_W
3982 };
3983 uint32_t desc[8], i;
3984 bool is_array = util_resource_is_array_texture(res);
3985
3986 /* DRM 2.x.x doesn't support this. */
3987 if (rscreen->info.drm_major != 3)
3988 return;
3989
3990 assert(rtex->dcc_separate_buffer == NULL);
3991 assert(rtex->fmask.size == 0);
3992
3993 /* Metadata image format format version 1:
3994 * [0] = 1 (metadata format identifier)
3995 * [1] = (VENDOR_ID << 16) | PCI_ID
3996 * [2:9] = image descriptor for the whole resource
3997 * [2] is always 0, because the base address is cleared
3998 * [9] is the DCC offset bits [39:8] from the beginning of
3999 * the buffer
4000 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4001 */
4002
4003 md->metadata[0] = 1; /* metadata image format version 1 */
4004
4005 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4006 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4007
4008 si_make_texture_descriptor(sscreen, rtex, true,
4009 res->target, res->format,
4010 swizzle, 0, res->last_level, 0,
4011 is_array ? res->array_size - 1 : 0,
4012 res->width0, res->height0, res->depth0,
4013 desc, NULL);
4014
4015 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.u.legacy.level[0], 0, 0,
4016 rtex->surface.blk_w, false, desc);
4017
4018 /* Clear the base address and set the relative DCC offset. */
4019 desc[0] = 0;
4020 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4021 desc[7] = rtex->dcc_offset >> 8;
4022
4023 /* Dwords [2:9] contain the image descriptor. */
4024 memcpy(&md->metadata[2], desc, sizeof(desc));
4025
4026 /* Dwords [10:..] contain the mipmap level offsets. */
4027 for (i = 0; i <= res->last_level; i++)
4028 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4029
4030 md->size_metadata = (11 + res->last_level) * 4;
4031 }
4032
4033 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4034 struct r600_texture *rtex,
4035 struct radeon_bo_metadata *md)
4036 {
4037 uint32_t *desc = &md->metadata[2];
4038
4039 if (rscreen->chip_class < VI)
4040 return;
4041
4042 /* Return if DCC is enabled. The texture should be set up with it
4043 * already.
4044 */
4045 if (md->size_metadata >= 11 * 4 &&
4046 md->metadata[0] != 0 &&
4047 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4048 G_008F28_COMPRESSION_EN(desc[6])) {
4049 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4050 return;
4051 }
4052
4053 /* Disable DCC. These are always set by texture_from_handle and must
4054 * be cleared here.
4055 */
4056 rtex->dcc_offset = 0;
4057 }
4058
4059 void si_init_screen_state_functions(struct si_screen *sscreen)
4060 {
4061 sscreen->b.b.is_format_supported = si_is_format_supported;
4062 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4063 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4064 }
4065
4066 static void
4067 si_write_harvested_raster_configs(struct si_context *sctx,
4068 struct si_pm4_state *pm4,
4069 unsigned raster_config,
4070 unsigned raster_config_1)
4071 {
4072 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4073 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4074 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4075 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4076 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4077 unsigned rb_per_se = num_rb / num_se;
4078 unsigned se_mask[4];
4079 unsigned se;
4080
4081 se_mask[0] = ((1 << rb_per_se) - 1);
4082 se_mask[1] = (se_mask[0] << rb_per_se);
4083 se_mask[2] = (se_mask[1] << rb_per_se);
4084 se_mask[3] = (se_mask[2] << rb_per_se);
4085
4086 se_mask[0] &= rb_mask;
4087 se_mask[1] &= rb_mask;
4088 se_mask[2] &= rb_mask;
4089 se_mask[3] &= rb_mask;
4090
4091 assert(num_se == 1 || num_se == 2 || num_se == 4);
4092 assert(sh_per_se == 1 || sh_per_se == 2);
4093 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4094
4095 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4096 * fields are for, so I'm leaving them as their default
4097 * values. */
4098
4099 for (se = 0; se < num_se; se++) {
4100 unsigned raster_config_se = raster_config;
4101 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4102 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4103 int idx = (se / 2) * 2;
4104
4105 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4106 raster_config_se &= C_028350_SE_MAP;
4107
4108 if (!se_mask[idx]) {
4109 raster_config_se |=
4110 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4111 } else {
4112 raster_config_se |=
4113 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4114 }
4115 }
4116
4117 pkr0_mask &= rb_mask;
4118 pkr1_mask &= rb_mask;
4119 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4120 raster_config_se &= C_028350_PKR_MAP;
4121
4122 if (!pkr0_mask) {
4123 raster_config_se |=
4124 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4125 } else {
4126 raster_config_se |=
4127 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4128 }
4129 }
4130
4131 if (rb_per_se >= 2) {
4132 unsigned rb0_mask = 1 << (se * rb_per_se);
4133 unsigned rb1_mask = rb0_mask << 1;
4134
4135 rb0_mask &= rb_mask;
4136 rb1_mask &= rb_mask;
4137 if (!rb0_mask || !rb1_mask) {
4138 raster_config_se &= C_028350_RB_MAP_PKR0;
4139
4140 if (!rb0_mask) {
4141 raster_config_se |=
4142 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4143 } else {
4144 raster_config_se |=
4145 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4146 }
4147 }
4148
4149 if (rb_per_se > 2) {
4150 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4151 rb1_mask = rb0_mask << 1;
4152 rb0_mask &= rb_mask;
4153 rb1_mask &= rb_mask;
4154 if (!rb0_mask || !rb1_mask) {
4155 raster_config_se &= C_028350_RB_MAP_PKR1;
4156
4157 if (!rb0_mask) {
4158 raster_config_se |=
4159 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4160 } else {
4161 raster_config_se |=
4162 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4163 }
4164 }
4165 }
4166 }
4167
4168 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4169 if (sctx->b.chip_class < CIK)
4170 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4171 SE_INDEX(se) | SH_BROADCAST_WRITES |
4172 INSTANCE_BROADCAST_WRITES);
4173 else
4174 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4175 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4176 S_030800_INSTANCE_BROADCAST_WRITES(1));
4177 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4178 }
4179
4180 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4181 if (sctx->b.chip_class < CIK)
4182 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4183 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4184 INSTANCE_BROADCAST_WRITES);
4185 else {
4186 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4187 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4188 S_030800_INSTANCE_BROADCAST_WRITES(1));
4189
4190 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4191 (!se_mask[2] && !se_mask[3]))) {
4192 raster_config_1 &= C_028354_SE_PAIR_MAP;
4193
4194 if (!se_mask[0] && !se_mask[1]) {
4195 raster_config_1 |=
4196 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4197 } else {
4198 raster_config_1 |=
4199 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4200 }
4201 }
4202
4203 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4204 }
4205 }
4206
4207 static void si_init_config(struct si_context *sctx)
4208 {
4209 struct si_screen *sscreen = sctx->screen;
4210 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4211 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4212 unsigned raster_config, raster_config_1;
4213 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4215
4216 if (!pm4)
4217 return;
4218
4219 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4220 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4221 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4222 si_pm4_cmd_end(pm4, false);
4223
4224 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4225 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4226
4227 /* FIXME calculate these values somehow ??? */
4228 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4229 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4230 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4231
4232 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4233 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4234
4235 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4236 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4237 if (sctx->b.chip_class < CIK)
4238 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4239 S_008A14_CLIP_VTX_REORDER_ENA(1));
4240
4241 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4242 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4243
4244 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4245
4246 switch (sctx->screen->b.family) {
4247 case CHIP_TAHITI:
4248 case CHIP_PITCAIRN:
4249 raster_config = 0x2a00126a;
4250 raster_config_1 = 0x00000000;
4251 break;
4252 case CHIP_VERDE:
4253 raster_config = 0x0000124a;
4254 raster_config_1 = 0x00000000;
4255 break;
4256 case CHIP_OLAND:
4257 raster_config = 0x00000082;
4258 raster_config_1 = 0x00000000;
4259 break;
4260 case CHIP_HAINAN:
4261 raster_config = 0x00000000;
4262 raster_config_1 = 0x00000000;
4263 break;
4264 case CHIP_BONAIRE:
4265 raster_config = 0x16000012;
4266 raster_config_1 = 0x00000000;
4267 break;
4268 case CHIP_HAWAII:
4269 raster_config = 0x3a00161a;
4270 raster_config_1 = 0x0000002e;
4271 break;
4272 case CHIP_FIJI:
4273 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4274 /* old kernels with old tiling config */
4275 raster_config = 0x16000012;
4276 raster_config_1 = 0x0000002a;
4277 } else {
4278 raster_config = 0x3a00161a;
4279 raster_config_1 = 0x0000002e;
4280 }
4281 break;
4282 case CHIP_POLARIS10:
4283 raster_config = 0x16000012;
4284 raster_config_1 = 0x0000002a;
4285 break;
4286 case CHIP_POLARIS11:
4287 case CHIP_POLARIS12:
4288 raster_config = 0x16000012;
4289 raster_config_1 = 0x00000000;
4290 break;
4291 case CHIP_TONGA:
4292 raster_config = 0x16000012;
4293 raster_config_1 = 0x0000002a;
4294 break;
4295 case CHIP_ICELAND:
4296 if (num_rb == 1)
4297 raster_config = 0x00000000;
4298 else
4299 raster_config = 0x00000002;
4300 raster_config_1 = 0x00000000;
4301 break;
4302 case CHIP_CARRIZO:
4303 raster_config = 0x00000002;
4304 raster_config_1 = 0x00000000;
4305 break;
4306 case CHIP_KAVERI:
4307 /* KV should be 0x00000002, but that causes problems with radeon */
4308 raster_config = 0x00000000; /* 0x00000002 */
4309 raster_config_1 = 0x00000000;
4310 break;
4311 case CHIP_KABINI:
4312 case CHIP_MULLINS:
4313 case CHIP_STONEY:
4314 raster_config = 0x00000000;
4315 raster_config_1 = 0x00000000;
4316 break;
4317 default:
4318 if (sctx->b.chip_class <= VI) {
4319 fprintf(stderr,
4320 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4321 raster_config = 0x00000000;
4322 raster_config_1 = 0x00000000;
4323 }
4324 break;
4325 }
4326
4327 if (sctx->b.chip_class <= VI) {
4328 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4329 /* Always use the default config when all backends are enabled
4330 * (or when we failed to determine the enabled backends).
4331 */
4332 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4333 raster_config);
4334 if (sctx->b.chip_class >= CIK)
4335 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4336 raster_config_1);
4337 } else {
4338 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4339 }
4340 }
4341
4342 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4343 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4344 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4345 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4346 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4347 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4348 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4349
4350 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4351 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4352 S_028230_ER_TRI(0xA) |
4353 S_028230_ER_POINT(0xA) |
4354 S_028230_ER_RECT(0xA) |
4355 /* Required by DX10_DIAMOND_TEST_ENA: */
4356 S_028230_ER_LINE_LR(0x1A) |
4357 S_028230_ER_LINE_RL(0x26) |
4358 S_028230_ER_LINE_TB(0xA) |
4359 S_028230_ER_LINE_BT(0xA));
4360 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4361 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4362 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4363 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4364 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4365 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4366 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4367
4368 if (sctx->b.chip_class >= GFX9) {
4369 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4370 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4371 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4372 } else {
4373 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4374 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4375 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4376 }
4377
4378 if (sctx->b.chip_class >= CIK) {
4379 /* If this is 0, Bonaire can hang even if GS isn't being used.
4380 * Other chips are unaffected. These are suboptimal values,
4381 * but we don't use on-chip GS.
4382 */
4383 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4384 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4385 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4386
4387 if (sctx->b.chip_class >= GFX9) {
4388 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4389 } else {
4390 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4391 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4392 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4393 }
4394 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4395
4396 if (sscreen->b.info.num_good_compute_units /
4397 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4398 /* Too few available compute units per SH. Disallowing
4399 * VS to run on CU0 could hurt us more than late VS
4400 * allocation would help.
4401 *
4402 * LATE_ALLOC_VS = 2 is the highest safe number.
4403 */
4404 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4405 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4406 } else {
4407 /* Set LATE_ALLOC_VS == 31. It should be less than
4408 * the number of scratch waves. Limitations:
4409 * - VS can't execute on CU0.
4410 * - If HS writes outputs to LDS, LS can't execute on CU0.
4411 */
4412 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4413 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4414 }
4415
4416 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4417 }
4418
4419 if (sctx->b.chip_class >= VI) {
4420 unsigned vgt_tess_distribution;
4421
4422 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4423 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4424 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4425 if (sctx->b.family < CHIP_POLARIS10)
4426 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4427 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4428
4429 vgt_tess_distribution =
4430 S_028B50_ACCUM_ISOLINE(32) |
4431 S_028B50_ACCUM_TRI(11) |
4432 S_028B50_ACCUM_QUAD(11) |
4433 S_028B50_DONUT_SPLIT(16);
4434
4435 /* Testing with Unigine Heaven extreme tesselation yielded best results
4436 * with TRAP_SPLIT = 3.
4437 */
4438 if (sctx->b.family == CHIP_FIJI ||
4439 sctx->b.family >= CHIP_POLARIS10)
4440 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4441
4442 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4443 } else {
4444 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4445 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4446 }
4447
4448 if (sctx->screen->b.has_rbplus)
4449 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4450
4451 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4452 if (sctx->b.chip_class >= CIK)
4453 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4454 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4455 RADEON_PRIO_BORDER_COLORS);
4456
4457 if (sctx->b.chip_class >= GFX9) {
4458 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
4459 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4460 /* TODO: We can use this to disable RBs for rendering to GART: */
4461 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4462 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4463 /* TODO: Enable the binner: */
4464 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4465 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
4466 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
4467 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4468 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4469 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4470 }
4471
4472 si_pm4_upload_indirect_buffer(sctx, pm4);
4473 sctx->init_config = pm4;
4474 }