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radeonsi: enable fast color clear for level 0 of mipmapped textures on <= VI
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 /* Initialize an external atom (owned by ../radeon). */
37 static void
38 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
39 struct r600_atom **list_elem)
40 {
41 atom->id = list_elem - sctx->atoms.array;
42 *list_elem = atom;
43 }
44
45 /* Initialize an atom owned by radeonsi. */
46 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
47 struct r600_atom **list_elem,
48 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
49 {
50 atom->emit = emit_func;
51 atom->id = list_elem - sctx->atoms.array;
52 *list_elem = atom;
53 }
54
55 static unsigned si_map_swizzle(unsigned swizzle)
56 {
57 switch (swizzle) {
58 case PIPE_SWIZZLE_Y:
59 return V_008F0C_SQ_SEL_Y;
60 case PIPE_SWIZZLE_Z:
61 return V_008F0C_SQ_SEL_Z;
62 case PIPE_SWIZZLE_W:
63 return V_008F0C_SQ_SEL_W;
64 case PIPE_SWIZZLE_0:
65 return V_008F0C_SQ_SEL_0;
66 case PIPE_SWIZZLE_1:
67 return V_008F0C_SQ_SEL_1;
68 default: /* PIPE_SWIZZLE_X */
69 return V_008F0C_SQ_SEL_X;
70 }
71 }
72
73 /* 12.4 fixed-point */
74 static unsigned si_pack_float_12p4(float x)
75 {
76 return x <= 0 ? 0 :
77 x >= 4096 ? 0xffff : x * 16;
78 }
79
80 /*
81 * Inferred framebuffer and blender state.
82 *
83 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
84 * if there is not enough PS outputs.
85 */
86 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
87 {
88 struct radeon_winsys_cs *cs = sctx->gfx_cs;
89 struct si_state_blend *blend = sctx->queued.named.blend;
90 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
91 * but you never know. */
92 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
93 unsigned i;
94
95 if (blend)
96 cb_target_mask &= blend->cb_target_mask;
97
98 /* Avoid a hang that happens when dual source blending is enabled
99 * but there is not enough color outputs. This is undefined behavior,
100 * so disable color writes completely.
101 *
102 * Reproducible with Unigine Heaven 4.0 and drirc missing.
103 */
104 if (blend && blend->dual_src_blend &&
105 sctx->ps_shader.cso &&
106 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
107 cb_target_mask = 0;
108
109 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
110
111 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
112 * I think we don't have to do anything between IBs.
113 */
114 if (sctx->screen->dfsm_allowed &&
115 sctx->last_cb_target_mask != cb_target_mask) {
116 sctx->last_cb_target_mask = cb_target_mask;
117
118 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
119 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
120 }
121
122 if (sctx->chip_class >= VI) {
123 /* DCC MSAA workaround for blending.
124 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
125 * COMBINER_DISABLE, but that would be more complicated.
126 */
127 bool oc_disable = (sctx->chip_class == VI ||
128 sctx->chip_class == GFX9) &&
129 blend &&
130 blend->blend_enable_4bit & cb_target_mask &&
131 sctx->framebuffer.nr_samples >= 2;
132
133 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
134 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
135 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
136 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
137 }
138
139 /* RB+ register settings. */
140 if (sctx->screen->rbplus_allowed) {
141 unsigned spi_shader_col_format =
142 sctx->ps_shader.cso ?
143 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
144 unsigned sx_ps_downconvert = 0;
145 unsigned sx_blend_opt_epsilon = 0;
146 unsigned sx_blend_opt_control = 0;
147
148 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
149 struct r600_surface *surf =
150 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
151 unsigned format, swap, spi_format, colormask;
152 bool has_alpha, has_rgb;
153
154 if (!surf)
155 continue;
156
157 format = G_028C70_FORMAT(surf->cb_color_info);
158 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
159 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
160 colormask = (cb_target_mask >> (i * 4)) & 0xf;
161
162 /* Set if RGB and A are present. */
163 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
164
165 if (format == V_028C70_COLOR_8 ||
166 format == V_028C70_COLOR_16 ||
167 format == V_028C70_COLOR_32)
168 has_rgb = !has_alpha;
169 else
170 has_rgb = true;
171
172 /* Check the colormask and export format. */
173 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
174 has_rgb = false;
175 if (!(colormask & PIPE_MASK_A))
176 has_alpha = false;
177
178 if (spi_format == V_028714_SPI_SHADER_ZERO) {
179 has_rgb = false;
180 has_alpha = false;
181 }
182
183 /* Disable value checking for disabled channels. */
184 if (!has_rgb)
185 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
186 if (!has_alpha)
187 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
188
189 /* Enable down-conversion for 32bpp and smaller formats. */
190 switch (format) {
191 case V_028C70_COLOR_8:
192 case V_028C70_COLOR_8_8:
193 case V_028C70_COLOR_8_8_8_8:
194 /* For 1 and 2-channel formats, use the superset thereof. */
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
196 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_5_6_5:
204 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
205 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
206 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
207 }
208 break;
209
210 case V_028C70_COLOR_1_5_5_5:
211 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
212 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
213 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
214 }
215 break;
216
217 case V_028C70_COLOR_4_4_4_4:
218 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
220 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
221 }
222 break;
223
224 case V_028C70_COLOR_32:
225 if (swap == V_028C70_SWAP_STD &&
226 spi_format == V_028714_SPI_SHADER_32_R)
227 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
228 else if (swap == V_028C70_SWAP_ALT_REV &&
229 spi_format == V_028714_SPI_SHADER_32_AR)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
231 break;
232
233 case V_028C70_COLOR_16:
234 case V_028C70_COLOR_16_16:
235 /* For 1-channel formats, use the superset thereof. */
236 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
237 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
240 if (swap == V_028C70_SWAP_STD ||
241 swap == V_028C70_SWAP_STD_REV)
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
243 else
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
245 }
246 break;
247
248 case V_028C70_COLOR_10_11_11:
249 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
250 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
251 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
252 }
253 break;
254
255 case V_028C70_COLOR_2_10_10_10:
256 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
257 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
258 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
259 }
260 break;
261 }
262 }
263
264 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
265 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
266 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
267 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
268 }
269 }
270
271 /*
272 * Blender functions
273 */
274
275 static uint32_t si_translate_blend_function(int blend_func)
276 {
277 switch (blend_func) {
278 case PIPE_BLEND_ADD:
279 return V_028780_COMB_DST_PLUS_SRC;
280 case PIPE_BLEND_SUBTRACT:
281 return V_028780_COMB_SRC_MINUS_DST;
282 case PIPE_BLEND_REVERSE_SUBTRACT:
283 return V_028780_COMB_DST_MINUS_SRC;
284 case PIPE_BLEND_MIN:
285 return V_028780_COMB_MIN_DST_SRC;
286 case PIPE_BLEND_MAX:
287 return V_028780_COMB_MAX_DST_SRC;
288 default:
289 PRINT_ERR("Unknown blend function %d\n", blend_func);
290 assert(0);
291 break;
292 }
293 return 0;
294 }
295
296 static uint32_t si_translate_blend_factor(int blend_fact)
297 {
298 switch (blend_fact) {
299 case PIPE_BLENDFACTOR_ONE:
300 return V_028780_BLEND_ONE;
301 case PIPE_BLENDFACTOR_SRC_COLOR:
302 return V_028780_BLEND_SRC_COLOR;
303 case PIPE_BLENDFACTOR_SRC_ALPHA:
304 return V_028780_BLEND_SRC_ALPHA;
305 case PIPE_BLENDFACTOR_DST_ALPHA:
306 return V_028780_BLEND_DST_ALPHA;
307 case PIPE_BLENDFACTOR_DST_COLOR:
308 return V_028780_BLEND_DST_COLOR;
309 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
310 return V_028780_BLEND_SRC_ALPHA_SATURATE;
311 case PIPE_BLENDFACTOR_CONST_COLOR:
312 return V_028780_BLEND_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_CONST_ALPHA:
314 return V_028780_BLEND_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_ZERO:
316 return V_028780_BLEND_ZERO;
317 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
318 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
319 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
321 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
322 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
323 case PIPE_BLENDFACTOR_INV_DST_COLOR:
324 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
325 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
326 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
327 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
329 case PIPE_BLENDFACTOR_SRC1_COLOR:
330 return V_028780_BLEND_SRC1_COLOR;
331 case PIPE_BLENDFACTOR_SRC1_ALPHA:
332 return V_028780_BLEND_SRC1_ALPHA;
333 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
334 return V_028780_BLEND_INV_SRC1_COLOR;
335 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
336 return V_028780_BLEND_INV_SRC1_ALPHA;
337 default:
338 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
339 assert(0);
340 break;
341 }
342 return 0;
343 }
344
345 static uint32_t si_translate_blend_opt_function(int blend_func)
346 {
347 switch (blend_func) {
348 case PIPE_BLEND_ADD:
349 return V_028760_OPT_COMB_ADD;
350 case PIPE_BLEND_SUBTRACT:
351 return V_028760_OPT_COMB_SUBTRACT;
352 case PIPE_BLEND_REVERSE_SUBTRACT:
353 return V_028760_OPT_COMB_REVSUBTRACT;
354 case PIPE_BLEND_MIN:
355 return V_028760_OPT_COMB_MIN;
356 case PIPE_BLEND_MAX:
357 return V_028760_OPT_COMB_MAX;
358 default:
359 return V_028760_OPT_COMB_BLEND_DISABLED;
360 }
361 }
362
363 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
364 {
365 switch (blend_fact) {
366 case PIPE_BLENDFACTOR_ZERO:
367 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
368 case PIPE_BLENDFACTOR_ONE:
369 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
370 case PIPE_BLENDFACTOR_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
372 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
373 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
375 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
376 case PIPE_BLENDFACTOR_SRC_ALPHA:
377 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
378 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
379 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
380 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
381 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
382 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
383 default:
384 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
385 }
386 }
387
388 static void si_blend_check_commutativity(struct si_screen *sscreen,
389 struct si_state_blend *blend,
390 enum pipe_blend_func func,
391 enum pipe_blendfactor src,
392 enum pipe_blendfactor dst,
393 unsigned chanmask)
394 {
395 /* Src factor is allowed when it does not depend on Dst */
396 static const uint32_t src_allowed =
397 (1u << PIPE_BLENDFACTOR_ONE) |
398 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
399 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
400 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
401 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
402 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
403 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
404 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
405 (1u << PIPE_BLENDFACTOR_ZERO) |
406 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
407 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
409 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
410 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
411 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
412
413 if (dst == PIPE_BLENDFACTOR_ONE &&
414 (src_allowed & (1u << src))) {
415 /* Addition is commutative, but floating point addition isn't
416 * associative: subtle changes can be introduced via different
417 * rounding.
418 *
419 * Out-of-order is also non-deterministic, which means that
420 * this breaks OpenGL invariance requirements. So only enable
421 * out-of-order additive blending if explicitly allowed by a
422 * setting.
423 */
424 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
425 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
426 blend->commutative_4bit |= chanmask;
427 }
428 }
429
430 /**
431 * Get rid of DST in the blend factors by commuting the operands:
432 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
433 */
434 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
435 unsigned *dst_factor, unsigned expected_dst,
436 unsigned replacement_src)
437 {
438 if (*src_factor == expected_dst &&
439 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
440 *src_factor = PIPE_BLENDFACTOR_ZERO;
441 *dst_factor = replacement_src;
442
443 /* Commuting the operands requires reversing subtractions. */
444 if (*func == PIPE_BLEND_SUBTRACT)
445 *func = PIPE_BLEND_REVERSE_SUBTRACT;
446 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
447 *func = PIPE_BLEND_SUBTRACT;
448 }
449 }
450
451 static bool si_blend_factor_uses_dst(unsigned factor)
452 {
453 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
454 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
455 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
456 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
457 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
458 }
459
460 static void *si_create_blend_state_mode(struct pipe_context *ctx,
461 const struct pipe_blend_state *state,
462 unsigned mode)
463 {
464 struct si_context *sctx = (struct si_context*)ctx;
465 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
466 struct si_pm4_state *pm4 = &blend->pm4;
467 uint32_t sx_mrt_blend_opt[8] = {0};
468 uint32_t color_control = 0;
469
470 if (!blend)
471 return NULL;
472
473 blend->alpha_to_coverage = state->alpha_to_coverage;
474 blend->alpha_to_one = state->alpha_to_one;
475 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
476 blend->logicop_enable = state->logicop_enable;
477
478 if (state->logicop_enable) {
479 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
480 } else {
481 color_control |= S_028808_ROP3(0xcc);
482 }
483
484 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
485 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
486 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
487 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
488 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
489 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
490
491 if (state->alpha_to_coverage)
492 blend->need_src_alpha_4bit |= 0xf;
493
494 blend->cb_target_mask = 0;
495 blend->cb_target_enabled_4bit = 0;
496
497 for (int i = 0; i < 8; i++) {
498 /* state->rt entries > 0 only written if independent blending */
499 const int j = state->independent_blend_enable ? i : 0;
500
501 unsigned eqRGB = state->rt[j].rgb_func;
502 unsigned srcRGB = state->rt[j].rgb_src_factor;
503 unsigned dstRGB = state->rt[j].rgb_dst_factor;
504 unsigned eqA = state->rt[j].alpha_func;
505 unsigned srcA = state->rt[j].alpha_src_factor;
506 unsigned dstA = state->rt[j].alpha_dst_factor;
507
508 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
509 unsigned blend_cntl = 0;
510
511 sx_mrt_blend_opt[i] =
512 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
513 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
514
515 /* Only set dual source blending for MRT0 to avoid a hang. */
516 if (i >= 1 && blend->dual_src_blend) {
517 /* Vulkan does this for dual source blending. */
518 if (i == 1)
519 blend_cntl |= S_028780_ENABLE(1);
520
521 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
522 continue;
523 }
524
525 /* Only addition and subtraction equations are supported with
526 * dual source blending.
527 */
528 if (blend->dual_src_blend &&
529 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
530 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
531 assert(!"Unsupported equation for dual source blending");
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 /* cb_render_state will disable unused ones */
537 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
538 if (state->rt[j].colormask)
539 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
540
541 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
542 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
543 continue;
544 }
545
546 si_blend_check_commutativity(sctx->screen, blend,
547 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
548 si_blend_check_commutativity(sctx->screen, blend,
549 eqA, srcA, dstA, 0x8 << (4 * i));
550
551 /* Blending optimizations for RB+.
552 * These transformations don't change the behavior.
553 *
554 * First, get rid of DST in the blend factors:
555 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
556 */
557 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
558 PIPE_BLENDFACTOR_DST_COLOR,
559 PIPE_BLENDFACTOR_SRC_COLOR);
560 si_blend_remove_dst(&eqA, &srcA, &dstA,
561 PIPE_BLENDFACTOR_DST_COLOR,
562 PIPE_BLENDFACTOR_SRC_COLOR);
563 si_blend_remove_dst(&eqA, &srcA, &dstA,
564 PIPE_BLENDFACTOR_DST_ALPHA,
565 PIPE_BLENDFACTOR_SRC_ALPHA);
566
567 /* Look up the ideal settings from tables. */
568 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
569 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
570 srcA_opt = si_translate_blend_opt_factor(srcA, true);
571 dstA_opt = si_translate_blend_opt_factor(dstA, true);
572
573 /* Handle interdependencies. */
574 if (si_blend_factor_uses_dst(srcRGB))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
576 if (si_blend_factor_uses_dst(srcA))
577 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
578
579 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
580 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
581 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
582 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
583 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
584
585 /* Set the final value. */
586 sx_mrt_blend_opt[i] =
587 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
588 S_028760_COLOR_DST_OPT(dstRGB_opt) |
589 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
590 S_028760_ALPHA_SRC_OPT(srcA_opt) |
591 S_028760_ALPHA_DST_OPT(dstA_opt) |
592 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
593
594 /* Set blend state. */
595 blend_cntl |= S_028780_ENABLE(1);
596 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
597 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
598 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
599
600 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
601 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
602 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
603 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
604 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
605 }
606 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
607
608 blend->blend_enable_4bit |= 0xfu << (i * 4);
609
610 /* This is only important for formats without alpha. */
611 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
612 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
613 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
614 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
615 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
616 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
617 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
618 }
619
620 if (blend->cb_target_mask) {
621 color_control |= S_028808_MODE(mode);
622 } else {
623 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
624 }
625
626 if (sctx->screen->rbplus_allowed) {
627 /* Disable RB+ blend optimizations for dual source blending.
628 * Vulkan does this.
629 */
630 if (blend->dual_src_blend) {
631 for (int i = 0; i < 8; i++) {
632 sx_mrt_blend_opt[i] =
633 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
634 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
635 }
636 }
637
638 for (int i = 0; i < 8; i++)
639 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
640 sx_mrt_blend_opt[i]);
641
642 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
643 if (blend->dual_src_blend || state->logicop_enable ||
644 mode == V_028808_CB_RESOLVE)
645 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
646 }
647
648 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
649 return blend;
650 }
651
652 static void *si_create_blend_state(struct pipe_context *ctx,
653 const struct pipe_blend_state *state)
654 {
655 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
656 }
657
658 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
659 {
660 struct si_context *sctx = (struct si_context *)ctx;
661 struct si_state_blend *old_blend = sctx->queued.named.blend;
662 struct si_state_blend *blend = (struct si_state_blend *)state;
663
664 if (!state)
665 return;
666
667 si_pm4_bind_state(sctx, blend, state);
668
669 if (!old_blend ||
670 old_blend->cb_target_mask != blend->cb_target_mask ||
671 old_blend->dual_src_blend != blend->dual_src_blend ||
672 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
673 sctx->framebuffer.nr_samples >= 2 &&
674 sctx->screen->dcc_msaa_allowed))
675 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
676
677 if (!old_blend ||
678 old_blend->cb_target_mask != blend->cb_target_mask ||
679 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
680 old_blend->alpha_to_one != blend->alpha_to_one ||
681 old_blend->dual_src_blend != blend->dual_src_blend ||
682 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
683 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
684 sctx->do_update_shaders = true;
685
686 if (sctx->screen->dpbb_allowed &&
687 (!old_blend ||
688 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
689 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
690 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
691 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
692
693 if (sctx->screen->has_out_of_order_rast &&
694 (!old_blend ||
695 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
696 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
697 old_blend->commutative_4bit != blend->commutative_4bit ||
698 old_blend->logicop_enable != blend->logicop_enable)))
699 si_mark_atom_dirty(sctx, &sctx->msaa_config);
700 }
701
702 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
703 {
704 struct si_context *sctx = (struct si_context *)ctx;
705 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
706 }
707
708 static void si_set_blend_color(struct pipe_context *ctx,
709 const struct pipe_blend_color *state)
710 {
711 struct si_context *sctx = (struct si_context *)ctx;
712 static const struct pipe_blend_color zeros;
713
714 sctx->blend_color.state = *state;
715 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
716 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
717 }
718
719 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
720 {
721 struct radeon_winsys_cs *cs = sctx->gfx_cs;
722
723 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
724 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
725 }
726
727 /*
728 * Clipping
729 */
730
731 static void si_set_clip_state(struct pipe_context *ctx,
732 const struct pipe_clip_state *state)
733 {
734 struct si_context *sctx = (struct si_context *)ctx;
735 struct pipe_constant_buffer cb;
736 static const struct pipe_clip_state zeros;
737
738 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
739 return;
740
741 sctx->clip_state.state = *state;
742 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
743 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
744
745 cb.buffer = NULL;
746 cb.user_buffer = state->ucp;
747 cb.buffer_offset = 0;
748 cb.buffer_size = 4*4*8;
749 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
750 pipe_resource_reference(&cb.buffer, NULL);
751 }
752
753 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
754 {
755 struct radeon_winsys_cs *cs = sctx->gfx_cs;
756
757 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
758 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
759 }
760
761 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
762 {
763 struct radeon_winsys_cs *cs = sctx->gfx_cs;
764 struct si_shader *vs = si_get_vs_state(sctx);
765 struct si_shader_selector *vs_sel = vs->selector;
766 struct tgsi_shader_info *info = &vs_sel->info;
767 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
768 unsigned window_space =
769 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
770 unsigned clipdist_mask = vs_sel->clipdist_mask;
771 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
772 unsigned culldist_mask = vs_sel->culldist_mask;
773 unsigned total_mask;
774
775 if (vs->key.opt.clip_disable) {
776 assert(!info->culldist_writemask);
777 clipdist_mask = 0;
778 culldist_mask = 0;
779 }
780 total_mask = clipdist_mask | culldist_mask;
781
782 /* Clip distances on points have no effect, so need to be implemented
783 * as cull distances. This applies for the clipvertex case as well.
784 *
785 * Setting this for primitives other than points should have no adverse
786 * effects.
787 */
788 clipdist_mask &= rs->clip_plane_enable;
789 culldist_mask |= clipdist_mask;
790
791 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
792 vs_sel->pa_cl_vs_out_cntl |
793 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
794 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
795 clipdist_mask | (culldist_mask << 8));
796 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
797 rs->pa_cl_clip_cntl |
798 ucp_mask |
799 S_028810_CLIP_DISABLE(window_space));
800 }
801
802 /*
803 * inferred state between framebuffer and rasterizer
804 */
805 static void si_update_poly_offset_state(struct si_context *sctx)
806 {
807 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
808
809 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
810 si_pm4_bind_state(sctx, poly_offset, NULL);
811 return;
812 }
813
814 /* Use the user format, not db_render_format, so that the polygon
815 * offset behaves as expected by applications.
816 */
817 switch (sctx->framebuffer.state.zsbuf->texture->format) {
818 case PIPE_FORMAT_Z16_UNORM:
819 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
820 break;
821 default: /* 24-bit */
822 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
823 break;
824 case PIPE_FORMAT_Z32_FLOAT:
825 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
826 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
827 break;
828 }
829 }
830
831 /*
832 * Rasterizer
833 */
834
835 static uint32_t si_translate_fill(uint32_t func)
836 {
837 switch(func) {
838 case PIPE_POLYGON_MODE_FILL:
839 return V_028814_X_DRAW_TRIANGLES;
840 case PIPE_POLYGON_MODE_LINE:
841 return V_028814_X_DRAW_LINES;
842 case PIPE_POLYGON_MODE_POINT:
843 return V_028814_X_DRAW_POINTS;
844 default:
845 assert(0);
846 return V_028814_X_DRAW_POINTS;
847 }
848 }
849
850 static void *si_create_rs_state(struct pipe_context *ctx,
851 const struct pipe_rasterizer_state *state)
852 {
853 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
854 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
855 struct si_pm4_state *pm4 = &rs->pm4;
856 unsigned tmp, i;
857 float psize_min, psize_max;
858
859 if (!rs) {
860 return NULL;
861 }
862
863 rs->scissor_enable = state->scissor;
864 rs->clip_halfz = state->clip_halfz;
865 rs->two_side = state->light_twoside;
866 rs->multisample_enable = state->multisample;
867 rs->force_persample_interp = state->force_persample_interp;
868 rs->clip_plane_enable = state->clip_plane_enable;
869 rs->line_stipple_enable = state->line_stipple_enable;
870 rs->poly_stipple_enable = state->poly_stipple_enable;
871 rs->line_smooth = state->line_smooth;
872 rs->line_width = state->line_width;
873 rs->poly_smooth = state->poly_smooth;
874 rs->uses_poly_offset = state->offset_point || state->offset_line ||
875 state->offset_tri;
876 rs->clamp_fragment_color = state->clamp_fragment_color;
877 rs->clamp_vertex_color = state->clamp_vertex_color;
878 rs->flatshade = state->flatshade;
879 rs->sprite_coord_enable = state->sprite_coord_enable;
880 rs->rasterizer_discard = state->rasterizer_discard;
881 rs->pa_sc_line_stipple = state->line_stipple_enable ?
882 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
883 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
884 rs->pa_cl_clip_cntl =
885 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
886 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
887 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
888 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
889 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
890
891 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
892 S_0286D4_FLAT_SHADE_ENA(1) |
893 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
894 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
895 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
896 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
897 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
898 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
899
900 /* point size 12.4 fixed point */
901 tmp = (unsigned)(state->point_size * 8.0);
902 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
903
904 if (state->point_size_per_vertex) {
905 psize_min = util_get_min_point_size(state);
906 psize_max = 8192;
907 } else {
908 /* Force the point size to be as if the vertex output was disabled. */
909 psize_min = state->point_size;
910 psize_max = state->point_size;
911 }
912 rs->max_point_size = psize_max;
913
914 /* Divide by two, because 0.5 = 1 pixel. */
915 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
916 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
917 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
918
919 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
920 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
921 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
922 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
923 S_028A48_MSAA_ENABLE(state->multisample ||
924 state->poly_smooth ||
925 state->line_smooth) |
926 S_028A48_VPORT_SCISSOR_ENABLE(1) |
927 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
928
929 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
930 S_028BE4_PIX_CENTER(state->half_pixel_center) |
931 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
932
933 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
934 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
935 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
936 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
937 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
938 S_028814_FACE(!state->front_ccw) |
939 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
940 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
941 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
942 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
943 state->fill_back != PIPE_POLYGON_MODE_FILL) |
944 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
945 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
946
947 if (!rs->uses_poly_offset)
948 return rs;
949
950 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
951 if (!rs->pm4_poly_offset) {
952 FREE(rs);
953 return NULL;
954 }
955
956 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
957 for (i = 0; i < 3; i++) {
958 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
959 float offset_units = state->offset_units;
960 float offset_scale = state->offset_scale * 16.0f;
961 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
962
963 if (!state->offset_units_unscaled) {
964 switch (i) {
965 case 0: /* 16-bit zbuffer */
966 offset_units *= 4.0f;
967 pa_su_poly_offset_db_fmt_cntl =
968 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
969 break;
970 case 1: /* 24-bit zbuffer */
971 offset_units *= 2.0f;
972 pa_su_poly_offset_db_fmt_cntl =
973 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
974 break;
975 case 2: /* 32-bit zbuffer */
976 offset_units *= 1.0f;
977 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
978 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
979 break;
980 }
981 }
982
983 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
984 fui(offset_scale));
985 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
986 fui(offset_units));
987 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
988 fui(offset_scale));
989 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
990 fui(offset_units));
991 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
992 pa_su_poly_offset_db_fmt_cntl);
993 }
994
995 return rs;
996 }
997
998 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
999 {
1000 struct si_context *sctx = (struct si_context *)ctx;
1001 struct si_state_rasterizer *old_rs =
1002 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1003 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1004
1005 if (!state)
1006 return;
1007
1008 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1009 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1010
1011 /* Update the small primitive filter workaround if necessary. */
1012 if (sctx->screen->has_msaa_sample_loc_bug &&
1013 sctx->framebuffer.nr_samples > 1)
1014 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1015 }
1016
1017 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1018 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1019
1020 si_pm4_bind_state(sctx, rasterizer, rs);
1021 si_update_poly_offset_state(sctx);
1022
1023 if (!old_rs ||
1024 (old_rs->scissor_enable != rs->scissor_enable ||
1025 old_rs->line_width != rs->line_width ||
1026 old_rs->max_point_size != rs->max_point_size)) {
1027 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1028 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1029 }
1030
1031 if (!old_rs ||
1032 old_rs->clip_halfz != rs->clip_halfz) {
1033 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1034 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1035 }
1036
1037 if (!old_rs ||
1038 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1039 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1040 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1041
1042 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1043 rs->line_stipple_enable;
1044
1045 if (!old_rs ||
1046 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1047 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1048 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1049 old_rs->flatshade != rs->flatshade ||
1050 old_rs->two_side != rs->two_side ||
1051 old_rs->multisample_enable != rs->multisample_enable ||
1052 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1053 old_rs->poly_smooth != rs->poly_smooth ||
1054 old_rs->line_smooth != rs->line_smooth ||
1055 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1056 old_rs->force_persample_interp != rs->force_persample_interp)
1057 sctx->do_update_shaders = true;
1058 }
1059
1060 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1061 {
1062 struct si_context *sctx = (struct si_context *)ctx;
1063 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1064
1065 if (sctx->queued.named.rasterizer == state)
1066 si_pm4_bind_state(sctx, poly_offset, NULL);
1067
1068 FREE(rs->pm4_poly_offset);
1069 si_pm4_delete_state(sctx, rasterizer, rs);
1070 }
1071
1072 /*
1073 * infeered state between dsa and stencil ref
1074 */
1075 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1076 {
1077 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1078 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1079 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1080
1081 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1082 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1083 S_028430_STENCILMASK(dsa->valuemask[0]) |
1084 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1085 S_028430_STENCILOPVAL(1));
1086 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1087 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1088 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1089 S_028434_STENCILOPVAL_BF(1));
1090 }
1091
1092 static void si_set_stencil_ref(struct pipe_context *ctx,
1093 const struct pipe_stencil_ref *state)
1094 {
1095 struct si_context *sctx = (struct si_context *)ctx;
1096
1097 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1098 return;
1099
1100 sctx->stencil_ref.state = *state;
1101 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1102 }
1103
1104
1105 /*
1106 * DSA
1107 */
1108
1109 static uint32_t si_translate_stencil_op(int s_op)
1110 {
1111 switch (s_op) {
1112 case PIPE_STENCIL_OP_KEEP:
1113 return V_02842C_STENCIL_KEEP;
1114 case PIPE_STENCIL_OP_ZERO:
1115 return V_02842C_STENCIL_ZERO;
1116 case PIPE_STENCIL_OP_REPLACE:
1117 return V_02842C_STENCIL_REPLACE_TEST;
1118 case PIPE_STENCIL_OP_INCR:
1119 return V_02842C_STENCIL_ADD_CLAMP;
1120 case PIPE_STENCIL_OP_DECR:
1121 return V_02842C_STENCIL_SUB_CLAMP;
1122 case PIPE_STENCIL_OP_INCR_WRAP:
1123 return V_02842C_STENCIL_ADD_WRAP;
1124 case PIPE_STENCIL_OP_DECR_WRAP:
1125 return V_02842C_STENCIL_SUB_WRAP;
1126 case PIPE_STENCIL_OP_INVERT:
1127 return V_02842C_STENCIL_INVERT;
1128 default:
1129 PRINT_ERR("Unknown stencil op %d", s_op);
1130 assert(0);
1131 break;
1132 }
1133 return 0;
1134 }
1135
1136 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1137 {
1138 return s->enabled && s->writemask &&
1139 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1140 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1141 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1142 }
1143
1144 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1145 {
1146 /* REPLACE is normally order invariant, except when the stencil
1147 * reference value is written by the fragment shader. Tracking this
1148 * interaction does not seem worth the effort, so be conservative. */
1149 return op != PIPE_STENCIL_OP_INCR &&
1150 op != PIPE_STENCIL_OP_DECR &&
1151 op != PIPE_STENCIL_OP_REPLACE;
1152 }
1153
1154 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1155 * invariant in the sense that the set of passing fragments as well as the
1156 * final stencil buffer result does not depend on the order of fragments. */
1157 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1158 {
1159 return !state->enabled || !state->writemask ||
1160 /* The following assumes that Z writes are disabled. */
1161 (state->func == PIPE_FUNC_ALWAYS &&
1162 si_order_invariant_stencil_op(state->zpass_op) &&
1163 si_order_invariant_stencil_op(state->zfail_op)) ||
1164 (state->func == PIPE_FUNC_NEVER &&
1165 si_order_invariant_stencil_op(state->fail_op));
1166 }
1167
1168 static void *si_create_dsa_state(struct pipe_context *ctx,
1169 const struct pipe_depth_stencil_alpha_state *state)
1170 {
1171 struct si_context *sctx = (struct si_context *)ctx;
1172 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1173 struct si_pm4_state *pm4 = &dsa->pm4;
1174 unsigned db_depth_control;
1175 uint32_t db_stencil_control = 0;
1176
1177 if (!dsa) {
1178 return NULL;
1179 }
1180
1181 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1182 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1183 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1184 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1185
1186 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1187 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1188 S_028800_ZFUNC(state->depth.func) |
1189 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1190
1191 /* stencil */
1192 if (state->stencil[0].enabled) {
1193 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1194 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1195 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1196 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1197 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1198
1199 if (state->stencil[1].enabled) {
1200 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1201 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1202 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1203 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1204 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1205 }
1206 }
1207
1208 /* alpha */
1209 if (state->alpha.enabled) {
1210 dsa->alpha_func = state->alpha.func;
1211
1212 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1213 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1214 } else {
1215 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1216 }
1217
1218 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1219 if (state->stencil[0].enabled)
1220 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1221 if (state->depth.bounds_test) {
1222 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1223 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1224 }
1225
1226 dsa->depth_enabled = state->depth.enabled;
1227 dsa->depth_write_enabled = state->depth.enabled &&
1228 state->depth.writemask;
1229 dsa->stencil_enabled = state->stencil[0].enabled;
1230 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1231 (si_dsa_writes_stencil(&state->stencil[0]) ||
1232 si_dsa_writes_stencil(&state->stencil[1]));
1233 dsa->db_can_write = dsa->depth_write_enabled ||
1234 dsa->stencil_write_enabled;
1235
1236 bool zfunc_is_ordered =
1237 state->depth.func == PIPE_FUNC_NEVER ||
1238 state->depth.func == PIPE_FUNC_LESS ||
1239 state->depth.func == PIPE_FUNC_LEQUAL ||
1240 state->depth.func == PIPE_FUNC_GREATER ||
1241 state->depth.func == PIPE_FUNC_GEQUAL;
1242
1243 bool nozwrite_and_order_invariant_stencil =
1244 !dsa->db_can_write ||
1245 (!dsa->depth_write_enabled &&
1246 si_order_invariant_stencil_state(&state->stencil[0]) &&
1247 si_order_invariant_stencil_state(&state->stencil[1]));
1248
1249 dsa->order_invariance[1].zs =
1250 nozwrite_and_order_invariant_stencil ||
1251 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1252 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1253
1254 dsa->order_invariance[1].pass_set =
1255 nozwrite_and_order_invariant_stencil ||
1256 (!dsa->stencil_write_enabled &&
1257 (state->depth.func == PIPE_FUNC_ALWAYS ||
1258 state->depth.func == PIPE_FUNC_NEVER));
1259 dsa->order_invariance[0].pass_set =
1260 !dsa->depth_write_enabled ||
1261 (state->depth.func == PIPE_FUNC_ALWAYS ||
1262 state->depth.func == PIPE_FUNC_NEVER);
1263
1264 dsa->order_invariance[1].pass_last =
1265 sctx->screen->assume_no_z_fights &&
1266 !dsa->stencil_write_enabled &&
1267 dsa->depth_write_enabled && zfunc_is_ordered;
1268 dsa->order_invariance[0].pass_last =
1269 sctx->screen->assume_no_z_fights &&
1270 dsa->depth_write_enabled && zfunc_is_ordered;
1271
1272 return dsa;
1273 }
1274
1275 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1276 {
1277 struct si_context *sctx = (struct si_context *)ctx;
1278 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1279 struct si_state_dsa *dsa = state;
1280
1281 if (!state)
1282 return;
1283
1284 si_pm4_bind_state(sctx, dsa, dsa);
1285
1286 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1287 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1288 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1289 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1290 }
1291
1292 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1293 sctx->do_update_shaders = true;
1294
1295 if (sctx->screen->dpbb_allowed &&
1296 (!old_dsa ||
1297 (old_dsa->depth_enabled != dsa->depth_enabled ||
1298 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1299 old_dsa->db_can_write != dsa->db_can_write)))
1300 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1301
1302 if (sctx->screen->has_out_of_order_rast &&
1303 (!old_dsa ||
1304 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1305 sizeof(old_dsa->order_invariance))))
1306 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1307 }
1308
1309 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1310 {
1311 struct si_context *sctx = (struct si_context *)ctx;
1312 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1313 }
1314
1315 static void *si_create_db_flush_dsa(struct si_context *sctx)
1316 {
1317 struct pipe_depth_stencil_alpha_state dsa = {};
1318
1319 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1320 }
1321
1322 /* DB RENDER STATE */
1323
1324 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1325 {
1326 struct si_context *sctx = (struct si_context*)ctx;
1327
1328 /* Pipeline stat & streamout queries. */
1329 if (enable) {
1330 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1331 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1332 } else {
1333 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1334 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1335 }
1336
1337 /* Occlusion queries. */
1338 if (sctx->occlusion_queries_disabled != !enable) {
1339 sctx->occlusion_queries_disabled = !enable;
1340 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1341 }
1342 }
1343
1344 void si_set_occlusion_query_state(struct si_context *sctx,
1345 bool old_perfect_enable)
1346 {
1347 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1348
1349 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1350
1351 if (perfect_enable != old_perfect_enable)
1352 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1353 }
1354
1355 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1356 {
1357 st->saved_compute = sctx->cs_shader_state.program;
1358
1359 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1360 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1361 }
1362
1363 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1364 {
1365 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1366 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1367 unsigned db_shader_control;
1368
1369 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1370
1371 /* DB_RENDER_CONTROL */
1372 if (sctx->dbcb_depth_copy_enabled ||
1373 sctx->dbcb_stencil_copy_enabled) {
1374 radeon_emit(cs,
1375 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1376 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1377 S_028000_COPY_CENTROID(1) |
1378 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1379 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1380 radeon_emit(cs,
1381 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1382 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1383 } else {
1384 radeon_emit(cs,
1385 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1386 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1387 }
1388
1389 /* DB_COUNT_CONTROL (occlusion queries) */
1390 if (sctx->num_occlusion_queries > 0 &&
1391 !sctx->occlusion_queries_disabled) {
1392 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1393
1394 if (sctx->chip_class >= CIK) {
1395 radeon_emit(cs,
1396 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1397 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1398 S_028004_ZPASS_ENABLE(1) |
1399 S_028004_SLICE_EVEN_ENABLE(1) |
1400 S_028004_SLICE_ODD_ENABLE(1));
1401 } else {
1402 radeon_emit(cs,
1403 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1404 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1405 }
1406 } else {
1407 /* Disable occlusion queries. */
1408 if (sctx->chip_class >= CIK) {
1409 radeon_emit(cs, 0);
1410 } else {
1411 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1412 }
1413 }
1414
1415 /* DB_RENDER_OVERRIDE2 */
1416 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1417 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1418 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1419 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1420
1421 db_shader_control = sctx->ps_db_shader_control;
1422
1423 /* Bug workaround for smoothing (overrasterization) on SI. */
1424 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1425 db_shader_control &= C_02880C_Z_ORDER;
1426 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1427 }
1428
1429 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1430 if (!rs || !rs->multisample_enable)
1431 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1432
1433 if (sctx->screen->has_rbplus &&
1434 !sctx->screen->rbplus_allowed)
1435 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1436
1437 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1438 db_shader_control);
1439 }
1440
1441 /*
1442 * format translation
1443 */
1444 static uint32_t si_translate_colorformat(enum pipe_format format)
1445 {
1446 const struct util_format_description *desc = util_format_description(format);
1447 if (!desc)
1448 return V_028C70_COLOR_INVALID;
1449
1450 #define HAS_SIZE(x,y,z,w) \
1451 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1452 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1453
1454 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1455 return V_028C70_COLOR_10_11_11;
1456
1457 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1458 return V_028C70_COLOR_INVALID;
1459
1460 /* hw cannot support mixed formats (except depth/stencil, since
1461 * stencil is not written to). */
1462 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1463 return V_028C70_COLOR_INVALID;
1464
1465 switch (desc->nr_channels) {
1466 case 1:
1467 switch (desc->channel[0].size) {
1468 case 8:
1469 return V_028C70_COLOR_8;
1470 case 16:
1471 return V_028C70_COLOR_16;
1472 case 32:
1473 return V_028C70_COLOR_32;
1474 }
1475 break;
1476 case 2:
1477 if (desc->channel[0].size == desc->channel[1].size) {
1478 switch (desc->channel[0].size) {
1479 case 8:
1480 return V_028C70_COLOR_8_8;
1481 case 16:
1482 return V_028C70_COLOR_16_16;
1483 case 32:
1484 return V_028C70_COLOR_32_32;
1485 }
1486 } else if (HAS_SIZE(8,24,0,0)) {
1487 return V_028C70_COLOR_24_8;
1488 } else if (HAS_SIZE(24,8,0,0)) {
1489 return V_028C70_COLOR_8_24;
1490 }
1491 break;
1492 case 3:
1493 if (HAS_SIZE(5,6,5,0)) {
1494 return V_028C70_COLOR_5_6_5;
1495 } else if (HAS_SIZE(32,8,24,0)) {
1496 return V_028C70_COLOR_X24_8_32_FLOAT;
1497 }
1498 break;
1499 case 4:
1500 if (desc->channel[0].size == desc->channel[1].size &&
1501 desc->channel[0].size == desc->channel[2].size &&
1502 desc->channel[0].size == desc->channel[3].size) {
1503 switch (desc->channel[0].size) {
1504 case 4:
1505 return V_028C70_COLOR_4_4_4_4;
1506 case 8:
1507 return V_028C70_COLOR_8_8_8_8;
1508 case 16:
1509 return V_028C70_COLOR_16_16_16_16;
1510 case 32:
1511 return V_028C70_COLOR_32_32_32_32;
1512 }
1513 } else if (HAS_SIZE(5,5,5,1)) {
1514 return V_028C70_COLOR_1_5_5_5;
1515 } else if (HAS_SIZE(1,5,5,5)) {
1516 return V_028C70_COLOR_5_5_5_1;
1517 } else if (HAS_SIZE(10,10,10,2)) {
1518 return V_028C70_COLOR_2_10_10_10;
1519 }
1520 break;
1521 }
1522 return V_028C70_COLOR_INVALID;
1523 }
1524
1525 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1526 {
1527 if (SI_BIG_ENDIAN) {
1528 switch(colorformat) {
1529 /* 8-bit buffers. */
1530 case V_028C70_COLOR_8:
1531 return V_028C70_ENDIAN_NONE;
1532
1533 /* 16-bit buffers. */
1534 case V_028C70_COLOR_5_6_5:
1535 case V_028C70_COLOR_1_5_5_5:
1536 case V_028C70_COLOR_4_4_4_4:
1537 case V_028C70_COLOR_16:
1538 case V_028C70_COLOR_8_8:
1539 return V_028C70_ENDIAN_8IN16;
1540
1541 /* 32-bit buffers. */
1542 case V_028C70_COLOR_8_8_8_8:
1543 case V_028C70_COLOR_2_10_10_10:
1544 case V_028C70_COLOR_8_24:
1545 case V_028C70_COLOR_24_8:
1546 case V_028C70_COLOR_16_16:
1547 return V_028C70_ENDIAN_8IN32;
1548
1549 /* 64-bit buffers. */
1550 case V_028C70_COLOR_16_16_16_16:
1551 return V_028C70_ENDIAN_8IN16;
1552
1553 case V_028C70_COLOR_32_32:
1554 return V_028C70_ENDIAN_8IN32;
1555
1556 /* 128-bit buffers. */
1557 case V_028C70_COLOR_32_32_32_32:
1558 return V_028C70_ENDIAN_8IN32;
1559 default:
1560 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1561 }
1562 } else {
1563 return V_028C70_ENDIAN_NONE;
1564 }
1565 }
1566
1567 static uint32_t si_translate_dbformat(enum pipe_format format)
1568 {
1569 switch (format) {
1570 case PIPE_FORMAT_Z16_UNORM:
1571 return V_028040_Z_16;
1572 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1573 case PIPE_FORMAT_X8Z24_UNORM:
1574 case PIPE_FORMAT_Z24X8_UNORM:
1575 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1576 return V_028040_Z_24; /* deprecated on SI */
1577 case PIPE_FORMAT_Z32_FLOAT:
1578 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1579 return V_028040_Z_32_FLOAT;
1580 default:
1581 return V_028040_Z_INVALID;
1582 }
1583 }
1584
1585 /*
1586 * Texture translation
1587 */
1588
1589 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1590 enum pipe_format format,
1591 const struct util_format_description *desc,
1592 int first_non_void)
1593 {
1594 struct si_screen *sscreen = (struct si_screen*)screen;
1595 bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
1596 sscreen->info.drm_minor >= 31) ||
1597 sscreen->info.drm_major == 3;
1598 bool uniform = true;
1599 int i;
1600
1601 /* Colorspace (return non-RGB formats directly). */
1602 switch (desc->colorspace) {
1603 /* Depth stencil formats */
1604 case UTIL_FORMAT_COLORSPACE_ZS:
1605 switch (format) {
1606 case PIPE_FORMAT_Z16_UNORM:
1607 return V_008F14_IMG_DATA_FORMAT_16;
1608 case PIPE_FORMAT_X24S8_UINT:
1609 case PIPE_FORMAT_S8X24_UINT:
1610 /*
1611 * Implemented as an 8_8_8_8 data format to fix texture
1612 * gathers in stencil sampling. This affects at least
1613 * GL45-CTS.texture_cube_map_array.sampling on VI.
1614 */
1615 if (sscreen->info.chip_class <= VI)
1616 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1617
1618 if (format == PIPE_FORMAT_X24S8_UINT)
1619 return V_008F14_IMG_DATA_FORMAT_8_24;
1620 else
1621 return V_008F14_IMG_DATA_FORMAT_24_8;
1622 case PIPE_FORMAT_Z24X8_UNORM:
1623 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1624 return V_008F14_IMG_DATA_FORMAT_8_24;
1625 case PIPE_FORMAT_X8Z24_UNORM:
1626 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1627 return V_008F14_IMG_DATA_FORMAT_24_8;
1628 case PIPE_FORMAT_S8_UINT:
1629 return V_008F14_IMG_DATA_FORMAT_8;
1630 case PIPE_FORMAT_Z32_FLOAT:
1631 return V_008F14_IMG_DATA_FORMAT_32;
1632 case PIPE_FORMAT_X32_S8X24_UINT:
1633 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1634 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1635 default:
1636 goto out_unknown;
1637 }
1638
1639 case UTIL_FORMAT_COLORSPACE_YUV:
1640 goto out_unknown; /* TODO */
1641
1642 case UTIL_FORMAT_COLORSPACE_SRGB:
1643 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1644 goto out_unknown;
1645 break;
1646
1647 default:
1648 break;
1649 }
1650
1651 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1652 if (!enable_compressed_formats)
1653 goto out_unknown;
1654
1655 switch (format) {
1656 case PIPE_FORMAT_RGTC1_SNORM:
1657 case PIPE_FORMAT_LATC1_SNORM:
1658 case PIPE_FORMAT_RGTC1_UNORM:
1659 case PIPE_FORMAT_LATC1_UNORM:
1660 return V_008F14_IMG_DATA_FORMAT_BC4;
1661 case PIPE_FORMAT_RGTC2_SNORM:
1662 case PIPE_FORMAT_LATC2_SNORM:
1663 case PIPE_FORMAT_RGTC2_UNORM:
1664 case PIPE_FORMAT_LATC2_UNORM:
1665 return V_008F14_IMG_DATA_FORMAT_BC5;
1666 default:
1667 goto out_unknown;
1668 }
1669 }
1670
1671 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1672 (sscreen->info.family == CHIP_STONEY ||
1673 sscreen->info.family == CHIP_VEGA10 ||
1674 sscreen->info.family == CHIP_RAVEN)) {
1675 switch (format) {
1676 case PIPE_FORMAT_ETC1_RGB8:
1677 case PIPE_FORMAT_ETC2_RGB8:
1678 case PIPE_FORMAT_ETC2_SRGB8:
1679 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1680 case PIPE_FORMAT_ETC2_RGB8A1:
1681 case PIPE_FORMAT_ETC2_SRGB8A1:
1682 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1683 case PIPE_FORMAT_ETC2_RGBA8:
1684 case PIPE_FORMAT_ETC2_SRGBA8:
1685 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1686 case PIPE_FORMAT_ETC2_R11_UNORM:
1687 case PIPE_FORMAT_ETC2_R11_SNORM:
1688 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1689 case PIPE_FORMAT_ETC2_RG11_UNORM:
1690 case PIPE_FORMAT_ETC2_RG11_SNORM:
1691 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1692 default:
1693 goto out_unknown;
1694 }
1695 }
1696
1697 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1698 if (!enable_compressed_formats)
1699 goto out_unknown;
1700
1701 switch (format) {
1702 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1703 case PIPE_FORMAT_BPTC_SRGBA:
1704 return V_008F14_IMG_DATA_FORMAT_BC7;
1705 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1706 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1707 return V_008F14_IMG_DATA_FORMAT_BC6;
1708 default:
1709 goto out_unknown;
1710 }
1711 }
1712
1713 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1714 switch (format) {
1715 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1716 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1717 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1718 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1719 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1720 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1721 default:
1722 goto out_unknown;
1723 }
1724 }
1725
1726 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1727 if (!enable_compressed_formats)
1728 goto out_unknown;
1729
1730 switch (format) {
1731 case PIPE_FORMAT_DXT1_RGB:
1732 case PIPE_FORMAT_DXT1_RGBA:
1733 case PIPE_FORMAT_DXT1_SRGB:
1734 case PIPE_FORMAT_DXT1_SRGBA:
1735 return V_008F14_IMG_DATA_FORMAT_BC1;
1736 case PIPE_FORMAT_DXT3_RGBA:
1737 case PIPE_FORMAT_DXT3_SRGBA:
1738 return V_008F14_IMG_DATA_FORMAT_BC2;
1739 case PIPE_FORMAT_DXT5_RGBA:
1740 case PIPE_FORMAT_DXT5_SRGBA:
1741 return V_008F14_IMG_DATA_FORMAT_BC3;
1742 default:
1743 goto out_unknown;
1744 }
1745 }
1746
1747 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1748 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1749 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1750 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1751 }
1752
1753 /* R8G8Bx_SNORM - TODO CxV8U8 */
1754
1755 /* hw cannot support mixed formats (except depth/stencil, since only
1756 * depth is read).*/
1757 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1758 goto out_unknown;
1759
1760 /* See whether the components are of the same size. */
1761 for (i = 1; i < desc->nr_channels; i++) {
1762 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1763 }
1764
1765 /* Non-uniform formats. */
1766 if (!uniform) {
1767 switch(desc->nr_channels) {
1768 case 3:
1769 if (desc->channel[0].size == 5 &&
1770 desc->channel[1].size == 6 &&
1771 desc->channel[2].size == 5) {
1772 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1773 }
1774 goto out_unknown;
1775 case 4:
1776 if (desc->channel[0].size == 5 &&
1777 desc->channel[1].size == 5 &&
1778 desc->channel[2].size == 5 &&
1779 desc->channel[3].size == 1) {
1780 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1781 }
1782 if (desc->channel[0].size == 1 &&
1783 desc->channel[1].size == 5 &&
1784 desc->channel[2].size == 5 &&
1785 desc->channel[3].size == 5) {
1786 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1787 }
1788 if (desc->channel[0].size == 10 &&
1789 desc->channel[1].size == 10 &&
1790 desc->channel[2].size == 10 &&
1791 desc->channel[3].size == 2) {
1792 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1793 }
1794 goto out_unknown;
1795 }
1796 goto out_unknown;
1797 }
1798
1799 if (first_non_void < 0 || first_non_void > 3)
1800 goto out_unknown;
1801
1802 /* uniform formats */
1803 switch (desc->channel[first_non_void].size) {
1804 case 4:
1805 switch (desc->nr_channels) {
1806 #if 0 /* Not supported for render targets */
1807 case 2:
1808 return V_008F14_IMG_DATA_FORMAT_4_4;
1809 #endif
1810 case 4:
1811 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1812 }
1813 break;
1814 case 8:
1815 switch (desc->nr_channels) {
1816 case 1:
1817 return V_008F14_IMG_DATA_FORMAT_8;
1818 case 2:
1819 return V_008F14_IMG_DATA_FORMAT_8_8;
1820 case 4:
1821 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1822 }
1823 break;
1824 case 16:
1825 switch (desc->nr_channels) {
1826 case 1:
1827 return V_008F14_IMG_DATA_FORMAT_16;
1828 case 2:
1829 return V_008F14_IMG_DATA_FORMAT_16_16;
1830 case 4:
1831 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1832 }
1833 break;
1834 case 32:
1835 switch (desc->nr_channels) {
1836 case 1:
1837 return V_008F14_IMG_DATA_FORMAT_32;
1838 case 2:
1839 return V_008F14_IMG_DATA_FORMAT_32_32;
1840 #if 0 /* Not supported for render targets */
1841 case 3:
1842 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1843 #endif
1844 case 4:
1845 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1846 }
1847 }
1848
1849 out_unknown:
1850 return ~0;
1851 }
1852
1853 static unsigned si_tex_wrap(unsigned wrap)
1854 {
1855 switch (wrap) {
1856 default:
1857 case PIPE_TEX_WRAP_REPEAT:
1858 return V_008F30_SQ_TEX_WRAP;
1859 case PIPE_TEX_WRAP_CLAMP:
1860 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1861 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1862 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1863 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1864 return V_008F30_SQ_TEX_CLAMP_BORDER;
1865 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1866 return V_008F30_SQ_TEX_MIRROR;
1867 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1868 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1869 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1870 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1871 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1872 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1873 }
1874 }
1875
1876 static unsigned si_tex_mipfilter(unsigned filter)
1877 {
1878 switch (filter) {
1879 case PIPE_TEX_MIPFILTER_NEAREST:
1880 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1881 case PIPE_TEX_MIPFILTER_LINEAR:
1882 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1883 default:
1884 case PIPE_TEX_MIPFILTER_NONE:
1885 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1886 }
1887 }
1888
1889 static unsigned si_tex_compare(unsigned compare)
1890 {
1891 switch (compare) {
1892 default:
1893 case PIPE_FUNC_NEVER:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1895 case PIPE_FUNC_LESS:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1897 case PIPE_FUNC_EQUAL:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1899 case PIPE_FUNC_LEQUAL:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1901 case PIPE_FUNC_GREATER:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1903 case PIPE_FUNC_NOTEQUAL:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1905 case PIPE_FUNC_GEQUAL:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1907 case PIPE_FUNC_ALWAYS:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1909 }
1910 }
1911
1912 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1913 unsigned view_target, unsigned nr_samples)
1914 {
1915 unsigned res_target = rtex->resource.b.b.target;
1916
1917 if (view_target == PIPE_TEXTURE_CUBE ||
1918 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1919 res_target = view_target;
1920 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1921 else if (res_target == PIPE_TEXTURE_CUBE ||
1922 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1923 res_target = PIPE_TEXTURE_2D_ARRAY;
1924
1925 /* GFX9 allocates 1D textures as 2D. */
1926 if ((res_target == PIPE_TEXTURE_1D ||
1927 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1928 sscreen->info.chip_class >= GFX9 &&
1929 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1930 if (res_target == PIPE_TEXTURE_1D)
1931 res_target = PIPE_TEXTURE_2D;
1932 else
1933 res_target = PIPE_TEXTURE_2D_ARRAY;
1934 }
1935
1936 switch (res_target) {
1937 default:
1938 case PIPE_TEXTURE_1D:
1939 return V_008F1C_SQ_RSRC_IMG_1D;
1940 case PIPE_TEXTURE_1D_ARRAY:
1941 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1942 case PIPE_TEXTURE_2D:
1943 case PIPE_TEXTURE_RECT:
1944 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1945 V_008F1C_SQ_RSRC_IMG_2D;
1946 case PIPE_TEXTURE_2D_ARRAY:
1947 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1948 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1949 case PIPE_TEXTURE_3D:
1950 return V_008F1C_SQ_RSRC_IMG_3D;
1951 case PIPE_TEXTURE_CUBE:
1952 case PIPE_TEXTURE_CUBE_ARRAY:
1953 return V_008F1C_SQ_RSRC_IMG_CUBE;
1954 }
1955 }
1956
1957 /*
1958 * Format support testing
1959 */
1960
1961 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1962 {
1963 const struct util_format_description *desc = util_format_description(format);
1964 if (!desc)
1965 return false;
1966
1967 return si_translate_texformat(screen, format, desc,
1968 util_format_get_first_non_void_channel(format)) != ~0U;
1969 }
1970
1971 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1972 const struct util_format_description *desc,
1973 int first_non_void)
1974 {
1975 int i;
1976
1977 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1978 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1979
1980 assert(first_non_void >= 0);
1981
1982 if (desc->nr_channels == 4 &&
1983 desc->channel[0].size == 10 &&
1984 desc->channel[1].size == 10 &&
1985 desc->channel[2].size == 10 &&
1986 desc->channel[3].size == 2)
1987 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1988
1989 /* See whether the components are of the same size. */
1990 for (i = 0; i < desc->nr_channels; i++) {
1991 if (desc->channel[first_non_void].size != desc->channel[i].size)
1992 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1993 }
1994
1995 switch (desc->channel[first_non_void].size) {
1996 case 8:
1997 switch (desc->nr_channels) {
1998 case 1:
1999 case 3: /* 3 loads */
2000 return V_008F0C_BUF_DATA_FORMAT_8;
2001 case 2:
2002 return V_008F0C_BUF_DATA_FORMAT_8_8;
2003 case 4:
2004 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2005 }
2006 break;
2007 case 16:
2008 switch (desc->nr_channels) {
2009 case 1:
2010 case 3: /* 3 loads */
2011 return V_008F0C_BUF_DATA_FORMAT_16;
2012 case 2:
2013 return V_008F0C_BUF_DATA_FORMAT_16_16;
2014 case 4:
2015 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2016 }
2017 break;
2018 case 32:
2019 switch (desc->nr_channels) {
2020 case 1:
2021 return V_008F0C_BUF_DATA_FORMAT_32;
2022 case 2:
2023 return V_008F0C_BUF_DATA_FORMAT_32_32;
2024 case 3:
2025 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2026 case 4:
2027 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2028 }
2029 break;
2030 case 64:
2031 /* Legacy double formats. */
2032 switch (desc->nr_channels) {
2033 case 1: /* 1 load */
2034 return V_008F0C_BUF_DATA_FORMAT_32_32;
2035 case 2: /* 1 load */
2036 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2037 case 3: /* 3 loads */
2038 return V_008F0C_BUF_DATA_FORMAT_32_32;
2039 case 4: /* 2 loads */
2040 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2041 }
2042 break;
2043 }
2044
2045 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2046 }
2047
2048 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2049 const struct util_format_description *desc,
2050 int first_non_void)
2051 {
2052 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2053 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2054
2055 assert(first_non_void >= 0);
2056
2057 switch (desc->channel[first_non_void].type) {
2058 case UTIL_FORMAT_TYPE_SIGNED:
2059 case UTIL_FORMAT_TYPE_FIXED:
2060 if (desc->channel[first_non_void].size >= 32 ||
2061 desc->channel[first_non_void].pure_integer)
2062 return V_008F0C_BUF_NUM_FORMAT_SINT;
2063 else if (desc->channel[first_non_void].normalized)
2064 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2065 else
2066 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2067 break;
2068 case UTIL_FORMAT_TYPE_UNSIGNED:
2069 if (desc->channel[first_non_void].size >= 32 ||
2070 desc->channel[first_non_void].pure_integer)
2071 return V_008F0C_BUF_NUM_FORMAT_UINT;
2072 else if (desc->channel[first_non_void].normalized)
2073 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2074 else
2075 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2076 break;
2077 case UTIL_FORMAT_TYPE_FLOAT:
2078 default:
2079 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2080 }
2081 }
2082
2083 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2084 enum pipe_format format,
2085 unsigned usage)
2086 {
2087 const struct util_format_description *desc;
2088 int first_non_void;
2089 unsigned data_format;
2090
2091 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2092 PIPE_BIND_SAMPLER_VIEW |
2093 PIPE_BIND_VERTEX_BUFFER)) == 0);
2094
2095 desc = util_format_description(format);
2096 if (!desc)
2097 return 0;
2098
2099 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2100 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2101 * for read-only access (with caveats surrounding bounds checks), but
2102 * obviously fails for write access which we have to implement for
2103 * shader images. Luckily, OpenGL doesn't expect this to be supported
2104 * anyway, and so the only impact is on PBO uploads / downloads, which
2105 * shouldn't be expected to be fast for GL_RGB anyway.
2106 */
2107 if (desc->block.bits == 3 * 8 ||
2108 desc->block.bits == 3 * 16) {
2109 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2110 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2111 if (!usage)
2112 return 0;
2113 }
2114 }
2115
2116 first_non_void = util_format_get_first_non_void_channel(format);
2117 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2118 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2119 return 0;
2120
2121 return usage;
2122 }
2123
2124 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2125 {
2126 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2127 si_translate_colorswap(format, false) != ~0U;
2128 }
2129
2130 static bool si_is_zs_format_supported(enum pipe_format format)
2131 {
2132 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2133 }
2134
2135 static boolean si_is_format_supported(struct pipe_screen *screen,
2136 enum pipe_format format,
2137 enum pipe_texture_target target,
2138 unsigned sample_count,
2139 unsigned usage)
2140 {
2141 unsigned retval = 0;
2142
2143 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2144 PRINT_ERR("r600: unsupported texture type %d\n", target);
2145 return false;
2146 }
2147
2148 if (!util_format_is_supported(format, usage))
2149 return false;
2150
2151 if (sample_count > 1) {
2152 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2153 return false;
2154
2155 if (usage & PIPE_BIND_SHADER_IMAGE)
2156 return false;
2157
2158 switch (sample_count) {
2159 case 2:
2160 case 4:
2161 case 8:
2162 break;
2163 case 16:
2164 if (format == PIPE_FORMAT_NONE)
2165 return true;
2166 else
2167 return false;
2168 default:
2169 return false;
2170 }
2171 }
2172
2173 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2174 PIPE_BIND_SHADER_IMAGE)) {
2175 if (target == PIPE_BUFFER) {
2176 retval |= si_is_vertex_format_supported(
2177 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2178 PIPE_BIND_SHADER_IMAGE));
2179 } else {
2180 if (si_is_sampler_format_supported(screen, format))
2181 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2182 PIPE_BIND_SHADER_IMAGE);
2183 }
2184 }
2185
2186 if ((usage & (PIPE_BIND_RENDER_TARGET |
2187 PIPE_BIND_DISPLAY_TARGET |
2188 PIPE_BIND_SCANOUT |
2189 PIPE_BIND_SHARED |
2190 PIPE_BIND_BLENDABLE)) &&
2191 si_is_colorbuffer_format_supported(format)) {
2192 retval |= usage &
2193 (PIPE_BIND_RENDER_TARGET |
2194 PIPE_BIND_DISPLAY_TARGET |
2195 PIPE_BIND_SCANOUT |
2196 PIPE_BIND_SHARED);
2197 if (!util_format_is_pure_integer(format) &&
2198 !util_format_is_depth_or_stencil(format))
2199 retval |= usage & PIPE_BIND_BLENDABLE;
2200 }
2201
2202 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2203 si_is_zs_format_supported(format)) {
2204 retval |= PIPE_BIND_DEPTH_STENCIL;
2205 }
2206
2207 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2208 retval |= si_is_vertex_format_supported(screen, format,
2209 PIPE_BIND_VERTEX_BUFFER);
2210 }
2211
2212 if ((usage & PIPE_BIND_LINEAR) &&
2213 !util_format_is_compressed(format) &&
2214 !(usage & PIPE_BIND_DEPTH_STENCIL))
2215 retval |= PIPE_BIND_LINEAR;
2216
2217 return retval == usage;
2218 }
2219
2220 /*
2221 * framebuffer handling
2222 */
2223
2224 static void si_choose_spi_color_formats(struct r600_surface *surf,
2225 unsigned format, unsigned swap,
2226 unsigned ntype, bool is_depth)
2227 {
2228 /* Alpha is needed for alpha-to-coverage.
2229 * Blending may be with or without alpha.
2230 */
2231 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2232 unsigned alpha = 0; /* exports alpha, but may not support blending */
2233 unsigned blend = 0; /* supports blending, but may not export alpha */
2234 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2235
2236 /* Choose the SPI color formats. These are required values for RB+.
2237 * Other chips have multiple choices, though they are not necessarily better.
2238 */
2239 switch (format) {
2240 case V_028C70_COLOR_5_6_5:
2241 case V_028C70_COLOR_1_5_5_5:
2242 case V_028C70_COLOR_5_5_5_1:
2243 case V_028C70_COLOR_4_4_4_4:
2244 case V_028C70_COLOR_10_11_11:
2245 case V_028C70_COLOR_11_11_10:
2246 case V_028C70_COLOR_8:
2247 case V_028C70_COLOR_8_8:
2248 case V_028C70_COLOR_8_8_8_8:
2249 case V_028C70_COLOR_10_10_10_2:
2250 case V_028C70_COLOR_2_10_10_10:
2251 if (ntype == V_028C70_NUMBER_UINT)
2252 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2253 else if (ntype == V_028C70_NUMBER_SINT)
2254 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2255 else
2256 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2257 break;
2258
2259 case V_028C70_COLOR_16:
2260 case V_028C70_COLOR_16_16:
2261 case V_028C70_COLOR_16_16_16_16:
2262 if (ntype == V_028C70_NUMBER_UNORM ||
2263 ntype == V_028C70_NUMBER_SNORM) {
2264 /* UNORM16 and SNORM16 don't support blending */
2265 if (ntype == V_028C70_NUMBER_UNORM)
2266 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2267 else
2268 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2269
2270 /* Use 32 bits per channel for blending. */
2271 if (format == V_028C70_COLOR_16) {
2272 if (swap == V_028C70_SWAP_STD) { /* R */
2273 blend = V_028714_SPI_SHADER_32_R;
2274 blend_alpha = V_028714_SPI_SHADER_32_AR;
2275 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2276 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2277 else
2278 assert(0);
2279 } else if (format == V_028C70_COLOR_16_16) {
2280 if (swap == V_028C70_SWAP_STD) { /* RG */
2281 blend = V_028714_SPI_SHADER_32_GR;
2282 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2283 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2284 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2285 else
2286 assert(0);
2287 } else /* 16_16_16_16 */
2288 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2289 } else if (ntype == V_028C70_NUMBER_UINT)
2290 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2291 else if (ntype == V_028C70_NUMBER_SINT)
2292 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2293 else if (ntype == V_028C70_NUMBER_FLOAT)
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2295 else
2296 assert(0);
2297 break;
2298
2299 case V_028C70_COLOR_32:
2300 if (swap == V_028C70_SWAP_STD) { /* R */
2301 blend = normal = V_028714_SPI_SHADER_32_R;
2302 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2303 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2304 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2305 else
2306 assert(0);
2307 break;
2308
2309 case V_028C70_COLOR_32_32:
2310 if (swap == V_028C70_SWAP_STD) { /* RG */
2311 blend = normal = V_028714_SPI_SHADER_32_GR;
2312 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2313 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2314 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2315 else
2316 assert(0);
2317 break;
2318
2319 case V_028C70_COLOR_32_32_32_32:
2320 case V_028C70_COLOR_8_24:
2321 case V_028C70_COLOR_24_8:
2322 case V_028C70_COLOR_X24_8_32_FLOAT:
2323 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2324 break;
2325
2326 default:
2327 assert(0);
2328 return;
2329 }
2330
2331 /* The DB->CB copy needs 32_ABGR. */
2332 if (is_depth)
2333 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2334
2335 surf->spi_shader_col_format = normal;
2336 surf->spi_shader_col_format_alpha = alpha;
2337 surf->spi_shader_col_format_blend = blend;
2338 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2339 }
2340
2341 static void si_initialize_color_surface(struct si_context *sctx,
2342 struct r600_surface *surf)
2343 {
2344 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2345 unsigned color_info, color_attrib;
2346 unsigned format, swap, ntype, endian;
2347 const struct util_format_description *desc;
2348 int firstchan;
2349 unsigned blend_clamp = 0, blend_bypass = 0;
2350
2351 desc = util_format_description(surf->base.format);
2352 for (firstchan = 0; firstchan < 4; firstchan++) {
2353 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2354 break;
2355 }
2356 }
2357 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2358 ntype = V_028C70_NUMBER_FLOAT;
2359 } else {
2360 ntype = V_028C70_NUMBER_UNORM;
2361 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2362 ntype = V_028C70_NUMBER_SRGB;
2363 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2364 if (desc->channel[firstchan].pure_integer) {
2365 ntype = V_028C70_NUMBER_SINT;
2366 } else {
2367 assert(desc->channel[firstchan].normalized);
2368 ntype = V_028C70_NUMBER_SNORM;
2369 }
2370 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2371 if (desc->channel[firstchan].pure_integer) {
2372 ntype = V_028C70_NUMBER_UINT;
2373 } else {
2374 assert(desc->channel[firstchan].normalized);
2375 ntype = V_028C70_NUMBER_UNORM;
2376 }
2377 }
2378 }
2379
2380 format = si_translate_colorformat(surf->base.format);
2381 if (format == V_028C70_COLOR_INVALID) {
2382 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2383 }
2384 assert(format != V_028C70_COLOR_INVALID);
2385 swap = si_translate_colorswap(surf->base.format, false);
2386 endian = si_colorformat_endian_swap(format);
2387
2388 /* blend clamp should be set for all NORM/SRGB types */
2389 if (ntype == V_028C70_NUMBER_UNORM ||
2390 ntype == V_028C70_NUMBER_SNORM ||
2391 ntype == V_028C70_NUMBER_SRGB)
2392 blend_clamp = 1;
2393
2394 /* set blend bypass according to docs if SINT/UINT or
2395 8/24 COLOR variants */
2396 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2397 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2398 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2399 blend_clamp = 0;
2400 blend_bypass = 1;
2401 }
2402
2403 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2404 if (format == V_028C70_COLOR_8 ||
2405 format == V_028C70_COLOR_8_8 ||
2406 format == V_028C70_COLOR_8_8_8_8)
2407 surf->color_is_int8 = true;
2408 else if (format == V_028C70_COLOR_10_10_10_2 ||
2409 format == V_028C70_COLOR_2_10_10_10)
2410 surf->color_is_int10 = true;
2411 }
2412
2413 color_info = S_028C70_FORMAT(format) |
2414 S_028C70_COMP_SWAP(swap) |
2415 S_028C70_BLEND_CLAMP(blend_clamp) |
2416 S_028C70_BLEND_BYPASS(blend_bypass) |
2417 S_028C70_SIMPLE_FLOAT(1) |
2418 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2419 ntype != V_028C70_NUMBER_SNORM &&
2420 ntype != V_028C70_NUMBER_SRGB &&
2421 format != V_028C70_COLOR_8_24 &&
2422 format != V_028C70_COLOR_24_8) |
2423 S_028C70_NUMBER_TYPE(ntype) |
2424 S_028C70_ENDIAN(endian);
2425
2426 /* Intensity is implemented as Red, so treat it that way. */
2427 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2428 util_format_is_intensity(surf->base.format));
2429
2430 if (rtex->resource.b.b.nr_samples > 1) {
2431 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2432
2433 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2434 S_028C74_NUM_FRAGMENTS(log_samples);
2435
2436 if (rtex->fmask.size) {
2437 color_info |= S_028C70_COMPRESSION(1);
2438 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2439
2440 if (sctx->chip_class == SI) {
2441 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2442 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2443 }
2444 }
2445 }
2446
2447 if (sctx->chip_class >= VI) {
2448 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2449 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2450
2451 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2452 64 for APU because all of our APUs to date use DIMMs which have
2453 a request granularity size of 64B while all other chips have a
2454 32B request size */
2455 if (!sctx->screen->info.has_dedicated_vram)
2456 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2457
2458 if (rtex->resource.b.b.nr_samples > 1) {
2459 if (rtex->surface.bpe == 1)
2460 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2461 else if (rtex->surface.bpe == 2)
2462 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2463 }
2464
2465 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2466 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2467 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2468 }
2469
2470 /* This must be set for fast clear to work without FMASK. */
2471 if (!rtex->fmask.size && sctx->chip_class == SI) {
2472 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2473 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2474 }
2475
2476 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2477 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2478
2479 if (sctx->chip_class >= GFX9) {
2480 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2481
2482 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2483 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2484 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2485 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2486 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2487 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2488 }
2489
2490 surf->cb_color_view = color_view;
2491 surf->cb_color_info = color_info;
2492 surf->cb_color_attrib = color_attrib;
2493
2494 /* Determine pixel shader export format */
2495 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2496
2497 surf->color_initialized = true;
2498 }
2499
2500 static void si_init_depth_surface(struct si_context *sctx,
2501 struct r600_surface *surf)
2502 {
2503 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2504 unsigned level = surf->base.u.tex.level;
2505 unsigned format, stencil_format;
2506 uint32_t z_info, s_info;
2507
2508 format = si_translate_dbformat(rtex->db_render_format);
2509 stencil_format = rtex->surface.has_stencil ?
2510 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2511
2512 assert(format != V_028040_Z_INVALID);
2513 if (format == V_028040_Z_INVALID)
2514 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2515
2516 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2517 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2518 surf->db_htile_data_base = 0;
2519 surf->db_htile_surface = 0;
2520
2521 if (sctx->chip_class >= GFX9) {
2522 assert(rtex->surface.u.gfx9.surf_offset == 0);
2523 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2524 surf->db_stencil_base = (rtex->resource.gpu_address +
2525 rtex->surface.u.gfx9.stencil_offset) >> 8;
2526 z_info = S_028038_FORMAT(format) |
2527 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2528 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2529 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2530 s_info = S_02803C_FORMAT(stencil_format) |
2531 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2532 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2533 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2534 surf->db_depth_view |= S_028008_MIPID(level);
2535 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2536 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2537
2538 if (si_htile_enabled(rtex, level)) {
2539 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2540 S_028038_ALLOW_EXPCLEAR(1);
2541
2542 if (rtex->tc_compatible_htile) {
2543 unsigned max_zplanes = 4;
2544
2545 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2546 rtex->resource.b.b.nr_samples > 1)
2547 max_zplanes = 2;
2548
2549 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2550 S_028038_ITERATE_FLUSH(1);
2551 s_info |= S_02803C_ITERATE_FLUSH(1);
2552 }
2553
2554 if (rtex->surface.has_stencil) {
2555 /* Stencil buffer workaround ported from the SI-CI-VI code.
2556 * See that for explanation.
2557 */
2558 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2559 } else {
2560 /* Use all HTILE for depth if there's no stencil. */
2561 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2562 }
2563
2564 surf->db_htile_data_base = (rtex->resource.gpu_address +
2565 rtex->htile_offset) >> 8;
2566 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2567 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2568 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2569 }
2570 } else {
2571 /* SI-CI-VI */
2572 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2573
2574 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2575
2576 surf->db_depth_base = (rtex->resource.gpu_address +
2577 rtex->surface.u.legacy.level[level].offset) >> 8;
2578 surf->db_stencil_base = (rtex->resource.gpu_address +
2579 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2580
2581 z_info = S_028040_FORMAT(format) |
2582 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2583 s_info = S_028044_FORMAT(stencil_format);
2584 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2585
2586 if (sctx->chip_class >= CIK) {
2587 struct radeon_info *info = &sctx->screen->info;
2588 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2589 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2590 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2591 unsigned tile_mode = info->si_tile_mode_array[index];
2592 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2593 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2594
2595 surf->db_depth_info |=
2596 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2597 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2598 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2599 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2600 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2601 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2602 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2603 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2604 } else {
2605 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2606 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2607 tile_mode_index = si_tile_mode_index(rtex, level, true);
2608 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2609 }
2610
2611 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2612 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2613 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2614 levelinfo->nblk_y) / 64 - 1);
2615
2616 if (si_htile_enabled(rtex, level)) {
2617 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2618 S_028040_ALLOW_EXPCLEAR(1);
2619
2620 if (rtex->surface.has_stencil) {
2621 /* Workaround: For a not yet understood reason, the
2622 * combination of MSAA, fast stencil clear and stencil
2623 * decompress messes with subsequent stencil buffer
2624 * uses. Problem was reproduced on Verde, Bonaire,
2625 * Tonga, and Carrizo.
2626 *
2627 * Disabling EXPCLEAR works around the problem.
2628 *
2629 * Check piglit's arb_texture_multisample-stencil-clear
2630 * test if you want to try changing this.
2631 */
2632 if (rtex->resource.b.b.nr_samples <= 1)
2633 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2634 } else if (!rtex->tc_compatible_htile) {
2635 /* Use all of the htile_buffer for depth if there's no stencil.
2636 * This must not be set when TC-compatible HTILE is enabled
2637 * due to a hw bug.
2638 */
2639 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2640 }
2641
2642 surf->db_htile_data_base = (rtex->resource.gpu_address +
2643 rtex->htile_offset) >> 8;
2644 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2645
2646 if (rtex->tc_compatible_htile) {
2647 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2648
2649 if (rtex->resource.b.b.nr_samples <= 1)
2650 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2651 else if (rtex->resource.b.b.nr_samples <= 4)
2652 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2653 else
2654 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2655 }
2656 }
2657 }
2658
2659 surf->db_z_info = z_info;
2660 surf->db_stencil_info = s_info;
2661
2662 surf->depth_initialized = true;
2663 }
2664
2665 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2666 {
2667 if (sctx->decompression_enabled)
2668 return;
2669
2670 if (sctx->framebuffer.state.zsbuf) {
2671 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2672 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2673
2674 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2675
2676 if (rtex->surface.has_stencil)
2677 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2678 }
2679
2680 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2681 while (compressed_cb_mask) {
2682 unsigned i = u_bit_scan(&compressed_cb_mask);
2683 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2684 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2685
2686 if (rtex->fmask.size)
2687 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2688 if (rtex->dcc_gather_statistics)
2689 rtex->separate_dcc_dirty = true;
2690 }
2691 }
2692
2693 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2694 {
2695 for (int i = 0; i < state->nr_cbufs; ++i) {
2696 struct r600_surface *surf = NULL;
2697 struct r600_texture *rtex;
2698
2699 if (!state->cbufs[i])
2700 continue;
2701 surf = (struct r600_surface*)state->cbufs[i];
2702 rtex = (struct r600_texture*)surf->base.texture;
2703
2704 p_atomic_dec(&rtex->framebuffers_bound);
2705 }
2706 }
2707
2708 static void si_set_framebuffer_state(struct pipe_context *ctx,
2709 const struct pipe_framebuffer_state *state)
2710 {
2711 struct si_context *sctx = (struct si_context *)ctx;
2712 struct pipe_constant_buffer constbuf = {0};
2713 struct r600_surface *surf = NULL;
2714 struct r600_texture *rtex;
2715 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2716 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2717 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2718 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2719 bool old_has_stencil =
2720 old_has_zsbuf &&
2721 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2722 bool unbound = false;
2723 int i;
2724
2725 si_update_fb_dirtiness_after_rendering(sctx);
2726
2727 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2728 if (!sctx->framebuffer.state.cbufs[i])
2729 continue;
2730
2731 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2732 if (rtex->dcc_gather_statistics)
2733 vi_separate_dcc_stop_query(sctx, rtex);
2734 }
2735
2736 /* Disable DCC if the formats are incompatible. */
2737 for (i = 0; i < state->nr_cbufs; i++) {
2738 if (!state->cbufs[i])
2739 continue;
2740
2741 surf = (struct r600_surface*)state->cbufs[i];
2742 rtex = (struct r600_texture*)surf->base.texture;
2743
2744 if (!surf->dcc_incompatible)
2745 continue;
2746
2747 /* Since the DCC decompression calls back into set_framebuffer-
2748 * _state, we need to unbind the framebuffer, so that
2749 * vi_separate_dcc_stop_query isn't called twice with the same
2750 * color buffer.
2751 */
2752 if (!unbound) {
2753 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2754 unbound = true;
2755 }
2756
2757 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2758 if (!si_texture_disable_dcc(sctx, rtex))
2759 si_decompress_dcc(sctx, rtex);
2760
2761 surf->dcc_incompatible = false;
2762 }
2763
2764 /* Only flush TC when changing the framebuffer state, because
2765 * the only client not using TC that can change textures is
2766 * the framebuffer.
2767 *
2768 * Wait for compute shaders because of possible transitions:
2769 * - FB write -> shader read
2770 * - shader write -> FB read
2771 *
2772 * DB caches are flushed on demand (using si_decompress_textures).
2773 *
2774 * When MSAA is enabled, CB and TC caches are flushed on demand
2775 * (after FMASK decompression). Shader write -> FB read transitions
2776 * cannot happen for MSAA textures, because MSAA shader images are
2777 * not supported.
2778 *
2779 * Only flush and wait for CB if there is actually a bound color buffer.
2780 */
2781 if (sctx->framebuffer.uncompressed_cb_mask)
2782 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2783 sctx->framebuffer.CB_has_shader_readable_metadata);
2784
2785 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2786
2787 /* u_blitter doesn't invoke depth decompression when it does multiple
2788 * blits in a row, but the only case when it matters for DB is when
2789 * doing generate_mipmap. So here we flush DB manually between
2790 * individual generate_mipmap blits.
2791 * Note that lower mipmap levels aren't compressed.
2792 */
2793 if (sctx->generate_mipmap_for_depth) {
2794 si_make_DB_shader_coherent(sctx, 1, false,
2795 sctx->framebuffer.DB_has_shader_readable_metadata);
2796 } else if (sctx->chip_class == GFX9) {
2797 /* It appears that DB metadata "leaks" in a sequence of:
2798 * - depth clear
2799 * - DCC decompress for shader image writes (with DB disabled)
2800 * - render with DEPTH_BEFORE_SHADER=1
2801 * Flushing DB metadata works around the problem.
2802 */
2803 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2804 }
2805
2806 /* Take the maximum of the old and new count. If the new count is lower,
2807 * dirtying is needed to disable the unbound colorbuffers.
2808 */
2809 sctx->framebuffer.dirty_cbufs |=
2810 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2811 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2812
2813 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2814 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2815
2816 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2817 sctx->framebuffer.spi_shader_col_format = 0;
2818 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2819 sctx->framebuffer.spi_shader_col_format_blend = 0;
2820 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2821 sctx->framebuffer.color_is_int8 = 0;
2822 sctx->framebuffer.color_is_int10 = 0;
2823
2824 sctx->framebuffer.compressed_cb_mask = 0;
2825 sctx->framebuffer.uncompressed_cb_mask = 0;
2826 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2827 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2828 sctx->framebuffer.any_dst_linear = false;
2829 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2830 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2831
2832 for (i = 0; i < state->nr_cbufs; i++) {
2833 if (!state->cbufs[i])
2834 continue;
2835
2836 surf = (struct r600_surface*)state->cbufs[i];
2837 rtex = (struct r600_texture*)surf->base.texture;
2838
2839 if (!surf->color_initialized) {
2840 si_initialize_color_surface(sctx, surf);
2841 }
2842
2843 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2844 sctx->framebuffer.spi_shader_col_format |=
2845 surf->spi_shader_col_format << (i * 4);
2846 sctx->framebuffer.spi_shader_col_format_alpha |=
2847 surf->spi_shader_col_format_alpha << (i * 4);
2848 sctx->framebuffer.spi_shader_col_format_blend |=
2849 surf->spi_shader_col_format_blend << (i * 4);
2850 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2851 surf->spi_shader_col_format_blend_alpha << (i * 4);
2852
2853 if (surf->color_is_int8)
2854 sctx->framebuffer.color_is_int8 |= 1 << i;
2855 if (surf->color_is_int10)
2856 sctx->framebuffer.color_is_int10 |= 1 << i;
2857
2858 if (rtex->fmask.size)
2859 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2860 else
2861 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2862
2863 if (rtex->surface.is_linear)
2864 sctx->framebuffer.any_dst_linear = true;
2865
2866 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2867 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2868
2869 si_context_add_resource_size(sctx, surf->base.texture);
2870
2871 p_atomic_inc(&rtex->framebuffers_bound);
2872
2873 if (rtex->dcc_gather_statistics) {
2874 /* Dirty tracking must be enabled for DCC usage analysis. */
2875 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2876 vi_separate_dcc_start_query(sctx, rtex);
2877 }
2878 }
2879
2880 struct r600_texture *zstex = NULL;
2881
2882 if (state->zsbuf) {
2883 surf = (struct r600_surface*)state->zsbuf;
2884 zstex = (struct r600_texture*)surf->base.texture;
2885
2886 if (!surf->depth_initialized) {
2887 si_init_depth_surface(sctx, surf);
2888 }
2889
2890 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2891 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2892
2893 si_context_add_resource_size(sctx, surf->base.texture);
2894 }
2895
2896 si_update_ps_colorbuf0_slot(sctx);
2897 si_update_poly_offset_state(sctx);
2898 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2899 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2900
2901 if (sctx->screen->dpbb_allowed)
2902 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2903
2904 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2905 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2906
2907 if (sctx->screen->has_out_of_order_rast &&
2908 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2909 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2910 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2911 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2912
2913 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2914 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2915 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2916
2917 /* Set sample locations as fragment shader constants. */
2918 switch (sctx->framebuffer.nr_samples) {
2919 case 1:
2920 constbuf.user_buffer = sctx->sample_locations_1x;
2921 break;
2922 case 2:
2923 constbuf.user_buffer = sctx->sample_locations_2x;
2924 break;
2925 case 4:
2926 constbuf.user_buffer = sctx->sample_locations_4x;
2927 break;
2928 case 8:
2929 constbuf.user_buffer = sctx->sample_locations_8x;
2930 break;
2931 case 16:
2932 constbuf.user_buffer = sctx->sample_locations_16x;
2933 break;
2934 default:
2935 PRINT_ERR("Requested an invalid number of samples %i.\n",
2936 sctx->framebuffer.nr_samples);
2937 assert(0);
2938 }
2939 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2940 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2941
2942 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2943 }
2944
2945 sctx->do_update_shaders = true;
2946
2947 if (!sctx->decompression_enabled) {
2948 /* Prevent textures decompression when the framebuffer state
2949 * changes come from the decompression passes themselves.
2950 */
2951 sctx->need_check_render_feedback = true;
2952 }
2953 }
2954
2955 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2956 {
2957 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2958 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2959 unsigned i, nr_cbufs = state->nr_cbufs;
2960 struct r600_texture *tex = NULL;
2961 struct r600_surface *cb = NULL;
2962 unsigned cb_color_info = 0;
2963
2964 /* Colorbuffers. */
2965 for (i = 0; i < nr_cbufs; i++) {
2966 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2967 unsigned cb_color_attrib;
2968
2969 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2970 continue;
2971
2972 cb = (struct r600_surface*)state->cbufs[i];
2973 if (!cb) {
2974 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2975 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2976 continue;
2977 }
2978
2979 tex = (struct r600_texture *)cb->base.texture;
2980 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2981 &tex->resource, RADEON_USAGE_READWRITE,
2982 tex->resource.b.b.nr_samples > 1 ?
2983 RADEON_PRIO_COLOR_BUFFER_MSAA :
2984 RADEON_PRIO_COLOR_BUFFER);
2985
2986 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2987 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2988 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2989 RADEON_PRIO_CMASK);
2990 }
2991
2992 if (tex->dcc_separate_buffer)
2993 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2994 tex->dcc_separate_buffer,
2995 RADEON_USAGE_READWRITE,
2996 RADEON_PRIO_DCC);
2997
2998 /* Compute mutable surface parameters. */
2999 cb_color_base = tex->resource.gpu_address >> 8;
3000 cb_color_fmask = 0;
3001 cb_color_cmask = tex->cmask.base_address_reg;
3002 cb_dcc_base = 0;
3003 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3004 cb_color_attrib = cb->cb_color_attrib;
3005
3006 if (cb->base.u.tex.level > 0)
3007 cb_color_info &= C_028C70_FAST_CLEAR;
3008
3009 if (tex->fmask.size) {
3010 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
3011 cb_color_fmask |= tex->fmask.tile_swizzle;
3012 }
3013
3014 /* Set up DCC. */
3015 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3016 bool is_msaa_resolve_dst = state->cbufs[0] &&
3017 state->cbufs[0]->texture->nr_samples > 1 &&
3018 state->cbufs[1] == &cb->base &&
3019 state->cbufs[1]->texture->nr_samples <= 1;
3020
3021 if (!is_msaa_resolve_dst)
3022 cb_color_info |= S_028C70_DCC_ENABLE(1);
3023
3024 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3025 tex->dcc_offset) >> 8;
3026 cb_dcc_base |= tex->surface.tile_swizzle;
3027 }
3028
3029 if (sctx->chip_class >= GFX9) {
3030 struct gfx9_surf_meta_flags meta;
3031
3032 if (tex->dcc_offset)
3033 meta = tex->surface.u.gfx9.dcc;
3034 else
3035 meta = tex->surface.u.gfx9.cmask;
3036
3037 /* Set mutable surface parameters. */
3038 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3039 cb_color_base |= tex->surface.tile_swizzle;
3040 if (!tex->fmask.size)
3041 cb_color_fmask = cb_color_base;
3042 if (cb->base.u.tex.level > 0)
3043 cb_color_cmask = cb_color_base;
3044 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3045 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3046 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3047 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3048
3049 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3050 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3051 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3052 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3053 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3054 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3055 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3056 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3057 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3058 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3059 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3060 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3061 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3062 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3063 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3064 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3065
3066 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3067 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3068 } else {
3069 /* Compute mutable surface parameters (SI-CI-VI). */
3070 const struct legacy_surf_level *level_info =
3071 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3072 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3073 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3074
3075 cb_color_base += level_info->offset >> 8;
3076 /* Only macrotiled modes can set tile swizzle. */
3077 if (level_info->mode == RADEON_SURF_MODE_2D)
3078 cb_color_base |= tex->surface.tile_swizzle;
3079
3080 if (!tex->fmask.size)
3081 cb_color_fmask = cb_color_base;
3082 if (cb->base.u.tex.level > 0)
3083 cb_color_cmask = cb_color_base;
3084 if (cb_dcc_base)
3085 cb_dcc_base += level_info->dcc_offset >> 8;
3086
3087 pitch_tile_max = level_info->nblk_x / 8 - 1;
3088 slice_tile_max = level_info->nblk_x *
3089 level_info->nblk_y / 64 - 1;
3090 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3091
3092 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3093 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3094 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3095
3096 if (tex->fmask.size) {
3097 if (sctx->chip_class >= CIK)
3098 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3099 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3100 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3101 } else {
3102 /* This must be set for fast clear to work without FMASK. */
3103 if (sctx->chip_class >= CIK)
3104 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3105 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3106 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3107 }
3108
3109 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3110 sctx->chip_class >= VI ? 14 : 13);
3111 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3112 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3113 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3114 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3115 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3116 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3117 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3118 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3119 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3120 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3121 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3122 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3123 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3124
3125 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3126 radeon_emit(cs, cb_dcc_base);
3127 }
3128 }
3129 for (; i < 8 ; i++)
3130 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3131 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3132
3133 /* ZS buffer. */
3134 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3135 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3136 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3137
3138 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3139 &rtex->resource, RADEON_USAGE_READWRITE,
3140 zb->base.texture->nr_samples > 1 ?
3141 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3142 RADEON_PRIO_DEPTH_BUFFER);
3143
3144 if (sctx->chip_class >= GFX9) {
3145 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3146 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3147 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3148 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3149
3150 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3151 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3152 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3153 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3154 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3155 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3156 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3157 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3158 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3159 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3160 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3161 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3162
3163 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3164 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3165 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3166 } else {
3167 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3168
3169 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3170 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3171 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3172 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3173 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3174 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3175 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3176 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3177 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3178 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3179 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3180 }
3181
3182 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3183 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3184 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3185
3186 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3187 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3188 } else if (sctx->framebuffer.dirty_zsbuf) {
3189 if (sctx->chip_class >= GFX9)
3190 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3191 else
3192 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3193
3194 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3195 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3196 }
3197
3198 /* Framebuffer dimensions. */
3199 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3200 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3201 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3202
3203 if (sctx->screen->dfsm_allowed) {
3204 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3205 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3206 }
3207
3208 sctx->framebuffer.dirty_cbufs = 0;
3209 sctx->framebuffer.dirty_zsbuf = false;
3210 }
3211
3212 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3213 struct r600_atom *atom)
3214 {
3215 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3216 unsigned nr_samples = sctx->framebuffer.nr_samples;
3217 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3218
3219 /* Smoothing (only possible with nr_samples == 1) uses the same
3220 * sample locations as the MSAA it simulates.
3221 */
3222 if (nr_samples <= 1 && sctx->smoothing_enabled)
3223 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3224
3225 /* On Polaris, the small primitive filter uses the sample locations
3226 * even when MSAA is off, so we need to make sure they're set to 0.
3227 */
3228 if (has_msaa_sample_loc_bug)
3229 nr_samples = MAX2(nr_samples, 1);
3230
3231 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3232 sctx->msaa_sample_locs.nr_samples = nr_samples;
3233 si_emit_sample_locations(cs, nr_samples);
3234 }
3235
3236 if (sctx->family >= CHIP_POLARIS10) {
3237 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3238 unsigned small_prim_filter_cntl =
3239 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3240 /* line bug */
3241 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3242
3243 /* The alternative of setting sample locations to 0 would
3244 * require a DB flush to avoid Z errors, see
3245 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3246 */
3247 if (has_msaa_sample_loc_bug &&
3248 sctx->framebuffer.nr_samples > 1 &&
3249 rs && !rs->multisample_enable)
3250 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3251
3252 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3253 small_prim_filter_cntl);
3254 }
3255 }
3256
3257 static bool si_out_of_order_rasterization(struct si_context *sctx)
3258 {
3259 struct si_state_blend *blend = sctx->queued.named.blend;
3260 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3261
3262 if (!sctx->screen->has_out_of_order_rast)
3263 return false;
3264
3265 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3266
3267 if (blend) {
3268 colormask &= blend->cb_target_enabled_4bit;
3269 } else {
3270 colormask = 0;
3271 }
3272
3273 /* Conservative: No logic op. */
3274 if (colormask && blend->logicop_enable)
3275 return false;
3276
3277 struct si_dsa_order_invariance dsa_order_invariant = {
3278 .zs = true, .pass_set = true, .pass_last = false
3279 };
3280
3281 if (sctx->framebuffer.state.zsbuf) {
3282 struct r600_texture *zstex =
3283 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3284 bool has_stencil = zstex->surface.has_stencil;
3285 dsa_order_invariant = dsa->order_invariance[has_stencil];
3286 if (!dsa_order_invariant.zs)
3287 return false;
3288
3289 /* The set of PS invocations is always order invariant,
3290 * except when early Z/S tests are requested. */
3291 if (sctx->ps_shader.cso &&
3292 sctx->ps_shader.cso->info.writes_memory &&
3293 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3294 !dsa_order_invariant.pass_set)
3295 return false;
3296
3297 if (sctx->num_perfect_occlusion_queries != 0 &&
3298 !dsa_order_invariant.pass_set)
3299 return false;
3300 }
3301
3302 if (!colormask)
3303 return true;
3304
3305 unsigned blendmask = colormask & blend->blend_enable_4bit;
3306
3307 if (blendmask) {
3308 /* Only commutative blending. */
3309 if (blendmask & ~blend->commutative_4bit)
3310 return false;
3311
3312 if (!dsa_order_invariant.pass_set)
3313 return false;
3314 }
3315
3316 if (colormask & ~blendmask) {
3317 if (!dsa_order_invariant.pass_last)
3318 return false;
3319 }
3320
3321 return true;
3322 }
3323
3324 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3325 {
3326 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3327 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3328 /* 33% faster rendering to linear color buffers */
3329 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3330 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3331 unsigned sc_mode_cntl_1 =
3332 S_028A4C_WALK_SIZE(dst_is_linear) |
3333 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3334 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3335 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3336 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3337 /* always 1: */
3338 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3339 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3340 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3341 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3342 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3343 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3344
3345 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3346 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3347
3348 /* Required by OpenGL line rasterization.
3349 *
3350 * TODO: We should also enable perpendicular endcaps for AA lines,
3351 * but that requires implementing line stippling in the pixel
3352 * shader. SC can only do line stippling with axis-aligned
3353 * endcaps.
3354 */
3355 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3356
3357 if (setup_samples > 1) {
3358 /* distance from the pixel center, indexed by log2(nr_samples) */
3359 static unsigned max_dist[] = {
3360 0, /* unused */
3361 4, /* 2x MSAA */
3362 6, /* 4x MSAA */
3363 7, /* 8x MSAA */
3364 8, /* 16x MSAA */
3365 };
3366 unsigned log_samples = util_logbase2(setup_samples);
3367 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3368 unsigned log_ps_iter_samples =
3369 util_logbase2(util_next_power_of_two(ps_iter_samples));
3370
3371 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3372 radeon_emit(cs, sc_line_cntl |
3373 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3374 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3375 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3376 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3377
3378 if (sctx->framebuffer.nr_samples > 1) {
3379 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3380 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3381 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3382 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3383 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3384 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3385 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3386 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3387 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3388 sc_mode_cntl_1);
3389 } else if (sctx->smoothing_enabled) {
3390 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3391 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3392 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3393 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3394 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3395 sc_mode_cntl_1);
3396 }
3397 } else {
3398 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3399 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3400 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3401
3402 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3403 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3404 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3405 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3406 sc_mode_cntl_1);
3407 }
3408
3409 /* GFX9: Flush DFSM when the AA mode changes. */
3410 if (sctx->screen->dfsm_allowed) {
3411 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3412 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3413 }
3414 }
3415
3416 void si_update_ps_iter_samples(struct si_context *sctx)
3417 {
3418 if (sctx->framebuffer.nr_samples > 1)
3419 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3420 if (sctx->screen->dpbb_allowed)
3421 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3422 }
3423
3424 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3425 {
3426 struct si_context *sctx = (struct si_context *)ctx;
3427
3428 if (sctx->ps_iter_samples == min_samples)
3429 return;
3430
3431 sctx->ps_iter_samples = min_samples;
3432 sctx->do_update_shaders = true;
3433
3434 si_update_ps_iter_samples(sctx);
3435 }
3436
3437 /*
3438 * Samplers
3439 */
3440
3441 /**
3442 * Build the sampler view descriptor for a buffer texture.
3443 * @param state 256-bit descriptor; only the high 128 bits are filled in
3444 */
3445 void
3446 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3447 enum pipe_format format,
3448 unsigned offset, unsigned size,
3449 uint32_t *state)
3450 {
3451 const struct util_format_description *desc;
3452 int first_non_void;
3453 unsigned stride;
3454 unsigned num_records;
3455 unsigned num_format, data_format;
3456
3457 desc = util_format_description(format);
3458 first_non_void = util_format_get_first_non_void_channel(format);
3459 stride = desc->block.bits / 8;
3460 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3461 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3462
3463 num_records = size / stride;
3464 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3465
3466 /* The NUM_RECORDS field has a different meaning depending on the chip,
3467 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3468 *
3469 * SI-CIK:
3470 * - If STRIDE == 0, it's in byte units.
3471 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3472 *
3473 * VI:
3474 * - For SMEM and STRIDE == 0, it's in byte units.
3475 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3476 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3477 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3478 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3479 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3480 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3481 * That way the same descriptor can be used by both SMEM and VMEM.
3482 *
3483 * GFX9:
3484 * - For SMEM and STRIDE == 0, it's in byte units.
3485 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3486 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3487 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3488 */
3489 if (screen->info.chip_class >= GFX9)
3490 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3491 * from STRIDE to bytes. This works around it by setting
3492 * NUM_RECORDS to at least the size of one element, so that
3493 * the first element is readable when IDXEN == 0.
3494 *
3495 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3496 * IDXEN is enforced?
3497 */
3498 num_records = num_records ? MAX2(num_records, stride) : 0;
3499 else if (screen->info.chip_class == VI)
3500 num_records *= stride;
3501
3502 state[4] = 0;
3503 state[5] = S_008F04_STRIDE(stride);
3504 state[6] = num_records;
3505 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3506 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3507 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3508 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3509 S_008F0C_NUM_FORMAT(num_format) |
3510 S_008F0C_DATA_FORMAT(data_format);
3511 }
3512
3513 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3514 {
3515 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3516
3517 if (swizzle[3] == PIPE_SWIZZLE_X) {
3518 /* For the pre-defined border color values (white, opaque
3519 * black, transparent black), the only thing that matters is
3520 * that the alpha channel winds up in the correct place
3521 * (because the RGB channels are all the same) so either of
3522 * these enumerations will work.
3523 */
3524 if (swizzle[2] == PIPE_SWIZZLE_Y)
3525 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3526 else
3527 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3528 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3529 if (swizzle[1] == PIPE_SWIZZLE_Y)
3530 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3531 else
3532 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3533 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3534 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3535 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3536 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3537 }
3538
3539 return bc_swizzle;
3540 }
3541
3542 /**
3543 * Build the sampler view descriptor for a texture.
3544 */
3545 void
3546 si_make_texture_descriptor(struct si_screen *screen,
3547 struct r600_texture *tex,
3548 bool sampler,
3549 enum pipe_texture_target target,
3550 enum pipe_format pipe_format,
3551 const unsigned char state_swizzle[4],
3552 unsigned first_level, unsigned last_level,
3553 unsigned first_layer, unsigned last_layer,
3554 unsigned width, unsigned height, unsigned depth,
3555 uint32_t *state,
3556 uint32_t *fmask_state)
3557 {
3558 struct pipe_resource *res = &tex->resource.b.b;
3559 const struct util_format_description *desc;
3560 unsigned char swizzle[4];
3561 int first_non_void;
3562 unsigned num_format, data_format, type;
3563 uint64_t va;
3564
3565 desc = util_format_description(pipe_format);
3566
3567 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3568 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3569 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3570 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3571
3572 switch (pipe_format) {
3573 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3574 case PIPE_FORMAT_X32_S8X24_UINT:
3575 case PIPE_FORMAT_X8Z24_UNORM:
3576 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3577 break;
3578 case PIPE_FORMAT_X24S8_UINT:
3579 /*
3580 * X24S8 is implemented as an 8_8_8_8 data format, to
3581 * fix texture gathers. This affects at least
3582 * GL45-CTS.texture_cube_map_array.sampling on VI.
3583 */
3584 if (screen->info.chip_class <= VI)
3585 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3586 else
3587 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3588 break;
3589 default:
3590 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3591 }
3592 } else {
3593 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3594 }
3595
3596 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3597
3598 switch (pipe_format) {
3599 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3600 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3601 break;
3602 default:
3603 if (first_non_void < 0) {
3604 if (util_format_is_compressed(pipe_format)) {
3605 switch (pipe_format) {
3606 case PIPE_FORMAT_DXT1_SRGB:
3607 case PIPE_FORMAT_DXT1_SRGBA:
3608 case PIPE_FORMAT_DXT3_SRGBA:
3609 case PIPE_FORMAT_DXT5_SRGBA:
3610 case PIPE_FORMAT_BPTC_SRGBA:
3611 case PIPE_FORMAT_ETC2_SRGB8:
3612 case PIPE_FORMAT_ETC2_SRGB8A1:
3613 case PIPE_FORMAT_ETC2_SRGBA8:
3614 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3615 break;
3616 case PIPE_FORMAT_RGTC1_SNORM:
3617 case PIPE_FORMAT_LATC1_SNORM:
3618 case PIPE_FORMAT_RGTC2_SNORM:
3619 case PIPE_FORMAT_LATC2_SNORM:
3620 case PIPE_FORMAT_ETC2_R11_SNORM:
3621 case PIPE_FORMAT_ETC2_RG11_SNORM:
3622 /* implies float, so use SNORM/UNORM to determine
3623 whether data is signed or not */
3624 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3625 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3626 break;
3627 default:
3628 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3629 break;
3630 }
3631 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3632 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3633 } else {
3634 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3635 }
3636 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3637 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3638 } else {
3639 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3640
3641 switch (desc->channel[first_non_void].type) {
3642 case UTIL_FORMAT_TYPE_FLOAT:
3643 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3644 break;
3645 case UTIL_FORMAT_TYPE_SIGNED:
3646 if (desc->channel[first_non_void].normalized)
3647 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3648 else if (desc->channel[first_non_void].pure_integer)
3649 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3650 else
3651 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3652 break;
3653 case UTIL_FORMAT_TYPE_UNSIGNED:
3654 if (desc->channel[first_non_void].normalized)
3655 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3656 else if (desc->channel[first_non_void].pure_integer)
3657 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3658 else
3659 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3660 }
3661 }
3662 }
3663
3664 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3665 if (data_format == ~0) {
3666 data_format = 0;
3667 }
3668
3669 /* S8 with Z32 HTILE needs a special format. */
3670 if (screen->info.chip_class >= GFX9 &&
3671 pipe_format == PIPE_FORMAT_S8_UINT &&
3672 tex->tc_compatible_htile)
3673 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3674
3675 if (!sampler &&
3676 (res->target == PIPE_TEXTURE_CUBE ||
3677 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3678 (screen->info.chip_class <= VI &&
3679 res->target == PIPE_TEXTURE_3D))) {
3680 /* For the purpose of shader images, treat cube maps and 3D
3681 * textures as 2D arrays. For 3D textures, the address
3682 * calculations for mipmaps are different, so we rely on the
3683 * caller to effectively disable mipmaps.
3684 */
3685 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3686
3687 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3688 } else {
3689 type = si_tex_dim(screen, tex, target, res->nr_samples);
3690 }
3691
3692 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3693 height = 1;
3694 depth = res->array_size;
3695 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3696 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3697 if (sampler || res->target != PIPE_TEXTURE_3D)
3698 depth = res->array_size;
3699 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3700 depth = res->array_size / 6;
3701
3702 state[0] = 0;
3703 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3704 S_008F14_NUM_FORMAT_GFX6(num_format));
3705 state[2] = (S_008F18_WIDTH(width - 1) |
3706 S_008F18_HEIGHT(height - 1) |
3707 S_008F18_PERF_MOD(4));
3708 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3709 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3710 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3711 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3712 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3713 0 : first_level) |
3714 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3715 util_logbase2(res->nr_samples) :
3716 last_level) |
3717 S_008F1C_TYPE(type));
3718 state[4] = 0;
3719 state[5] = S_008F24_BASE_ARRAY(first_layer);
3720 state[6] = 0;
3721 state[7] = 0;
3722
3723 if (screen->info.chip_class >= GFX9) {
3724 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3725
3726 /* Depth is the the last accessible layer on Gfx9.
3727 * The hw doesn't need to know the total number of layers.
3728 */
3729 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3730 state[4] |= S_008F20_DEPTH(depth - 1);
3731 else
3732 state[4] |= S_008F20_DEPTH(last_layer);
3733
3734 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3735 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3736 util_logbase2(res->nr_samples) :
3737 tex->resource.b.b.last_level);
3738 } else {
3739 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3740 state[4] |= S_008F20_DEPTH(depth - 1);
3741 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3742 }
3743
3744 if (tex->dcc_offset) {
3745 unsigned swap = si_translate_colorswap(pipe_format, false);
3746
3747 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3748 } else {
3749 /* The last dword is unused by hw. The shader uses it to clear
3750 * bits in the first dword of sampler state.
3751 */
3752 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3753 if (first_level == last_level)
3754 state[7] = C_008F30_MAX_ANISO_RATIO;
3755 else
3756 state[7] = 0xffffffff;
3757 }
3758 }
3759
3760 /* Initialize the sampler view for FMASK. */
3761 if (tex->fmask.size) {
3762 uint32_t data_format, num_format;
3763
3764 va = tex->resource.gpu_address + tex->fmask.offset;
3765
3766 if (screen->info.chip_class >= GFX9) {
3767 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3768 switch (res->nr_samples) {
3769 case 2:
3770 num_format = V_008F14_IMG_FMASK_8_2_2;
3771 break;
3772 case 4:
3773 num_format = V_008F14_IMG_FMASK_8_4_4;
3774 break;
3775 case 8:
3776 num_format = V_008F14_IMG_FMASK_32_8_8;
3777 break;
3778 default:
3779 unreachable("invalid nr_samples");
3780 }
3781 } else {
3782 switch (res->nr_samples) {
3783 case 2:
3784 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3785 break;
3786 case 4:
3787 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3788 break;
3789 case 8:
3790 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3791 break;
3792 default:
3793 unreachable("invalid nr_samples");
3794 }
3795 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3796 }
3797
3798 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3799 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3800 S_008F14_DATA_FORMAT_GFX6(data_format) |
3801 S_008F14_NUM_FORMAT_GFX6(num_format);
3802 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3803 S_008F18_HEIGHT(height - 1);
3804 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3805 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3806 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3807 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3808 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3809 fmask_state[4] = 0;
3810 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3811 fmask_state[6] = 0;
3812 fmask_state[7] = 0;
3813
3814 if (screen->info.chip_class >= GFX9) {
3815 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3816 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3817 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3818 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3819 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3820 } else {
3821 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3822 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3823 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3824 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3825 }
3826 }
3827 }
3828
3829 /**
3830 * Create a sampler view.
3831 *
3832 * @param ctx context
3833 * @param texture texture
3834 * @param state sampler view template
3835 * @param width0 width0 override (for compressed textures as int)
3836 * @param height0 height0 override (for compressed textures as int)
3837 * @param force_level set the base address to the level (for compressed textures)
3838 */
3839 struct pipe_sampler_view *
3840 si_create_sampler_view_custom(struct pipe_context *ctx,
3841 struct pipe_resource *texture,
3842 const struct pipe_sampler_view *state,
3843 unsigned width0, unsigned height0,
3844 unsigned force_level)
3845 {
3846 struct si_context *sctx = (struct si_context*)ctx;
3847 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3848 struct r600_texture *tmp = (struct r600_texture*)texture;
3849 unsigned base_level, first_level, last_level;
3850 unsigned char state_swizzle[4];
3851 unsigned height, depth, width;
3852 unsigned last_layer = state->u.tex.last_layer;
3853 enum pipe_format pipe_format;
3854 const struct legacy_surf_level *surflevel;
3855
3856 if (!view)
3857 return NULL;
3858
3859 /* initialize base object */
3860 view->base = *state;
3861 view->base.texture = NULL;
3862 view->base.reference.count = 1;
3863 view->base.context = ctx;
3864
3865 assert(texture);
3866 pipe_resource_reference(&view->base.texture, texture);
3867
3868 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3869 state->format == PIPE_FORMAT_S8X24_UINT ||
3870 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3871 state->format == PIPE_FORMAT_S8_UINT)
3872 view->is_stencil_sampler = true;
3873
3874 /* Buffer resource. */
3875 if (texture->target == PIPE_BUFFER) {
3876 si_make_buffer_descriptor(sctx->screen,
3877 (struct r600_resource *)texture,
3878 state->format,
3879 state->u.buf.offset,
3880 state->u.buf.size,
3881 view->state);
3882 return &view->base;
3883 }
3884
3885 state_swizzle[0] = state->swizzle_r;
3886 state_swizzle[1] = state->swizzle_g;
3887 state_swizzle[2] = state->swizzle_b;
3888 state_swizzle[3] = state->swizzle_a;
3889
3890 base_level = 0;
3891 first_level = state->u.tex.first_level;
3892 last_level = state->u.tex.last_level;
3893 width = width0;
3894 height = height0;
3895 depth = texture->depth0;
3896
3897 if (sctx->chip_class <= VI && force_level) {
3898 assert(force_level == first_level &&
3899 force_level == last_level);
3900 base_level = force_level;
3901 first_level = 0;
3902 last_level = 0;
3903 width = u_minify(width, force_level);
3904 height = u_minify(height, force_level);
3905 depth = u_minify(depth, force_level);
3906 }
3907
3908 /* This is not needed if state trackers set last_layer correctly. */
3909 if (state->target == PIPE_TEXTURE_1D ||
3910 state->target == PIPE_TEXTURE_2D ||
3911 state->target == PIPE_TEXTURE_RECT ||
3912 state->target == PIPE_TEXTURE_CUBE)
3913 last_layer = state->u.tex.first_layer;
3914
3915 /* Texturing with separate depth and stencil. */
3916 pipe_format = state->format;
3917
3918 /* Depth/stencil texturing sometimes needs separate texture. */
3919 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
3920 if (!tmp->flushed_depth_texture &&
3921 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3922 pipe_resource_reference(&view->base.texture, NULL);
3923 FREE(view);
3924 return NULL;
3925 }
3926
3927 assert(tmp->flushed_depth_texture);
3928
3929 /* Override format for the case where the flushed texture
3930 * contains only Z or only S.
3931 */
3932 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3933 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3934
3935 tmp = tmp->flushed_depth_texture;
3936 }
3937
3938 surflevel = tmp->surface.u.legacy.level;
3939
3940 if (tmp->db_compatible) {
3941 if (!view->is_stencil_sampler)
3942 pipe_format = tmp->db_render_format;
3943
3944 switch (pipe_format) {
3945 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3946 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3947 break;
3948 case PIPE_FORMAT_X8Z24_UNORM:
3949 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3950 /* Z24 is always stored like this for DB
3951 * compatibility.
3952 */
3953 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3954 break;
3955 case PIPE_FORMAT_X24S8_UINT:
3956 case PIPE_FORMAT_S8X24_UINT:
3957 case PIPE_FORMAT_X32_S8X24_UINT:
3958 pipe_format = PIPE_FORMAT_S8_UINT;
3959 surflevel = tmp->surface.u.legacy.stencil_level;
3960 break;
3961 default:;
3962 }
3963 }
3964
3965 view->dcc_incompatible =
3966 vi_dcc_formats_are_incompatible(texture,
3967 state->u.tex.first_level,
3968 state->format);
3969
3970 si_make_texture_descriptor(sctx->screen, tmp, true,
3971 state->target, pipe_format, state_swizzle,
3972 first_level, last_level,
3973 state->u.tex.first_layer, last_layer,
3974 width, height, depth,
3975 view->state, view->fmask_state);
3976
3977 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3978 view->is_integer =
3979 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3980 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3981 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3982 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3983 view->base_level_info = &surflevel[base_level];
3984 view->base_level = base_level;
3985 view->block_width = util_format_get_blockwidth(pipe_format);
3986 return &view->base;
3987 }
3988
3989 static struct pipe_sampler_view *
3990 si_create_sampler_view(struct pipe_context *ctx,
3991 struct pipe_resource *texture,
3992 const struct pipe_sampler_view *state)
3993 {
3994 return si_create_sampler_view_custom(ctx, texture, state,
3995 texture ? texture->width0 : 0,
3996 texture ? texture->height0 : 0, 0);
3997 }
3998
3999 static void si_sampler_view_destroy(struct pipe_context *ctx,
4000 struct pipe_sampler_view *state)
4001 {
4002 struct si_sampler_view *view = (struct si_sampler_view *)state;
4003
4004 pipe_resource_reference(&state->texture, NULL);
4005 FREE(view);
4006 }
4007
4008 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4009 {
4010 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4011 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4012 (linear_filter &&
4013 (wrap == PIPE_TEX_WRAP_CLAMP ||
4014 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4015 }
4016
4017 static uint32_t si_translate_border_color(struct si_context *sctx,
4018 const struct pipe_sampler_state *state,
4019 const union pipe_color_union *color,
4020 bool is_integer)
4021 {
4022 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4023 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4024
4025 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4026 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4027 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4028 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4029
4030 #define simple_border_types(elt) \
4031 do { \
4032 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4033 color->elt[2] == 0 && color->elt[3] == 0) \
4034 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4035 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4036 color->elt[2] == 0 && color->elt[3] == 1) \
4037 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4038 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4039 color->elt[2] == 1 && color->elt[3] == 1) \
4040 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4041 } while (false)
4042
4043 if (is_integer)
4044 simple_border_types(ui);
4045 else
4046 simple_border_types(f);
4047
4048 #undef simple_border_types
4049
4050 int i;
4051
4052 /* Check if the border has been uploaded already. */
4053 for (i = 0; i < sctx->border_color_count; i++)
4054 if (memcmp(&sctx->border_color_table[i], color,
4055 sizeof(*color)) == 0)
4056 break;
4057
4058 if (i >= SI_MAX_BORDER_COLORS) {
4059 /* Getting 4096 unique border colors is very unlikely. */
4060 fprintf(stderr, "radeonsi: The border color table is full. "
4061 "Any new border colors will be just black. "
4062 "Please file a bug.\n");
4063 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4064 }
4065
4066 if (i == sctx->border_color_count) {
4067 /* Upload a new border color. */
4068 memcpy(&sctx->border_color_table[i], color,
4069 sizeof(*color));
4070 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4071 color, sizeof(*color));
4072 sctx->border_color_count++;
4073 }
4074
4075 return S_008F3C_BORDER_COLOR_PTR(i) |
4076 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4077 }
4078
4079 static inline int S_FIXED(float value, unsigned frac_bits)
4080 {
4081 return value * (1 << frac_bits);
4082 }
4083
4084 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4085 {
4086 if (filter == PIPE_TEX_FILTER_LINEAR)
4087 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4088 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4089 else
4090 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4091 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4092 }
4093
4094 static inline unsigned si_tex_aniso_filter(unsigned filter)
4095 {
4096 if (filter < 2)
4097 return 0;
4098 if (filter < 4)
4099 return 1;
4100 if (filter < 8)
4101 return 2;
4102 if (filter < 16)
4103 return 3;
4104 return 4;
4105 }
4106
4107 static void *si_create_sampler_state(struct pipe_context *ctx,
4108 const struct pipe_sampler_state *state)
4109 {
4110 struct si_context *sctx = (struct si_context *)ctx;
4111 struct si_screen *sscreen = sctx->screen;
4112 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4113 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4114 : state->max_anisotropy;
4115 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4116 union pipe_color_union clamped_border_color;
4117
4118 if (!rstate) {
4119 return NULL;
4120 }
4121
4122 #ifdef DEBUG
4123 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4124 #endif
4125 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4126 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4127 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4128 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4129 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4130 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4131 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4132 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4133 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4134 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4135 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4136 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4137 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4138 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4139 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4140 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4141 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4142 S_008F38_MIP_POINT_PRECLAMP(0) |
4143 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4144 S_008F38_FILTER_PREC_FIX(1) |
4145 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4146 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4147
4148 /* Create sampler resource for integer textures. */
4149 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4150 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4151
4152 /* Create sampler resource for upgraded depth textures. */
4153 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4154
4155 for (unsigned i = 0; i < 4; ++i) {
4156 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4157 * when the border color is 1.0. */
4158 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4159 }
4160
4161 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4162 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4163 else
4164 rstate->upgraded_depth_val[3] =
4165 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4166 S_008F3C_UPGRADED_DEPTH(1);
4167
4168 return rstate;
4169 }
4170
4171 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4172 {
4173 struct si_context *sctx = (struct si_context *)ctx;
4174
4175 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4176 return;
4177
4178 sctx->sample_mask.sample_mask = sample_mask;
4179 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4180 }
4181
4182 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4183 {
4184 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4185 unsigned mask = sctx->sample_mask.sample_mask;
4186
4187 /* Needed for line and polygon smoothing as well as for the Polaris
4188 * small primitive filter. We expect the state tracker to take care of
4189 * this for us.
4190 */
4191 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4192 (mask & 1 && sctx->blitter->running));
4193
4194 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4195 radeon_emit(cs, mask | (mask << 16));
4196 radeon_emit(cs, mask | (mask << 16));
4197 }
4198
4199 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4200 {
4201 #ifdef DEBUG
4202 struct si_sampler_state *s = state;
4203
4204 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4205 s->magic = 0;
4206 #endif
4207 free(state);
4208 }
4209
4210 /*
4211 * Vertex elements & buffers
4212 */
4213
4214 static void *si_create_vertex_elements(struct pipe_context *ctx,
4215 unsigned count,
4216 const struct pipe_vertex_element *elements)
4217 {
4218 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4219 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4220 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4221 int i;
4222
4223 assert(count <= SI_MAX_ATTRIBS);
4224 if (!v)
4225 return NULL;
4226
4227 v->count = count;
4228 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4229
4230 for (i = 0; i < count; ++i) {
4231 const struct util_format_description *desc;
4232 const struct util_format_channel_description *channel;
4233 unsigned data_format, num_format;
4234 int first_non_void;
4235 unsigned vbo_index = elements[i].vertex_buffer_index;
4236 unsigned char swizzle[4];
4237
4238 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4239 FREE(v);
4240 return NULL;
4241 }
4242
4243 if (elements[i].instance_divisor) {
4244 v->uses_instance_divisors = true;
4245 v->instance_divisors[i] = elements[i].instance_divisor;
4246
4247 if (v->instance_divisors[i] == 1)
4248 v->instance_divisor_is_one |= 1u << i;
4249 else
4250 v->instance_divisor_is_fetched |= 1u << i;
4251 }
4252
4253 if (!used[vbo_index]) {
4254 v->first_vb_use_mask |= 1 << i;
4255 used[vbo_index] = true;
4256 }
4257
4258 desc = util_format_description(elements[i].src_format);
4259 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4260 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4261 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4262 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4263 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4264
4265 v->format_size[i] = desc->block.bits / 8;
4266 v->src_offset[i] = elements[i].src_offset;
4267 v->vertex_buffer_index[i] = vbo_index;
4268
4269 /* The hardware always treats the 2-bit alpha channel as
4270 * unsigned, so a shader workaround is needed. The affected
4271 * chips are VI and older except Stoney (GFX8.1).
4272 */
4273 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4274 sscreen->info.chip_class <= VI &&
4275 sscreen->info.family != CHIP_STONEY) {
4276 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4277 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4278 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4279 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4280 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4281 /* This isn't actually used in OpenGL. */
4282 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4283 }
4284 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4285 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4286 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4287 else
4288 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4289 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4290 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4291 if (channel->normalized) {
4292 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4293 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4294 else
4295 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4296 } else {
4297 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4298 }
4299 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4300 if (channel->normalized) {
4301 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4302 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4303 else
4304 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4305 } else {
4306 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4307 }
4308 }
4309 } else if (channel && channel->size == 64 &&
4310 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4311 switch (desc->nr_channels) {
4312 case 1:
4313 case 2:
4314 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4315 swizzle[0] = PIPE_SWIZZLE_X;
4316 swizzle[1] = PIPE_SWIZZLE_Y;
4317 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4318 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4319 break;
4320 case 3:
4321 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4322 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4323 swizzle[1] = PIPE_SWIZZLE_Y;
4324 swizzle[2] = PIPE_SWIZZLE_0;
4325 swizzle[3] = PIPE_SWIZZLE_0;
4326 break;
4327 case 4:
4328 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4329 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4330 swizzle[1] = PIPE_SWIZZLE_Y;
4331 swizzle[2] = PIPE_SWIZZLE_Z;
4332 swizzle[3] = PIPE_SWIZZLE_W;
4333 break;
4334 default:
4335 assert(0);
4336 }
4337 } else if (channel && desc->nr_channels == 3) {
4338 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4339
4340 if (channel->size == 8) {
4341 if (channel->pure_integer)
4342 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4343 else
4344 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4345 } else if (channel->size == 16) {
4346 if (channel->pure_integer)
4347 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4348 else
4349 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4350 }
4351 }
4352
4353 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4354 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4355 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4356 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4357 S_008F0C_NUM_FORMAT(num_format) |
4358 S_008F0C_DATA_FORMAT(data_format);
4359 }
4360 return v;
4361 }
4362
4363 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4364 {
4365 struct si_context *sctx = (struct si_context *)ctx;
4366 struct si_vertex_elements *old = sctx->vertex_elements;
4367 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4368
4369 sctx->vertex_elements = v;
4370 sctx->vertex_buffers_dirty = true;
4371
4372 if (v &&
4373 (!old ||
4374 old->count != v->count ||
4375 old->uses_instance_divisors != v->uses_instance_divisors ||
4376 v->uses_instance_divisors || /* we don't check which divisors changed */
4377 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4378 sctx->do_update_shaders = true;
4379
4380 if (v && v->instance_divisor_is_fetched) {
4381 struct pipe_constant_buffer cb;
4382
4383 cb.buffer = NULL;
4384 cb.user_buffer = v->instance_divisors;
4385 cb.buffer_offset = 0;
4386 cb.buffer_size = sizeof(uint32_t) * v->count;
4387 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4388 }
4389 }
4390
4391 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4392 {
4393 struct si_context *sctx = (struct si_context *)ctx;
4394
4395 if (sctx->vertex_elements == state)
4396 sctx->vertex_elements = NULL;
4397 FREE(state);
4398 }
4399
4400 static void si_set_vertex_buffers(struct pipe_context *ctx,
4401 unsigned start_slot, unsigned count,
4402 const struct pipe_vertex_buffer *buffers)
4403 {
4404 struct si_context *sctx = (struct si_context *)ctx;
4405 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4406 int i;
4407
4408 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4409
4410 if (buffers) {
4411 for (i = 0; i < count; i++) {
4412 const struct pipe_vertex_buffer *src = buffers + i;
4413 struct pipe_vertex_buffer *dsti = dst + i;
4414 struct pipe_resource *buf = src->buffer.resource;
4415
4416 pipe_resource_reference(&dsti->buffer.resource, buf);
4417 dsti->buffer_offset = src->buffer_offset;
4418 dsti->stride = src->stride;
4419 si_context_add_resource_size(sctx, buf);
4420 if (buf)
4421 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4422 }
4423 } else {
4424 for (i = 0; i < count; i++) {
4425 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4426 }
4427 }
4428 sctx->vertex_buffers_dirty = true;
4429 }
4430
4431 /*
4432 * Misc
4433 */
4434
4435 static void si_set_tess_state(struct pipe_context *ctx,
4436 const float default_outer_level[4],
4437 const float default_inner_level[2])
4438 {
4439 struct si_context *sctx = (struct si_context *)ctx;
4440 struct pipe_constant_buffer cb;
4441 float array[8];
4442
4443 memcpy(array, default_outer_level, sizeof(float) * 4);
4444 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4445
4446 cb.buffer = NULL;
4447 cb.user_buffer = NULL;
4448 cb.buffer_size = sizeof(array);
4449
4450 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4451 (void*)array, sizeof(array),
4452 &cb.buffer_offset);
4453
4454 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4455 pipe_resource_reference(&cb.buffer, NULL);
4456 }
4457
4458 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4459 {
4460 struct si_context *sctx = (struct si_context *)ctx;
4461
4462 si_update_fb_dirtiness_after_rendering(sctx);
4463
4464 /* Multisample surfaces are flushed in si_decompress_textures. */
4465 if (sctx->framebuffer.uncompressed_cb_mask)
4466 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4467 sctx->framebuffer.CB_has_shader_readable_metadata);
4468 }
4469
4470 /* This only ensures coherency for shader image/buffer stores. */
4471 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4472 {
4473 struct si_context *sctx = (struct si_context *)ctx;
4474
4475 /* Subsequent commands must wait for all shader invocations to
4476 * complete. */
4477 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4478 SI_CONTEXT_CS_PARTIAL_FLUSH;
4479
4480 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4481 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4482 SI_CONTEXT_INV_VMEM_L1;
4483
4484 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4485 PIPE_BARRIER_SHADER_BUFFER |
4486 PIPE_BARRIER_TEXTURE |
4487 PIPE_BARRIER_IMAGE |
4488 PIPE_BARRIER_STREAMOUT_BUFFER |
4489 PIPE_BARRIER_GLOBAL_BUFFER)) {
4490 /* As far as I can tell, L1 contents are written back to L2
4491 * automatically at end of shader, but the contents of other
4492 * L1 caches might still be stale. */
4493 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4494 }
4495
4496 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4497 /* Indices are read through TC L2 since VI.
4498 * L1 isn't used.
4499 */
4500 if (sctx->screen->info.chip_class <= CIK)
4501 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4502 }
4503
4504 /* MSAA color, any depth and any stencil are flushed in
4505 * si_decompress_textures when needed.
4506 */
4507 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4508 sctx->framebuffer.uncompressed_cb_mask) {
4509 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4510
4511 if (sctx->chip_class <= VI)
4512 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4513 }
4514
4515 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4516 if (sctx->screen->info.chip_class <= VI &&
4517 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4518 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4519 }
4520
4521 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4522 {
4523 struct pipe_blend_state blend;
4524
4525 memset(&blend, 0, sizeof(blend));
4526 blend.independent_blend_enable = true;
4527 blend.rt[0].colormask = 0xf;
4528 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4529 }
4530
4531 static void si_init_config(struct si_context *sctx);
4532
4533 void si_init_state_functions(struct si_context *sctx)
4534 {
4535 si_init_external_atom(sctx, &sctx->render_cond_atom, &sctx->atoms.s.render_cond);
4536 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4537 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4538 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4539 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4540
4541 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4542 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4543 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4544 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4545 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4546 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4547 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4548 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4549 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4550 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4551 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4552
4553 sctx->b.create_blend_state = si_create_blend_state;
4554 sctx->b.bind_blend_state = si_bind_blend_state;
4555 sctx->b.delete_blend_state = si_delete_blend_state;
4556 sctx->b.set_blend_color = si_set_blend_color;
4557
4558 sctx->b.create_rasterizer_state = si_create_rs_state;
4559 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4560 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4561
4562 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4563 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4564 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4565
4566 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4567 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4568 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4569 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4570 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4571
4572 sctx->b.set_clip_state = si_set_clip_state;
4573 sctx->b.set_stencil_ref = si_set_stencil_ref;
4574
4575 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4576
4577 sctx->b.create_sampler_state = si_create_sampler_state;
4578 sctx->b.delete_sampler_state = si_delete_sampler_state;
4579
4580 sctx->b.create_sampler_view = si_create_sampler_view;
4581 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4582
4583 sctx->b.set_sample_mask = si_set_sample_mask;
4584
4585 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4586 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4587 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4588 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4589
4590 sctx->b.texture_barrier = si_texture_barrier;
4591 sctx->b.memory_barrier = si_memory_barrier;
4592 sctx->b.set_min_samples = si_set_min_samples;
4593 sctx->b.set_tess_state = si_set_tess_state;
4594
4595 sctx->b.set_active_query_state = si_set_active_query_state;
4596
4597 sctx->b.draw_vbo = si_draw_vbo;
4598
4599 si_init_config(sctx);
4600 }
4601
4602 void si_init_screen_state_functions(struct si_screen *sscreen)
4603 {
4604 sscreen->b.is_format_supported = si_is_format_supported;
4605 }
4606
4607 static void si_set_grbm_gfx_index(struct si_context *sctx,
4608 struct si_pm4_state *pm4, unsigned value)
4609 {
4610 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4611 R_00802C_GRBM_GFX_INDEX;
4612 si_pm4_set_reg(pm4, reg, value);
4613 }
4614
4615 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4616 struct si_pm4_state *pm4, unsigned se)
4617 {
4618 assert(se == ~0 || se < sctx->screen->info.max_se);
4619 si_set_grbm_gfx_index(sctx, pm4,
4620 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4621 S_030800_SE_INDEX(se)) |
4622 S_030800_SH_BROADCAST_WRITES(1) |
4623 S_030800_INSTANCE_BROADCAST_WRITES(1));
4624 }
4625
4626 static void
4627 si_write_harvested_raster_configs(struct si_context *sctx,
4628 struct si_pm4_state *pm4,
4629 unsigned raster_config,
4630 unsigned raster_config_1)
4631 {
4632 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4633 unsigned raster_config_se[4];
4634 unsigned se;
4635
4636 ac_get_harvested_configs(&sctx->screen->info,
4637 raster_config,
4638 &raster_config_1,
4639 raster_config_se);
4640
4641 for (se = 0; se < num_se; se++) {
4642 si_set_grbm_gfx_index_se(sctx, pm4, se);
4643 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4644 }
4645 si_set_grbm_gfx_index(sctx, pm4, ~0);
4646
4647 if (sctx->chip_class >= CIK) {
4648 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4649 }
4650 }
4651
4652 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4653 {
4654 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4655 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4656 unsigned raster_config, raster_config_1;
4657
4658 ac_get_raster_config(&sctx->screen->info,
4659 &raster_config,
4660 &raster_config_1);
4661
4662 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4663 /* Always use the default config when all backends are enabled
4664 * (or when we failed to determine the enabled backends).
4665 */
4666 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4667 raster_config);
4668 if (sctx->chip_class >= CIK)
4669 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4670 raster_config_1);
4671 } else {
4672 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4673 }
4674 }
4675
4676 static void si_init_config(struct si_context *sctx)
4677 {
4678 struct si_screen *sscreen = sctx->screen;
4679 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4680 bool has_clear_state = sscreen->has_clear_state;
4681 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4682
4683 /* Only SI can disable CLEAR_STATE for now. */
4684 assert(has_clear_state || sscreen->info.chip_class == SI);
4685
4686 if (!pm4)
4687 return;
4688
4689 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4690 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4691 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4692 si_pm4_cmd_end(pm4, false);
4693
4694 if (has_clear_state) {
4695 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4696 si_pm4_cmd_add(pm4, 0);
4697 si_pm4_cmd_end(pm4, false);
4698 }
4699
4700 if (sctx->chip_class <= VI)
4701 si_set_raster_config(sctx, pm4);
4702
4703 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4704 if (!has_clear_state)
4705 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4706
4707 /* FIXME calculate these values somehow ??? */
4708 if (sctx->chip_class <= VI) {
4709 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4710 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4711 }
4712
4713 if (!has_clear_state) {
4714 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4715 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4716 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4717 }
4718
4719 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4720 if (!has_clear_state)
4721 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4722 if (sctx->chip_class < CIK)
4723 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4724 S_008A14_CLIP_VTX_REORDER_ENA(1));
4725
4726 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4727 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4728
4729 if (!has_clear_state)
4730 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4731
4732 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4733 * I don't know why. Deduced by trial and error.
4734 */
4735 if (sctx->chip_class <= CIK) {
4736 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4737 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4738 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4739 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4740 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4741 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4742 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4743 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4744 }
4745
4746 if (!has_clear_state) {
4747 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4748 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4749 S_028230_ER_TRI(0xA) |
4750 S_028230_ER_POINT(0xA) |
4751 S_028230_ER_RECT(0xA) |
4752 /* Required by DX10_DIAMOND_TEST_ENA: */
4753 S_028230_ER_LINE_LR(0x1A) |
4754 S_028230_ER_LINE_RL(0x26) |
4755 S_028230_ER_LINE_TB(0xA) |
4756 S_028230_ER_LINE_BT(0xA));
4757 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4758 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4759 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4760 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4761 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4762 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4763 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4764 }
4765
4766 if (sctx->chip_class >= GFX9) {
4767 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4768 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4769 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4770 } else {
4771 /* These registers, when written, also overwrite the CLEAR_STATE
4772 * context, so we can't rely on CLEAR_STATE setting them.
4773 * It would be an issue if there was another UMD changing them.
4774 */
4775 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4776 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4777 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4778 }
4779
4780 if (sctx->chip_class >= CIK) {
4781 if (sctx->chip_class >= GFX9) {
4782 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4783 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4784 } else {
4785 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4786 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4787 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4788 S_00B41C_WAVE_LIMIT(0x3F));
4789 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4790 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4791
4792 /* If this is 0, Bonaire can hang even if GS isn't being used.
4793 * Other chips are unaffected. These are suboptimal values,
4794 * but we don't use on-chip GS.
4795 */
4796 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4797 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4798 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4799 }
4800 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4801 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4802
4803 /* Compute LATE_ALLOC_VS.LIMIT. */
4804 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4805 (sscreen->info.max_se *
4806 sscreen->info.max_sh_per_se);
4807 unsigned late_alloc_limit; /* The limit is per SH. */
4808
4809 if (sctx->family == CHIP_KABINI) {
4810 late_alloc_limit = 0; /* Potential hang on Kabini. */
4811 } else if (num_cu_per_sh <= 4) {
4812 /* Too few available compute units per SH. Disallowing
4813 * VS to run on one CU could hurt us more than late VS
4814 * allocation would help.
4815 *
4816 * 2 is the highest safe number that allows us to keep
4817 * all CUs enabled.
4818 */
4819 late_alloc_limit = 2;
4820 } else {
4821 /* This is a good initial value, allowing 1 late_alloc
4822 * wave per SIMD on num_cu - 2.
4823 */
4824 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4825
4826 /* The limit is 0-based, so 0 means 1. */
4827 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4828 late_alloc_limit -= 1;
4829 }
4830
4831 /* VS can't execute on one CU if the limit is > 2. */
4832 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4833 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4834 S_00B118_WAVE_LIMIT(0x3F));
4835 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4836 S_00B11C_LIMIT(late_alloc_limit));
4837 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4838 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4839 }
4840
4841 if (sctx->chip_class >= VI) {
4842 unsigned vgt_tess_distribution;
4843
4844 vgt_tess_distribution =
4845 S_028B50_ACCUM_ISOLINE(32) |
4846 S_028B50_ACCUM_TRI(11) |
4847 S_028B50_ACCUM_QUAD(11) |
4848 S_028B50_DONUT_SPLIT(16);
4849
4850 /* Testing with Unigine Heaven extreme tesselation yielded best results
4851 * with TRAP_SPLIT = 3.
4852 */
4853 if (sctx->family == CHIP_FIJI ||
4854 sctx->family >= CHIP_POLARIS10)
4855 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4856
4857 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4858 } else if (!has_clear_state) {
4859 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4860 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4861 }
4862
4863 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4864 if (sctx->chip_class >= CIK) {
4865 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4866 S_028084_ADDRESS(border_color_va >> 40));
4867 }
4868 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4869 RADEON_PRIO_BORDER_COLORS);
4870
4871 if (sctx->chip_class >= GFX9) {
4872 unsigned num_se = sscreen->info.max_se;
4873 unsigned pc_lines = 0;
4874
4875 switch (sctx->family) {
4876 case CHIP_VEGA10:
4877 case CHIP_VEGA12:
4878 pc_lines = 4096;
4879 break;
4880 case CHIP_RAVEN:
4881 pc_lines = 1024;
4882 break;
4883 default:
4884 assert(0);
4885 }
4886
4887 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4888 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4889 S_028C48_MAX_PRIM_PER_BATCH(1023));
4890 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4891 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4892 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4893 }
4894
4895 si_pm4_upload_indirect_buffer(sctx, pm4);
4896 sctx->init_config = pm4;
4897 }