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radeonsi: move draw state into new handling
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "si_state.h"
33 #include "sid.h"
34
35 /*
36 * inferred framebuffer and blender state
37 */
38 static void si_update_fb_blend_state(struct r600_context *rctx)
39 {
40 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
41 struct si_state_blend *blend = rctx->queued.named.blend;
42 uint32_t mask;
43
44 if (pm4 == NULL || blend == NULL)
45 return;
46
47 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
48 mask &= blend->cb_target_mask;
49 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
50
51 si_pm4_set_state(rctx, fb_blend, pm4);
52 }
53
54 /*
55 * Blender functions
56 */
57
58 static uint32_t si_translate_blend_function(int blend_func)
59 {
60 switch (blend_func) {
61 case PIPE_BLEND_ADD:
62 return V_028780_COMB_DST_PLUS_SRC;
63 case PIPE_BLEND_SUBTRACT:
64 return V_028780_COMB_SRC_MINUS_DST;
65 case PIPE_BLEND_REVERSE_SUBTRACT:
66 return V_028780_COMB_DST_MINUS_SRC;
67 case PIPE_BLEND_MIN:
68 return V_028780_COMB_MIN_DST_SRC;
69 case PIPE_BLEND_MAX:
70 return V_028780_COMB_MAX_DST_SRC;
71 default:
72 R600_ERR("Unknown blend function %d\n", blend_func);
73 assert(0);
74 break;
75 }
76 return 0;
77 }
78
79 static uint32_t si_translate_blend_factor(int blend_fact)
80 {
81 switch (blend_fact) {
82 case PIPE_BLENDFACTOR_ONE:
83 return V_028780_BLEND_ONE;
84 case PIPE_BLENDFACTOR_SRC_COLOR:
85 return V_028780_BLEND_SRC_COLOR;
86 case PIPE_BLENDFACTOR_SRC_ALPHA:
87 return V_028780_BLEND_SRC_ALPHA;
88 case PIPE_BLENDFACTOR_DST_ALPHA:
89 return V_028780_BLEND_DST_ALPHA;
90 case PIPE_BLENDFACTOR_DST_COLOR:
91 return V_028780_BLEND_DST_COLOR;
92 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
93 return V_028780_BLEND_SRC_ALPHA_SATURATE;
94 case PIPE_BLENDFACTOR_CONST_COLOR:
95 return V_028780_BLEND_CONSTANT_COLOR;
96 case PIPE_BLENDFACTOR_CONST_ALPHA:
97 return V_028780_BLEND_CONSTANT_ALPHA;
98 case PIPE_BLENDFACTOR_ZERO:
99 return V_028780_BLEND_ZERO;
100 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
101 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
102 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
103 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
104 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
105 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
106 case PIPE_BLENDFACTOR_INV_DST_COLOR:
107 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
108 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
109 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
110 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
112 case PIPE_BLENDFACTOR_SRC1_COLOR:
113 return V_028780_BLEND_SRC1_COLOR;
114 case PIPE_BLENDFACTOR_SRC1_ALPHA:
115 return V_028780_BLEND_SRC1_ALPHA;
116 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
117 return V_028780_BLEND_INV_SRC1_COLOR;
118 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
119 return V_028780_BLEND_INV_SRC1_ALPHA;
120 default:
121 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
122 assert(0);
123 break;
124 }
125 return 0;
126 }
127
128 static void *si_create_blend_state(struct pipe_context *ctx,
129 const struct pipe_blend_state *state)
130 {
131 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
132 struct si_pm4_state *pm4 = &blend->pm4;
133
134 uint32_t color_control;
135
136 if (blend == NULL)
137 return NULL;
138
139 color_control = S_028808_MODE(V_028808_CB_NORMAL);
140 if (state->logicop_enable) {
141 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
142 } else {
143 color_control |= S_028808_ROP3(0xcc);
144 }
145 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
146
147 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
148 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
149
150 blend->cb_target_mask = 0;
151 for (int i = 0; i < 8; i++) {
152 /* state->rt entries > 0 only written if independent blending */
153 const int j = state->independent_blend_enable ? i : 0;
154
155 unsigned eqRGB = state->rt[j].rgb_func;
156 unsigned srcRGB = state->rt[j].rgb_src_factor;
157 unsigned dstRGB = state->rt[j].rgb_dst_factor;
158 unsigned eqA = state->rt[j].alpha_func;
159 unsigned srcA = state->rt[j].alpha_src_factor;
160 unsigned dstA = state->rt[j].alpha_dst_factor;
161
162 unsigned blend_cntl = 0;
163
164 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
165 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
166
167 if (!state->rt[j].blend_enable) {
168 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
169 continue;
170 }
171
172 blend_cntl |= S_028780_ENABLE(1);
173 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
174 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
175 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
176
177 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
178 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
179 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
180 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
181 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
182 }
183 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
184 }
185
186 return blend;
187 }
188
189 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
190 {
191 struct r600_context *rctx = (struct r600_context *)ctx;
192 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
193 si_update_fb_blend_state(rctx);
194 }
195
196 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
197 {
198 struct r600_context *rctx = (struct r600_context *)ctx;
199 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
200 }
201
202 static void si_set_blend_color(struct pipe_context *ctx,
203 const struct pipe_blend_color *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
207
208 if (pm4 == NULL)
209 return;
210
211 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
212 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
213 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
214 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
215
216 si_pm4_set_state(rctx, blend_color, pm4);
217 }
218
219 /*
220 * Clipping, scissors and viewport
221 */
222
223 static void si_set_clip_state(struct pipe_context *ctx,
224 const struct pipe_clip_state *state)
225 {
226 struct r600_context *rctx = (struct r600_context *)ctx;
227 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
228
229 if (pm4 == NULL)
230 return;
231
232 for (int i = 0; i < 6; i++) {
233 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
234 fui(state->ucp[i][0]));
235 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
236 fui(state->ucp[i][1]));
237 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
238 fui(state->ucp[i][2]));
239 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
240 fui(state->ucp[i][3]));
241 }
242
243 si_pm4_set_state(rctx, clip, pm4);
244 }
245
246 static void si_set_scissor_state(struct pipe_context *ctx,
247 const struct pipe_scissor_state *state)
248 {
249 struct r600_context *rctx = (struct r600_context *)ctx;
250 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
251 uint32_t tl, br;
252
253 if (pm4 == NULL)
254 return;
255
256 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
257 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
258 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
259 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
260 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
261 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
262 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
263 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
264 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
265 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
266
267 si_pm4_set_state(rctx, scissor, pm4);
268 }
269
270 static void si_set_viewport_state(struct pipe_context *ctx,
271 const struct pipe_viewport_state *state)
272 {
273 struct r600_context *rctx = (struct r600_context *)ctx;
274 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
275 struct si_pm4_state *pm4 = &viewport->pm4;
276
277 if (viewport == NULL)
278 return;
279
280 viewport->viewport = *state;
281 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
282 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
283 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
284 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
285 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
286 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
287 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
288 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
289 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
290 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
291
292 si_pm4_set_state(rctx, viewport, viewport);
293 }
294
295 /*
296 * inferred state between framebuffer and rasterizer
297 */
298 static void si_update_fb_rs_state(struct r600_context *rctx)
299 {
300 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
301 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
302 unsigned offset_db_fmt_cntl = 0, depth;
303 float offset_units;
304
305 if (!rs || !rctx->framebuffer.zsbuf) {
306 FREE(pm4);
307 return;
308 }
309
310 offset_units = rctx->queued.named.rasterizer->offset_units;
311 switch (rctx->framebuffer.zsbuf->texture->format) {
312 case PIPE_FORMAT_Z24X8_UNORM:
313 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
314 depth = -24;
315 offset_units *= 2.0f;
316 break;
317 case PIPE_FORMAT_Z32_FLOAT:
318 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
319 depth = -23;
320 offset_units *= 1.0f;
321 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
322 break;
323 case PIPE_FORMAT_Z16_UNORM:
324 depth = -16;
325 offset_units *= 4.0f;
326 break;
327 default:
328 return;
329 }
330
331 /* FIXME some of those reg can be computed with cso */
332 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
333 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
334 fui(rctx->queued.named.rasterizer->offset_scale));
335 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
336 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
337 fui(rctx->queued.named.rasterizer->offset_scale));
338 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
339 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
340
341 si_pm4_set_state(rctx, fb_rs, pm4);
342 }
343
344 /*
345 * Rasterizer
346 */
347
348 static uint32_t si_translate_fill(uint32_t func)
349 {
350 switch(func) {
351 case PIPE_POLYGON_MODE_FILL:
352 return V_028814_X_DRAW_TRIANGLES;
353 case PIPE_POLYGON_MODE_LINE:
354 return V_028814_X_DRAW_LINES;
355 case PIPE_POLYGON_MODE_POINT:
356 return V_028814_X_DRAW_POINTS;
357 default:
358 assert(0);
359 return V_028814_X_DRAW_POINTS;
360 }
361 }
362
363 static void *si_create_rs_state(struct pipe_context *ctx,
364 const struct pipe_rasterizer_state *state)
365 {
366 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
367 struct si_pm4_state *pm4 = &rs->pm4;
368 unsigned tmp;
369 unsigned prov_vtx = 1, polygon_dual_mode;
370 unsigned clip_rule;
371 float psize_min, psize_max;
372
373 if (rs == NULL) {
374 return NULL;
375 }
376
377 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
378 state->fill_back != PIPE_POLYGON_MODE_FILL);
379
380 if (state->flatshade_first)
381 prov_vtx = 0;
382
383 rs->flatshade = state->flatshade;
384 rs->sprite_coord_enable = state->sprite_coord_enable;
385 rs->pa_sc_line_stipple = state->line_stipple_enable ?
386 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
387 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
388 rs->pa_su_sc_mode_cntl =
389 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
390 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
391 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
392 S_028814_FACE(!state->front_ccw) |
393 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
394 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
395 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
396 S_028814_POLY_MODE(polygon_dual_mode) |
397 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
398 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
399 rs->pa_cl_clip_cntl =
400 S_028810_PS_UCP_MODE(3) |
401 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
402 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
403 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
404 rs->pa_cl_vs_out_cntl =
405 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
406 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
407
408 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
409
410 /* offset */
411 rs->offset_units = state->offset_units;
412 rs->offset_scale = state->offset_scale * 12.0f;
413
414 /* XXX: Flat shading hangs the GPU */
415 tmp = S_0286D4_FLAT_SHADE_ENA(0);
416 if (state->sprite_coord_enable) {
417 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
418 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
419 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
420 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
421 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
422 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
423 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
424 }
425 }
426 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
427
428 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
429 /* point size 12.4 fixed point */
430 tmp = (unsigned)(state->point_size * 8.0);
431 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
432
433 if (state->point_size_per_vertex) {
434 psize_min = util_get_min_point_size(state);
435 psize_max = 8192;
436 } else {
437 /* Force the point size to be as if the vertex output was disabled. */
438 psize_min = state->point_size;
439 psize_max = state->point_size;
440 }
441 /* Divide by two, because 0.5 = 1 pixel. */
442 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
443 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
444 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
445
446 tmp = (unsigned)state->line_width * 8;
447 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
448 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
449 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
450
451 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
452 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
453 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
454 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
455 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
456 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
457 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
458
459 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
460 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
461
462 return rs;
463 }
464
465 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
466 {
467 struct r600_context *rctx = (struct r600_context *)ctx;
468 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
469
470 if (state == NULL)
471 return;
472
473 // TODO
474 rctx->sprite_coord_enable = rs->sprite_coord_enable;
475 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
476 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
477 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
478 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
479
480 si_pm4_bind_state(rctx, rasterizer, rs);
481 si_update_fb_rs_state(rctx);
482 }
483
484 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
485 {
486 struct r600_context *rctx = (struct r600_context *)ctx;
487 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
488 }
489
490 /*
491 * infeered state between dsa and stencil ref
492 */
493 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
494 {
495 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
496 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
497 struct si_state_dsa *dsa = rctx->queued.named.dsa;
498
499 if (pm4 == NULL)
500 return;
501
502 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
503 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
504 S_028430_STENCILMASK(dsa->valuemask[0]) |
505 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
506 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
507 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
508 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
509 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
510
511 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
512 }
513
514 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
515 const struct pipe_stencil_ref *state)
516 {
517 struct r600_context *rctx = (struct r600_context *)ctx;
518 rctx->stencil_ref = *state;
519 si_update_dsa_stencil_ref(rctx);
520 }
521
522
523 /*
524 * DSA
525 */
526
527 /* transnates straight */
528 static uint32_t si_translate_ds_func(int func)
529 {
530 return func;
531 }
532
533 static void *si_create_dsa_state(struct pipe_context *ctx,
534 const struct pipe_depth_stencil_alpha_state *state)
535 {
536 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
537 struct si_pm4_state *pm4 = &dsa->pm4;
538 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
539 unsigned db_render_override, db_render_control;
540
541 if (dsa == NULL) {
542 return NULL;
543 }
544
545 dsa->valuemask[0] = state->stencil[0].valuemask;
546 dsa->valuemask[1] = state->stencil[1].valuemask;
547 dsa->writemask[0] = state->stencil[0].writemask;
548 dsa->writemask[1] = state->stencil[1].writemask;
549
550 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
551 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
552 S_028800_ZFUNC(state->depth.func);
553
554 /* stencil */
555 if (state->stencil[0].enabled) {
556 db_depth_control |= S_028800_STENCIL_ENABLE(1);
557 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
558 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
559 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
560 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
561
562 if (state->stencil[1].enabled) {
563 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
564 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
565 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
566 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
567 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
568 }
569 }
570
571 /* alpha */
572 //alpha_test_control = 0;
573 alpha_ref = 0;
574 if (state->alpha.enabled) {
575 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
576 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
577 alpha_ref = fui(state->alpha.ref_value);
578 }
579 dsa->alpha_ref = alpha_ref;
580
581 /* misc */
582 db_render_control = 0;
583 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
584 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
585 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
586 /* TODO db_render_override depends on query */
587 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
588 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
589 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
590 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
591 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
592 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
593 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
594 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
595 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
596 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
597 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
598 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
599 dsa->db_render_override = db_render_override;
600
601 return dsa;
602 }
603
604 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
605 {
606 struct r600_context *rctx = (struct r600_context *)ctx;
607 struct si_state_dsa *dsa = state;
608
609 if (state == NULL)
610 return;
611
612 si_pm4_bind_state(rctx, dsa, dsa);
613 si_update_dsa_stencil_ref(rctx);
614
615 // TODO
616 rctx->alpha_ref = dsa->alpha_ref;
617 rctx->alpha_ref_dirty = true;
618 }
619
620 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
621 {
622 struct r600_context *rctx = (struct r600_context *)ctx;
623 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
624 }
625
626 static void *si_create_db_flush_dsa(struct r600_context *rctx)
627 {
628 struct pipe_depth_stencil_alpha_state dsa;
629 struct si_state_dsa *state;
630
631 memset(&dsa, 0, sizeof(dsa));
632
633 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
634 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
635 S_028000_DEPTH_COPY(1) |
636 S_028000_STENCIL_COPY(1) |
637 S_028000_COPY_CENTROID(1));
638 return state;
639 }
640
641 /*
642 * format translation
643 */
644 static uint32_t si_translate_colorformat(enum pipe_format format)
645 {
646 switch (format) {
647 /* 8-bit buffers. */
648 case PIPE_FORMAT_A8_UNORM:
649 case PIPE_FORMAT_A8_UINT:
650 case PIPE_FORMAT_A8_SINT:
651 case PIPE_FORMAT_I8_UNORM:
652 case PIPE_FORMAT_I8_UINT:
653 case PIPE_FORMAT_I8_SINT:
654 case PIPE_FORMAT_L8_UNORM:
655 case PIPE_FORMAT_L8_UINT:
656 case PIPE_FORMAT_L8_SINT:
657 case PIPE_FORMAT_L8_SRGB:
658 case PIPE_FORMAT_R8_UNORM:
659 case PIPE_FORMAT_R8_SNORM:
660 case PIPE_FORMAT_R8_UINT:
661 case PIPE_FORMAT_R8_SINT:
662 return V_028C70_COLOR_8;
663
664 /* 16-bit buffers. */
665 case PIPE_FORMAT_B5G6R5_UNORM:
666 return V_028C70_COLOR_5_6_5;
667
668 case PIPE_FORMAT_B5G5R5A1_UNORM:
669 case PIPE_FORMAT_B5G5R5X1_UNORM:
670 return V_028C70_COLOR_1_5_5_5;
671
672 case PIPE_FORMAT_B4G4R4A4_UNORM:
673 case PIPE_FORMAT_B4G4R4X4_UNORM:
674 return V_028C70_COLOR_4_4_4_4;
675
676 case PIPE_FORMAT_L8A8_UNORM:
677 case PIPE_FORMAT_L8A8_UINT:
678 case PIPE_FORMAT_L8A8_SINT:
679 case PIPE_FORMAT_L8A8_SRGB:
680 case PIPE_FORMAT_R8G8_UNORM:
681 case PIPE_FORMAT_R8G8_UINT:
682 case PIPE_FORMAT_R8G8_SINT:
683 return V_028C70_COLOR_8_8;
684
685 case PIPE_FORMAT_Z16_UNORM:
686 case PIPE_FORMAT_R16_UNORM:
687 case PIPE_FORMAT_R16_UINT:
688 case PIPE_FORMAT_R16_SINT:
689 case PIPE_FORMAT_R16_FLOAT:
690 case PIPE_FORMAT_R16G16_FLOAT:
691 return V_028C70_COLOR_16;
692
693 /* 32-bit buffers. */
694 case PIPE_FORMAT_A8B8G8R8_SRGB:
695 case PIPE_FORMAT_A8B8G8R8_UNORM:
696 case PIPE_FORMAT_A8R8G8B8_UNORM:
697 case PIPE_FORMAT_B8G8R8A8_SRGB:
698 case PIPE_FORMAT_B8G8R8A8_UNORM:
699 case PIPE_FORMAT_B8G8R8X8_UNORM:
700 case PIPE_FORMAT_R8G8B8A8_SNORM:
701 case PIPE_FORMAT_R8G8B8A8_UNORM:
702 case PIPE_FORMAT_R8G8B8X8_UNORM:
703 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
704 case PIPE_FORMAT_X8B8G8R8_UNORM:
705 case PIPE_FORMAT_X8R8G8B8_UNORM:
706 case PIPE_FORMAT_R8G8B8_UNORM:
707 case PIPE_FORMAT_R8G8B8A8_SSCALED:
708 case PIPE_FORMAT_R8G8B8A8_USCALED:
709 case PIPE_FORMAT_R8G8B8A8_SINT:
710 case PIPE_FORMAT_R8G8B8A8_UINT:
711 return V_028C70_COLOR_8_8_8_8;
712
713 case PIPE_FORMAT_R10G10B10A2_UNORM:
714 case PIPE_FORMAT_R10G10B10X2_SNORM:
715 case PIPE_FORMAT_B10G10R10A2_UNORM:
716 case PIPE_FORMAT_B10G10R10A2_UINT:
717 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
718 return V_028C70_COLOR_2_10_10_10;
719
720 case PIPE_FORMAT_Z24X8_UNORM:
721 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
722 return V_028C70_COLOR_8_24;
723
724 case PIPE_FORMAT_X8Z24_UNORM:
725 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
726 return V_028C70_COLOR_24_8;
727
728 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
729 return V_028C70_COLOR_X24_8_32_FLOAT;
730
731 case PIPE_FORMAT_R32_FLOAT:
732 case PIPE_FORMAT_Z32_FLOAT:
733 return V_028C70_COLOR_32;
734
735 case PIPE_FORMAT_R16G16_SSCALED:
736 case PIPE_FORMAT_R16G16_UNORM:
737 case PIPE_FORMAT_R16G16_UINT:
738 case PIPE_FORMAT_R16G16_SINT:
739 return V_028C70_COLOR_16_16;
740
741 case PIPE_FORMAT_R11G11B10_FLOAT:
742 return V_028C70_COLOR_10_11_11;
743
744 /* 64-bit buffers. */
745 case PIPE_FORMAT_R16G16B16_USCALED:
746 case PIPE_FORMAT_R16G16B16_SSCALED:
747 case PIPE_FORMAT_R16G16B16A16_UINT:
748 case PIPE_FORMAT_R16G16B16A16_SINT:
749 case PIPE_FORMAT_R16G16B16A16_USCALED:
750 case PIPE_FORMAT_R16G16B16A16_SSCALED:
751 case PIPE_FORMAT_R16G16B16A16_UNORM:
752 case PIPE_FORMAT_R16G16B16A16_SNORM:
753 case PIPE_FORMAT_R16G16B16_FLOAT:
754 case PIPE_FORMAT_R16G16B16A16_FLOAT:
755 return V_028C70_COLOR_16_16_16_16;
756
757 case PIPE_FORMAT_R32G32_FLOAT:
758 case PIPE_FORMAT_R32G32_USCALED:
759 case PIPE_FORMAT_R32G32_SSCALED:
760 case PIPE_FORMAT_R32G32_SINT:
761 case PIPE_FORMAT_R32G32_UINT:
762 return V_028C70_COLOR_32_32;
763
764 /* 128-bit buffers. */
765 case PIPE_FORMAT_R32G32B32A32_SNORM:
766 case PIPE_FORMAT_R32G32B32A32_UNORM:
767 case PIPE_FORMAT_R32G32B32A32_SSCALED:
768 case PIPE_FORMAT_R32G32B32A32_USCALED:
769 case PIPE_FORMAT_R32G32B32A32_SINT:
770 case PIPE_FORMAT_R32G32B32A32_UINT:
771 case PIPE_FORMAT_R32G32B32A32_FLOAT:
772 return V_028C70_COLOR_32_32_32_32;
773
774 /* YUV buffers. */
775 case PIPE_FORMAT_UYVY:
776 case PIPE_FORMAT_YUYV:
777 /* 96-bit buffers. */
778 case PIPE_FORMAT_R32G32B32_FLOAT:
779 /* 8-bit buffers. */
780 case PIPE_FORMAT_L4A4_UNORM:
781 case PIPE_FORMAT_R4A4_UNORM:
782 case PIPE_FORMAT_A4R4_UNORM:
783 default:
784 return ~0U; /* Unsupported. */
785 }
786 }
787
788 static uint32_t si_translate_colorswap(enum pipe_format format)
789 {
790 switch (format) {
791 /* 8-bit buffers. */
792 case PIPE_FORMAT_L4A4_UNORM:
793 case PIPE_FORMAT_A4R4_UNORM:
794 return V_028C70_SWAP_ALT;
795
796 case PIPE_FORMAT_A8_UNORM:
797 case PIPE_FORMAT_A8_UINT:
798 case PIPE_FORMAT_A8_SINT:
799 case PIPE_FORMAT_R4A4_UNORM:
800 return V_028C70_SWAP_ALT_REV;
801 case PIPE_FORMAT_I8_UNORM:
802 case PIPE_FORMAT_L8_UNORM:
803 case PIPE_FORMAT_I8_UINT:
804 case PIPE_FORMAT_I8_SINT:
805 case PIPE_FORMAT_L8_UINT:
806 case PIPE_FORMAT_L8_SINT:
807 case PIPE_FORMAT_L8_SRGB:
808 case PIPE_FORMAT_R8_UNORM:
809 case PIPE_FORMAT_R8_SNORM:
810 case PIPE_FORMAT_R8_UINT:
811 case PIPE_FORMAT_R8_SINT:
812 return V_028C70_SWAP_STD;
813
814 /* 16-bit buffers. */
815 case PIPE_FORMAT_B5G6R5_UNORM:
816 return V_028C70_SWAP_STD_REV;
817
818 case PIPE_FORMAT_B5G5R5A1_UNORM:
819 case PIPE_FORMAT_B5G5R5X1_UNORM:
820 return V_028C70_SWAP_ALT;
821
822 case PIPE_FORMAT_B4G4R4A4_UNORM:
823 case PIPE_FORMAT_B4G4R4X4_UNORM:
824 return V_028C70_SWAP_ALT;
825
826 case PIPE_FORMAT_Z16_UNORM:
827 return V_028C70_SWAP_STD;
828
829 case PIPE_FORMAT_L8A8_UNORM:
830 case PIPE_FORMAT_L8A8_UINT:
831 case PIPE_FORMAT_L8A8_SINT:
832 case PIPE_FORMAT_L8A8_SRGB:
833 return V_028C70_SWAP_ALT;
834 case PIPE_FORMAT_R8G8_UNORM:
835 case PIPE_FORMAT_R8G8_UINT:
836 case PIPE_FORMAT_R8G8_SINT:
837 return V_028C70_SWAP_STD;
838
839 case PIPE_FORMAT_R16_UNORM:
840 case PIPE_FORMAT_R16_UINT:
841 case PIPE_FORMAT_R16_SINT:
842 case PIPE_FORMAT_R16_FLOAT:
843 return V_028C70_SWAP_STD;
844
845 /* 32-bit buffers. */
846 case PIPE_FORMAT_A8B8G8R8_SRGB:
847 return V_028C70_SWAP_STD_REV;
848 case PIPE_FORMAT_B8G8R8A8_SRGB:
849 return V_028C70_SWAP_ALT;
850
851 case PIPE_FORMAT_B8G8R8A8_UNORM:
852 case PIPE_FORMAT_B8G8R8X8_UNORM:
853 return V_028C70_SWAP_ALT;
854
855 case PIPE_FORMAT_A8R8G8B8_UNORM:
856 case PIPE_FORMAT_X8R8G8B8_UNORM:
857 return V_028C70_SWAP_ALT_REV;
858 case PIPE_FORMAT_R8G8B8A8_SNORM:
859 case PIPE_FORMAT_R8G8B8A8_UNORM:
860 case PIPE_FORMAT_R8G8B8A8_SSCALED:
861 case PIPE_FORMAT_R8G8B8A8_USCALED:
862 case PIPE_FORMAT_R8G8B8A8_SINT:
863 case PIPE_FORMAT_R8G8B8A8_UINT:
864 case PIPE_FORMAT_R8G8B8X8_UNORM:
865 return V_028C70_SWAP_STD;
866
867 case PIPE_FORMAT_A8B8G8R8_UNORM:
868 case PIPE_FORMAT_X8B8G8R8_UNORM:
869 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
870 return V_028C70_SWAP_STD_REV;
871
872 case PIPE_FORMAT_Z24X8_UNORM:
873 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
874 return V_028C70_SWAP_STD;
875
876 case PIPE_FORMAT_X8Z24_UNORM:
877 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
878 return V_028C70_SWAP_STD;
879
880 case PIPE_FORMAT_R10G10B10A2_UNORM:
881 case PIPE_FORMAT_R10G10B10X2_SNORM:
882 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
883 return V_028C70_SWAP_STD;
884
885 case PIPE_FORMAT_B10G10R10A2_UNORM:
886 case PIPE_FORMAT_B10G10R10A2_UINT:
887 return V_028C70_SWAP_ALT;
888
889 case PIPE_FORMAT_R11G11B10_FLOAT:
890 case PIPE_FORMAT_R32_FLOAT:
891 case PIPE_FORMAT_R32_UINT:
892 case PIPE_FORMAT_R32_SINT:
893 case PIPE_FORMAT_Z32_FLOAT:
894 case PIPE_FORMAT_R16G16_FLOAT:
895 case PIPE_FORMAT_R16G16_UNORM:
896 case PIPE_FORMAT_R16G16_UINT:
897 case PIPE_FORMAT_R16G16_SINT:
898 return V_028C70_SWAP_STD;
899
900 /* 64-bit buffers. */
901 case PIPE_FORMAT_R32G32_FLOAT:
902 case PIPE_FORMAT_R32G32_UINT:
903 case PIPE_FORMAT_R32G32_SINT:
904 case PIPE_FORMAT_R16G16B16A16_UNORM:
905 case PIPE_FORMAT_R16G16B16A16_SNORM:
906 case PIPE_FORMAT_R16G16B16A16_USCALED:
907 case PIPE_FORMAT_R16G16B16A16_SSCALED:
908 case PIPE_FORMAT_R16G16B16A16_UINT:
909 case PIPE_FORMAT_R16G16B16A16_SINT:
910 case PIPE_FORMAT_R16G16B16A16_FLOAT:
911 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
912
913 /* 128-bit buffers. */
914 case PIPE_FORMAT_R32G32B32A32_FLOAT:
915 case PIPE_FORMAT_R32G32B32A32_SNORM:
916 case PIPE_FORMAT_R32G32B32A32_UNORM:
917 case PIPE_FORMAT_R32G32B32A32_SSCALED:
918 case PIPE_FORMAT_R32G32B32A32_USCALED:
919 case PIPE_FORMAT_R32G32B32A32_SINT:
920 case PIPE_FORMAT_R32G32B32A32_UINT:
921 return V_028C70_SWAP_STD;
922 default:
923 R600_ERR("unsupported colorswap format %d\n", format);
924 return ~0U;
925 }
926 return ~0U;
927 }
928
929 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
930 {
931 if (R600_BIG_ENDIAN) {
932 switch(colorformat) {
933 /* 8-bit buffers. */
934 case V_028C70_COLOR_8:
935 return V_028C70_ENDIAN_NONE;
936
937 /* 16-bit buffers. */
938 case V_028C70_COLOR_5_6_5:
939 case V_028C70_COLOR_1_5_5_5:
940 case V_028C70_COLOR_4_4_4_4:
941 case V_028C70_COLOR_16:
942 case V_028C70_COLOR_8_8:
943 return V_028C70_ENDIAN_8IN16;
944
945 /* 32-bit buffers. */
946 case V_028C70_COLOR_8_8_8_8:
947 case V_028C70_COLOR_2_10_10_10:
948 case V_028C70_COLOR_8_24:
949 case V_028C70_COLOR_24_8:
950 case V_028C70_COLOR_16_16:
951 return V_028C70_ENDIAN_8IN32;
952
953 /* 64-bit buffers. */
954 case V_028C70_COLOR_16_16_16_16:
955 return V_028C70_ENDIAN_8IN16;
956
957 case V_028C70_COLOR_32_32:
958 return V_028C70_ENDIAN_8IN32;
959
960 /* 128-bit buffers. */
961 case V_028C70_COLOR_32_32_32_32:
962 return V_028C70_ENDIAN_8IN32;
963 default:
964 return V_028C70_ENDIAN_NONE; /* Unsupported. */
965 }
966 } else {
967 return V_028C70_ENDIAN_NONE;
968 }
969 }
970
971 static uint32_t si_translate_dbformat(enum pipe_format format)
972 {
973 switch (format) {
974 case PIPE_FORMAT_Z16_UNORM:
975 return V_028040_Z_16;
976 case PIPE_FORMAT_Z24X8_UNORM:
977 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
978 return V_028040_Z_24; /* XXX no longer supported on SI */
979 case PIPE_FORMAT_Z32_FLOAT:
980 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
981 return V_028040_Z_32_FLOAT;
982 default:
983 return ~0U;
984 }
985 }
986
987 /*
988 * framebuffer handling
989 */
990
991 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
992 const struct pipe_framebuffer_state *state, int cb)
993 {
994 struct r600_resource_texture *rtex;
995 struct r600_surface *surf;
996 unsigned level = state->cbufs[cb]->u.tex.level;
997 unsigned pitch, slice;
998 unsigned color_info, color_attrib;
999 unsigned format, swap, ntype, endian;
1000 uint64_t offset;
1001 unsigned blocksize;
1002 const struct util_format_description *desc;
1003 int i;
1004 unsigned blend_clamp = 0, blend_bypass = 0;
1005
1006 surf = (struct r600_surface *)state->cbufs[cb];
1007 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1008 blocksize = util_format_get_blocksize(rtex->real_format);
1009
1010 if (rtex->depth)
1011 rctx->have_depth_fb = TRUE;
1012
1013 if (rtex->depth && !rtex->is_flushing_texture) {
1014 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1015 rtex = rtex->flushed_depth_texture;
1016 }
1017
1018 offset = rtex->surface.level[level].offset;
1019 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1020 offset += rtex->surface.level[level].slice_size *
1021 state->cbufs[cb]->u.tex.first_layer;
1022 }
1023 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1024 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1025 if (slice) {
1026 slice = slice - 1;
1027 }
1028
1029 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1030 switch (rtex->surface.level[level].mode) {
1031 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1032 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1033 break;
1034 case RADEON_SURF_MODE_1D:
1035 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1036 break;
1037 case RADEON_SURF_MODE_2D:
1038 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1039 switch (blocksize) {
1040 case 1:
1041 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1042 break;
1043 case 2:
1044 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1045 break;
1046 case 4:
1047 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1048 break;
1049 }
1050 break;
1051 } else switch (blocksize) {
1052 case 1:
1053 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1054 break;
1055 case 2:
1056 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1057 break;
1058 case 4:
1059 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1060 break;
1061 case 8:
1062 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1063 break;
1064 default:
1065 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1066 }
1067 break;
1068 }
1069
1070 desc = util_format_description(surf->base.format);
1071 for (i = 0; i < 4; i++) {
1072 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1073 break;
1074 }
1075 }
1076 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1077 ntype = V_028C70_NUMBER_FLOAT;
1078 } else {
1079 ntype = V_028C70_NUMBER_UNORM;
1080 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1081 ntype = V_028C70_NUMBER_SRGB;
1082 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1083 if (desc->channel[i].normalized)
1084 ntype = V_028C70_NUMBER_SNORM;
1085 else if (desc->channel[i].pure_integer)
1086 ntype = V_028C70_NUMBER_SINT;
1087 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1088 if (desc->channel[i].normalized)
1089 ntype = V_028C70_NUMBER_UNORM;
1090 else if (desc->channel[i].pure_integer)
1091 ntype = V_028C70_NUMBER_UINT;
1092 }
1093 }
1094
1095 format = si_translate_colorformat(surf->base.format);
1096 swap = si_translate_colorswap(surf->base.format);
1097 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1098 endian = V_028C70_ENDIAN_NONE;
1099 } else {
1100 endian = si_colorformat_endian_swap(format);
1101 }
1102
1103 /* blend clamp should be set for all NORM/SRGB types */
1104 if (ntype == V_028C70_NUMBER_UNORM ||
1105 ntype == V_028C70_NUMBER_SNORM ||
1106 ntype == V_028C70_NUMBER_SRGB)
1107 blend_clamp = 1;
1108
1109 /* set blend bypass according to docs if SINT/UINT or
1110 8/24 COLOR variants */
1111 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1112 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1113 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1114 blend_clamp = 0;
1115 blend_bypass = 1;
1116 }
1117
1118 color_info = S_028C70_FORMAT(format) |
1119 S_028C70_COMP_SWAP(swap) |
1120 S_028C70_BLEND_CLAMP(blend_clamp) |
1121 S_028C70_BLEND_BYPASS(blend_bypass) |
1122 S_028C70_NUMBER_TYPE(ntype) |
1123 S_028C70_ENDIAN(endian);
1124
1125 rctx->alpha_ref_dirty = true;
1126
1127 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1128 offset >>= 8;
1129
1130 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1131 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1132 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1133 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1134 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1135
1136 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1137 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1138 } else {
1139 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1140 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1141 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1142 }
1143 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1144 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1145 }
1146
1147 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1148 const struct pipe_framebuffer_state *state)
1149 {
1150 struct r600_resource_texture *rtex;
1151 struct r600_surface *surf;
1152 unsigned level, first_layer, pitch, slice, format;
1153 uint32_t db_z_info, stencil_info;
1154 uint64_t offset;
1155
1156 if (state->zsbuf == NULL) {
1157 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1158 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1159 return;
1160 }
1161
1162 surf = (struct r600_surface *)state->zsbuf;
1163 level = surf->base.u.tex.level;
1164 rtex = (struct r600_resource_texture*)surf->base.texture;
1165
1166 first_layer = surf->base.u.tex.first_layer;
1167 format = si_translate_dbformat(rtex->real_format);
1168
1169 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1170 offset += rtex->surface.level[level].offset;
1171 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1172 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1173 if (slice) {
1174 slice = slice - 1;
1175 }
1176 offset >>= 8;
1177
1178 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1179 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, offset);
1180 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, offset);
1181 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1182 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1183 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1184
1185 db_z_info = S_028040_FORMAT(format);
1186 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1187
1188 switch (format) {
1189 case V_028040_Z_16:
1190 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1191 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1192 break;
1193 case V_028040_Z_24:
1194 case V_028040_Z_32_FLOAT:
1195 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1196 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1197 break;
1198 default:
1199 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1200 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1201 }
1202
1203 if (rtex->stencil) {
1204 uint64_t stencil_offset =
1205 r600_texture_get_offset(rtex->stencil, level, first_layer);
1206
1207 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1208 stencil_offset >>= 8;
1209
1210 si_pm4_add_bo(pm4, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1211 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, stencil_offset);
1212 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, stencil_offset);
1213 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, stencil_info);
1214 } else {
1215 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1216 }
1217
1218 if (format != ~0U) {
1219 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1220 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, db_z_info);
1221 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1222 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1223
1224 } else {
1225 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1226 }
1227 }
1228
1229 static void si_set_framebuffer_state(struct pipe_context *ctx,
1230 const struct pipe_framebuffer_state *state)
1231 {
1232 struct r600_context *rctx = (struct r600_context *)ctx;
1233 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1234 uint32_t shader_mask, tl, br;
1235 int tl_x, tl_y, br_x, br_y;
1236
1237 if (pm4 == NULL)
1238 return;
1239
1240 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1241
1242 if (state->zsbuf)
1243 si_pm4_inval_zsbuf_cache(pm4);
1244
1245 util_copy_framebuffer_state(&rctx->framebuffer, state);
1246
1247 /* build states */
1248 rctx->have_depth_fb = 0;
1249 for (int i = 0; i < state->nr_cbufs; i++) {
1250 si_cb(rctx, pm4, state, i);
1251 }
1252 si_db(rctx, pm4, state);
1253
1254 shader_mask = 0;
1255 for (int i = 0; i < state->nr_cbufs; i++) {
1256 shader_mask |= 0xf << (i * 4);
1257 }
1258 tl_x = 0;
1259 tl_y = 0;
1260 br_x = state->width;
1261 br_y = state->height;
1262 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1263 /* EG hw workaround */
1264 if (br_x == 0)
1265 tl_x = 1;
1266 if (br_y == 0)
1267 tl_y = 1;
1268 /* cayman hw workaround */
1269 if (rctx->chip_class == CAYMAN) {
1270 if (br_x == 1 && br_y == 1)
1271 br_x = 2;
1272 }
1273 #endif
1274 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1275 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1276
1277 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1278 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1279 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1280 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1281 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1282 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1283 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1284 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1285 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1286 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1287 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1288 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1289
1290 si_pm4_set_state(rctx, framebuffer, pm4);
1291 si_update_fb_rs_state(rctx);
1292 si_update_fb_blend_state(rctx);
1293 }
1294
1295 /*
1296 * shaders
1297 */
1298
1299 static void *si_create_shader_state(struct pipe_context *ctx,
1300 const struct pipe_shader_state *state)
1301 {
1302 struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
1303
1304 shader->tokens = tgsi_dup_tokens(state->tokens);
1305 shader->so = state->stream_output;
1306
1307 return shader;
1308 }
1309
1310 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1311 {
1312 struct r600_context *rctx = (struct r600_context *)ctx;
1313 struct si_pipe_shader *shader = state;
1314
1315 if (rctx->vs_shader == state)
1316 return;
1317
1318 rctx->shader_dirty = true;
1319 rctx->vs_shader = shader;
1320 si_pm4_bind_state(rctx, vs, shader->pm4);
1321 }
1322
1323 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1324 {
1325 struct r600_context *rctx = (struct r600_context *)ctx;
1326 struct si_pipe_shader *shader = state;
1327
1328 if (rctx->ps_shader == state)
1329 return;
1330
1331 rctx->shader_dirty = true;
1332 rctx->ps_shader = shader;
1333 si_pm4_bind_state(rctx, ps, shader->pm4);
1334 }
1335
1336 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
1337 {
1338 struct r600_context *rctx = (struct r600_context *)ctx;
1339 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1340
1341 if (rctx->vs_shader == shader) {
1342 rctx->vs_shader = NULL;
1343 }
1344
1345 si_pm4_delete_state(rctx, vs, shader->pm4);
1346 free(shader->tokens);
1347 si_pipe_shader_destroy(ctx, shader);
1348 free(shader);
1349 }
1350
1351 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
1352 {
1353 struct r600_context *rctx = (struct r600_context *)ctx;
1354 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1355
1356 if (rctx->ps_shader == shader) {
1357 rctx->ps_shader = NULL;
1358 }
1359
1360 si_pm4_delete_state(rctx, ps, shader->pm4);
1361 free(shader->tokens);
1362 si_pipe_shader_destroy(ctx, shader);
1363 free(shader);
1364 }
1365
1366 /*
1367 * Samplers
1368 */
1369
1370 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1371 struct pipe_sampler_view **views)
1372 {
1373 assert(count == 0);
1374 }
1375
1376 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1377 struct pipe_sampler_view **views)
1378 {
1379 struct r600_context *rctx = (struct r600_context *)ctx;
1380 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1381 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1382 struct r600_resource *bo;
1383 int i;
1384 int has_depth = 0;
1385 uint64_t va;
1386 char *ptr;
1387
1388 if (!count)
1389 goto out;
1390
1391 si_pm4_inval_texture_cache(pm4);
1392
1393 bo = (struct r600_resource*)
1394 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1395 count * sizeof(resource[0]->state));
1396 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1397
1398 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1399 struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
1400
1401 pipe_sampler_view_reference(
1402 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1403 views[i]);
1404
1405 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
1406
1407 if (resource[i]) {
1408 if (tex->depth)
1409 has_depth = 1;
1410
1411 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1412 } else
1413 memset(ptr, 0, sizeof(resource[0]->state));
1414 }
1415
1416 rctx->ws->buffer_unmap(bo->cs_buf);
1417
1418 for (i = count; i < NUM_TEX_UNITS; i++) {
1419 if (rctx->ps_samplers.views[i])
1420 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1421 }
1422
1423 va = r600_resource_va(ctx->screen, (void *)bo);
1424 si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
1425 si_pm4_set_reg(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4, va);
1426 si_pm4_set_reg(pm4, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32);
1427
1428 out:
1429 si_pm4_set_state(rctx, ps_sampler_views, pm4);
1430 rctx->have_depth_texture = has_depth;
1431 rctx->ps_samplers.n_views = count;
1432 }
1433
1434 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1435 {
1436 assert(0);
1437 }
1438
1439 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1440 {
1441 struct r600_context *rctx = (struct r600_context *)ctx;
1442 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
1443 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1444 struct r600_resource *bo;
1445 uint64_t va;
1446 char *ptr;
1447 int i;
1448
1449 if (!count)
1450 goto out;
1451
1452 si_pm4_inval_texture_cache(pm4);
1453
1454 bo = (struct r600_resource*)
1455 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
1456 count * sizeof(rstates[0]->val));
1457 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1458
1459 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
1460 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
1461 }
1462
1463 rctx->ws->buffer_unmap(bo->cs_buf);
1464
1465 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1466
1467 va = r600_resource_va(ctx->screen, (void *)bo);
1468 si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
1469 si_pm4_set_reg(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2, va);
1470 si_pm4_set_reg(pm4, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32);
1471
1472 out:
1473 si_pm4_set_state(rctx, ps_sampler, pm4);
1474 rctx->ps_samplers.n_samplers = count;
1475 }
1476
1477 /*
1478 * Constants
1479 */
1480 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1481 struct pipe_constant_buffer *cb)
1482 {
1483 struct r600_context *rctx = (struct r600_context *)ctx;
1484 struct r600_resource *rbuffer = cb ? r600_resource(cb->buffer) : NULL;
1485 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1486 uint64_t va_offset;
1487 uint32_t offset;
1488
1489 /* Note that the state tracker can unbind constant buffers by
1490 * passing NULL here.
1491 */
1492 if (cb == NULL) {
1493 FREE(pm4);
1494 return;
1495 }
1496
1497 si_pm4_inval_shader_cache(pm4);
1498
1499 if (cb->user_buffer)
1500 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
1501 else
1502 offset = 0;
1503 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
1504 va_offset += offset;
1505
1506 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
1507
1508 switch (shader) {
1509 case PIPE_SHADER_VERTEX:
1510 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset);
1511 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32);
1512 si_pm4_set_state(rctx, vs_const, pm4);
1513 break;
1514
1515 case PIPE_SHADER_FRAGMENT:
1516 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset);
1517 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32);
1518 si_pm4_set_state(rctx, ps_const, pm4);
1519 break;
1520
1521 default:
1522 R600_ERR("unsupported %d\n", shader);
1523 return;
1524 }
1525
1526 if (cb->buffer != &rbuffer->b.b)
1527 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
1528 }
1529
1530 void si_init_state_functions(struct r600_context *rctx)
1531 {
1532 rctx->context.create_blend_state = si_create_blend_state;
1533 rctx->context.bind_blend_state = si_bind_blend_state;
1534 rctx->context.delete_blend_state = si_delete_blend_state;
1535 rctx->context.set_blend_color = si_set_blend_color;
1536
1537 rctx->context.create_rasterizer_state = si_create_rs_state;
1538 rctx->context.bind_rasterizer_state = si_bind_rs_state;
1539 rctx->context.delete_rasterizer_state = si_delete_rs_state;
1540
1541 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
1542 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
1543 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
1544 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
1545
1546 rctx->context.set_clip_state = si_set_clip_state;
1547 rctx->context.set_scissor_state = si_set_scissor_state;
1548 rctx->context.set_viewport_state = si_set_viewport_state;
1549 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
1550
1551 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
1552
1553 rctx->context.create_vs_state = si_create_shader_state;
1554 rctx->context.create_fs_state = si_create_shader_state;
1555 rctx->context.bind_vs_state = si_bind_vs_shader;
1556 rctx->context.bind_fs_state = si_bind_ps_shader;
1557 rctx->context.delete_vs_state = si_delete_vs_shader;
1558 rctx->context.delete_fs_state = si_delete_ps_shader;
1559
1560 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
1561 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
1562
1563 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
1564 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
1565
1566 rctx->context.set_constant_buffer = si_set_constant_buffer;
1567
1568 rctx->context.draw_vbo = si_draw_vbo;
1569 }
1570
1571 void si_init_config(struct r600_context *rctx)
1572 {
1573 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1574
1575 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
1576
1577 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
1578 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
1579 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
1580 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
1581 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
1582 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
1583 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
1584 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
1585 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
1586 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
1587 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
1588 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
1589 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
1590 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
1591 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
1592 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
1593 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
1594 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
1595 S_028AA8_SWITCH_ON_EOP(1) |
1596 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
1597 S_028AA8_PRIMGROUP_SIZE(63));
1598 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
1599 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
1600 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1601
1602 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
1603 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
1604 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
1605
1606 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
1607
1608 si_pm4_set_state(rctx, init, pm4);
1609 }