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radeonsi: remove si_atom::id
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 /* Initialize an atom owned by radeonsi. */
37 void si_init_atom(struct si_context *sctx, struct si_atom *atom,
38 void (*emit_func)(struct si_context *ctx, struct si_atom *state))
39 {
40 atom->emit = emit_func;
41 }
42
43 static unsigned si_map_swizzle(unsigned swizzle)
44 {
45 switch (swizzle) {
46 case PIPE_SWIZZLE_Y:
47 return V_008F0C_SQ_SEL_Y;
48 case PIPE_SWIZZLE_Z:
49 return V_008F0C_SQ_SEL_Z;
50 case PIPE_SWIZZLE_W:
51 return V_008F0C_SQ_SEL_W;
52 case PIPE_SWIZZLE_0:
53 return V_008F0C_SQ_SEL_0;
54 case PIPE_SWIZZLE_1:
55 return V_008F0C_SQ_SEL_1;
56 default: /* PIPE_SWIZZLE_X */
57 return V_008F0C_SQ_SEL_X;
58 }
59 }
60
61 /* 12.4 fixed-point */
62 static unsigned si_pack_float_12p4(float x)
63 {
64 return x <= 0 ? 0 :
65 x >= 4096 ? 0xffff : x * 16;
66 }
67
68 /*
69 * Inferred framebuffer and blender state.
70 *
71 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
72 * if there is not enough PS outputs.
73 */
74 static void si_emit_cb_render_state(struct si_context *sctx, struct si_atom *atom)
75 {
76 struct radeon_winsys_cs *cs = sctx->gfx_cs;
77 struct si_state_blend *blend = sctx->queued.named.blend;
78 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
79 * but you never know. */
80 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
81 unsigned i;
82
83 if (blend)
84 cb_target_mask &= blend->cb_target_mask;
85
86 /* Avoid a hang that happens when dual source blending is enabled
87 * but there is not enough color outputs. This is undefined behavior,
88 * so disable color writes completely.
89 *
90 * Reproducible with Unigine Heaven 4.0 and drirc missing.
91 */
92 if (blend && blend->dual_src_blend &&
93 sctx->ps_shader.cso &&
94 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
95 cb_target_mask = 0;
96
97 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
98
99 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
100 * I think we don't have to do anything between IBs.
101 */
102 if (sctx->screen->dfsm_allowed &&
103 sctx->last_cb_target_mask != cb_target_mask) {
104 sctx->last_cb_target_mask = cb_target_mask;
105
106 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
107 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
108 }
109
110 if (sctx->chip_class >= VI) {
111 /* DCC MSAA workaround for blending.
112 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
113 * COMBINER_DISABLE, but that would be more complicated.
114 */
115 bool oc_disable = (sctx->chip_class == VI ||
116 sctx->chip_class == GFX9) &&
117 blend &&
118 blend->blend_enable_4bit & cb_target_mask &&
119 sctx->framebuffer.nr_samples >= 2;
120
121 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
122 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
123 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
124 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
125 }
126
127 /* RB+ register settings. */
128 if (sctx->screen->rbplus_allowed) {
129 unsigned spi_shader_col_format =
130 sctx->ps_shader.cso ?
131 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
132 unsigned sx_ps_downconvert = 0;
133 unsigned sx_blend_opt_epsilon = 0;
134 unsigned sx_blend_opt_control = 0;
135
136 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
137 struct r600_surface *surf =
138 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
139 unsigned format, swap, spi_format, colormask;
140 bool has_alpha, has_rgb;
141
142 if (!surf)
143 continue;
144
145 format = G_028C70_FORMAT(surf->cb_color_info);
146 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
147 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
149
150 /* Set if RGB and A are present. */
151 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
152
153 if (format == V_028C70_COLOR_8 ||
154 format == V_028C70_COLOR_16 ||
155 format == V_028C70_COLOR_32)
156 has_rgb = !has_alpha;
157 else
158 has_rgb = true;
159
160 /* Check the colormask and export format. */
161 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
162 has_rgb = false;
163 if (!(colormask & PIPE_MASK_A))
164 has_alpha = false;
165
166 if (spi_format == V_028714_SPI_SHADER_ZERO) {
167 has_rgb = false;
168 has_alpha = false;
169 }
170
171 /* Disable value checking for disabled channels. */
172 if (!has_rgb)
173 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
174 if (!has_alpha)
175 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
176
177 /* Enable down-conversion for 32bpp and smaller formats. */
178 switch (format) {
179 case V_028C70_COLOR_8:
180 case V_028C70_COLOR_8_8:
181 case V_028C70_COLOR_8_8_8_8:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_5_6_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_1_5_5_5:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_4_4_4_4:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_32:
213 if (swap == V_028C70_SWAP_STD &&
214 spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV &&
217 spi_format == V_028714_SPI_SHADER_32_AR)
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
219 break;
220
221 case V_028C70_COLOR_16:
222 case V_028C70_COLOR_16_16:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
227 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
228 if (swap == V_028C70_SWAP_STD ||
229 swap == V_028C70_SWAP_STD_REV)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
231 else
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_10_11_11:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
240 }
241 break;
242
243 case V_028C70_COLOR_2_10_10_10:
244 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
246 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
247 }
248 break;
249 }
250 }
251
252 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
253 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
254 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
255 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
256 }
257 }
258
259 /*
260 * Blender functions
261 */
262
263 static uint32_t si_translate_blend_function(int blend_func)
264 {
265 switch (blend_func) {
266 case PIPE_BLEND_ADD:
267 return V_028780_COMB_DST_PLUS_SRC;
268 case PIPE_BLEND_SUBTRACT:
269 return V_028780_COMB_SRC_MINUS_DST;
270 case PIPE_BLEND_REVERSE_SUBTRACT:
271 return V_028780_COMB_DST_MINUS_SRC;
272 case PIPE_BLEND_MIN:
273 return V_028780_COMB_MIN_DST_SRC;
274 case PIPE_BLEND_MAX:
275 return V_028780_COMB_MAX_DST_SRC;
276 default:
277 PRINT_ERR("Unknown blend function %d\n", blend_func);
278 assert(0);
279 break;
280 }
281 return 0;
282 }
283
284 static uint32_t si_translate_blend_factor(int blend_fact)
285 {
286 switch (blend_fact) {
287 case PIPE_BLENDFACTOR_ONE:
288 return V_028780_BLEND_ONE;
289 case PIPE_BLENDFACTOR_SRC_COLOR:
290 return V_028780_BLEND_SRC_COLOR;
291 case PIPE_BLENDFACTOR_SRC_ALPHA:
292 return V_028780_BLEND_SRC_ALPHA;
293 case PIPE_BLENDFACTOR_DST_ALPHA:
294 return V_028780_BLEND_DST_ALPHA;
295 case PIPE_BLENDFACTOR_DST_COLOR:
296 return V_028780_BLEND_DST_COLOR;
297 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
298 return V_028780_BLEND_SRC_ALPHA_SATURATE;
299 case PIPE_BLENDFACTOR_CONST_COLOR:
300 return V_028780_BLEND_CONSTANT_COLOR;
301 case PIPE_BLENDFACTOR_CONST_ALPHA:
302 return V_028780_BLEND_CONSTANT_ALPHA;
303 case PIPE_BLENDFACTOR_ZERO:
304 return V_028780_BLEND_ZERO;
305 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
306 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
307 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
310 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
311 case PIPE_BLENDFACTOR_INV_DST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
315 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
316 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
317 case PIPE_BLENDFACTOR_SRC1_COLOR:
318 return V_028780_BLEND_SRC1_COLOR;
319 case PIPE_BLENDFACTOR_SRC1_ALPHA:
320 return V_028780_BLEND_SRC1_ALPHA;
321 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
322 return V_028780_BLEND_INV_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
324 return V_028780_BLEND_INV_SRC1_ALPHA;
325 default:
326 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
327 assert(0);
328 break;
329 }
330 return 0;
331 }
332
333 static uint32_t si_translate_blend_opt_function(int blend_func)
334 {
335 switch (blend_func) {
336 case PIPE_BLEND_ADD:
337 return V_028760_OPT_COMB_ADD;
338 case PIPE_BLEND_SUBTRACT:
339 return V_028760_OPT_COMB_SUBTRACT;
340 case PIPE_BLEND_REVERSE_SUBTRACT:
341 return V_028760_OPT_COMB_REVSUBTRACT;
342 case PIPE_BLEND_MIN:
343 return V_028760_OPT_COMB_MIN;
344 case PIPE_BLEND_MAX:
345 return V_028760_OPT_COMB_MAX;
346 default:
347 return V_028760_OPT_COMB_BLEND_DISABLED;
348 }
349 }
350
351 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
352 {
353 switch (blend_fact) {
354 case PIPE_BLENDFACTOR_ZERO:
355 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
356 case PIPE_BLENDFACTOR_ONE:
357 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
358 case PIPE_BLENDFACTOR_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
360 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
361 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
363 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
364 case PIPE_BLENDFACTOR_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
366 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
367 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
369 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
370 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
371 default:
372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
373 }
374 }
375
376 static void si_blend_check_commutativity(struct si_screen *sscreen,
377 struct si_state_blend *blend,
378 enum pipe_blend_func func,
379 enum pipe_blendfactor src,
380 enum pipe_blendfactor dst,
381 unsigned chanmask)
382 {
383 /* Src factor is allowed when it does not depend on Dst */
384 static const uint32_t src_allowed =
385 (1u << PIPE_BLENDFACTOR_ONE) |
386 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
387 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
388 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
389 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
390 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
392 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_ZERO) |
394 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
397 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
399 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
400
401 if (dst == PIPE_BLENDFACTOR_ONE &&
402 (src_allowed & (1u << src))) {
403 /* Addition is commutative, but floating point addition isn't
404 * associative: subtle changes can be introduced via different
405 * rounding.
406 *
407 * Out-of-order is also non-deterministic, which means that
408 * this breaks OpenGL invariance requirements. So only enable
409 * out-of-order additive blending if explicitly allowed by a
410 * setting.
411 */
412 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
413 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
414 blend->commutative_4bit |= chanmask;
415 }
416 }
417
418 /**
419 * Get rid of DST in the blend factors by commuting the operands:
420 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
421 */
422 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
423 unsigned *dst_factor, unsigned expected_dst,
424 unsigned replacement_src)
425 {
426 if (*src_factor == expected_dst &&
427 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
428 *src_factor = PIPE_BLENDFACTOR_ZERO;
429 *dst_factor = replacement_src;
430
431 /* Commuting the operands requires reversing subtractions. */
432 if (*func == PIPE_BLEND_SUBTRACT)
433 *func = PIPE_BLEND_REVERSE_SUBTRACT;
434 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
435 *func = PIPE_BLEND_SUBTRACT;
436 }
437 }
438
439 static bool si_blend_factor_uses_dst(unsigned factor)
440 {
441 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
442 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
443 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
444 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
445 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
446 }
447
448 static void *si_create_blend_state_mode(struct pipe_context *ctx,
449 const struct pipe_blend_state *state,
450 unsigned mode)
451 {
452 struct si_context *sctx = (struct si_context*)ctx;
453 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
454 struct si_pm4_state *pm4 = &blend->pm4;
455 uint32_t sx_mrt_blend_opt[8] = {0};
456 uint32_t color_control = 0;
457
458 if (!blend)
459 return NULL;
460
461 blend->alpha_to_coverage = state->alpha_to_coverage;
462 blend->alpha_to_one = state->alpha_to_one;
463 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
464 blend->logicop_enable = state->logicop_enable;
465
466 if (state->logicop_enable) {
467 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
468 } else {
469 color_control |= S_028808_ROP3(0xcc);
470 }
471
472 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
473 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
474 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
475 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
476 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
477 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
478
479 if (state->alpha_to_coverage)
480 blend->need_src_alpha_4bit |= 0xf;
481
482 blend->cb_target_mask = 0;
483 blend->cb_target_enabled_4bit = 0;
484
485 for (int i = 0; i < 8; i++) {
486 /* state->rt entries > 0 only written if independent blending */
487 const int j = state->independent_blend_enable ? i : 0;
488
489 unsigned eqRGB = state->rt[j].rgb_func;
490 unsigned srcRGB = state->rt[j].rgb_src_factor;
491 unsigned dstRGB = state->rt[j].rgb_dst_factor;
492 unsigned eqA = state->rt[j].alpha_func;
493 unsigned srcA = state->rt[j].alpha_src_factor;
494 unsigned dstA = state->rt[j].alpha_dst_factor;
495
496 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
497 unsigned blend_cntl = 0;
498
499 sx_mrt_blend_opt[i] =
500 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
501 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
502
503 /* Only set dual source blending for MRT0 to avoid a hang. */
504 if (i >= 1 && blend->dual_src_blend) {
505 /* Vulkan does this for dual source blending. */
506 if (i == 1)
507 blend_cntl |= S_028780_ENABLE(1);
508
509 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
510 continue;
511 }
512
513 /* Only addition and subtraction equations are supported with
514 * dual source blending.
515 */
516 if (blend->dual_src_blend &&
517 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
518 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
519 assert(!"Unsupported equation for dual source blending");
520 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
521 continue;
522 }
523
524 /* cb_render_state will disable unused ones */
525 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
526 if (state->rt[j].colormask)
527 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
528
529 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
530 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
531 continue;
532 }
533
534 si_blend_check_commutativity(sctx->screen, blend,
535 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
536 si_blend_check_commutativity(sctx->screen, blend,
537 eqA, srcA, dstA, 0x8 << (4 * i));
538
539 /* Blending optimizations for RB+.
540 * These transformations don't change the behavior.
541 *
542 * First, get rid of DST in the blend factors:
543 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
544 */
545 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
546 PIPE_BLENDFACTOR_DST_COLOR,
547 PIPE_BLENDFACTOR_SRC_COLOR);
548 si_blend_remove_dst(&eqA, &srcA, &dstA,
549 PIPE_BLENDFACTOR_DST_COLOR,
550 PIPE_BLENDFACTOR_SRC_COLOR);
551 si_blend_remove_dst(&eqA, &srcA, &dstA,
552 PIPE_BLENDFACTOR_DST_ALPHA,
553 PIPE_BLENDFACTOR_SRC_ALPHA);
554
555 /* Look up the ideal settings from tables. */
556 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
557 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
558 srcA_opt = si_translate_blend_opt_factor(srcA, true);
559 dstA_opt = si_translate_blend_opt_factor(dstA, true);
560
561 /* Handle interdependencies. */
562 if (si_blend_factor_uses_dst(srcRGB))
563 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
564 if (si_blend_factor_uses_dst(srcA))
565 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
566
567 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
568 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
569 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
570 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
571 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
572
573 /* Set the final value. */
574 sx_mrt_blend_opt[i] =
575 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
576 S_028760_COLOR_DST_OPT(dstRGB_opt) |
577 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
578 S_028760_ALPHA_SRC_OPT(srcA_opt) |
579 S_028760_ALPHA_DST_OPT(dstA_opt) |
580 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
581
582 /* Set blend state. */
583 blend_cntl |= S_028780_ENABLE(1);
584 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
585 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
586 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
587
588 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
589 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
590 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
591 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
592 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
593 }
594 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
595
596 blend->blend_enable_4bit |= 0xfu << (i * 4);
597
598 /* This is only important for formats without alpha. */
599 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
600 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
601 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
602 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
603 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
605 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
606 }
607
608 if (blend->cb_target_mask) {
609 color_control |= S_028808_MODE(mode);
610 } else {
611 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
612 }
613
614 if (sctx->screen->rbplus_allowed) {
615 /* Disable RB+ blend optimizations for dual source blending.
616 * Vulkan does this.
617 */
618 if (blend->dual_src_blend) {
619 for (int i = 0; i < 8; i++) {
620 sx_mrt_blend_opt[i] =
621 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
622 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
623 }
624 }
625
626 for (int i = 0; i < 8; i++)
627 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
628 sx_mrt_blend_opt[i]);
629
630 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
631 if (blend->dual_src_blend || state->logicop_enable ||
632 mode == V_028808_CB_RESOLVE)
633 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
634 }
635
636 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
637 return blend;
638 }
639
640 static void *si_create_blend_state(struct pipe_context *ctx,
641 const struct pipe_blend_state *state)
642 {
643 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
644 }
645
646 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
647 {
648 struct si_context *sctx = (struct si_context *)ctx;
649 struct si_state_blend *old_blend = sctx->queued.named.blend;
650 struct si_state_blend *blend = (struct si_state_blend *)state;
651
652 if (!state)
653 return;
654
655 si_pm4_bind_state(sctx, blend, state);
656
657 if (!old_blend ||
658 old_blend->cb_target_mask != blend->cb_target_mask ||
659 old_blend->dual_src_blend != blend->dual_src_blend ||
660 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
661 sctx->framebuffer.nr_samples >= 2 &&
662 sctx->screen->dcc_msaa_allowed))
663 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
664
665 if (!old_blend ||
666 old_blend->cb_target_mask != blend->cb_target_mask ||
667 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
668 old_blend->alpha_to_one != blend->alpha_to_one ||
669 old_blend->dual_src_blend != blend->dual_src_blend ||
670 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
671 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
672 sctx->do_update_shaders = true;
673
674 if (sctx->screen->dpbb_allowed &&
675 (!old_blend ||
676 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
677 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
678 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
679 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
680
681 if (sctx->screen->has_out_of_order_rast &&
682 (!old_blend ||
683 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
684 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
685 old_blend->commutative_4bit != blend->commutative_4bit ||
686 old_blend->logicop_enable != blend->logicop_enable)))
687 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
688 }
689
690 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
691 {
692 struct si_context *sctx = (struct si_context *)ctx;
693 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
694 }
695
696 static void si_set_blend_color(struct pipe_context *ctx,
697 const struct pipe_blend_color *state)
698 {
699 struct si_context *sctx = (struct si_context *)ctx;
700 static const struct pipe_blend_color zeros;
701
702 sctx->blend_color.state = *state;
703 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
704 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
705 }
706
707 static void si_emit_blend_color(struct si_context *sctx, struct si_atom *atom)
708 {
709 struct radeon_winsys_cs *cs = sctx->gfx_cs;
710
711 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
712 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
713 }
714
715 /*
716 * Clipping
717 */
718
719 static void si_set_clip_state(struct pipe_context *ctx,
720 const struct pipe_clip_state *state)
721 {
722 struct si_context *sctx = (struct si_context *)ctx;
723 struct pipe_constant_buffer cb;
724 static const struct pipe_clip_state zeros;
725
726 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
727 return;
728
729 sctx->clip_state.state = *state;
730 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
731 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
732
733 cb.buffer = NULL;
734 cb.user_buffer = state->ucp;
735 cb.buffer_offset = 0;
736 cb.buffer_size = 4*4*8;
737 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
738 pipe_resource_reference(&cb.buffer, NULL);
739 }
740
741 static void si_emit_clip_state(struct si_context *sctx, struct si_atom *atom)
742 {
743 struct radeon_winsys_cs *cs = sctx->gfx_cs;
744
745 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
746 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
747 }
748
749 static void si_emit_clip_regs(struct si_context *sctx, struct si_atom *atom)
750 {
751 struct radeon_winsys_cs *cs = sctx->gfx_cs;
752 struct si_shader *vs = si_get_vs_state(sctx);
753 struct si_shader_selector *vs_sel = vs->selector;
754 struct tgsi_shader_info *info = &vs_sel->info;
755 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
756 unsigned window_space =
757 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
758 unsigned clipdist_mask = vs_sel->clipdist_mask;
759 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
760 unsigned culldist_mask = vs_sel->culldist_mask;
761 unsigned total_mask;
762
763 if (vs->key.opt.clip_disable) {
764 assert(!info->culldist_writemask);
765 clipdist_mask = 0;
766 culldist_mask = 0;
767 }
768 total_mask = clipdist_mask | culldist_mask;
769
770 /* Clip distances on points have no effect, so need to be implemented
771 * as cull distances. This applies for the clipvertex case as well.
772 *
773 * Setting this for primitives other than points should have no adverse
774 * effects.
775 */
776 clipdist_mask &= rs->clip_plane_enable;
777 culldist_mask |= clipdist_mask;
778
779 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
780 vs_sel->pa_cl_vs_out_cntl |
781 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
782 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
783 clipdist_mask | (culldist_mask << 8));
784 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
785 rs->pa_cl_clip_cntl |
786 ucp_mask |
787 S_028810_CLIP_DISABLE(window_space));
788 }
789
790 /*
791 * inferred state between framebuffer and rasterizer
792 */
793 static void si_update_poly_offset_state(struct si_context *sctx)
794 {
795 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
796
797 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
798 si_pm4_bind_state(sctx, poly_offset, NULL);
799 return;
800 }
801
802 /* Use the user format, not db_render_format, so that the polygon
803 * offset behaves as expected by applications.
804 */
805 switch (sctx->framebuffer.state.zsbuf->texture->format) {
806 case PIPE_FORMAT_Z16_UNORM:
807 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
808 break;
809 default: /* 24-bit */
810 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
811 break;
812 case PIPE_FORMAT_Z32_FLOAT:
813 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
814 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
815 break;
816 }
817 }
818
819 /*
820 * Rasterizer
821 */
822
823 static uint32_t si_translate_fill(uint32_t func)
824 {
825 switch(func) {
826 case PIPE_POLYGON_MODE_FILL:
827 return V_028814_X_DRAW_TRIANGLES;
828 case PIPE_POLYGON_MODE_LINE:
829 return V_028814_X_DRAW_LINES;
830 case PIPE_POLYGON_MODE_POINT:
831 return V_028814_X_DRAW_POINTS;
832 default:
833 assert(0);
834 return V_028814_X_DRAW_POINTS;
835 }
836 }
837
838 static void *si_create_rs_state(struct pipe_context *ctx,
839 const struct pipe_rasterizer_state *state)
840 {
841 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
842 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
843 struct si_pm4_state *pm4 = &rs->pm4;
844 unsigned tmp, i;
845 float psize_min, psize_max;
846
847 if (!rs) {
848 return NULL;
849 }
850
851 rs->scissor_enable = state->scissor;
852 rs->clip_halfz = state->clip_halfz;
853 rs->two_side = state->light_twoside;
854 rs->multisample_enable = state->multisample;
855 rs->force_persample_interp = state->force_persample_interp;
856 rs->clip_plane_enable = state->clip_plane_enable;
857 rs->line_stipple_enable = state->line_stipple_enable;
858 rs->poly_stipple_enable = state->poly_stipple_enable;
859 rs->line_smooth = state->line_smooth;
860 rs->line_width = state->line_width;
861 rs->poly_smooth = state->poly_smooth;
862 rs->uses_poly_offset = state->offset_point || state->offset_line ||
863 state->offset_tri;
864 rs->clamp_fragment_color = state->clamp_fragment_color;
865 rs->clamp_vertex_color = state->clamp_vertex_color;
866 rs->flatshade = state->flatshade;
867 rs->sprite_coord_enable = state->sprite_coord_enable;
868 rs->rasterizer_discard = state->rasterizer_discard;
869 rs->pa_sc_line_stipple = state->line_stipple_enable ?
870 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
871 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
872 rs->pa_cl_clip_cntl =
873 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
874 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
875 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
876 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
877 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
878
879 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
880 S_0286D4_FLAT_SHADE_ENA(1) |
881 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
882 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
883 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
884 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
885 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
886 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
887
888 /* point size 12.4 fixed point */
889 tmp = (unsigned)(state->point_size * 8.0);
890 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
891
892 if (state->point_size_per_vertex) {
893 psize_min = util_get_min_point_size(state);
894 psize_max = 8192;
895 } else {
896 /* Force the point size to be as if the vertex output was disabled. */
897 psize_min = state->point_size;
898 psize_max = state->point_size;
899 }
900 rs->max_point_size = psize_max;
901
902 /* Divide by two, because 0.5 = 1 pixel. */
903 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
904 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
905 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
906
907 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
908 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
909 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
910 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
911 S_028A48_MSAA_ENABLE(state->multisample ||
912 state->poly_smooth ||
913 state->line_smooth) |
914 S_028A48_VPORT_SCISSOR_ENABLE(1) |
915 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
916
917 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
918 S_028BE4_PIX_CENTER(state->half_pixel_center) |
919 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
920
921 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
922 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
923 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
924 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
925 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
926 S_028814_FACE(!state->front_ccw) |
927 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
928 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
929 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
930 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
931 state->fill_back != PIPE_POLYGON_MODE_FILL) |
932 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
933 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
934
935 if (!rs->uses_poly_offset)
936 return rs;
937
938 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
939 if (!rs->pm4_poly_offset) {
940 FREE(rs);
941 return NULL;
942 }
943
944 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
945 for (i = 0; i < 3; i++) {
946 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
947 float offset_units = state->offset_units;
948 float offset_scale = state->offset_scale * 16.0f;
949 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
950
951 if (!state->offset_units_unscaled) {
952 switch (i) {
953 case 0: /* 16-bit zbuffer */
954 offset_units *= 4.0f;
955 pa_su_poly_offset_db_fmt_cntl =
956 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
957 break;
958 case 1: /* 24-bit zbuffer */
959 offset_units *= 2.0f;
960 pa_su_poly_offset_db_fmt_cntl =
961 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
962 break;
963 case 2: /* 32-bit zbuffer */
964 offset_units *= 1.0f;
965 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
966 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
967 break;
968 }
969 }
970
971 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
972 fui(offset_scale));
973 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
974 fui(offset_units));
975 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
976 fui(offset_scale));
977 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
978 fui(offset_units));
979 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
980 pa_su_poly_offset_db_fmt_cntl);
981 }
982
983 return rs;
984 }
985
986 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
987 {
988 struct si_context *sctx = (struct si_context *)ctx;
989 struct si_state_rasterizer *old_rs =
990 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
991 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
992
993 if (!state)
994 return;
995
996 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
997 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
998
999 /* Update the small primitive filter workaround if necessary. */
1000 if (sctx->screen->has_msaa_sample_loc_bug &&
1001 sctx->framebuffer.nr_samples > 1)
1002 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1003 }
1004
1005 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1006 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1007
1008 si_pm4_bind_state(sctx, rasterizer, rs);
1009 si_update_poly_offset_state(sctx);
1010
1011 if (!old_rs ||
1012 (old_rs->scissor_enable != rs->scissor_enable ||
1013 old_rs->line_width != rs->line_width ||
1014 old_rs->max_point_size != rs->max_point_size)) {
1015 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1016 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1017 }
1018
1019 if (!old_rs ||
1020 old_rs->clip_halfz != rs->clip_halfz) {
1021 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1022 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1023 }
1024
1025 if (!old_rs ||
1026 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1027 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1028 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1029
1030 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1031 rs->line_stipple_enable;
1032
1033 if (!old_rs ||
1034 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1035 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1036 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1037 old_rs->flatshade != rs->flatshade ||
1038 old_rs->two_side != rs->two_side ||
1039 old_rs->multisample_enable != rs->multisample_enable ||
1040 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1041 old_rs->poly_smooth != rs->poly_smooth ||
1042 old_rs->line_smooth != rs->line_smooth ||
1043 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1044 old_rs->force_persample_interp != rs->force_persample_interp)
1045 sctx->do_update_shaders = true;
1046 }
1047
1048 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1049 {
1050 struct si_context *sctx = (struct si_context *)ctx;
1051 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1052
1053 if (sctx->queued.named.rasterizer == state)
1054 si_pm4_bind_state(sctx, poly_offset, NULL);
1055
1056 FREE(rs->pm4_poly_offset);
1057 si_pm4_delete_state(sctx, rasterizer, rs);
1058 }
1059
1060 /*
1061 * infeered state between dsa and stencil ref
1062 */
1063 static void si_emit_stencil_ref(struct si_context *sctx, struct si_atom *atom)
1064 {
1065 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1066 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1067 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1068
1069 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1070 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1071 S_028430_STENCILMASK(dsa->valuemask[0]) |
1072 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1073 S_028430_STENCILOPVAL(1));
1074 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1075 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1076 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1077 S_028434_STENCILOPVAL_BF(1));
1078 }
1079
1080 static void si_set_stencil_ref(struct pipe_context *ctx,
1081 const struct pipe_stencil_ref *state)
1082 {
1083 struct si_context *sctx = (struct si_context *)ctx;
1084
1085 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1086 return;
1087
1088 sctx->stencil_ref.state = *state;
1089 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1090 }
1091
1092
1093 /*
1094 * DSA
1095 */
1096
1097 static uint32_t si_translate_stencil_op(int s_op)
1098 {
1099 switch (s_op) {
1100 case PIPE_STENCIL_OP_KEEP:
1101 return V_02842C_STENCIL_KEEP;
1102 case PIPE_STENCIL_OP_ZERO:
1103 return V_02842C_STENCIL_ZERO;
1104 case PIPE_STENCIL_OP_REPLACE:
1105 return V_02842C_STENCIL_REPLACE_TEST;
1106 case PIPE_STENCIL_OP_INCR:
1107 return V_02842C_STENCIL_ADD_CLAMP;
1108 case PIPE_STENCIL_OP_DECR:
1109 return V_02842C_STENCIL_SUB_CLAMP;
1110 case PIPE_STENCIL_OP_INCR_WRAP:
1111 return V_02842C_STENCIL_ADD_WRAP;
1112 case PIPE_STENCIL_OP_DECR_WRAP:
1113 return V_02842C_STENCIL_SUB_WRAP;
1114 case PIPE_STENCIL_OP_INVERT:
1115 return V_02842C_STENCIL_INVERT;
1116 default:
1117 PRINT_ERR("Unknown stencil op %d", s_op);
1118 assert(0);
1119 break;
1120 }
1121 return 0;
1122 }
1123
1124 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1125 {
1126 return s->enabled && s->writemask &&
1127 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1128 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1129 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1130 }
1131
1132 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1133 {
1134 /* REPLACE is normally order invariant, except when the stencil
1135 * reference value is written by the fragment shader. Tracking this
1136 * interaction does not seem worth the effort, so be conservative. */
1137 return op != PIPE_STENCIL_OP_INCR &&
1138 op != PIPE_STENCIL_OP_DECR &&
1139 op != PIPE_STENCIL_OP_REPLACE;
1140 }
1141
1142 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1143 * invariant in the sense that the set of passing fragments as well as the
1144 * final stencil buffer result does not depend on the order of fragments. */
1145 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1146 {
1147 return !state->enabled || !state->writemask ||
1148 /* The following assumes that Z writes are disabled. */
1149 (state->func == PIPE_FUNC_ALWAYS &&
1150 si_order_invariant_stencil_op(state->zpass_op) &&
1151 si_order_invariant_stencil_op(state->zfail_op)) ||
1152 (state->func == PIPE_FUNC_NEVER &&
1153 si_order_invariant_stencil_op(state->fail_op));
1154 }
1155
1156 static void *si_create_dsa_state(struct pipe_context *ctx,
1157 const struct pipe_depth_stencil_alpha_state *state)
1158 {
1159 struct si_context *sctx = (struct si_context *)ctx;
1160 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1161 struct si_pm4_state *pm4 = &dsa->pm4;
1162 unsigned db_depth_control;
1163 uint32_t db_stencil_control = 0;
1164
1165 if (!dsa) {
1166 return NULL;
1167 }
1168
1169 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1170 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1171 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1172 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1173
1174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1176 S_028800_ZFUNC(state->depth.func) |
1177 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1178
1179 /* stencil */
1180 if (state->stencil[0].enabled) {
1181 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1182 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1183 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1184 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1185 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1186
1187 if (state->stencil[1].enabled) {
1188 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1189 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1190 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1191 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1192 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1193 }
1194 }
1195
1196 /* alpha */
1197 if (state->alpha.enabled) {
1198 dsa->alpha_func = state->alpha.func;
1199
1200 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1201 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1202 } else {
1203 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1204 }
1205
1206 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1207 if (state->stencil[0].enabled)
1208 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1209 if (state->depth.bounds_test) {
1210 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1211 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1212 }
1213
1214 dsa->depth_enabled = state->depth.enabled;
1215 dsa->depth_write_enabled = state->depth.enabled &&
1216 state->depth.writemask;
1217 dsa->stencil_enabled = state->stencil[0].enabled;
1218 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1219 (si_dsa_writes_stencil(&state->stencil[0]) ||
1220 si_dsa_writes_stencil(&state->stencil[1]));
1221 dsa->db_can_write = dsa->depth_write_enabled ||
1222 dsa->stencil_write_enabled;
1223
1224 bool zfunc_is_ordered =
1225 state->depth.func == PIPE_FUNC_NEVER ||
1226 state->depth.func == PIPE_FUNC_LESS ||
1227 state->depth.func == PIPE_FUNC_LEQUAL ||
1228 state->depth.func == PIPE_FUNC_GREATER ||
1229 state->depth.func == PIPE_FUNC_GEQUAL;
1230
1231 bool nozwrite_and_order_invariant_stencil =
1232 !dsa->db_can_write ||
1233 (!dsa->depth_write_enabled &&
1234 si_order_invariant_stencil_state(&state->stencil[0]) &&
1235 si_order_invariant_stencil_state(&state->stencil[1]));
1236
1237 dsa->order_invariance[1].zs =
1238 nozwrite_and_order_invariant_stencil ||
1239 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1240 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1241
1242 dsa->order_invariance[1].pass_set =
1243 nozwrite_and_order_invariant_stencil ||
1244 (!dsa->stencil_write_enabled &&
1245 (state->depth.func == PIPE_FUNC_ALWAYS ||
1246 state->depth.func == PIPE_FUNC_NEVER));
1247 dsa->order_invariance[0].pass_set =
1248 !dsa->depth_write_enabled ||
1249 (state->depth.func == PIPE_FUNC_ALWAYS ||
1250 state->depth.func == PIPE_FUNC_NEVER);
1251
1252 dsa->order_invariance[1].pass_last =
1253 sctx->screen->assume_no_z_fights &&
1254 !dsa->stencil_write_enabled &&
1255 dsa->depth_write_enabled && zfunc_is_ordered;
1256 dsa->order_invariance[0].pass_last =
1257 sctx->screen->assume_no_z_fights &&
1258 dsa->depth_write_enabled && zfunc_is_ordered;
1259
1260 return dsa;
1261 }
1262
1263 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1264 {
1265 struct si_context *sctx = (struct si_context *)ctx;
1266 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1267 struct si_state_dsa *dsa = state;
1268
1269 if (!state)
1270 return;
1271
1272 si_pm4_bind_state(sctx, dsa, dsa);
1273
1274 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1275 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1276 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1277 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1278 }
1279
1280 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1281 sctx->do_update_shaders = true;
1282
1283 if (sctx->screen->dpbb_allowed &&
1284 (!old_dsa ||
1285 (old_dsa->depth_enabled != dsa->depth_enabled ||
1286 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1287 old_dsa->db_can_write != dsa->db_can_write)))
1288 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1289
1290 if (sctx->screen->has_out_of_order_rast &&
1291 (!old_dsa ||
1292 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1293 sizeof(old_dsa->order_invariance))))
1294 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1295 }
1296
1297 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1298 {
1299 struct si_context *sctx = (struct si_context *)ctx;
1300 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1301 }
1302
1303 static void *si_create_db_flush_dsa(struct si_context *sctx)
1304 {
1305 struct pipe_depth_stencil_alpha_state dsa = {};
1306
1307 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1308 }
1309
1310 /* DB RENDER STATE */
1311
1312 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1313 {
1314 struct si_context *sctx = (struct si_context*)ctx;
1315
1316 /* Pipeline stat & streamout queries. */
1317 if (enable) {
1318 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1319 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1320 } else {
1321 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1322 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1323 }
1324
1325 /* Occlusion queries. */
1326 if (sctx->occlusion_queries_disabled != !enable) {
1327 sctx->occlusion_queries_disabled = !enable;
1328 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1329 }
1330 }
1331
1332 void si_set_occlusion_query_state(struct si_context *sctx,
1333 bool old_perfect_enable)
1334 {
1335 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1336
1337 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1338
1339 if (perfect_enable != old_perfect_enable)
1340 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1341 }
1342
1343 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1344 {
1345 st->saved_compute = sctx->cs_shader_state.program;
1346
1347 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1348 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1349 }
1350
1351 static void si_emit_db_render_state(struct si_context *sctx, struct si_atom *state)
1352 {
1353 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1354 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1355 unsigned db_shader_control;
1356
1357 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1358
1359 /* DB_RENDER_CONTROL */
1360 if (sctx->dbcb_depth_copy_enabled ||
1361 sctx->dbcb_stencil_copy_enabled) {
1362 radeon_emit(cs,
1363 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1364 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1365 S_028000_COPY_CENTROID(1) |
1366 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1367 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1368 radeon_emit(cs,
1369 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1370 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1371 } else {
1372 radeon_emit(cs,
1373 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1374 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1375 }
1376
1377 /* DB_COUNT_CONTROL (occlusion queries) */
1378 if (sctx->num_occlusion_queries > 0 &&
1379 !sctx->occlusion_queries_disabled) {
1380 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1381
1382 if (sctx->chip_class >= CIK) {
1383 radeon_emit(cs,
1384 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1385 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1386 S_028004_ZPASS_ENABLE(1) |
1387 S_028004_SLICE_EVEN_ENABLE(1) |
1388 S_028004_SLICE_ODD_ENABLE(1));
1389 } else {
1390 radeon_emit(cs,
1391 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1392 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1393 }
1394 } else {
1395 /* Disable occlusion queries. */
1396 if (sctx->chip_class >= CIK) {
1397 radeon_emit(cs, 0);
1398 } else {
1399 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1400 }
1401 }
1402
1403 /* DB_RENDER_OVERRIDE2 */
1404 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1405 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1406 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1407 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1408
1409 db_shader_control = sctx->ps_db_shader_control;
1410
1411 /* Bug workaround for smoothing (overrasterization) on SI. */
1412 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1413 db_shader_control &= C_02880C_Z_ORDER;
1414 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1415 }
1416
1417 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1418 if (!rs || !rs->multisample_enable)
1419 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1420
1421 if (sctx->screen->has_rbplus &&
1422 !sctx->screen->rbplus_allowed)
1423 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1424
1425 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1426 db_shader_control);
1427 }
1428
1429 /*
1430 * format translation
1431 */
1432 static uint32_t si_translate_colorformat(enum pipe_format format)
1433 {
1434 const struct util_format_description *desc = util_format_description(format);
1435 if (!desc)
1436 return V_028C70_COLOR_INVALID;
1437
1438 #define HAS_SIZE(x,y,z,w) \
1439 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1440 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1441
1442 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1443 return V_028C70_COLOR_10_11_11;
1444
1445 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1446 return V_028C70_COLOR_INVALID;
1447
1448 /* hw cannot support mixed formats (except depth/stencil, since
1449 * stencil is not written to). */
1450 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1451 return V_028C70_COLOR_INVALID;
1452
1453 switch (desc->nr_channels) {
1454 case 1:
1455 switch (desc->channel[0].size) {
1456 case 8:
1457 return V_028C70_COLOR_8;
1458 case 16:
1459 return V_028C70_COLOR_16;
1460 case 32:
1461 return V_028C70_COLOR_32;
1462 }
1463 break;
1464 case 2:
1465 if (desc->channel[0].size == desc->channel[1].size) {
1466 switch (desc->channel[0].size) {
1467 case 8:
1468 return V_028C70_COLOR_8_8;
1469 case 16:
1470 return V_028C70_COLOR_16_16;
1471 case 32:
1472 return V_028C70_COLOR_32_32;
1473 }
1474 } else if (HAS_SIZE(8,24,0,0)) {
1475 return V_028C70_COLOR_24_8;
1476 } else if (HAS_SIZE(24,8,0,0)) {
1477 return V_028C70_COLOR_8_24;
1478 }
1479 break;
1480 case 3:
1481 if (HAS_SIZE(5,6,5,0)) {
1482 return V_028C70_COLOR_5_6_5;
1483 } else if (HAS_SIZE(32,8,24,0)) {
1484 return V_028C70_COLOR_X24_8_32_FLOAT;
1485 }
1486 break;
1487 case 4:
1488 if (desc->channel[0].size == desc->channel[1].size &&
1489 desc->channel[0].size == desc->channel[2].size &&
1490 desc->channel[0].size == desc->channel[3].size) {
1491 switch (desc->channel[0].size) {
1492 case 4:
1493 return V_028C70_COLOR_4_4_4_4;
1494 case 8:
1495 return V_028C70_COLOR_8_8_8_8;
1496 case 16:
1497 return V_028C70_COLOR_16_16_16_16;
1498 case 32:
1499 return V_028C70_COLOR_32_32_32_32;
1500 }
1501 } else if (HAS_SIZE(5,5,5,1)) {
1502 return V_028C70_COLOR_1_5_5_5;
1503 } else if (HAS_SIZE(1,5,5,5)) {
1504 return V_028C70_COLOR_5_5_5_1;
1505 } else if (HAS_SIZE(10,10,10,2)) {
1506 return V_028C70_COLOR_2_10_10_10;
1507 }
1508 break;
1509 }
1510 return V_028C70_COLOR_INVALID;
1511 }
1512
1513 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1514 {
1515 if (SI_BIG_ENDIAN) {
1516 switch(colorformat) {
1517 /* 8-bit buffers. */
1518 case V_028C70_COLOR_8:
1519 return V_028C70_ENDIAN_NONE;
1520
1521 /* 16-bit buffers. */
1522 case V_028C70_COLOR_5_6_5:
1523 case V_028C70_COLOR_1_5_5_5:
1524 case V_028C70_COLOR_4_4_4_4:
1525 case V_028C70_COLOR_16:
1526 case V_028C70_COLOR_8_8:
1527 return V_028C70_ENDIAN_8IN16;
1528
1529 /* 32-bit buffers. */
1530 case V_028C70_COLOR_8_8_8_8:
1531 case V_028C70_COLOR_2_10_10_10:
1532 case V_028C70_COLOR_8_24:
1533 case V_028C70_COLOR_24_8:
1534 case V_028C70_COLOR_16_16:
1535 return V_028C70_ENDIAN_8IN32;
1536
1537 /* 64-bit buffers. */
1538 case V_028C70_COLOR_16_16_16_16:
1539 return V_028C70_ENDIAN_8IN16;
1540
1541 case V_028C70_COLOR_32_32:
1542 return V_028C70_ENDIAN_8IN32;
1543
1544 /* 128-bit buffers. */
1545 case V_028C70_COLOR_32_32_32_32:
1546 return V_028C70_ENDIAN_8IN32;
1547 default:
1548 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1549 }
1550 } else {
1551 return V_028C70_ENDIAN_NONE;
1552 }
1553 }
1554
1555 static uint32_t si_translate_dbformat(enum pipe_format format)
1556 {
1557 switch (format) {
1558 case PIPE_FORMAT_Z16_UNORM:
1559 return V_028040_Z_16;
1560 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1561 case PIPE_FORMAT_X8Z24_UNORM:
1562 case PIPE_FORMAT_Z24X8_UNORM:
1563 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1564 return V_028040_Z_24; /* deprecated on SI */
1565 case PIPE_FORMAT_Z32_FLOAT:
1566 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1567 return V_028040_Z_32_FLOAT;
1568 default:
1569 return V_028040_Z_INVALID;
1570 }
1571 }
1572
1573 /*
1574 * Texture translation
1575 */
1576
1577 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1578 enum pipe_format format,
1579 const struct util_format_description *desc,
1580 int first_non_void)
1581 {
1582 struct si_screen *sscreen = (struct si_screen*)screen;
1583 bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
1584 sscreen->info.drm_minor >= 31) ||
1585 sscreen->info.drm_major == 3;
1586 bool uniform = true;
1587 int i;
1588
1589 /* Colorspace (return non-RGB formats directly). */
1590 switch (desc->colorspace) {
1591 /* Depth stencil formats */
1592 case UTIL_FORMAT_COLORSPACE_ZS:
1593 switch (format) {
1594 case PIPE_FORMAT_Z16_UNORM:
1595 return V_008F14_IMG_DATA_FORMAT_16;
1596 case PIPE_FORMAT_X24S8_UINT:
1597 case PIPE_FORMAT_S8X24_UINT:
1598 /*
1599 * Implemented as an 8_8_8_8 data format to fix texture
1600 * gathers in stencil sampling. This affects at least
1601 * GL45-CTS.texture_cube_map_array.sampling on VI.
1602 */
1603 if (sscreen->info.chip_class <= VI)
1604 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1605
1606 if (format == PIPE_FORMAT_X24S8_UINT)
1607 return V_008F14_IMG_DATA_FORMAT_8_24;
1608 else
1609 return V_008F14_IMG_DATA_FORMAT_24_8;
1610 case PIPE_FORMAT_Z24X8_UNORM:
1611 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1612 return V_008F14_IMG_DATA_FORMAT_8_24;
1613 case PIPE_FORMAT_X8Z24_UNORM:
1614 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1615 return V_008F14_IMG_DATA_FORMAT_24_8;
1616 case PIPE_FORMAT_S8_UINT:
1617 return V_008F14_IMG_DATA_FORMAT_8;
1618 case PIPE_FORMAT_Z32_FLOAT:
1619 return V_008F14_IMG_DATA_FORMAT_32;
1620 case PIPE_FORMAT_X32_S8X24_UINT:
1621 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1622 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1623 default:
1624 goto out_unknown;
1625 }
1626
1627 case UTIL_FORMAT_COLORSPACE_YUV:
1628 goto out_unknown; /* TODO */
1629
1630 case UTIL_FORMAT_COLORSPACE_SRGB:
1631 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1632 goto out_unknown;
1633 break;
1634
1635 default:
1636 break;
1637 }
1638
1639 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1640 if (!enable_compressed_formats)
1641 goto out_unknown;
1642
1643 switch (format) {
1644 case PIPE_FORMAT_RGTC1_SNORM:
1645 case PIPE_FORMAT_LATC1_SNORM:
1646 case PIPE_FORMAT_RGTC1_UNORM:
1647 case PIPE_FORMAT_LATC1_UNORM:
1648 return V_008F14_IMG_DATA_FORMAT_BC4;
1649 case PIPE_FORMAT_RGTC2_SNORM:
1650 case PIPE_FORMAT_LATC2_SNORM:
1651 case PIPE_FORMAT_RGTC2_UNORM:
1652 case PIPE_FORMAT_LATC2_UNORM:
1653 return V_008F14_IMG_DATA_FORMAT_BC5;
1654 default:
1655 goto out_unknown;
1656 }
1657 }
1658
1659 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1660 (sscreen->info.family == CHIP_STONEY ||
1661 sscreen->info.family == CHIP_VEGA10 ||
1662 sscreen->info.family == CHIP_RAVEN)) {
1663 switch (format) {
1664 case PIPE_FORMAT_ETC1_RGB8:
1665 case PIPE_FORMAT_ETC2_RGB8:
1666 case PIPE_FORMAT_ETC2_SRGB8:
1667 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1668 case PIPE_FORMAT_ETC2_RGB8A1:
1669 case PIPE_FORMAT_ETC2_SRGB8A1:
1670 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1671 case PIPE_FORMAT_ETC2_RGBA8:
1672 case PIPE_FORMAT_ETC2_SRGBA8:
1673 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1674 case PIPE_FORMAT_ETC2_R11_UNORM:
1675 case PIPE_FORMAT_ETC2_R11_SNORM:
1676 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1677 case PIPE_FORMAT_ETC2_RG11_UNORM:
1678 case PIPE_FORMAT_ETC2_RG11_SNORM:
1679 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1680 default:
1681 goto out_unknown;
1682 }
1683 }
1684
1685 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1686 if (!enable_compressed_formats)
1687 goto out_unknown;
1688
1689 switch (format) {
1690 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1691 case PIPE_FORMAT_BPTC_SRGBA:
1692 return V_008F14_IMG_DATA_FORMAT_BC7;
1693 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1694 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1695 return V_008F14_IMG_DATA_FORMAT_BC6;
1696 default:
1697 goto out_unknown;
1698 }
1699 }
1700
1701 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1702 switch (format) {
1703 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1704 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1705 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1706 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1707 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1708 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1709 default:
1710 goto out_unknown;
1711 }
1712 }
1713
1714 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1715 if (!enable_compressed_formats)
1716 goto out_unknown;
1717
1718 switch (format) {
1719 case PIPE_FORMAT_DXT1_RGB:
1720 case PIPE_FORMAT_DXT1_RGBA:
1721 case PIPE_FORMAT_DXT1_SRGB:
1722 case PIPE_FORMAT_DXT1_SRGBA:
1723 return V_008F14_IMG_DATA_FORMAT_BC1;
1724 case PIPE_FORMAT_DXT3_RGBA:
1725 case PIPE_FORMAT_DXT3_SRGBA:
1726 return V_008F14_IMG_DATA_FORMAT_BC2;
1727 case PIPE_FORMAT_DXT5_RGBA:
1728 case PIPE_FORMAT_DXT5_SRGBA:
1729 return V_008F14_IMG_DATA_FORMAT_BC3;
1730 default:
1731 goto out_unknown;
1732 }
1733 }
1734
1735 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1736 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1737 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1738 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1739 }
1740
1741 /* R8G8Bx_SNORM - TODO CxV8U8 */
1742
1743 /* hw cannot support mixed formats (except depth/stencil, since only
1744 * depth is read).*/
1745 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1746 goto out_unknown;
1747
1748 /* See whether the components are of the same size. */
1749 for (i = 1; i < desc->nr_channels; i++) {
1750 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1751 }
1752
1753 /* Non-uniform formats. */
1754 if (!uniform) {
1755 switch(desc->nr_channels) {
1756 case 3:
1757 if (desc->channel[0].size == 5 &&
1758 desc->channel[1].size == 6 &&
1759 desc->channel[2].size == 5) {
1760 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1761 }
1762 goto out_unknown;
1763 case 4:
1764 if (desc->channel[0].size == 5 &&
1765 desc->channel[1].size == 5 &&
1766 desc->channel[2].size == 5 &&
1767 desc->channel[3].size == 1) {
1768 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1769 }
1770 if (desc->channel[0].size == 1 &&
1771 desc->channel[1].size == 5 &&
1772 desc->channel[2].size == 5 &&
1773 desc->channel[3].size == 5) {
1774 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1775 }
1776 if (desc->channel[0].size == 10 &&
1777 desc->channel[1].size == 10 &&
1778 desc->channel[2].size == 10 &&
1779 desc->channel[3].size == 2) {
1780 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1781 }
1782 goto out_unknown;
1783 }
1784 goto out_unknown;
1785 }
1786
1787 if (first_non_void < 0 || first_non_void > 3)
1788 goto out_unknown;
1789
1790 /* uniform formats */
1791 switch (desc->channel[first_non_void].size) {
1792 case 4:
1793 switch (desc->nr_channels) {
1794 #if 0 /* Not supported for render targets */
1795 case 2:
1796 return V_008F14_IMG_DATA_FORMAT_4_4;
1797 #endif
1798 case 4:
1799 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1800 }
1801 break;
1802 case 8:
1803 switch (desc->nr_channels) {
1804 case 1:
1805 return V_008F14_IMG_DATA_FORMAT_8;
1806 case 2:
1807 return V_008F14_IMG_DATA_FORMAT_8_8;
1808 case 4:
1809 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1810 }
1811 break;
1812 case 16:
1813 switch (desc->nr_channels) {
1814 case 1:
1815 return V_008F14_IMG_DATA_FORMAT_16;
1816 case 2:
1817 return V_008F14_IMG_DATA_FORMAT_16_16;
1818 case 4:
1819 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1820 }
1821 break;
1822 case 32:
1823 switch (desc->nr_channels) {
1824 case 1:
1825 return V_008F14_IMG_DATA_FORMAT_32;
1826 case 2:
1827 return V_008F14_IMG_DATA_FORMAT_32_32;
1828 #if 0 /* Not supported for render targets */
1829 case 3:
1830 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1831 #endif
1832 case 4:
1833 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1834 }
1835 }
1836
1837 out_unknown:
1838 return ~0;
1839 }
1840
1841 static unsigned si_tex_wrap(unsigned wrap)
1842 {
1843 switch (wrap) {
1844 default:
1845 case PIPE_TEX_WRAP_REPEAT:
1846 return V_008F30_SQ_TEX_WRAP;
1847 case PIPE_TEX_WRAP_CLAMP:
1848 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1849 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1850 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1851 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1852 return V_008F30_SQ_TEX_CLAMP_BORDER;
1853 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1854 return V_008F30_SQ_TEX_MIRROR;
1855 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1856 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1857 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1858 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1859 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1860 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1861 }
1862 }
1863
1864 static unsigned si_tex_mipfilter(unsigned filter)
1865 {
1866 switch (filter) {
1867 case PIPE_TEX_MIPFILTER_NEAREST:
1868 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1869 case PIPE_TEX_MIPFILTER_LINEAR:
1870 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1871 default:
1872 case PIPE_TEX_MIPFILTER_NONE:
1873 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1874 }
1875 }
1876
1877 static unsigned si_tex_compare(unsigned compare)
1878 {
1879 switch (compare) {
1880 default:
1881 case PIPE_FUNC_NEVER:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1883 case PIPE_FUNC_LESS:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1885 case PIPE_FUNC_EQUAL:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1887 case PIPE_FUNC_LEQUAL:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1889 case PIPE_FUNC_GREATER:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1891 case PIPE_FUNC_NOTEQUAL:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1893 case PIPE_FUNC_GEQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1895 case PIPE_FUNC_ALWAYS:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1897 }
1898 }
1899
1900 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1901 unsigned view_target, unsigned nr_samples)
1902 {
1903 unsigned res_target = rtex->resource.b.b.target;
1904
1905 if (view_target == PIPE_TEXTURE_CUBE ||
1906 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1907 res_target = view_target;
1908 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1909 else if (res_target == PIPE_TEXTURE_CUBE ||
1910 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1911 res_target = PIPE_TEXTURE_2D_ARRAY;
1912
1913 /* GFX9 allocates 1D textures as 2D. */
1914 if ((res_target == PIPE_TEXTURE_1D ||
1915 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1916 sscreen->info.chip_class >= GFX9 &&
1917 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1918 if (res_target == PIPE_TEXTURE_1D)
1919 res_target = PIPE_TEXTURE_2D;
1920 else
1921 res_target = PIPE_TEXTURE_2D_ARRAY;
1922 }
1923
1924 switch (res_target) {
1925 default:
1926 case PIPE_TEXTURE_1D:
1927 return V_008F1C_SQ_RSRC_IMG_1D;
1928 case PIPE_TEXTURE_1D_ARRAY:
1929 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1930 case PIPE_TEXTURE_2D:
1931 case PIPE_TEXTURE_RECT:
1932 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1933 V_008F1C_SQ_RSRC_IMG_2D;
1934 case PIPE_TEXTURE_2D_ARRAY:
1935 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1936 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1937 case PIPE_TEXTURE_3D:
1938 return V_008F1C_SQ_RSRC_IMG_3D;
1939 case PIPE_TEXTURE_CUBE:
1940 case PIPE_TEXTURE_CUBE_ARRAY:
1941 return V_008F1C_SQ_RSRC_IMG_CUBE;
1942 }
1943 }
1944
1945 /*
1946 * Format support testing
1947 */
1948
1949 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1950 {
1951 const struct util_format_description *desc = util_format_description(format);
1952 if (!desc)
1953 return false;
1954
1955 return si_translate_texformat(screen, format, desc,
1956 util_format_get_first_non_void_channel(format)) != ~0U;
1957 }
1958
1959 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1960 const struct util_format_description *desc,
1961 int first_non_void)
1962 {
1963 int i;
1964
1965 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1966 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1967
1968 assert(first_non_void >= 0);
1969
1970 if (desc->nr_channels == 4 &&
1971 desc->channel[0].size == 10 &&
1972 desc->channel[1].size == 10 &&
1973 desc->channel[2].size == 10 &&
1974 desc->channel[3].size == 2)
1975 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1976
1977 /* See whether the components are of the same size. */
1978 for (i = 0; i < desc->nr_channels; i++) {
1979 if (desc->channel[first_non_void].size != desc->channel[i].size)
1980 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1981 }
1982
1983 switch (desc->channel[first_non_void].size) {
1984 case 8:
1985 switch (desc->nr_channels) {
1986 case 1:
1987 case 3: /* 3 loads */
1988 return V_008F0C_BUF_DATA_FORMAT_8;
1989 case 2:
1990 return V_008F0C_BUF_DATA_FORMAT_8_8;
1991 case 4:
1992 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1993 }
1994 break;
1995 case 16:
1996 switch (desc->nr_channels) {
1997 case 1:
1998 case 3: /* 3 loads */
1999 return V_008F0C_BUF_DATA_FORMAT_16;
2000 case 2:
2001 return V_008F0C_BUF_DATA_FORMAT_16_16;
2002 case 4:
2003 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2004 }
2005 break;
2006 case 32:
2007 switch (desc->nr_channels) {
2008 case 1:
2009 return V_008F0C_BUF_DATA_FORMAT_32;
2010 case 2:
2011 return V_008F0C_BUF_DATA_FORMAT_32_32;
2012 case 3:
2013 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2014 case 4:
2015 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2016 }
2017 break;
2018 case 64:
2019 /* Legacy double formats. */
2020 switch (desc->nr_channels) {
2021 case 1: /* 1 load */
2022 return V_008F0C_BUF_DATA_FORMAT_32_32;
2023 case 2: /* 1 load */
2024 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2025 case 3: /* 3 loads */
2026 return V_008F0C_BUF_DATA_FORMAT_32_32;
2027 case 4: /* 2 loads */
2028 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2029 }
2030 break;
2031 }
2032
2033 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2034 }
2035
2036 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2037 const struct util_format_description *desc,
2038 int first_non_void)
2039 {
2040 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2041 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2042
2043 assert(first_non_void >= 0);
2044
2045 switch (desc->channel[first_non_void].type) {
2046 case UTIL_FORMAT_TYPE_SIGNED:
2047 case UTIL_FORMAT_TYPE_FIXED:
2048 if (desc->channel[first_non_void].size >= 32 ||
2049 desc->channel[first_non_void].pure_integer)
2050 return V_008F0C_BUF_NUM_FORMAT_SINT;
2051 else if (desc->channel[first_non_void].normalized)
2052 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2053 else
2054 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2055 break;
2056 case UTIL_FORMAT_TYPE_UNSIGNED:
2057 if (desc->channel[first_non_void].size >= 32 ||
2058 desc->channel[first_non_void].pure_integer)
2059 return V_008F0C_BUF_NUM_FORMAT_UINT;
2060 else if (desc->channel[first_non_void].normalized)
2061 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2062 else
2063 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2064 break;
2065 case UTIL_FORMAT_TYPE_FLOAT:
2066 default:
2067 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2068 }
2069 }
2070
2071 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2072 enum pipe_format format,
2073 unsigned usage)
2074 {
2075 const struct util_format_description *desc;
2076 int first_non_void;
2077 unsigned data_format;
2078
2079 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2080 PIPE_BIND_SAMPLER_VIEW |
2081 PIPE_BIND_VERTEX_BUFFER)) == 0);
2082
2083 desc = util_format_description(format);
2084 if (!desc)
2085 return 0;
2086
2087 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2088 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2089 * for read-only access (with caveats surrounding bounds checks), but
2090 * obviously fails for write access which we have to implement for
2091 * shader images. Luckily, OpenGL doesn't expect this to be supported
2092 * anyway, and so the only impact is on PBO uploads / downloads, which
2093 * shouldn't be expected to be fast for GL_RGB anyway.
2094 */
2095 if (desc->block.bits == 3 * 8 ||
2096 desc->block.bits == 3 * 16) {
2097 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2098 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2099 if (!usage)
2100 return 0;
2101 }
2102 }
2103
2104 first_non_void = util_format_get_first_non_void_channel(format);
2105 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2106 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2107 return 0;
2108
2109 return usage;
2110 }
2111
2112 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2113 {
2114 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2115 si_translate_colorswap(format, false) != ~0U;
2116 }
2117
2118 static bool si_is_zs_format_supported(enum pipe_format format)
2119 {
2120 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2121 }
2122
2123 static boolean si_is_format_supported(struct pipe_screen *screen,
2124 enum pipe_format format,
2125 enum pipe_texture_target target,
2126 unsigned sample_count,
2127 unsigned usage)
2128 {
2129 unsigned retval = 0;
2130
2131 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2132 PRINT_ERR("r600: unsupported texture type %d\n", target);
2133 return false;
2134 }
2135
2136 if (!util_format_is_supported(format, usage))
2137 return false;
2138
2139 if (sample_count > 1) {
2140 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2141 return false;
2142
2143 if (usage & PIPE_BIND_SHADER_IMAGE)
2144 return false;
2145
2146 switch (sample_count) {
2147 case 2:
2148 case 4:
2149 case 8:
2150 break;
2151 case 16:
2152 if (format == PIPE_FORMAT_NONE)
2153 return true;
2154 else
2155 return false;
2156 default:
2157 return false;
2158 }
2159 }
2160
2161 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2162 PIPE_BIND_SHADER_IMAGE)) {
2163 if (target == PIPE_BUFFER) {
2164 retval |= si_is_vertex_format_supported(
2165 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2166 PIPE_BIND_SHADER_IMAGE));
2167 } else {
2168 if (si_is_sampler_format_supported(screen, format))
2169 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2170 PIPE_BIND_SHADER_IMAGE);
2171 }
2172 }
2173
2174 if ((usage & (PIPE_BIND_RENDER_TARGET |
2175 PIPE_BIND_DISPLAY_TARGET |
2176 PIPE_BIND_SCANOUT |
2177 PIPE_BIND_SHARED |
2178 PIPE_BIND_BLENDABLE)) &&
2179 si_is_colorbuffer_format_supported(format)) {
2180 retval |= usage &
2181 (PIPE_BIND_RENDER_TARGET |
2182 PIPE_BIND_DISPLAY_TARGET |
2183 PIPE_BIND_SCANOUT |
2184 PIPE_BIND_SHARED);
2185 if (!util_format_is_pure_integer(format) &&
2186 !util_format_is_depth_or_stencil(format))
2187 retval |= usage & PIPE_BIND_BLENDABLE;
2188 }
2189
2190 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2191 si_is_zs_format_supported(format)) {
2192 retval |= PIPE_BIND_DEPTH_STENCIL;
2193 }
2194
2195 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2196 retval |= si_is_vertex_format_supported(screen, format,
2197 PIPE_BIND_VERTEX_BUFFER);
2198 }
2199
2200 if ((usage & PIPE_BIND_LINEAR) &&
2201 !util_format_is_compressed(format) &&
2202 !(usage & PIPE_BIND_DEPTH_STENCIL))
2203 retval |= PIPE_BIND_LINEAR;
2204
2205 return retval == usage;
2206 }
2207
2208 /*
2209 * framebuffer handling
2210 */
2211
2212 static void si_choose_spi_color_formats(struct r600_surface *surf,
2213 unsigned format, unsigned swap,
2214 unsigned ntype, bool is_depth)
2215 {
2216 /* Alpha is needed for alpha-to-coverage.
2217 * Blending may be with or without alpha.
2218 */
2219 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2220 unsigned alpha = 0; /* exports alpha, but may not support blending */
2221 unsigned blend = 0; /* supports blending, but may not export alpha */
2222 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2223
2224 /* Choose the SPI color formats. These are required values for RB+.
2225 * Other chips have multiple choices, though they are not necessarily better.
2226 */
2227 switch (format) {
2228 case V_028C70_COLOR_5_6_5:
2229 case V_028C70_COLOR_1_5_5_5:
2230 case V_028C70_COLOR_5_5_5_1:
2231 case V_028C70_COLOR_4_4_4_4:
2232 case V_028C70_COLOR_10_11_11:
2233 case V_028C70_COLOR_11_11_10:
2234 case V_028C70_COLOR_8:
2235 case V_028C70_COLOR_8_8:
2236 case V_028C70_COLOR_8_8_8_8:
2237 case V_028C70_COLOR_10_10_10_2:
2238 case V_028C70_COLOR_2_10_10_10:
2239 if (ntype == V_028C70_NUMBER_UINT)
2240 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2241 else if (ntype == V_028C70_NUMBER_SINT)
2242 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2243 else
2244 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2245 break;
2246
2247 case V_028C70_COLOR_16:
2248 case V_028C70_COLOR_16_16:
2249 case V_028C70_COLOR_16_16_16_16:
2250 if (ntype == V_028C70_NUMBER_UNORM ||
2251 ntype == V_028C70_NUMBER_SNORM) {
2252 /* UNORM16 and SNORM16 don't support blending */
2253 if (ntype == V_028C70_NUMBER_UNORM)
2254 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2255 else
2256 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2257
2258 /* Use 32 bits per channel for blending. */
2259 if (format == V_028C70_COLOR_16) {
2260 if (swap == V_028C70_SWAP_STD) { /* R */
2261 blend = V_028714_SPI_SHADER_32_R;
2262 blend_alpha = V_028714_SPI_SHADER_32_AR;
2263 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2264 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2265 else
2266 assert(0);
2267 } else if (format == V_028C70_COLOR_16_16) {
2268 if (swap == V_028C70_SWAP_STD) { /* RG */
2269 blend = V_028714_SPI_SHADER_32_GR;
2270 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2271 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2272 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2273 else
2274 assert(0);
2275 } else /* 16_16_16_16 */
2276 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2277 } else if (ntype == V_028C70_NUMBER_UINT)
2278 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2279 else if (ntype == V_028C70_NUMBER_SINT)
2280 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2281 else if (ntype == V_028C70_NUMBER_FLOAT)
2282 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2283 else
2284 assert(0);
2285 break;
2286
2287 case V_028C70_COLOR_32:
2288 if (swap == V_028C70_SWAP_STD) { /* R */
2289 blend = normal = V_028714_SPI_SHADER_32_R;
2290 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2291 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2292 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2293 else
2294 assert(0);
2295 break;
2296
2297 case V_028C70_COLOR_32_32:
2298 if (swap == V_028C70_SWAP_STD) { /* RG */
2299 blend = normal = V_028714_SPI_SHADER_32_GR;
2300 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2301 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2302 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2303 else
2304 assert(0);
2305 break;
2306
2307 case V_028C70_COLOR_32_32_32_32:
2308 case V_028C70_COLOR_8_24:
2309 case V_028C70_COLOR_24_8:
2310 case V_028C70_COLOR_X24_8_32_FLOAT:
2311 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2312 break;
2313
2314 default:
2315 assert(0);
2316 return;
2317 }
2318
2319 /* The DB->CB copy needs 32_ABGR. */
2320 if (is_depth)
2321 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2322
2323 surf->spi_shader_col_format = normal;
2324 surf->spi_shader_col_format_alpha = alpha;
2325 surf->spi_shader_col_format_blend = blend;
2326 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2327 }
2328
2329 static void si_initialize_color_surface(struct si_context *sctx,
2330 struct r600_surface *surf)
2331 {
2332 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2333 unsigned color_info, color_attrib;
2334 unsigned format, swap, ntype, endian;
2335 const struct util_format_description *desc;
2336 int firstchan;
2337 unsigned blend_clamp = 0, blend_bypass = 0;
2338
2339 desc = util_format_description(surf->base.format);
2340 for (firstchan = 0; firstchan < 4; firstchan++) {
2341 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2342 break;
2343 }
2344 }
2345 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2346 ntype = V_028C70_NUMBER_FLOAT;
2347 } else {
2348 ntype = V_028C70_NUMBER_UNORM;
2349 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2350 ntype = V_028C70_NUMBER_SRGB;
2351 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2352 if (desc->channel[firstchan].pure_integer) {
2353 ntype = V_028C70_NUMBER_SINT;
2354 } else {
2355 assert(desc->channel[firstchan].normalized);
2356 ntype = V_028C70_NUMBER_SNORM;
2357 }
2358 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2359 if (desc->channel[firstchan].pure_integer) {
2360 ntype = V_028C70_NUMBER_UINT;
2361 } else {
2362 assert(desc->channel[firstchan].normalized);
2363 ntype = V_028C70_NUMBER_UNORM;
2364 }
2365 }
2366 }
2367
2368 format = si_translate_colorformat(surf->base.format);
2369 if (format == V_028C70_COLOR_INVALID) {
2370 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2371 }
2372 assert(format != V_028C70_COLOR_INVALID);
2373 swap = si_translate_colorswap(surf->base.format, false);
2374 endian = si_colorformat_endian_swap(format);
2375
2376 /* blend clamp should be set for all NORM/SRGB types */
2377 if (ntype == V_028C70_NUMBER_UNORM ||
2378 ntype == V_028C70_NUMBER_SNORM ||
2379 ntype == V_028C70_NUMBER_SRGB)
2380 blend_clamp = 1;
2381
2382 /* set blend bypass according to docs if SINT/UINT or
2383 8/24 COLOR variants */
2384 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2385 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2386 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2387 blend_clamp = 0;
2388 blend_bypass = 1;
2389 }
2390
2391 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2392 if (format == V_028C70_COLOR_8 ||
2393 format == V_028C70_COLOR_8_8 ||
2394 format == V_028C70_COLOR_8_8_8_8)
2395 surf->color_is_int8 = true;
2396 else if (format == V_028C70_COLOR_10_10_10_2 ||
2397 format == V_028C70_COLOR_2_10_10_10)
2398 surf->color_is_int10 = true;
2399 }
2400
2401 color_info = S_028C70_FORMAT(format) |
2402 S_028C70_COMP_SWAP(swap) |
2403 S_028C70_BLEND_CLAMP(blend_clamp) |
2404 S_028C70_BLEND_BYPASS(blend_bypass) |
2405 S_028C70_SIMPLE_FLOAT(1) |
2406 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2407 ntype != V_028C70_NUMBER_SNORM &&
2408 ntype != V_028C70_NUMBER_SRGB &&
2409 format != V_028C70_COLOR_8_24 &&
2410 format != V_028C70_COLOR_24_8) |
2411 S_028C70_NUMBER_TYPE(ntype) |
2412 S_028C70_ENDIAN(endian);
2413
2414 /* Intensity is implemented as Red, so treat it that way. */
2415 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2416 util_format_is_intensity(surf->base.format));
2417
2418 if (rtex->resource.b.b.nr_samples > 1) {
2419 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2420
2421 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2422 S_028C74_NUM_FRAGMENTS(log_samples);
2423
2424 if (rtex->fmask.size) {
2425 color_info |= S_028C70_COMPRESSION(1);
2426 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2427
2428 if (sctx->chip_class == SI) {
2429 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2430 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2431 }
2432 }
2433 }
2434
2435 if (sctx->chip_class >= VI) {
2436 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2437 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2438
2439 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2440 64 for APU because all of our APUs to date use DIMMs which have
2441 a request granularity size of 64B while all other chips have a
2442 32B request size */
2443 if (!sctx->screen->info.has_dedicated_vram)
2444 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2445
2446 if (rtex->resource.b.b.nr_samples > 1) {
2447 if (rtex->surface.bpe == 1)
2448 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2449 else if (rtex->surface.bpe == 2)
2450 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2451 }
2452
2453 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2454 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2455 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2456 }
2457
2458 /* This must be set for fast clear to work without FMASK. */
2459 if (!rtex->fmask.size && sctx->chip_class == SI) {
2460 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2461 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2462 }
2463
2464 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2465 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2466
2467 if (sctx->chip_class >= GFX9) {
2468 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2469
2470 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2471 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2472 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2473 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2474 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2475 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2476 }
2477
2478 surf->cb_color_view = color_view;
2479 surf->cb_color_info = color_info;
2480 surf->cb_color_attrib = color_attrib;
2481
2482 /* Determine pixel shader export format */
2483 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2484
2485 surf->color_initialized = true;
2486 }
2487
2488 static void si_init_depth_surface(struct si_context *sctx,
2489 struct r600_surface *surf)
2490 {
2491 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2492 unsigned level = surf->base.u.tex.level;
2493 unsigned format, stencil_format;
2494 uint32_t z_info, s_info;
2495
2496 format = si_translate_dbformat(rtex->db_render_format);
2497 stencil_format = rtex->surface.has_stencil ?
2498 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2499
2500 assert(format != V_028040_Z_INVALID);
2501 if (format == V_028040_Z_INVALID)
2502 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2503
2504 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2505 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2506 surf->db_htile_data_base = 0;
2507 surf->db_htile_surface = 0;
2508
2509 if (sctx->chip_class >= GFX9) {
2510 assert(rtex->surface.u.gfx9.surf_offset == 0);
2511 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2512 surf->db_stencil_base = (rtex->resource.gpu_address +
2513 rtex->surface.u.gfx9.stencil_offset) >> 8;
2514 z_info = S_028038_FORMAT(format) |
2515 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2516 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2517 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2518 s_info = S_02803C_FORMAT(stencil_format) |
2519 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2520 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2521 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2522 surf->db_depth_view |= S_028008_MIPID(level);
2523 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2524 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2525
2526 if (si_htile_enabled(rtex, level)) {
2527 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2528 S_028038_ALLOW_EXPCLEAR(1);
2529
2530 if (rtex->tc_compatible_htile) {
2531 unsigned max_zplanes = 4;
2532
2533 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2534 rtex->resource.b.b.nr_samples > 1)
2535 max_zplanes = 2;
2536
2537 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2538 S_028038_ITERATE_FLUSH(1);
2539 s_info |= S_02803C_ITERATE_FLUSH(1);
2540 }
2541
2542 if (rtex->surface.has_stencil) {
2543 /* Stencil buffer workaround ported from the SI-CI-VI code.
2544 * See that for explanation.
2545 */
2546 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2547 } else {
2548 /* Use all HTILE for depth if there's no stencil. */
2549 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2550 }
2551
2552 surf->db_htile_data_base = (rtex->resource.gpu_address +
2553 rtex->htile_offset) >> 8;
2554 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2555 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2556 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2557 }
2558 } else {
2559 /* SI-CI-VI */
2560 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2561
2562 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2563
2564 surf->db_depth_base = (rtex->resource.gpu_address +
2565 rtex->surface.u.legacy.level[level].offset) >> 8;
2566 surf->db_stencil_base = (rtex->resource.gpu_address +
2567 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2568
2569 z_info = S_028040_FORMAT(format) |
2570 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2571 s_info = S_028044_FORMAT(stencil_format);
2572 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2573
2574 if (sctx->chip_class >= CIK) {
2575 struct radeon_info *info = &sctx->screen->info;
2576 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2577 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2578 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2579 unsigned tile_mode = info->si_tile_mode_array[index];
2580 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2581 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2582
2583 surf->db_depth_info |=
2584 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2585 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2586 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2587 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2588 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2589 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2590 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2591 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2592 } else {
2593 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2594 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2595 tile_mode_index = si_tile_mode_index(rtex, level, true);
2596 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2597 }
2598
2599 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2600 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2601 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2602 levelinfo->nblk_y) / 64 - 1);
2603
2604 if (si_htile_enabled(rtex, level)) {
2605 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2606 S_028040_ALLOW_EXPCLEAR(1);
2607
2608 if (rtex->surface.has_stencil) {
2609 /* Workaround: For a not yet understood reason, the
2610 * combination of MSAA, fast stencil clear and stencil
2611 * decompress messes with subsequent stencil buffer
2612 * uses. Problem was reproduced on Verde, Bonaire,
2613 * Tonga, and Carrizo.
2614 *
2615 * Disabling EXPCLEAR works around the problem.
2616 *
2617 * Check piglit's arb_texture_multisample-stencil-clear
2618 * test if you want to try changing this.
2619 */
2620 if (rtex->resource.b.b.nr_samples <= 1)
2621 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2622 } else if (!rtex->tc_compatible_htile) {
2623 /* Use all of the htile_buffer for depth if there's no stencil.
2624 * This must not be set when TC-compatible HTILE is enabled
2625 * due to a hw bug.
2626 */
2627 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2628 }
2629
2630 surf->db_htile_data_base = (rtex->resource.gpu_address +
2631 rtex->htile_offset) >> 8;
2632 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2633
2634 if (rtex->tc_compatible_htile) {
2635 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2636
2637 if (rtex->resource.b.b.nr_samples <= 1)
2638 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2639 else if (rtex->resource.b.b.nr_samples <= 4)
2640 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2641 else
2642 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2643 }
2644 }
2645 }
2646
2647 surf->db_z_info = z_info;
2648 surf->db_stencil_info = s_info;
2649
2650 surf->depth_initialized = true;
2651 }
2652
2653 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2654 {
2655 if (sctx->decompression_enabled)
2656 return;
2657
2658 if (sctx->framebuffer.state.zsbuf) {
2659 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2660 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2661
2662 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2663
2664 if (rtex->surface.has_stencil)
2665 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2666 }
2667
2668 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2669 while (compressed_cb_mask) {
2670 unsigned i = u_bit_scan(&compressed_cb_mask);
2671 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2672 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2673
2674 if (rtex->fmask.size)
2675 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2676 if (rtex->dcc_gather_statistics)
2677 rtex->separate_dcc_dirty = true;
2678 }
2679 }
2680
2681 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2682 {
2683 for (int i = 0; i < state->nr_cbufs; ++i) {
2684 struct r600_surface *surf = NULL;
2685 struct r600_texture *rtex;
2686
2687 if (!state->cbufs[i])
2688 continue;
2689 surf = (struct r600_surface*)state->cbufs[i];
2690 rtex = (struct r600_texture*)surf->base.texture;
2691
2692 p_atomic_dec(&rtex->framebuffers_bound);
2693 }
2694 }
2695
2696 static void si_set_framebuffer_state(struct pipe_context *ctx,
2697 const struct pipe_framebuffer_state *state)
2698 {
2699 struct si_context *sctx = (struct si_context *)ctx;
2700 struct pipe_constant_buffer constbuf = {0};
2701 struct r600_surface *surf = NULL;
2702 struct r600_texture *rtex;
2703 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2704 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2705 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2706 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2707 bool old_has_stencil =
2708 old_has_zsbuf &&
2709 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2710 bool unbound = false;
2711 int i;
2712
2713 si_update_fb_dirtiness_after_rendering(sctx);
2714
2715 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2716 if (!sctx->framebuffer.state.cbufs[i])
2717 continue;
2718
2719 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2720 if (rtex->dcc_gather_statistics)
2721 vi_separate_dcc_stop_query(sctx, rtex);
2722 }
2723
2724 /* Disable DCC if the formats are incompatible. */
2725 for (i = 0; i < state->nr_cbufs; i++) {
2726 if (!state->cbufs[i])
2727 continue;
2728
2729 surf = (struct r600_surface*)state->cbufs[i];
2730 rtex = (struct r600_texture*)surf->base.texture;
2731
2732 if (!surf->dcc_incompatible)
2733 continue;
2734
2735 /* Since the DCC decompression calls back into set_framebuffer-
2736 * _state, we need to unbind the framebuffer, so that
2737 * vi_separate_dcc_stop_query isn't called twice with the same
2738 * color buffer.
2739 */
2740 if (!unbound) {
2741 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2742 unbound = true;
2743 }
2744
2745 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2746 if (!si_texture_disable_dcc(sctx, rtex))
2747 si_decompress_dcc(sctx, rtex);
2748
2749 surf->dcc_incompatible = false;
2750 }
2751
2752 /* Only flush TC when changing the framebuffer state, because
2753 * the only client not using TC that can change textures is
2754 * the framebuffer.
2755 *
2756 * Wait for compute shaders because of possible transitions:
2757 * - FB write -> shader read
2758 * - shader write -> FB read
2759 *
2760 * DB caches are flushed on demand (using si_decompress_textures).
2761 *
2762 * When MSAA is enabled, CB and TC caches are flushed on demand
2763 * (after FMASK decompression). Shader write -> FB read transitions
2764 * cannot happen for MSAA textures, because MSAA shader images are
2765 * not supported.
2766 *
2767 * Only flush and wait for CB if there is actually a bound color buffer.
2768 */
2769 if (sctx->framebuffer.uncompressed_cb_mask)
2770 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2771 sctx->framebuffer.CB_has_shader_readable_metadata);
2772
2773 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2774
2775 /* u_blitter doesn't invoke depth decompression when it does multiple
2776 * blits in a row, but the only case when it matters for DB is when
2777 * doing generate_mipmap. So here we flush DB manually between
2778 * individual generate_mipmap blits.
2779 * Note that lower mipmap levels aren't compressed.
2780 */
2781 if (sctx->generate_mipmap_for_depth) {
2782 si_make_DB_shader_coherent(sctx, 1, false,
2783 sctx->framebuffer.DB_has_shader_readable_metadata);
2784 } else if (sctx->chip_class == GFX9) {
2785 /* It appears that DB metadata "leaks" in a sequence of:
2786 * - depth clear
2787 * - DCC decompress for shader image writes (with DB disabled)
2788 * - render with DEPTH_BEFORE_SHADER=1
2789 * Flushing DB metadata works around the problem.
2790 */
2791 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2792 }
2793
2794 /* Take the maximum of the old and new count. If the new count is lower,
2795 * dirtying is needed to disable the unbound colorbuffers.
2796 */
2797 sctx->framebuffer.dirty_cbufs |=
2798 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2799 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2800
2801 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2802 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2803
2804 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2805 sctx->framebuffer.spi_shader_col_format = 0;
2806 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2807 sctx->framebuffer.spi_shader_col_format_blend = 0;
2808 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2809 sctx->framebuffer.color_is_int8 = 0;
2810 sctx->framebuffer.color_is_int10 = 0;
2811
2812 sctx->framebuffer.compressed_cb_mask = 0;
2813 sctx->framebuffer.uncompressed_cb_mask = 0;
2814 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2815 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2816 sctx->framebuffer.any_dst_linear = false;
2817 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2818 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2819
2820 for (i = 0; i < state->nr_cbufs; i++) {
2821 if (!state->cbufs[i])
2822 continue;
2823
2824 surf = (struct r600_surface*)state->cbufs[i];
2825 rtex = (struct r600_texture*)surf->base.texture;
2826
2827 if (!surf->color_initialized) {
2828 si_initialize_color_surface(sctx, surf);
2829 }
2830
2831 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2832 sctx->framebuffer.spi_shader_col_format |=
2833 surf->spi_shader_col_format << (i * 4);
2834 sctx->framebuffer.spi_shader_col_format_alpha |=
2835 surf->spi_shader_col_format_alpha << (i * 4);
2836 sctx->framebuffer.spi_shader_col_format_blend |=
2837 surf->spi_shader_col_format_blend << (i * 4);
2838 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2839 surf->spi_shader_col_format_blend_alpha << (i * 4);
2840
2841 if (surf->color_is_int8)
2842 sctx->framebuffer.color_is_int8 |= 1 << i;
2843 if (surf->color_is_int10)
2844 sctx->framebuffer.color_is_int10 |= 1 << i;
2845
2846 if (rtex->fmask.size)
2847 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2848 else
2849 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2850
2851 if (rtex->surface.is_linear)
2852 sctx->framebuffer.any_dst_linear = true;
2853
2854 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2855 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2856
2857 si_context_add_resource_size(sctx, surf->base.texture);
2858
2859 p_atomic_inc(&rtex->framebuffers_bound);
2860
2861 if (rtex->dcc_gather_statistics) {
2862 /* Dirty tracking must be enabled for DCC usage analysis. */
2863 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2864 vi_separate_dcc_start_query(sctx, rtex);
2865 }
2866 }
2867
2868 struct r600_texture *zstex = NULL;
2869
2870 if (state->zsbuf) {
2871 surf = (struct r600_surface*)state->zsbuf;
2872 zstex = (struct r600_texture*)surf->base.texture;
2873
2874 if (!surf->depth_initialized) {
2875 si_init_depth_surface(sctx, surf);
2876 }
2877
2878 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2879 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2880
2881 si_context_add_resource_size(sctx, surf->base.texture);
2882 }
2883
2884 si_update_ps_colorbuf0_slot(sctx);
2885 si_update_poly_offset_state(sctx);
2886 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2887 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2888
2889 if (sctx->screen->dpbb_allowed)
2890 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2891
2892 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2893 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2894
2895 if (sctx->screen->has_out_of_order_rast &&
2896 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2897 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2898 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2899 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2900
2901 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2902 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2903 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2904
2905 /* Set sample locations as fragment shader constants. */
2906 switch (sctx->framebuffer.nr_samples) {
2907 case 1:
2908 constbuf.user_buffer = sctx->sample_locations_1x;
2909 break;
2910 case 2:
2911 constbuf.user_buffer = sctx->sample_locations_2x;
2912 break;
2913 case 4:
2914 constbuf.user_buffer = sctx->sample_locations_4x;
2915 break;
2916 case 8:
2917 constbuf.user_buffer = sctx->sample_locations_8x;
2918 break;
2919 case 16:
2920 constbuf.user_buffer = sctx->sample_locations_16x;
2921 break;
2922 default:
2923 PRINT_ERR("Requested an invalid number of samples %i.\n",
2924 sctx->framebuffer.nr_samples);
2925 assert(0);
2926 }
2927 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2928 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2929
2930 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2931 }
2932
2933 sctx->do_update_shaders = true;
2934
2935 if (!sctx->decompression_enabled) {
2936 /* Prevent textures decompression when the framebuffer state
2937 * changes come from the decompression passes themselves.
2938 */
2939 sctx->need_check_render_feedback = true;
2940 }
2941 }
2942
2943 static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *atom)
2944 {
2945 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2946 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2947 unsigned i, nr_cbufs = state->nr_cbufs;
2948 struct r600_texture *tex = NULL;
2949 struct r600_surface *cb = NULL;
2950 unsigned cb_color_info = 0;
2951
2952 /* Colorbuffers. */
2953 for (i = 0; i < nr_cbufs; i++) {
2954 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2955 unsigned cb_color_attrib;
2956
2957 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2958 continue;
2959
2960 cb = (struct r600_surface*)state->cbufs[i];
2961 if (!cb) {
2962 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2963 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2964 continue;
2965 }
2966
2967 tex = (struct r600_texture *)cb->base.texture;
2968 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2969 &tex->resource, RADEON_USAGE_READWRITE,
2970 tex->resource.b.b.nr_samples > 1 ?
2971 RADEON_PRIO_COLOR_BUFFER_MSAA :
2972 RADEON_PRIO_COLOR_BUFFER);
2973
2974 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2975 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2976 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2977 RADEON_PRIO_CMASK);
2978 }
2979
2980 if (tex->dcc_separate_buffer)
2981 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2982 tex->dcc_separate_buffer,
2983 RADEON_USAGE_READWRITE,
2984 RADEON_PRIO_DCC);
2985
2986 /* Compute mutable surface parameters. */
2987 cb_color_base = tex->resource.gpu_address >> 8;
2988 cb_color_fmask = 0;
2989 cb_color_cmask = tex->cmask.base_address_reg;
2990 cb_dcc_base = 0;
2991 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2992 cb_color_attrib = cb->cb_color_attrib;
2993
2994 if (cb->base.u.tex.level > 0)
2995 cb_color_info &= C_028C70_FAST_CLEAR;
2996
2997 if (tex->fmask.size) {
2998 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2999 cb_color_fmask |= tex->fmask.tile_swizzle;
3000 }
3001
3002 /* Set up DCC. */
3003 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3004 bool is_msaa_resolve_dst = state->cbufs[0] &&
3005 state->cbufs[0]->texture->nr_samples > 1 &&
3006 state->cbufs[1] == &cb->base &&
3007 state->cbufs[1]->texture->nr_samples <= 1;
3008
3009 if (!is_msaa_resolve_dst)
3010 cb_color_info |= S_028C70_DCC_ENABLE(1);
3011
3012 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3013 tex->dcc_offset) >> 8;
3014 cb_dcc_base |= tex->surface.tile_swizzle;
3015 }
3016
3017 if (sctx->chip_class >= GFX9) {
3018 struct gfx9_surf_meta_flags meta;
3019
3020 if (tex->dcc_offset)
3021 meta = tex->surface.u.gfx9.dcc;
3022 else
3023 meta = tex->surface.u.gfx9.cmask;
3024
3025 /* Set mutable surface parameters. */
3026 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3027 cb_color_base |= tex->surface.tile_swizzle;
3028 if (!tex->fmask.size)
3029 cb_color_fmask = cb_color_base;
3030 if (cb->base.u.tex.level > 0)
3031 cb_color_cmask = cb_color_base;
3032 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3033 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3034 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3035 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3036
3037 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3038 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3039 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3040 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3041 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3042 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3043 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3044 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3045 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3046 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3047 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3048 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3049 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3050 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3051 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3052 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3053
3054 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3055 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3056 } else {
3057 /* Compute mutable surface parameters (SI-CI-VI). */
3058 const struct legacy_surf_level *level_info =
3059 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3060 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3061 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3062
3063 cb_color_base += level_info->offset >> 8;
3064 /* Only macrotiled modes can set tile swizzle. */
3065 if (level_info->mode == RADEON_SURF_MODE_2D)
3066 cb_color_base |= tex->surface.tile_swizzle;
3067
3068 if (!tex->fmask.size)
3069 cb_color_fmask = cb_color_base;
3070 if (cb->base.u.tex.level > 0)
3071 cb_color_cmask = cb_color_base;
3072 if (cb_dcc_base)
3073 cb_dcc_base += level_info->dcc_offset >> 8;
3074
3075 pitch_tile_max = level_info->nblk_x / 8 - 1;
3076 slice_tile_max = level_info->nblk_x *
3077 level_info->nblk_y / 64 - 1;
3078 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3079
3080 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3081 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3082 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3083
3084 if (tex->fmask.size) {
3085 if (sctx->chip_class >= CIK)
3086 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3087 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3088 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3089 } else {
3090 /* This must be set for fast clear to work without FMASK. */
3091 if (sctx->chip_class >= CIK)
3092 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3093 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3094 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3095 }
3096
3097 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3098 sctx->chip_class >= VI ? 14 : 13);
3099 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3100 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3101 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3102 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3103 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3104 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3105 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3106 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3107 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3108 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3109 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3110 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3111 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3112
3113 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3114 radeon_emit(cs, cb_dcc_base);
3115 }
3116 }
3117 for (; i < 8 ; i++)
3118 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3119 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3120
3121 /* ZS buffer. */
3122 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3123 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3124 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3125
3126 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3127 &rtex->resource, RADEON_USAGE_READWRITE,
3128 zb->base.texture->nr_samples > 1 ?
3129 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3130 RADEON_PRIO_DEPTH_BUFFER);
3131
3132 if (sctx->chip_class >= GFX9) {
3133 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3134 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3135 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3136 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3137
3138 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3139 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3140 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3141 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3142 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3143 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3144 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3145 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3146 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3147 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3148 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3149 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3150
3151 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3152 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3153 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3154 } else {
3155 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3156
3157 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3158 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3159 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3160 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3161 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3162 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3163 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3164 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3165 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3166 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3167 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3168 }
3169
3170 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3171 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3172 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3173
3174 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3175 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3176 } else if (sctx->framebuffer.dirty_zsbuf) {
3177 if (sctx->chip_class >= GFX9)
3178 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3179 else
3180 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3181
3182 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3183 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3184 }
3185
3186 /* Framebuffer dimensions. */
3187 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3188 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3189 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3190
3191 if (sctx->screen->dfsm_allowed) {
3192 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3193 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3194 }
3195
3196 sctx->framebuffer.dirty_cbufs = 0;
3197 sctx->framebuffer.dirty_zsbuf = false;
3198 }
3199
3200 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3201 struct si_atom *atom)
3202 {
3203 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3204 unsigned nr_samples = sctx->framebuffer.nr_samples;
3205 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3206
3207 /* Smoothing (only possible with nr_samples == 1) uses the same
3208 * sample locations as the MSAA it simulates.
3209 */
3210 if (nr_samples <= 1 && sctx->smoothing_enabled)
3211 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3212
3213 /* On Polaris, the small primitive filter uses the sample locations
3214 * even when MSAA is off, so we need to make sure they're set to 0.
3215 */
3216 if (has_msaa_sample_loc_bug)
3217 nr_samples = MAX2(nr_samples, 1);
3218
3219 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3220 sctx->msaa_sample_locs.nr_samples = nr_samples;
3221 si_emit_sample_locations(cs, nr_samples);
3222 }
3223
3224 if (sctx->family >= CHIP_POLARIS10) {
3225 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3226 unsigned small_prim_filter_cntl =
3227 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3228 /* line bug */
3229 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3230
3231 /* The alternative of setting sample locations to 0 would
3232 * require a DB flush to avoid Z errors, see
3233 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3234 */
3235 if (has_msaa_sample_loc_bug &&
3236 sctx->framebuffer.nr_samples > 1 &&
3237 rs && !rs->multisample_enable)
3238 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3239
3240 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3241 small_prim_filter_cntl);
3242 }
3243 }
3244
3245 static bool si_out_of_order_rasterization(struct si_context *sctx)
3246 {
3247 struct si_state_blend *blend = sctx->queued.named.blend;
3248 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3249
3250 if (!sctx->screen->has_out_of_order_rast)
3251 return false;
3252
3253 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3254
3255 if (blend) {
3256 colormask &= blend->cb_target_enabled_4bit;
3257 } else {
3258 colormask = 0;
3259 }
3260
3261 /* Conservative: No logic op. */
3262 if (colormask && blend->logicop_enable)
3263 return false;
3264
3265 struct si_dsa_order_invariance dsa_order_invariant = {
3266 .zs = true, .pass_set = true, .pass_last = false
3267 };
3268
3269 if (sctx->framebuffer.state.zsbuf) {
3270 struct r600_texture *zstex =
3271 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3272 bool has_stencil = zstex->surface.has_stencil;
3273 dsa_order_invariant = dsa->order_invariance[has_stencil];
3274 if (!dsa_order_invariant.zs)
3275 return false;
3276
3277 /* The set of PS invocations is always order invariant,
3278 * except when early Z/S tests are requested. */
3279 if (sctx->ps_shader.cso &&
3280 sctx->ps_shader.cso->info.writes_memory &&
3281 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3282 !dsa_order_invariant.pass_set)
3283 return false;
3284
3285 if (sctx->num_perfect_occlusion_queries != 0 &&
3286 !dsa_order_invariant.pass_set)
3287 return false;
3288 }
3289
3290 if (!colormask)
3291 return true;
3292
3293 unsigned blendmask = colormask & blend->blend_enable_4bit;
3294
3295 if (blendmask) {
3296 /* Only commutative blending. */
3297 if (blendmask & ~blend->commutative_4bit)
3298 return false;
3299
3300 if (!dsa_order_invariant.pass_set)
3301 return false;
3302 }
3303
3304 if (colormask & ~blendmask) {
3305 if (!dsa_order_invariant.pass_last)
3306 return false;
3307 }
3308
3309 return true;
3310 }
3311
3312 static void si_emit_msaa_config(struct si_context *sctx, struct si_atom *atom)
3313 {
3314 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3315 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3316 /* 33% faster rendering to linear color buffers */
3317 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3318 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3319 unsigned sc_mode_cntl_1 =
3320 S_028A4C_WALK_SIZE(dst_is_linear) |
3321 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3322 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3323 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3324 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3325 /* always 1: */
3326 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3327 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3328 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3329 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3330 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3331 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3332
3333 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3334 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3335
3336 /* Required by OpenGL line rasterization.
3337 *
3338 * TODO: We should also enable perpendicular endcaps for AA lines,
3339 * but that requires implementing line stippling in the pixel
3340 * shader. SC can only do line stippling with axis-aligned
3341 * endcaps.
3342 */
3343 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3344
3345 if (setup_samples > 1) {
3346 /* distance from the pixel center, indexed by log2(nr_samples) */
3347 static unsigned max_dist[] = {
3348 0, /* unused */
3349 4, /* 2x MSAA */
3350 6, /* 4x MSAA */
3351 7, /* 8x MSAA */
3352 8, /* 16x MSAA */
3353 };
3354 unsigned log_samples = util_logbase2(setup_samples);
3355 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3356 unsigned log_ps_iter_samples =
3357 util_logbase2(util_next_power_of_two(ps_iter_samples));
3358
3359 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3360 radeon_emit(cs, sc_line_cntl |
3361 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3362 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3363 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3364 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3365
3366 if (sctx->framebuffer.nr_samples > 1) {
3367 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3368 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3369 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3370 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3371 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3372 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3373 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3374 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3375 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3376 sc_mode_cntl_1);
3377 } else if (sctx->smoothing_enabled) {
3378 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3379 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3380 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3381 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3382 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3383 sc_mode_cntl_1);
3384 }
3385 } else {
3386 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3387 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3388 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3389
3390 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3391 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3392 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3393 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3394 sc_mode_cntl_1);
3395 }
3396
3397 /* GFX9: Flush DFSM when the AA mode changes. */
3398 if (sctx->screen->dfsm_allowed) {
3399 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3400 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3401 }
3402 }
3403
3404 void si_update_ps_iter_samples(struct si_context *sctx)
3405 {
3406 if (sctx->framebuffer.nr_samples > 1)
3407 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3408 if (sctx->screen->dpbb_allowed)
3409 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3410 }
3411
3412 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3413 {
3414 struct si_context *sctx = (struct si_context *)ctx;
3415
3416 if (sctx->ps_iter_samples == min_samples)
3417 return;
3418
3419 sctx->ps_iter_samples = min_samples;
3420 sctx->do_update_shaders = true;
3421
3422 si_update_ps_iter_samples(sctx);
3423 }
3424
3425 /*
3426 * Samplers
3427 */
3428
3429 /**
3430 * Build the sampler view descriptor for a buffer texture.
3431 * @param state 256-bit descriptor; only the high 128 bits are filled in
3432 */
3433 void
3434 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3435 enum pipe_format format,
3436 unsigned offset, unsigned size,
3437 uint32_t *state)
3438 {
3439 const struct util_format_description *desc;
3440 int first_non_void;
3441 unsigned stride;
3442 unsigned num_records;
3443 unsigned num_format, data_format;
3444
3445 desc = util_format_description(format);
3446 first_non_void = util_format_get_first_non_void_channel(format);
3447 stride = desc->block.bits / 8;
3448 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3449 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3450
3451 num_records = size / stride;
3452 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3453
3454 /* The NUM_RECORDS field has a different meaning depending on the chip,
3455 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3456 *
3457 * SI-CIK:
3458 * - If STRIDE == 0, it's in byte units.
3459 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3460 *
3461 * VI:
3462 * - For SMEM and STRIDE == 0, it's in byte units.
3463 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3464 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3465 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3466 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3467 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3468 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3469 * That way the same descriptor can be used by both SMEM and VMEM.
3470 *
3471 * GFX9:
3472 * - For SMEM and STRIDE == 0, it's in byte units.
3473 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3474 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3475 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3476 */
3477 if (screen->info.chip_class >= GFX9)
3478 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3479 * from STRIDE to bytes. This works around it by setting
3480 * NUM_RECORDS to at least the size of one element, so that
3481 * the first element is readable when IDXEN == 0.
3482 *
3483 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3484 * IDXEN is enforced?
3485 */
3486 num_records = num_records ? MAX2(num_records, stride) : 0;
3487 else if (screen->info.chip_class == VI)
3488 num_records *= stride;
3489
3490 state[4] = 0;
3491 state[5] = S_008F04_STRIDE(stride);
3492 state[6] = num_records;
3493 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3494 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3495 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3496 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3497 S_008F0C_NUM_FORMAT(num_format) |
3498 S_008F0C_DATA_FORMAT(data_format);
3499 }
3500
3501 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3502 {
3503 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3504
3505 if (swizzle[3] == PIPE_SWIZZLE_X) {
3506 /* For the pre-defined border color values (white, opaque
3507 * black, transparent black), the only thing that matters is
3508 * that the alpha channel winds up in the correct place
3509 * (because the RGB channels are all the same) so either of
3510 * these enumerations will work.
3511 */
3512 if (swizzle[2] == PIPE_SWIZZLE_Y)
3513 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3514 else
3515 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3516 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3517 if (swizzle[1] == PIPE_SWIZZLE_Y)
3518 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3519 else
3520 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3521 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3522 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3523 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3524 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3525 }
3526
3527 return bc_swizzle;
3528 }
3529
3530 /**
3531 * Build the sampler view descriptor for a texture.
3532 */
3533 void
3534 si_make_texture_descriptor(struct si_screen *screen,
3535 struct r600_texture *tex,
3536 bool sampler,
3537 enum pipe_texture_target target,
3538 enum pipe_format pipe_format,
3539 const unsigned char state_swizzle[4],
3540 unsigned first_level, unsigned last_level,
3541 unsigned first_layer, unsigned last_layer,
3542 unsigned width, unsigned height, unsigned depth,
3543 uint32_t *state,
3544 uint32_t *fmask_state)
3545 {
3546 struct pipe_resource *res = &tex->resource.b.b;
3547 const struct util_format_description *desc;
3548 unsigned char swizzle[4];
3549 int first_non_void;
3550 unsigned num_format, data_format, type;
3551 uint64_t va;
3552
3553 desc = util_format_description(pipe_format);
3554
3555 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3556 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3557 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3558 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3559
3560 switch (pipe_format) {
3561 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3562 case PIPE_FORMAT_X32_S8X24_UINT:
3563 case PIPE_FORMAT_X8Z24_UNORM:
3564 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3565 break;
3566 case PIPE_FORMAT_X24S8_UINT:
3567 /*
3568 * X24S8 is implemented as an 8_8_8_8 data format, to
3569 * fix texture gathers. This affects at least
3570 * GL45-CTS.texture_cube_map_array.sampling on VI.
3571 */
3572 if (screen->info.chip_class <= VI)
3573 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3574 else
3575 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3576 break;
3577 default:
3578 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3579 }
3580 } else {
3581 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3582 }
3583
3584 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3585
3586 switch (pipe_format) {
3587 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3588 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3589 break;
3590 default:
3591 if (first_non_void < 0) {
3592 if (util_format_is_compressed(pipe_format)) {
3593 switch (pipe_format) {
3594 case PIPE_FORMAT_DXT1_SRGB:
3595 case PIPE_FORMAT_DXT1_SRGBA:
3596 case PIPE_FORMAT_DXT3_SRGBA:
3597 case PIPE_FORMAT_DXT5_SRGBA:
3598 case PIPE_FORMAT_BPTC_SRGBA:
3599 case PIPE_FORMAT_ETC2_SRGB8:
3600 case PIPE_FORMAT_ETC2_SRGB8A1:
3601 case PIPE_FORMAT_ETC2_SRGBA8:
3602 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3603 break;
3604 case PIPE_FORMAT_RGTC1_SNORM:
3605 case PIPE_FORMAT_LATC1_SNORM:
3606 case PIPE_FORMAT_RGTC2_SNORM:
3607 case PIPE_FORMAT_LATC2_SNORM:
3608 case PIPE_FORMAT_ETC2_R11_SNORM:
3609 case PIPE_FORMAT_ETC2_RG11_SNORM:
3610 /* implies float, so use SNORM/UNORM to determine
3611 whether data is signed or not */
3612 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3613 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3614 break;
3615 default:
3616 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3617 break;
3618 }
3619 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3620 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3621 } else {
3622 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3623 }
3624 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3625 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3626 } else {
3627 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3628
3629 switch (desc->channel[first_non_void].type) {
3630 case UTIL_FORMAT_TYPE_FLOAT:
3631 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3632 break;
3633 case UTIL_FORMAT_TYPE_SIGNED:
3634 if (desc->channel[first_non_void].normalized)
3635 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3636 else if (desc->channel[first_non_void].pure_integer)
3637 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3638 else
3639 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3640 break;
3641 case UTIL_FORMAT_TYPE_UNSIGNED:
3642 if (desc->channel[first_non_void].normalized)
3643 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3644 else if (desc->channel[first_non_void].pure_integer)
3645 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3646 else
3647 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3648 }
3649 }
3650 }
3651
3652 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3653 if (data_format == ~0) {
3654 data_format = 0;
3655 }
3656
3657 /* S8 with Z32 HTILE needs a special format. */
3658 if (screen->info.chip_class >= GFX9 &&
3659 pipe_format == PIPE_FORMAT_S8_UINT &&
3660 tex->tc_compatible_htile)
3661 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3662
3663 if (!sampler &&
3664 (res->target == PIPE_TEXTURE_CUBE ||
3665 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3666 (screen->info.chip_class <= VI &&
3667 res->target == PIPE_TEXTURE_3D))) {
3668 /* For the purpose of shader images, treat cube maps and 3D
3669 * textures as 2D arrays. For 3D textures, the address
3670 * calculations for mipmaps are different, so we rely on the
3671 * caller to effectively disable mipmaps.
3672 */
3673 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3674
3675 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3676 } else {
3677 type = si_tex_dim(screen, tex, target, res->nr_samples);
3678 }
3679
3680 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3681 height = 1;
3682 depth = res->array_size;
3683 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3684 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3685 if (sampler || res->target != PIPE_TEXTURE_3D)
3686 depth = res->array_size;
3687 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3688 depth = res->array_size / 6;
3689
3690 state[0] = 0;
3691 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3692 S_008F14_NUM_FORMAT_GFX6(num_format));
3693 state[2] = (S_008F18_WIDTH(width - 1) |
3694 S_008F18_HEIGHT(height - 1) |
3695 S_008F18_PERF_MOD(4));
3696 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3697 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3698 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3699 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3700 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3701 0 : first_level) |
3702 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3703 util_logbase2(res->nr_samples) :
3704 last_level) |
3705 S_008F1C_TYPE(type));
3706 state[4] = 0;
3707 state[5] = S_008F24_BASE_ARRAY(first_layer);
3708 state[6] = 0;
3709 state[7] = 0;
3710
3711 if (screen->info.chip_class >= GFX9) {
3712 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3713
3714 /* Depth is the the last accessible layer on Gfx9.
3715 * The hw doesn't need to know the total number of layers.
3716 */
3717 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3718 state[4] |= S_008F20_DEPTH(depth - 1);
3719 else
3720 state[4] |= S_008F20_DEPTH(last_layer);
3721
3722 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3723 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3724 util_logbase2(res->nr_samples) :
3725 tex->resource.b.b.last_level);
3726 } else {
3727 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3728 state[4] |= S_008F20_DEPTH(depth - 1);
3729 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3730 }
3731
3732 if (tex->dcc_offset) {
3733 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3734 } else {
3735 /* The last dword is unused by hw. The shader uses it to clear
3736 * bits in the first dword of sampler state.
3737 */
3738 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3739 if (first_level == last_level)
3740 state[7] = C_008F30_MAX_ANISO_RATIO;
3741 else
3742 state[7] = 0xffffffff;
3743 }
3744 }
3745
3746 /* Initialize the sampler view for FMASK. */
3747 if (tex->fmask.size) {
3748 uint32_t data_format, num_format;
3749
3750 va = tex->resource.gpu_address + tex->fmask.offset;
3751
3752 if (screen->info.chip_class >= GFX9) {
3753 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3754 switch (res->nr_samples) {
3755 case 2:
3756 num_format = V_008F14_IMG_FMASK_8_2_2;
3757 break;
3758 case 4:
3759 num_format = V_008F14_IMG_FMASK_8_4_4;
3760 break;
3761 case 8:
3762 num_format = V_008F14_IMG_FMASK_32_8_8;
3763 break;
3764 default:
3765 unreachable("invalid nr_samples");
3766 }
3767 } else {
3768 switch (res->nr_samples) {
3769 case 2:
3770 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3771 break;
3772 case 4:
3773 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3774 break;
3775 case 8:
3776 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3777 break;
3778 default:
3779 unreachable("invalid nr_samples");
3780 }
3781 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3782 }
3783
3784 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3785 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3786 S_008F14_DATA_FORMAT_GFX6(data_format) |
3787 S_008F14_NUM_FORMAT_GFX6(num_format);
3788 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3789 S_008F18_HEIGHT(height - 1);
3790 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3791 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3792 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3793 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3794 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3795 fmask_state[4] = 0;
3796 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3797 fmask_state[6] = 0;
3798 fmask_state[7] = 0;
3799
3800 if (screen->info.chip_class >= GFX9) {
3801 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3802 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3803 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3804 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3805 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3806 } else {
3807 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3808 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3809 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3810 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3811 }
3812 }
3813 }
3814
3815 /**
3816 * Create a sampler view.
3817 *
3818 * @param ctx context
3819 * @param texture texture
3820 * @param state sampler view template
3821 * @param width0 width0 override (for compressed textures as int)
3822 * @param height0 height0 override (for compressed textures as int)
3823 * @param force_level set the base address to the level (for compressed textures)
3824 */
3825 struct pipe_sampler_view *
3826 si_create_sampler_view_custom(struct pipe_context *ctx,
3827 struct pipe_resource *texture,
3828 const struct pipe_sampler_view *state,
3829 unsigned width0, unsigned height0,
3830 unsigned force_level)
3831 {
3832 struct si_context *sctx = (struct si_context*)ctx;
3833 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3834 struct r600_texture *tmp = (struct r600_texture*)texture;
3835 unsigned base_level, first_level, last_level;
3836 unsigned char state_swizzle[4];
3837 unsigned height, depth, width;
3838 unsigned last_layer = state->u.tex.last_layer;
3839 enum pipe_format pipe_format;
3840 const struct legacy_surf_level *surflevel;
3841
3842 if (!view)
3843 return NULL;
3844
3845 /* initialize base object */
3846 view->base = *state;
3847 view->base.texture = NULL;
3848 view->base.reference.count = 1;
3849 view->base.context = ctx;
3850
3851 assert(texture);
3852 pipe_resource_reference(&view->base.texture, texture);
3853
3854 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3855 state->format == PIPE_FORMAT_S8X24_UINT ||
3856 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3857 state->format == PIPE_FORMAT_S8_UINT)
3858 view->is_stencil_sampler = true;
3859
3860 /* Buffer resource. */
3861 if (texture->target == PIPE_BUFFER) {
3862 si_make_buffer_descriptor(sctx->screen,
3863 (struct r600_resource *)texture,
3864 state->format,
3865 state->u.buf.offset,
3866 state->u.buf.size,
3867 view->state);
3868 return &view->base;
3869 }
3870
3871 state_swizzle[0] = state->swizzle_r;
3872 state_swizzle[1] = state->swizzle_g;
3873 state_swizzle[2] = state->swizzle_b;
3874 state_swizzle[3] = state->swizzle_a;
3875
3876 base_level = 0;
3877 first_level = state->u.tex.first_level;
3878 last_level = state->u.tex.last_level;
3879 width = width0;
3880 height = height0;
3881 depth = texture->depth0;
3882
3883 if (sctx->chip_class <= VI && force_level) {
3884 assert(force_level == first_level &&
3885 force_level == last_level);
3886 base_level = force_level;
3887 first_level = 0;
3888 last_level = 0;
3889 width = u_minify(width, force_level);
3890 height = u_minify(height, force_level);
3891 depth = u_minify(depth, force_level);
3892 }
3893
3894 /* This is not needed if state trackers set last_layer correctly. */
3895 if (state->target == PIPE_TEXTURE_1D ||
3896 state->target == PIPE_TEXTURE_2D ||
3897 state->target == PIPE_TEXTURE_RECT ||
3898 state->target == PIPE_TEXTURE_CUBE)
3899 last_layer = state->u.tex.first_layer;
3900
3901 /* Texturing with separate depth and stencil. */
3902 pipe_format = state->format;
3903
3904 /* Depth/stencil texturing sometimes needs separate texture. */
3905 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
3906 if (!tmp->flushed_depth_texture &&
3907 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3908 pipe_resource_reference(&view->base.texture, NULL);
3909 FREE(view);
3910 return NULL;
3911 }
3912
3913 assert(tmp->flushed_depth_texture);
3914
3915 /* Override format for the case where the flushed texture
3916 * contains only Z or only S.
3917 */
3918 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3919 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3920
3921 tmp = tmp->flushed_depth_texture;
3922 }
3923
3924 surflevel = tmp->surface.u.legacy.level;
3925
3926 if (tmp->db_compatible) {
3927 if (!view->is_stencil_sampler)
3928 pipe_format = tmp->db_render_format;
3929
3930 switch (pipe_format) {
3931 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3932 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3933 break;
3934 case PIPE_FORMAT_X8Z24_UNORM:
3935 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3936 /* Z24 is always stored like this for DB
3937 * compatibility.
3938 */
3939 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3940 break;
3941 case PIPE_FORMAT_X24S8_UINT:
3942 case PIPE_FORMAT_S8X24_UINT:
3943 case PIPE_FORMAT_X32_S8X24_UINT:
3944 pipe_format = PIPE_FORMAT_S8_UINT;
3945 surflevel = tmp->surface.u.legacy.stencil_level;
3946 break;
3947 default:;
3948 }
3949 }
3950
3951 view->dcc_incompatible =
3952 vi_dcc_formats_are_incompatible(texture,
3953 state->u.tex.first_level,
3954 state->format);
3955
3956 si_make_texture_descriptor(sctx->screen, tmp, true,
3957 state->target, pipe_format, state_swizzle,
3958 first_level, last_level,
3959 state->u.tex.first_layer, last_layer,
3960 width, height, depth,
3961 view->state, view->fmask_state);
3962
3963 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3964 view->is_integer =
3965 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3966 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3967 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3968 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3969 view->base_level_info = &surflevel[base_level];
3970 view->base_level = base_level;
3971 view->block_width = util_format_get_blockwidth(pipe_format);
3972 return &view->base;
3973 }
3974
3975 static struct pipe_sampler_view *
3976 si_create_sampler_view(struct pipe_context *ctx,
3977 struct pipe_resource *texture,
3978 const struct pipe_sampler_view *state)
3979 {
3980 return si_create_sampler_view_custom(ctx, texture, state,
3981 texture ? texture->width0 : 0,
3982 texture ? texture->height0 : 0, 0);
3983 }
3984
3985 static void si_sampler_view_destroy(struct pipe_context *ctx,
3986 struct pipe_sampler_view *state)
3987 {
3988 struct si_sampler_view *view = (struct si_sampler_view *)state;
3989
3990 pipe_resource_reference(&state->texture, NULL);
3991 FREE(view);
3992 }
3993
3994 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3995 {
3996 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3997 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3998 (linear_filter &&
3999 (wrap == PIPE_TEX_WRAP_CLAMP ||
4000 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4001 }
4002
4003 static uint32_t si_translate_border_color(struct si_context *sctx,
4004 const struct pipe_sampler_state *state,
4005 const union pipe_color_union *color,
4006 bool is_integer)
4007 {
4008 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4009 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4010
4011 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4012 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4013 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4014 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4015
4016 #define simple_border_types(elt) \
4017 do { \
4018 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4019 color->elt[2] == 0 && color->elt[3] == 0) \
4020 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4021 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4022 color->elt[2] == 0 && color->elt[3] == 1) \
4023 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4024 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4025 color->elt[2] == 1 && color->elt[3] == 1) \
4026 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4027 } while (false)
4028
4029 if (is_integer)
4030 simple_border_types(ui);
4031 else
4032 simple_border_types(f);
4033
4034 #undef simple_border_types
4035
4036 int i;
4037
4038 /* Check if the border has been uploaded already. */
4039 for (i = 0; i < sctx->border_color_count; i++)
4040 if (memcmp(&sctx->border_color_table[i], color,
4041 sizeof(*color)) == 0)
4042 break;
4043
4044 if (i >= SI_MAX_BORDER_COLORS) {
4045 /* Getting 4096 unique border colors is very unlikely. */
4046 fprintf(stderr, "radeonsi: The border color table is full. "
4047 "Any new border colors will be just black. "
4048 "Please file a bug.\n");
4049 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4050 }
4051
4052 if (i == sctx->border_color_count) {
4053 /* Upload a new border color. */
4054 memcpy(&sctx->border_color_table[i], color,
4055 sizeof(*color));
4056 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4057 color, sizeof(*color));
4058 sctx->border_color_count++;
4059 }
4060
4061 return S_008F3C_BORDER_COLOR_PTR(i) |
4062 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4063 }
4064
4065 static inline int S_FIXED(float value, unsigned frac_bits)
4066 {
4067 return value * (1 << frac_bits);
4068 }
4069
4070 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4071 {
4072 if (filter == PIPE_TEX_FILTER_LINEAR)
4073 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4074 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4075 else
4076 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4077 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4078 }
4079
4080 static inline unsigned si_tex_aniso_filter(unsigned filter)
4081 {
4082 if (filter < 2)
4083 return 0;
4084 if (filter < 4)
4085 return 1;
4086 if (filter < 8)
4087 return 2;
4088 if (filter < 16)
4089 return 3;
4090 return 4;
4091 }
4092
4093 static void *si_create_sampler_state(struct pipe_context *ctx,
4094 const struct pipe_sampler_state *state)
4095 {
4096 struct si_context *sctx = (struct si_context *)ctx;
4097 struct si_screen *sscreen = sctx->screen;
4098 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4099 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4100 : state->max_anisotropy;
4101 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4102 union pipe_color_union clamped_border_color;
4103
4104 if (!rstate) {
4105 return NULL;
4106 }
4107
4108 #ifdef DEBUG
4109 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4110 #endif
4111 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4112 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4113 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4114 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4115 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4116 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4117 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4118 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4119 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4120 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4121 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4122 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4123 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4124 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4125 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4126 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4127 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4128 S_008F38_MIP_POINT_PRECLAMP(0) |
4129 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4130 S_008F38_FILTER_PREC_FIX(1) |
4131 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4132 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4133
4134 /* Create sampler resource for integer textures. */
4135 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4136 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4137
4138 /* Create sampler resource for upgraded depth textures. */
4139 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4140
4141 for (unsigned i = 0; i < 4; ++i) {
4142 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4143 * when the border color is 1.0. */
4144 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4145 }
4146
4147 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4148 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4149 else
4150 rstate->upgraded_depth_val[3] =
4151 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4152 S_008F3C_UPGRADED_DEPTH(1);
4153
4154 return rstate;
4155 }
4156
4157 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4158 {
4159 struct si_context *sctx = (struct si_context *)ctx;
4160
4161 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4162 return;
4163
4164 sctx->sample_mask.sample_mask = sample_mask;
4165 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4166 }
4167
4168 static void si_emit_sample_mask(struct si_context *sctx, struct si_atom *atom)
4169 {
4170 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4171 unsigned mask = sctx->sample_mask.sample_mask;
4172
4173 /* Needed for line and polygon smoothing as well as for the Polaris
4174 * small primitive filter. We expect the state tracker to take care of
4175 * this for us.
4176 */
4177 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4178 (mask & 1 && sctx->blitter->running));
4179
4180 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4181 radeon_emit(cs, mask | (mask << 16));
4182 radeon_emit(cs, mask | (mask << 16));
4183 }
4184
4185 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4186 {
4187 #ifdef DEBUG
4188 struct si_sampler_state *s = state;
4189
4190 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4191 s->magic = 0;
4192 #endif
4193 free(state);
4194 }
4195
4196 /*
4197 * Vertex elements & buffers
4198 */
4199
4200 static void *si_create_vertex_elements(struct pipe_context *ctx,
4201 unsigned count,
4202 const struct pipe_vertex_element *elements)
4203 {
4204 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4205 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4206 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4207 int i;
4208
4209 assert(count <= SI_MAX_ATTRIBS);
4210 if (!v)
4211 return NULL;
4212
4213 v->count = count;
4214 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4215
4216 for (i = 0; i < count; ++i) {
4217 const struct util_format_description *desc;
4218 const struct util_format_channel_description *channel;
4219 unsigned data_format, num_format;
4220 int first_non_void;
4221 unsigned vbo_index = elements[i].vertex_buffer_index;
4222 unsigned char swizzle[4];
4223
4224 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4225 FREE(v);
4226 return NULL;
4227 }
4228
4229 if (elements[i].instance_divisor) {
4230 v->uses_instance_divisors = true;
4231 v->instance_divisors[i] = elements[i].instance_divisor;
4232
4233 if (v->instance_divisors[i] == 1)
4234 v->instance_divisor_is_one |= 1u << i;
4235 else
4236 v->instance_divisor_is_fetched |= 1u << i;
4237 }
4238
4239 if (!used[vbo_index]) {
4240 v->first_vb_use_mask |= 1 << i;
4241 used[vbo_index] = true;
4242 }
4243
4244 desc = util_format_description(elements[i].src_format);
4245 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4246 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4247 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4248 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4249 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4250
4251 v->format_size[i] = desc->block.bits / 8;
4252 v->src_offset[i] = elements[i].src_offset;
4253 v->vertex_buffer_index[i] = vbo_index;
4254
4255 /* The hardware always treats the 2-bit alpha channel as
4256 * unsigned, so a shader workaround is needed. The affected
4257 * chips are VI and older except Stoney (GFX8.1).
4258 */
4259 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4260 sscreen->info.chip_class <= VI &&
4261 sscreen->info.family != CHIP_STONEY) {
4262 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4263 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4264 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4265 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4266 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4267 /* This isn't actually used in OpenGL. */
4268 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4269 }
4270 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4271 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4272 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4273 else
4274 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4275 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4276 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4277 if (channel->normalized) {
4278 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4279 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4280 else
4281 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4282 } else {
4283 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4284 }
4285 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4286 if (channel->normalized) {
4287 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4288 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4289 else
4290 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4291 } else {
4292 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4293 }
4294 }
4295 } else if (channel && channel->size == 64 &&
4296 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4297 switch (desc->nr_channels) {
4298 case 1:
4299 case 2:
4300 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4301 swizzle[0] = PIPE_SWIZZLE_X;
4302 swizzle[1] = PIPE_SWIZZLE_Y;
4303 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4304 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4305 break;
4306 case 3:
4307 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4308 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4309 swizzle[1] = PIPE_SWIZZLE_Y;
4310 swizzle[2] = PIPE_SWIZZLE_0;
4311 swizzle[3] = PIPE_SWIZZLE_0;
4312 break;
4313 case 4:
4314 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4315 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4316 swizzle[1] = PIPE_SWIZZLE_Y;
4317 swizzle[2] = PIPE_SWIZZLE_Z;
4318 swizzle[3] = PIPE_SWIZZLE_W;
4319 break;
4320 default:
4321 assert(0);
4322 }
4323 } else if (channel && desc->nr_channels == 3) {
4324 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4325
4326 if (channel->size == 8) {
4327 if (channel->pure_integer)
4328 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4329 else
4330 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4331 } else if (channel->size == 16) {
4332 if (channel->pure_integer)
4333 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4334 else
4335 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4336 }
4337 }
4338
4339 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4340 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4341 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4342 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4343 S_008F0C_NUM_FORMAT(num_format) |
4344 S_008F0C_DATA_FORMAT(data_format);
4345 }
4346 return v;
4347 }
4348
4349 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4350 {
4351 struct si_context *sctx = (struct si_context *)ctx;
4352 struct si_vertex_elements *old = sctx->vertex_elements;
4353 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4354
4355 sctx->vertex_elements = v;
4356 sctx->vertex_buffers_dirty = true;
4357
4358 if (v &&
4359 (!old ||
4360 old->count != v->count ||
4361 old->uses_instance_divisors != v->uses_instance_divisors ||
4362 v->uses_instance_divisors || /* we don't check which divisors changed */
4363 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4364 sctx->do_update_shaders = true;
4365
4366 if (v && v->instance_divisor_is_fetched) {
4367 struct pipe_constant_buffer cb;
4368
4369 cb.buffer = NULL;
4370 cb.user_buffer = v->instance_divisors;
4371 cb.buffer_offset = 0;
4372 cb.buffer_size = sizeof(uint32_t) * v->count;
4373 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4374 }
4375 }
4376
4377 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4378 {
4379 struct si_context *sctx = (struct si_context *)ctx;
4380
4381 if (sctx->vertex_elements == state)
4382 sctx->vertex_elements = NULL;
4383 FREE(state);
4384 }
4385
4386 static void si_set_vertex_buffers(struct pipe_context *ctx,
4387 unsigned start_slot, unsigned count,
4388 const struct pipe_vertex_buffer *buffers)
4389 {
4390 struct si_context *sctx = (struct si_context *)ctx;
4391 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4392 int i;
4393
4394 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4395
4396 if (buffers) {
4397 for (i = 0; i < count; i++) {
4398 const struct pipe_vertex_buffer *src = buffers + i;
4399 struct pipe_vertex_buffer *dsti = dst + i;
4400 struct pipe_resource *buf = src->buffer.resource;
4401
4402 pipe_resource_reference(&dsti->buffer.resource, buf);
4403 dsti->buffer_offset = src->buffer_offset;
4404 dsti->stride = src->stride;
4405 si_context_add_resource_size(sctx, buf);
4406 if (buf)
4407 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4408 }
4409 } else {
4410 for (i = 0; i < count; i++) {
4411 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4412 }
4413 }
4414 sctx->vertex_buffers_dirty = true;
4415 }
4416
4417 /*
4418 * Misc
4419 */
4420
4421 static void si_set_tess_state(struct pipe_context *ctx,
4422 const float default_outer_level[4],
4423 const float default_inner_level[2])
4424 {
4425 struct si_context *sctx = (struct si_context *)ctx;
4426 struct pipe_constant_buffer cb;
4427 float array[8];
4428
4429 memcpy(array, default_outer_level, sizeof(float) * 4);
4430 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4431
4432 cb.buffer = NULL;
4433 cb.user_buffer = NULL;
4434 cb.buffer_size = sizeof(array);
4435
4436 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4437 (void*)array, sizeof(array),
4438 &cb.buffer_offset);
4439
4440 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4441 pipe_resource_reference(&cb.buffer, NULL);
4442 }
4443
4444 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4445 {
4446 struct si_context *sctx = (struct si_context *)ctx;
4447
4448 si_update_fb_dirtiness_after_rendering(sctx);
4449
4450 /* Multisample surfaces are flushed in si_decompress_textures. */
4451 if (sctx->framebuffer.uncompressed_cb_mask)
4452 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4453 sctx->framebuffer.CB_has_shader_readable_metadata);
4454 }
4455
4456 /* This only ensures coherency for shader image/buffer stores. */
4457 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4458 {
4459 struct si_context *sctx = (struct si_context *)ctx;
4460
4461 /* Subsequent commands must wait for all shader invocations to
4462 * complete. */
4463 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4464 SI_CONTEXT_CS_PARTIAL_FLUSH;
4465
4466 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4467 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4468 SI_CONTEXT_INV_VMEM_L1;
4469
4470 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4471 PIPE_BARRIER_SHADER_BUFFER |
4472 PIPE_BARRIER_TEXTURE |
4473 PIPE_BARRIER_IMAGE |
4474 PIPE_BARRIER_STREAMOUT_BUFFER |
4475 PIPE_BARRIER_GLOBAL_BUFFER)) {
4476 /* As far as I can tell, L1 contents are written back to L2
4477 * automatically at end of shader, but the contents of other
4478 * L1 caches might still be stale. */
4479 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4480 }
4481
4482 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4483 /* Indices are read through TC L2 since VI.
4484 * L1 isn't used.
4485 */
4486 if (sctx->screen->info.chip_class <= CIK)
4487 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4488 }
4489
4490 /* MSAA color, any depth and any stencil are flushed in
4491 * si_decompress_textures when needed.
4492 */
4493 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4494 sctx->framebuffer.uncompressed_cb_mask) {
4495 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4496
4497 if (sctx->chip_class <= VI)
4498 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4499 }
4500
4501 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4502 if (sctx->screen->info.chip_class <= VI &&
4503 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4504 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4505 }
4506
4507 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4508 {
4509 struct pipe_blend_state blend;
4510
4511 memset(&blend, 0, sizeof(blend));
4512 blend.independent_blend_enable = true;
4513 blend.rt[0].colormask = 0xf;
4514 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4515 }
4516
4517 static void si_init_config(struct si_context *sctx);
4518
4519 void si_init_state_functions(struct si_context *sctx)
4520 {
4521 si_init_atom(sctx, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4522 si_init_atom(sctx, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4523 si_init_atom(sctx, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4524 si_init_atom(sctx, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4525 si_init_atom(sctx, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4526 si_init_atom(sctx, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4527 si_init_atom(sctx, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4528 si_init_atom(sctx, &sctx->atoms.s.blend_color, si_emit_blend_color);
4529 si_init_atom(sctx, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4530 si_init_atom(sctx, &sctx->atoms.s.clip_state, si_emit_clip_state);
4531 si_init_atom(sctx, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4532
4533 sctx->b.create_blend_state = si_create_blend_state;
4534 sctx->b.bind_blend_state = si_bind_blend_state;
4535 sctx->b.delete_blend_state = si_delete_blend_state;
4536 sctx->b.set_blend_color = si_set_blend_color;
4537
4538 sctx->b.create_rasterizer_state = si_create_rs_state;
4539 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4540 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4541
4542 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4543 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4544 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4545
4546 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4547 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4548 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4549 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4550 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4551
4552 sctx->b.set_clip_state = si_set_clip_state;
4553 sctx->b.set_stencil_ref = si_set_stencil_ref;
4554
4555 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4556
4557 sctx->b.create_sampler_state = si_create_sampler_state;
4558 sctx->b.delete_sampler_state = si_delete_sampler_state;
4559
4560 sctx->b.create_sampler_view = si_create_sampler_view;
4561 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4562
4563 sctx->b.set_sample_mask = si_set_sample_mask;
4564
4565 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4566 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4567 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4568 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4569
4570 sctx->b.texture_barrier = si_texture_barrier;
4571 sctx->b.memory_barrier = si_memory_barrier;
4572 sctx->b.set_min_samples = si_set_min_samples;
4573 sctx->b.set_tess_state = si_set_tess_state;
4574
4575 sctx->b.set_active_query_state = si_set_active_query_state;
4576
4577 sctx->b.draw_vbo = si_draw_vbo;
4578
4579 si_init_config(sctx);
4580 }
4581
4582 void si_init_screen_state_functions(struct si_screen *sscreen)
4583 {
4584 sscreen->b.is_format_supported = si_is_format_supported;
4585 }
4586
4587 static void si_set_grbm_gfx_index(struct si_context *sctx,
4588 struct si_pm4_state *pm4, unsigned value)
4589 {
4590 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4591 R_00802C_GRBM_GFX_INDEX;
4592 si_pm4_set_reg(pm4, reg, value);
4593 }
4594
4595 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4596 struct si_pm4_state *pm4, unsigned se)
4597 {
4598 assert(se == ~0 || se < sctx->screen->info.max_se);
4599 si_set_grbm_gfx_index(sctx, pm4,
4600 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4601 S_030800_SE_INDEX(se)) |
4602 S_030800_SH_BROADCAST_WRITES(1) |
4603 S_030800_INSTANCE_BROADCAST_WRITES(1));
4604 }
4605
4606 static void
4607 si_write_harvested_raster_configs(struct si_context *sctx,
4608 struct si_pm4_state *pm4,
4609 unsigned raster_config,
4610 unsigned raster_config_1)
4611 {
4612 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4613 unsigned raster_config_se[4];
4614 unsigned se;
4615
4616 ac_get_harvested_configs(&sctx->screen->info,
4617 raster_config,
4618 &raster_config_1,
4619 raster_config_se);
4620
4621 for (se = 0; se < num_se; se++) {
4622 si_set_grbm_gfx_index_se(sctx, pm4, se);
4623 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4624 }
4625 si_set_grbm_gfx_index(sctx, pm4, ~0);
4626
4627 if (sctx->chip_class >= CIK) {
4628 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4629 }
4630 }
4631
4632 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4633 {
4634 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4635 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4636 unsigned raster_config, raster_config_1;
4637
4638 ac_get_raster_config(&sctx->screen->info,
4639 &raster_config,
4640 &raster_config_1);
4641
4642 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4643 /* Always use the default config when all backends are enabled
4644 * (or when we failed to determine the enabled backends).
4645 */
4646 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4647 raster_config);
4648 if (sctx->chip_class >= CIK)
4649 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4650 raster_config_1);
4651 } else {
4652 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4653 }
4654 }
4655
4656 static void si_init_config(struct si_context *sctx)
4657 {
4658 struct si_screen *sscreen = sctx->screen;
4659 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4660 bool has_clear_state = sscreen->has_clear_state;
4661 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4662
4663 /* Only SI can disable CLEAR_STATE for now. */
4664 assert(has_clear_state || sscreen->info.chip_class == SI);
4665
4666 if (!pm4)
4667 return;
4668
4669 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4670 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4671 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4672 si_pm4_cmd_end(pm4, false);
4673
4674 if (has_clear_state) {
4675 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4676 si_pm4_cmd_add(pm4, 0);
4677 si_pm4_cmd_end(pm4, false);
4678 }
4679
4680 if (sctx->chip_class <= VI)
4681 si_set_raster_config(sctx, pm4);
4682
4683 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4684 if (!has_clear_state)
4685 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4686
4687 /* FIXME calculate these values somehow ??? */
4688 if (sctx->chip_class <= VI) {
4689 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4690 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4691 }
4692
4693 if (!has_clear_state) {
4694 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4695 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4696 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4697 }
4698
4699 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4700 if (!has_clear_state)
4701 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4702 if (sctx->chip_class < CIK)
4703 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4704 S_008A14_CLIP_VTX_REORDER_ENA(1));
4705
4706 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4707 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4708
4709 if (!has_clear_state)
4710 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4711
4712 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4713 * I don't know why. Deduced by trial and error.
4714 */
4715 if (sctx->chip_class <= CIK) {
4716 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4717 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4718 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4719 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4720 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4721 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4722 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4723 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4724 }
4725
4726 if (!has_clear_state) {
4727 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4728 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4729 S_028230_ER_TRI(0xA) |
4730 S_028230_ER_POINT(0xA) |
4731 S_028230_ER_RECT(0xA) |
4732 /* Required by DX10_DIAMOND_TEST_ENA: */
4733 S_028230_ER_LINE_LR(0x1A) |
4734 S_028230_ER_LINE_RL(0x26) |
4735 S_028230_ER_LINE_TB(0xA) |
4736 S_028230_ER_LINE_BT(0xA));
4737 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4738 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4739 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4740 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4741 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4742 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4743 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4744 }
4745
4746 if (sctx->chip_class >= GFX9) {
4747 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4748 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4749 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4750 } else {
4751 /* These registers, when written, also overwrite the CLEAR_STATE
4752 * context, so we can't rely on CLEAR_STATE setting them.
4753 * It would be an issue if there was another UMD changing them.
4754 */
4755 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4756 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4757 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4758 }
4759
4760 if (sctx->chip_class >= CIK) {
4761 if (sctx->chip_class >= GFX9) {
4762 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4763 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4764 } else {
4765 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4766 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4767 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4768 S_00B41C_WAVE_LIMIT(0x3F));
4769 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4770 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4771
4772 /* If this is 0, Bonaire can hang even if GS isn't being used.
4773 * Other chips are unaffected. These are suboptimal values,
4774 * but we don't use on-chip GS.
4775 */
4776 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4777 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4778 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4779 }
4780 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4781 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4782
4783 /* Compute LATE_ALLOC_VS.LIMIT. */
4784 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4785 (sscreen->info.max_se *
4786 sscreen->info.max_sh_per_se);
4787 unsigned late_alloc_limit; /* The limit is per SH. */
4788
4789 if (sctx->family == CHIP_KABINI) {
4790 late_alloc_limit = 0; /* Potential hang on Kabini. */
4791 } else if (num_cu_per_sh <= 4) {
4792 /* Too few available compute units per SH. Disallowing
4793 * VS to run on one CU could hurt us more than late VS
4794 * allocation would help.
4795 *
4796 * 2 is the highest safe number that allows us to keep
4797 * all CUs enabled.
4798 */
4799 late_alloc_limit = 2;
4800 } else {
4801 /* This is a good initial value, allowing 1 late_alloc
4802 * wave per SIMD on num_cu - 2.
4803 */
4804 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4805
4806 /* The limit is 0-based, so 0 means 1. */
4807 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4808 late_alloc_limit -= 1;
4809 }
4810
4811 /* VS can't execute on one CU if the limit is > 2. */
4812 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4813 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4814 S_00B118_WAVE_LIMIT(0x3F));
4815 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4816 S_00B11C_LIMIT(late_alloc_limit));
4817 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4818 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4819 }
4820
4821 if (sctx->chip_class >= VI) {
4822 unsigned vgt_tess_distribution;
4823
4824 vgt_tess_distribution =
4825 S_028B50_ACCUM_ISOLINE(32) |
4826 S_028B50_ACCUM_TRI(11) |
4827 S_028B50_ACCUM_QUAD(11) |
4828 S_028B50_DONUT_SPLIT(16);
4829
4830 /* Testing with Unigine Heaven extreme tesselation yielded best results
4831 * with TRAP_SPLIT = 3.
4832 */
4833 if (sctx->family == CHIP_FIJI ||
4834 sctx->family >= CHIP_POLARIS10)
4835 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4836
4837 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4838 } else if (!has_clear_state) {
4839 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4840 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4841 }
4842
4843 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4844 if (sctx->chip_class >= CIK) {
4845 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4846 S_028084_ADDRESS(border_color_va >> 40));
4847 }
4848 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4849 RADEON_PRIO_BORDER_COLORS);
4850
4851 if (sctx->chip_class >= GFX9) {
4852 unsigned num_se = sscreen->info.max_se;
4853 unsigned pc_lines = 0;
4854
4855 switch (sctx->family) {
4856 case CHIP_VEGA10:
4857 case CHIP_VEGA12:
4858 pc_lines = 4096;
4859 break;
4860 case CHIP_RAVEN:
4861 pc_lines = 1024;
4862 break;
4863 default:
4864 assert(0);
4865 }
4866
4867 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4868 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4869 S_028C48_MAX_PRIM_PER_BATCH(1023));
4870 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4871 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4872 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4873 }
4874
4875 si_pm4_upload_indirect_buffer(sctx, pm4);
4876 sctx->init_config = pm4;
4877 }