2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
38 /* Initialize an external atom (owned by ../radeon). */
40 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
41 struct r600_atom
**list_elem
)
43 atom
->id
= list_elem
- sctx
->atoms
.array
+ 1;
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
49 struct r600_atom
**list_elem
,
50 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
52 atom
->emit
= (void*)emit_func
;
53 atom
->id
= list_elem
- sctx
->atoms
.array
+ 1; /* index+1 in the atom array */
57 static unsigned si_map_swizzle(unsigned swizzle
)
61 return V_008F0C_SQ_SEL_Y
;
63 return V_008F0C_SQ_SEL_Z
;
65 return V_008F0C_SQ_SEL_W
;
67 return V_008F0C_SQ_SEL_0
;
69 return V_008F0C_SQ_SEL_1
;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X
;
75 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
77 return value
* (1 << frac_bits
);
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x
)
84 x
>= 4096 ? 0xffff : x
* 16;
88 * Inferred framebuffer and blender state.
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
93 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
95 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
96 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
97 uint32_t cb_target_mask
, i
;
99 /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
101 cb_target_mask
= blend
->cb_target_mask
;
103 cb_target_mask
= 0xffffffff;
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
111 if (blend
&& blend
->dual_src_blend
&&
112 sctx
->ps_shader
.cso
&&
113 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
116 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
118 /* STONEY-specific register settings. */
119 if (sctx
->b
.family
== CHIP_STONEY
) {
120 unsigned spi_shader_col_format
=
121 sctx
->ps_shader
.cso
?
122 sctx
->ps_shader
.current
->key
.ps
.epilog
.spi_shader_col_format
: 0;
123 unsigned sx_ps_downconvert
= 0;
124 unsigned sx_blend_opt_epsilon
= 0;
125 unsigned sx_blend_opt_control
= 0;
127 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
128 struct r600_surface
*surf
=
129 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
130 unsigned format
, swap
, spi_format
, colormask
;
131 bool has_alpha
, has_rgb
;
136 format
= G_028C70_FORMAT(surf
->cb_color_info
);
137 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
138 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
139 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
141 /* Set if RGB and A are present. */
142 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
144 if (format
== V_028C70_COLOR_8
||
145 format
== V_028C70_COLOR_16
||
146 format
== V_028C70_COLOR_32
)
147 has_rgb
= !has_alpha
;
151 /* Check the colormask and export format. */
152 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
154 if (!(colormask
& PIPE_MASK_A
))
157 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
162 /* Disable value checking for disabled channels. */
164 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
166 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
168 /* Enable down-conversion for 32bpp and smaller formats. */
170 case V_028C70_COLOR_8
:
171 case V_028C70_COLOR_8_8
:
172 case V_028C70_COLOR_8_8_8_8
:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
175 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
176 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
177 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
178 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
182 case V_028C70_COLOR_5_6_5
:
183 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
184 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
185 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
189 case V_028C70_COLOR_1_5_5_5
:
190 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
191 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
192 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
196 case V_028C70_COLOR_4_4_4_4
:
197 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
198 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
199 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
203 case V_028C70_COLOR_32
:
204 if (swap
== V_0280A0_SWAP_STD
&&
205 spi_format
== V_028714_SPI_SHADER_32_R
)
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
207 else if (swap
== V_0280A0_SWAP_ALT_REV
&&
208 spi_format
== V_028714_SPI_SHADER_32_AR
)
209 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
212 case V_028C70_COLOR_16
:
213 case V_028C70_COLOR_16_16
:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
216 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
217 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
218 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
219 if (swap
== V_0280A0_SWAP_STD
||
220 swap
== V_0280A0_SWAP_STD_REV
)
221 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
227 case V_028C70_COLOR_10_11_11
:
228 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
229 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
230 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
234 case V_028C70_COLOR_2_10_10_10
:
235 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
236 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
237 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
243 if (sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
) {
244 sx_ps_downconvert
= 0;
245 sx_blend_opt_epsilon
= 0;
246 sx_blend_opt_control
= 0;
249 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
250 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 static uint32_t si_translate_blend_function(int blend_func
)
262 switch (blend_func
) {
264 return V_028780_COMB_DST_PLUS_SRC
;
265 case PIPE_BLEND_SUBTRACT
:
266 return V_028780_COMB_SRC_MINUS_DST
;
267 case PIPE_BLEND_REVERSE_SUBTRACT
:
268 return V_028780_COMB_DST_MINUS_SRC
;
270 return V_028780_COMB_MIN_DST_SRC
;
272 return V_028780_COMB_MAX_DST_SRC
;
274 R600_ERR("Unknown blend function %d\n", blend_func
);
281 static uint32_t si_translate_blend_factor(int blend_fact
)
283 switch (blend_fact
) {
284 case PIPE_BLENDFACTOR_ONE
:
285 return V_028780_BLEND_ONE
;
286 case PIPE_BLENDFACTOR_SRC_COLOR
:
287 return V_028780_BLEND_SRC_COLOR
;
288 case PIPE_BLENDFACTOR_SRC_ALPHA
:
289 return V_028780_BLEND_SRC_ALPHA
;
290 case PIPE_BLENDFACTOR_DST_ALPHA
:
291 return V_028780_BLEND_DST_ALPHA
;
292 case PIPE_BLENDFACTOR_DST_COLOR
:
293 return V_028780_BLEND_DST_COLOR
;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
296 case PIPE_BLENDFACTOR_CONST_COLOR
:
297 return V_028780_BLEND_CONSTANT_COLOR
;
298 case PIPE_BLENDFACTOR_CONST_ALPHA
:
299 return V_028780_BLEND_CONSTANT_ALPHA
;
300 case PIPE_BLENDFACTOR_ZERO
:
301 return V_028780_BLEND_ZERO
;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
314 case PIPE_BLENDFACTOR_SRC1_COLOR
:
315 return V_028780_BLEND_SRC1_COLOR
;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
317 return V_028780_BLEND_SRC1_ALPHA
;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
319 return V_028780_BLEND_INV_SRC1_COLOR
;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
321 return V_028780_BLEND_INV_SRC1_ALPHA
;
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
330 static uint32_t si_translate_blend_opt_function(int blend_func
)
332 switch (blend_func
) {
334 return V_028760_OPT_COMB_ADD
;
335 case PIPE_BLEND_SUBTRACT
:
336 return V_028760_OPT_COMB_SUBTRACT
;
337 case PIPE_BLEND_REVERSE_SUBTRACT
:
338 return V_028760_OPT_COMB_REVSUBTRACT
;
340 return V_028760_OPT_COMB_MIN
;
342 return V_028760_OPT_COMB_MAX
;
344 return V_028760_OPT_COMB_BLEND_DISABLED
;
348 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
350 switch (blend_fact
) {
351 case PIPE_BLENDFACTOR_ZERO
:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
353 case PIPE_BLENDFACTOR_ONE
:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
355 case PIPE_BLENDFACTOR_SRC_COLOR
:
356 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
359 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
361 case PIPE_BLENDFACTOR_SRC_ALPHA
:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
378 unsigned *dst_factor
, unsigned expected_dst
,
379 unsigned replacement_src
)
381 if (*src_factor
== expected_dst
&&
382 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
383 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
384 *dst_factor
= replacement_src
;
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func
== PIPE_BLEND_SUBTRACT
)
388 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
389 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
390 *func
= PIPE_BLEND_SUBTRACT
;
394 static bool si_blend_factor_uses_dst(unsigned factor
)
396 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
397 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
398 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
399 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
400 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
403 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
404 const struct pipe_blend_state
*state
,
407 struct si_context
*sctx
= (struct si_context
*)ctx
;
408 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
409 struct si_pm4_state
*pm4
= &blend
->pm4
;
410 uint32_t sx_mrt_blend_opt
[8] = {0};
411 uint32_t color_control
= 0;
416 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
417 blend
->alpha_to_one
= state
->alpha_to_one
;
418 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
420 if (state
->logicop_enable
) {
421 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
423 color_control
|= S_028808_ROP3(0xcc);
426 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433 if (state
->alpha_to_coverage
)
434 blend
->need_src_alpha_4bit
|= 0xf;
436 blend
->cb_target_mask
= 0;
437 for (int i
= 0; i
< 8; i
++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j
= state
->independent_blend_enable
? i
: 0;
441 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
442 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
443 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
444 unsigned eqA
= state
->rt
[j
].alpha_func
;
445 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
446 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
448 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
449 unsigned blend_cntl
= 0;
451 sx_mrt_blend_opt
[i
] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i
>= 1 && blend
->dual_src_blend
)
459 /* Only addition and subtraction equations are supported with
460 * dual source blending.
462 if (blend
->dual_src_blend
&&
463 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
464 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
465 assert(!"Unsupported equation for dual source blending");
469 if (!state
->rt
[j
].colormask
)
472 /* cb_render_state will disable unused ones */
473 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
475 if (!state
->rt
[j
].blend_enable
) {
476 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
480 /* Blending optimizations for Stoney.
481 * These transformations don't change the behavior.
483 * First, get rid of DST in the blend factors:
484 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
486 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
487 PIPE_BLENDFACTOR_DST_COLOR
,
488 PIPE_BLENDFACTOR_SRC_COLOR
);
489 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
490 PIPE_BLENDFACTOR_DST_COLOR
,
491 PIPE_BLENDFACTOR_SRC_COLOR
);
492 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
493 PIPE_BLENDFACTOR_DST_ALPHA
,
494 PIPE_BLENDFACTOR_SRC_ALPHA
);
496 /* Look up the ideal settings from tables. */
497 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
498 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
499 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
500 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
502 /* Handle interdependencies. */
503 if (si_blend_factor_uses_dst(srcRGB
))
504 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
505 if (si_blend_factor_uses_dst(srcA
))
506 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
508 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
509 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
510 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
511 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
512 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
514 /* Set the final value. */
515 sx_mrt_blend_opt
[i
] =
516 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
517 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
518 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
519 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
520 S_028760_ALPHA_DST_OPT(dstA_opt
) |
521 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
523 /* Set blend state. */
524 blend_cntl
|= S_028780_ENABLE(1);
525 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
526 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
527 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
529 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
530 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
531 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
532 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
533 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
535 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
537 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
539 /* This is only important for formats without alpha. */
540 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
541 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
542 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
543 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
544 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
545 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
546 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
549 if (blend
->cb_target_mask
) {
550 color_control
|= S_028808_MODE(mode
);
552 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
555 if (sctx
->b
.family
== CHIP_STONEY
) {
556 for (int i
= 0; i
< 8; i
++)
557 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
558 sx_mrt_blend_opt
[i
]);
560 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
561 if (blend
->dual_src_blend
|| state
->logicop_enable
||
562 mode
== V_028808_CB_RESOLVE
)
563 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
566 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
570 static void *si_create_blend_state(struct pipe_context
*ctx
,
571 const struct pipe_blend_state
*state
)
573 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
576 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
578 struct si_context
*sctx
= (struct si_context
*)ctx
;
579 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
580 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
581 sctx
->do_update_shaders
= true;
584 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
586 struct si_context
*sctx
= (struct si_context
*)ctx
;
587 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
590 static void si_set_blend_color(struct pipe_context
*ctx
,
591 const struct pipe_blend_color
*state
)
593 struct si_context
*sctx
= (struct si_context
*)ctx
;
595 if (memcmp(&sctx
->blend_color
.state
, state
, sizeof(*state
)) == 0)
598 sctx
->blend_color
.state
= *state
;
599 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
602 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
604 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
606 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
607 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
614 static void si_set_clip_state(struct pipe_context
*ctx
,
615 const struct pipe_clip_state
*state
)
617 struct si_context
*sctx
= (struct si_context
*)ctx
;
618 struct pipe_constant_buffer cb
;
620 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
623 sctx
->clip_state
.state
= *state
;
624 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
627 cb
.user_buffer
= state
->ucp
;
628 cb
.buffer_offset
= 0;
629 cb
.buffer_size
= 4*4*8;
630 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
631 pipe_resource_reference(&cb
.buffer
, NULL
);
634 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
636 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
638 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
639 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
642 #define SIX_BITS 0x3F
644 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
646 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
647 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
648 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
649 unsigned window_space
=
650 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
651 unsigned clipdist_mask
=
652 info
->writes_clipvertex
? SIX_BITS
: info
->clipdist_writemask
;
653 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
654 unsigned culldist_mask
= info
->culldist_writemask
<< info
->num_written_clipdistance
;
655 unsigned total_mask
= clipdist_mask
| culldist_mask
;
657 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
658 S_02881C_USE_VTX_POINT_SIZE(info
->writes_psize
) |
659 S_02881C_USE_VTX_EDGE_FLAG(info
->writes_edgeflag
) |
660 S_02881C_USE_VTX_RENDER_TARGET_INDX(info
->writes_layer
) |
661 S_02881C_USE_VTX_VIEWPORT_INDX(info
->writes_viewport_index
) |
662 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
663 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
664 S_02881C_VS_OUT_MISC_VEC_ENA(info
->writes_psize
||
665 info
->writes_edgeflag
||
666 info
->writes_layer
||
667 info
->writes_viewport_index
) |
668 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
669 (rs
->clip_plane_enable
&
670 clipdist_mask
) | (culldist_mask
<< 8));
671 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
672 rs
->pa_cl_clip_cntl
|
674 S_028810_CLIP_DISABLE(window_space
));
676 /* reuse needs to be set off if we write oViewport */
677 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
678 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
682 * inferred state between framebuffer and rasterizer
684 static void si_update_poly_offset_state(struct si_context
*sctx
)
686 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
688 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
)
691 /* Use the user format, not db_render_format, so that the polygon
692 * offset behaves as expected by applications.
694 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
695 case PIPE_FORMAT_Z16_UNORM
:
696 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
698 default: /* 24-bit */
699 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
701 case PIPE_FORMAT_Z32_FLOAT
:
702 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
703 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
712 static uint32_t si_translate_fill(uint32_t func
)
715 case PIPE_POLYGON_MODE_FILL
:
716 return V_028814_X_DRAW_TRIANGLES
;
717 case PIPE_POLYGON_MODE_LINE
:
718 return V_028814_X_DRAW_LINES
;
719 case PIPE_POLYGON_MODE_POINT
:
720 return V_028814_X_DRAW_POINTS
;
723 return V_028814_X_DRAW_POINTS
;
727 static void *si_create_rs_state(struct pipe_context
*ctx
,
728 const struct pipe_rasterizer_state
*state
)
730 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
731 struct si_pm4_state
*pm4
= &rs
->pm4
;
733 float psize_min
, psize_max
;
739 rs
->scissor_enable
= state
->scissor
;
740 rs
->clip_halfz
= state
->clip_halfz
;
741 rs
->two_side
= state
->light_twoside
;
742 rs
->multisample_enable
= state
->multisample
;
743 rs
->force_persample_interp
= state
->force_persample_interp
;
744 rs
->clip_plane_enable
= state
->clip_plane_enable
;
745 rs
->line_stipple_enable
= state
->line_stipple_enable
;
746 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
747 rs
->line_smooth
= state
->line_smooth
;
748 rs
->poly_smooth
= state
->poly_smooth
;
749 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
751 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
752 rs
->flatshade
= state
->flatshade
;
753 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
754 rs
->rasterizer_discard
= state
->rasterizer_discard
;
755 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
756 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
757 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
758 rs
->pa_cl_clip_cntl
=
759 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
760 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
761 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
762 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
763 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
765 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
766 S_0286D4_FLAT_SHADE_ENA(1) |
767 S_0286D4_PNT_SPRITE_ENA(1) |
768 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
769 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
770 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
771 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
772 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
774 /* point size 12.4 fixed point */
775 tmp
= (unsigned)(state
->point_size
* 8.0);
776 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
778 if (state
->point_size_per_vertex
) {
779 psize_min
= util_get_min_point_size(state
);
782 /* Force the point size to be as if the vertex output was disabled. */
783 psize_min
= state
->point_size
;
784 psize_max
= state
->point_size
;
786 /* Divide by two, because 0.5 = 1 pixel. */
787 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
788 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
789 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
791 tmp
= (unsigned)state
->line_width
* 8;
792 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
793 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
794 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
795 S_028A48_MSAA_ENABLE(state
->multisample
||
796 state
->poly_smooth
||
797 state
->line_smooth
) |
798 S_028A48_VPORT_SCISSOR_ENABLE(1));
800 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
801 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
802 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
804 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
805 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
806 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
807 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
808 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
809 S_028814_FACE(!state
->front_ccw
) |
810 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
811 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
812 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
813 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
814 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
815 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
816 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
817 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+
818 SI_SGPR_VS_STATE_BITS
* 4, state
->clamp_vertex_color
);
820 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
821 for (i
= 0; i
< 3; i
++) {
822 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
823 float offset_units
= state
->offset_units
;
824 float offset_scale
= state
->offset_scale
* 16.0f
;
825 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
827 if (!state
->offset_units_unscaled
) {
829 case 0: /* 16-bit zbuffer */
830 offset_units
*= 4.0f
;
831 pa_su_poly_offset_db_fmt_cntl
=
832 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
834 case 1: /* 24-bit zbuffer */
835 offset_units
*= 2.0f
;
836 pa_su_poly_offset_db_fmt_cntl
=
837 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
839 case 2: /* 32-bit zbuffer */
840 offset_units
*= 1.0f
;
841 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
842 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
847 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
849 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
851 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
853 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
855 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
856 pa_su_poly_offset_db_fmt_cntl
);
862 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
864 struct si_context
*sctx
= (struct si_context
*)ctx
;
865 struct si_state_rasterizer
*old_rs
=
866 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
867 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
872 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
873 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
875 /* Update the small primitive filter workaround if necessary. */
876 if (sctx
->b
.family
>= CHIP_POLARIS10
&&
877 sctx
->framebuffer
.nr_samples
> 1)
878 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
881 r600_viewport_set_rast_deps(&sctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
883 si_pm4_bind_state(sctx
, rasterizer
, rs
);
884 si_update_poly_offset_state(sctx
);
886 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
887 sctx
->do_update_shaders
= true;
890 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
892 struct si_context
*sctx
= (struct si_context
*)ctx
;
894 if (sctx
->queued
.named
.rasterizer
== state
)
895 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
896 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
900 * infeered state between dsa and stencil ref
902 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
904 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
905 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
906 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
908 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
909 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
910 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
911 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
912 S_028430_STENCILOPVAL(1));
913 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
914 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
915 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
916 S_028434_STENCILOPVAL_BF(1));
919 static void si_set_stencil_ref(struct pipe_context
*ctx
,
920 const struct pipe_stencil_ref
*state
)
922 struct si_context
*sctx
= (struct si_context
*)ctx
;
924 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
927 sctx
->stencil_ref
.state
= *state
;
928 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
936 static uint32_t si_translate_stencil_op(int s_op
)
939 case PIPE_STENCIL_OP_KEEP
:
940 return V_02842C_STENCIL_KEEP
;
941 case PIPE_STENCIL_OP_ZERO
:
942 return V_02842C_STENCIL_ZERO
;
943 case PIPE_STENCIL_OP_REPLACE
:
944 return V_02842C_STENCIL_REPLACE_TEST
;
945 case PIPE_STENCIL_OP_INCR
:
946 return V_02842C_STENCIL_ADD_CLAMP
;
947 case PIPE_STENCIL_OP_DECR
:
948 return V_02842C_STENCIL_SUB_CLAMP
;
949 case PIPE_STENCIL_OP_INCR_WRAP
:
950 return V_02842C_STENCIL_ADD_WRAP
;
951 case PIPE_STENCIL_OP_DECR_WRAP
:
952 return V_02842C_STENCIL_SUB_WRAP
;
953 case PIPE_STENCIL_OP_INVERT
:
954 return V_02842C_STENCIL_INVERT
;
956 R600_ERR("Unknown stencil op %d", s_op
);
963 static void *si_create_dsa_state(struct pipe_context
*ctx
,
964 const struct pipe_depth_stencil_alpha_state
*state
)
966 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
967 struct si_pm4_state
*pm4
= &dsa
->pm4
;
968 unsigned db_depth_control
;
969 uint32_t db_stencil_control
= 0;
975 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
976 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
977 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
978 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
980 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
981 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
982 S_028800_ZFUNC(state
->depth
.func
) |
983 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
986 if (state
->stencil
[0].enabled
) {
987 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
988 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
989 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
990 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
991 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
993 if (state
->stencil
[1].enabled
) {
994 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
995 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
996 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
997 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
998 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1003 if (state
->alpha
.enabled
) {
1004 dsa
->alpha_func
= state
->alpha
.func
;
1006 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1007 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1009 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1012 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1013 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1014 if (state
->depth
.bounds_test
) {
1015 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1016 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1022 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1024 struct si_context
*sctx
= (struct si_context
*)ctx
;
1025 struct si_state_dsa
*dsa
= state
;
1030 si_pm4_bind_state(sctx
, dsa
, dsa
);
1032 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1033 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1034 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1035 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1037 sctx
->do_update_shaders
= true;
1040 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1042 struct si_context
*sctx
= (struct si_context
*)ctx
;
1043 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1046 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1048 struct pipe_depth_stencil_alpha_state dsa
= {};
1050 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1053 /* DB RENDER STATE */
1055 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1057 struct si_context
*sctx
= (struct si_context
*)ctx
;
1059 /* Pipeline stat & streamout queries. */
1061 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1062 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1064 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1065 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1068 /* Occlusion queries. */
1069 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1070 sctx
->occlusion_queries_disabled
= !enable
;
1071 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1075 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
1077 struct si_context
*sctx
= (struct si_context
*)ctx
;
1079 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1082 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1084 struct si_context
*sctx
= (struct si_context
*)ctx
;
1086 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1088 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1089 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1092 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1094 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1095 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1096 unsigned db_shader_control
;
1098 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1100 /* DB_RENDER_CONTROL */
1101 if (sctx
->dbcb_depth_copy_enabled
||
1102 sctx
->dbcb_stencil_copy_enabled
) {
1104 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1105 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1106 S_028000_COPY_CENTROID(1) |
1107 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1108 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1110 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1111 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1114 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1115 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1118 /* DB_COUNT_CONTROL (occlusion queries) */
1119 if (sctx
->b
.num_occlusion_queries
> 0 &&
1120 !sctx
->occlusion_queries_disabled
) {
1121 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1123 if (sctx
->b
.chip_class
>= CIK
) {
1125 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1126 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1127 S_028004_ZPASS_ENABLE(1) |
1128 S_028004_SLICE_EVEN_ENABLE(1) |
1129 S_028004_SLICE_ODD_ENABLE(1));
1132 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1133 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1136 /* Disable occlusion queries. */
1137 if (sctx
->b
.chip_class
>= CIK
) {
1140 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1144 /* DB_RENDER_OVERRIDE2 */
1145 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1146 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1147 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1148 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1150 db_shader_control
= sctx
->ps_db_shader_control
;
1152 /* Bug workaround for smoothing (overrasterization) on SI. */
1153 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1154 db_shader_control
&= C_02880C_Z_ORDER
;
1155 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1158 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1159 if (!rs
|| !rs
->multisample_enable
)
1160 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1162 if (sctx
->b
.family
== CHIP_STONEY
&&
1163 sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
)
1164 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1166 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1171 * format translation
1173 static uint32_t si_translate_colorformat(enum pipe_format format
)
1175 const struct util_format_description
*desc
= util_format_description(format
);
1177 #define HAS_SIZE(x,y,z,w) \
1178 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1179 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1181 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1182 return V_028C70_COLOR_10_11_11
;
1184 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1185 return V_028C70_COLOR_INVALID
;
1187 /* hw cannot support mixed formats (except depth/stencil, since
1188 * stencil is not written to). */
1189 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1190 return V_028C70_COLOR_INVALID
;
1192 switch (desc
->nr_channels
) {
1194 switch (desc
->channel
[0].size
) {
1196 return V_028C70_COLOR_8
;
1198 return V_028C70_COLOR_16
;
1200 return V_028C70_COLOR_32
;
1204 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1205 switch (desc
->channel
[0].size
) {
1207 return V_028C70_COLOR_8_8
;
1209 return V_028C70_COLOR_16_16
;
1211 return V_028C70_COLOR_32_32
;
1213 } else if (HAS_SIZE(8,24,0,0)) {
1214 return V_028C70_COLOR_24_8
;
1215 } else if (HAS_SIZE(24,8,0,0)) {
1216 return V_028C70_COLOR_8_24
;
1220 if (HAS_SIZE(5,6,5,0)) {
1221 return V_028C70_COLOR_5_6_5
;
1222 } else if (HAS_SIZE(32,8,24,0)) {
1223 return V_028C70_COLOR_X24_8_32_FLOAT
;
1227 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1228 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1229 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1230 switch (desc
->channel
[0].size
) {
1232 return V_028C70_COLOR_4_4_4_4
;
1234 return V_028C70_COLOR_8_8_8_8
;
1236 return V_028C70_COLOR_16_16_16_16
;
1238 return V_028C70_COLOR_32_32_32_32
;
1240 } else if (HAS_SIZE(5,5,5,1)) {
1241 return V_028C70_COLOR_1_5_5_5
;
1242 } else if (HAS_SIZE(10,10,10,2)) {
1243 return V_028C70_COLOR_2_10_10_10
;
1247 return V_028C70_COLOR_INVALID
;
1250 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1252 if (SI_BIG_ENDIAN
) {
1253 switch(colorformat
) {
1254 /* 8-bit buffers. */
1255 case V_028C70_COLOR_8
:
1256 return V_028C70_ENDIAN_NONE
;
1258 /* 16-bit buffers. */
1259 case V_028C70_COLOR_5_6_5
:
1260 case V_028C70_COLOR_1_5_5_5
:
1261 case V_028C70_COLOR_4_4_4_4
:
1262 case V_028C70_COLOR_16
:
1263 case V_028C70_COLOR_8_8
:
1264 return V_028C70_ENDIAN_8IN16
;
1266 /* 32-bit buffers. */
1267 case V_028C70_COLOR_8_8_8_8
:
1268 case V_028C70_COLOR_2_10_10_10
:
1269 case V_028C70_COLOR_8_24
:
1270 case V_028C70_COLOR_24_8
:
1271 case V_028C70_COLOR_16_16
:
1272 return V_028C70_ENDIAN_8IN32
;
1274 /* 64-bit buffers. */
1275 case V_028C70_COLOR_16_16_16_16
:
1276 return V_028C70_ENDIAN_8IN16
;
1278 case V_028C70_COLOR_32_32
:
1279 return V_028C70_ENDIAN_8IN32
;
1281 /* 128-bit buffers. */
1282 case V_028C70_COLOR_32_32_32_32
:
1283 return V_028C70_ENDIAN_8IN32
;
1285 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1288 return V_028C70_ENDIAN_NONE
;
1292 static uint32_t si_translate_dbformat(enum pipe_format format
)
1295 case PIPE_FORMAT_Z16_UNORM
:
1296 return V_028040_Z_16
;
1297 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1298 case PIPE_FORMAT_X8Z24_UNORM
:
1299 case PIPE_FORMAT_Z24X8_UNORM
:
1300 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1301 return V_028040_Z_24
; /* deprecated on SI */
1302 case PIPE_FORMAT_Z32_FLOAT
:
1303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1304 return V_028040_Z_32_FLOAT
;
1306 return V_028040_Z_INVALID
;
1311 * Texture translation
1314 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1315 enum pipe_format format
,
1316 const struct util_format_description
*desc
,
1319 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1320 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1321 sscreen
->b
.info
.drm_minor
>= 31) ||
1322 sscreen
->b
.info
.drm_major
== 3;
1323 bool uniform
= true;
1326 /* Colorspace (return non-RGB formats directly). */
1327 switch (desc
->colorspace
) {
1328 /* Depth stencil formats */
1329 case UTIL_FORMAT_COLORSPACE_ZS
:
1331 case PIPE_FORMAT_Z16_UNORM
:
1332 return V_008F14_IMG_DATA_FORMAT_16
;
1333 case PIPE_FORMAT_X24S8_UINT
:
1334 case PIPE_FORMAT_Z24X8_UNORM
:
1335 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1336 return V_008F14_IMG_DATA_FORMAT_8_24
;
1337 case PIPE_FORMAT_X8Z24_UNORM
:
1338 case PIPE_FORMAT_S8X24_UINT
:
1339 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1340 return V_008F14_IMG_DATA_FORMAT_24_8
;
1341 case PIPE_FORMAT_S8_UINT
:
1342 return V_008F14_IMG_DATA_FORMAT_8
;
1343 case PIPE_FORMAT_Z32_FLOAT
:
1344 return V_008F14_IMG_DATA_FORMAT_32
;
1345 case PIPE_FORMAT_X32_S8X24_UINT
:
1346 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1347 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1352 case UTIL_FORMAT_COLORSPACE_YUV
:
1353 goto out_unknown
; /* TODO */
1355 case UTIL_FORMAT_COLORSPACE_SRGB
:
1356 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1364 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1365 if (!enable_compressed_formats
)
1369 case PIPE_FORMAT_RGTC1_SNORM
:
1370 case PIPE_FORMAT_LATC1_SNORM
:
1371 case PIPE_FORMAT_RGTC1_UNORM
:
1372 case PIPE_FORMAT_LATC1_UNORM
:
1373 return V_008F14_IMG_DATA_FORMAT_BC4
;
1374 case PIPE_FORMAT_RGTC2_SNORM
:
1375 case PIPE_FORMAT_LATC2_SNORM
:
1376 case PIPE_FORMAT_RGTC2_UNORM
:
1377 case PIPE_FORMAT_LATC2_UNORM
:
1378 return V_008F14_IMG_DATA_FORMAT_BC5
;
1384 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1385 sscreen
->b
.family
== CHIP_STONEY
) {
1387 case PIPE_FORMAT_ETC1_RGB8
:
1388 case PIPE_FORMAT_ETC2_RGB8
:
1389 case PIPE_FORMAT_ETC2_SRGB8
:
1390 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1391 case PIPE_FORMAT_ETC2_RGB8A1
:
1392 case PIPE_FORMAT_ETC2_SRGB8A1
:
1393 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1394 case PIPE_FORMAT_ETC2_RGBA8
:
1395 case PIPE_FORMAT_ETC2_SRGBA8
:
1396 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1397 case PIPE_FORMAT_ETC2_R11_UNORM
:
1398 case PIPE_FORMAT_ETC2_R11_SNORM
:
1399 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1400 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1401 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1402 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1408 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1409 if (!enable_compressed_formats
)
1413 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1414 case PIPE_FORMAT_BPTC_SRGBA
:
1415 return V_008F14_IMG_DATA_FORMAT_BC7
;
1416 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1417 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1418 return V_008F14_IMG_DATA_FORMAT_BC6
;
1424 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1426 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1427 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1428 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1429 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1430 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1431 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1437 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1438 if (!enable_compressed_formats
)
1441 if (!util_format_s3tc_enabled
) {
1446 case PIPE_FORMAT_DXT1_RGB
:
1447 case PIPE_FORMAT_DXT1_RGBA
:
1448 case PIPE_FORMAT_DXT1_SRGB
:
1449 case PIPE_FORMAT_DXT1_SRGBA
:
1450 return V_008F14_IMG_DATA_FORMAT_BC1
;
1451 case PIPE_FORMAT_DXT3_RGBA
:
1452 case PIPE_FORMAT_DXT3_SRGBA
:
1453 return V_008F14_IMG_DATA_FORMAT_BC2
;
1454 case PIPE_FORMAT_DXT5_RGBA
:
1455 case PIPE_FORMAT_DXT5_SRGBA
:
1456 return V_008F14_IMG_DATA_FORMAT_BC3
;
1462 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1463 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1464 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1465 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1468 /* R8G8Bx_SNORM - TODO CxV8U8 */
1470 /* hw cannot support mixed formats (except depth/stencil, since only
1472 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1475 /* See whether the components are of the same size. */
1476 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1477 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1480 /* Non-uniform formats. */
1482 switch(desc
->nr_channels
) {
1484 if (desc
->channel
[0].size
== 5 &&
1485 desc
->channel
[1].size
== 6 &&
1486 desc
->channel
[2].size
== 5) {
1487 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1491 if (desc
->channel
[0].size
== 5 &&
1492 desc
->channel
[1].size
== 5 &&
1493 desc
->channel
[2].size
== 5 &&
1494 desc
->channel
[3].size
== 1) {
1495 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1497 if (desc
->channel
[0].size
== 10 &&
1498 desc
->channel
[1].size
== 10 &&
1499 desc
->channel
[2].size
== 10 &&
1500 desc
->channel
[3].size
== 2) {
1501 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1508 if (first_non_void
< 0 || first_non_void
> 3)
1511 /* uniform formats */
1512 switch (desc
->channel
[first_non_void
].size
) {
1514 switch (desc
->nr_channels
) {
1515 #if 0 /* Not supported for render targets */
1517 return V_008F14_IMG_DATA_FORMAT_4_4
;
1520 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1524 switch (desc
->nr_channels
) {
1526 return V_008F14_IMG_DATA_FORMAT_8
;
1528 return V_008F14_IMG_DATA_FORMAT_8_8
;
1530 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1534 switch (desc
->nr_channels
) {
1536 return V_008F14_IMG_DATA_FORMAT_16
;
1538 return V_008F14_IMG_DATA_FORMAT_16_16
;
1540 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1544 switch (desc
->nr_channels
) {
1546 return V_008F14_IMG_DATA_FORMAT_32
;
1548 return V_008F14_IMG_DATA_FORMAT_32_32
;
1549 #if 0 /* Not supported for render targets */
1551 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1554 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1559 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1563 static unsigned si_tex_wrap(unsigned wrap
)
1567 case PIPE_TEX_WRAP_REPEAT
:
1568 return V_008F30_SQ_TEX_WRAP
;
1569 case PIPE_TEX_WRAP_CLAMP
:
1570 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1571 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1572 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1573 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1574 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1575 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1576 return V_008F30_SQ_TEX_MIRROR
;
1577 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1578 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1579 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1580 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1581 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1582 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1586 static unsigned si_tex_mipfilter(unsigned filter
)
1589 case PIPE_TEX_MIPFILTER_NEAREST
:
1590 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1591 case PIPE_TEX_MIPFILTER_LINEAR
:
1592 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1594 case PIPE_TEX_MIPFILTER_NONE
:
1595 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1599 static unsigned si_tex_compare(unsigned compare
)
1603 case PIPE_FUNC_NEVER
:
1604 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1605 case PIPE_FUNC_LESS
:
1606 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1607 case PIPE_FUNC_EQUAL
:
1608 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1609 case PIPE_FUNC_LEQUAL
:
1610 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1611 case PIPE_FUNC_GREATER
:
1612 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1613 case PIPE_FUNC_NOTEQUAL
:
1614 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1615 case PIPE_FUNC_GEQUAL
:
1616 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1617 case PIPE_FUNC_ALWAYS
:
1618 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1622 static unsigned si_tex_dim(unsigned res_target
, unsigned view_target
,
1623 unsigned nr_samples
)
1625 if (view_target
== PIPE_TEXTURE_CUBE
||
1626 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1627 res_target
= view_target
;
1628 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1629 else if (res_target
== PIPE_TEXTURE_CUBE
||
1630 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1631 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1633 switch (res_target
) {
1635 case PIPE_TEXTURE_1D
:
1636 return V_008F1C_SQ_RSRC_IMG_1D
;
1637 case PIPE_TEXTURE_1D_ARRAY
:
1638 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1639 case PIPE_TEXTURE_2D
:
1640 case PIPE_TEXTURE_RECT
:
1641 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1642 V_008F1C_SQ_RSRC_IMG_2D
;
1643 case PIPE_TEXTURE_2D_ARRAY
:
1644 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1645 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1646 case PIPE_TEXTURE_3D
:
1647 return V_008F1C_SQ_RSRC_IMG_3D
;
1648 case PIPE_TEXTURE_CUBE
:
1649 case PIPE_TEXTURE_CUBE_ARRAY
:
1650 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1655 * Format support testing
1658 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1660 return si_translate_texformat(screen
, format
, util_format_description(format
),
1661 util_format_get_first_non_void_channel(format
)) != ~0U;
1664 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1665 const struct util_format_description
*desc
,
1671 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1672 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1674 assert(first_non_void
>= 0);
1675 type
= desc
->channel
[first_non_void
].type
;
1677 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1678 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1680 if (desc
->nr_channels
== 4 &&
1681 desc
->channel
[0].size
== 10 &&
1682 desc
->channel
[1].size
== 10 &&
1683 desc
->channel
[2].size
== 10 &&
1684 desc
->channel
[3].size
== 2)
1685 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1687 /* See whether the components are of the same size. */
1688 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1689 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1690 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1693 switch (desc
->channel
[first_non_void
].size
) {
1695 switch (desc
->nr_channels
) {
1697 return V_008F0C_BUF_DATA_FORMAT_8
;
1699 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1702 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1706 switch (desc
->nr_channels
) {
1708 return V_008F0C_BUF_DATA_FORMAT_16
;
1710 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1713 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1717 /* From the Southern Islands ISA documentation about MTBUF:
1718 * 'Memory reads of data in memory that is 32 or 64 bits do not
1719 * undergo any format conversion.'
1721 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1722 !desc
->channel
[first_non_void
].pure_integer
)
1723 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1725 switch (desc
->nr_channels
) {
1727 return V_008F0C_BUF_DATA_FORMAT_32
;
1729 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1731 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1733 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1738 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1741 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1742 const struct util_format_description
*desc
,
1745 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1746 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1748 assert(first_non_void
>= 0);
1750 switch (desc
->channel
[first_non_void
].type
) {
1751 case UTIL_FORMAT_TYPE_SIGNED
:
1752 if (desc
->channel
[first_non_void
].normalized
)
1753 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1754 else if (desc
->channel
[first_non_void
].pure_integer
)
1755 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1757 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1759 case UTIL_FORMAT_TYPE_UNSIGNED
:
1760 if (desc
->channel
[first_non_void
].normalized
)
1761 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1762 else if (desc
->channel
[first_non_void
].pure_integer
)
1763 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1765 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1767 case UTIL_FORMAT_TYPE_FLOAT
:
1769 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1773 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
1774 enum pipe_format format
,
1777 const struct util_format_description
*desc
;
1779 unsigned data_format
;
1781 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
1782 PIPE_BIND_SAMPLER_VIEW
|
1783 PIPE_BIND_VERTEX_BUFFER
)) == 0);
1785 desc
= util_format_description(format
);
1787 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1788 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1789 * for read-only access (with caveats surrounding bounds checks), but
1790 * obviously fails for write access which we have to implement for
1791 * shader images. Luckily, OpenGL doesn't expect this to be supported
1792 * anyway, and so the only impact is on PBO uploads / downloads, which
1793 * shouldn't be expected to be fast for GL_RGB anyway.
1795 if (desc
->block
.bits
== 3 * 8 ||
1796 desc
->block
.bits
== 3 * 16) {
1797 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
1798 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
1804 first_non_void
= util_format_get_first_non_void_channel(format
);
1805 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1806 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
1812 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1814 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1815 r600_translate_colorswap(format
, false) != ~0U;
1818 static bool si_is_zs_format_supported(enum pipe_format format
)
1820 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1823 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
1824 enum pipe_format format
,
1825 enum pipe_texture_target target
,
1826 unsigned sample_count
,
1829 unsigned retval
= 0;
1831 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1832 R600_ERR("r600: unsupported texture type %d\n", target
);
1836 if (!util_format_is_supported(format
, usage
))
1839 if (sample_count
> 1) {
1840 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1843 if (usage
& PIPE_BIND_SHADER_IMAGE
)
1846 switch (sample_count
) {
1852 if (format
== PIPE_FORMAT_NONE
)
1861 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
1862 PIPE_BIND_SHADER_IMAGE
)) {
1863 if (target
== PIPE_BUFFER
) {
1864 retval
|= si_is_vertex_format_supported(
1865 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
1866 PIPE_BIND_SHADER_IMAGE
));
1868 if (si_is_sampler_format_supported(screen
, format
))
1869 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
1870 PIPE_BIND_SHADER_IMAGE
);
1874 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1875 PIPE_BIND_DISPLAY_TARGET
|
1878 PIPE_BIND_BLENDABLE
)) &&
1879 si_is_colorbuffer_format_supported(format
)) {
1881 (PIPE_BIND_RENDER_TARGET
|
1882 PIPE_BIND_DISPLAY_TARGET
|
1885 if (!util_format_is_pure_integer(format
) &&
1886 !util_format_is_depth_or_stencil(format
))
1887 retval
|= usage
& PIPE_BIND_BLENDABLE
;
1890 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1891 si_is_zs_format_supported(format
)) {
1892 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1895 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
1896 retval
|= si_is_vertex_format_supported(screen
, format
,
1897 PIPE_BIND_VERTEX_BUFFER
);
1900 if ((usage
& PIPE_BIND_LINEAR
) &&
1901 !util_format_is_compressed(format
) &&
1902 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
1903 retval
|= PIPE_BIND_LINEAR
;
1905 return retval
== usage
;
1909 * framebuffer handling
1912 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
1913 unsigned format
, unsigned swap
,
1914 unsigned ntype
, bool is_depth
)
1916 /* Alpha is needed for alpha-to-coverage.
1917 * Blending may be with or without alpha.
1919 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
1920 unsigned alpha
= 0; /* exports alpha, but may not support blending */
1921 unsigned blend
= 0; /* supports blending, but may not export alpha */
1922 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
1924 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1925 * Other chips have multiple choices, though they are not necessarily better.
1928 case V_028C70_COLOR_5_6_5
:
1929 case V_028C70_COLOR_1_5_5_5
:
1930 case V_028C70_COLOR_5_5_5_1
:
1931 case V_028C70_COLOR_4_4_4_4
:
1932 case V_028C70_COLOR_10_11_11
:
1933 case V_028C70_COLOR_11_11_10
:
1934 case V_028C70_COLOR_8
:
1935 case V_028C70_COLOR_8_8
:
1936 case V_028C70_COLOR_8_8_8_8
:
1937 case V_028C70_COLOR_10_10_10_2
:
1938 case V_028C70_COLOR_2_10_10_10
:
1939 if (ntype
== V_028C70_NUMBER_UINT
)
1940 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
1941 else if (ntype
== V_028C70_NUMBER_SINT
)
1942 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
1944 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
1947 case V_028C70_COLOR_16
:
1948 case V_028C70_COLOR_16_16
:
1949 case V_028C70_COLOR_16_16_16_16
:
1950 if (ntype
== V_028C70_NUMBER_UNORM
||
1951 ntype
== V_028C70_NUMBER_SNORM
) {
1952 /* UNORM16 and SNORM16 don't support blending */
1953 if (ntype
== V_028C70_NUMBER_UNORM
)
1954 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
1956 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
1958 /* Use 32 bits per channel for blending. */
1959 if (format
== V_028C70_COLOR_16
) {
1960 if (swap
== V_028C70_SWAP_STD
) { /* R */
1961 blend
= V_028714_SPI_SHADER_32_R
;
1962 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
1963 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
1964 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
1967 } else if (format
== V_028C70_COLOR_16_16
) {
1968 if (swap
== V_028C70_SWAP_STD
) { /* RG */
1969 blend
= V_028714_SPI_SHADER_32_GR
;
1970 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
1971 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
1972 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
1975 } else /* 16_16_16_16 */
1976 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
1977 } else if (ntype
== V_028C70_NUMBER_UINT
)
1978 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
1979 else if (ntype
== V_028C70_NUMBER_SINT
)
1980 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
1981 else if (ntype
== V_028C70_NUMBER_FLOAT
)
1982 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
1987 case V_028C70_COLOR_32
:
1988 if (swap
== V_028C70_SWAP_STD
) { /* R */
1989 blend
= normal
= V_028714_SPI_SHADER_32_R
;
1990 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
1991 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
1992 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
1997 case V_028C70_COLOR_32_32
:
1998 if (swap
== V_028C70_SWAP_STD
) { /* RG */
1999 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2000 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2001 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2002 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2007 case V_028C70_COLOR_32_32_32_32
:
2008 case V_028C70_COLOR_8_24
:
2009 case V_028C70_COLOR_24_8
:
2010 case V_028C70_COLOR_X24_8_32_FLOAT
:
2011 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2019 /* The DB->CB copy needs 32_ABGR. */
2021 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2023 surf
->spi_shader_col_format
= normal
;
2024 surf
->spi_shader_col_format_alpha
= alpha
;
2025 surf
->spi_shader_col_format_blend
= blend
;
2026 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2029 static void si_initialize_color_surface(struct si_context
*sctx
,
2030 struct r600_surface
*surf
)
2032 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2033 unsigned color_info
, color_attrib
, color_view
;
2034 unsigned format
, swap
, ntype
, endian
;
2035 const struct util_format_description
*desc
;
2037 unsigned blend_clamp
= 0, blend_bypass
= 0;
2039 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2040 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2042 desc
= util_format_description(surf
->base
.format
);
2043 for (i
= 0; i
< 4; i
++) {
2044 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2048 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2049 ntype
= V_028C70_NUMBER_FLOAT
;
2051 ntype
= V_028C70_NUMBER_UNORM
;
2052 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2053 ntype
= V_028C70_NUMBER_SRGB
;
2054 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2055 if (desc
->channel
[i
].pure_integer
) {
2056 ntype
= V_028C70_NUMBER_SINT
;
2058 assert(desc
->channel
[i
].normalized
);
2059 ntype
= V_028C70_NUMBER_SNORM
;
2061 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2062 if (desc
->channel
[i
].pure_integer
) {
2063 ntype
= V_028C70_NUMBER_UINT
;
2065 assert(desc
->channel
[i
].normalized
);
2066 ntype
= V_028C70_NUMBER_UNORM
;
2071 format
= si_translate_colorformat(surf
->base
.format
);
2072 if (format
== V_028C70_COLOR_INVALID
) {
2073 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2075 assert(format
!= V_028C70_COLOR_INVALID
);
2076 swap
= r600_translate_colorswap(surf
->base
.format
, false);
2077 endian
= si_colorformat_endian_swap(format
);
2079 /* blend clamp should be set for all NORM/SRGB types */
2080 if (ntype
== V_028C70_NUMBER_UNORM
||
2081 ntype
== V_028C70_NUMBER_SNORM
||
2082 ntype
== V_028C70_NUMBER_SRGB
)
2085 /* set blend bypass according to docs if SINT/UINT or
2086 8/24 COLOR variants */
2087 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2088 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2089 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2094 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2095 (format
== V_028C70_COLOR_8
||
2096 format
== V_028C70_COLOR_8_8
||
2097 format
== V_028C70_COLOR_8_8_8_8
))
2098 surf
->color_is_int8
= true;
2100 color_info
= S_028C70_FORMAT(format
) |
2101 S_028C70_COMP_SWAP(swap
) |
2102 S_028C70_BLEND_CLAMP(blend_clamp
) |
2103 S_028C70_BLEND_BYPASS(blend_bypass
) |
2104 S_028C70_SIMPLE_FLOAT(1) |
2105 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2106 ntype
!= V_028C70_NUMBER_SNORM
&&
2107 ntype
!= V_028C70_NUMBER_SRGB
&&
2108 format
!= V_028C70_COLOR_8_24
&&
2109 format
!= V_028C70_COLOR_24_8
) |
2110 S_028C70_NUMBER_TYPE(ntype
) |
2111 S_028C70_ENDIAN(endian
);
2113 /* Intensity is implemented as Red, so treat it that way. */
2114 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2115 util_format_is_intensity(surf
->base
.format
));
2117 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2118 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2120 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2121 S_028C74_NUM_FRAGMENTS(log_samples
);
2123 if (rtex
->fmask
.size
) {
2124 color_info
|= S_028C70_COMPRESSION(1);
2125 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2127 if (sctx
->b
.chip_class
== SI
) {
2128 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2129 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2134 surf
->cb_color_view
= color_view
;
2135 surf
->cb_color_info
= color_info
;
2136 surf
->cb_color_attrib
= color_attrib
;
2138 if (sctx
->b
.chip_class
>= VI
) {
2139 unsigned max_uncompressed_block_size
= 2;
2141 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2142 if (rtex
->surface
.bpe
== 1)
2143 max_uncompressed_block_size
= 0;
2144 else if (rtex
->surface
.bpe
== 2)
2145 max_uncompressed_block_size
= 1;
2148 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2149 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2152 /* This must be set for fast clear to work without FMASK. */
2153 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2154 unsigned bankh
= util_logbase2(rtex
->surface
.bankh
);
2155 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2158 /* Determine pixel shader export format */
2159 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2161 surf
->color_initialized
= true;
2164 static void si_init_depth_surface(struct si_context
*sctx
,
2165 struct r600_surface
*surf
)
2167 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2168 unsigned level
= surf
->base
.u
.tex
.level
;
2169 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
2171 uint32_t z_info
, s_info
, db_depth_info
;
2172 uint64_t z_offs
, s_offs
;
2173 uint32_t db_htile_data_base
, db_htile_surface
;
2175 format
= si_translate_dbformat(rtex
->db_render_format
);
2177 if (format
== V_028040_Z_INVALID
) {
2178 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2180 assert(format
!= V_028040_Z_INVALID
);
2182 s_offs
= z_offs
= rtex
->resource
.gpu_address
;
2183 z_offs
+= rtex
->surface
.level
[level
].offset
;
2184 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
2186 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2188 z_info
= S_028040_FORMAT(format
);
2189 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2190 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2193 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2194 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2196 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2198 if (sctx
->b
.chip_class
>= CIK
) {
2199 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
2200 unsigned index
= rtex
->surface
.tiling_index
[level
];
2201 unsigned stencil_index
= rtex
->surface
.stencil_tiling_index
[level
];
2202 unsigned macro_index
= rtex
->surface
.macro_tile_index
;
2203 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2204 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2205 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2208 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2209 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2210 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2211 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2212 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2213 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2214 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2215 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2217 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2218 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2219 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2220 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2223 /* HiZ aka depth buffer htile */
2224 /* use htile only for first level */
2225 if (rtex
->htile_buffer
&& !level
) {
2226 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2227 S_028040_ALLOW_EXPCLEAR(1);
2229 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2230 /* Workaround: For a not yet understood reason, the
2231 * combination of MSAA, fast stencil clear and stencil
2232 * decompress messes with subsequent stencil buffer
2233 * uses. Problem was reproduced on Verde, Bonaire,
2234 * Tonga, and Carrizo.
2236 * Disabling EXPCLEAR works around the problem.
2238 * Check piglit's arb_texture_multisample-stencil-clear
2239 * test if you want to try changing this.
2241 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2242 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2243 } else if (!rtex
->tc_compatible_htile
) {
2244 /* Use all of the htile_buffer for depth if there's no stencil.
2245 * This must not be set when TC-compatible HTILE is enabled
2248 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2251 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
2252 db_htile_data_base
= va
>> 8;
2253 db_htile_surface
= S_028ABC_FULL_CACHE(1);
2255 if (rtex
->tc_compatible_htile
) {
2256 db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2258 switch (rtex
->resource
.b
.b
.nr_samples
) {
2261 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2265 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2268 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2275 db_htile_data_base
= 0;
2276 db_htile_surface
= 0;
2279 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2281 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2282 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2283 surf
->db_htile_data_base
= db_htile_data_base
;
2284 surf
->db_depth_info
= db_depth_info
;
2285 surf
->db_z_info
= z_info
;
2286 surf
->db_stencil_info
= s_info
;
2287 surf
->db_depth_base
= z_offs
>> 8;
2288 surf
->db_stencil_base
= s_offs
>> 8;
2289 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2290 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2291 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2292 levelinfo
->nblk_y
) / 64 - 1);
2293 surf
->db_htile_surface
= db_htile_surface
;
2295 surf
->depth_initialized
= true;
2298 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2300 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2301 struct r600_surface
*surf
= NULL
;
2302 struct r600_texture
*rtex
;
2304 if (!state
->cbufs
[i
])
2306 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2307 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2309 p_atomic_dec(&rtex
->framebuffers_bound
);
2313 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2314 const struct pipe_framebuffer_state
*state
)
2316 struct si_context
*sctx
= (struct si_context
*)ctx
;
2317 struct pipe_constant_buffer constbuf
= {0};
2318 struct r600_surface
*surf
= NULL
;
2319 struct r600_texture
*rtex
;
2320 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2321 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2324 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2325 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2328 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2329 if (rtex
->dcc_gather_statistics
)
2330 vi_separate_dcc_stop_query(ctx
, rtex
);
2333 /* Only flush TC when changing the framebuffer state, because
2334 * the only client not using TC that can change textures is
2337 * Flush all CB and DB caches here because all buffers can be used
2338 * for write by both TC (with shader image stores) and CB/DB.
2340 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2341 SI_CONTEXT_INV_GLOBAL_L2
|
2342 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
|
2343 SI_CONTEXT_CS_PARTIAL_FLUSH
;
2345 /* Take the maximum of the old and new count. If the new count is lower,
2346 * dirtying is needed to disable the unbound colorbuffers.
2348 sctx
->framebuffer
.dirty_cbufs
|=
2349 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2350 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2352 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2353 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2355 sctx
->framebuffer
.spi_shader_col_format
= 0;
2356 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2357 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2358 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2359 sctx
->framebuffer
.color_is_int8
= 0;
2361 sctx
->framebuffer
.compressed_cb_mask
= 0;
2362 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2363 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2364 sctx
->framebuffer
.any_dst_linear
= false;
2366 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2367 if (!state
->cbufs
[i
])
2370 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2371 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2373 if (!surf
->color_initialized
) {
2374 si_initialize_color_surface(sctx
, surf
);
2377 sctx
->framebuffer
.spi_shader_col_format
|=
2378 surf
->spi_shader_col_format
<< (i
* 4);
2379 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2380 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2381 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2382 surf
->spi_shader_col_format_blend
<< (i
* 4);
2383 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2384 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2386 if (surf
->color_is_int8
)
2387 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2389 if (rtex
->fmask
.size
) {
2390 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2393 if (rtex
->surface
.is_linear
)
2394 sctx
->framebuffer
.any_dst_linear
= true;
2396 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2398 p_atomic_inc(&rtex
->framebuffers_bound
);
2400 if (rtex
->dcc_gather_statistics
) {
2401 /* Dirty tracking must be enabled for DCC usage analysis. */
2402 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2403 vi_separate_dcc_start_query(ctx
, rtex
);
2408 surf
= (struct r600_surface
*)state
->zsbuf
;
2409 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2411 if (!surf
->depth_initialized
) {
2412 si_init_depth_surface(sctx
, surf
);
2414 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2417 si_update_poly_offset_state(sctx
);
2418 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2419 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2421 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2422 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2424 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2425 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2426 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2428 /* Set sample locations as fragment shader constants. */
2429 switch (sctx
->framebuffer
.nr_samples
) {
2431 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2434 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2437 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2440 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2443 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2446 R600_ERR("Requested an invalid number of samples %i.\n",
2447 sctx
->framebuffer
.nr_samples
);
2450 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2451 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2453 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2456 sctx
->need_check_render_feedback
= true;
2457 sctx
->do_update_shaders
= true;
2460 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2462 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2463 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2464 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2465 struct r600_texture
*tex
= NULL
;
2466 struct r600_surface
*cb
= NULL
;
2467 unsigned cb_color_info
= 0;
2470 for (i
= 0; i
< nr_cbufs
; i
++) {
2471 const struct radeon_surf_level
*level_info
;
2472 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2473 unsigned cb_color_base
, cb_color_fmask
, cb_color_attrib
;
2474 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
2476 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2479 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2481 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2482 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2486 tex
= (struct r600_texture
*)cb
->base
.texture
;
2487 level_info
= &tex
->surface
.level
[cb
->base
.u
.tex
.level
];
2488 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2489 &tex
->resource
, RADEON_USAGE_READWRITE
,
2490 tex
->resource
.b
.b
.nr_samples
> 1 ?
2491 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2492 RADEON_PRIO_COLOR_BUFFER
);
2494 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2495 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2496 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2500 if (tex
->dcc_separate_buffer
)
2501 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2502 tex
->dcc_separate_buffer
,
2503 RADEON_USAGE_READWRITE
,
2506 /* Compute mutable surface parameters. */
2507 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2508 slice_tile_max
= level_info
->nblk_x
*
2509 level_info
->nblk_y
/ 64 - 1;
2510 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
2512 cb_color_base
= (tex
->resource
.gpu_address
+ level_info
->offset
) >> 8;
2513 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2514 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2515 cb_color_attrib
= cb
->cb_color_attrib
|
2516 S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2518 if (tex
->fmask
.size
) {
2519 if (sctx
->b
.chip_class
>= CIK
)
2520 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
2521 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
2522 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
2523 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
2525 /* This must be set for fast clear to work without FMASK. */
2526 if (sctx
->b
.chip_class
>= CIK
)
2527 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2528 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2529 cb_color_fmask
= cb_color_base
;
2530 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2533 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2535 if (tex
->dcc_offset
&& cb
->base
.u
.tex
.level
< tex
->surface
.num_dcc_levels
) {
2536 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
2537 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2538 state
->cbufs
[1] == &cb
->base
&&
2539 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2541 if (!is_msaa_resolve_dst
)
2542 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2545 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2546 sctx
->b
.chip_class
>= VI
? 14 : 13);
2547 radeon_emit(cs
, cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2548 radeon_emit(cs
, cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2549 radeon_emit(cs
, cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2550 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2551 radeon_emit(cs
, cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2552 radeon_emit(cs
, cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2553 radeon_emit(cs
, cb
->cb_dcc_control
); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2554 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
2555 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2556 radeon_emit(cs
, cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2557 radeon_emit(cs
, cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2558 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2559 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2561 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
2562 radeon_emit(cs
, ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
2564 tex
->surface
.level
[cb
->base
.u
.tex
.level
].dcc_offset
) >> 8);
2567 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
2568 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2571 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
2572 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2573 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2575 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2576 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2577 zb
->base
.texture
->nr_samples
> 1 ?
2578 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2579 RADEON_PRIO_DEPTH_BUFFER
);
2581 if (zb
->db_htile_data_base
) {
2582 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2583 rtex
->htile_buffer
, RADEON_USAGE_READWRITE
,
2587 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2588 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2590 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2591 radeon_emit(cs
, zb
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
2592 radeon_emit(cs
, zb
->db_z_info
| /* R_028040_DB_Z_INFO */
2593 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2594 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2595 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2596 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2597 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2598 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2599 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2600 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2602 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
2603 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
2604 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
2606 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2607 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
2608 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2609 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2610 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2613 /* Framebuffer dimensions. */
2614 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2615 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2616 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2618 sctx
->framebuffer
.dirty_cbufs
= 0;
2619 sctx
->framebuffer
.dirty_zsbuf
= false;
2622 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
2623 struct r600_atom
*atom
)
2625 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2626 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2628 /* Smoothing (only possible with nr_samples == 1) uses the same
2629 * sample locations as the MSAA it simulates.
2631 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
2632 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
2634 /* On Polaris, the small primitive filter uses the sample locations
2635 * even when MSAA is off, so we need to make sure they're set to 0.
2637 if (sctx
->b
.family
>= CHIP_POLARIS10
)
2638 nr_samples
= MAX2(nr_samples
, 1);
2640 if (nr_samples
>= 1 &&
2641 (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
)) {
2642 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
2643 cayman_emit_msaa_sample_locs(cs
, nr_samples
);
2646 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
2647 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2648 unsigned small_prim_filter_cntl
=
2649 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2650 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2652 /* The alternative of setting sample locations to 0 would
2653 * require a DB flush to avoid Z errors, see
2654 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2656 if (sctx
->framebuffer
.nr_samples
> 1 && rs
&& !rs
->multisample_enable
)
2657 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
2659 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
2660 small_prim_filter_cntl
);
2664 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
2666 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2667 unsigned num_tile_pipes
= sctx
->screen
->b
.info
.num_tile_pipes
;
2668 /* 33% faster rendering to linear color buffers */
2669 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
2670 unsigned sc_mode_cntl_1
=
2671 S_028A4C_WALK_SIZE(dst_is_linear
) |
2672 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
2673 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
2675 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2676 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2677 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2678 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2679 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2680 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2682 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2683 sctx
->ps_iter_samples
,
2684 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0,
2688 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
2690 struct si_context
*sctx
= (struct si_context
*)ctx
;
2692 if (sctx
->ps_iter_samples
== min_samples
)
2695 sctx
->ps_iter_samples
= min_samples
;
2696 sctx
->do_update_shaders
= true;
2698 if (sctx
->framebuffer
.nr_samples
> 1)
2699 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2707 * Build the sampler view descriptor for a buffer texture.
2708 * @param state 256-bit descriptor; only the high 128 bits are filled in
2711 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
2712 enum pipe_format format
,
2713 unsigned offset
, unsigned size
,
2716 const struct util_format_description
*desc
;
2719 unsigned num_records
;
2720 unsigned num_format
, data_format
;
2722 desc
= util_format_description(format
);
2723 first_non_void
= util_format_get_first_non_void_channel(format
);
2724 stride
= desc
->block
.bits
/ 8;
2725 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
2726 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
2728 num_records
= size
/ stride
;
2729 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
2731 if (screen
->b
.chip_class
>= VI
)
2732 num_records
*= stride
;
2735 state
[5] = S_008F04_STRIDE(stride
);
2736 state
[6] = num_records
;
2737 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2738 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2739 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2740 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2741 S_008F0C_NUM_FORMAT(num_format
) |
2742 S_008F0C_DATA_FORMAT(data_format
);
2746 * Build the sampler view descriptor for a texture.
2749 si_make_texture_descriptor(struct si_screen
*screen
,
2750 struct r600_texture
*tex
,
2752 enum pipe_texture_target target
,
2753 enum pipe_format pipe_format
,
2754 const unsigned char state_swizzle
[4],
2755 unsigned first_level
, unsigned last_level
,
2756 unsigned first_layer
, unsigned last_layer
,
2757 unsigned width
, unsigned height
, unsigned depth
,
2759 uint32_t *fmask_state
)
2761 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
2762 const struct util_format_description
*desc
;
2763 unsigned char swizzle
[4];
2765 unsigned num_format
, data_format
, type
;
2768 desc
= util_format_description(pipe_format
);
2770 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2771 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2772 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2774 switch (pipe_format
) {
2775 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2776 case PIPE_FORMAT_X24S8_UINT
:
2777 case PIPE_FORMAT_X32_S8X24_UINT
:
2778 case PIPE_FORMAT_X8Z24_UNORM
:
2779 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2782 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2785 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2788 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2790 switch (pipe_format
) {
2791 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2792 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2795 if (first_non_void
< 0) {
2796 if (util_format_is_compressed(pipe_format
)) {
2797 switch (pipe_format
) {
2798 case PIPE_FORMAT_DXT1_SRGB
:
2799 case PIPE_FORMAT_DXT1_SRGBA
:
2800 case PIPE_FORMAT_DXT3_SRGBA
:
2801 case PIPE_FORMAT_DXT5_SRGBA
:
2802 case PIPE_FORMAT_BPTC_SRGBA
:
2803 case PIPE_FORMAT_ETC2_SRGB8
:
2804 case PIPE_FORMAT_ETC2_SRGB8A1
:
2805 case PIPE_FORMAT_ETC2_SRGBA8
:
2806 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2808 case PIPE_FORMAT_RGTC1_SNORM
:
2809 case PIPE_FORMAT_LATC1_SNORM
:
2810 case PIPE_FORMAT_RGTC2_SNORM
:
2811 case PIPE_FORMAT_LATC2_SNORM
:
2812 case PIPE_FORMAT_ETC2_R11_SNORM
:
2813 case PIPE_FORMAT_ETC2_RG11_SNORM
:
2814 /* implies float, so use SNORM/UNORM to determine
2815 whether data is signed or not */
2816 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2817 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2820 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2823 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2824 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2826 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2828 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2829 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2831 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2833 switch (desc
->channel
[first_non_void
].type
) {
2834 case UTIL_FORMAT_TYPE_FLOAT
:
2835 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2837 case UTIL_FORMAT_TYPE_SIGNED
:
2838 if (desc
->channel
[first_non_void
].normalized
)
2839 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2840 else if (desc
->channel
[first_non_void
].pure_integer
)
2841 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2843 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2845 case UTIL_FORMAT_TYPE_UNSIGNED
:
2846 if (desc
->channel
[first_non_void
].normalized
)
2847 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2848 else if (desc
->channel
[first_non_void
].pure_integer
)
2849 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2851 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2856 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
2857 if (data_format
== ~0) {
2862 (res
->target
== PIPE_TEXTURE_CUBE
||
2863 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2864 res
->target
== PIPE_TEXTURE_3D
)) {
2865 /* For the purpose of shader images, treat cube maps and 3D
2866 * textures as 2D arrays. For 3D textures, the address
2867 * calculations for mipmaps are different, so we rely on the
2868 * caller to effectively disable mipmaps.
2870 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2872 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
2874 type
= si_tex_dim(res
->target
, target
, res
->nr_samples
);
2877 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
2879 depth
= res
->array_size
;
2880 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
2881 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
2882 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
2883 depth
= res
->array_size
;
2884 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
2885 depth
= res
->array_size
/ 6;
2888 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
2889 S_008F14_NUM_FORMAT(num_format
));
2890 state
[2] = (S_008F18_WIDTH(width
- 1) |
2891 S_008F18_HEIGHT(height
- 1) |
2892 S_008F18_PERF_MOD(4));
2893 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2894 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2895 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2896 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2897 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
2899 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
2900 util_logbase2(res
->nr_samples
) :
2902 S_008F1C_POW2_PAD(res
->last_level
> 0) |
2903 S_008F1C_TYPE(type
));
2904 state
[4] = S_008F20_DEPTH(depth
- 1);
2905 state
[5] = (S_008F24_BASE_ARRAY(first_layer
) |
2906 S_008F24_LAST_ARRAY(last_layer
));
2910 if (tex
->dcc_offset
) {
2911 unsigned swap
= r600_translate_colorswap(pipe_format
, false);
2913 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
2915 /* The last dword is unused by hw. The shader uses it to clear
2916 * bits in the first dword of sampler state.
2918 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
2919 if (first_level
== last_level
)
2920 state
[7] = C_008F30_MAX_ANISO_RATIO
;
2922 state
[7] = 0xffffffff;
2926 /* Initialize the sampler view for FMASK. */
2927 if (tex
->fmask
.size
) {
2928 uint32_t fmask_format
;
2930 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
2932 switch (res
->nr_samples
) {
2934 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2937 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2940 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2944 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2947 fmask_state
[0] = va
>> 8;
2948 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2949 S_008F14_DATA_FORMAT(fmask_format
) |
2950 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2951 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2952 S_008F18_HEIGHT(height
- 1);
2953 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2954 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
2955 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
2956 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
2957 S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
) |
2958 S_008F1C_TYPE(si_tex_dim(res
->target
, target
, 0));
2959 fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
2960 S_008F20_PITCH(tex
->fmask
.pitch_in_pixels
- 1);
2961 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
) |
2962 S_008F24_LAST_ARRAY(last_layer
);
2969 * Create a sampler view.
2971 * @param ctx context
2972 * @param texture texture
2973 * @param state sampler view template
2974 * @param width0 width0 override (for compressed textures as int)
2975 * @param height0 height0 override (for compressed textures as int)
2976 * @param force_level set the base address to the level (for compressed textures)
2978 struct pipe_sampler_view
*
2979 si_create_sampler_view_custom(struct pipe_context
*ctx
,
2980 struct pipe_resource
*texture
,
2981 const struct pipe_sampler_view
*state
,
2982 unsigned width0
, unsigned height0
,
2983 unsigned force_level
)
2985 struct si_context
*sctx
= (struct si_context
*)ctx
;
2986 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
2987 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
2988 unsigned base_level
, first_level
, last_level
;
2989 unsigned char state_swizzle
[4];
2990 unsigned height
, depth
, width
;
2991 unsigned last_layer
= state
->u
.tex
.last_layer
;
2992 enum pipe_format pipe_format
;
2993 const struct radeon_surf_level
*surflevel
;
2998 /* initialize base object */
2999 view
->base
= *state
;
3000 view
->base
.texture
= NULL
;
3001 view
->base
.reference
.count
= 1;
3002 view
->base
.context
= ctx
;
3005 pipe_resource_reference(&view
->base
.texture
, texture
);
3007 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3008 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3009 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3010 state
->format
== PIPE_FORMAT_S8_UINT
)
3011 view
->is_stencil_sampler
= true;
3013 /* Buffer resource. */
3014 if (texture
->target
== PIPE_BUFFER
) {
3015 si_make_buffer_descriptor(sctx
->screen
,
3016 (struct r600_resource
*)texture
,
3018 state
->u
.buf
.offset
,
3024 state_swizzle
[0] = state
->swizzle_r
;
3025 state_swizzle
[1] = state
->swizzle_g
;
3026 state_swizzle
[2] = state
->swizzle_b
;
3027 state_swizzle
[3] = state
->swizzle_a
;
3030 first_level
= state
->u
.tex
.first_level
;
3031 last_level
= state
->u
.tex
.last_level
;
3034 depth
= texture
->depth0
;
3037 assert(force_level
== first_level
&&
3038 force_level
== last_level
);
3039 base_level
= force_level
;
3042 width
= u_minify(width
, force_level
);
3043 height
= u_minify(height
, force_level
);
3044 depth
= u_minify(depth
, force_level
);
3047 /* This is not needed if state trackers set last_layer correctly. */
3048 if (state
->target
== PIPE_TEXTURE_1D
||
3049 state
->target
== PIPE_TEXTURE_2D
||
3050 state
->target
== PIPE_TEXTURE_RECT
||
3051 state
->target
== PIPE_TEXTURE_CUBE
)
3052 last_layer
= state
->u
.tex
.first_layer
;
3054 /* Texturing with separate depth and stencil. */
3055 pipe_format
= state
->format
;
3057 /* Depth/stencil texturing sometimes needs separate texture. */
3058 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3059 if (!tmp
->flushed_depth_texture
&&
3060 !r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3061 pipe_resource_reference(&view
->base
.texture
, NULL
);
3066 assert(tmp
->flushed_depth_texture
);
3068 /* Override format for the case where the flushed texture
3069 * contains only Z or only S.
3071 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3072 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3074 tmp
= tmp
->flushed_depth_texture
;
3077 surflevel
= tmp
->surface
.level
;
3079 if (tmp
->db_compatible
) {
3080 if (!view
->is_stencil_sampler
)
3081 pipe_format
= tmp
->db_render_format
;
3083 switch (pipe_format
) {
3084 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3085 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3087 case PIPE_FORMAT_X8Z24_UNORM
:
3088 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3089 /* Z24 is always stored like this for DB
3092 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3094 case PIPE_FORMAT_X24S8_UINT
:
3095 case PIPE_FORMAT_S8X24_UINT
:
3096 case PIPE_FORMAT_X32_S8X24_UINT
:
3097 pipe_format
= PIPE_FORMAT_S8_UINT
;
3098 surflevel
= tmp
->surface
.stencil_level
;
3104 vi_dcc_disable_if_incompatible_format(&sctx
->b
, texture
,
3105 state
->u
.tex
.first_level
,
3108 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3109 state
->target
, pipe_format
, state_swizzle
,
3110 first_level
, last_level
,
3111 state
->u
.tex
.first_layer
, last_layer
,
3112 width
, height
, depth
,
3113 view
->state
, view
->fmask_state
);
3115 view
->base_level_info
= &surflevel
[base_level
];
3116 view
->base_level
= base_level
;
3117 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3121 static struct pipe_sampler_view
*
3122 si_create_sampler_view(struct pipe_context
*ctx
,
3123 struct pipe_resource
*texture
,
3124 const struct pipe_sampler_view
*state
)
3126 return si_create_sampler_view_custom(ctx
, texture
, state
,
3127 texture
? texture
->width0
: 0,
3128 texture
? texture
->height0
: 0, 0);
3131 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3132 struct pipe_sampler_view
*state
)
3134 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3136 pipe_resource_reference(&state
->texture
, NULL
);
3140 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3142 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3143 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3145 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3146 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3149 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
3151 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3152 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3154 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
3155 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
3156 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
3157 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
3158 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
3161 static void *si_create_sampler_state(struct pipe_context
*ctx
,
3162 const struct pipe_sampler_state
*state
)
3164 struct si_context
*sctx
= (struct si_context
*)ctx
;
3165 struct r600_common_screen
*rscreen
= sctx
->b
.screen
;
3166 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
3167 unsigned border_color_type
, border_color_index
= 0;
3168 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
3169 : state
->max_anisotropy
;
3170 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
3176 if (!sampler_state_needs_border_color(state
))
3177 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3178 else if (state
->border_color
.f
[0] == 0 &&
3179 state
->border_color
.f
[1] == 0 &&
3180 state
->border_color
.f
[2] == 0 &&
3181 state
->border_color
.f
[3] == 0)
3182 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3183 else if (state
->border_color
.f
[0] == 0 &&
3184 state
->border_color
.f
[1] == 0 &&
3185 state
->border_color
.f
[2] == 0 &&
3186 state
->border_color
.f
[3] == 1)
3187 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3188 else if (state
->border_color
.f
[0] == 1 &&
3189 state
->border_color
.f
[1] == 1 &&
3190 state
->border_color
.f
[2] == 1 &&
3191 state
->border_color
.f
[3] == 1)
3192 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3196 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
3198 /* Check if the border has been uploaded already. */
3199 for (i
= 0; i
< sctx
->border_color_count
; i
++)
3200 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
3201 sizeof(state
->border_color
)) == 0)
3204 if (i
>= SI_MAX_BORDER_COLORS
) {
3205 /* Getting 4096 unique border colors is very unlikely. */
3206 fprintf(stderr
, "radeonsi: The border color table is full. "
3207 "Any new border colors will be just black. "
3208 "Please file a bug.\n");
3209 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3211 if (i
== sctx
->border_color_count
) {
3212 /* Upload a new border color. */
3213 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
3214 sizeof(state
->border_color
));
3215 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
3216 &state
->border_color
,
3217 sizeof(state
->border_color
));
3218 sctx
->border_color_count
++;
3221 border_color_index
= i
;
3225 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
3226 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
3227 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
3228 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3229 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
3230 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
3231 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3232 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3233 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
3234 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
3235 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
3236 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
3237 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3238 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
3239 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
3240 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
3241 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
3242 S_008F38_MIP_POINT_PRECLAMP(1) |
3243 S_008F38_DISABLE_LSB_CEIL(1) |
3244 S_008F38_FILTER_PREC_FIX(1) |
3245 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
3246 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
3247 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
3251 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
3253 struct si_context
*sctx
= (struct si_context
*)ctx
;
3255 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
3258 sctx
->sample_mask
.sample_mask
= sample_mask
;
3259 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
3262 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
3264 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3265 unsigned mask
= sctx
->sample_mask
.sample_mask
;
3267 /* Needed for line and polygon smoothing as well as for the Polaris
3268 * small primitive filter. We expect the state tracker to take care of
3271 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
3272 (mask
& 1 && sctx
->blitter
->running
));
3274 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3275 radeon_emit(cs
, mask
| (mask
<< 16));
3276 radeon_emit(cs
, mask
| (mask
<< 16));
3279 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3285 * Vertex elements & buffers
3288 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3290 const struct pipe_vertex_element
*elements
)
3292 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
3295 assert(count
<= SI_MAX_ATTRIBS
);
3300 for (i
= 0; i
< count
; ++i
) {
3301 const struct util_format_description
*desc
;
3302 unsigned data_format
, num_format
;
3305 desc
= util_format_description(elements
[i
].src_format
);
3306 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3307 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3308 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3310 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3311 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3312 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3313 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3314 S_008F0C_NUM_FORMAT(num_format
) |
3315 S_008F0C_DATA_FORMAT(data_format
);
3316 v
->format_size
[i
] = desc
->block
.bits
/ 8;
3318 /* The hardware always treats the 2-bit alpha channel as
3319 * unsigned, so a shader workaround is needed.
3321 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
) {
3322 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
3323 v
->fix_fetch
|= SI_FIX_FETCH_A2_SNORM
<< (2 * i
);
3324 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
3325 v
->fix_fetch
|= SI_FIX_FETCH_A2_SSCALED
<< (2 * i
);
3326 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
3327 /* This isn't actually used in OpenGL. */
3328 v
->fix_fetch
|= SI_FIX_FETCH_A2_SINT
<< (2 * i
);
3332 /* We work around the fact that 8_8_8 and 16_16_16 data formats
3333 * do not exist by using the corresponding 4-component formats.
3334 * This requires a fixup of the descriptor for bounds checks.
3336 if (desc
->block
.bits
== 3 * 8 ||
3337 desc
->block
.bits
== 3 * 16) {
3338 v
->fix_size3
|= (desc
->block
.bits
/ 24) << (2 * i
);
3341 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3346 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3348 struct si_context
*sctx
= (struct si_context
*)ctx
;
3349 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3351 sctx
->vertex_elements
= v
;
3352 sctx
->vertex_buffers_dirty
= true;
3353 sctx
->do_update_shaders
= true;
3356 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3358 struct si_context
*sctx
= (struct si_context
*)ctx
;
3360 if (sctx
->vertex_elements
== state
)
3361 sctx
->vertex_elements
= NULL
;
3365 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
3366 unsigned start_slot
, unsigned count
,
3367 const struct pipe_vertex_buffer
*buffers
)
3369 struct si_context
*sctx
= (struct si_context
*)ctx
;
3370 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
3373 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
3376 for (i
= 0; i
< count
; i
++) {
3377 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
3378 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
3379 struct pipe_resource
*buf
= src
->buffer
;
3381 pipe_resource_reference(&dsti
->buffer
, buf
);
3382 dsti
->buffer_offset
= src
->buffer_offset
;
3383 dsti
->stride
= src
->stride
;
3384 r600_context_add_resource_size(ctx
, buf
);
3386 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3389 for (i
= 0; i
< count
; i
++) {
3390 pipe_resource_reference(&dst
[i
].buffer
, NULL
);
3393 sctx
->vertex_buffers_dirty
= true;
3396 static void si_set_index_buffer(struct pipe_context
*ctx
,
3397 const struct pipe_index_buffer
*ib
)
3399 struct si_context
*sctx
= (struct si_context
*)ctx
;
3402 struct pipe_resource
*buf
= ib
->buffer
;
3404 pipe_resource_reference(&sctx
->index_buffer
.buffer
, buf
);
3405 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3406 r600_context_add_resource_size(ctx
, buf
);
3408 r600_resource(buf
)->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
3410 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3418 static void si_set_tess_state(struct pipe_context
*ctx
,
3419 const float default_outer_level
[4],
3420 const float default_inner_level
[2])
3422 struct si_context
*sctx
= (struct si_context
*)ctx
;
3423 struct pipe_constant_buffer cb
;
3426 memcpy(array
, default_outer_level
, sizeof(float) * 4);
3427 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
3430 cb
.user_buffer
= NULL
;
3431 cb
.buffer_size
= sizeof(array
);
3433 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
3434 (void*)array
, sizeof(array
),
3437 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
3438 pipe_resource_reference(&cb
.buffer
, NULL
);
3441 static void si_texture_barrier(struct pipe_context
*ctx
)
3443 struct si_context
*sctx
= (struct si_context
*)ctx
;
3445 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
3446 SI_CONTEXT_INV_GLOBAL_L2
|
3447 SI_CONTEXT_FLUSH_AND_INV_CB
|
3448 SI_CONTEXT_CS_PARTIAL_FLUSH
;
3451 /* This only ensures coherency for shader image/buffer stores. */
3452 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
3454 struct si_context
*sctx
= (struct si_context
*)ctx
;
3456 /* Subsequent commands must wait for all shader invocations to
3458 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
3459 SI_CONTEXT_CS_PARTIAL_FLUSH
;
3461 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
3462 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
3463 SI_CONTEXT_INV_VMEM_L1
;
3465 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
3466 PIPE_BARRIER_SHADER_BUFFER
|
3467 PIPE_BARRIER_TEXTURE
|
3468 PIPE_BARRIER_IMAGE
|
3469 PIPE_BARRIER_STREAMOUT_BUFFER
|
3470 PIPE_BARRIER_GLOBAL_BUFFER
)) {
3471 /* As far as I can tell, L1 contents are written back to L2
3472 * automatically at end of shader, but the contents of other
3473 * L1 caches might still be stale. */
3474 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
3477 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
3478 /* Indices are read through TC L2 since VI.
3481 if (sctx
->screen
->b
.chip_class
<= CIK
)
3482 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
3485 if (flags
& PIPE_BARRIER_FRAMEBUFFER
)
3486 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
;
3488 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
3489 PIPE_BARRIER_INDIRECT_BUFFER
))
3490 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
3493 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3495 struct pipe_blend_state blend
;
3497 memset(&blend
, 0, sizeof(blend
));
3498 blend
.independent_blend_enable
= true;
3499 blend
.rt
[0].colormask
= 0xf;
3500 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3503 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3504 bool include_draw_vbo
)
3506 si_need_cs_space((struct si_context
*)ctx
);
3509 static void si_init_config(struct si_context
*sctx
);
3511 void si_init_state_functions(struct si_context
*sctx
)
3513 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
3514 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
3515 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
3516 si_init_external_atom(sctx
, &sctx
->b
.scissors
.atom
, &sctx
->atoms
.s
.scissors
);
3517 si_init_external_atom(sctx
, &sctx
->b
.viewports
.atom
, &sctx
->atoms
.s
.viewports
);
3519 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
3520 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
3521 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
3522 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
3523 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
3524 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
3525 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
3526 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
3527 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
3528 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
3530 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3531 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3532 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3533 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3535 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3536 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3537 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3539 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3540 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3541 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3543 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
3544 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3545 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3546 sctx
->custom_blend_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
3547 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
3549 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3550 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
3552 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3553 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3555 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3556 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3558 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3559 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3561 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3563 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3564 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3565 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3566 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3567 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3569 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3570 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
3571 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
3572 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
3574 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
3575 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3576 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
3577 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3579 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3581 si_init_config(sctx
);
3584 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen
*rscreen
)
3586 return (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
3589 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
3590 struct r600_texture
*rtex
,
3591 struct radeon_bo_metadata
*md
)
3593 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
3594 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
3595 static const unsigned char swizzle
[] = {
3601 uint32_t desc
[8], i
;
3602 bool is_array
= util_resource_is_array_texture(res
);
3604 /* DRM 2.x.x doesn't support this. */
3605 if (rscreen
->info
.drm_major
!= 3)
3608 assert(rtex
->dcc_separate_buffer
== NULL
);
3609 assert(rtex
->fmask
.size
== 0);
3611 /* Metadata image format format version 1:
3612 * [0] = 1 (metadata format identifier)
3613 * [1] = (VENDOR_ID << 16) | PCI_ID
3614 * [2:9] = image descriptor for the whole resource
3615 * [2] is always 0, because the base address is cleared
3616 * [9] is the DCC offset bits [39:8] from the beginning of
3618 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3621 md
->metadata
[0] = 1; /* metadata image format version 1 */
3623 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3624 md
->metadata
[1] = si_get_bo_metadata_word1(rscreen
);
3626 si_make_texture_descriptor(sscreen
, rtex
, true,
3627 res
->target
, res
->format
,
3628 swizzle
, 0, res
->last_level
, 0,
3629 is_array
? res
->array_size
- 1 : 0,
3630 res
->width0
, res
->height0
, res
->depth0
,
3633 si_set_mutable_tex_desc_fields(rtex
, &rtex
->surface
.level
[0], 0, 0,
3634 rtex
->surface
.blk_w
, false, desc
);
3636 /* Clear the base address and set the relative DCC offset. */
3638 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
3639 desc
[7] = rtex
->dcc_offset
>> 8;
3641 /* Dwords [2:9] contain the image descriptor. */
3642 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
3644 /* Dwords [10:..] contain the mipmap level offsets. */
3645 for (i
= 0; i
<= res
->last_level
; i
++)
3646 md
->metadata
[10+i
] = rtex
->surface
.level
[i
].offset
>> 8;
3648 md
->size_metadata
= (11 + res
->last_level
) * 4;
3651 static void si_apply_opaque_metadata(struct r600_common_screen
*rscreen
,
3652 struct r600_texture
*rtex
,
3653 struct radeon_bo_metadata
*md
)
3655 uint32_t *desc
= &md
->metadata
[2];
3657 if (rscreen
->chip_class
< VI
)
3660 /* Return if DCC is enabled. The texture should be set up with it
3663 if (md
->size_metadata
>= 11 * 4 &&
3664 md
->metadata
[0] != 0 &&
3665 md
->metadata
[1] == si_get_bo_metadata_word1(rscreen
) &&
3666 G_008F28_COMPRESSION_EN(desc
[6])) {
3667 assert(rtex
->dcc_offset
== ((uint64_t)desc
[7] << 8));
3671 /* Disable DCC. These are always set by texture_from_handle and must
3674 rtex
->dcc_offset
= 0;
3677 void si_init_screen_state_functions(struct si_screen
*sscreen
)
3679 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
3680 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
3681 sscreen
->b
.apply_opaque_metadata
= si_apply_opaque_metadata
;
3685 si_write_harvested_raster_configs(struct si_context
*sctx
,
3686 struct si_pm4_state
*pm4
,
3687 unsigned raster_config
,
3688 unsigned raster_config_1
)
3690 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
3691 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
3692 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
3693 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
3694 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
3695 unsigned rb_per_se
= num_rb
/ num_se
;
3696 unsigned se_mask
[4];
3699 se_mask
[0] = ((1 << rb_per_se
) - 1);
3700 se_mask
[1] = (se_mask
[0] << rb_per_se
);
3701 se_mask
[2] = (se_mask
[1] << rb_per_se
);
3702 se_mask
[3] = (se_mask
[2] << rb_per_se
);
3704 se_mask
[0] &= rb_mask
;
3705 se_mask
[1] &= rb_mask
;
3706 se_mask
[2] &= rb_mask
;
3707 se_mask
[3] &= rb_mask
;
3709 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
3710 assert(sh_per_se
== 1 || sh_per_se
== 2);
3711 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
3713 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3714 * fields are for, so I'm leaving them as their default
3717 for (se
= 0; se
< num_se
; se
++) {
3718 unsigned raster_config_se
= raster_config
;
3719 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
3720 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
3721 int idx
= (se
/ 2) * 2;
3723 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
3724 raster_config_se
&= C_028350_SE_MAP
;
3726 if (!se_mask
[idx
]) {
3728 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
3731 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
3735 pkr0_mask
&= rb_mask
;
3736 pkr1_mask
&= rb_mask
;
3737 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
3738 raster_config_se
&= C_028350_PKR_MAP
;
3742 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
3745 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
3749 if (rb_per_se
>= 2) {
3750 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
3751 unsigned rb1_mask
= rb0_mask
<< 1;
3753 rb0_mask
&= rb_mask
;
3754 rb1_mask
&= rb_mask
;
3755 if (!rb0_mask
|| !rb1_mask
) {
3756 raster_config_se
&= C_028350_RB_MAP_PKR0
;
3760 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
3763 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
3767 if (rb_per_se
> 2) {
3768 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
3769 rb1_mask
= rb0_mask
<< 1;
3770 rb0_mask
&= rb_mask
;
3771 rb1_mask
&= rb_mask
;
3772 if (!rb0_mask
|| !rb1_mask
) {
3773 raster_config_se
&= C_028350_RB_MAP_PKR1
;
3777 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
3780 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
3786 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3787 if (sctx
->b
.chip_class
< CIK
)
3788 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3789 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
3790 INSTANCE_BROADCAST_WRITES
);
3792 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3793 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
3794 S_030800_INSTANCE_BROADCAST_WRITES(1));
3795 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
3798 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3799 if (sctx
->b
.chip_class
< CIK
)
3800 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3801 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
3802 INSTANCE_BROADCAST_WRITES
);
3804 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3805 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3806 S_030800_INSTANCE_BROADCAST_WRITES(1));
3808 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
3809 (!se_mask
[2] && !se_mask
[3]))) {
3810 raster_config_1
&= C_028354_SE_PAIR_MAP
;
3812 if (!se_mask
[0] && !se_mask
[1]) {
3814 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
3817 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
3821 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
3825 static void si_init_config(struct si_context
*sctx
)
3827 struct si_screen
*sscreen
= sctx
->screen
;
3828 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
3829 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
3830 unsigned raster_config
, raster_config_1
;
3831 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
3832 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3837 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
3838 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
3839 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3840 si_pm4_cmd_end(pm4
, false);
3842 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
3843 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
3845 /* FIXME calculate these values somehow ??? */
3846 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
3847 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3848 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3850 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3851 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3853 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3854 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3855 if (sctx
->b
.chip_class
< CIK
)
3856 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3857 S_008A14_CLIP_VTX_REORDER_ENA(1));
3859 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3860 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3862 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3864 switch (sctx
->screen
->b
.family
) {
3867 raster_config
= 0x2a00126a;
3868 raster_config_1
= 0x00000000;
3871 raster_config
= 0x0000124a;
3872 raster_config_1
= 0x00000000;
3875 raster_config
= 0x00000082;
3876 raster_config_1
= 0x00000000;
3879 raster_config
= 0x00000000;
3880 raster_config_1
= 0x00000000;
3883 raster_config
= 0x16000012;
3884 raster_config_1
= 0x00000000;
3887 raster_config
= 0x3a00161a;
3888 raster_config_1
= 0x0000002e;
3891 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
3892 /* old kernels with old tiling config */
3893 raster_config
= 0x16000012;
3894 raster_config_1
= 0x0000002a;
3896 raster_config
= 0x3a00161a;
3897 raster_config_1
= 0x0000002e;
3900 case CHIP_POLARIS10
:
3901 raster_config
= 0x16000012;
3902 raster_config_1
= 0x0000002a;
3904 case CHIP_POLARIS11
:
3905 raster_config
= 0x16000012;
3906 raster_config_1
= 0x00000000;
3909 raster_config
= 0x16000012;
3910 raster_config_1
= 0x0000002a;
3914 raster_config
= 0x00000000;
3916 raster_config
= 0x00000002;
3917 raster_config_1
= 0x00000000;
3920 raster_config
= 0x00000002;
3921 raster_config_1
= 0x00000000;
3924 /* KV should be 0x00000002, but that causes problems with radeon */
3925 raster_config
= 0x00000000; /* 0x00000002 */
3926 raster_config_1
= 0x00000000;
3931 raster_config
= 0x00000000;
3932 raster_config_1
= 0x00000000;
3936 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3937 raster_config
= 0x00000000;
3938 raster_config_1
= 0x00000000;
3942 /* Always use the default config when all backends are enabled
3943 * (or when we failed to determine the enabled backends).
3945 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
3946 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
3948 if (sctx
->b
.chip_class
>= CIK
)
3949 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
3952 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
3955 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
3956 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
3957 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
3958 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3959 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
3960 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
3961 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3963 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3964 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
3965 S_028230_ER_TRI(0xA) |
3966 S_028230_ER_POINT(0xA) |
3967 S_028230_ER_RECT(0xA) |
3968 /* Required by DX10_DIAMOND_TEST_ENA: */
3969 S_028230_ER_LINE_LR(0x1A) |
3970 S_028230_ER_LINE_RL(0x26) |
3971 S_028230_ER_LINE_TB(0xA) |
3972 S_028230_ER_LINE_BT(0xA));
3973 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3974 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3975 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
3976 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
3977 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
3978 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
3979 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
3981 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
3982 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
3983 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
3985 if (sctx
->b
.chip_class
>= CIK
) {
3986 /* If this is 0, Bonaire can hang even if GS isn't being used.
3987 * Other chips are unaffected. These are suboptimal values,
3988 * but we don't use on-chip GS.
3990 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3991 S_028A44_ES_VERTS_PER_SUBGRP(64) |
3992 S_028A44_GS_PRIMS_PER_SUBGRP(4));
3994 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
3995 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
3996 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
3997 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
3999 if (sscreen
->b
.info
.num_good_compute_units
/
4000 (sscreen
->b
.info
.max_se
* sscreen
->b
.info
.max_sh_per_se
) <= 4) {
4001 /* Too few available compute units per SH. Disallowing
4002 * VS to run on CU0 could hurt us more than late VS
4003 * allocation would help.
4005 * LATE_ALLOC_VS = 2 is the highest safe number.
4007 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
4008 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
4010 /* Set LATE_ALLOC_VS == 31. It should be less than
4011 * the number of scratch waves. Limitations:
4012 * - VS can't execute on CU0.
4013 * - If HS writes outputs to LDS, LS can't execute on CU0.
4015 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
4016 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
4019 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
4022 if (sctx
->b
.chip_class
>= VI
) {
4023 unsigned vgt_tess_distribution
;
4025 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
4026 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4027 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4028 if (sctx
->b
.family
< CHIP_POLARIS10
)
4029 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
4030 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
4032 vgt_tess_distribution
=
4033 S_028B50_ACCUM_ISOLINE(32) |
4034 S_028B50_ACCUM_TRI(11) |
4035 S_028B50_ACCUM_QUAD(11) |
4036 S_028B50_DONUT_SPLIT(16);
4038 /* Testing with Unigine Heaven extreme tesselation yielded best results
4039 * with TRAP_SPLIT = 3.
4041 if (sctx
->b
.family
== CHIP_FIJI
||
4042 sctx
->b
.family
>= CHIP_POLARIS10
)
4043 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
4045 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
4047 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
4048 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
4051 if (sctx
->b
.family
== CHIP_STONEY
)
4052 si_pm4_set_reg(pm4
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
4054 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4055 if (sctx
->b
.chip_class
>= CIK
)
4056 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
4057 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4058 RADEON_PRIO_BORDER_COLORS
);
4060 si_pm4_upload_indirect_buffer(sctx
, pm4
);
4061 sctx
->init_config
= pm4
;