2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
40 /* Initialize an external atom (owned by ../radeon). */
42 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
43 struct r600_atom
**list_elem
)
45 atom
->id
= list_elem
- sctx
->atoms
.array
;
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
51 struct r600_atom
**list_elem
,
52 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
54 atom
->emit
= (void*)emit_func
;
55 atom
->id
= list_elem
- sctx
->atoms
.array
;
59 static unsigned si_map_swizzle(unsigned swizzle
)
63 return V_008F0C_SQ_SEL_Y
;
65 return V_008F0C_SQ_SEL_Z
;
67 return V_008F0C_SQ_SEL_W
;
69 return V_008F0C_SQ_SEL_0
;
71 return V_008F0C_SQ_SEL_1
;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X
;
77 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
79 return value
* (1 << frac_bits
);
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x
)
86 x
>= 4096 ? 0xffff : x
* 16;
90 * Inferred framebuffer and blender state.
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
95 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
97 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
98 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
105 cb_target_mask
&= blend
->cb_target_mask
;
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
113 if (blend
&& blend
->dual_src_blend
&&
114 sctx
->ps_shader
.cso
&&
115 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
118 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
123 if (sctx
->b
.chip_class
>= GFX9
&&
124 sctx
->last_cb_target_mask
!= cb_target_mask
) {
125 sctx
->last_cb_target_mask
= cb_target_mask
;
127 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
128 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
131 /* RB+ register settings. */
132 if (sctx
->screen
->b
.rbplus_allowed
) {
133 unsigned spi_shader_col_format
=
134 sctx
->ps_shader
.cso
?
135 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
136 unsigned sx_ps_downconvert
= 0;
137 unsigned sx_blend_opt_epsilon
= 0;
138 unsigned sx_blend_opt_control
= 0;
140 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
141 struct r600_surface
*surf
=
142 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
143 unsigned format
, swap
, spi_format
, colormask
;
144 bool has_alpha
, has_rgb
;
149 format
= G_028C70_FORMAT(surf
->cb_color_info
);
150 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
151 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
152 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
154 /* Set if RGB and A are present. */
155 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
157 if (format
== V_028C70_COLOR_8
||
158 format
== V_028C70_COLOR_16
||
159 format
== V_028C70_COLOR_32
)
160 has_rgb
= !has_alpha
;
164 /* Check the colormask and export format. */
165 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
167 if (!(colormask
& PIPE_MASK_A
))
170 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
175 /* Disable value checking for disabled channels. */
177 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
179 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
181 /* Enable down-conversion for 32bpp and smaller formats. */
183 case V_028C70_COLOR_8
:
184 case V_028C70_COLOR_8_8
:
185 case V_028C70_COLOR_8_8_8_8
:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
188 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
189 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
190 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
191 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
195 case V_028C70_COLOR_5_6_5
:
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
197 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
198 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
202 case V_028C70_COLOR_1_5_5_5
:
203 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
204 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
205 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
209 case V_028C70_COLOR_4_4_4_4
:
210 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
212 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
216 case V_028C70_COLOR_32
:
217 if (swap
== V_0280A0_SWAP_STD
&&
218 spi_format
== V_028714_SPI_SHADER_32_R
)
219 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
220 else if (swap
== V_0280A0_SWAP_ALT_REV
&&
221 spi_format
== V_028714_SPI_SHADER_32_AR
)
222 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
225 case V_028C70_COLOR_16
:
226 case V_028C70_COLOR_16_16
:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
229 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
230 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
231 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
232 if (swap
== V_0280A0_SWAP_STD
||
233 swap
== V_0280A0_SWAP_STD_REV
)
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
236 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
240 case V_028C70_COLOR_10_11_11
:
241 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
242 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
243 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
247 case V_028C70_COLOR_2_10_10_10
:
248 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
249 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
250 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
256 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
257 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx
->screen
->b
.has_rbplus
) {
261 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
262 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
272 static uint32_t si_translate_blend_function(int blend_func
)
274 switch (blend_func
) {
276 return V_028780_COMB_DST_PLUS_SRC
;
277 case PIPE_BLEND_SUBTRACT
:
278 return V_028780_COMB_SRC_MINUS_DST
;
279 case PIPE_BLEND_REVERSE_SUBTRACT
:
280 return V_028780_COMB_DST_MINUS_SRC
;
282 return V_028780_COMB_MIN_DST_SRC
;
284 return V_028780_COMB_MAX_DST_SRC
;
286 R600_ERR("Unknown blend function %d\n", blend_func
);
293 static uint32_t si_translate_blend_factor(int blend_fact
)
295 switch (blend_fact
) {
296 case PIPE_BLENDFACTOR_ONE
:
297 return V_028780_BLEND_ONE
;
298 case PIPE_BLENDFACTOR_SRC_COLOR
:
299 return V_028780_BLEND_SRC_COLOR
;
300 case PIPE_BLENDFACTOR_SRC_ALPHA
:
301 return V_028780_BLEND_SRC_ALPHA
;
302 case PIPE_BLENDFACTOR_DST_ALPHA
:
303 return V_028780_BLEND_DST_ALPHA
;
304 case PIPE_BLENDFACTOR_DST_COLOR
:
305 return V_028780_BLEND_DST_COLOR
;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
308 case PIPE_BLENDFACTOR_CONST_COLOR
:
309 return V_028780_BLEND_CONSTANT_COLOR
;
310 case PIPE_BLENDFACTOR_CONST_ALPHA
:
311 return V_028780_BLEND_CONSTANT_ALPHA
;
312 case PIPE_BLENDFACTOR_ZERO
:
313 return V_028780_BLEND_ZERO
;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
326 case PIPE_BLENDFACTOR_SRC1_COLOR
:
327 return V_028780_BLEND_SRC1_COLOR
;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
329 return V_028780_BLEND_SRC1_ALPHA
;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
331 return V_028780_BLEND_INV_SRC1_COLOR
;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
333 return V_028780_BLEND_INV_SRC1_ALPHA
;
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
342 static uint32_t si_translate_blend_opt_function(int blend_func
)
344 switch (blend_func
) {
346 return V_028760_OPT_COMB_ADD
;
347 case PIPE_BLEND_SUBTRACT
:
348 return V_028760_OPT_COMB_SUBTRACT
;
349 case PIPE_BLEND_REVERSE_SUBTRACT
:
350 return V_028760_OPT_COMB_REVSUBTRACT
;
352 return V_028760_OPT_COMB_MIN
;
354 return V_028760_OPT_COMB_MAX
;
356 return V_028760_OPT_COMB_BLEND_DISABLED
;
360 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
362 switch (blend_fact
) {
363 case PIPE_BLENDFACTOR_ZERO
:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
365 case PIPE_BLENDFACTOR_ONE
:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
367 case PIPE_BLENDFACTOR_SRC_COLOR
:
368 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
371 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
373 case PIPE_BLENDFACTOR_SRC_ALPHA
:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
378 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
389 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
390 unsigned *dst_factor
, unsigned expected_dst
,
391 unsigned replacement_src
)
393 if (*src_factor
== expected_dst
&&
394 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
395 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
396 *dst_factor
= replacement_src
;
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func
== PIPE_BLEND_SUBTRACT
)
400 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
401 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
402 *func
= PIPE_BLEND_SUBTRACT
;
406 static bool si_blend_factor_uses_dst(unsigned factor
)
408 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
409 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
410 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
411 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
412 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
415 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
416 const struct pipe_blend_state
*state
,
419 struct si_context
*sctx
= (struct si_context
*)ctx
;
420 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
421 struct si_pm4_state
*pm4
= &blend
->pm4
;
422 uint32_t sx_mrt_blend_opt
[8] = {0};
423 uint32_t color_control
= 0;
428 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
429 blend
->alpha_to_one
= state
->alpha_to_one
;
430 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
432 if (state
->logicop_enable
) {
433 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
435 color_control
|= S_028808_ROP3(0xcc);
438 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
445 if (state
->alpha_to_coverage
)
446 blend
->need_src_alpha_4bit
|= 0xf;
448 blend
->cb_target_mask
= 0;
449 for (int i
= 0; i
< 8; i
++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j
= state
->independent_blend_enable
? i
: 0;
453 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
454 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
455 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
456 unsigned eqA
= state
->rt
[j
].alpha_func
;
457 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
458 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
460 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
461 unsigned blend_cntl
= 0;
463 sx_mrt_blend_opt
[i
] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i
>= 1 && blend
->dual_src_blend
) {
469 /* Vulkan does this for dual source blending. */
471 blend_cntl
|= S_028780_ENABLE(1);
473 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
480 if (blend
->dual_src_blend
&&
481 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
482 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
488 /* cb_render_state will disable unused ones */
489 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
491 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
492 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
502 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
503 PIPE_BLENDFACTOR_DST_COLOR
,
504 PIPE_BLENDFACTOR_SRC_COLOR
);
505 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
506 PIPE_BLENDFACTOR_DST_COLOR
,
507 PIPE_BLENDFACTOR_SRC_COLOR
);
508 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
509 PIPE_BLENDFACTOR_DST_ALPHA
,
510 PIPE_BLENDFACTOR_SRC_ALPHA
);
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
514 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
515 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
516 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB
))
520 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
521 if (si_blend_factor_uses_dst(srcA
))
522 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
524 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
525 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
526 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
527 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
528 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
530 /* Set the final value. */
531 sx_mrt_blend_opt
[i
] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
536 S_028760_ALPHA_DST_OPT(dstA_opt
) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
539 /* Set blend state. */
540 blend_cntl
|= S_028780_ENABLE(1);
541 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
542 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
543 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
545 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
546 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
548 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
549 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
551 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
553 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
555 /* This is only important for formats without alpha. */
556 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
557 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
558 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
559 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
560 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
561 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
562 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
565 if (blend
->cb_target_mask
) {
566 color_control
|= S_028808_MODE(mode
);
568 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
571 if (sctx
->screen
->b
.has_rbplus
) {
572 /* Disable RB+ blend optimizations for dual source blending.
575 if (blend
->dual_src_blend
) {
576 for (int i
= 0; i
< 8; i
++) {
577 sx_mrt_blend_opt
[i
] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
583 for (int i
= 0; i
< 8; i
++)
584 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
585 sx_mrt_blend_opt
[i
]);
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend
->dual_src_blend
|| state
->logicop_enable
||
589 mode
== V_028808_CB_RESOLVE
)
590 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
593 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
597 static void *si_create_blend_state(struct pipe_context
*ctx
,
598 const struct pipe_blend_state
*state
)
600 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
603 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
605 struct si_context
*sctx
= (struct si_context
*)ctx
;
606 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
607 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
613 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
614 old_blend
->dual_src_blend
!= blend
->dual_src_blend
)
615 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
617 si_pm4_bind_state(sctx
, blend
, state
);
620 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
621 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
622 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
623 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
624 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
625 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
626 sctx
->do_update_shaders
= true;
629 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
631 struct si_context
*sctx
= (struct si_context
*)ctx
;
632 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
635 static void si_set_blend_color(struct pipe_context
*ctx
,
636 const struct pipe_blend_color
*state
)
638 struct si_context
*sctx
= (struct si_context
*)ctx
;
640 sctx
->blend_color
.state
= *state
;
641 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
644 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
646 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
648 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
649 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
656 static void si_set_clip_state(struct pipe_context
*ctx
,
657 const struct pipe_clip_state
*state
)
659 struct si_context
*sctx
= (struct si_context
*)ctx
;
660 struct pipe_constant_buffer cb
;
662 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
665 sctx
->clip_state
.state
= *state
;
666 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
669 cb
.user_buffer
= state
->ucp
;
670 cb
.buffer_offset
= 0;
671 cb
.buffer_size
= 4*4*8;
672 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
673 pipe_resource_reference(&cb
.buffer
, NULL
);
676 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
678 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
680 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
681 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
684 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
686 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
687 struct si_shader
*vs
= si_get_vs_state(sctx
);
688 struct si_shader_selector
*vs_sel
= vs
->selector
;
689 struct tgsi_shader_info
*info
= &vs_sel
->info
;
690 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
691 unsigned window_space
=
692 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
693 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
694 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
695 unsigned culldist_mask
= vs_sel
->culldist_mask
;
698 if (vs
->key
.opt
.clip_disable
) {
699 assert(!info
->culldist_writemask
);
703 total_mask
= clipdist_mask
| culldist_mask
;
705 /* Clip distances on points have no effect, so need to be implemented
706 * as cull distances. This applies for the clipvertex case as well.
708 * Setting this for primitives other than points should have no adverse
711 clipdist_mask
&= rs
->clip_plane_enable
;
712 culldist_mask
|= clipdist_mask
;
714 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
715 vs_sel
->pa_cl_vs_out_cntl
|
716 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
717 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
718 clipdist_mask
| (culldist_mask
<< 8));
719 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
720 rs
->pa_cl_clip_cntl
|
722 S_028810_CLIP_DISABLE(window_space
));
724 if (sctx
->b
.chip_class
<= VI
) {
725 /* reuse needs to be set off if we write oViewport */
726 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
727 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
732 * inferred state between framebuffer and rasterizer
734 static void si_update_poly_offset_state(struct si_context
*sctx
)
736 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
738 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
739 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
743 /* Use the user format, not db_render_format, so that the polygon
744 * offset behaves as expected by applications.
746 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
747 case PIPE_FORMAT_Z16_UNORM
:
748 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
750 default: /* 24-bit */
751 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
753 case PIPE_FORMAT_Z32_FLOAT
:
754 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
755 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
764 static uint32_t si_translate_fill(uint32_t func
)
767 case PIPE_POLYGON_MODE_FILL
:
768 return V_028814_X_DRAW_TRIANGLES
;
769 case PIPE_POLYGON_MODE_LINE
:
770 return V_028814_X_DRAW_LINES
;
771 case PIPE_POLYGON_MODE_POINT
:
772 return V_028814_X_DRAW_POINTS
;
775 return V_028814_X_DRAW_POINTS
;
779 static void *si_create_rs_state(struct pipe_context
*ctx
,
780 const struct pipe_rasterizer_state
*state
)
782 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
783 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
784 struct si_pm4_state
*pm4
= &rs
->pm4
;
786 float psize_min
, psize_max
;
792 rs
->scissor_enable
= state
->scissor
;
793 rs
->clip_halfz
= state
->clip_halfz
;
794 rs
->two_side
= state
->light_twoside
;
795 rs
->multisample_enable
= state
->multisample
;
796 rs
->force_persample_interp
= state
->force_persample_interp
;
797 rs
->clip_plane_enable
= state
->clip_plane_enable
;
798 rs
->line_stipple_enable
= state
->line_stipple_enable
;
799 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
800 rs
->line_smooth
= state
->line_smooth
;
801 rs
->poly_smooth
= state
->poly_smooth
;
802 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
804 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
805 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
806 rs
->flatshade
= state
->flatshade
;
807 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
808 rs
->rasterizer_discard
= state
->rasterizer_discard
;
809 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
810 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
811 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
812 rs
->pa_cl_clip_cntl
=
813 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
814 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
815 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
816 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
817 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
819 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
820 S_0286D4_FLAT_SHADE_ENA(1) |
821 S_0286D4_PNT_SPRITE_ENA(1) |
822 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
823 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
824 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
825 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
826 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
828 /* point size 12.4 fixed point */
829 tmp
= (unsigned)(state
->point_size
* 8.0);
830 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
832 if (state
->point_size_per_vertex
) {
833 psize_min
= util_get_min_point_size(state
);
836 /* Force the point size to be as if the vertex output was disabled. */
837 psize_min
= state
->point_size
;
838 psize_max
= state
->point_size
;
840 /* Divide by two, because 0.5 = 1 pixel. */
841 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
842 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
843 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
845 tmp
= (unsigned)state
->line_width
* 8;
846 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
847 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
848 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
849 S_028A48_MSAA_ENABLE(state
->multisample
||
850 state
->poly_smooth
||
851 state
->line_smooth
) |
852 S_028A48_VPORT_SCISSOR_ENABLE(1) |
853 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->b
.chip_class
>= GFX9
));
855 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
856 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
857 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
859 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
860 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
861 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
862 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
863 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
864 S_028814_FACE(!state
->front_ccw
) |
865 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
866 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
867 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
868 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
869 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
870 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
871 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
873 if (!rs
->uses_poly_offset
)
876 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
877 if (!rs
->pm4_poly_offset
) {
882 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
883 for (i
= 0; i
< 3; i
++) {
884 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
885 float offset_units
= state
->offset_units
;
886 float offset_scale
= state
->offset_scale
* 16.0f
;
887 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
889 if (!state
->offset_units_unscaled
) {
891 case 0: /* 16-bit zbuffer */
892 offset_units
*= 4.0f
;
893 pa_su_poly_offset_db_fmt_cntl
=
894 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
896 case 1: /* 24-bit zbuffer */
897 offset_units
*= 2.0f
;
898 pa_su_poly_offset_db_fmt_cntl
=
899 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
901 case 2: /* 32-bit zbuffer */
902 offset_units
*= 1.0f
;
903 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
904 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
909 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
911 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
913 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
915 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
917 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
918 pa_su_poly_offset_db_fmt_cntl
);
924 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
926 struct si_context
*sctx
= (struct si_context
*)ctx
;
927 struct si_state_rasterizer
*old_rs
=
928 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
929 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
934 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
935 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
937 /* Update the small primitive filter workaround if necessary. */
938 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
939 sctx
->framebuffer
.nr_samples
> 1)
940 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
943 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
944 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
946 r600_viewport_set_rast_deps(&sctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
948 si_pm4_bind_state(sctx
, rasterizer
, rs
);
949 si_update_poly_offset_state(sctx
);
952 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
953 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
954 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
956 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
957 rs
->line_stipple_enable
;
960 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
961 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
962 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
963 old_rs
->flatshade
!= rs
->flatshade
||
964 old_rs
->two_side
!= rs
->two_side
||
965 old_rs
->multisample_enable
!= rs
->multisample_enable
||
966 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
967 old_rs
->poly_smooth
!= rs
->poly_smooth
||
968 old_rs
->line_smooth
!= rs
->line_smooth
||
969 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
970 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
971 sctx
->do_update_shaders
= true;
974 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
976 struct si_context
*sctx
= (struct si_context
*)ctx
;
977 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
979 if (sctx
->queued
.named
.rasterizer
== state
)
980 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
982 FREE(rs
->pm4_poly_offset
);
983 si_pm4_delete_state(sctx
, rasterizer
, rs
);
987 * infeered state between dsa and stencil ref
989 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
991 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
992 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
993 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
995 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
996 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
997 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
998 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
999 S_028430_STENCILOPVAL(1));
1000 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1001 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1002 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1003 S_028434_STENCILOPVAL_BF(1));
1006 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1007 const struct pipe_stencil_ref
*state
)
1009 struct si_context
*sctx
= (struct si_context
*)ctx
;
1011 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1014 sctx
->stencil_ref
.state
= *state
;
1015 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1023 static uint32_t si_translate_stencil_op(int s_op
)
1026 case PIPE_STENCIL_OP_KEEP
:
1027 return V_02842C_STENCIL_KEEP
;
1028 case PIPE_STENCIL_OP_ZERO
:
1029 return V_02842C_STENCIL_ZERO
;
1030 case PIPE_STENCIL_OP_REPLACE
:
1031 return V_02842C_STENCIL_REPLACE_TEST
;
1032 case PIPE_STENCIL_OP_INCR
:
1033 return V_02842C_STENCIL_ADD_CLAMP
;
1034 case PIPE_STENCIL_OP_DECR
:
1035 return V_02842C_STENCIL_SUB_CLAMP
;
1036 case PIPE_STENCIL_OP_INCR_WRAP
:
1037 return V_02842C_STENCIL_ADD_WRAP
;
1038 case PIPE_STENCIL_OP_DECR_WRAP
:
1039 return V_02842C_STENCIL_SUB_WRAP
;
1040 case PIPE_STENCIL_OP_INVERT
:
1041 return V_02842C_STENCIL_INVERT
;
1043 R600_ERR("Unknown stencil op %d", s_op
);
1050 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1051 const struct pipe_depth_stencil_alpha_state
*state
)
1053 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1054 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1055 unsigned db_depth_control
;
1056 uint32_t db_stencil_control
= 0;
1062 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1063 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1064 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1065 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1067 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1068 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1069 S_028800_ZFUNC(state
->depth
.func
) |
1070 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1073 if (state
->stencil
[0].enabled
) {
1074 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1075 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1076 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1077 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1078 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1080 if (state
->stencil
[1].enabled
) {
1081 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1082 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1083 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1084 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1085 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1090 if (state
->alpha
.enabled
) {
1091 dsa
->alpha_func
= state
->alpha
.func
;
1093 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1094 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1096 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1099 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1100 if (state
->stencil
[0].enabled
)
1101 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1102 if (state
->depth
.bounds_test
) {
1103 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1104 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1110 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1112 struct si_context
*sctx
= (struct si_context
*)ctx
;
1113 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1114 struct si_state_dsa
*dsa
= state
;
1119 si_pm4_bind_state(sctx
, dsa
, dsa
);
1121 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1122 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1123 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1124 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1127 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1128 sctx
->do_update_shaders
= true;
1131 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1133 struct si_context
*sctx
= (struct si_context
*)ctx
;
1134 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1137 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1139 struct pipe_depth_stencil_alpha_state dsa
= {};
1141 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1144 /* DB RENDER STATE */
1146 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1148 struct si_context
*sctx
= (struct si_context
*)ctx
;
1150 /* Pipeline stat & streamout queries. */
1152 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1153 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1155 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1156 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1159 /* Occlusion queries. */
1160 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1161 sctx
->occlusion_queries_disabled
= !enable
;
1162 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1166 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
1168 struct si_context
*sctx
= (struct si_context
*)ctx
;
1170 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1173 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1175 struct si_context
*sctx
= (struct si_context
*)ctx
;
1177 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1179 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1180 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1183 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1185 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1186 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1187 unsigned db_shader_control
;
1189 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1191 /* DB_RENDER_CONTROL */
1192 if (sctx
->dbcb_depth_copy_enabled
||
1193 sctx
->dbcb_stencil_copy_enabled
) {
1195 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1196 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1197 S_028000_COPY_CENTROID(1) |
1198 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1199 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1201 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1202 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1205 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1206 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1209 /* DB_COUNT_CONTROL (occlusion queries) */
1210 if (sctx
->b
.num_occlusion_queries
> 0 &&
1211 !sctx
->occlusion_queries_disabled
) {
1212 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1214 if (sctx
->b
.chip_class
>= CIK
) {
1216 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1217 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1218 S_028004_ZPASS_ENABLE(1) |
1219 S_028004_SLICE_EVEN_ENABLE(1) |
1220 S_028004_SLICE_ODD_ENABLE(1));
1223 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1224 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1227 /* Disable occlusion queries. */
1228 if (sctx
->b
.chip_class
>= CIK
) {
1231 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1235 /* DB_RENDER_OVERRIDE2 */
1236 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1237 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1238 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1239 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1241 db_shader_control
= sctx
->ps_db_shader_control
;
1243 /* Bug workaround for smoothing (overrasterization) on SI. */
1244 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1245 db_shader_control
&= C_02880C_Z_ORDER
;
1246 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1249 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1250 if (!rs
|| !rs
->multisample_enable
)
1251 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1253 if (sctx
->screen
->b
.has_rbplus
&&
1254 !sctx
->screen
->b
.rbplus_allowed
)
1255 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1257 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1262 * format translation
1264 static uint32_t si_translate_colorformat(enum pipe_format format
)
1266 const struct util_format_description
*desc
= util_format_description(format
);
1268 #define HAS_SIZE(x,y,z,w) \
1269 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1270 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1272 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1273 return V_028C70_COLOR_10_11_11
;
1275 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1276 return V_028C70_COLOR_INVALID
;
1278 /* hw cannot support mixed formats (except depth/stencil, since
1279 * stencil is not written to). */
1280 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1281 return V_028C70_COLOR_INVALID
;
1283 switch (desc
->nr_channels
) {
1285 switch (desc
->channel
[0].size
) {
1287 return V_028C70_COLOR_8
;
1289 return V_028C70_COLOR_16
;
1291 return V_028C70_COLOR_32
;
1295 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1296 switch (desc
->channel
[0].size
) {
1298 return V_028C70_COLOR_8_8
;
1300 return V_028C70_COLOR_16_16
;
1302 return V_028C70_COLOR_32_32
;
1304 } else if (HAS_SIZE(8,24,0,0)) {
1305 return V_028C70_COLOR_24_8
;
1306 } else if (HAS_SIZE(24,8,0,0)) {
1307 return V_028C70_COLOR_8_24
;
1311 if (HAS_SIZE(5,6,5,0)) {
1312 return V_028C70_COLOR_5_6_5
;
1313 } else if (HAS_SIZE(32,8,24,0)) {
1314 return V_028C70_COLOR_X24_8_32_FLOAT
;
1318 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1319 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1320 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1321 switch (desc
->channel
[0].size
) {
1323 return V_028C70_COLOR_4_4_4_4
;
1325 return V_028C70_COLOR_8_8_8_8
;
1327 return V_028C70_COLOR_16_16_16_16
;
1329 return V_028C70_COLOR_32_32_32_32
;
1331 } else if (HAS_SIZE(5,5,5,1)) {
1332 return V_028C70_COLOR_1_5_5_5
;
1333 } else if (HAS_SIZE(10,10,10,2)) {
1334 return V_028C70_COLOR_2_10_10_10
;
1338 return V_028C70_COLOR_INVALID
;
1341 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1343 if (SI_BIG_ENDIAN
) {
1344 switch(colorformat
) {
1345 /* 8-bit buffers. */
1346 case V_028C70_COLOR_8
:
1347 return V_028C70_ENDIAN_NONE
;
1349 /* 16-bit buffers. */
1350 case V_028C70_COLOR_5_6_5
:
1351 case V_028C70_COLOR_1_5_5_5
:
1352 case V_028C70_COLOR_4_4_4_4
:
1353 case V_028C70_COLOR_16
:
1354 case V_028C70_COLOR_8_8
:
1355 return V_028C70_ENDIAN_8IN16
;
1357 /* 32-bit buffers. */
1358 case V_028C70_COLOR_8_8_8_8
:
1359 case V_028C70_COLOR_2_10_10_10
:
1360 case V_028C70_COLOR_8_24
:
1361 case V_028C70_COLOR_24_8
:
1362 case V_028C70_COLOR_16_16
:
1363 return V_028C70_ENDIAN_8IN32
;
1365 /* 64-bit buffers. */
1366 case V_028C70_COLOR_16_16_16_16
:
1367 return V_028C70_ENDIAN_8IN16
;
1369 case V_028C70_COLOR_32_32
:
1370 return V_028C70_ENDIAN_8IN32
;
1372 /* 128-bit buffers. */
1373 case V_028C70_COLOR_32_32_32_32
:
1374 return V_028C70_ENDIAN_8IN32
;
1376 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1379 return V_028C70_ENDIAN_NONE
;
1383 static uint32_t si_translate_dbformat(enum pipe_format format
)
1386 case PIPE_FORMAT_Z16_UNORM
:
1387 return V_028040_Z_16
;
1388 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1389 case PIPE_FORMAT_X8Z24_UNORM
:
1390 case PIPE_FORMAT_Z24X8_UNORM
:
1391 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1392 return V_028040_Z_24
; /* deprecated on SI */
1393 case PIPE_FORMAT_Z32_FLOAT
:
1394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1395 return V_028040_Z_32_FLOAT
;
1397 return V_028040_Z_INVALID
;
1402 * Texture translation
1405 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1406 enum pipe_format format
,
1407 const struct util_format_description
*desc
,
1410 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1411 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1412 sscreen
->b
.info
.drm_minor
>= 31) ||
1413 sscreen
->b
.info
.drm_major
== 3;
1414 bool uniform
= true;
1417 /* Colorspace (return non-RGB formats directly). */
1418 switch (desc
->colorspace
) {
1419 /* Depth stencil formats */
1420 case UTIL_FORMAT_COLORSPACE_ZS
:
1422 case PIPE_FORMAT_Z16_UNORM
:
1423 return V_008F14_IMG_DATA_FORMAT_16
;
1424 case PIPE_FORMAT_X24S8_UINT
:
1425 case PIPE_FORMAT_S8X24_UINT
:
1427 * Implemented as an 8_8_8_8 data format to fix texture
1428 * gathers in stencil sampling. This affects at least
1429 * GL45-CTS.texture_cube_map_array.sampling on VI.
1431 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1432 case PIPE_FORMAT_Z24X8_UNORM
:
1433 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1434 return V_008F14_IMG_DATA_FORMAT_8_24
;
1435 case PIPE_FORMAT_X8Z24_UNORM
:
1436 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1437 return V_008F14_IMG_DATA_FORMAT_24_8
;
1438 case PIPE_FORMAT_S8_UINT
:
1439 return V_008F14_IMG_DATA_FORMAT_8
;
1440 case PIPE_FORMAT_Z32_FLOAT
:
1441 return V_008F14_IMG_DATA_FORMAT_32
;
1442 case PIPE_FORMAT_X32_S8X24_UINT
:
1443 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1444 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1449 case UTIL_FORMAT_COLORSPACE_YUV
:
1450 goto out_unknown
; /* TODO */
1452 case UTIL_FORMAT_COLORSPACE_SRGB
:
1453 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1461 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1462 if (!enable_compressed_formats
)
1466 case PIPE_FORMAT_RGTC1_SNORM
:
1467 case PIPE_FORMAT_LATC1_SNORM
:
1468 case PIPE_FORMAT_RGTC1_UNORM
:
1469 case PIPE_FORMAT_LATC1_UNORM
:
1470 return V_008F14_IMG_DATA_FORMAT_BC4
;
1471 case PIPE_FORMAT_RGTC2_SNORM
:
1472 case PIPE_FORMAT_LATC2_SNORM
:
1473 case PIPE_FORMAT_RGTC2_UNORM
:
1474 case PIPE_FORMAT_LATC2_UNORM
:
1475 return V_008F14_IMG_DATA_FORMAT_BC5
;
1481 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1482 (sscreen
->b
.family
== CHIP_STONEY
||
1483 sscreen
->b
.chip_class
>= GFX9
)) {
1485 case PIPE_FORMAT_ETC1_RGB8
:
1486 case PIPE_FORMAT_ETC2_RGB8
:
1487 case PIPE_FORMAT_ETC2_SRGB8
:
1488 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1489 case PIPE_FORMAT_ETC2_RGB8A1
:
1490 case PIPE_FORMAT_ETC2_SRGB8A1
:
1491 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1492 case PIPE_FORMAT_ETC2_RGBA8
:
1493 case PIPE_FORMAT_ETC2_SRGBA8
:
1494 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1495 case PIPE_FORMAT_ETC2_R11_UNORM
:
1496 case PIPE_FORMAT_ETC2_R11_SNORM
:
1497 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1498 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1499 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1500 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1506 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1507 if (!enable_compressed_formats
)
1511 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1512 case PIPE_FORMAT_BPTC_SRGBA
:
1513 return V_008F14_IMG_DATA_FORMAT_BC7
;
1514 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1515 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1516 return V_008F14_IMG_DATA_FORMAT_BC6
;
1522 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1524 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1525 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1526 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1527 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1528 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1529 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1535 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1536 if (!enable_compressed_formats
)
1539 if (!util_format_s3tc_enabled
) {
1544 case PIPE_FORMAT_DXT1_RGB
:
1545 case PIPE_FORMAT_DXT1_RGBA
:
1546 case PIPE_FORMAT_DXT1_SRGB
:
1547 case PIPE_FORMAT_DXT1_SRGBA
:
1548 return V_008F14_IMG_DATA_FORMAT_BC1
;
1549 case PIPE_FORMAT_DXT3_RGBA
:
1550 case PIPE_FORMAT_DXT3_SRGBA
:
1551 return V_008F14_IMG_DATA_FORMAT_BC2
;
1552 case PIPE_FORMAT_DXT5_RGBA
:
1553 case PIPE_FORMAT_DXT5_SRGBA
:
1554 return V_008F14_IMG_DATA_FORMAT_BC3
;
1560 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1561 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1562 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1563 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1566 /* R8G8Bx_SNORM - TODO CxV8U8 */
1568 /* hw cannot support mixed formats (except depth/stencil, since only
1570 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1573 /* See whether the components are of the same size. */
1574 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1575 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1578 /* Non-uniform formats. */
1580 switch(desc
->nr_channels
) {
1582 if (desc
->channel
[0].size
== 5 &&
1583 desc
->channel
[1].size
== 6 &&
1584 desc
->channel
[2].size
== 5) {
1585 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1589 if (desc
->channel
[0].size
== 5 &&
1590 desc
->channel
[1].size
== 5 &&
1591 desc
->channel
[2].size
== 5 &&
1592 desc
->channel
[3].size
== 1) {
1593 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1595 if (desc
->channel
[0].size
== 10 &&
1596 desc
->channel
[1].size
== 10 &&
1597 desc
->channel
[2].size
== 10 &&
1598 desc
->channel
[3].size
== 2) {
1599 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1606 if (first_non_void
< 0 || first_non_void
> 3)
1609 /* uniform formats */
1610 switch (desc
->channel
[first_non_void
].size
) {
1612 switch (desc
->nr_channels
) {
1613 #if 0 /* Not supported for render targets */
1615 return V_008F14_IMG_DATA_FORMAT_4_4
;
1618 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1622 switch (desc
->nr_channels
) {
1624 return V_008F14_IMG_DATA_FORMAT_8
;
1626 return V_008F14_IMG_DATA_FORMAT_8_8
;
1628 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1632 switch (desc
->nr_channels
) {
1634 return V_008F14_IMG_DATA_FORMAT_16
;
1636 return V_008F14_IMG_DATA_FORMAT_16_16
;
1638 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1642 switch (desc
->nr_channels
) {
1644 return V_008F14_IMG_DATA_FORMAT_32
;
1646 return V_008F14_IMG_DATA_FORMAT_32_32
;
1647 #if 0 /* Not supported for render targets */
1649 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1652 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1657 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1661 static unsigned si_tex_wrap(unsigned wrap
)
1665 case PIPE_TEX_WRAP_REPEAT
:
1666 return V_008F30_SQ_TEX_WRAP
;
1667 case PIPE_TEX_WRAP_CLAMP
:
1668 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1669 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1670 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1671 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1672 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1673 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1674 return V_008F30_SQ_TEX_MIRROR
;
1675 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1676 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1677 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1678 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1679 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1680 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1684 static unsigned si_tex_mipfilter(unsigned filter
)
1687 case PIPE_TEX_MIPFILTER_NEAREST
:
1688 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1689 case PIPE_TEX_MIPFILTER_LINEAR
:
1690 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1692 case PIPE_TEX_MIPFILTER_NONE
:
1693 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1697 static unsigned si_tex_compare(unsigned compare
)
1701 case PIPE_FUNC_NEVER
:
1702 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1703 case PIPE_FUNC_LESS
:
1704 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1705 case PIPE_FUNC_EQUAL
:
1706 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1707 case PIPE_FUNC_LEQUAL
:
1708 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1709 case PIPE_FUNC_GREATER
:
1710 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1711 case PIPE_FUNC_NOTEQUAL
:
1712 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1713 case PIPE_FUNC_GEQUAL
:
1714 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1715 case PIPE_FUNC_ALWAYS
:
1716 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1720 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1721 unsigned view_target
, unsigned nr_samples
)
1723 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1725 if (view_target
== PIPE_TEXTURE_CUBE
||
1726 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1727 res_target
= view_target
;
1728 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1729 else if (res_target
== PIPE_TEXTURE_CUBE
||
1730 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1731 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1733 /* GFX9 allocates 1D textures as 2D. */
1734 if ((res_target
== PIPE_TEXTURE_1D
||
1735 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1736 sscreen
->b
.chip_class
>= GFX9
&&
1737 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1738 if (res_target
== PIPE_TEXTURE_1D
)
1739 res_target
= PIPE_TEXTURE_2D
;
1741 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1744 switch (res_target
) {
1746 case PIPE_TEXTURE_1D
:
1747 return V_008F1C_SQ_RSRC_IMG_1D
;
1748 case PIPE_TEXTURE_1D_ARRAY
:
1749 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1750 case PIPE_TEXTURE_2D
:
1751 case PIPE_TEXTURE_RECT
:
1752 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1753 V_008F1C_SQ_RSRC_IMG_2D
;
1754 case PIPE_TEXTURE_2D_ARRAY
:
1755 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1756 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1757 case PIPE_TEXTURE_3D
:
1758 return V_008F1C_SQ_RSRC_IMG_3D
;
1759 case PIPE_TEXTURE_CUBE
:
1760 case PIPE_TEXTURE_CUBE_ARRAY
:
1761 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1766 * Format support testing
1769 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1771 return si_translate_texformat(screen
, format
, util_format_description(format
),
1772 util_format_get_first_non_void_channel(format
)) != ~0U;
1775 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1776 const struct util_format_description
*desc
,
1781 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1782 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1784 assert(first_non_void
>= 0);
1786 if (desc
->nr_channels
== 4 &&
1787 desc
->channel
[0].size
== 10 &&
1788 desc
->channel
[1].size
== 10 &&
1789 desc
->channel
[2].size
== 10 &&
1790 desc
->channel
[3].size
== 2)
1791 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1793 /* See whether the components are of the same size. */
1794 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1795 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1796 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1799 switch (desc
->channel
[first_non_void
].size
) {
1801 switch (desc
->nr_channels
) {
1803 case 3: /* 3 loads */
1804 return V_008F0C_BUF_DATA_FORMAT_8
;
1806 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1808 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1812 switch (desc
->nr_channels
) {
1814 case 3: /* 3 loads */
1815 return V_008F0C_BUF_DATA_FORMAT_16
;
1817 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1819 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1823 switch (desc
->nr_channels
) {
1825 return V_008F0C_BUF_DATA_FORMAT_32
;
1827 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1829 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1831 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1835 /* Legacy double formats. */
1836 switch (desc
->nr_channels
) {
1837 case 1: /* 1 load */
1838 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1839 case 2: /* 1 load */
1840 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1841 case 3: /* 3 loads */
1842 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1843 case 4: /* 2 loads */
1844 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1849 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1852 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1853 const struct util_format_description
*desc
,
1856 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1857 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1859 assert(first_non_void
>= 0);
1861 switch (desc
->channel
[first_non_void
].type
) {
1862 case UTIL_FORMAT_TYPE_SIGNED
:
1863 case UTIL_FORMAT_TYPE_FIXED
:
1864 if (desc
->channel
[first_non_void
].size
>= 32 ||
1865 desc
->channel
[first_non_void
].pure_integer
)
1866 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1867 else if (desc
->channel
[first_non_void
].normalized
)
1868 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1870 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1872 case UTIL_FORMAT_TYPE_UNSIGNED
:
1873 if (desc
->channel
[first_non_void
].size
>= 32 ||
1874 desc
->channel
[first_non_void
].pure_integer
)
1875 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1876 else if (desc
->channel
[first_non_void
].normalized
)
1877 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1879 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1881 case UTIL_FORMAT_TYPE_FLOAT
:
1883 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1887 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
1888 enum pipe_format format
,
1891 const struct util_format_description
*desc
;
1893 unsigned data_format
;
1895 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
1896 PIPE_BIND_SAMPLER_VIEW
|
1897 PIPE_BIND_VERTEX_BUFFER
)) == 0);
1899 desc
= util_format_description(format
);
1901 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1902 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1903 * for read-only access (with caveats surrounding bounds checks), but
1904 * obviously fails for write access which we have to implement for
1905 * shader images. Luckily, OpenGL doesn't expect this to be supported
1906 * anyway, and so the only impact is on PBO uploads / downloads, which
1907 * shouldn't be expected to be fast for GL_RGB anyway.
1909 if (desc
->block
.bits
== 3 * 8 ||
1910 desc
->block
.bits
== 3 * 16) {
1911 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
1912 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
1918 first_non_void
= util_format_get_first_non_void_channel(format
);
1919 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1920 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
1926 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1928 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1929 r600_translate_colorswap(format
, false) != ~0U;
1932 static bool si_is_zs_format_supported(enum pipe_format format
)
1934 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1937 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
1938 enum pipe_format format
,
1939 enum pipe_texture_target target
,
1940 unsigned sample_count
,
1943 unsigned retval
= 0;
1945 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1946 R600_ERR("r600: unsupported texture type %d\n", target
);
1950 if (!util_format_is_supported(format
, usage
))
1953 if (sample_count
> 1) {
1954 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1957 if (usage
& PIPE_BIND_SHADER_IMAGE
)
1960 switch (sample_count
) {
1966 if (format
== PIPE_FORMAT_NONE
)
1975 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
1976 PIPE_BIND_SHADER_IMAGE
)) {
1977 if (target
== PIPE_BUFFER
) {
1978 retval
|= si_is_vertex_format_supported(
1979 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
1980 PIPE_BIND_SHADER_IMAGE
));
1982 if (si_is_sampler_format_supported(screen
, format
))
1983 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
1984 PIPE_BIND_SHADER_IMAGE
);
1988 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1989 PIPE_BIND_DISPLAY_TARGET
|
1992 PIPE_BIND_BLENDABLE
)) &&
1993 si_is_colorbuffer_format_supported(format
)) {
1995 (PIPE_BIND_RENDER_TARGET
|
1996 PIPE_BIND_DISPLAY_TARGET
|
1999 if (!util_format_is_pure_integer(format
) &&
2000 !util_format_is_depth_or_stencil(format
))
2001 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2004 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2005 si_is_zs_format_supported(format
)) {
2006 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2009 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2010 retval
|= si_is_vertex_format_supported(screen
, format
,
2011 PIPE_BIND_VERTEX_BUFFER
);
2014 if ((usage
& PIPE_BIND_LINEAR
) &&
2015 !util_format_is_compressed(format
) &&
2016 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2017 retval
|= PIPE_BIND_LINEAR
;
2019 return retval
== usage
;
2023 * framebuffer handling
2026 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2027 unsigned format
, unsigned swap
,
2028 unsigned ntype
, bool is_depth
)
2030 /* Alpha is needed for alpha-to-coverage.
2031 * Blending may be with or without alpha.
2033 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2034 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2035 unsigned blend
= 0; /* supports blending, but may not export alpha */
2036 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2038 /* Choose the SPI color formats. These are required values for RB+.
2039 * Other chips have multiple choices, though they are not necessarily better.
2042 case V_028C70_COLOR_5_6_5
:
2043 case V_028C70_COLOR_1_5_5_5
:
2044 case V_028C70_COLOR_5_5_5_1
:
2045 case V_028C70_COLOR_4_4_4_4
:
2046 case V_028C70_COLOR_10_11_11
:
2047 case V_028C70_COLOR_11_11_10
:
2048 case V_028C70_COLOR_8
:
2049 case V_028C70_COLOR_8_8
:
2050 case V_028C70_COLOR_8_8_8_8
:
2051 case V_028C70_COLOR_10_10_10_2
:
2052 case V_028C70_COLOR_2_10_10_10
:
2053 if (ntype
== V_028C70_NUMBER_UINT
)
2054 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2055 else if (ntype
== V_028C70_NUMBER_SINT
)
2056 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2058 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2061 case V_028C70_COLOR_16
:
2062 case V_028C70_COLOR_16_16
:
2063 case V_028C70_COLOR_16_16_16_16
:
2064 if (ntype
== V_028C70_NUMBER_UNORM
||
2065 ntype
== V_028C70_NUMBER_SNORM
) {
2066 /* UNORM16 and SNORM16 don't support blending */
2067 if (ntype
== V_028C70_NUMBER_UNORM
)
2068 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2070 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2072 /* Use 32 bits per channel for blending. */
2073 if (format
== V_028C70_COLOR_16
) {
2074 if (swap
== V_028C70_SWAP_STD
) { /* R */
2075 blend
= V_028714_SPI_SHADER_32_R
;
2076 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2077 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2078 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2081 } else if (format
== V_028C70_COLOR_16_16
) {
2082 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2083 blend
= V_028714_SPI_SHADER_32_GR
;
2084 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2085 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2086 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2089 } else /* 16_16_16_16 */
2090 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2091 } else if (ntype
== V_028C70_NUMBER_UINT
)
2092 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2093 else if (ntype
== V_028C70_NUMBER_SINT
)
2094 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2095 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2096 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2101 case V_028C70_COLOR_32
:
2102 if (swap
== V_028C70_SWAP_STD
) { /* R */
2103 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2104 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2105 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2106 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2111 case V_028C70_COLOR_32_32
:
2112 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2113 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2114 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2115 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2116 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2121 case V_028C70_COLOR_32_32_32_32
:
2122 case V_028C70_COLOR_8_24
:
2123 case V_028C70_COLOR_24_8
:
2124 case V_028C70_COLOR_X24_8_32_FLOAT
:
2125 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2133 /* The DB->CB copy needs 32_ABGR. */
2135 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2137 surf
->spi_shader_col_format
= normal
;
2138 surf
->spi_shader_col_format_alpha
= alpha
;
2139 surf
->spi_shader_col_format_blend
= blend
;
2140 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2143 static void si_initialize_color_surface(struct si_context
*sctx
,
2144 struct r600_surface
*surf
)
2146 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2147 unsigned color_info
, color_attrib
, color_view
;
2148 unsigned format
, swap
, ntype
, endian
;
2149 const struct util_format_description
*desc
;
2151 unsigned blend_clamp
= 0, blend_bypass
= 0;
2153 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2154 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2156 desc
= util_format_description(surf
->base
.format
);
2157 for (i
= 0; i
< 4; i
++) {
2158 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2162 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2163 ntype
= V_028C70_NUMBER_FLOAT
;
2165 ntype
= V_028C70_NUMBER_UNORM
;
2166 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2167 ntype
= V_028C70_NUMBER_SRGB
;
2168 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2169 if (desc
->channel
[i
].pure_integer
) {
2170 ntype
= V_028C70_NUMBER_SINT
;
2172 assert(desc
->channel
[i
].normalized
);
2173 ntype
= V_028C70_NUMBER_SNORM
;
2175 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2176 if (desc
->channel
[i
].pure_integer
) {
2177 ntype
= V_028C70_NUMBER_UINT
;
2179 assert(desc
->channel
[i
].normalized
);
2180 ntype
= V_028C70_NUMBER_UNORM
;
2185 format
= si_translate_colorformat(surf
->base
.format
);
2186 if (format
== V_028C70_COLOR_INVALID
) {
2187 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2189 assert(format
!= V_028C70_COLOR_INVALID
);
2190 swap
= r600_translate_colorswap(surf
->base
.format
, false);
2191 endian
= si_colorformat_endian_swap(format
);
2193 /* blend clamp should be set for all NORM/SRGB types */
2194 if (ntype
== V_028C70_NUMBER_UNORM
||
2195 ntype
== V_028C70_NUMBER_SNORM
||
2196 ntype
== V_028C70_NUMBER_SRGB
)
2199 /* set blend bypass according to docs if SINT/UINT or
2200 8/24 COLOR variants */
2201 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2202 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2203 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2208 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2209 if (format
== V_028C70_COLOR_8
||
2210 format
== V_028C70_COLOR_8_8
||
2211 format
== V_028C70_COLOR_8_8_8_8
)
2212 surf
->color_is_int8
= true;
2213 else if (format
== V_028C70_COLOR_10_10_10_2
||
2214 format
== V_028C70_COLOR_2_10_10_10
)
2215 surf
->color_is_int10
= true;
2218 color_info
= S_028C70_FORMAT(format
) |
2219 S_028C70_COMP_SWAP(swap
) |
2220 S_028C70_BLEND_CLAMP(blend_clamp
) |
2221 S_028C70_BLEND_BYPASS(blend_bypass
) |
2222 S_028C70_SIMPLE_FLOAT(1) |
2223 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2224 ntype
!= V_028C70_NUMBER_SNORM
&&
2225 ntype
!= V_028C70_NUMBER_SRGB
&&
2226 format
!= V_028C70_COLOR_8_24
&&
2227 format
!= V_028C70_COLOR_24_8
) |
2228 S_028C70_NUMBER_TYPE(ntype
) |
2229 S_028C70_ENDIAN(endian
);
2231 /* Intensity is implemented as Red, so treat it that way. */
2232 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2233 util_format_is_intensity(surf
->base
.format
));
2235 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2236 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2238 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2239 S_028C74_NUM_FRAGMENTS(log_samples
);
2241 if (rtex
->fmask
.size
) {
2242 color_info
|= S_028C70_COMPRESSION(1);
2243 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2245 if (sctx
->b
.chip_class
== SI
) {
2246 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2247 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2252 surf
->cb_color_view
= color_view
;
2253 surf
->cb_color_info
= color_info
;
2254 surf
->cb_color_attrib
= color_attrib
;
2256 if (sctx
->b
.chip_class
>= VI
) {
2257 unsigned max_uncompressed_block_size
= 2;
2259 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2260 if (rtex
->surface
.bpe
== 1)
2261 max_uncompressed_block_size
= 0;
2262 else if (rtex
->surface
.bpe
== 2)
2263 max_uncompressed_block_size
= 1;
2266 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2267 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2270 /* This must be set for fast clear to work without FMASK. */
2271 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2272 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2273 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2276 if (sctx
->b
.chip_class
>= GFX9
) {
2277 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2279 surf
->cb_color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2280 surf
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2281 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2282 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2283 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2284 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2287 /* Determine pixel shader export format */
2288 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2290 surf
->color_initialized
= true;
2293 static void si_init_depth_surface(struct si_context
*sctx
,
2294 struct r600_surface
*surf
)
2296 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2297 unsigned level
= surf
->base
.u
.tex
.level
;
2298 unsigned format
, stencil_format
;
2299 uint32_t z_info
, s_info
;
2301 format
= si_translate_dbformat(rtex
->db_render_format
);
2302 stencil_format
= rtex
->surface
.flags
& RADEON_SURF_SBUFFER
?
2303 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2305 assert(format
!= V_028040_Z_INVALID
);
2306 if (format
== V_028040_Z_INVALID
)
2307 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2309 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2310 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2311 surf
->db_htile_data_base
= 0;
2312 surf
->db_htile_surface
= 0;
2314 if (sctx
->b
.chip_class
>= GFX9
) {
2315 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2316 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2317 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2318 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2319 z_info
= S_028038_FORMAT(format
) |
2320 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2321 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2322 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2323 s_info
= S_02803C_FORMAT(stencil_format
) |
2324 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2325 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2326 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2327 surf
->db_depth_view
|= S_028008_MIPID(level
);
2328 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2329 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2331 /* Only use HTILE for the first level. */
2332 if (rtex
->htile_offset
&& !level
) {
2333 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2334 S_028038_ALLOW_EXPCLEAR(1);
2336 if (rtex
->tc_compatible_htile
) {
2337 unsigned max_zplanes
= 4;
2339 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2340 rtex
->resource
.b
.b
.nr_samples
> 1)
2343 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2344 S_028038_ITERATE_FLUSH(1);
2345 s_info
|= S_02803C_ITERATE_FLUSH(1);
2348 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2349 /* Stencil buffer workaround ported from the SI-CI-VI code.
2350 * See that for explanation.
2352 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2354 /* Use all HTILE for depth if there's no stencil. */
2355 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2358 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2359 rtex
->htile_offset
) >> 8;
2360 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2361 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2362 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2366 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2368 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2370 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2371 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2372 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2373 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2375 z_info
= S_028040_FORMAT(format
) |
2376 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2377 s_info
= S_028044_FORMAT(stencil_format
);
2378 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2380 if (sctx
->b
.chip_class
>= CIK
) {
2381 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
2382 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2383 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2384 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2385 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2386 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2387 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2389 surf
->db_depth_info
|=
2390 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2391 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2392 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2393 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2394 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2395 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2396 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2397 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2399 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2400 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2401 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2402 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2405 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2406 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2407 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2408 levelinfo
->nblk_y
) / 64 - 1);
2410 /* Only use HTILE for the first level. */
2411 if (rtex
->htile_offset
&& !level
) {
2412 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2413 S_028040_ALLOW_EXPCLEAR(1);
2415 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2416 /* Workaround: For a not yet understood reason, the
2417 * combination of MSAA, fast stencil clear and stencil
2418 * decompress messes with subsequent stencil buffer
2419 * uses. Problem was reproduced on Verde, Bonaire,
2420 * Tonga, and Carrizo.
2422 * Disabling EXPCLEAR works around the problem.
2424 * Check piglit's arb_texture_multisample-stencil-clear
2425 * test if you want to try changing this.
2427 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2428 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2429 } else if (!rtex
->tc_compatible_htile
) {
2430 /* Use all of the htile_buffer for depth if there's no stencil.
2431 * This must not be set when TC-compatible HTILE is enabled
2434 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2437 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2438 rtex
->htile_offset
) >> 8;
2439 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2441 if (rtex
->tc_compatible_htile
) {
2442 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2444 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2445 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2446 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2447 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2449 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2454 surf
->db_z_info
= z_info
;
2455 surf
->db_stencil_info
= s_info
;
2457 surf
->depth_initialized
= true;
2460 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2462 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2463 struct r600_surface
*surf
= NULL
;
2464 struct r600_texture
*rtex
;
2466 if (!state
->cbufs
[i
])
2468 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2469 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2471 p_atomic_dec(&rtex
->framebuffers_bound
);
2475 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2476 const struct pipe_framebuffer_state
*state
)
2478 struct si_context
*sctx
= (struct si_context
*)ctx
;
2479 struct pipe_constant_buffer constbuf
= {0};
2480 struct r600_surface
*surf
= NULL
;
2481 struct r600_texture
*rtex
;
2482 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2483 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2484 bool unbound
= false;
2487 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2488 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2491 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2492 if (rtex
->dcc_gather_statistics
)
2493 vi_separate_dcc_stop_query(ctx
, rtex
);
2496 /* Disable DCC if the formats are incompatible. */
2497 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2498 if (!state
->cbufs
[i
])
2501 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2502 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2504 if (!surf
->dcc_incompatible
)
2507 /* Since the DCC decompression calls back into set_framebuffer-
2508 * _state, we need to unbind the framebuffer, so that
2509 * vi_separate_dcc_stop_query isn't called twice with the same
2513 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2517 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2518 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
2519 sctx
->b
.decompress_dcc(ctx
, rtex
);
2521 surf
->dcc_incompatible
= false;
2524 /* Only flush TC when changing the framebuffer state, because
2525 * the only client not using TC that can change textures is
2528 * Wait for compute shaders because of possible transitions:
2529 * - FB write -> shader read
2530 * - shader write -> FB read
2532 * DB caches are flushed on demand (using si_decompress_textures).
2534 * When MSAA is enabled, CB and TC caches are flushed on demand
2535 * (after FMASK decompression). Shader write -> FB read transitions
2536 * cannot happen for MSAA textures, because MSAA shader images are
2539 if (sctx
->framebuffer
.nr_samples
<= 1) {
2540 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2541 SI_CONTEXT_INV_GLOBAL_L2
|
2542 SI_CONTEXT_FLUSH_AND_INV_CB
;
2544 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2546 /* u_blitter doesn't invoke depth decompression when it does multiple
2547 * blits in a row, but the only case when it matters for DB is when
2548 * doing generate_mipmap. So here we flush DB manually between
2549 * individual generate_mipmap blits.
2550 * Note that lower mipmap levels aren't compressed.
2552 if (sctx
->generate_mipmap_for_depth
) {
2553 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2554 SI_CONTEXT_INV_GLOBAL_L2
|
2555 SI_CONTEXT_FLUSH_AND_INV_DB
;
2558 /* Take the maximum of the old and new count. If the new count is lower,
2559 * dirtying is needed to disable the unbound colorbuffers.
2561 sctx
->framebuffer
.dirty_cbufs
|=
2562 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2563 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2565 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2566 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2568 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2569 sctx
->framebuffer
.spi_shader_col_format
= 0;
2570 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2571 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2572 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2573 sctx
->framebuffer
.color_is_int8
= 0;
2574 sctx
->framebuffer
.color_is_int10
= 0;
2576 sctx
->framebuffer
.compressed_cb_mask
= 0;
2577 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2578 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2579 sctx
->framebuffer
.any_dst_linear
= false;
2581 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2582 if (!state
->cbufs
[i
])
2585 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2586 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2588 if (!surf
->color_initialized
) {
2589 si_initialize_color_surface(sctx
, surf
);
2592 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2593 sctx
->framebuffer
.spi_shader_col_format
|=
2594 surf
->spi_shader_col_format
<< (i
* 4);
2595 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2596 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2597 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2598 surf
->spi_shader_col_format_blend
<< (i
* 4);
2599 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2600 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2602 if (surf
->color_is_int8
)
2603 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2604 if (surf
->color_is_int10
)
2605 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2607 if (rtex
->fmask
.size
) {
2608 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2611 if (rtex
->surface
.is_linear
)
2612 sctx
->framebuffer
.any_dst_linear
= true;
2614 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2616 p_atomic_inc(&rtex
->framebuffers_bound
);
2618 if (rtex
->dcc_gather_statistics
) {
2619 /* Dirty tracking must be enabled for DCC usage analysis. */
2620 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2621 vi_separate_dcc_start_query(ctx
, rtex
);
2626 surf
= (struct r600_surface
*)state
->zsbuf
;
2627 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2629 if (!surf
->depth_initialized
) {
2630 si_init_depth_surface(sctx
, surf
);
2632 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2635 si_update_poly_offset_state(sctx
);
2636 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2637 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2639 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2640 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2642 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2643 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2644 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2646 /* Set sample locations as fragment shader constants. */
2647 switch (sctx
->framebuffer
.nr_samples
) {
2649 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2652 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2655 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2658 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2661 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2664 R600_ERR("Requested an invalid number of samples %i.\n",
2665 sctx
->framebuffer
.nr_samples
);
2668 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2669 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2671 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2674 sctx
->do_update_shaders
= true;
2676 if (!sctx
->decompression_enabled
) {
2677 /* Prevent textures decompression when the framebuffer state
2678 * changes come from the decompression passes themselves.
2680 sctx
->need_check_render_feedback
= true;
2681 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
2685 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2687 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2688 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2689 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2690 struct r600_texture
*tex
= NULL
;
2691 struct r600_surface
*cb
= NULL
;
2692 unsigned cb_color_info
= 0;
2695 for (i
= 0; i
< nr_cbufs
; i
++) {
2696 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2697 unsigned cb_color_attrib
;
2699 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2702 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2704 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2705 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2709 tex
= (struct r600_texture
*)cb
->base
.texture
;
2710 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2711 &tex
->resource
, RADEON_USAGE_READWRITE
,
2712 tex
->resource
.b
.b
.nr_samples
> 1 ?
2713 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2714 RADEON_PRIO_COLOR_BUFFER
);
2716 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2717 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2718 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2722 if (tex
->dcc_separate_buffer
)
2723 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2724 tex
->dcc_separate_buffer
,
2725 RADEON_USAGE_READWRITE
,
2728 /* Compute mutable surface parameters. */
2729 cb_color_base
= tex
->resource
.gpu_address
>> 8;
2730 cb_color_fmask
= cb_color_base
;
2732 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2733 cb_color_attrib
= cb
->cb_color_attrib
;
2735 if (tex
->fmask
.size
)
2736 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
2739 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
2740 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
2741 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2742 state
->cbufs
[1] == &cb
->base
&&
2743 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2745 if (!is_msaa_resolve_dst
)
2746 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2748 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
2749 tex
->dcc_offset
) >> 8;
2752 if (sctx
->b
.chip_class
>= GFX9
) {
2753 struct gfx9_surf_meta_flags meta
;
2755 if (tex
->dcc_offset
)
2756 meta
= tex
->surface
.u
.gfx9
.dcc
;
2758 meta
= tex
->surface
.u
.gfx9
.cmask
;
2760 /* Set mutable surface parameters. */
2761 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
2762 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2763 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2764 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2765 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2767 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
2768 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
2769 radeon_emit(cs
, cb_color_base
>> 32); /* CB_COLOR0_BASE_EXT */
2770 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
2771 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
2772 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
2773 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
2774 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
2775 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
2776 radeon_emit(cs
, tex
->cmask
.base_address_reg
>> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2777 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
2778 radeon_emit(cs
, cb_color_fmask
>> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2779 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
2780 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
2781 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
2782 radeon_emit(cs
, cb_dcc_base
>> 32); /* CB_COLOR0_DCC_BASE_EXT */
2784 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
2785 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
2787 /* Compute mutable surface parameters (SI-CI-VI). */
2788 const struct legacy_surf_level
*level_info
=
2789 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
2790 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2791 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
2793 cb_color_base
+= level_info
->offset
>> 8;
2795 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
2797 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2798 slice_tile_max
= level_info
->nblk_x
*
2799 level_info
->nblk_y
/ 64 - 1;
2800 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
2802 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2803 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2804 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2806 if (tex
->fmask
.size
) {
2807 if (sctx
->b
.chip_class
>= CIK
)
2808 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
2809 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
2810 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
2812 /* This must be set for fast clear to work without FMASK. */
2813 if (sctx
->b
.chip_class
>= CIK
)
2814 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2815 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2816 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2819 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2820 sctx
->b
.chip_class
>= VI
? 14 : 13);
2821 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
2822 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
2823 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
2824 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
2825 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
2826 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
2827 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
2828 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
2829 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
2830 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
2831 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
2832 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
2833 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
2835 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
2836 radeon_emit(cs
, cb_dcc_base
);
2840 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
2841 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2844 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
2845 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2846 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2848 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2849 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2850 zb
->base
.texture
->nr_samples
> 1 ?
2851 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2852 RADEON_PRIO_DEPTH_BUFFER
);
2854 if (sctx
->b
.chip_class
>= GFX9
) {
2855 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
2856 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
2857 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
2858 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
2860 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
2861 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
2862 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2863 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
2864 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
2865 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
2866 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
2867 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
2868 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
2869 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
2870 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
2871 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
2873 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
2874 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
2875 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
2877 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2879 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2880 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
2881 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
2882 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2883 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
2884 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
2885 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
2886 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
2887 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
2888 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
2889 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
2892 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
2893 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
2894 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
2896 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2897 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2898 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
2899 if (sctx
->b
.chip_class
>= GFX9
)
2900 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
2902 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2904 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2905 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2908 /* Framebuffer dimensions. */
2909 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2910 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2911 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2913 if (sctx
->b
.chip_class
>= GFX9
) {
2914 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2915 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2918 sctx
->framebuffer
.dirty_cbufs
= 0;
2919 sctx
->framebuffer
.dirty_zsbuf
= false;
2922 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
2923 struct r600_atom
*atom
)
2925 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2926 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2927 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
2929 /* Smoothing (only possible with nr_samples == 1) uses the same
2930 * sample locations as the MSAA it simulates.
2932 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
2933 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
2935 /* On Polaris, the small primitive filter uses the sample locations
2936 * even when MSAA is off, so we need to make sure they're set to 0.
2938 if (has_msaa_sample_loc_bug
)
2939 nr_samples
= MAX2(nr_samples
, 1);
2941 if (nr_samples
>= 1 &&
2942 (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
)) {
2943 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
2944 cayman_emit_msaa_sample_locs(cs
, nr_samples
);
2947 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
2948 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2949 unsigned small_prim_filter_cntl
=
2950 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2952 S_028830_LINE_FILTER_DISABLE(sctx
->b
.family
<= CHIP_POLARIS12
);
2954 /* The alternative of setting sample locations to 0 would
2955 * require a DB flush to avoid Z errors, see
2956 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2958 if (has_msaa_sample_loc_bug
&&
2959 sctx
->framebuffer
.nr_samples
> 1 &&
2960 rs
&& !rs
->multisample_enable
)
2961 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
2963 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
2964 small_prim_filter_cntl
);
2968 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
2970 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2971 unsigned num_tile_pipes
= sctx
->screen
->b
.info
.num_tile_pipes
;
2972 /* 33% faster rendering to linear color buffers */
2973 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
2974 unsigned sc_mode_cntl_1
=
2975 S_028A4C_WALK_SIZE(dst_is_linear
) |
2976 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
2977 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
2979 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2980 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2981 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2982 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2983 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2984 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2986 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2987 sctx
->ps_iter_samples
,
2988 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0,
2991 /* GFX9: Flush DFSM when the AA mode changes. */
2992 if (sctx
->b
.chip_class
>= GFX9
) {
2993 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2994 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
2998 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3000 struct si_context
*sctx
= (struct si_context
*)ctx
;
3002 if (sctx
->ps_iter_samples
== min_samples
)
3005 sctx
->ps_iter_samples
= min_samples
;
3006 sctx
->do_update_shaders
= true;
3008 if (sctx
->framebuffer
.nr_samples
> 1)
3009 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3017 * Build the sampler view descriptor for a buffer texture.
3018 * @param state 256-bit descriptor; only the high 128 bits are filled in
3021 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3022 enum pipe_format format
,
3023 unsigned offset
, unsigned size
,
3026 const struct util_format_description
*desc
;
3029 unsigned num_records
;
3030 unsigned num_format
, data_format
;
3032 desc
= util_format_description(format
);
3033 first_non_void
= util_format_get_first_non_void_channel(format
);
3034 stride
= desc
->block
.bits
/ 8;
3035 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
3036 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
3038 num_records
= size
/ stride
;
3039 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3041 /* The NUM_RECORDS field has a different meaning depending on the chip,
3042 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3045 * - If STRIDE == 0, it's in byte units.
3046 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3049 * - For SMEM and STRIDE == 0, it's in byte units.
3050 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3051 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3052 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3053 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3054 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3055 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3056 * That way the same descriptor can be used by both SMEM and VMEM.
3059 * - For SMEM and STRIDE == 0, it's in byte units.
3060 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3061 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3062 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3064 if (screen
->b
.chip_class
>= GFX9
)
3065 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3066 * from STRIDE to bytes. This works around it by setting
3067 * NUM_RECORDS to at least the size of one element, so that
3068 * the first element is readable when IDXEN == 0.
3070 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3071 * IDXEN is enforced?
3073 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3074 else if (screen
->b
.chip_class
== VI
)
3075 num_records
*= stride
;
3078 state
[5] = S_008F04_STRIDE(stride
);
3079 state
[6] = num_records
;
3080 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3081 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3082 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3083 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3084 S_008F0C_NUM_FORMAT(num_format
) |
3085 S_008F0C_DATA_FORMAT(data_format
);
3088 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3090 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3092 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3093 /* For the pre-defined border color values (white, opaque
3094 * black, transparent black), the only thing that matters is
3095 * that the alpha channel winds up in the correct place
3096 * (because the RGB channels are all the same) so either of
3097 * these enumerations will work.
3099 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3100 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3102 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3103 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3104 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3105 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3107 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3108 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3109 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3110 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3111 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3118 * Build the sampler view descriptor for a texture.
3121 si_make_texture_descriptor(struct si_screen
*screen
,
3122 struct r600_texture
*tex
,
3124 enum pipe_texture_target target
,
3125 enum pipe_format pipe_format
,
3126 const unsigned char state_swizzle
[4],
3127 unsigned first_level
, unsigned last_level
,
3128 unsigned first_layer
, unsigned last_layer
,
3129 unsigned width
, unsigned height
, unsigned depth
,
3131 uint32_t *fmask_state
)
3133 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
3134 const struct util_format_description
*base_desc
, *desc
;
3135 unsigned char swizzle
[4];
3137 unsigned num_format
, data_format
, type
;
3140 desc
= util_format_description(pipe_format
);
3141 base_desc
= util_format_description(res
->format
);
3143 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3144 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3145 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3146 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3148 switch (pipe_format
) {
3149 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3150 case PIPE_FORMAT_X32_S8X24_UINT
:
3151 case PIPE_FORMAT_X8Z24_UNORM
:
3152 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3154 case PIPE_FORMAT_X24S8_UINT
:
3156 * X24S8 is implemented as an 8_8_8_8 data format, to
3157 * fix texture gathers. This affects at least
3158 * GL45-CTS.texture_cube_map_array.sampling on VI.
3160 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3163 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3166 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3169 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3171 switch (pipe_format
) {
3172 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3173 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3176 if (first_non_void
< 0) {
3177 if (util_format_is_compressed(pipe_format
)) {
3178 switch (pipe_format
) {
3179 case PIPE_FORMAT_DXT1_SRGB
:
3180 case PIPE_FORMAT_DXT1_SRGBA
:
3181 case PIPE_FORMAT_DXT3_SRGBA
:
3182 case PIPE_FORMAT_DXT5_SRGBA
:
3183 case PIPE_FORMAT_BPTC_SRGBA
:
3184 case PIPE_FORMAT_ETC2_SRGB8
:
3185 case PIPE_FORMAT_ETC2_SRGB8A1
:
3186 case PIPE_FORMAT_ETC2_SRGBA8
:
3187 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3189 case PIPE_FORMAT_RGTC1_SNORM
:
3190 case PIPE_FORMAT_LATC1_SNORM
:
3191 case PIPE_FORMAT_RGTC2_SNORM
:
3192 case PIPE_FORMAT_LATC2_SNORM
:
3193 case PIPE_FORMAT_ETC2_R11_SNORM
:
3194 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3195 /* implies float, so use SNORM/UNORM to determine
3196 whether data is signed or not */
3197 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3198 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3201 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3204 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3205 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3207 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3209 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3210 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3212 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3214 switch (desc
->channel
[first_non_void
].type
) {
3215 case UTIL_FORMAT_TYPE_FLOAT
:
3216 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3218 case UTIL_FORMAT_TYPE_SIGNED
:
3219 if (desc
->channel
[first_non_void
].normalized
)
3220 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3221 else if (desc
->channel
[first_non_void
].pure_integer
)
3222 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3224 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3226 case UTIL_FORMAT_TYPE_UNSIGNED
:
3227 if (desc
->channel
[first_non_void
].normalized
)
3228 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3229 else if (desc
->channel
[first_non_void
].pure_integer
)
3230 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3232 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3237 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
3238 if (data_format
== ~0) {
3242 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3243 if (screen
->b
.chip_class
>= GFX9
&&
3244 util_format_has_depth(desc
) &&
3245 num_format
== V_008F14_IMG_NUM_FORMAT_FLOAT
&&
3246 util_get_depth_format_type(base_desc
) != UTIL_FORMAT_TYPE_FLOAT
) {
3247 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3248 data_format
= V_008F14_IMG_DATA_FORMAT_24_8
;
3251 /* S8 with Z32 HTILE needs a special format. */
3252 if (screen
->b
.chip_class
>= GFX9
&&
3253 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3254 tex
->tc_compatible_htile
)
3255 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3258 (res
->target
== PIPE_TEXTURE_CUBE
||
3259 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3260 (screen
->b
.chip_class
<= VI
&&
3261 res
->target
== PIPE_TEXTURE_3D
))) {
3262 /* For the purpose of shader images, treat cube maps and 3D
3263 * textures as 2D arrays. For 3D textures, the address
3264 * calculations for mipmaps are different, so we rely on the
3265 * caller to effectively disable mipmaps.
3267 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3269 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3271 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3274 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3276 depth
= res
->array_size
;
3277 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3278 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3279 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3280 depth
= res
->array_size
;
3281 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3282 depth
= res
->array_size
/ 6;
3285 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3286 S_008F14_NUM_FORMAT_GFX6(num_format
));
3287 state
[2] = (S_008F18_WIDTH(width
- 1) |
3288 S_008F18_HEIGHT(height
- 1) |
3289 S_008F18_PERF_MOD(4));
3290 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3291 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3292 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3293 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3294 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3296 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3297 util_logbase2(res
->nr_samples
) :
3299 S_008F1C_TYPE(type
));
3301 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3305 if (screen
->b
.chip_class
>= GFX9
) {
3306 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3308 /* Depth is the the last accessible layer on Gfx9.
3309 * The hw doesn't need to know the total number of layers.
3311 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3312 state
[4] |= S_008F20_DEPTH(depth
- 1);
3314 state
[4] |= S_008F20_DEPTH(last_layer
);
3316 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3317 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3318 util_logbase2(res
->nr_samples
) :
3319 tex
->resource
.b
.b
.last_level
);
3321 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3322 state
[4] |= S_008F20_DEPTH(depth
- 1);
3323 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3326 if (tex
->dcc_offset
) {
3327 unsigned swap
= r600_translate_colorswap(pipe_format
, false);
3329 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3331 /* The last dword is unused by hw. The shader uses it to clear
3332 * bits in the first dword of sampler state.
3334 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3335 if (first_level
== last_level
)
3336 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3338 state
[7] = 0xffffffff;
3342 /* Initialize the sampler view for FMASK. */
3343 if (tex
->fmask
.size
) {
3344 uint32_t data_format
, num_format
;
3346 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3348 if (screen
->b
.chip_class
>= GFX9
) {
3349 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3350 switch (res
->nr_samples
) {
3352 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3355 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3358 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3361 unreachable("invalid nr_samples");
3364 switch (res
->nr_samples
) {
3366 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3369 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3372 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3375 unreachable("invalid nr_samples");
3377 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3380 fmask_state
[0] = va
>> 8;
3381 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3382 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3383 S_008F14_NUM_FORMAT_GFX6(num_format
);
3384 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3385 S_008F18_HEIGHT(height
- 1);
3386 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3387 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3388 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3389 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3390 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3392 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3396 if (screen
->b
.chip_class
>= GFX9
) {
3397 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3398 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3399 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3400 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3401 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3403 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3404 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3405 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3406 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3412 * Create a sampler view.
3414 * @param ctx context
3415 * @param texture texture
3416 * @param state sampler view template
3417 * @param width0 width0 override (for compressed textures as int)
3418 * @param height0 height0 override (for compressed textures as int)
3419 * @param force_level set the base address to the level (for compressed textures)
3421 struct pipe_sampler_view
*
3422 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3423 struct pipe_resource
*texture
,
3424 const struct pipe_sampler_view
*state
,
3425 unsigned width0
, unsigned height0
,
3426 unsigned force_level
)
3428 struct si_context
*sctx
= (struct si_context
*)ctx
;
3429 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3430 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3431 unsigned base_level
, first_level
, last_level
;
3432 unsigned char state_swizzle
[4];
3433 unsigned height
, depth
, width
;
3434 unsigned last_layer
= state
->u
.tex
.last_layer
;
3435 enum pipe_format pipe_format
;
3436 const struct legacy_surf_level
*surflevel
;
3441 /* initialize base object */
3442 view
->base
= *state
;
3443 view
->base
.texture
= NULL
;
3444 view
->base
.reference
.count
= 1;
3445 view
->base
.context
= ctx
;
3448 pipe_resource_reference(&view
->base
.texture
, texture
);
3450 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3451 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3452 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3453 state
->format
== PIPE_FORMAT_S8_UINT
)
3454 view
->is_stencil_sampler
= true;
3456 /* Buffer resource. */
3457 if (texture
->target
== PIPE_BUFFER
) {
3458 si_make_buffer_descriptor(sctx
->screen
,
3459 (struct r600_resource
*)texture
,
3461 state
->u
.buf
.offset
,
3467 state_swizzle
[0] = state
->swizzle_r
;
3468 state_swizzle
[1] = state
->swizzle_g
;
3469 state_swizzle
[2] = state
->swizzle_b
;
3470 state_swizzle
[3] = state
->swizzle_a
;
3473 first_level
= state
->u
.tex
.first_level
;
3474 last_level
= state
->u
.tex
.last_level
;
3477 depth
= texture
->depth0
;
3479 if (sctx
->b
.chip_class
<= VI
&& force_level
) {
3480 assert(force_level
== first_level
&&
3481 force_level
== last_level
);
3482 base_level
= force_level
;
3485 width
= u_minify(width
, force_level
);
3486 height
= u_minify(height
, force_level
);
3487 depth
= u_minify(depth
, force_level
);
3490 /* This is not needed if state trackers set last_layer correctly. */
3491 if (state
->target
== PIPE_TEXTURE_1D
||
3492 state
->target
== PIPE_TEXTURE_2D
||
3493 state
->target
== PIPE_TEXTURE_RECT
||
3494 state
->target
== PIPE_TEXTURE_CUBE
)
3495 last_layer
= state
->u
.tex
.first_layer
;
3497 /* Texturing with separate depth and stencil. */
3498 pipe_format
= state
->format
;
3500 /* Depth/stencil texturing sometimes needs separate texture. */
3501 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3502 if (!tmp
->flushed_depth_texture
&&
3503 !r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3504 pipe_resource_reference(&view
->base
.texture
, NULL
);
3509 assert(tmp
->flushed_depth_texture
);
3511 /* Override format for the case where the flushed texture
3512 * contains only Z or only S.
3514 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3515 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3517 tmp
= tmp
->flushed_depth_texture
;
3520 surflevel
= tmp
->surface
.u
.legacy
.level
;
3522 if (tmp
->db_compatible
) {
3523 if (!view
->is_stencil_sampler
)
3524 pipe_format
= tmp
->db_render_format
;
3526 switch (pipe_format
) {
3527 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3528 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3530 case PIPE_FORMAT_X8Z24_UNORM
:
3531 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3532 /* Z24 is always stored like this for DB
3535 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3537 case PIPE_FORMAT_X24S8_UINT
:
3538 case PIPE_FORMAT_S8X24_UINT
:
3539 case PIPE_FORMAT_X32_S8X24_UINT
:
3540 pipe_format
= PIPE_FORMAT_S8_UINT
;
3541 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3547 view
->dcc_incompatible
=
3548 vi_dcc_formats_are_incompatible(texture
,
3549 state
->u
.tex
.first_level
,
3552 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3553 state
->target
, pipe_format
, state_swizzle
,
3554 first_level
, last_level
,
3555 state
->u
.tex
.first_layer
, last_layer
,
3556 width
, height
, depth
,
3557 view
->state
, view
->fmask_state
);
3559 view
->base_level_info
= &surflevel
[base_level
];
3560 view
->base_level
= base_level
;
3561 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3565 static struct pipe_sampler_view
*
3566 si_create_sampler_view(struct pipe_context
*ctx
,
3567 struct pipe_resource
*texture
,
3568 const struct pipe_sampler_view
*state
)
3570 return si_create_sampler_view_custom(ctx
, texture
, state
,
3571 texture
? texture
->width0
: 0,
3572 texture
? texture
->height0
: 0, 0);
3575 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3576 struct pipe_sampler_view
*state
)
3578 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3580 pipe_resource_reference(&state
->texture
, NULL
);
3584 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3586 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3587 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3589 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3590 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3593 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
3595 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3596 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3598 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
3599 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
3600 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
3601 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
3602 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
3605 static void *si_create_sampler_state(struct pipe_context
*ctx
,
3606 const struct pipe_sampler_state
*state
)
3608 struct si_context
*sctx
= (struct si_context
*)ctx
;
3609 struct r600_common_screen
*rscreen
= sctx
->b
.screen
;
3610 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
3611 unsigned border_color_type
, border_color_index
= 0;
3612 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
3613 : state
->max_anisotropy
;
3614 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
3620 if (!sampler_state_needs_border_color(state
))
3621 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3622 else if (state
->border_color
.f
[0] == 0 &&
3623 state
->border_color
.f
[1] == 0 &&
3624 state
->border_color
.f
[2] == 0 &&
3625 state
->border_color
.f
[3] == 0)
3626 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3627 else if (state
->border_color
.f
[0] == 0 &&
3628 state
->border_color
.f
[1] == 0 &&
3629 state
->border_color
.f
[2] == 0 &&
3630 state
->border_color
.f
[3] == 1)
3631 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3632 else if (state
->border_color
.f
[0] == 1 &&
3633 state
->border_color
.f
[1] == 1 &&
3634 state
->border_color
.f
[2] == 1 &&
3635 state
->border_color
.f
[3] == 1)
3636 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3640 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
3642 /* Check if the border has been uploaded already. */
3643 for (i
= 0; i
< sctx
->border_color_count
; i
++)
3644 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
3645 sizeof(state
->border_color
)) == 0)
3648 if (i
>= SI_MAX_BORDER_COLORS
) {
3649 /* Getting 4096 unique border colors is very unlikely. */
3650 fprintf(stderr
, "radeonsi: The border color table is full. "
3651 "Any new border colors will be just black. "
3652 "Please file a bug.\n");
3653 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3655 if (i
== sctx
->border_color_count
) {
3656 /* Upload a new border color. */
3657 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
3658 sizeof(state
->border_color
));
3659 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
3660 &state
->border_color
,
3661 sizeof(state
->border_color
));
3662 sctx
->border_color_count
++;
3665 border_color_index
= i
;
3670 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
3672 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
3673 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
3674 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
3675 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3676 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
3677 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
3678 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3679 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3680 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
3681 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
3682 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
3683 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
3684 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3685 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
3686 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
3687 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
3688 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
3689 S_008F38_MIP_POINT_PRECLAMP(1) |
3690 S_008F38_DISABLE_LSB_CEIL(sctx
->b
.chip_class
<= VI
) |
3691 S_008F38_FILTER_PREC_FIX(1) |
3692 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
3693 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
3694 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
3698 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
3700 struct si_context
*sctx
= (struct si_context
*)ctx
;
3702 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
3705 sctx
->sample_mask
.sample_mask
= sample_mask
;
3706 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
3709 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
3711 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3712 unsigned mask
= sctx
->sample_mask
.sample_mask
;
3714 /* Needed for line and polygon smoothing as well as for the Polaris
3715 * small primitive filter. We expect the state tracker to take care of
3718 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
3719 (mask
& 1 && sctx
->blitter
->running
));
3721 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3722 radeon_emit(cs
, mask
| (mask
<< 16));
3723 radeon_emit(cs
, mask
| (mask
<< 16));
3726 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3729 struct si_sampler_state
*s
= state
;
3731 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
3738 * Vertex elements & buffers
3741 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3743 const struct pipe_vertex_element
*elements
)
3745 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
3746 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
3747 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
3750 assert(count
<= SI_MAX_ATTRIBS
);
3755 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
3757 for (i
= 0; i
< count
; ++i
) {
3758 const struct util_format_description
*desc
;
3759 const struct util_format_channel_description
*channel
;
3760 unsigned data_format
, num_format
;
3762 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
3763 unsigned char swizzle
[4];
3765 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
3770 if (elements
[i
].instance_divisor
) {
3771 v
->uses_instance_divisors
= true;
3772 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
3775 if (!used
[vbo_index
]) {
3776 v
->first_vb_use_mask
|= 1 << i
;
3777 used
[vbo_index
] = true;
3780 desc
= util_format_description(elements
[i
].src_format
);
3781 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3782 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3783 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3784 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
3785 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
3787 v
->format_size
[i
] = desc
->block
.bits
/ 8;
3788 v
->src_offset
[i
] = elements
[i
].src_offset
;
3789 v
->vertex_buffer_index
[i
] = vbo_index
;
3791 /* The hardware always treats the 2-bit alpha channel as
3792 * unsigned, so a shader workaround is needed. The affected
3793 * chips are VI and older except Stoney (GFX8.1).
3795 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
3796 sscreen
->b
.chip_class
<= VI
&&
3797 sscreen
->b
.family
!= CHIP_STONEY
) {
3798 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
3799 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
3800 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
3801 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
3802 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
3803 /* This isn't actually used in OpenGL. */
3804 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
3806 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
3807 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3808 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
3810 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
3811 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
3812 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
3813 if (channel
->normalized
) {
3814 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3815 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
3817 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
3819 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
3821 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
3822 if (channel
->normalized
) {
3823 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3824 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
3826 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
3828 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
3831 } else if (channel
&& channel
->size
== 64 &&
3832 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
3833 switch (desc
->nr_channels
) {
3836 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
3837 swizzle
[0] = PIPE_SWIZZLE_X
;
3838 swizzle
[1] = PIPE_SWIZZLE_Y
;
3839 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
3840 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
3843 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
3844 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
3845 swizzle
[1] = PIPE_SWIZZLE_Y
;
3846 swizzle
[2] = PIPE_SWIZZLE_0
;
3847 swizzle
[3] = PIPE_SWIZZLE_0
;
3850 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
3851 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
3852 swizzle
[1] = PIPE_SWIZZLE_Y
;
3853 swizzle
[2] = PIPE_SWIZZLE_Z
;
3854 swizzle
[3] = PIPE_SWIZZLE_W
;
3859 } else if (channel
&& desc
->nr_channels
== 3) {
3860 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
3862 if (channel
->size
== 8) {
3863 if (channel
->pure_integer
)
3864 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
3866 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
3867 } else if (channel
->size
== 16) {
3868 if (channel
->pure_integer
)
3869 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
3871 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
3875 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3876 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3877 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3878 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3879 S_008F0C_NUM_FORMAT(num_format
) |
3880 S_008F0C_DATA_FORMAT(data_format
);
3885 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3887 struct si_context
*sctx
= (struct si_context
*)ctx
;
3888 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
3889 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
3891 sctx
->vertex_elements
= v
;
3892 sctx
->vertex_buffers_dirty
= true;
3896 old
->count
!= v
->count
||
3897 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
3898 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
3899 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
3900 sctx
->do_update_shaders
= true;
3903 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3905 struct si_context
*sctx
= (struct si_context
*)ctx
;
3907 if (sctx
->vertex_elements
== state
)
3908 sctx
->vertex_elements
= NULL
;
3912 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
3913 unsigned start_slot
, unsigned count
,
3914 const struct pipe_vertex_buffer
*buffers
)
3916 struct si_context
*sctx
= (struct si_context
*)ctx
;
3917 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
3920 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
3923 for (i
= 0; i
< count
; i
++) {
3924 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
3925 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
3926 struct pipe_resource
*buf
= src
->buffer
.resource
;
3928 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
3929 dsti
->buffer_offset
= src
->buffer_offset
;
3930 dsti
->stride
= src
->stride
;
3931 r600_context_add_resource_size(ctx
, buf
);
3933 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3936 for (i
= 0; i
< count
; i
++) {
3937 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
3940 sctx
->vertex_buffers_dirty
= true;
3947 static void si_set_tess_state(struct pipe_context
*ctx
,
3948 const float default_outer_level
[4],
3949 const float default_inner_level
[2])
3951 struct si_context
*sctx
= (struct si_context
*)ctx
;
3952 struct pipe_constant_buffer cb
;
3955 memcpy(array
, default_outer_level
, sizeof(float) * 4);
3956 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
3959 cb
.user_buffer
= NULL
;
3960 cb
.buffer_size
= sizeof(array
);
3962 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
3963 (void*)array
, sizeof(array
),
3966 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
3967 pipe_resource_reference(&cb
.buffer
, NULL
);
3970 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
3972 struct si_context
*sctx
= (struct si_context
*)ctx
;
3974 /* Multisample surfaces are flushed in si_decompress_textures. */
3975 if (sctx
->framebuffer
.nr_samples
<= 1) {
3976 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
3977 SI_CONTEXT_INV_GLOBAL_L2
|
3978 SI_CONTEXT_FLUSH_AND_INV_CB
;
3980 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
3983 /* This only ensures coherency for shader image/buffer stores. */
3984 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
3986 struct si_context
*sctx
= (struct si_context
*)ctx
;
3988 /* Subsequent commands must wait for all shader invocations to
3990 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
3991 SI_CONTEXT_CS_PARTIAL_FLUSH
;
3993 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
3994 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
3995 SI_CONTEXT_INV_VMEM_L1
;
3997 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
3998 PIPE_BARRIER_SHADER_BUFFER
|
3999 PIPE_BARRIER_TEXTURE
|
4000 PIPE_BARRIER_IMAGE
|
4001 PIPE_BARRIER_STREAMOUT_BUFFER
|
4002 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4003 /* As far as I can tell, L1 contents are written back to L2
4004 * automatically at end of shader, but the contents of other
4005 * L1 caches might still be stale. */
4006 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
4009 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4010 /* Indices are read through TC L2 since VI.
4013 if (sctx
->screen
->b
.chip_class
<= CIK
)
4014 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4017 /* MSAA color, any depth and any stencil are flushed in
4018 * si_decompress_textures when needed.
4020 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4021 sctx
->framebuffer
.nr_samples
<= 1) {
4022 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
4023 SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4026 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4027 if (sctx
->screen
->b
.chip_class
<= VI
&&
4028 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4029 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4032 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4034 struct pipe_blend_state blend
;
4036 memset(&blend
, 0, sizeof(blend
));
4037 blend
.independent_blend_enable
= true;
4038 blend
.rt
[0].colormask
= 0xf;
4039 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
4042 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
4043 bool include_draw_vbo
)
4045 si_need_cs_space((struct si_context
*)ctx
);
4048 static void si_init_config(struct si_context
*sctx
);
4050 void si_init_state_functions(struct si_context
*sctx
)
4052 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
4053 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
4054 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
4055 si_init_external_atom(sctx
, &sctx
->b
.scissors
.atom
, &sctx
->atoms
.s
.scissors
);
4056 si_init_external_atom(sctx
, &sctx
->b
.viewports
.atom
, &sctx
->atoms
.s
.viewports
);
4058 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
4059 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
4060 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
4061 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
4062 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
4063 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
4064 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
4065 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
4066 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
4067 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
4069 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
4070 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
4071 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
4072 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
4074 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
4075 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
4076 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
4078 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4079 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4080 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4082 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4083 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4084 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4085 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4086 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4088 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
4089 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
4091 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
4092 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
4094 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
4095 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
4097 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
4098 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
4100 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
4102 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
4103 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4104 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4105 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
4107 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
4108 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
4109 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
4110 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
4112 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
4113 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
4114 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
4115 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
4117 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
4119 si_init_config(sctx
);
4122 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen
*rscreen
)
4124 return (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
4127 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
4128 struct r600_texture
*rtex
,
4129 struct radeon_bo_metadata
*md
)
4131 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
4132 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
4133 static const unsigned char swizzle
[] = {
4139 uint32_t desc
[8], i
;
4140 bool is_array
= util_resource_is_array_texture(res
);
4142 /* DRM 2.x.x doesn't support this. */
4143 if (rscreen
->info
.drm_major
!= 3)
4146 assert(rtex
->dcc_separate_buffer
== NULL
);
4147 assert(rtex
->fmask
.size
== 0);
4149 /* Metadata image format format version 1:
4150 * [0] = 1 (metadata format identifier)
4151 * [1] = (VENDOR_ID << 16) | PCI_ID
4152 * [2:9] = image descriptor for the whole resource
4153 * [2] is always 0, because the base address is cleared
4154 * [9] is the DCC offset bits [39:8] from the beginning of
4156 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4159 md
->metadata
[0] = 1; /* metadata image format version 1 */
4161 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4162 md
->metadata
[1] = si_get_bo_metadata_word1(rscreen
);
4164 si_make_texture_descriptor(sscreen
, rtex
, true,
4165 res
->target
, res
->format
,
4166 swizzle
, 0, res
->last_level
, 0,
4167 is_array
? res
->array_size
- 1 : 0,
4168 res
->width0
, res
->height0
, res
->depth0
,
4171 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
4172 0, 0, rtex
->surface
.blk_w
, false, desc
);
4174 /* Clear the base address and set the relative DCC offset. */
4176 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
4177 desc
[7] = rtex
->dcc_offset
>> 8;
4179 /* Dwords [2:9] contain the image descriptor. */
4180 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
4181 md
->size_metadata
= 10 * 4;
4183 /* Dwords [10:..] contain the mipmap level offsets. */
4184 if (rscreen
->chip_class
<= VI
) {
4185 for (i
= 0; i
<= res
->last_level
; i
++)
4186 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
4188 md
->size_metadata
+= (1 + res
->last_level
) * 4;
4192 static void si_apply_opaque_metadata(struct r600_common_screen
*rscreen
,
4193 struct r600_texture
*rtex
,
4194 struct radeon_bo_metadata
*md
)
4196 uint32_t *desc
= &md
->metadata
[2];
4198 if (rscreen
->chip_class
< VI
)
4201 /* Return if DCC is enabled. The texture should be set up with it
4204 if (md
->size_metadata
>= 11 * 4 &&
4205 md
->metadata
[0] != 0 &&
4206 md
->metadata
[1] == si_get_bo_metadata_word1(rscreen
) &&
4207 G_008F28_COMPRESSION_EN(desc
[6])) {
4208 assert(rtex
->dcc_offset
== ((uint64_t)desc
[7] << 8));
4212 /* Disable DCC. These are always set by texture_from_handle and must
4215 rtex
->dcc_offset
= 0;
4218 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4220 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
4221 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
4222 sscreen
->b
.apply_opaque_metadata
= si_apply_opaque_metadata
;
4226 si_write_harvested_raster_configs(struct si_context
*sctx
,
4227 struct si_pm4_state
*pm4
,
4228 unsigned raster_config
,
4229 unsigned raster_config_1
)
4231 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
4232 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
4233 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4234 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4235 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4236 unsigned rb_per_se
= num_rb
/ num_se
;
4237 unsigned se_mask
[4];
4240 se_mask
[0] = ((1 << rb_per_se
) - 1);
4241 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4242 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4243 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4245 se_mask
[0] &= rb_mask
;
4246 se_mask
[1] &= rb_mask
;
4247 se_mask
[2] &= rb_mask
;
4248 se_mask
[3] &= rb_mask
;
4250 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4251 assert(sh_per_se
== 1 || sh_per_se
== 2);
4252 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4254 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4255 * fields are for, so I'm leaving them as their default
4258 for (se
= 0; se
< num_se
; se
++) {
4259 unsigned raster_config_se
= raster_config
;
4260 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4261 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4262 int idx
= (se
/ 2) * 2;
4264 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4265 raster_config_se
&= C_028350_SE_MAP
;
4267 if (!se_mask
[idx
]) {
4269 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4272 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4276 pkr0_mask
&= rb_mask
;
4277 pkr1_mask
&= rb_mask
;
4278 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4279 raster_config_se
&= C_028350_PKR_MAP
;
4283 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4286 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4290 if (rb_per_se
>= 2) {
4291 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4292 unsigned rb1_mask
= rb0_mask
<< 1;
4294 rb0_mask
&= rb_mask
;
4295 rb1_mask
&= rb_mask
;
4296 if (!rb0_mask
|| !rb1_mask
) {
4297 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4301 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4304 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4308 if (rb_per_se
> 2) {
4309 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4310 rb1_mask
= rb0_mask
<< 1;
4311 rb0_mask
&= rb_mask
;
4312 rb1_mask
&= rb_mask
;
4313 if (!rb0_mask
|| !rb1_mask
) {
4314 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4318 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4321 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4327 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4328 if (sctx
->b
.chip_class
< CIK
)
4329 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
4330 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
4331 INSTANCE_BROADCAST_WRITES
);
4333 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
4334 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
4335 S_030800_INSTANCE_BROADCAST_WRITES(1));
4336 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4339 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4340 if (sctx
->b
.chip_class
< CIK
)
4341 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
4342 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
4343 INSTANCE_BROADCAST_WRITES
);
4345 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
4346 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4347 S_030800_INSTANCE_BROADCAST_WRITES(1));
4349 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4350 (!se_mask
[2] && !se_mask
[3]))) {
4351 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4353 if (!se_mask
[0] && !se_mask
[1]) {
4355 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4358 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4362 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4366 static void si_init_config(struct si_context
*sctx
)
4368 struct si_screen
*sscreen
= sctx
->screen
;
4369 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4370 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4371 unsigned raster_config
, raster_config_1
;
4372 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4373 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4378 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4379 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4380 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4381 si_pm4_cmd_end(pm4
, false);
4383 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4384 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4386 /* FIXME calculate these values somehow ??? */
4387 if (sctx
->b
.chip_class
<= VI
) {
4388 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4389 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4391 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4393 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4394 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4396 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4397 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4398 if (sctx
->b
.chip_class
>= GFX9
)
4399 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0);
4400 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4401 if (sctx
->b
.chip_class
< CIK
)
4402 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4403 S_008A14_CLIP_VTX_REORDER_ENA(1));
4405 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4406 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4408 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4410 switch (sctx
->screen
->b
.family
) {
4413 raster_config
= 0x2a00126a;
4414 raster_config_1
= 0x00000000;
4417 raster_config
= 0x0000124a;
4418 raster_config_1
= 0x00000000;
4421 raster_config
= 0x00000082;
4422 raster_config_1
= 0x00000000;
4425 raster_config
= 0x00000000;
4426 raster_config_1
= 0x00000000;
4429 raster_config
= 0x16000012;
4430 raster_config_1
= 0x00000000;
4433 raster_config
= 0x3a00161a;
4434 raster_config_1
= 0x0000002e;
4437 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4438 /* old kernels with old tiling config */
4439 raster_config
= 0x16000012;
4440 raster_config_1
= 0x0000002a;
4442 raster_config
= 0x3a00161a;
4443 raster_config_1
= 0x0000002e;
4446 case CHIP_POLARIS10
:
4447 raster_config
= 0x16000012;
4448 raster_config_1
= 0x0000002a;
4450 case CHIP_POLARIS11
:
4451 case CHIP_POLARIS12
:
4452 raster_config
= 0x16000012;
4453 raster_config_1
= 0x00000000;
4456 raster_config
= 0x16000012;
4457 raster_config_1
= 0x0000002a;
4461 raster_config
= 0x00000000;
4463 raster_config
= 0x00000002;
4464 raster_config_1
= 0x00000000;
4467 raster_config
= 0x00000002;
4468 raster_config_1
= 0x00000000;
4471 /* KV should be 0x00000002, but that causes problems with radeon */
4472 raster_config
= 0x00000000; /* 0x00000002 */
4473 raster_config_1
= 0x00000000;
4478 raster_config
= 0x00000000;
4479 raster_config_1
= 0x00000000;
4482 if (sctx
->b
.chip_class
<= VI
) {
4484 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4485 raster_config
= 0x00000000;
4486 raster_config_1
= 0x00000000;
4491 if (sctx
->b
.chip_class
<= VI
) {
4492 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4493 /* Always use the default config when all backends are enabled
4494 * (or when we failed to determine the enabled backends).
4496 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4498 if (sctx
->b
.chip_class
>= CIK
)
4499 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4502 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4506 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4507 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4508 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4509 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4510 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4511 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4512 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4514 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4515 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4516 S_028230_ER_TRI(0xA) |
4517 S_028230_ER_POINT(0xA) |
4518 S_028230_ER_RECT(0xA) |
4519 /* Required by DX10_DIAMOND_TEST_ENA: */
4520 S_028230_ER_LINE_LR(0x1A) |
4521 S_028230_ER_LINE_RL(0x26) |
4522 S_028230_ER_LINE_TB(0xA) |
4523 S_028230_ER_LINE_BT(0xA));
4524 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4525 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4526 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4527 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4528 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4529 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4530 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4532 if (sctx
->b
.chip_class
>= GFX9
) {
4533 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4534 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4535 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4537 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4538 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4539 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4542 if (sctx
->b
.chip_class
>= CIK
) {
4543 if (sctx
->b
.chip_class
>= GFX9
) {
4544 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_CU_EN(0xffff));
4546 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
4547 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
4548 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
4550 /* If this is 0, Bonaire can hang even if GS isn't being used.
4551 * Other chips are unaffected. These are suboptimal values,
4552 * but we don't use on-chip GS.
4554 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4555 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4556 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4558 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
4560 if (sscreen
->b
.info
.num_good_compute_units
/
4561 (sscreen
->b
.info
.max_se
* sscreen
->b
.info
.max_sh_per_se
) <= 4) {
4562 /* Too few available compute units per SH. Disallowing
4563 * VS to run on CU0 could hurt us more than late VS
4564 * allocation would help.
4566 * LATE_ALLOC_VS = 2 is the highest safe number.
4568 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
4569 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
4571 /* Set LATE_ALLOC_VS == 31. It should be less than
4572 * the number of scratch waves. Limitations:
4573 * - VS can't execute on CU0.
4574 * - If HS writes outputs to LDS, LS can't execute on CU0.
4576 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
4577 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
4580 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
4583 if (sctx
->b
.chip_class
>= VI
) {
4584 unsigned vgt_tess_distribution
;
4586 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
4587 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4588 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4589 if (sctx
->b
.family
< CHIP_POLARIS10
)
4590 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
4591 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
4593 vgt_tess_distribution
=
4594 S_028B50_ACCUM_ISOLINE(32) |
4595 S_028B50_ACCUM_TRI(11) |
4596 S_028B50_ACCUM_QUAD(11) |
4597 S_028B50_DONUT_SPLIT(16);
4599 /* Testing with Unigine Heaven extreme tesselation yielded best results
4600 * with TRAP_SPLIT = 3.
4602 if (sctx
->b
.family
== CHIP_FIJI
||
4603 sctx
->b
.family
>= CHIP_POLARIS10
)
4604 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
4606 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
4608 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
4609 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
4612 if (sctx
->screen
->b
.has_rbplus
)
4613 si_pm4_set_reg(pm4
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
4615 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4616 if (sctx
->b
.chip_class
>= CIK
)
4617 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
4618 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4619 RADEON_PRIO_BORDER_COLORS
);
4621 if (sctx
->b
.chip_class
>= GFX9
) {
4622 unsigned num_se
= sscreen
->b
.info
.max_se
;
4623 unsigned pc_lines
= 0;
4625 switch (sctx
->b
.family
) {
4636 si_pm4_set_reg(pm4
, R_028060_DB_DFSM_CONTROL
,
4637 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
));
4638 si_pm4_set_reg(pm4
, R_028064_DB_RENDER_FILTER
, 0);
4639 /* TODO: We can use this to disable RBs for rendering to GART: */
4640 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
, 0);
4641 si_pm4_set_reg(pm4
, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL
, 0);
4642 /* TODO: Enable the binner: */
4643 si_pm4_set_reg(pm4
, R_028C44_PA_SC_BINNER_CNTL_0
,
4644 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
4645 S_028C44_DISABLE_START_OF_PRIM(1));
4646 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
4647 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
4648 S_028C48_MAX_PRIM_PER_BATCH(1023));
4649 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
4650 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4651 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
4654 si_pm4_upload_indirect_buffer(sctx
, pm4
);
4655 sctx
->init_config
= pm4
;