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radeonsi: use guard band clipping
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.info.r600_num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.num_render_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case UTIL_FORMAT_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case UTIL_FORMAT_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case UTIL_FORMAT_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case UTIL_FORMAT_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case UTIL_FORMAT_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
243 * is that:
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
248 *
249 * Another reason is to avoid a hang with dual source blending.
250 */
251 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
252 {
253 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
254 struct si_state_blend *blend = sctx->queued.named.blend;
255 uint32_t cb_target_mask = 0, i;
256
257 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
258 if (sctx->framebuffer.state.cbufs[i])
259 cb_target_mask |= 0xf << (4*i);
260
261 if (blend)
262 cb_target_mask &= blend->cb_target_mask;
263
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
267 *
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
269 */
270 if (blend && blend->dual_src_blend &&
271 sctx->ps_shader.cso &&
272 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
273 cb_target_mask = 0;
274
275 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
276
277 /* STONEY-specific register settings. */
278 if (sctx->b.family == CHIP_STONEY) {
279 unsigned spi_shader_col_format =
280 sctx->ps_shader.cso ?
281 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
282 unsigned sx_ps_downconvert = 0;
283 unsigned sx_blend_opt_epsilon = 0;
284 unsigned sx_blend_opt_control = 0;
285
286 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
287 struct r600_surface *surf =
288 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
289 unsigned format, swap, spi_format, colormask;
290 bool has_alpha, has_rgb;
291
292 if (!surf)
293 continue;
294
295 format = G_028C70_FORMAT(surf->cb_color_info);
296 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
297 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
298 colormask = (cb_target_mask >> (i * 4)) & 0xf;
299
300 /* Set if RGB and A are present. */
301 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
302
303 if (format == V_028C70_COLOR_8 ||
304 format == V_028C70_COLOR_16 ||
305 format == V_028C70_COLOR_32)
306 has_rgb = !has_alpha;
307 else
308 has_rgb = true;
309
310 /* Check the colormask and export format. */
311 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
312 has_rgb = false;
313 if (!(colormask & PIPE_MASK_A))
314 has_alpha = false;
315
316 if (spi_format == V_028714_SPI_SHADER_ZERO) {
317 has_rgb = false;
318 has_alpha = false;
319 }
320
321 /* Disable value checking for disabled channels. */
322 if (!has_rgb)
323 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
324 if (!has_alpha)
325 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
326
327 /* Enable down-conversion for 32bpp and smaller formats. */
328 switch (format) {
329 case V_028C70_COLOR_8:
330 case V_028C70_COLOR_8_8:
331 case V_028C70_COLOR_8_8_8_8:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
335 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
336 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
337 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
338 }
339 break;
340
341 case V_028C70_COLOR_5_6_5:
342 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
343 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
344 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
345 }
346 break;
347
348 case V_028C70_COLOR_1_5_5_5:
349 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
350 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
351 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
352 }
353 break;
354
355 case V_028C70_COLOR_4_4_4_4:
356 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
357 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
358 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
359 }
360 break;
361
362 case V_028C70_COLOR_32:
363 if (swap == V_0280A0_SWAP_STD &&
364 spi_format == V_028714_SPI_SHADER_32_R)
365 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
366 else if (swap == V_0280A0_SWAP_ALT_REV &&
367 spi_format == V_028714_SPI_SHADER_32_AR)
368 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
369 break;
370
371 case V_028C70_COLOR_16:
372 case V_028C70_COLOR_16_16:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
377 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
378 if (swap == V_0280A0_SWAP_STD ||
379 swap == V_0280A0_SWAP_STD_REV)
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
381 else
382 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
383 }
384 break;
385
386 case V_028C70_COLOR_10_11_11:
387 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
388 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
389 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
390 }
391 break;
392
393 case V_028C70_COLOR_2_10_10_10:
394 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
395 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
396 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
397 }
398 break;
399 }
400 }
401
402 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
403 sx_ps_downconvert = 0;
404 sx_blend_opt_epsilon = 0;
405 sx_blend_opt_control = 0;
406 }
407
408 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
409 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
412 }
413 }
414
415 /*
416 * Blender functions
417 */
418
419 static uint32_t si_translate_blend_function(int blend_func)
420 {
421 switch (blend_func) {
422 case PIPE_BLEND_ADD:
423 return V_028780_COMB_DST_PLUS_SRC;
424 case PIPE_BLEND_SUBTRACT:
425 return V_028780_COMB_SRC_MINUS_DST;
426 case PIPE_BLEND_REVERSE_SUBTRACT:
427 return V_028780_COMB_DST_MINUS_SRC;
428 case PIPE_BLEND_MIN:
429 return V_028780_COMB_MIN_DST_SRC;
430 case PIPE_BLEND_MAX:
431 return V_028780_COMB_MAX_DST_SRC;
432 default:
433 R600_ERR("Unknown blend function %d\n", blend_func);
434 assert(0);
435 break;
436 }
437 return 0;
438 }
439
440 static uint32_t si_translate_blend_factor(int blend_fact)
441 {
442 switch (blend_fact) {
443 case PIPE_BLENDFACTOR_ONE:
444 return V_028780_BLEND_ONE;
445 case PIPE_BLENDFACTOR_SRC_COLOR:
446 return V_028780_BLEND_SRC_COLOR;
447 case PIPE_BLENDFACTOR_SRC_ALPHA:
448 return V_028780_BLEND_SRC_ALPHA;
449 case PIPE_BLENDFACTOR_DST_ALPHA:
450 return V_028780_BLEND_DST_ALPHA;
451 case PIPE_BLENDFACTOR_DST_COLOR:
452 return V_028780_BLEND_DST_COLOR;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE;
455 case PIPE_BLENDFACTOR_CONST_COLOR:
456 return V_028780_BLEND_CONSTANT_COLOR;
457 case PIPE_BLENDFACTOR_CONST_ALPHA:
458 return V_028780_BLEND_CONSTANT_ALPHA;
459 case PIPE_BLENDFACTOR_ZERO:
460 return V_028780_BLEND_ZERO;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
473 case PIPE_BLENDFACTOR_SRC1_COLOR:
474 return V_028780_BLEND_SRC1_COLOR;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA:
476 return V_028780_BLEND_SRC1_ALPHA;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
478 return V_028780_BLEND_INV_SRC1_COLOR;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
480 return V_028780_BLEND_INV_SRC1_ALPHA;
481 default:
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
483 assert(0);
484 break;
485 }
486 return 0;
487 }
488
489 static uint32_t si_translate_blend_opt_function(int blend_func)
490 {
491 switch (blend_func) {
492 case PIPE_BLEND_ADD:
493 return V_028760_OPT_COMB_ADD;
494 case PIPE_BLEND_SUBTRACT:
495 return V_028760_OPT_COMB_SUBTRACT;
496 case PIPE_BLEND_REVERSE_SUBTRACT:
497 return V_028760_OPT_COMB_REVSUBTRACT;
498 case PIPE_BLEND_MIN:
499 return V_028760_OPT_COMB_MIN;
500 case PIPE_BLEND_MAX:
501 return V_028760_OPT_COMB_MAX;
502 default:
503 return V_028760_OPT_COMB_BLEND_DISABLED;
504 }
505 }
506
507 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
508 {
509 switch (blend_fact) {
510 case PIPE_BLENDFACTOR_ZERO:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
512 case PIPE_BLENDFACTOR_ONE:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
514 case PIPE_BLENDFACTOR_SRC_COLOR:
515 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
518 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
520 case PIPE_BLENDFACTOR_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
525 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
527 default:
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
529 }
530 }
531
532 /**
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 */
536 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
537 unsigned *dst_factor, unsigned expected_dst,
538 unsigned replacement_src)
539 {
540 if (*src_factor == expected_dst &&
541 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
542 *src_factor = PIPE_BLENDFACTOR_ZERO;
543 *dst_factor = replacement_src;
544
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func == PIPE_BLEND_SUBTRACT)
547 *func = PIPE_BLEND_REVERSE_SUBTRACT;
548 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
549 *func = PIPE_BLEND_SUBTRACT;
550 }
551 }
552
553 static bool si_blend_factor_uses_dst(unsigned factor)
554 {
555 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
556 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
559 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
560 }
561
562 static void *si_create_blend_state_mode(struct pipe_context *ctx,
563 const struct pipe_blend_state *state,
564 unsigned mode)
565 {
566 struct si_context *sctx = (struct si_context*)ctx;
567 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
568 struct si_pm4_state *pm4 = &blend->pm4;
569 uint32_t sx_mrt_blend_opt[8] = {0};
570 uint32_t color_control = 0;
571
572 if (!blend)
573 return NULL;
574
575 blend->alpha_to_coverage = state->alpha_to_coverage;
576 blend->alpha_to_one = state->alpha_to_one;
577 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
578
579 if (state->logicop_enable) {
580 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
581 } else {
582 color_control |= S_028808_ROP3(0xcc);
583 }
584
585 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
591
592 if (state->alpha_to_coverage)
593 blend->need_src_alpha_4bit |= 0xf;
594
595 blend->cb_target_mask = 0;
596 for (int i = 0; i < 8; i++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j = state->independent_blend_enable ? i : 0;
599
600 unsigned eqRGB = state->rt[j].rgb_func;
601 unsigned srcRGB = state->rt[j].rgb_src_factor;
602 unsigned dstRGB = state->rt[j].rgb_dst_factor;
603 unsigned eqA = state->rt[j].alpha_func;
604 unsigned srcA = state->rt[j].alpha_src_factor;
605 unsigned dstA = state->rt[j].alpha_dst_factor;
606
607 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
608 unsigned blend_cntl = 0;
609
610 sx_mrt_blend_opt[i] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
613
614 if (!state->rt[j].colormask)
615 continue;
616
617 /* cb_render_state will disable unused ones */
618 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
619
620 if (!state->rt[j].blend_enable) {
621 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 continue;
623 }
624
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
627 *
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
630 */
631 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
632 PIPE_BLENDFACTOR_DST_COLOR,
633 PIPE_BLENDFACTOR_SRC_COLOR);
634 si_blend_remove_dst(&eqA, &srcA, &dstA,
635 PIPE_BLENDFACTOR_DST_COLOR,
636 PIPE_BLENDFACTOR_SRC_COLOR);
637 si_blend_remove_dst(&eqA, &srcA, &dstA,
638 PIPE_BLENDFACTOR_DST_ALPHA,
639 PIPE_BLENDFACTOR_SRC_ALPHA);
640
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
643 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
644 srcA_opt = si_translate_blend_opt_factor(srcA, true);
645 dstA_opt = si_translate_blend_opt_factor(dstA, true);
646
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650 if (si_blend_factor_uses_dst(srcA))
651 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
652
653 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
654 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
656 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
657 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
658
659 /* Set the final value. */
660 sx_mrt_blend_opt[i] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt) |
665 S_028760_ALPHA_DST_OPT(dstA_opt) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
667
668 /* Set blend state. */
669 blend_cntl |= S_028780_ENABLE(1);
670 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
671 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
672 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
673
674 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
675 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
677 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
678 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
679 }
680 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
681
682 blend->blend_enable_4bit |= 0xf << (i * 4);
683
684 /* This is only important for formats without alpha. */
685 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
687 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
689 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
690 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
691 blend->need_src_alpha_4bit |= 0xf << (i * 4);
692 }
693
694 if (blend->cb_target_mask) {
695 color_control |= S_028808_MODE(mode);
696 } else {
697 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
698 }
699
700 if (sctx->b.family == CHIP_STONEY) {
701 for (int i = 0; i < 8; i++)
702 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
703 sx_mrt_blend_opt[i]);
704
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend->dual_src_blend || state->logicop_enable ||
707 mode == V_028808_CB_RESOLVE)
708 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
709 }
710
711 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
712 return blend;
713 }
714
715 static void *si_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
719 }
720
721 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
725 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
726 }
727
728 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
729 {
730 struct si_context *sctx = (struct si_context *)ctx;
731 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
732 }
733
734 static void si_set_blend_color(struct pipe_context *ctx,
735 const struct pipe_blend_color *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738
739 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->blend_color.state = *state;
743 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
744 }
745
746 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
747 {
748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
749
750 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
751 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
752 }
753
754 /*
755 * Clipping, scissors and viewport
756 */
757
758 static void si_set_clip_state(struct pipe_context *ctx,
759 const struct pipe_clip_state *state)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_constant_buffer cb;
763
764 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
765 return;
766
767 sctx->clip_state.state = *state;
768 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
769
770 cb.buffer = NULL;
771 cb.user_buffer = state->ucp;
772 cb.buffer_offset = 0;
773 cb.buffer_size = 4*4*8;
774 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
775 pipe_resource_reference(&cb.buffer, NULL);
776 }
777
778 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
779 {
780 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
781
782 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
783 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
784 }
785
786 #define SIX_BITS 0x3F
787
788 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
789 {
790 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
791 struct tgsi_shader_info *info = si_get_vs_info(sctx);
792 unsigned window_space =
793 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
794 unsigned clipdist_mask =
795 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
796
797 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
798 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
799 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
800 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
801 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
802 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
803 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
804 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
805 info->writes_edgeflag ||
806 info->writes_layer ||
807 info->writes_viewport_index) |
808 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
809 (sctx->queued.named.rasterizer->clip_plane_enable &
810 clipdist_mask));
811 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
812 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
813 (clipdist_mask ? 0 :
814 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
815 S_028810_CLIP_DISABLE(window_space));
816
817 /* reuse needs to be set off if we write oViewport */
818 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
819 S_028AB4_REUSE_OFF(info->writes_viewport_index));
820 }
821
822 static void si_set_scissor_states(struct pipe_context *ctx,
823 unsigned start_slot,
824 unsigned num_scissors,
825 const struct pipe_scissor_state *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828 int i;
829
830 for (i = 0; i < num_scissors; i++)
831 sctx->scissors.states[start_slot + i] = state[i];
832
833 if (!sctx->queued.named.rasterizer ||
834 !sctx->queued.named.rasterizer->scissor_enable)
835 return;
836
837 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
838 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
839 }
840
841 static void si_get_scissor_from_viewport(const struct pipe_viewport_state *vp,
842 struct si_signed_scissor *scissor)
843 {
844 int tmp;
845
846 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
847 scissor->minx = -vp->scale[0] + vp->translate[0];
848 scissor->miny = -vp->scale[1] + vp->translate[1];
849 scissor->maxx = vp->scale[0] + vp->translate[0];
850 scissor->maxy = vp->scale[1] + vp->translate[1];
851
852 /* r600_draw_rectangle sets this. Disable the scissor. */
853 if (scissor->minx == -1 && scissor->miny == -1 &&
854 scissor->maxx == 1 && scissor->maxy == 1) {
855 scissor->minx = scissor->miny = 0;
856 scissor->maxx = scissor->maxy = 16384;
857 }
858
859 /* Handle inverted viewports. */
860 if (scissor->minx > scissor->maxx) {
861 tmp = scissor->minx;
862 scissor->minx = scissor->maxx;
863 scissor->maxx = tmp;
864 }
865 if (scissor->miny > scissor->maxy) {
866 tmp = scissor->miny;
867 scissor->miny = scissor->maxy;
868 scissor->maxy = tmp;
869 }
870 }
871
872 static void si_clamp_scissor(struct pipe_scissor_state *out,
873 struct si_signed_scissor *scissor)
874 {
875 out->minx = CLAMP(scissor->minx, 0, 16384);
876 out->miny = CLAMP(scissor->miny, 0, 16384);
877 out->maxx = CLAMP(scissor->maxx, 0, 16384);
878 out->maxy = CLAMP(scissor->maxy, 0, 16384);
879 }
880
881 static void si_clip_scissor(struct pipe_scissor_state *out,
882 struct pipe_scissor_state *clip)
883 {
884 out->minx = MAX2(out->minx, clip->minx);
885 out->miny = MAX2(out->miny, clip->miny);
886 out->maxx = MIN2(out->maxx, clip->maxx);
887 out->maxy = MIN2(out->maxy, clip->maxy);
888 }
889
890 static void si_scissor_make_union(struct si_signed_scissor *out,
891 struct si_signed_scissor *in)
892 {
893 out->minx = MIN2(out->minx, in->minx);
894 out->miny = MIN2(out->miny, in->miny);
895 out->maxx = MAX2(out->maxx, in->maxx);
896 out->maxy = MAX2(out->maxy, in->maxy);
897 }
898
899 static void si_emit_one_scissor(struct radeon_winsys_cs *cs,
900 struct si_signed_scissor *vp_scissor,
901 struct pipe_scissor_state *scissor)
902 {
903 struct pipe_scissor_state final;
904
905 /* Since the guard band disables clipping, we have to clip per-pixel
906 * using a scissor.
907 */
908 si_clamp_scissor(&final, vp_scissor);
909
910 if (scissor)
911 si_clip_scissor(&final, scissor);
912
913 radeon_emit(cs, S_028250_TL_X(final.minx) |
914 S_028250_TL_Y(final.miny) |
915 S_028250_WINDOW_OFFSET_DISABLE(1));
916 radeon_emit(cs, S_028254_BR_X(final.maxx) |
917 S_028254_BR_Y(final.maxy));
918 }
919
920 /* the range is [-MAX, MAX] */
921 #define SI_MAX_VIEWPORT_RANGE 32768
922
923 static void si_emit_guardband(struct si_context *sctx,
924 struct si_signed_scissor *vp_as_scissor)
925 {
926 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
927 struct pipe_viewport_state vp;
928 float left, top, right, bottom, max_range, guardband_x, guardband_y;
929
930 /* Reconstruct the viewport transformation from the scissor. */
931 vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
932 vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
933 vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
934 vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
935
936 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
937 if (vp_as_scissor->minx == vp_as_scissor->maxx)
938 vp.scale[0] = 0.5;
939 if (vp_as_scissor->miny == vp_as_scissor->maxy)
940 vp.scale[1] = 0.5;
941
942 /* Find the biggest guard band that is inside the supported viewport
943 * range. The guard band is specified as a horizontal and vertical
944 * distance from (0,0) in clip space.
945 *
946 * This is done by applying the inverse viewport transformation
947 * on the viewport limits to get those limits in clip space.
948 *
949 * Use a limit one pixel smaller to allow for some precision error.
950 */
951 max_range = SI_MAX_VIEWPORT_RANGE - 1;
952 left = (-max_range - vp.translate[0]) / vp.scale[0];
953 right = ( max_range - vp.translate[0]) / vp.scale[0];
954 top = (-max_range - vp.translate[1]) / vp.scale[1];
955 bottom = ( max_range - vp.translate[1]) / vp.scale[1];
956
957 assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
958
959 guardband_x = MIN2(-left, right);
960 guardband_y = MIN2(-top, bottom);
961
962 /* If any of the GB registers is updated, all of them must be updated. */
963 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
964 radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
965 radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
966 radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
967 radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
968 }
969
970 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
971 {
972 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
973 struct pipe_scissor_state *states = sctx->scissors.states;
974 unsigned mask = sctx->scissors.dirty_mask;
975 bool scissor_enable = sctx->queued.named.rasterizer->scissor_enable;
976 struct si_signed_scissor max_vp_scissor;
977 int i;
978
979 /* The simple case: Only 1 viewport is active. */
980 if (!si_get_vs_info(sctx)->writes_viewport_index) {
981 struct si_signed_scissor *vp = &sctx->viewports.as_scissor[0];
982
983 if (!(mask & 1))
984 return;
985
986 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
987 si_emit_one_scissor(cs, vp, scissor_enable ? &states[0] : NULL);
988 si_emit_guardband(sctx, vp);
989 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
990 return;
991 }
992
993 /* Shaders can draw to any viewport. Make a union of all viewports. */
994 max_vp_scissor = sctx->viewports.as_scissor[0];
995 for (i = 1; i < SI_MAX_VIEWPORTS; i++)
996 si_scissor_make_union(&max_vp_scissor,
997 &sctx->viewports.as_scissor[i]);
998
999 while (mask) {
1000 int start, count, i;
1001
1002 u_bit_scan_consecutive_range(&mask, &start, &count);
1003
1004 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
1005 start * 4 * 2, count * 2);
1006 for (i = start; i < start+count; i++) {
1007 si_emit_one_scissor(cs, &sctx->viewports.as_scissor[i],
1008 scissor_enable ? &states[i] : NULL);
1009 }
1010 }
1011 si_emit_guardband(sctx, &max_vp_scissor);
1012 sctx->scissors.dirty_mask = 0;
1013 }
1014
1015 static void si_set_viewport_states(struct pipe_context *ctx,
1016 unsigned start_slot,
1017 unsigned num_viewports,
1018 const struct pipe_viewport_state *state)
1019 {
1020 struct si_context *sctx = (struct si_context *)ctx;
1021 int i;
1022
1023 for (i = 0; i < num_viewports; i++) {
1024 unsigned index = start_slot + i;
1025
1026 sctx->viewports.states[index] = state[i];
1027 si_get_scissor_from_viewport(&state[i],
1028 &sctx->viewports.as_scissor[index]);
1029 }
1030
1031 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
1032 sctx->scissors.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
1033 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1034 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1035 }
1036
1037 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
1038 {
1039 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1040 struct pipe_viewport_state *states = sctx->viewports.states;
1041 unsigned mask = sctx->viewports.dirty_mask;
1042
1043 /* The simple case: Only 1 viewport is active. */
1044 if (!si_get_vs_info(sctx)->writes_viewport_index) {
1045 if (!(mask & 1))
1046 return;
1047
1048 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
1049 radeon_emit(cs, fui(states[0].scale[0]));
1050 radeon_emit(cs, fui(states[0].translate[0]));
1051 radeon_emit(cs, fui(states[0].scale[1]));
1052 radeon_emit(cs, fui(states[0].translate[1]));
1053 radeon_emit(cs, fui(states[0].scale[2]));
1054 radeon_emit(cs, fui(states[0].translate[2]));
1055 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
1056 return;
1057 }
1058
1059 while (mask) {
1060 int start, count, i;
1061
1062 u_bit_scan_consecutive_range(&mask, &start, &count);
1063
1064 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
1065 start * 4 * 6, count * 6);
1066 for (i = start; i < start+count; i++) {
1067 radeon_emit(cs, fui(states[i].scale[0]));
1068 radeon_emit(cs, fui(states[i].translate[0]));
1069 radeon_emit(cs, fui(states[i].scale[1]));
1070 radeon_emit(cs, fui(states[i].translate[1]));
1071 radeon_emit(cs, fui(states[i].scale[2]));
1072 radeon_emit(cs, fui(states[i].translate[2]));
1073 }
1074 }
1075 sctx->viewports.dirty_mask = 0;
1076 }
1077
1078 /*
1079 * inferred state between framebuffer and rasterizer
1080 */
1081 static void si_update_poly_offset_state(struct si_context *sctx)
1082 {
1083 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1084
1085 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
1086 return;
1087
1088 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1089 case PIPE_FORMAT_Z16_UNORM:
1090 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
1091 break;
1092 default: /* 24-bit */
1093 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
1094 break;
1095 case PIPE_FORMAT_Z32_FLOAT:
1096 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1097 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
1098 break;
1099 }
1100 }
1101
1102 /*
1103 * Rasterizer
1104 */
1105
1106 static uint32_t si_translate_fill(uint32_t func)
1107 {
1108 switch(func) {
1109 case PIPE_POLYGON_MODE_FILL:
1110 return V_028814_X_DRAW_TRIANGLES;
1111 case PIPE_POLYGON_MODE_LINE:
1112 return V_028814_X_DRAW_LINES;
1113 case PIPE_POLYGON_MODE_POINT:
1114 return V_028814_X_DRAW_POINTS;
1115 default:
1116 assert(0);
1117 return V_028814_X_DRAW_POINTS;
1118 }
1119 }
1120
1121 static void *si_create_rs_state(struct pipe_context *ctx,
1122 const struct pipe_rasterizer_state *state)
1123 {
1124 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
1125 struct si_pm4_state *pm4 = &rs->pm4;
1126 unsigned tmp, i;
1127 float psize_min, psize_max;
1128
1129 if (!rs) {
1130 return NULL;
1131 }
1132
1133 rs->scissor_enable = state->scissor;
1134 rs->two_side = state->light_twoside;
1135 rs->multisample_enable = state->multisample;
1136 rs->force_persample_interp = state->force_persample_interp;
1137 rs->clip_plane_enable = state->clip_plane_enable;
1138 rs->line_stipple_enable = state->line_stipple_enable;
1139 rs->poly_stipple_enable = state->poly_stipple_enable;
1140 rs->line_smooth = state->line_smooth;
1141 rs->poly_smooth = state->poly_smooth;
1142 rs->uses_poly_offset = state->offset_point || state->offset_line ||
1143 state->offset_tri;
1144 rs->clamp_fragment_color = state->clamp_fragment_color;
1145 rs->flatshade = state->flatshade;
1146 rs->sprite_coord_enable = state->sprite_coord_enable;
1147 rs->rasterizer_discard = state->rasterizer_discard;
1148 rs->pa_sc_line_stipple = state->line_stipple_enable ?
1149 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1150 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1151 rs->pa_cl_clip_cntl =
1152 S_028810_PS_UCP_MODE(3) |
1153 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1154 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1155 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1156 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1157 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1158
1159 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
1160 S_0286D4_FLAT_SHADE_ENA(1) |
1161 S_0286D4_PNT_SPRITE_ENA(1) |
1162 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1163 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1164 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1165 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1166 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1167
1168 /* point size 12.4 fixed point */
1169 tmp = (unsigned)(state->point_size * 8.0);
1170 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1171
1172 if (state->point_size_per_vertex) {
1173 psize_min = util_get_min_point_size(state);
1174 psize_max = 8192;
1175 } else {
1176 /* Force the point size to be as if the vertex output was disabled. */
1177 psize_min = state->point_size;
1178 psize_max = state->point_size;
1179 }
1180 /* Divide by two, because 0.5 = 1 pixel. */
1181 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1182 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
1183 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
1184
1185 tmp = (unsigned)state->line_width * 8;
1186 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
1187 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
1188 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1189 S_028A48_MSAA_ENABLE(state->multisample ||
1190 state->poly_smooth ||
1191 state->line_smooth) |
1192 S_028A48_VPORT_SCISSOR_ENABLE(1));
1193
1194 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
1195 S_028BE4_PIX_CENTER(state->half_pixel_center) |
1196 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
1197
1198 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1199 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1200 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1201 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1202 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1203 S_028814_FACE(!state->front_ccw) |
1204 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1205 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1206 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1207 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
1208 state->fill_back != PIPE_POLYGON_MODE_FILL) |
1209 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1210 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
1211 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
1212 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
1213
1214 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1215 for (i = 0; i < 3; i++) {
1216 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1217 float offset_units = state->offset_units;
1218 float offset_scale = state->offset_scale * 16.0f;
1219
1220 switch (i) {
1221 case 0: /* 16-bit zbuffer */
1222 offset_units *= 4.0f;
1223 break;
1224 case 1: /* 24-bit zbuffer */
1225 offset_units *= 2.0f;
1226 break;
1227 case 2: /* 32-bit zbuffer */
1228 offset_units *= 1.0f;
1229 break;
1230 }
1231
1232 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1233 fui(offset_scale));
1234 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1235 fui(offset_units));
1236 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1237 fui(offset_scale));
1238 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1239 fui(offset_units));
1240 }
1241
1242 return rs;
1243 }
1244
1245 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1246 {
1247 struct si_context *sctx = (struct si_context *)ctx;
1248 struct si_state_rasterizer *old_rs =
1249 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1250 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1251
1252 if (!state)
1253 return;
1254
1255 if (sctx->framebuffer.nr_samples > 1 &&
1256 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1257 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1258
1259 if (!old_rs || old_rs->scissor_enable != rs->scissor_enable) {
1260 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1261 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1262 }
1263
1264 si_pm4_bind_state(sctx, rasterizer, rs);
1265 si_update_poly_offset_state(sctx);
1266
1267 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1268 }
1269
1270 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1271 {
1272 struct si_context *sctx = (struct si_context *)ctx;
1273
1274 if (sctx->queued.named.rasterizer == state)
1275 si_pm4_bind_state(sctx, poly_offset, NULL);
1276 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1277 }
1278
1279 /*
1280 * infeered state between dsa and stencil ref
1281 */
1282 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1283 {
1284 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1285 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1286 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1287
1288 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1289 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1290 S_028430_STENCILMASK(dsa->valuemask[0]) |
1291 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1292 S_028430_STENCILOPVAL(1));
1293 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1294 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1295 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1296 S_028434_STENCILOPVAL_BF(1));
1297 }
1298
1299 static void si_set_stencil_ref(struct pipe_context *ctx,
1300 const struct pipe_stencil_ref *state)
1301 {
1302 struct si_context *sctx = (struct si_context *)ctx;
1303
1304 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1305 return;
1306
1307 sctx->stencil_ref.state = *state;
1308 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1309 }
1310
1311
1312 /*
1313 * DSA
1314 */
1315
1316 static uint32_t si_translate_stencil_op(int s_op)
1317 {
1318 switch (s_op) {
1319 case PIPE_STENCIL_OP_KEEP:
1320 return V_02842C_STENCIL_KEEP;
1321 case PIPE_STENCIL_OP_ZERO:
1322 return V_02842C_STENCIL_ZERO;
1323 case PIPE_STENCIL_OP_REPLACE:
1324 return V_02842C_STENCIL_REPLACE_TEST;
1325 case PIPE_STENCIL_OP_INCR:
1326 return V_02842C_STENCIL_ADD_CLAMP;
1327 case PIPE_STENCIL_OP_DECR:
1328 return V_02842C_STENCIL_SUB_CLAMP;
1329 case PIPE_STENCIL_OP_INCR_WRAP:
1330 return V_02842C_STENCIL_ADD_WRAP;
1331 case PIPE_STENCIL_OP_DECR_WRAP:
1332 return V_02842C_STENCIL_SUB_WRAP;
1333 case PIPE_STENCIL_OP_INVERT:
1334 return V_02842C_STENCIL_INVERT;
1335 default:
1336 R600_ERR("Unknown stencil op %d", s_op);
1337 assert(0);
1338 break;
1339 }
1340 return 0;
1341 }
1342
1343 static void *si_create_dsa_state(struct pipe_context *ctx,
1344 const struct pipe_depth_stencil_alpha_state *state)
1345 {
1346 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1347 struct si_pm4_state *pm4 = &dsa->pm4;
1348 unsigned db_depth_control;
1349 uint32_t db_stencil_control = 0;
1350
1351 if (!dsa) {
1352 return NULL;
1353 }
1354
1355 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1356 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1357 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1358 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1359
1360 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1361 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1362 S_028800_ZFUNC(state->depth.func) |
1363 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1364
1365 /* stencil */
1366 if (state->stencil[0].enabled) {
1367 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1368 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1369 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1370 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1371 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1372
1373 if (state->stencil[1].enabled) {
1374 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1375 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1376 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1377 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1378 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1379 }
1380 }
1381
1382 /* alpha */
1383 if (state->alpha.enabled) {
1384 dsa->alpha_func = state->alpha.func;
1385
1386 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1387 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1388 } else {
1389 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1390 }
1391
1392 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1393 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1394 if (state->depth.bounds_test) {
1395 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1396 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1397 }
1398
1399 return dsa;
1400 }
1401
1402 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1403 {
1404 struct si_context *sctx = (struct si_context *)ctx;
1405 struct si_state_dsa *dsa = state;
1406
1407 if (!state)
1408 return;
1409
1410 si_pm4_bind_state(sctx, dsa, dsa);
1411
1412 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1413 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1414 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1415 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1416 }
1417 }
1418
1419 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1420 {
1421 struct si_context *sctx = (struct si_context *)ctx;
1422 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1423 }
1424
1425 static void *si_create_db_flush_dsa(struct si_context *sctx)
1426 {
1427 struct pipe_depth_stencil_alpha_state dsa = {};
1428
1429 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1430 }
1431
1432 /* DB RENDER STATE */
1433
1434 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1435 {
1436 struct si_context *sctx = (struct si_context*)ctx;
1437
1438 /* Pipeline stat & streamout queries. */
1439 if (enable) {
1440 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1441 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1442 } else {
1443 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1444 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1445 }
1446
1447 /* Occlusion queries. */
1448 if (sctx->occlusion_queries_disabled != !enable) {
1449 sctx->occlusion_queries_disabled = !enable;
1450 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1451 }
1452 }
1453
1454 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1455 {
1456 struct si_context *sctx = (struct si_context*)ctx;
1457
1458 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1459 }
1460
1461 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1462 {
1463 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1464 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1465 unsigned db_shader_control;
1466
1467 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1468
1469 /* DB_RENDER_CONTROL */
1470 if (sctx->dbcb_depth_copy_enabled ||
1471 sctx->dbcb_stencil_copy_enabled) {
1472 radeon_emit(cs,
1473 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1474 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1475 S_028000_COPY_CENTROID(1) |
1476 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1477 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1478 radeon_emit(cs,
1479 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1480 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1481 } else {
1482 radeon_emit(cs,
1483 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1484 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1485 }
1486
1487 /* DB_COUNT_CONTROL (occlusion queries) */
1488 if (sctx->b.num_occlusion_queries > 0 &&
1489 !sctx->occlusion_queries_disabled) {
1490 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1491
1492 if (sctx->b.chip_class >= CIK) {
1493 radeon_emit(cs,
1494 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1495 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1496 S_028004_ZPASS_ENABLE(1) |
1497 S_028004_SLICE_EVEN_ENABLE(1) |
1498 S_028004_SLICE_ODD_ENABLE(1));
1499 } else {
1500 radeon_emit(cs,
1501 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1502 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1503 }
1504 } else {
1505 /* Disable occlusion queries. */
1506 if (sctx->b.chip_class >= CIK) {
1507 radeon_emit(cs, 0);
1508 } else {
1509 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1510 }
1511 }
1512
1513 /* DB_RENDER_OVERRIDE2 */
1514 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1515 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1516 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1517
1518 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1519 sctx->ps_db_shader_control;
1520
1521 /* Bug workaround for smoothing (overrasterization) on SI. */
1522 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1523 db_shader_control &= C_02880C_Z_ORDER;
1524 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1525 }
1526
1527 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1528 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1529 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1530
1531 if (sctx->b.family == CHIP_STONEY &&
1532 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1533 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1534
1535 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1536 db_shader_control);
1537 }
1538
1539 /*
1540 * format translation
1541 */
1542 static uint32_t si_translate_colorformat(enum pipe_format format)
1543 {
1544 const struct util_format_description *desc = util_format_description(format);
1545
1546 #define HAS_SIZE(x,y,z,w) \
1547 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1548 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1549
1550 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1551 return V_028C70_COLOR_10_11_11;
1552
1553 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1554 return V_028C70_COLOR_INVALID;
1555
1556 switch (desc->nr_channels) {
1557 case 1:
1558 switch (desc->channel[0].size) {
1559 case 8:
1560 return V_028C70_COLOR_8;
1561 case 16:
1562 return V_028C70_COLOR_16;
1563 case 32:
1564 return V_028C70_COLOR_32;
1565 }
1566 break;
1567 case 2:
1568 if (desc->channel[0].size == desc->channel[1].size) {
1569 switch (desc->channel[0].size) {
1570 case 8:
1571 return V_028C70_COLOR_8_8;
1572 case 16:
1573 return V_028C70_COLOR_16_16;
1574 case 32:
1575 return V_028C70_COLOR_32_32;
1576 }
1577 } else if (HAS_SIZE(8,24,0,0)) {
1578 return V_028C70_COLOR_24_8;
1579 } else if (HAS_SIZE(24,8,0,0)) {
1580 return V_028C70_COLOR_8_24;
1581 }
1582 break;
1583 case 3:
1584 if (HAS_SIZE(5,6,5,0)) {
1585 return V_028C70_COLOR_5_6_5;
1586 } else if (HAS_SIZE(32,8,24,0)) {
1587 return V_028C70_COLOR_X24_8_32_FLOAT;
1588 }
1589 break;
1590 case 4:
1591 if (desc->channel[0].size == desc->channel[1].size &&
1592 desc->channel[0].size == desc->channel[2].size &&
1593 desc->channel[0].size == desc->channel[3].size) {
1594 switch (desc->channel[0].size) {
1595 case 4:
1596 return V_028C70_COLOR_4_4_4_4;
1597 case 8:
1598 return V_028C70_COLOR_8_8_8_8;
1599 case 16:
1600 return V_028C70_COLOR_16_16_16_16;
1601 case 32:
1602 return V_028C70_COLOR_32_32_32_32;
1603 }
1604 } else if (HAS_SIZE(5,5,5,1)) {
1605 return V_028C70_COLOR_1_5_5_5;
1606 } else if (HAS_SIZE(10,10,10,2)) {
1607 return V_028C70_COLOR_2_10_10_10;
1608 }
1609 break;
1610 }
1611 return V_028C70_COLOR_INVALID;
1612 }
1613
1614 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1615 {
1616 if (SI_BIG_ENDIAN) {
1617 switch(colorformat) {
1618 /* 8-bit buffers. */
1619 case V_028C70_COLOR_8:
1620 return V_028C70_ENDIAN_NONE;
1621
1622 /* 16-bit buffers. */
1623 case V_028C70_COLOR_5_6_5:
1624 case V_028C70_COLOR_1_5_5_5:
1625 case V_028C70_COLOR_4_4_4_4:
1626 case V_028C70_COLOR_16:
1627 case V_028C70_COLOR_8_8:
1628 return V_028C70_ENDIAN_8IN16;
1629
1630 /* 32-bit buffers. */
1631 case V_028C70_COLOR_8_8_8_8:
1632 case V_028C70_COLOR_2_10_10_10:
1633 case V_028C70_COLOR_8_24:
1634 case V_028C70_COLOR_24_8:
1635 case V_028C70_COLOR_16_16:
1636 return V_028C70_ENDIAN_8IN32;
1637
1638 /* 64-bit buffers. */
1639 case V_028C70_COLOR_16_16_16_16:
1640 return V_028C70_ENDIAN_8IN16;
1641
1642 case V_028C70_COLOR_32_32:
1643 return V_028C70_ENDIAN_8IN32;
1644
1645 /* 128-bit buffers. */
1646 case V_028C70_COLOR_32_32_32_32:
1647 return V_028C70_ENDIAN_8IN32;
1648 default:
1649 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1650 }
1651 } else {
1652 return V_028C70_ENDIAN_NONE;
1653 }
1654 }
1655
1656 static uint32_t si_translate_dbformat(enum pipe_format format)
1657 {
1658 switch (format) {
1659 case PIPE_FORMAT_Z16_UNORM:
1660 return V_028040_Z_16;
1661 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1662 case PIPE_FORMAT_X8Z24_UNORM:
1663 case PIPE_FORMAT_Z24X8_UNORM:
1664 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1665 return V_028040_Z_24; /* deprecated on SI */
1666 case PIPE_FORMAT_Z32_FLOAT:
1667 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1668 return V_028040_Z_32_FLOAT;
1669 default:
1670 return V_028040_Z_INVALID;
1671 }
1672 }
1673
1674 /*
1675 * Texture translation
1676 */
1677
1678 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1679 enum pipe_format format,
1680 const struct util_format_description *desc,
1681 int first_non_void)
1682 {
1683 struct si_screen *sscreen = (struct si_screen*)screen;
1684 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1685 sscreen->b.info.drm_minor >= 31) ||
1686 sscreen->b.info.drm_major == 3;
1687 boolean uniform = TRUE;
1688 int i;
1689
1690 /* Colorspace (return non-RGB formats directly). */
1691 switch (desc->colorspace) {
1692 /* Depth stencil formats */
1693 case UTIL_FORMAT_COLORSPACE_ZS:
1694 switch (format) {
1695 case PIPE_FORMAT_Z16_UNORM:
1696 return V_008F14_IMG_DATA_FORMAT_16;
1697 case PIPE_FORMAT_X24S8_UINT:
1698 case PIPE_FORMAT_Z24X8_UNORM:
1699 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1700 return V_008F14_IMG_DATA_FORMAT_8_24;
1701 case PIPE_FORMAT_X8Z24_UNORM:
1702 case PIPE_FORMAT_S8X24_UINT:
1703 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1704 return V_008F14_IMG_DATA_FORMAT_24_8;
1705 case PIPE_FORMAT_S8_UINT:
1706 return V_008F14_IMG_DATA_FORMAT_8;
1707 case PIPE_FORMAT_Z32_FLOAT:
1708 return V_008F14_IMG_DATA_FORMAT_32;
1709 case PIPE_FORMAT_X32_S8X24_UINT:
1710 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1711 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1712 default:
1713 goto out_unknown;
1714 }
1715
1716 case UTIL_FORMAT_COLORSPACE_YUV:
1717 goto out_unknown; /* TODO */
1718
1719 case UTIL_FORMAT_COLORSPACE_SRGB:
1720 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1721 goto out_unknown;
1722 break;
1723
1724 default:
1725 break;
1726 }
1727
1728 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1729 if (!enable_compressed_formats)
1730 goto out_unknown;
1731
1732 switch (format) {
1733 case PIPE_FORMAT_RGTC1_SNORM:
1734 case PIPE_FORMAT_LATC1_SNORM:
1735 case PIPE_FORMAT_RGTC1_UNORM:
1736 case PIPE_FORMAT_LATC1_UNORM:
1737 return V_008F14_IMG_DATA_FORMAT_BC4;
1738 case PIPE_FORMAT_RGTC2_SNORM:
1739 case PIPE_FORMAT_LATC2_SNORM:
1740 case PIPE_FORMAT_RGTC2_UNORM:
1741 case PIPE_FORMAT_LATC2_UNORM:
1742 return V_008F14_IMG_DATA_FORMAT_BC5;
1743 default:
1744 goto out_unknown;
1745 }
1746 }
1747
1748 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1749 sscreen->b.family >= CHIP_STONEY) {
1750 switch (format) {
1751 case PIPE_FORMAT_ETC1_RGB8:
1752 case PIPE_FORMAT_ETC2_RGB8:
1753 case PIPE_FORMAT_ETC2_SRGB8:
1754 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1755 case PIPE_FORMAT_ETC2_RGB8A1:
1756 case PIPE_FORMAT_ETC2_SRGB8A1:
1757 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1758 case PIPE_FORMAT_ETC2_RGBA8:
1759 case PIPE_FORMAT_ETC2_SRGBA8:
1760 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1761 case PIPE_FORMAT_ETC2_R11_UNORM:
1762 case PIPE_FORMAT_ETC2_R11_SNORM:
1763 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1764 case PIPE_FORMAT_ETC2_RG11_UNORM:
1765 case PIPE_FORMAT_ETC2_RG11_SNORM:
1766 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1767 default:
1768 goto out_unknown;
1769 }
1770 }
1771
1772 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1773 if (!enable_compressed_formats)
1774 goto out_unknown;
1775
1776 switch (format) {
1777 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1778 case PIPE_FORMAT_BPTC_SRGBA:
1779 return V_008F14_IMG_DATA_FORMAT_BC7;
1780 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1781 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1782 return V_008F14_IMG_DATA_FORMAT_BC6;
1783 default:
1784 goto out_unknown;
1785 }
1786 }
1787
1788 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1789 switch (format) {
1790 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1791 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1792 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1793 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1794 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1795 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1796 default:
1797 goto out_unknown;
1798 }
1799 }
1800
1801 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1802 if (!enable_compressed_formats)
1803 goto out_unknown;
1804
1805 if (!util_format_s3tc_enabled) {
1806 goto out_unknown;
1807 }
1808
1809 switch (format) {
1810 case PIPE_FORMAT_DXT1_RGB:
1811 case PIPE_FORMAT_DXT1_RGBA:
1812 case PIPE_FORMAT_DXT1_SRGB:
1813 case PIPE_FORMAT_DXT1_SRGBA:
1814 return V_008F14_IMG_DATA_FORMAT_BC1;
1815 case PIPE_FORMAT_DXT3_RGBA:
1816 case PIPE_FORMAT_DXT3_SRGBA:
1817 return V_008F14_IMG_DATA_FORMAT_BC2;
1818 case PIPE_FORMAT_DXT5_RGBA:
1819 case PIPE_FORMAT_DXT5_SRGBA:
1820 return V_008F14_IMG_DATA_FORMAT_BC3;
1821 default:
1822 goto out_unknown;
1823 }
1824 }
1825
1826 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1827 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1828 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1829 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1830 }
1831
1832 /* R8G8Bx_SNORM - TODO CxV8U8 */
1833
1834 /* See whether the components are of the same size. */
1835 for (i = 1; i < desc->nr_channels; i++) {
1836 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1837 }
1838
1839 /* Non-uniform formats. */
1840 if (!uniform) {
1841 switch(desc->nr_channels) {
1842 case 3:
1843 if (desc->channel[0].size == 5 &&
1844 desc->channel[1].size == 6 &&
1845 desc->channel[2].size == 5) {
1846 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1847 }
1848 goto out_unknown;
1849 case 4:
1850 if (desc->channel[0].size == 5 &&
1851 desc->channel[1].size == 5 &&
1852 desc->channel[2].size == 5 &&
1853 desc->channel[3].size == 1) {
1854 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1855 }
1856 if (desc->channel[0].size == 10 &&
1857 desc->channel[1].size == 10 &&
1858 desc->channel[2].size == 10 &&
1859 desc->channel[3].size == 2) {
1860 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1861 }
1862 goto out_unknown;
1863 }
1864 goto out_unknown;
1865 }
1866
1867 if (first_non_void < 0 || first_non_void > 3)
1868 goto out_unknown;
1869
1870 /* uniform formats */
1871 switch (desc->channel[first_non_void].size) {
1872 case 4:
1873 switch (desc->nr_channels) {
1874 #if 0 /* Not supported for render targets */
1875 case 2:
1876 return V_008F14_IMG_DATA_FORMAT_4_4;
1877 #endif
1878 case 4:
1879 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1880 }
1881 break;
1882 case 8:
1883 switch (desc->nr_channels) {
1884 case 1:
1885 return V_008F14_IMG_DATA_FORMAT_8;
1886 case 2:
1887 return V_008F14_IMG_DATA_FORMAT_8_8;
1888 case 4:
1889 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1890 }
1891 break;
1892 case 16:
1893 switch (desc->nr_channels) {
1894 case 1:
1895 return V_008F14_IMG_DATA_FORMAT_16;
1896 case 2:
1897 return V_008F14_IMG_DATA_FORMAT_16_16;
1898 case 4:
1899 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1900 }
1901 break;
1902 case 32:
1903 switch (desc->nr_channels) {
1904 case 1:
1905 return V_008F14_IMG_DATA_FORMAT_32;
1906 case 2:
1907 return V_008F14_IMG_DATA_FORMAT_32_32;
1908 #if 0 /* Not supported for render targets */
1909 case 3:
1910 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1911 #endif
1912 case 4:
1913 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1914 }
1915 }
1916
1917 out_unknown:
1918 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1919 return ~0;
1920 }
1921
1922 static unsigned si_tex_wrap(unsigned wrap)
1923 {
1924 switch (wrap) {
1925 default:
1926 case PIPE_TEX_WRAP_REPEAT:
1927 return V_008F30_SQ_TEX_WRAP;
1928 case PIPE_TEX_WRAP_CLAMP:
1929 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1930 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1931 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1932 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1933 return V_008F30_SQ_TEX_CLAMP_BORDER;
1934 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1935 return V_008F30_SQ_TEX_MIRROR;
1936 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1937 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1938 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1939 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1940 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1941 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1942 }
1943 }
1944
1945 static unsigned si_tex_mipfilter(unsigned filter)
1946 {
1947 switch (filter) {
1948 case PIPE_TEX_MIPFILTER_NEAREST:
1949 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1950 case PIPE_TEX_MIPFILTER_LINEAR:
1951 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1952 default:
1953 case PIPE_TEX_MIPFILTER_NONE:
1954 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1955 }
1956 }
1957
1958 static unsigned si_tex_compare(unsigned compare)
1959 {
1960 switch (compare) {
1961 default:
1962 case PIPE_FUNC_NEVER:
1963 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1964 case PIPE_FUNC_LESS:
1965 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1966 case PIPE_FUNC_EQUAL:
1967 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1968 case PIPE_FUNC_LEQUAL:
1969 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1970 case PIPE_FUNC_GREATER:
1971 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1972 case PIPE_FUNC_NOTEQUAL:
1973 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1974 case PIPE_FUNC_GEQUAL:
1975 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1976 case PIPE_FUNC_ALWAYS:
1977 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1978 }
1979 }
1980
1981 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1982 unsigned nr_samples)
1983 {
1984 if (view_target == PIPE_TEXTURE_CUBE ||
1985 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1986 res_target = view_target;
1987
1988 switch (res_target) {
1989 default:
1990 case PIPE_TEXTURE_1D:
1991 return V_008F1C_SQ_RSRC_IMG_1D;
1992 case PIPE_TEXTURE_1D_ARRAY:
1993 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1994 case PIPE_TEXTURE_2D:
1995 case PIPE_TEXTURE_RECT:
1996 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1997 V_008F1C_SQ_RSRC_IMG_2D;
1998 case PIPE_TEXTURE_2D_ARRAY:
1999 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2000 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2001 case PIPE_TEXTURE_3D:
2002 return V_008F1C_SQ_RSRC_IMG_3D;
2003 case PIPE_TEXTURE_CUBE:
2004 case PIPE_TEXTURE_CUBE_ARRAY:
2005 return V_008F1C_SQ_RSRC_IMG_CUBE;
2006 }
2007 }
2008
2009 /*
2010 * Format support testing
2011 */
2012
2013 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2014 {
2015 return si_translate_texformat(screen, format, util_format_description(format),
2016 util_format_get_first_non_void_channel(format)) != ~0U;
2017 }
2018
2019 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2020 const struct util_format_description *desc,
2021 int first_non_void)
2022 {
2023 unsigned type = desc->channel[first_non_void].type;
2024 int i;
2025
2026 if (type == UTIL_FORMAT_TYPE_FIXED)
2027 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2028
2029 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2030 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2031
2032 if (desc->nr_channels == 4 &&
2033 desc->channel[0].size == 10 &&
2034 desc->channel[1].size == 10 &&
2035 desc->channel[2].size == 10 &&
2036 desc->channel[3].size == 2)
2037 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2038
2039 /* See whether the components are of the same size. */
2040 for (i = 0; i < desc->nr_channels; i++) {
2041 if (desc->channel[first_non_void].size != desc->channel[i].size)
2042 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2043 }
2044
2045 switch (desc->channel[first_non_void].size) {
2046 case 8:
2047 switch (desc->nr_channels) {
2048 case 1:
2049 return V_008F0C_BUF_DATA_FORMAT_8;
2050 case 2:
2051 return V_008F0C_BUF_DATA_FORMAT_8_8;
2052 case 3:
2053 case 4:
2054 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2055 }
2056 break;
2057 case 16:
2058 switch (desc->nr_channels) {
2059 case 1:
2060 return V_008F0C_BUF_DATA_FORMAT_16;
2061 case 2:
2062 return V_008F0C_BUF_DATA_FORMAT_16_16;
2063 case 3:
2064 case 4:
2065 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2066 }
2067 break;
2068 case 32:
2069 /* From the Southern Islands ISA documentation about MTBUF:
2070 * 'Memory reads of data in memory that is 32 or 64 bits do not
2071 * undergo any format conversion.'
2072 */
2073 if (type != UTIL_FORMAT_TYPE_FLOAT &&
2074 !desc->channel[first_non_void].pure_integer)
2075 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2076
2077 switch (desc->nr_channels) {
2078 case 1:
2079 return V_008F0C_BUF_DATA_FORMAT_32;
2080 case 2:
2081 return V_008F0C_BUF_DATA_FORMAT_32_32;
2082 case 3:
2083 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2084 case 4:
2085 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2086 }
2087 break;
2088 }
2089
2090 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2091 }
2092
2093 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2094 const struct util_format_description *desc,
2095 int first_non_void)
2096 {
2097 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2098 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2099
2100 switch (desc->channel[first_non_void].type) {
2101 case UTIL_FORMAT_TYPE_SIGNED:
2102 if (desc->channel[first_non_void].normalized)
2103 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2104 else if (desc->channel[first_non_void].pure_integer)
2105 return V_008F0C_BUF_NUM_FORMAT_SINT;
2106 else
2107 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2108 break;
2109 case UTIL_FORMAT_TYPE_UNSIGNED:
2110 if (desc->channel[first_non_void].normalized)
2111 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2112 else if (desc->channel[first_non_void].pure_integer)
2113 return V_008F0C_BUF_NUM_FORMAT_UINT;
2114 else
2115 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2116 break;
2117 case UTIL_FORMAT_TYPE_FLOAT:
2118 default:
2119 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2120 }
2121 }
2122
2123 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
2124 {
2125 const struct util_format_description *desc;
2126 int first_non_void;
2127 unsigned data_format;
2128
2129 desc = util_format_description(format);
2130 first_non_void = util_format_get_first_non_void_channel(format);
2131 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2132 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
2133 }
2134
2135 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2136 {
2137 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2138 r600_translate_colorswap(format) != ~0U;
2139 }
2140
2141 static bool si_is_zs_format_supported(enum pipe_format format)
2142 {
2143 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2144 }
2145
2146 boolean si_is_format_supported(struct pipe_screen *screen,
2147 enum pipe_format format,
2148 enum pipe_texture_target target,
2149 unsigned sample_count,
2150 unsigned usage)
2151 {
2152 unsigned retval = 0;
2153
2154 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2155 R600_ERR("r600: unsupported texture type %d\n", target);
2156 return FALSE;
2157 }
2158
2159 if (!util_format_is_supported(format, usage))
2160 return FALSE;
2161
2162 if (sample_count > 1) {
2163 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2164 return FALSE;
2165
2166 switch (sample_count) {
2167 case 2:
2168 case 4:
2169 case 8:
2170 break;
2171 case 16:
2172 if (format == PIPE_FORMAT_NONE)
2173 return TRUE;
2174 else
2175 return FALSE;
2176 default:
2177 return FALSE;
2178 }
2179 }
2180
2181 if (usage & PIPE_BIND_SAMPLER_VIEW) {
2182 if (target == PIPE_BUFFER) {
2183 if (si_is_vertex_format_supported(screen, format))
2184 retval |= PIPE_BIND_SAMPLER_VIEW;
2185 } else {
2186 if (si_is_sampler_format_supported(screen, format))
2187 retval |= PIPE_BIND_SAMPLER_VIEW;
2188 }
2189 }
2190
2191 if ((usage & (PIPE_BIND_RENDER_TARGET |
2192 PIPE_BIND_DISPLAY_TARGET |
2193 PIPE_BIND_SCANOUT |
2194 PIPE_BIND_SHARED |
2195 PIPE_BIND_BLENDABLE)) &&
2196 si_is_colorbuffer_format_supported(format)) {
2197 retval |= usage &
2198 (PIPE_BIND_RENDER_TARGET |
2199 PIPE_BIND_DISPLAY_TARGET |
2200 PIPE_BIND_SCANOUT |
2201 PIPE_BIND_SHARED);
2202 if (!util_format_is_pure_integer(format) &&
2203 !util_format_is_depth_or_stencil(format))
2204 retval |= usage & PIPE_BIND_BLENDABLE;
2205 }
2206
2207 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2208 si_is_zs_format_supported(format)) {
2209 retval |= PIPE_BIND_DEPTH_STENCIL;
2210 }
2211
2212 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
2213 si_is_vertex_format_supported(screen, format)) {
2214 retval |= PIPE_BIND_VERTEX_BUFFER;
2215 }
2216
2217 if (usage & PIPE_BIND_TRANSFER_READ)
2218 retval |= PIPE_BIND_TRANSFER_READ;
2219 if (usage & PIPE_BIND_TRANSFER_WRITE)
2220 retval |= PIPE_BIND_TRANSFER_WRITE;
2221
2222 if ((usage & PIPE_BIND_LINEAR) &&
2223 !util_format_is_compressed(format) &&
2224 !(usage & PIPE_BIND_DEPTH_STENCIL))
2225 retval |= PIPE_BIND_LINEAR;
2226
2227 return retval == usage;
2228 }
2229
2230 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
2231 {
2232 unsigned tile_mode_index = 0;
2233
2234 if (stencil) {
2235 tile_mode_index = rtex->surface.stencil_tiling_index[level];
2236 } else {
2237 tile_mode_index = rtex->surface.tiling_index[level];
2238 }
2239 return tile_mode_index;
2240 }
2241
2242 /*
2243 * framebuffer handling
2244 */
2245
2246 static void si_choose_spi_color_formats(struct r600_surface *surf,
2247 unsigned format, unsigned swap,
2248 unsigned ntype, bool is_depth)
2249 {
2250 /* Alpha is needed for alpha-to-coverage.
2251 * Blending may be with or without alpha.
2252 */
2253 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2254 unsigned alpha = 0; /* exports alpha, but may not support blending */
2255 unsigned blend = 0; /* supports blending, but may not export alpha */
2256 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2257
2258 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2259 * Other chips have multiple choices, though they are not necessarily better.
2260 */
2261 switch (format) {
2262 case V_028C70_COLOR_5_6_5:
2263 case V_028C70_COLOR_1_5_5_5:
2264 case V_028C70_COLOR_5_5_5_1:
2265 case V_028C70_COLOR_4_4_4_4:
2266 case V_028C70_COLOR_10_11_11:
2267 case V_028C70_COLOR_11_11_10:
2268 case V_028C70_COLOR_8:
2269 case V_028C70_COLOR_8_8:
2270 case V_028C70_COLOR_8_8_8_8:
2271 case V_028C70_COLOR_10_10_10_2:
2272 case V_028C70_COLOR_2_10_10_10:
2273 if (ntype == V_028C70_NUMBER_UINT)
2274 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2275 else if (ntype == V_028C70_NUMBER_SINT)
2276 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2277 else
2278 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2279 break;
2280
2281 case V_028C70_COLOR_16:
2282 case V_028C70_COLOR_16_16:
2283 case V_028C70_COLOR_16_16_16_16:
2284 if (ntype == V_028C70_NUMBER_UNORM ||
2285 ntype == V_028C70_NUMBER_SNORM) {
2286 /* UNORM16 and SNORM16 don't support blending */
2287 if (ntype == V_028C70_NUMBER_UNORM)
2288 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2289 else
2290 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2291
2292 /* Use 32 bits per channel for blending. */
2293 if (format == V_028C70_COLOR_16) {
2294 if (swap == V_028C70_SWAP_STD) { /* R */
2295 blend = V_028714_SPI_SHADER_32_R;
2296 blend_alpha = V_028714_SPI_SHADER_32_AR;
2297 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2298 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2299 else
2300 assert(0);
2301 } else if (format == V_028C70_COLOR_16_16) {
2302 if (swap == V_028C70_SWAP_STD) { /* RG */
2303 blend = V_028714_SPI_SHADER_32_GR;
2304 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2305 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2306 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2307 else
2308 assert(0);
2309 } else /* 16_16_16_16 */
2310 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2311 } else if (ntype == V_028C70_NUMBER_UINT)
2312 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2313 else if (ntype == V_028C70_NUMBER_SINT)
2314 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2315 else if (ntype == V_028C70_NUMBER_FLOAT)
2316 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2317 else
2318 assert(0);
2319 break;
2320
2321 case V_028C70_COLOR_32:
2322 if (swap == V_028C70_SWAP_STD) { /* R */
2323 blend = normal = V_028714_SPI_SHADER_32_R;
2324 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2325 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2326 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2327 else
2328 assert(0);
2329 break;
2330
2331 case V_028C70_COLOR_32_32:
2332 if (swap == V_028C70_SWAP_STD) { /* RG */
2333 blend = normal = V_028714_SPI_SHADER_32_GR;
2334 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2335 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2336 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2337 else
2338 assert(0);
2339 break;
2340
2341 case V_028C70_COLOR_32_32_32_32:
2342 case V_028C70_COLOR_8_24:
2343 case V_028C70_COLOR_24_8:
2344 case V_028C70_COLOR_X24_8_32_FLOAT:
2345 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2346 break;
2347
2348 default:
2349 assert(0);
2350 return;
2351 }
2352
2353 /* The DB->CB copy needs 32_ABGR. */
2354 if (is_depth)
2355 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2356
2357 surf->spi_shader_col_format = normal;
2358 surf->spi_shader_col_format_alpha = alpha;
2359 surf->spi_shader_col_format_blend = blend;
2360 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2361 }
2362
2363 static void si_initialize_color_surface(struct si_context *sctx,
2364 struct r600_surface *surf)
2365 {
2366 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2367 unsigned level = surf->base.u.tex.level;
2368 uint64_t offset = rtex->surface.level[level].offset;
2369 unsigned pitch, slice;
2370 unsigned color_info, color_attrib, color_pitch, color_view;
2371 unsigned tile_mode_index;
2372 unsigned format, swap, ntype, endian;
2373 const struct util_format_description *desc;
2374 int i;
2375 unsigned blend_clamp = 0, blend_bypass = 0;
2376
2377 /* Layered rendering doesn't work with LINEAR_GENERAL.
2378 * (LINEAR_ALIGNED and others work) */
2379 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2380 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2381 offset += rtex->surface.level[level].slice_size *
2382 surf->base.u.tex.first_layer;
2383 color_view = 0;
2384 } else {
2385 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2386 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2387 }
2388
2389 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2390 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2391 if (slice) {
2392 slice = slice - 1;
2393 }
2394
2395 tile_mode_index = si_tile_mode_index(rtex, level, false);
2396
2397 desc = util_format_description(surf->base.format);
2398 for (i = 0; i < 4; i++) {
2399 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2400 break;
2401 }
2402 }
2403 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2404 ntype = V_028C70_NUMBER_FLOAT;
2405 } else {
2406 ntype = V_028C70_NUMBER_UNORM;
2407 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2408 ntype = V_028C70_NUMBER_SRGB;
2409 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2410 if (desc->channel[i].pure_integer) {
2411 ntype = V_028C70_NUMBER_SINT;
2412 } else {
2413 assert(desc->channel[i].normalized);
2414 ntype = V_028C70_NUMBER_SNORM;
2415 }
2416 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2417 if (desc->channel[i].pure_integer) {
2418 ntype = V_028C70_NUMBER_UINT;
2419 } else {
2420 assert(desc->channel[i].normalized);
2421 ntype = V_028C70_NUMBER_UNORM;
2422 }
2423 }
2424 }
2425
2426 format = si_translate_colorformat(surf->base.format);
2427 if (format == V_028C70_COLOR_INVALID) {
2428 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2429 }
2430 assert(format != V_028C70_COLOR_INVALID);
2431 swap = r600_translate_colorswap(surf->base.format);
2432 endian = si_colorformat_endian_swap(format);
2433
2434 /* blend clamp should be set for all NORM/SRGB types */
2435 if (ntype == V_028C70_NUMBER_UNORM ||
2436 ntype == V_028C70_NUMBER_SNORM ||
2437 ntype == V_028C70_NUMBER_SRGB)
2438 blend_clamp = 1;
2439
2440 /* set blend bypass according to docs if SINT/UINT or
2441 8/24 COLOR variants */
2442 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2443 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2444 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2445 blend_clamp = 0;
2446 blend_bypass = 1;
2447 }
2448
2449 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2450 (format == V_028C70_COLOR_8 ||
2451 format == V_028C70_COLOR_8_8 ||
2452 format == V_028C70_COLOR_8_8_8_8))
2453 surf->color_is_int8 = true;
2454
2455 color_info = S_028C70_FORMAT(format) |
2456 S_028C70_COMP_SWAP(swap) |
2457 S_028C70_BLEND_CLAMP(blend_clamp) |
2458 S_028C70_BLEND_BYPASS(blend_bypass) |
2459 S_028C70_NUMBER_TYPE(ntype) |
2460 S_028C70_ENDIAN(endian);
2461
2462 color_pitch = S_028C64_TILE_MAX(pitch);
2463
2464 /* Intensity is implemented as Red, so treat it that way. */
2465 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2466 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1 ||
2467 util_format_is_intensity(surf->base.format));
2468
2469 if (rtex->resource.b.b.nr_samples > 1) {
2470 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2471
2472 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2473 S_028C74_NUM_FRAGMENTS(log_samples);
2474
2475 if (rtex->fmask.size) {
2476 color_info |= S_028C70_COMPRESSION(1);
2477 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2478
2479 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2480
2481 if (sctx->b.chip_class == SI) {
2482 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2483 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2484 }
2485 if (sctx->b.chip_class >= CIK) {
2486 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2487 }
2488 }
2489 }
2490
2491 offset += rtex->resource.gpu_address;
2492
2493 surf->cb_color_base = offset >> 8;
2494 surf->cb_color_pitch = color_pitch;
2495 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2496 surf->cb_color_view = color_view;
2497 surf->cb_color_info = color_info;
2498 surf->cb_color_attrib = color_attrib;
2499
2500 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2501 unsigned max_uncompressed_block_size = 2;
2502
2503 if (rtex->surface.nsamples > 1) {
2504 if (rtex->surface.bpe == 1)
2505 max_uncompressed_block_size = 0;
2506 else if (rtex->surface.bpe == 2)
2507 max_uncompressed_block_size = 1;
2508 }
2509
2510 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2511 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2512 surf->cb_dcc_base = (rtex->resource.gpu_address +
2513 rtex->dcc_offset +
2514 rtex->surface.level[level].dcc_offset) >> 8;
2515 }
2516
2517 if (rtex->fmask.size) {
2518 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2519 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2520 } else {
2521 /* This must be set for fast clear to work without FMASK. */
2522 surf->cb_color_fmask = surf->cb_color_base;
2523 surf->cb_color_fmask_slice = surf->cb_color_slice;
2524 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2525
2526 if (sctx->b.chip_class == SI) {
2527 unsigned bankh = util_logbase2(rtex->surface.bankh);
2528 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2529 }
2530
2531 if (sctx->b.chip_class >= CIK) {
2532 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2533 }
2534 }
2535
2536 /* Determine pixel shader export format */
2537 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2538
2539 surf->color_initialized = true;
2540 }
2541
2542 static void si_init_depth_surface(struct si_context *sctx,
2543 struct r600_surface *surf)
2544 {
2545 struct si_screen *sscreen = sctx->screen;
2546 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2547 unsigned level = surf->base.u.tex.level;
2548 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2549 unsigned format, tile_mode_index, array_mode;
2550 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2551 uint32_t z_info, s_info, db_depth_info;
2552 uint64_t z_offs, s_offs;
2553 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2554
2555 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2556 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2557 case PIPE_FORMAT_X8Z24_UNORM:
2558 case PIPE_FORMAT_Z24X8_UNORM:
2559 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2560 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2561 break;
2562 case PIPE_FORMAT_Z32_FLOAT:
2563 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2564 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2565 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2566 break;
2567 case PIPE_FORMAT_Z16_UNORM:
2568 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2569 break;
2570 default:
2571 assert(0);
2572 }
2573
2574 format = si_translate_dbformat(rtex->resource.b.b.format);
2575
2576 if (format == V_028040_Z_INVALID) {
2577 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2578 }
2579 assert(format != V_028040_Z_INVALID);
2580
2581 s_offs = z_offs = rtex->resource.gpu_address;
2582 z_offs += rtex->surface.level[level].offset;
2583 s_offs += rtex->surface.stencil_level[level].offset;
2584
2585 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2586
2587 z_info = S_028040_FORMAT(format);
2588 if (rtex->resource.b.b.nr_samples > 1) {
2589 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2590 }
2591
2592 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2593 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2594 else
2595 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2596
2597 if (sctx->b.chip_class >= CIK) {
2598 switch (rtex->surface.level[level].mode) {
2599 case RADEON_SURF_MODE_2D:
2600 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2601 break;
2602 case RADEON_SURF_MODE_1D:
2603 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2604 case RADEON_SURF_MODE_LINEAR:
2605 default:
2606 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2607 break;
2608 }
2609 tile_split = rtex->surface.tile_split;
2610 stile_split = rtex->surface.stencil_tile_split;
2611 macro_aspect = rtex->surface.mtilea;
2612 bankw = rtex->surface.bankw;
2613 bankh = rtex->surface.bankh;
2614 tile_split = cik_tile_split(tile_split);
2615 stile_split = cik_tile_split(stile_split);
2616 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2617 bankw = cik_bank_wh(bankw);
2618 bankh = cik_bank_wh(bankh);
2619 nbanks = si_num_banks(sscreen, rtex);
2620 tile_mode_index = si_tile_mode_index(rtex, level, false);
2621 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2622
2623 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2624 S_02803C_PIPE_CONFIG(pipe_config) |
2625 S_02803C_BANK_WIDTH(bankw) |
2626 S_02803C_BANK_HEIGHT(bankh) |
2627 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2628 S_02803C_NUM_BANKS(nbanks);
2629 z_info |= S_028040_TILE_SPLIT(tile_split);
2630 s_info |= S_028044_TILE_SPLIT(stile_split);
2631 } else {
2632 tile_mode_index = si_tile_mode_index(rtex, level, false);
2633 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2634 tile_mode_index = si_tile_mode_index(rtex, level, true);
2635 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2636 }
2637
2638 /* HiZ aka depth buffer htile */
2639 /* use htile only for first level */
2640 if (rtex->htile_buffer && !level) {
2641 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2642 S_028040_ALLOW_EXPCLEAR(1);
2643
2644 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2645 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2646 else
2647 /* Use all of the htile_buffer for depth if there's no stencil. */
2648 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2649
2650 uint64_t va = rtex->htile_buffer->gpu_address;
2651 db_htile_data_base = va >> 8;
2652 db_htile_surface = S_028ABC_FULL_CACHE(1);
2653 } else {
2654 db_htile_data_base = 0;
2655 db_htile_surface = 0;
2656 }
2657
2658 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2659
2660 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2661 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2662 surf->db_htile_data_base = db_htile_data_base;
2663 surf->db_depth_info = db_depth_info;
2664 surf->db_z_info = z_info;
2665 surf->db_stencil_info = s_info;
2666 surf->db_depth_base = z_offs >> 8;
2667 surf->db_stencil_base = s_offs >> 8;
2668 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2669 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2670 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2671 levelinfo->nblk_y) / 64 - 1);
2672 surf->db_htile_surface = db_htile_surface;
2673 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2674
2675 surf->depth_initialized = true;
2676 }
2677
2678 static void si_set_framebuffer_state(struct pipe_context *ctx,
2679 const struct pipe_framebuffer_state *state)
2680 {
2681 struct si_context *sctx = (struct si_context *)ctx;
2682 struct pipe_constant_buffer constbuf = {0};
2683 struct r600_surface *surf = NULL;
2684 struct r600_texture *rtex;
2685 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2686 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2687 int i;
2688
2689 /* Only flush TC when changing the framebuffer state, because
2690 * the only client not using TC that can change textures is
2691 * the framebuffer.
2692 *
2693 * Flush all CB and DB caches here because all buffers can be used
2694 * for write by both TC (with shader image stores) and CB/DB.
2695 */
2696 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2697 SI_CONTEXT_INV_GLOBAL_L2 |
2698 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2699
2700 /* Take the maximum of the old and new count. If the new count is lower,
2701 * dirtying is needed to disable the unbound colorbuffers.
2702 */
2703 sctx->framebuffer.dirty_cbufs |=
2704 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2705 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2706
2707 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2708
2709 sctx->framebuffer.spi_shader_col_format = 0;
2710 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2711 sctx->framebuffer.spi_shader_col_format_blend = 0;
2712 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2713 sctx->framebuffer.color_is_int8 = 0;
2714
2715 sctx->framebuffer.compressed_cb_mask = 0;
2716 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2717 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2718 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2719 util_format_is_pure_integer(state->cbufs[0]->format);
2720
2721 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2722 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2723
2724 for (i = 0; i < state->nr_cbufs; i++) {
2725 if (!state->cbufs[i])
2726 continue;
2727
2728 surf = (struct r600_surface*)state->cbufs[i];
2729 rtex = (struct r600_texture*)surf->base.texture;
2730
2731 if (!surf->color_initialized) {
2732 si_initialize_color_surface(sctx, surf);
2733 }
2734
2735 sctx->framebuffer.spi_shader_col_format |=
2736 surf->spi_shader_col_format << (i * 4);
2737 sctx->framebuffer.spi_shader_col_format_alpha |=
2738 surf->spi_shader_col_format_alpha << (i * 4);
2739 sctx->framebuffer.spi_shader_col_format_blend |=
2740 surf->spi_shader_col_format_blend << (i * 4);
2741 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2742 surf->spi_shader_col_format_blend_alpha << (i * 4);
2743
2744 if (surf->color_is_int8)
2745 sctx->framebuffer.color_is_int8 |= 1 << i;
2746
2747 if (rtex->fmask.size && rtex->cmask.size) {
2748 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2749 }
2750 r600_context_add_resource_size(ctx, surf->base.texture);
2751 }
2752 /* Set the second SPI format for possible dual-src blending. */
2753 if (i == 1 && surf) {
2754 sctx->framebuffer.spi_shader_col_format |=
2755 surf->spi_shader_col_format << (i * 4);
2756 sctx->framebuffer.spi_shader_col_format_alpha |=
2757 surf->spi_shader_col_format_alpha << (i * 4);
2758 sctx->framebuffer.spi_shader_col_format_blend |=
2759 surf->spi_shader_col_format_blend << (i * 4);
2760 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2761 surf->spi_shader_col_format_blend_alpha << (i * 4);
2762 }
2763
2764 if (state->zsbuf) {
2765 surf = (struct r600_surface*)state->zsbuf;
2766
2767 if (!surf->depth_initialized) {
2768 si_init_depth_surface(sctx, surf);
2769 }
2770 r600_context_add_resource_size(ctx, surf->base.texture);
2771 }
2772
2773 si_update_poly_offset_state(sctx);
2774 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2775 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2776
2777 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2778 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2779 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2780
2781 /* Set sample locations as fragment shader constants. */
2782 switch (sctx->framebuffer.nr_samples) {
2783 case 1:
2784 constbuf.user_buffer = sctx->b.sample_locations_1x;
2785 break;
2786 case 2:
2787 constbuf.user_buffer = sctx->b.sample_locations_2x;
2788 break;
2789 case 4:
2790 constbuf.user_buffer = sctx->b.sample_locations_4x;
2791 break;
2792 case 8:
2793 constbuf.user_buffer = sctx->b.sample_locations_8x;
2794 break;
2795 case 16:
2796 constbuf.user_buffer = sctx->b.sample_locations_16x;
2797 break;
2798 default:
2799 R600_ERR("Requested an invalid number of samples %i.\n",
2800 sctx->framebuffer.nr_samples);
2801 assert(0);
2802 }
2803 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2804 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2805 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2806
2807 /* Smoothing (only possible with nr_samples == 1) uses the same
2808 * sample locations as the MSAA it simulates.
2809 *
2810 * Therefore, don't update the sample locations when
2811 * transitioning from no AA to smoothing-equivalent AA, and
2812 * vice versa.
2813 */
2814 if ((sctx->framebuffer.nr_samples != 1 ||
2815 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2816 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2817 old_nr_samples != 1))
2818 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2819 }
2820 }
2821
2822 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2823 {
2824 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2825 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2826 unsigned i, nr_cbufs = state->nr_cbufs;
2827 struct r600_texture *tex = NULL;
2828 struct r600_surface *cb = NULL;
2829
2830 /* Colorbuffers. */
2831 for (i = 0; i < nr_cbufs; i++) {
2832 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2833 continue;
2834
2835 cb = (struct r600_surface*)state->cbufs[i];
2836 if (!cb) {
2837 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2838 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2839 continue;
2840 }
2841
2842 tex = (struct r600_texture *)cb->base.texture;
2843 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2844 &tex->resource, RADEON_USAGE_READWRITE,
2845 tex->surface.nsamples > 1 ?
2846 RADEON_PRIO_COLOR_BUFFER_MSAA :
2847 RADEON_PRIO_COLOR_BUFFER);
2848
2849 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2850 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2851 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2852 RADEON_PRIO_CMASK);
2853 }
2854
2855 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2856 sctx->b.chip_class >= VI ? 14 : 13);
2857 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2858 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2859 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2860 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2861 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2862 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2863 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2864 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2865 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2866 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2867 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2868 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2869 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2870
2871 if (sctx->b.chip_class >= VI)
2872 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2873 }
2874 /* set CB_COLOR1_INFO for possible dual-src blending */
2875 if (i == 1 && state->cbufs[0] &&
2876 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2877 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2878 cb->cb_color_info | tex->cb_color_info);
2879 i++;
2880 }
2881 for (; i < 8 ; i++)
2882 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2883 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2884
2885 /* ZS buffer. */
2886 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2887 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2888 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2889
2890 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2891 &rtex->resource, RADEON_USAGE_READWRITE,
2892 zb->base.texture->nr_samples > 1 ?
2893 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2894 RADEON_PRIO_DEPTH_BUFFER);
2895
2896 if (zb->db_htile_data_base) {
2897 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2898 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2899 RADEON_PRIO_HTILE);
2900 }
2901
2902 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2903 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2904
2905 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2906 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2907 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2908 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2909 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2910 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2911 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2912 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2913 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2914 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2915 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2916
2917 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2918 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2919 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2920
2921 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2922 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2923 zb->pa_su_poly_offset_db_fmt_cntl);
2924 } else if (sctx->framebuffer.dirty_zsbuf) {
2925 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2926 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2927 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2928 }
2929
2930 /* Framebuffer dimensions. */
2931 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2932 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2933 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2934
2935 sctx->framebuffer.dirty_cbufs = 0;
2936 sctx->framebuffer.dirty_zsbuf = false;
2937 }
2938
2939 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2940 struct r600_atom *atom)
2941 {
2942 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2943 unsigned nr_samples = sctx->framebuffer.nr_samples;
2944
2945 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2946 SI_NUM_SMOOTH_AA_SAMPLES);
2947 }
2948
2949 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2950 {
2951 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2952
2953 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2954 sctx->ps_iter_samples,
2955 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2956 }
2957
2958
2959 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2960 {
2961 struct si_context *sctx = (struct si_context *)ctx;
2962
2963 if (sctx->ps_iter_samples == min_samples)
2964 return;
2965
2966 sctx->ps_iter_samples = min_samples;
2967
2968 if (sctx->framebuffer.nr_samples > 1)
2969 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2970 }
2971
2972 /*
2973 * Samplers
2974 */
2975
2976 /**
2977 * Build the sampler view descriptor for a buffer texture.
2978 * @param state 256-bit descriptor; only the high 128 bits are filled in
2979 */
2980 void
2981 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2982 enum pipe_format format,
2983 unsigned first_element, unsigned last_element,
2984 uint32_t *state)
2985 {
2986 const struct util_format_description *desc;
2987 int first_non_void;
2988 uint64_t va;
2989 unsigned stride;
2990 unsigned num_records;
2991 unsigned num_format, data_format;
2992
2993 desc = util_format_description(format);
2994 first_non_void = util_format_get_first_non_void_channel(format);
2995 stride = desc->block.bits / 8;
2996 va = buf->gpu_address + first_element * stride;
2997 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2998 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2999
3000 num_records = last_element + 1 - first_element;
3001 num_records = MIN2(num_records, buf->b.b.width0 / stride);
3002
3003 if (screen->b.chip_class >= VI)
3004 num_records *= stride;
3005
3006 state[4] = va;
3007 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
3008 S_008F04_STRIDE(stride);
3009 state[6] = num_records;
3010 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3011 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3012 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3013 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3014 S_008F0C_NUM_FORMAT(num_format) |
3015 S_008F0C_DATA_FORMAT(data_format);
3016 }
3017
3018 /**
3019 * Build the sampler view descriptor for a texture.
3020 */
3021 void
3022 si_make_texture_descriptor(struct si_screen *screen,
3023 struct r600_texture *tex,
3024 bool sampler,
3025 enum pipe_texture_target target,
3026 enum pipe_format pipe_format,
3027 const unsigned char state_swizzle[4],
3028 unsigned base_level, unsigned first_level, unsigned last_level,
3029 unsigned first_layer, unsigned last_layer,
3030 unsigned width, unsigned height, unsigned depth,
3031 uint32_t *state,
3032 uint32_t *fmask_state)
3033 {
3034 struct pipe_resource *res = &tex->resource.b.b;
3035 const struct radeon_surf_level *surflevel = tex->surface.level;
3036 const struct util_format_description *desc;
3037 unsigned char swizzle[4];
3038 int first_non_void;
3039 unsigned num_format, data_format, type;
3040 uint32_t pitch;
3041 uint64_t va;
3042
3043 /* Texturing with separate depth and stencil. */
3044 if (tex->is_depth && !tex->is_flushing_texture) {
3045 switch (pipe_format) {
3046 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3047 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3048 break;
3049 case PIPE_FORMAT_X8Z24_UNORM:
3050 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3051 /* Z24 is always stored like this. */
3052 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3053 break;
3054 case PIPE_FORMAT_X24S8_UINT:
3055 case PIPE_FORMAT_S8X24_UINT:
3056 case PIPE_FORMAT_X32_S8X24_UINT:
3057 pipe_format = PIPE_FORMAT_S8_UINT;
3058 surflevel = tex->surface.stencil_level;
3059 break;
3060 default:;
3061 }
3062 }
3063
3064 desc = util_format_description(pipe_format);
3065
3066 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3067 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3068 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3069
3070 switch (pipe_format) {
3071 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3072 case PIPE_FORMAT_X24S8_UINT:
3073 case PIPE_FORMAT_X32_S8X24_UINT:
3074 case PIPE_FORMAT_X8Z24_UNORM:
3075 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3076 break;
3077 default:
3078 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3079 }
3080 } else {
3081 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3082 }
3083
3084 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3085
3086 switch (pipe_format) {
3087 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3088 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3089 break;
3090 default:
3091 if (first_non_void < 0) {
3092 if (util_format_is_compressed(pipe_format)) {
3093 switch (pipe_format) {
3094 case PIPE_FORMAT_DXT1_SRGB:
3095 case PIPE_FORMAT_DXT1_SRGBA:
3096 case PIPE_FORMAT_DXT3_SRGBA:
3097 case PIPE_FORMAT_DXT5_SRGBA:
3098 case PIPE_FORMAT_BPTC_SRGBA:
3099 case PIPE_FORMAT_ETC2_SRGB8:
3100 case PIPE_FORMAT_ETC2_SRGB8A1:
3101 case PIPE_FORMAT_ETC2_SRGBA8:
3102 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3103 break;
3104 case PIPE_FORMAT_RGTC1_SNORM:
3105 case PIPE_FORMAT_LATC1_SNORM:
3106 case PIPE_FORMAT_RGTC2_SNORM:
3107 case PIPE_FORMAT_LATC2_SNORM:
3108 case PIPE_FORMAT_ETC2_R11_SNORM:
3109 case PIPE_FORMAT_ETC2_RG11_SNORM:
3110 /* implies float, so use SNORM/UNORM to determine
3111 whether data is signed or not */
3112 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3113 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3114 break;
3115 default:
3116 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3117 break;
3118 }
3119 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3120 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3121 } else {
3122 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3123 }
3124 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3125 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3126 } else {
3127 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3128
3129 switch (desc->channel[first_non_void].type) {
3130 case UTIL_FORMAT_TYPE_FLOAT:
3131 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3132 break;
3133 case UTIL_FORMAT_TYPE_SIGNED:
3134 if (desc->channel[first_non_void].normalized)
3135 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3136 else if (desc->channel[first_non_void].pure_integer)
3137 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3138 else
3139 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3140 break;
3141 case UTIL_FORMAT_TYPE_UNSIGNED:
3142 if (desc->channel[first_non_void].normalized)
3143 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3144 else if (desc->channel[first_non_void].pure_integer)
3145 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3146 else
3147 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3148 }
3149 }
3150 }
3151
3152 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3153 if (data_format == ~0) {
3154 data_format = 0;
3155 }
3156
3157 if (!sampler &&
3158 (res->target == PIPE_TEXTURE_CUBE ||
3159 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3160 res->target == PIPE_TEXTURE_3D)) {
3161 /* For the purpose of shader images, treat cube maps and 3D
3162 * textures as 2D arrays. For 3D textures, the address
3163 * calculations for mipmaps are different, so we rely on the
3164 * caller to effectively disable mipmaps.
3165 */
3166 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3167
3168 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3169 } else {
3170 type = si_tex_dim(res->target, target, res->nr_samples);
3171 }
3172
3173 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3174 height = 1;
3175 depth = res->array_size;
3176 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3177 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3178 if (sampler || res->target != PIPE_TEXTURE_3D)
3179 depth = res->array_size;
3180 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3181 depth = res->array_size / 6;
3182
3183 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
3184 va = tex->resource.gpu_address + surflevel[base_level].offset;
3185
3186 state[0] = va >> 8;
3187 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
3188 S_008F14_DATA_FORMAT(data_format) |
3189 S_008F14_NUM_FORMAT(num_format));
3190 state[2] = (S_008F18_WIDTH(width - 1) |
3191 S_008F18_HEIGHT(height - 1));
3192 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3193 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3194 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3195 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3196 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3197 0 : first_level) |
3198 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3199 util_logbase2(res->nr_samples) :
3200 last_level) |
3201 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
3202 S_008F1C_POW2_PAD(res->last_level > 0) |
3203 S_008F1C_TYPE(type));
3204 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
3205 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
3206 S_008F24_LAST_ARRAY(last_layer));
3207
3208 if (tex->dcc_offset) {
3209 unsigned swap = r600_translate_colorswap(pipe_format);
3210
3211 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3212 state[7] = (tex->resource.gpu_address +
3213 tex->dcc_offset +
3214 surflevel[base_level].dcc_offset) >> 8;
3215 } else {
3216 state[6] = 0;
3217 state[7] = 0;
3218
3219 /* The last dword is unused by hw. The shader uses it to clear
3220 * bits in the first dword of sampler state.
3221 */
3222 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3223 if (first_level == last_level)
3224 state[7] = C_008F30_MAX_ANISO_RATIO;
3225 else
3226 state[7] = 0xffffffff;
3227 }
3228 }
3229
3230 /* Initialize the sampler view for FMASK. */
3231 if (tex->fmask.size) {
3232 uint32_t fmask_format;
3233
3234 va = tex->resource.gpu_address + tex->fmask.offset;
3235
3236 switch (res->nr_samples) {
3237 case 2:
3238 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3239 break;
3240 case 4:
3241 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3242 break;
3243 case 8:
3244 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3245 break;
3246 default:
3247 assert(0);
3248 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3249 }
3250
3251 fmask_state[0] = va >> 8;
3252 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3253 S_008F14_DATA_FORMAT(fmask_format) |
3254 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3255 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3256 S_008F18_HEIGHT(height - 1);
3257 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3258 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3259 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3260 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3261 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3262 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3263 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3264 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3265 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3266 S_008F24_LAST_ARRAY(last_layer);
3267 fmask_state[6] = 0;
3268 fmask_state[7] = 0;
3269 }
3270 }
3271
3272 /**
3273 * Create a sampler view.
3274 *
3275 * @param ctx context
3276 * @param texture texture
3277 * @param state sampler view template
3278 * @param width0 width0 override (for compressed textures as int)
3279 * @param height0 height0 override (for compressed textures as int)
3280 * @param force_level set the base address to the level (for compressed textures)
3281 */
3282 struct pipe_sampler_view *
3283 si_create_sampler_view_custom(struct pipe_context *ctx,
3284 struct pipe_resource *texture,
3285 const struct pipe_sampler_view *state,
3286 unsigned width0, unsigned height0,
3287 unsigned force_level)
3288 {
3289 struct si_context *sctx = (struct si_context*)ctx;
3290 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3291 struct r600_texture *tmp = (struct r600_texture*)texture;
3292 unsigned base_level, first_level, last_level;
3293 unsigned char state_swizzle[4];
3294 unsigned height, depth, width;
3295 unsigned last_layer = state->u.tex.last_layer;
3296
3297 if (!view)
3298 return NULL;
3299
3300 /* initialize base object */
3301 view->base = *state;
3302 view->base.texture = NULL;
3303 view->base.reference.count = 1;
3304 view->base.context = ctx;
3305
3306 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3307 if (!texture) {
3308 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3309 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3310 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3311 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3312 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3313 return &view->base;
3314 }
3315
3316 pipe_resource_reference(&view->base.texture, texture);
3317
3318 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3319 state->format == PIPE_FORMAT_S8X24_UINT ||
3320 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3321 state->format == PIPE_FORMAT_S8_UINT)
3322 view->is_stencil_sampler = true;
3323
3324 /* Buffer resource. */
3325 if (texture->target == PIPE_BUFFER) {
3326 si_make_buffer_descriptor(sctx->screen,
3327 (struct r600_resource *)texture,
3328 state->format,
3329 state->u.buf.first_element,
3330 state->u.buf.last_element,
3331 view->state);
3332
3333 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3334 return &view->base;
3335 }
3336
3337 state_swizzle[0] = state->swizzle_r;
3338 state_swizzle[1] = state->swizzle_g;
3339 state_swizzle[2] = state->swizzle_b;
3340 state_swizzle[3] = state->swizzle_a;
3341
3342 base_level = 0;
3343 first_level = state->u.tex.first_level;
3344 last_level = state->u.tex.last_level;
3345 width = width0;
3346 height = height0;
3347 depth = texture->depth0;
3348
3349 if (force_level) {
3350 assert(force_level == first_level &&
3351 force_level == last_level);
3352 base_level = force_level;
3353 first_level = 0;
3354 last_level = 0;
3355 width = u_minify(width, force_level);
3356 height = u_minify(height, force_level);
3357 depth = u_minify(depth, force_level);
3358 }
3359
3360 /* This is not needed if state trackers set last_layer correctly. */
3361 if (state->target == PIPE_TEXTURE_1D ||
3362 state->target == PIPE_TEXTURE_2D ||
3363 state->target == PIPE_TEXTURE_RECT ||
3364 state->target == PIPE_TEXTURE_CUBE)
3365 last_layer = state->u.tex.first_layer;
3366
3367 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3368 state->format, state_swizzle,
3369 base_level, first_level, last_level,
3370 state->u.tex.first_layer, last_layer,
3371 width, height, depth,
3372 view->state, view->fmask_state);
3373
3374 return &view->base;
3375 }
3376
3377 static struct pipe_sampler_view *
3378 si_create_sampler_view(struct pipe_context *ctx,
3379 struct pipe_resource *texture,
3380 const struct pipe_sampler_view *state)
3381 {
3382 return si_create_sampler_view_custom(ctx, texture, state,
3383 texture ? texture->width0 : 0,
3384 texture ? texture->height0 : 0, 0);
3385 }
3386
3387 static void si_sampler_view_destroy(struct pipe_context *ctx,
3388 struct pipe_sampler_view *state)
3389 {
3390 struct si_sampler_view *view = (struct si_sampler_view *)state;
3391
3392 if (state->texture && state->texture->target == PIPE_BUFFER)
3393 LIST_DELINIT(&view->list);
3394
3395 pipe_resource_reference(&state->texture, NULL);
3396 FREE(view);
3397 }
3398
3399 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3400 {
3401 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3402 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3403 (linear_filter &&
3404 (wrap == PIPE_TEX_WRAP_CLAMP ||
3405 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3406 }
3407
3408 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3409 {
3410 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3411 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3412
3413 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3414 state->border_color.ui[2] || state->border_color.ui[3]) &&
3415 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3416 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3417 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3418 }
3419
3420 static void *si_create_sampler_state(struct pipe_context *ctx,
3421 const struct pipe_sampler_state *state)
3422 {
3423 struct si_context *sctx = (struct si_context *)ctx;
3424 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3425 unsigned border_color_type, border_color_index = 0;
3426
3427 if (!rstate) {
3428 return NULL;
3429 }
3430
3431 if (!sampler_state_needs_border_color(state))
3432 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3433 else if (state->border_color.f[0] == 0 &&
3434 state->border_color.f[1] == 0 &&
3435 state->border_color.f[2] == 0 &&
3436 state->border_color.f[3] == 0)
3437 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3438 else if (state->border_color.f[0] == 0 &&
3439 state->border_color.f[1] == 0 &&
3440 state->border_color.f[2] == 0 &&
3441 state->border_color.f[3] == 1)
3442 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3443 else if (state->border_color.f[0] == 1 &&
3444 state->border_color.f[1] == 1 &&
3445 state->border_color.f[2] == 1 &&
3446 state->border_color.f[3] == 1)
3447 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3448 else {
3449 int i;
3450
3451 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3452
3453 /* Check if the border has been uploaded already. */
3454 for (i = 0; i < sctx->border_color_count; i++)
3455 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3456 sizeof(state->border_color)) == 0)
3457 break;
3458
3459 if (i >= SI_MAX_BORDER_COLORS) {
3460 /* Getting 4096 unique border colors is very unlikely. */
3461 fprintf(stderr, "radeonsi: The border color table is full. "
3462 "Any new border colors will be just black. "
3463 "Please file a bug.\n");
3464 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3465 } else {
3466 if (i == sctx->border_color_count) {
3467 /* Upload a new border color. */
3468 memcpy(&sctx->border_color_table[i], &state->border_color,
3469 sizeof(state->border_color));
3470 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3471 &state->border_color,
3472 sizeof(state->border_color));
3473 sctx->border_color_count++;
3474 }
3475
3476 border_color_index = i;
3477 }
3478 }
3479
3480 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3481 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3482 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3483 S_008F30_MAX_ANISO_RATIO(r600_tex_aniso_filter(state->max_anisotropy)) |
3484 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3485 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3486 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3487 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3488 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3489 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3490 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3491 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, state->max_anisotropy)) |
3492 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, state->max_anisotropy)) |
3493 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3494 S_008F38_MIP_POINT_PRECLAMP(1) |
3495 S_008F38_DISABLE_LSB_CEIL(1) |
3496 S_008F38_FILTER_PREC_FIX(1) |
3497 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3498 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3499 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3500 return rstate;
3501 }
3502
3503 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3504 {
3505 struct si_context *sctx = (struct si_context *)ctx;
3506
3507 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3508 return;
3509
3510 sctx->sample_mask.sample_mask = sample_mask;
3511 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3512 }
3513
3514 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3515 {
3516 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3517 unsigned mask = sctx->sample_mask.sample_mask;
3518
3519 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3520 radeon_emit(cs, mask | (mask << 16));
3521 radeon_emit(cs, mask | (mask << 16));
3522 }
3523
3524 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3525 {
3526 free(state);
3527 }
3528
3529 /*
3530 * Vertex elements & buffers
3531 */
3532
3533 static void *si_create_vertex_elements(struct pipe_context *ctx,
3534 unsigned count,
3535 const struct pipe_vertex_element *elements)
3536 {
3537 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3538 int i;
3539
3540 assert(count < SI_MAX_ATTRIBS);
3541 if (!v)
3542 return NULL;
3543
3544 v->count = count;
3545 for (i = 0; i < count; ++i) {
3546 const struct util_format_description *desc;
3547 unsigned data_format, num_format;
3548 int first_non_void;
3549
3550 desc = util_format_description(elements[i].src_format);
3551 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3552 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3553 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3554
3555 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3556 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3557 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3558 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3559 S_008F0C_NUM_FORMAT(num_format) |
3560 S_008F0C_DATA_FORMAT(data_format);
3561 v->format_size[i] = desc->block.bits / 8;
3562 }
3563 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3564
3565 return v;
3566 }
3567
3568 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3569 {
3570 struct si_context *sctx = (struct si_context *)ctx;
3571 struct si_vertex_element *v = (struct si_vertex_element*)state;
3572
3573 sctx->vertex_elements = v;
3574 sctx->vertex_buffers_dirty = true;
3575 }
3576
3577 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3578 {
3579 struct si_context *sctx = (struct si_context *)ctx;
3580
3581 if (sctx->vertex_elements == state)
3582 sctx->vertex_elements = NULL;
3583 FREE(state);
3584 }
3585
3586 static void si_set_vertex_buffers(struct pipe_context *ctx,
3587 unsigned start_slot, unsigned count,
3588 const struct pipe_vertex_buffer *buffers)
3589 {
3590 struct si_context *sctx = (struct si_context *)ctx;
3591 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3592 int i;
3593
3594 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3595
3596 if (buffers) {
3597 for (i = 0; i < count; i++) {
3598 const struct pipe_vertex_buffer *src = buffers + i;
3599 struct pipe_vertex_buffer *dsti = dst + i;
3600
3601 pipe_resource_reference(&dsti->buffer, src->buffer);
3602 dsti->buffer_offset = src->buffer_offset;
3603 dsti->stride = src->stride;
3604 r600_context_add_resource_size(ctx, src->buffer);
3605 }
3606 } else {
3607 for (i = 0; i < count; i++) {
3608 pipe_resource_reference(&dst[i].buffer, NULL);
3609 }
3610 }
3611 sctx->vertex_buffers_dirty = true;
3612 }
3613
3614 static void si_set_index_buffer(struct pipe_context *ctx,
3615 const struct pipe_index_buffer *ib)
3616 {
3617 struct si_context *sctx = (struct si_context *)ctx;
3618
3619 if (ib) {
3620 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3621 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3622 r600_context_add_resource_size(ctx, ib->buffer);
3623 } else {
3624 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3625 }
3626 }
3627
3628 /*
3629 * Misc
3630 */
3631 static void si_set_polygon_stipple(struct pipe_context *ctx,
3632 const struct pipe_poly_stipple *state)
3633 {
3634 struct si_context *sctx = (struct si_context *)ctx;
3635 struct pipe_resource *tex;
3636 struct pipe_sampler_view *view;
3637 bool is_zero = true;
3638 bool is_one = true;
3639 int i;
3640
3641 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3642 * the resource is NULL/invalid. Take advantage of this fact and skip
3643 * texture allocation if the stipple pattern is constant.
3644 *
3645 * This is an optimization for the common case when stippling isn't
3646 * used but set_polygon_stipple is still called by st/mesa.
3647 */
3648 for (i = 0; i < Elements(state->stipple); i++) {
3649 is_zero = is_zero && state->stipple[i] == 0;
3650 is_one = is_one && state->stipple[i] == 0xffffffff;
3651 }
3652
3653 if (is_zero || is_one) {
3654 struct pipe_sampler_view templ = {{0}};
3655
3656 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3657 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3658 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3659 /* The pattern should be inverted in the texture. */
3660 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3661
3662 view = ctx->create_sampler_view(ctx, NULL, &templ);
3663 } else {
3664 /* Create a new texture. */
3665 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3666 if (!tex)
3667 return;
3668
3669 view = util_pstipple_create_sampler_view(ctx, tex);
3670 pipe_resource_reference(&tex, NULL);
3671 }
3672
3673 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3674 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3675 pipe_sampler_view_reference(&view, NULL);
3676
3677 /* Bind the sampler state if needed. */
3678 if (!sctx->pstipple_sampler_state) {
3679 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3680 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3681 SI_POLY_STIPPLE_SAMPLER, 1,
3682 &sctx->pstipple_sampler_state);
3683 }
3684 }
3685
3686 static void si_set_tess_state(struct pipe_context *ctx,
3687 const float default_outer_level[4],
3688 const float default_inner_level[2])
3689 {
3690 struct si_context *sctx = (struct si_context *)ctx;
3691 struct pipe_constant_buffer cb;
3692 float array[8];
3693
3694 memcpy(array, default_outer_level, sizeof(float) * 4);
3695 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3696
3697 cb.buffer = NULL;
3698 cb.user_buffer = NULL;
3699 cb.buffer_size = sizeof(array);
3700
3701 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3702 (void*)array, sizeof(array),
3703 &cb.buffer_offset);
3704
3705 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3706 SI_DRIVER_STATE_CONST_BUF, &cb);
3707 pipe_resource_reference(&cb.buffer, NULL);
3708 }
3709
3710 static void si_texture_barrier(struct pipe_context *ctx)
3711 {
3712 struct si_context *sctx = (struct si_context *)ctx;
3713
3714 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3715 SI_CONTEXT_INV_GLOBAL_L2 |
3716 SI_CONTEXT_FLUSH_AND_INV_CB;
3717 }
3718
3719 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3720 {
3721 struct si_context *sctx = (struct si_context *)ctx;
3722
3723 /* Subsequent commands must wait for all shader invocations to
3724 * complete. */
3725 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
3726
3727 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3728 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3729 SI_CONTEXT_INV_VMEM_L1;
3730
3731 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3732 PIPE_BARRIER_SHADER_BUFFER |
3733 PIPE_BARRIER_TEXTURE |
3734 PIPE_BARRIER_IMAGE |
3735 PIPE_BARRIER_STREAMOUT_BUFFER)) {
3736 /* As far as I can tell, L1 contents are written back to L2
3737 * automatically at end of shader, but the contents of other
3738 * L1 caches might still be stale. */
3739 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3740 }
3741
3742 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3743 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3744
3745 /* Indices are read through TC L2 since VI. */
3746 if (sctx->screen->b.chip_class <= CIK)
3747 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3748 }
3749
3750 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3751 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3752
3753 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3754 PIPE_BARRIER_FRAMEBUFFER |
3755 PIPE_BARRIER_INDIRECT_BUFFER)) {
3756 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3757 *
3758 * We need to make sure that TC L1 & L2 are written back to
3759 * memory, because neither CPU accesses nor CB fetches consider
3760 * TC, but there's no need to invalidate any TC cache lines. */
3761 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3762 }
3763 }
3764
3765 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3766 {
3767 struct pipe_blend_state blend;
3768
3769 memset(&blend, 0, sizeof(blend));
3770 blend.independent_blend_enable = true;
3771 blend.rt[0].colormask = 0xf;
3772 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3773 }
3774
3775 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3776 bool include_draw_vbo)
3777 {
3778 si_need_cs_space((struct si_context*)ctx);
3779 }
3780
3781 static void si_init_config(struct si_context *sctx);
3782
3783 void si_init_state_functions(struct si_context *sctx)
3784 {
3785 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3786 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3787 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3788
3789 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3790 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3791 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3792 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3793 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3794 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3795 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3796 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3797 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3798 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3799 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3800 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3801 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3802
3803 sctx->b.b.create_blend_state = si_create_blend_state;
3804 sctx->b.b.bind_blend_state = si_bind_blend_state;
3805 sctx->b.b.delete_blend_state = si_delete_blend_state;
3806 sctx->b.b.set_blend_color = si_set_blend_color;
3807
3808 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3809 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3810 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3811
3812 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3813 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3814 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3815
3816 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3817 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3818 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3819 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3820 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3821
3822 sctx->b.b.set_clip_state = si_set_clip_state;
3823 sctx->b.b.set_scissor_states = si_set_scissor_states;
3824 sctx->b.b.set_viewport_states = si_set_viewport_states;
3825 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3826
3827 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3828 sctx->b.b.get_sample_position = cayman_get_sample_position;
3829
3830 sctx->b.b.create_sampler_state = si_create_sampler_state;
3831 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3832
3833 sctx->b.b.create_sampler_view = si_create_sampler_view;
3834 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3835
3836 sctx->b.b.set_sample_mask = si_set_sample_mask;
3837
3838 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3839 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3840 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3841 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3842 sctx->b.b.set_index_buffer = si_set_index_buffer;
3843
3844 sctx->b.b.texture_barrier = si_texture_barrier;
3845 sctx->b.b.memory_barrier = si_memory_barrier;
3846 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3847 sctx->b.b.set_min_samples = si_set_min_samples;
3848 sctx->b.b.set_tess_state = si_set_tess_state;
3849
3850 sctx->b.b.set_active_query_state = si_set_active_query_state;
3851 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3852 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3853
3854 sctx->b.b.draw_vbo = si_draw_vbo;
3855
3856 if (sctx->b.chip_class >= CIK) {
3857 sctx->b.dma_copy = cik_sdma_copy;
3858 } else {
3859 sctx->b.dma_copy = si_dma_copy;
3860 }
3861
3862 si_init_config(sctx);
3863 }
3864
3865 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3866 struct r600_texture *rtex,
3867 struct radeon_bo_metadata *md)
3868 {
3869 struct si_screen *sscreen = (struct si_screen*)rscreen;
3870 struct pipe_resource *res = &rtex->resource.b.b;
3871 static const unsigned char swizzle[] = {
3872 PIPE_SWIZZLE_RED,
3873 PIPE_SWIZZLE_GREEN,
3874 PIPE_SWIZZLE_BLUE,
3875 PIPE_SWIZZLE_ALPHA
3876 };
3877 uint32_t desc[8], i;
3878 bool is_array = util_resource_is_array_texture(res);
3879
3880 /* DRM 2.x.x doesn't support this. */
3881 if (rscreen->info.drm_major != 3)
3882 return;
3883
3884 assert(rtex->fmask.size == 0);
3885
3886 /* Metadata image format format version 1:
3887 * [0] = 1 (metadata format identifier)
3888 * [1] = (VENDOR_ID << 16) | PCI_ID
3889 * [2:9] = image descriptor for the whole resource
3890 * [2] is always 0, because the base address is cleared
3891 * [9] is the DCC offset bits [39:8] from the beginning of
3892 * the buffer
3893 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3894 */
3895
3896 md->metadata[0] = 1; /* metadata image format version 1 */
3897
3898 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3899 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3900
3901 si_make_texture_descriptor(sscreen, rtex, true,
3902 res->target, res->format,
3903 swizzle, 0, 0, res->last_level, 0,
3904 is_array ? res->array_size - 1 : 0,
3905 res->width0, res->height0, res->depth0,
3906 desc, NULL);
3907
3908 /* Clear the base address and set the relative DCC offset. */
3909 desc[0] = 0;
3910 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3911 desc[7] = rtex->dcc_offset >> 8;
3912
3913 /* Dwords [2:9] contain the image descriptor. */
3914 memcpy(&md->metadata[2], desc, sizeof(desc));
3915
3916 /* Dwords [10:..] contain the mipmap level offsets. */
3917 for (i = 0; i <= res->last_level; i++)
3918 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3919
3920 md->size_metadata = (11 + res->last_level) * 4;
3921 }
3922
3923 void si_init_screen_state_functions(struct si_screen *sscreen)
3924 {
3925 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3926 }
3927
3928 static void
3929 si_write_harvested_raster_configs(struct si_context *sctx,
3930 struct si_pm4_state *pm4,
3931 unsigned raster_config,
3932 unsigned raster_config_1)
3933 {
3934 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3935 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3936 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3937 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3938 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3939 unsigned rb_per_se = num_rb / num_se;
3940 unsigned se_mask[4];
3941 unsigned se;
3942
3943 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3944 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3945 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3946 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3947
3948 assert(num_se == 1 || num_se == 2 || num_se == 4);
3949 assert(sh_per_se == 1 || sh_per_se == 2);
3950 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3951
3952 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3953 * fields are for, so I'm leaving them as their default
3954 * values. */
3955
3956 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3957 (!se_mask[2] && !se_mask[3]))) {
3958 raster_config_1 &= C_028354_SE_PAIR_MAP;
3959
3960 if (!se_mask[0] && !se_mask[1]) {
3961 raster_config_1 |=
3962 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3963 } else {
3964 raster_config_1 |=
3965 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3966 }
3967 }
3968
3969 for (se = 0; se < num_se; se++) {
3970 unsigned raster_config_se = raster_config;
3971 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3972 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3973 int idx = (se / 2) * 2;
3974
3975 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3976 raster_config_se &= C_028350_SE_MAP;
3977
3978 if (!se_mask[idx]) {
3979 raster_config_se |=
3980 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3981 } else {
3982 raster_config_se |=
3983 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3984 }
3985 }
3986
3987 pkr0_mask &= rb_mask;
3988 pkr1_mask &= rb_mask;
3989 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3990 raster_config_se &= C_028350_PKR_MAP;
3991
3992 if (!pkr0_mask) {
3993 raster_config_se |=
3994 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3995 } else {
3996 raster_config_se |=
3997 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3998 }
3999 }
4000
4001 if (rb_per_se >= 2) {
4002 unsigned rb0_mask = 1 << (se * rb_per_se);
4003 unsigned rb1_mask = rb0_mask << 1;
4004
4005 rb0_mask &= rb_mask;
4006 rb1_mask &= rb_mask;
4007 if (!rb0_mask || !rb1_mask) {
4008 raster_config_se &= C_028350_RB_MAP_PKR0;
4009
4010 if (!rb0_mask) {
4011 raster_config_se |=
4012 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4013 } else {
4014 raster_config_se |=
4015 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4016 }
4017 }
4018
4019 if (rb_per_se > 2) {
4020 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4021 rb1_mask = rb0_mask << 1;
4022 rb0_mask &= rb_mask;
4023 rb1_mask &= rb_mask;
4024 if (!rb0_mask || !rb1_mask) {
4025 raster_config_se &= C_028350_RB_MAP_PKR1;
4026
4027 if (!rb0_mask) {
4028 raster_config_se |=
4029 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4030 } else {
4031 raster_config_se |=
4032 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4033 }
4034 }
4035 }
4036 }
4037
4038 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4039 if (sctx->b.chip_class < CIK)
4040 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4041 SE_INDEX(se) | SH_BROADCAST_WRITES |
4042 INSTANCE_BROADCAST_WRITES);
4043 else
4044 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4045 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4046 S_030800_INSTANCE_BROADCAST_WRITES(1));
4047 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4048 if (sctx->b.chip_class >= CIK)
4049 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4050 }
4051
4052 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4053 if (sctx->b.chip_class < CIK)
4054 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4055 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4056 INSTANCE_BROADCAST_WRITES);
4057 else
4058 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4059 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4060 S_030800_INSTANCE_BROADCAST_WRITES(1));
4061 }
4062
4063 static void si_init_config(struct si_context *sctx)
4064 {
4065 struct si_screen *sscreen = sctx->screen;
4066 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4067 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4068 unsigned raster_config, raster_config_1;
4069 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4070 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4071 int i;
4072
4073 if (!pm4)
4074 return;
4075
4076 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4077 si_pm4_cmd_add(pm4, 0x80000000);
4078 si_pm4_cmd_add(pm4, 0x80000000);
4079 si_pm4_cmd_end(pm4, false);
4080
4081 /* This enables pipeline stat & streamout queries.
4082 * They are only disabled by blits.
4083 */
4084 si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
4085 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
4086 EVENT_INDEX(0));
4087 si_pm4_cmd_end(pm4, false);
4088
4089 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4090 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4091
4092 /* FIXME calculate these values somehow ??? */
4093 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4094 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4095 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4096
4097 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4098 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4099
4100 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4101 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4102 if (sctx->b.chip_class < CIK)
4103 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4104 S_008A14_CLIP_VTX_REORDER_ENA(1));
4105
4106 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4107 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4108
4109 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4110
4111 for (i = 0; i < 16; i++) {
4112 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
4113 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
4114 }
4115
4116 switch (sctx->screen->b.family) {
4117 case CHIP_TAHITI:
4118 case CHIP_PITCAIRN:
4119 raster_config = 0x2a00126a;
4120 raster_config_1 = 0x00000000;
4121 break;
4122 case CHIP_VERDE:
4123 raster_config = 0x0000124a;
4124 raster_config_1 = 0x00000000;
4125 break;
4126 case CHIP_OLAND:
4127 raster_config = 0x00000082;
4128 raster_config_1 = 0x00000000;
4129 break;
4130 case CHIP_HAINAN:
4131 raster_config = 0x00000000;
4132 raster_config_1 = 0x00000000;
4133 break;
4134 case CHIP_BONAIRE:
4135 raster_config = 0x16000012;
4136 raster_config_1 = 0x00000000;
4137 break;
4138 case CHIP_HAWAII:
4139 raster_config = 0x3a00161a;
4140 raster_config_1 = 0x0000002e;
4141 break;
4142 case CHIP_FIJI:
4143 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4144 /* old kernels with old tiling config */
4145 raster_config = 0x16000012;
4146 raster_config_1 = 0x0000002a;
4147 } else {
4148 raster_config = 0x3a00161a;
4149 raster_config_1 = 0x0000002e;
4150 }
4151 break;
4152 case CHIP_POLARIS10:
4153 raster_config = 0x16000012;
4154 raster_config_1 = 0x0000002a;
4155 break;
4156 case CHIP_POLARIS11:
4157 raster_config = 0x16000012;
4158 raster_config_1 = 0x00000000;
4159 break;
4160 case CHIP_TONGA:
4161 raster_config = 0x16000012;
4162 raster_config_1 = 0x0000002a;
4163 break;
4164 case CHIP_ICELAND:
4165 raster_config = 0x00000002;
4166 raster_config_1 = 0x00000000;
4167 break;
4168 case CHIP_CARRIZO:
4169 raster_config = 0x00000002;
4170 raster_config_1 = 0x00000000;
4171 break;
4172 case CHIP_KAVERI:
4173 /* KV should be 0x00000002, but that causes problems with radeon */
4174 raster_config = 0x00000000; /* 0x00000002 */
4175 raster_config_1 = 0x00000000;
4176 break;
4177 case CHIP_KABINI:
4178 case CHIP_MULLINS:
4179 case CHIP_STONEY:
4180 raster_config = 0x00000000;
4181 raster_config_1 = 0x00000000;
4182 break;
4183 default:
4184 fprintf(stderr,
4185 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4186 raster_config = 0x00000000;
4187 raster_config_1 = 0x00000000;
4188 break;
4189 }
4190
4191 /* Always use the default config when all backends are enabled
4192 * (or when we failed to determine the enabled backends).
4193 */
4194 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4195 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4196 raster_config);
4197 if (sctx->b.chip_class >= CIK)
4198 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4199 raster_config_1);
4200 } else {
4201 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4202 }
4203
4204 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4205 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4206 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4207 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4208 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4209 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4210 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4211
4212 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4213 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
4214 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4215 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4216 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4217 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4218 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4219 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4220 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
4221 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
4222 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
4223
4224 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4225 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4226 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4227
4228 if (sctx->b.chip_class >= CIK) {
4229 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4230 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4231 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4232
4233 if (sscreen->b.info.num_good_compute_units /
4234 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4235 /* Too few available compute units per SH. Disallowing
4236 * VS to run on CU0 could hurt us more than late VS
4237 * allocation would help.
4238 *
4239 * LATE_ALLOC_VS = 2 is the highest safe number.
4240 */
4241 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4242 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4243 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4244 } else {
4245 /* Set LATE_ALLOC_VS == 31. It should be less than
4246 * the number of scratch waves. Limitations:
4247 * - VS can't execute on CU0.
4248 * - If HS writes outputs to LDS, LS can't execute on CU0.
4249 */
4250 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
4251 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4252 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4253 }
4254
4255 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4256 }
4257
4258 if (sctx->b.chip_class >= VI) {
4259 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4260 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4261 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4262 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4263 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4264 }
4265
4266 if (sctx->b.family == CHIP_STONEY)
4267 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4268
4269 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4270 if (sctx->b.chip_class >= CIK)
4271 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4272 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4273 RADEON_PRIO_BORDER_COLORS);
4274
4275 si_pm4_upload_indirect_buffer(sctx, pm4);
4276 sctx->init_config = pm4;
4277 }