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radeonsi: move DB_SHADER_CONTROL into db_render_state
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
39 #include "util/u_simple_shaders.h"
40
41 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
42 void (*emit)(struct si_context *ctx, struct r600_atom *state),
43 unsigned num_dw)
44 {
45 atom->emit = (void*)emit;
46 atom->num_dw = num_dw;
47 atom->dirty = false;
48 *list_elem = atom;
49 }
50
51 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
52 {
53 if (sscreen->b.chip_class == CIK &&
54 sscreen->b.info.cik_macrotile_mode_array_valid) {
55 unsigned index, tileb;
56
57 tileb = 8 * 8 * tex->surface.bpe;
58 tileb = MIN2(tex->surface.tile_split, tileb);
59
60 for (index = 0; tileb > 64; index++) {
61 tileb >>= 1;
62 }
63 assert(index < 16);
64
65 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
66 }
67
68 if (sscreen->b.chip_class == SI &&
69 sscreen->b.info.si_tile_mode_array_valid) {
70 /* Don't use stencil_tiling_index, because num_banks is always
71 * read from the depth mode. */
72 unsigned tile_mode_index = tex->surface.tiling_index[0];
73 assert(tile_mode_index < 32);
74
75 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
76 }
77
78 /* The old way. */
79 switch (sscreen->b.tiling_info.num_banks) {
80 case 2:
81 return V_02803C_ADDR_SURF_2_BANK;
82 case 4:
83 return V_02803C_ADDR_SURF_4_BANK;
84 case 8:
85 default:
86 return V_02803C_ADDR_SURF_8_BANK;
87 case 16:
88 return V_02803C_ADDR_SURF_16_BANK;
89 }
90 }
91
92 unsigned cik_tile_split(unsigned tile_split)
93 {
94 switch (tile_split) {
95 case 64:
96 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
97 break;
98 case 128:
99 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
100 break;
101 case 256:
102 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
103 break;
104 case 512:
105 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
106 break;
107 default:
108 case 1024:
109 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
110 break;
111 case 2048:
112 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
113 break;
114 case 4096:
115 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
116 break;
117 }
118 return tile_split;
119 }
120
121 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
122 {
123 switch (macro_tile_aspect) {
124 default:
125 case 1:
126 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
127 break;
128 case 2:
129 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
130 break;
131 case 4:
132 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
133 break;
134 case 8:
135 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
136 break;
137 }
138 return macro_tile_aspect;
139 }
140
141 unsigned cik_bank_wh(unsigned bankwh)
142 {
143 switch (bankwh) {
144 default:
145 case 1:
146 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
147 break;
148 case 2:
149 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
150 break;
151 case 4:
152 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
153 break;
154 case 8:
155 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
156 break;
157 }
158 return bankwh;
159 }
160
161 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
162 {
163 if (sscreen->b.info.si_tile_mode_array_valid) {
164 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
165
166 return G_009910_PIPE_CONFIG(gb_tile_mode);
167 }
168
169 /* This is probably broken for a lot of chips, but it's only used
170 * if the kernel cannot return the tile mode array for CIK. */
171 switch (sscreen->b.info.r600_num_tile_pipes) {
172 case 16:
173 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
174 case 8:
175 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
176 case 4:
177 default:
178 if (sscreen->b.info.r600_num_backends == 4)
179 return V_02803C_X_ADDR_SURF_P4_16X16;
180 else
181 return V_02803C_X_ADDR_SURF_P4_8X16;
182 case 2:
183 return V_02803C_ADDR_SURF_P2;
184 }
185 }
186
187 static unsigned si_map_swizzle(unsigned swizzle)
188 {
189 switch (swizzle) {
190 case UTIL_FORMAT_SWIZZLE_Y:
191 return V_008F0C_SQ_SEL_Y;
192 case UTIL_FORMAT_SWIZZLE_Z:
193 return V_008F0C_SQ_SEL_Z;
194 case UTIL_FORMAT_SWIZZLE_W:
195 return V_008F0C_SQ_SEL_W;
196 case UTIL_FORMAT_SWIZZLE_0:
197 return V_008F0C_SQ_SEL_0;
198 case UTIL_FORMAT_SWIZZLE_1:
199 return V_008F0C_SQ_SEL_1;
200 default: /* UTIL_FORMAT_SWIZZLE_X */
201 return V_008F0C_SQ_SEL_X;
202 }
203 }
204
205 static uint32_t S_FIXED(float value, uint32_t frac_bits)
206 {
207 return value * (1 << frac_bits);
208 }
209
210 /* 12.4 fixed-point */
211 static unsigned si_pack_float_12p4(float x)
212 {
213 return x <= 0 ? 0 :
214 x >= 4096 ? 0xffff : x * 16;
215 }
216
217 /*
218 * inferred framebuffer and blender state
219 */
220 static void si_update_fb_blend_state(struct si_context *sctx)
221 {
222 struct si_pm4_state *pm4;
223 struct si_state_blend *blend = sctx->queued.named.blend;
224 uint32_t mask;
225
226 if (blend == NULL)
227 return;
228
229 pm4 = si_pm4_alloc_state(sctx);
230 if (pm4 == NULL)
231 return;
232
233 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
234 mask &= blend->cb_target_mask;
235 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
236
237 si_pm4_set_state(sctx, fb_blend, pm4);
238 }
239
240 /*
241 * Blender functions
242 */
243
244 static uint32_t si_translate_blend_function(int blend_func)
245 {
246 switch (blend_func) {
247 case PIPE_BLEND_ADD:
248 return V_028780_COMB_DST_PLUS_SRC;
249 case PIPE_BLEND_SUBTRACT:
250 return V_028780_COMB_SRC_MINUS_DST;
251 case PIPE_BLEND_REVERSE_SUBTRACT:
252 return V_028780_COMB_DST_MINUS_SRC;
253 case PIPE_BLEND_MIN:
254 return V_028780_COMB_MIN_DST_SRC;
255 case PIPE_BLEND_MAX:
256 return V_028780_COMB_MAX_DST_SRC;
257 default:
258 R600_ERR("Unknown blend function %d\n", blend_func);
259 assert(0);
260 break;
261 }
262 return 0;
263 }
264
265 static uint32_t si_translate_blend_factor(int blend_fact)
266 {
267 switch (blend_fact) {
268 case PIPE_BLENDFACTOR_ONE:
269 return V_028780_BLEND_ONE;
270 case PIPE_BLENDFACTOR_SRC_COLOR:
271 return V_028780_BLEND_SRC_COLOR;
272 case PIPE_BLENDFACTOR_SRC_ALPHA:
273 return V_028780_BLEND_SRC_ALPHA;
274 case PIPE_BLENDFACTOR_DST_ALPHA:
275 return V_028780_BLEND_DST_ALPHA;
276 case PIPE_BLENDFACTOR_DST_COLOR:
277 return V_028780_BLEND_DST_COLOR;
278 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
279 return V_028780_BLEND_SRC_ALPHA_SATURATE;
280 case PIPE_BLENDFACTOR_CONST_COLOR:
281 return V_028780_BLEND_CONSTANT_COLOR;
282 case PIPE_BLENDFACTOR_CONST_ALPHA:
283 return V_028780_BLEND_CONSTANT_ALPHA;
284 case PIPE_BLENDFACTOR_ZERO:
285 return V_028780_BLEND_ZERO;
286 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
287 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
288 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
289 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
291 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
292 case PIPE_BLENDFACTOR_INV_DST_COLOR:
293 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
294 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
295 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
296 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
297 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
298 case PIPE_BLENDFACTOR_SRC1_COLOR:
299 return V_028780_BLEND_SRC1_COLOR;
300 case PIPE_BLENDFACTOR_SRC1_ALPHA:
301 return V_028780_BLEND_SRC1_ALPHA;
302 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
303 return V_028780_BLEND_INV_SRC1_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
305 return V_028780_BLEND_INV_SRC1_ALPHA;
306 default:
307 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
308 assert(0);
309 break;
310 }
311 return 0;
312 }
313
314 static void *si_create_blend_state_mode(struct pipe_context *ctx,
315 const struct pipe_blend_state *state,
316 unsigned mode)
317 {
318 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
319 struct si_pm4_state *pm4 = &blend->pm4;
320
321 uint32_t color_control = 0;
322
323 if (blend == NULL)
324 return NULL;
325
326 blend->alpha_to_one = state->alpha_to_one;
327
328 if (state->logicop_enable) {
329 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
330 } else {
331 color_control |= S_028808_ROP3(0xcc);
332 }
333
334 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
335 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
336 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
337 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
338 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
339 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
340
341 blend->cb_target_mask = 0;
342 for (int i = 0; i < 8; i++) {
343 /* state->rt entries > 0 only written if independent blending */
344 const int j = state->independent_blend_enable ? i : 0;
345
346 unsigned eqRGB = state->rt[j].rgb_func;
347 unsigned srcRGB = state->rt[j].rgb_src_factor;
348 unsigned dstRGB = state->rt[j].rgb_dst_factor;
349 unsigned eqA = state->rt[j].alpha_func;
350 unsigned srcA = state->rt[j].alpha_src_factor;
351 unsigned dstA = state->rt[j].alpha_dst_factor;
352
353 unsigned blend_cntl = 0;
354
355 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
356 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
357
358 if (!state->rt[j].blend_enable) {
359 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
360 continue;
361 }
362
363 blend_cntl |= S_028780_ENABLE(1);
364 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
365 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
366 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
367
368 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
369 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
370 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
371 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
372 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
373 }
374 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
375 }
376
377 if (blend->cb_target_mask) {
378 color_control |= S_028808_MODE(mode);
379 } else {
380 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
381 }
382 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
383
384 return blend;
385 }
386
387 static void *si_create_blend_state(struct pipe_context *ctx,
388 const struct pipe_blend_state *state)
389 {
390 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
391 }
392
393 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
394 {
395 struct si_context *sctx = (struct si_context *)ctx;
396 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
397 si_update_fb_blend_state(sctx);
398 }
399
400 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
401 {
402 struct si_context *sctx = (struct si_context *)ctx;
403 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
404 }
405
406 static void si_set_blend_color(struct pipe_context *ctx,
407 const struct pipe_blend_color *state)
408 {
409 struct si_context *sctx = (struct si_context *)ctx;
410 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
411
412 if (pm4 == NULL)
413 return;
414
415 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
416 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
417 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
418 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
419
420 si_pm4_set_state(sctx, blend_color, pm4);
421 }
422
423 /*
424 * Clipping, scissors and viewport
425 */
426
427 static void si_set_clip_state(struct pipe_context *ctx,
428 const struct pipe_clip_state *state)
429 {
430 struct si_context *sctx = (struct si_context *)ctx;
431 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
432 struct pipe_constant_buffer cb;
433
434 if (pm4 == NULL)
435 return;
436
437 for (int i = 0; i < 6; i++) {
438 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
439 fui(state->ucp[i][0]));
440 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
441 fui(state->ucp[i][1]));
442 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
443 fui(state->ucp[i][2]));
444 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
445 fui(state->ucp[i][3]));
446 }
447
448 cb.buffer = NULL;
449 cb.user_buffer = state->ucp;
450 cb.buffer_offset = 0;
451 cb.buffer_size = 4*4*8;
452 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
453 pipe_resource_reference(&cb.buffer, NULL);
454
455 si_pm4_set_state(sctx, clip, pm4);
456 }
457
458 static void si_set_scissor_states(struct pipe_context *ctx,
459 unsigned start_slot,
460 unsigned num_scissors,
461 const struct pipe_scissor_state *state)
462 {
463 struct si_context *sctx = (struct si_context *)ctx;
464 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
465 struct si_pm4_state *pm4 = &scissor->pm4;
466
467 if (scissor == NULL)
468 return;
469
470 scissor->scissor = *state;
471 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
472 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
473 S_028250_WINDOW_OFFSET_DISABLE(1));
474 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
475 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
476
477 si_pm4_set_state(sctx, scissor, scissor);
478 }
479
480 static void si_set_viewport_states(struct pipe_context *ctx,
481 unsigned start_slot,
482 unsigned num_viewports,
483 const struct pipe_viewport_state *state)
484 {
485 struct si_context *sctx = (struct si_context *)ctx;
486 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
487 struct si_pm4_state *pm4 = &viewport->pm4;
488
489 if (viewport == NULL)
490 return;
491
492 viewport->viewport = *state;
493 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
494 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
495 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
496 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
497 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
498 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
499
500 si_pm4_set_state(sctx, viewport, viewport);
501 }
502
503 /*
504 * inferred state between framebuffer and rasterizer
505 */
506 static void si_update_fb_rs_state(struct si_context *sctx)
507 {
508 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
509 struct si_pm4_state *pm4;
510 float offset_units;
511
512 if (!rs || !sctx->framebuffer.state.zsbuf)
513 return;
514
515 offset_units = sctx->queued.named.rasterizer->offset_units;
516 switch (sctx->framebuffer.state.zsbuf->texture->format) {
517 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
518 case PIPE_FORMAT_X8Z24_UNORM:
519 case PIPE_FORMAT_Z24X8_UNORM:
520 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
521 offset_units *= 2.0f;
522 break;
523 case PIPE_FORMAT_Z32_FLOAT:
524 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
525 offset_units *= 1.0f;
526 break;
527 case PIPE_FORMAT_Z16_UNORM:
528 offset_units *= 4.0f;
529 break;
530 default:
531 return;
532 }
533
534 pm4 = si_pm4_alloc_state(sctx);
535
536 if (pm4 == NULL)
537 return;
538
539 /* FIXME some of those reg can be computed with cso */
540 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
541 fui(sctx->queued.named.rasterizer->offset_scale));
542 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
543 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
544 fui(sctx->queued.named.rasterizer->offset_scale));
545 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
546
547 si_pm4_set_state(sctx, fb_rs, pm4);
548 }
549
550 /*
551 * Rasterizer
552 */
553
554 static uint32_t si_translate_fill(uint32_t func)
555 {
556 switch(func) {
557 case PIPE_POLYGON_MODE_FILL:
558 return V_028814_X_DRAW_TRIANGLES;
559 case PIPE_POLYGON_MODE_LINE:
560 return V_028814_X_DRAW_LINES;
561 case PIPE_POLYGON_MODE_POINT:
562 return V_028814_X_DRAW_POINTS;
563 default:
564 assert(0);
565 return V_028814_X_DRAW_POINTS;
566 }
567 }
568
569 static void *si_create_rs_state(struct pipe_context *ctx,
570 const struct pipe_rasterizer_state *state)
571 {
572 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
573 struct si_pm4_state *pm4 = &rs->pm4;
574 unsigned tmp;
575 unsigned prov_vtx = 1, polygon_dual_mode;
576 float psize_min, psize_max;
577
578 if (rs == NULL) {
579 return NULL;
580 }
581
582 rs->two_side = state->light_twoside;
583 rs->multisample_enable = state->multisample;
584 rs->clip_plane_enable = state->clip_plane_enable;
585 rs->line_stipple_enable = state->line_stipple_enable;
586
587 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
588 state->fill_back != PIPE_POLYGON_MODE_FILL);
589
590 if (state->flatshade_first)
591 prov_vtx = 0;
592
593 rs->flatshade = state->flatshade;
594 rs->sprite_coord_enable = state->sprite_coord_enable;
595 rs->pa_sc_line_stipple = state->line_stipple_enable ?
596 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
597 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
598 rs->pa_su_sc_mode_cntl =
599 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
600 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
601 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
602 S_028814_FACE(!state->front_ccw) |
603 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
604 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
605 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
606 S_028814_POLY_MODE(polygon_dual_mode) |
607 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
608 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
609 rs->pa_cl_clip_cntl =
610 S_028810_PS_UCP_MODE(3) |
611 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
612 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
613 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
614 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
615
616 /* offset */
617 rs->offset_units = state->offset_units;
618 rs->offset_scale = state->offset_scale * 12.0f;
619
620 tmp = S_0286D4_FLAT_SHADE_ENA(1);
621 if (state->sprite_coord_enable) {
622 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
623 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
624 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
625 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
626 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
627 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
628 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
629 }
630 }
631 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
632
633 /* point size 12.4 fixed point */
634 tmp = (unsigned)(state->point_size * 8.0);
635 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
636
637 if (state->point_size_per_vertex) {
638 psize_min = util_get_min_point_size(state);
639 psize_max = 8192;
640 } else {
641 /* Force the point size to be as if the vertex output was disabled. */
642 psize_min = state->point_size;
643 psize_max = state->point_size;
644 }
645 /* Divide by two, because 0.5 = 1 pixel. */
646 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
647 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
648 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
649
650 tmp = (unsigned)state->line_width * 8;
651 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
652 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
653 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
654 S_028A48_MSAA_ENABLE(state->multisample) |
655 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
656
657 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
658 S_028BE4_PIX_CENTER(state->half_pixel_center) |
659 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
660
661 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
662
663 return rs;
664 }
665
666 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
667 {
668 struct si_context *sctx = (struct si_context *)ctx;
669 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
670
671 if (state == NULL)
672 return;
673
674 // TODO
675 sctx->sprite_coord_enable = rs->sprite_coord_enable;
676 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
677 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
678
679 si_pm4_bind_state(sctx, rasterizer, rs);
680 si_update_fb_rs_state(sctx);
681 }
682
683 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
684 {
685 struct si_context *sctx = (struct si_context *)ctx;
686 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
687 }
688
689 /*
690 * infeered state between dsa and stencil ref
691 */
692 static void si_update_dsa_stencil_ref(struct si_context *sctx)
693 {
694 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
695 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
696 struct si_state_dsa *dsa = sctx->queued.named.dsa;
697
698 if (pm4 == NULL)
699 return;
700
701 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
702 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
703 S_028430_STENCILMASK(dsa->valuemask[0]) |
704 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
705 S_028430_STENCILOPVAL(1));
706 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
707 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
708 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
709 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
710 S_028434_STENCILOPVAL_BF(1));
711
712 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
713 }
714
715 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
716 const struct pipe_stencil_ref *state)
717 {
718 struct si_context *sctx = (struct si_context *)ctx;
719 sctx->stencil_ref = *state;
720 si_update_dsa_stencil_ref(sctx);
721 }
722
723
724 /*
725 * DSA
726 */
727
728 static uint32_t si_translate_stencil_op(int s_op)
729 {
730 switch (s_op) {
731 case PIPE_STENCIL_OP_KEEP:
732 return V_02842C_STENCIL_KEEP;
733 case PIPE_STENCIL_OP_ZERO:
734 return V_02842C_STENCIL_ZERO;
735 case PIPE_STENCIL_OP_REPLACE:
736 return V_02842C_STENCIL_REPLACE_TEST;
737 case PIPE_STENCIL_OP_INCR:
738 return V_02842C_STENCIL_ADD_CLAMP;
739 case PIPE_STENCIL_OP_DECR:
740 return V_02842C_STENCIL_SUB_CLAMP;
741 case PIPE_STENCIL_OP_INCR_WRAP:
742 return V_02842C_STENCIL_ADD_WRAP;
743 case PIPE_STENCIL_OP_DECR_WRAP:
744 return V_02842C_STENCIL_SUB_WRAP;
745 case PIPE_STENCIL_OP_INVERT:
746 return V_02842C_STENCIL_INVERT;
747 default:
748 R600_ERR("Unknown stencil op %d", s_op);
749 assert(0);
750 break;
751 }
752 return 0;
753 }
754
755 static void *si_create_dsa_state(struct pipe_context *ctx,
756 const struct pipe_depth_stencil_alpha_state *state)
757 {
758 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
759 struct si_pm4_state *pm4 = &dsa->pm4;
760 unsigned db_depth_control;
761 uint32_t db_stencil_control = 0;
762
763 if (dsa == NULL) {
764 return NULL;
765 }
766
767 dsa->valuemask[0] = state->stencil[0].valuemask;
768 dsa->valuemask[1] = state->stencil[1].valuemask;
769 dsa->writemask[0] = state->stencil[0].writemask;
770 dsa->writemask[1] = state->stencil[1].writemask;
771
772 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
773 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
774 S_028800_ZFUNC(state->depth.func);
775
776 /* stencil */
777 if (state->stencil[0].enabled) {
778 db_depth_control |= S_028800_STENCIL_ENABLE(1);
779 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
780 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
781 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
782 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
783
784 if (state->stencil[1].enabled) {
785 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
786 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
787 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
788 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
789 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
790 }
791 }
792
793 /* alpha */
794 if (state->alpha.enabled) {
795 dsa->alpha_func = state->alpha.func;
796 dsa->alpha_ref = state->alpha.ref_value;
797
798 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
799 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
800 } else {
801 dsa->alpha_func = PIPE_FUNC_ALWAYS;
802 }
803
804 /* misc */
805 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
806 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
807
808 return dsa;
809 }
810
811 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
812 {
813 struct si_context *sctx = (struct si_context *)ctx;
814 struct si_state_dsa *dsa = state;
815
816 if (state == NULL)
817 return;
818
819 si_pm4_bind_state(sctx, dsa, dsa);
820 si_update_dsa_stencil_ref(sctx);
821 }
822
823 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
824 {
825 struct si_context *sctx = (struct si_context *)ctx;
826 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
827 }
828
829 static void *si_create_db_flush_dsa(struct si_context *sctx)
830 {
831 struct pipe_depth_stencil_alpha_state dsa = {};
832
833 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
834 }
835
836 /* DB RENDER STATE */
837
838 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
839 {
840 struct si_context *sctx = (struct si_context*)ctx;
841
842 sctx->db_render_state.dirty = true;
843 }
844
845 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
846 {
847 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
848
849 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
850
851 /* DB_RENDER_CONTROL */
852 if (sctx->dbcb_depth_copy_enabled ||
853 sctx->dbcb_stencil_copy_enabled) {
854 radeon_emit(cs,
855 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
856 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
857 S_028000_COPY_CENTROID(1) |
858 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
859 } else if (sctx->db_inplace_flush_enabled) {
860 radeon_emit(cs,
861 S_028000_DEPTH_COMPRESS_DISABLE(1) |
862 S_028000_STENCIL_COMPRESS_DISABLE(1));
863 } else if (sctx->db_depth_clear) {
864 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
865 } else {
866 radeon_emit(cs, 0);
867 }
868
869 /* DB_COUNT_CONTROL (occlusion queries) */
870 if (sctx->b.num_occlusion_queries > 0) {
871 if (sctx->b.chip_class >= CIK) {
872 radeon_emit(cs,
873 S_028004_PERFECT_ZPASS_COUNTS(1) |
874 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
875 S_028004_ZPASS_ENABLE(1) |
876 S_028004_SLICE_EVEN_ENABLE(1) |
877 S_028004_SLICE_ODD_ENABLE(1));
878 } else {
879 radeon_emit(cs,
880 S_028004_PERFECT_ZPASS_COUNTS(1) |
881 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
882 }
883 } else {
884 /* Disable occlusion queries. */
885 if (sctx->b.chip_class >= CIK) {
886 radeon_emit(cs, 0);
887 } else {
888 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
889 }
890 }
891
892 /* DB_RENDER_OVERRIDE2 */
893 if (sctx->db_depth_disable_expclear) {
894 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
895 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
896 } else {
897 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
898 }
899
900 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
901 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
902 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
903 sctx->ps_db_shader_control);
904 }
905
906 /*
907 * format translation
908 */
909 static uint32_t si_translate_colorformat(enum pipe_format format)
910 {
911 const struct util_format_description *desc = util_format_description(format);
912
913 #define HAS_SIZE(x,y,z,w) \
914 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
915 desc->channel[2].size == (z) && desc->channel[3].size == (w))
916
917 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
918 return V_028C70_COLOR_10_11_11;
919
920 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
921 return V_028C70_COLOR_INVALID;
922
923 switch (desc->nr_channels) {
924 case 1:
925 switch (desc->channel[0].size) {
926 case 8:
927 return V_028C70_COLOR_8;
928 case 16:
929 return V_028C70_COLOR_16;
930 case 32:
931 return V_028C70_COLOR_32;
932 }
933 break;
934 case 2:
935 if (desc->channel[0].size == desc->channel[1].size) {
936 switch (desc->channel[0].size) {
937 case 8:
938 return V_028C70_COLOR_8_8;
939 case 16:
940 return V_028C70_COLOR_16_16;
941 case 32:
942 return V_028C70_COLOR_32_32;
943 }
944 } else if (HAS_SIZE(8,24,0,0)) {
945 return V_028C70_COLOR_24_8;
946 } else if (HAS_SIZE(24,8,0,0)) {
947 return V_028C70_COLOR_8_24;
948 }
949 break;
950 case 3:
951 if (HAS_SIZE(5,6,5,0)) {
952 return V_028C70_COLOR_5_6_5;
953 } else if (HAS_SIZE(32,8,24,0)) {
954 return V_028C70_COLOR_X24_8_32_FLOAT;
955 }
956 break;
957 case 4:
958 if (desc->channel[0].size == desc->channel[1].size &&
959 desc->channel[0].size == desc->channel[2].size &&
960 desc->channel[0].size == desc->channel[3].size) {
961 switch (desc->channel[0].size) {
962 case 4:
963 return V_028C70_COLOR_4_4_4_4;
964 case 8:
965 return V_028C70_COLOR_8_8_8_8;
966 case 16:
967 return V_028C70_COLOR_16_16_16_16;
968 case 32:
969 return V_028C70_COLOR_32_32_32_32;
970 }
971 } else if (HAS_SIZE(5,5,5,1)) {
972 return V_028C70_COLOR_1_5_5_5;
973 } else if (HAS_SIZE(10,10,10,2)) {
974 return V_028C70_COLOR_2_10_10_10;
975 }
976 break;
977 }
978 return V_028C70_COLOR_INVALID;
979 }
980
981 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
982 {
983 if (SI_BIG_ENDIAN) {
984 switch(colorformat) {
985 /* 8-bit buffers. */
986 case V_028C70_COLOR_8:
987 return V_028C70_ENDIAN_NONE;
988
989 /* 16-bit buffers. */
990 case V_028C70_COLOR_5_6_5:
991 case V_028C70_COLOR_1_5_5_5:
992 case V_028C70_COLOR_4_4_4_4:
993 case V_028C70_COLOR_16:
994 case V_028C70_COLOR_8_8:
995 return V_028C70_ENDIAN_8IN16;
996
997 /* 32-bit buffers. */
998 case V_028C70_COLOR_8_8_8_8:
999 case V_028C70_COLOR_2_10_10_10:
1000 case V_028C70_COLOR_8_24:
1001 case V_028C70_COLOR_24_8:
1002 case V_028C70_COLOR_16_16:
1003 return V_028C70_ENDIAN_8IN32;
1004
1005 /* 64-bit buffers. */
1006 case V_028C70_COLOR_16_16_16_16:
1007 return V_028C70_ENDIAN_8IN16;
1008
1009 case V_028C70_COLOR_32_32:
1010 return V_028C70_ENDIAN_8IN32;
1011
1012 /* 128-bit buffers. */
1013 case V_028C70_COLOR_32_32_32_32:
1014 return V_028C70_ENDIAN_8IN32;
1015 default:
1016 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1017 }
1018 } else {
1019 return V_028C70_ENDIAN_NONE;
1020 }
1021 }
1022
1023 /* Returns the size in bits of the widest component of a CB format */
1024 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1025 {
1026 switch(colorformat) {
1027 case V_028C70_COLOR_4_4_4_4:
1028 return 4;
1029
1030 case V_028C70_COLOR_1_5_5_5:
1031 case V_028C70_COLOR_5_5_5_1:
1032 return 5;
1033
1034 case V_028C70_COLOR_5_6_5:
1035 return 6;
1036
1037 case V_028C70_COLOR_8:
1038 case V_028C70_COLOR_8_8:
1039 case V_028C70_COLOR_8_8_8_8:
1040 return 8;
1041
1042 case V_028C70_COLOR_10_10_10_2:
1043 case V_028C70_COLOR_2_10_10_10:
1044 return 10;
1045
1046 case V_028C70_COLOR_10_11_11:
1047 case V_028C70_COLOR_11_11_10:
1048 return 11;
1049
1050 case V_028C70_COLOR_16:
1051 case V_028C70_COLOR_16_16:
1052 case V_028C70_COLOR_16_16_16_16:
1053 return 16;
1054
1055 case V_028C70_COLOR_8_24:
1056 case V_028C70_COLOR_24_8:
1057 return 24;
1058
1059 case V_028C70_COLOR_32:
1060 case V_028C70_COLOR_32_32:
1061 case V_028C70_COLOR_32_32_32_32:
1062 case V_028C70_COLOR_X24_8_32_FLOAT:
1063 return 32;
1064 }
1065
1066 assert(!"Unknown maximum component size");
1067 return 0;
1068 }
1069
1070 static uint32_t si_translate_dbformat(enum pipe_format format)
1071 {
1072 switch (format) {
1073 case PIPE_FORMAT_Z16_UNORM:
1074 return V_028040_Z_16;
1075 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1076 case PIPE_FORMAT_X8Z24_UNORM:
1077 case PIPE_FORMAT_Z24X8_UNORM:
1078 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1079 return V_028040_Z_24; /* deprecated on SI */
1080 case PIPE_FORMAT_Z32_FLOAT:
1081 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1082 return V_028040_Z_32_FLOAT;
1083 default:
1084 return V_028040_Z_INVALID;
1085 }
1086 }
1087
1088 /*
1089 * Texture translation
1090 */
1091
1092 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1093 enum pipe_format format,
1094 const struct util_format_description *desc,
1095 int first_non_void)
1096 {
1097 struct si_screen *sscreen = (struct si_screen*)screen;
1098 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1099 boolean uniform = TRUE;
1100 int i;
1101
1102 /* Colorspace (return non-RGB formats directly). */
1103 switch (desc->colorspace) {
1104 /* Depth stencil formats */
1105 case UTIL_FORMAT_COLORSPACE_ZS:
1106 switch (format) {
1107 case PIPE_FORMAT_Z16_UNORM:
1108 return V_008F14_IMG_DATA_FORMAT_16;
1109 case PIPE_FORMAT_X24S8_UINT:
1110 case PIPE_FORMAT_Z24X8_UNORM:
1111 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1112 return V_008F14_IMG_DATA_FORMAT_8_24;
1113 case PIPE_FORMAT_X8Z24_UNORM:
1114 case PIPE_FORMAT_S8X24_UINT:
1115 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1116 return V_008F14_IMG_DATA_FORMAT_24_8;
1117 case PIPE_FORMAT_S8_UINT:
1118 return V_008F14_IMG_DATA_FORMAT_8;
1119 case PIPE_FORMAT_Z32_FLOAT:
1120 return V_008F14_IMG_DATA_FORMAT_32;
1121 case PIPE_FORMAT_X32_S8X24_UINT:
1122 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1123 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1124 default:
1125 goto out_unknown;
1126 }
1127
1128 case UTIL_FORMAT_COLORSPACE_YUV:
1129 goto out_unknown; /* TODO */
1130
1131 case UTIL_FORMAT_COLORSPACE_SRGB:
1132 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1133 goto out_unknown;
1134 break;
1135
1136 default:
1137 break;
1138 }
1139
1140 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1141 if (!enable_s3tc)
1142 goto out_unknown;
1143
1144 switch (format) {
1145 case PIPE_FORMAT_RGTC1_SNORM:
1146 case PIPE_FORMAT_LATC1_SNORM:
1147 case PIPE_FORMAT_RGTC1_UNORM:
1148 case PIPE_FORMAT_LATC1_UNORM:
1149 return V_008F14_IMG_DATA_FORMAT_BC4;
1150 case PIPE_FORMAT_RGTC2_SNORM:
1151 case PIPE_FORMAT_LATC2_SNORM:
1152 case PIPE_FORMAT_RGTC2_UNORM:
1153 case PIPE_FORMAT_LATC2_UNORM:
1154 return V_008F14_IMG_DATA_FORMAT_BC5;
1155 default:
1156 goto out_unknown;
1157 }
1158 }
1159
1160 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1161 if (!enable_s3tc)
1162 goto out_unknown;
1163
1164 switch (format) {
1165 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1166 case PIPE_FORMAT_BPTC_SRGBA:
1167 return V_008F14_IMG_DATA_FORMAT_BC7;
1168 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1169 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1170 return V_008F14_IMG_DATA_FORMAT_BC6;
1171 default:
1172 goto out_unknown;
1173 }
1174 }
1175
1176 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1177 switch (format) {
1178 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1179 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1180 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1181 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1182 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1183 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1184 default:
1185 goto out_unknown;
1186 }
1187 }
1188
1189 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1190
1191 if (!enable_s3tc)
1192 goto out_unknown;
1193
1194 if (!util_format_s3tc_enabled) {
1195 goto out_unknown;
1196 }
1197
1198 switch (format) {
1199 case PIPE_FORMAT_DXT1_RGB:
1200 case PIPE_FORMAT_DXT1_RGBA:
1201 case PIPE_FORMAT_DXT1_SRGB:
1202 case PIPE_FORMAT_DXT1_SRGBA:
1203 return V_008F14_IMG_DATA_FORMAT_BC1;
1204 case PIPE_FORMAT_DXT3_RGBA:
1205 case PIPE_FORMAT_DXT3_SRGBA:
1206 return V_008F14_IMG_DATA_FORMAT_BC2;
1207 case PIPE_FORMAT_DXT5_RGBA:
1208 case PIPE_FORMAT_DXT5_SRGBA:
1209 return V_008F14_IMG_DATA_FORMAT_BC3;
1210 default:
1211 goto out_unknown;
1212 }
1213 }
1214
1215 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1216 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1217 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1218 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1219 }
1220
1221 /* R8G8Bx_SNORM - TODO CxV8U8 */
1222
1223 /* See whether the components are of the same size. */
1224 for (i = 1; i < desc->nr_channels; i++) {
1225 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1226 }
1227
1228 /* Non-uniform formats. */
1229 if (!uniform) {
1230 switch(desc->nr_channels) {
1231 case 3:
1232 if (desc->channel[0].size == 5 &&
1233 desc->channel[1].size == 6 &&
1234 desc->channel[2].size == 5) {
1235 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1236 }
1237 goto out_unknown;
1238 case 4:
1239 if (desc->channel[0].size == 5 &&
1240 desc->channel[1].size == 5 &&
1241 desc->channel[2].size == 5 &&
1242 desc->channel[3].size == 1) {
1243 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1244 }
1245 if (desc->channel[0].size == 10 &&
1246 desc->channel[1].size == 10 &&
1247 desc->channel[2].size == 10 &&
1248 desc->channel[3].size == 2) {
1249 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1250 }
1251 goto out_unknown;
1252 }
1253 goto out_unknown;
1254 }
1255
1256 if (first_non_void < 0 || first_non_void > 3)
1257 goto out_unknown;
1258
1259 /* uniform formats */
1260 switch (desc->channel[first_non_void].size) {
1261 case 4:
1262 switch (desc->nr_channels) {
1263 #if 0 /* Not supported for render targets */
1264 case 2:
1265 return V_008F14_IMG_DATA_FORMAT_4_4;
1266 #endif
1267 case 4:
1268 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1269 }
1270 break;
1271 case 8:
1272 switch (desc->nr_channels) {
1273 case 1:
1274 return V_008F14_IMG_DATA_FORMAT_8;
1275 case 2:
1276 return V_008F14_IMG_DATA_FORMAT_8_8;
1277 case 4:
1278 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1279 }
1280 break;
1281 case 16:
1282 switch (desc->nr_channels) {
1283 case 1:
1284 return V_008F14_IMG_DATA_FORMAT_16;
1285 case 2:
1286 return V_008F14_IMG_DATA_FORMAT_16_16;
1287 case 4:
1288 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1289 }
1290 break;
1291 case 32:
1292 switch (desc->nr_channels) {
1293 case 1:
1294 return V_008F14_IMG_DATA_FORMAT_32;
1295 case 2:
1296 return V_008F14_IMG_DATA_FORMAT_32_32;
1297 #if 0 /* Not supported for render targets */
1298 case 3:
1299 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1300 #endif
1301 case 4:
1302 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1303 }
1304 }
1305
1306 out_unknown:
1307 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1308 return ~0;
1309 }
1310
1311 static unsigned si_tex_wrap(unsigned wrap)
1312 {
1313 switch (wrap) {
1314 default:
1315 case PIPE_TEX_WRAP_REPEAT:
1316 return V_008F30_SQ_TEX_WRAP;
1317 case PIPE_TEX_WRAP_CLAMP:
1318 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1319 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1320 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1321 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1322 return V_008F30_SQ_TEX_CLAMP_BORDER;
1323 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1324 return V_008F30_SQ_TEX_MIRROR;
1325 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1326 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1327 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1328 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1329 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1330 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1331 }
1332 }
1333
1334 static unsigned si_tex_filter(unsigned filter)
1335 {
1336 switch (filter) {
1337 default:
1338 case PIPE_TEX_FILTER_NEAREST:
1339 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1340 case PIPE_TEX_FILTER_LINEAR:
1341 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1342 }
1343 }
1344
1345 static unsigned si_tex_mipfilter(unsigned filter)
1346 {
1347 switch (filter) {
1348 case PIPE_TEX_MIPFILTER_NEAREST:
1349 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1350 case PIPE_TEX_MIPFILTER_LINEAR:
1351 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1352 default:
1353 case PIPE_TEX_MIPFILTER_NONE:
1354 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1355 }
1356 }
1357
1358 static unsigned si_tex_compare(unsigned compare)
1359 {
1360 switch (compare) {
1361 default:
1362 case PIPE_FUNC_NEVER:
1363 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1364 case PIPE_FUNC_LESS:
1365 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1366 case PIPE_FUNC_EQUAL:
1367 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1368 case PIPE_FUNC_LEQUAL:
1369 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1370 case PIPE_FUNC_GREATER:
1371 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1372 case PIPE_FUNC_NOTEQUAL:
1373 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1374 case PIPE_FUNC_GEQUAL:
1375 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1376 case PIPE_FUNC_ALWAYS:
1377 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1378 }
1379 }
1380
1381 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1382 {
1383 switch (dim) {
1384 default:
1385 case PIPE_TEXTURE_1D:
1386 return V_008F1C_SQ_RSRC_IMG_1D;
1387 case PIPE_TEXTURE_1D_ARRAY:
1388 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1389 case PIPE_TEXTURE_2D:
1390 case PIPE_TEXTURE_RECT:
1391 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1392 V_008F1C_SQ_RSRC_IMG_2D;
1393 case PIPE_TEXTURE_2D_ARRAY:
1394 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1395 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1396 case PIPE_TEXTURE_3D:
1397 return V_008F1C_SQ_RSRC_IMG_3D;
1398 case PIPE_TEXTURE_CUBE:
1399 case PIPE_TEXTURE_CUBE_ARRAY:
1400 return V_008F1C_SQ_RSRC_IMG_CUBE;
1401 }
1402 }
1403
1404 /*
1405 * Format support testing
1406 */
1407
1408 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1409 {
1410 return si_translate_texformat(screen, format, util_format_description(format),
1411 util_format_get_first_non_void_channel(format)) != ~0U;
1412 }
1413
1414 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1415 const struct util_format_description *desc,
1416 int first_non_void)
1417 {
1418 unsigned type = desc->channel[first_non_void].type;
1419 int i;
1420
1421 if (type == UTIL_FORMAT_TYPE_FIXED)
1422 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1423
1424 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1425 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1426
1427 if (desc->nr_channels == 4 &&
1428 desc->channel[0].size == 10 &&
1429 desc->channel[1].size == 10 &&
1430 desc->channel[2].size == 10 &&
1431 desc->channel[3].size == 2)
1432 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1433
1434 /* See whether the components are of the same size. */
1435 for (i = 0; i < desc->nr_channels; i++) {
1436 if (desc->channel[first_non_void].size != desc->channel[i].size)
1437 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1438 }
1439
1440 switch (desc->channel[first_non_void].size) {
1441 case 8:
1442 switch (desc->nr_channels) {
1443 case 1:
1444 return V_008F0C_BUF_DATA_FORMAT_8;
1445 case 2:
1446 return V_008F0C_BUF_DATA_FORMAT_8_8;
1447 case 3:
1448 case 4:
1449 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1450 }
1451 break;
1452 case 16:
1453 switch (desc->nr_channels) {
1454 case 1:
1455 return V_008F0C_BUF_DATA_FORMAT_16;
1456 case 2:
1457 return V_008F0C_BUF_DATA_FORMAT_16_16;
1458 case 3:
1459 case 4:
1460 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1461 }
1462 break;
1463 case 32:
1464 /* From the Southern Islands ISA documentation about MTBUF:
1465 * 'Memory reads of data in memory that is 32 or 64 bits do not
1466 * undergo any format conversion.'
1467 */
1468 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1469 !desc->channel[first_non_void].pure_integer)
1470 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1471
1472 switch (desc->nr_channels) {
1473 case 1:
1474 return V_008F0C_BUF_DATA_FORMAT_32;
1475 case 2:
1476 return V_008F0C_BUF_DATA_FORMAT_32_32;
1477 case 3:
1478 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1479 case 4:
1480 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1481 }
1482 break;
1483 }
1484
1485 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1486 }
1487
1488 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1489 const struct util_format_description *desc,
1490 int first_non_void)
1491 {
1492 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1493 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1494
1495 switch (desc->channel[first_non_void].type) {
1496 case UTIL_FORMAT_TYPE_SIGNED:
1497 if (desc->channel[first_non_void].normalized)
1498 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1499 else if (desc->channel[first_non_void].pure_integer)
1500 return V_008F0C_BUF_NUM_FORMAT_SINT;
1501 else
1502 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1503 break;
1504 case UTIL_FORMAT_TYPE_UNSIGNED:
1505 if (desc->channel[first_non_void].normalized)
1506 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1507 else if (desc->channel[first_non_void].pure_integer)
1508 return V_008F0C_BUF_NUM_FORMAT_UINT;
1509 else
1510 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1511 break;
1512 case UTIL_FORMAT_TYPE_FLOAT:
1513 default:
1514 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1515 }
1516 }
1517
1518 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1519 {
1520 const struct util_format_description *desc;
1521 int first_non_void;
1522 unsigned data_format;
1523
1524 desc = util_format_description(format);
1525 first_non_void = util_format_get_first_non_void_channel(format);
1526 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1527 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1528 }
1529
1530 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1531 {
1532 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1533 r600_translate_colorswap(format) != ~0U;
1534 }
1535
1536 static bool si_is_zs_format_supported(enum pipe_format format)
1537 {
1538 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1539 }
1540
1541 boolean si_is_format_supported(struct pipe_screen *screen,
1542 enum pipe_format format,
1543 enum pipe_texture_target target,
1544 unsigned sample_count,
1545 unsigned usage)
1546 {
1547 struct si_screen *sscreen = (struct si_screen *)screen;
1548 unsigned retval = 0;
1549
1550 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1551 R600_ERR("r600: unsupported texture type %d\n", target);
1552 return FALSE;
1553 }
1554
1555 if (!util_format_is_supported(format, usage))
1556 return FALSE;
1557
1558 if (sample_count > 1) {
1559 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1560 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1561 return FALSE;
1562
1563 switch (sample_count) {
1564 case 2:
1565 case 4:
1566 case 8:
1567 break;
1568 default:
1569 return FALSE;
1570 }
1571 }
1572
1573 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1574 if (target == PIPE_BUFFER) {
1575 if (si_is_vertex_format_supported(screen, format))
1576 retval |= PIPE_BIND_SAMPLER_VIEW;
1577 } else {
1578 if (si_is_sampler_format_supported(screen, format))
1579 retval |= PIPE_BIND_SAMPLER_VIEW;
1580 }
1581 }
1582
1583 if ((usage & (PIPE_BIND_RENDER_TARGET |
1584 PIPE_BIND_DISPLAY_TARGET |
1585 PIPE_BIND_SCANOUT |
1586 PIPE_BIND_SHARED |
1587 PIPE_BIND_BLENDABLE)) &&
1588 si_is_colorbuffer_format_supported(format)) {
1589 retval |= usage &
1590 (PIPE_BIND_RENDER_TARGET |
1591 PIPE_BIND_DISPLAY_TARGET |
1592 PIPE_BIND_SCANOUT |
1593 PIPE_BIND_SHARED);
1594 if (!util_format_is_pure_integer(format) &&
1595 !util_format_is_depth_or_stencil(format))
1596 retval |= usage & PIPE_BIND_BLENDABLE;
1597 }
1598
1599 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1600 si_is_zs_format_supported(format)) {
1601 retval |= PIPE_BIND_DEPTH_STENCIL;
1602 }
1603
1604 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1605 si_is_vertex_format_supported(screen, format)) {
1606 retval |= PIPE_BIND_VERTEX_BUFFER;
1607 }
1608
1609 if (usage & PIPE_BIND_TRANSFER_READ)
1610 retval |= PIPE_BIND_TRANSFER_READ;
1611 if (usage & PIPE_BIND_TRANSFER_WRITE)
1612 retval |= PIPE_BIND_TRANSFER_WRITE;
1613
1614 return retval == usage;
1615 }
1616
1617 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1618 {
1619 unsigned tile_mode_index = 0;
1620
1621 if (stencil) {
1622 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1623 } else {
1624 tile_mode_index = rtex->surface.tiling_index[level];
1625 }
1626 return tile_mode_index;
1627 }
1628
1629 /*
1630 * framebuffer handling
1631 */
1632
1633 static void si_initialize_color_surface(struct si_context *sctx,
1634 struct r600_surface *surf)
1635 {
1636 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1637 unsigned level = surf->base.u.tex.level;
1638 uint64_t offset = rtex->surface.level[level].offset;
1639 unsigned pitch, slice;
1640 unsigned color_info, color_attrib, color_pitch, color_view;
1641 unsigned tile_mode_index;
1642 unsigned format, swap, ntype, endian;
1643 const struct util_format_description *desc;
1644 int i;
1645 unsigned blend_clamp = 0, blend_bypass = 0;
1646 unsigned max_comp_size;
1647
1648 /* Layered rendering doesn't work with LINEAR_GENERAL.
1649 * (LINEAR_ALIGNED and others work) */
1650 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1651 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1652 offset += rtex->surface.level[level].slice_size *
1653 surf->base.u.tex.first_layer;
1654 color_view = 0;
1655 } else {
1656 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1657 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1658 }
1659
1660 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1661 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1662 if (slice) {
1663 slice = slice - 1;
1664 }
1665
1666 tile_mode_index = si_tile_mode_index(rtex, level, false);
1667
1668 desc = util_format_description(surf->base.format);
1669 for (i = 0; i < 4; i++) {
1670 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1671 break;
1672 }
1673 }
1674 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1675 ntype = V_028C70_NUMBER_FLOAT;
1676 } else {
1677 ntype = V_028C70_NUMBER_UNORM;
1678 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1679 ntype = V_028C70_NUMBER_SRGB;
1680 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1681 if (desc->channel[i].pure_integer) {
1682 ntype = V_028C70_NUMBER_SINT;
1683 } else {
1684 assert(desc->channel[i].normalized);
1685 ntype = V_028C70_NUMBER_SNORM;
1686 }
1687 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1688 if (desc->channel[i].pure_integer) {
1689 ntype = V_028C70_NUMBER_UINT;
1690 } else {
1691 assert(desc->channel[i].normalized);
1692 ntype = V_028C70_NUMBER_UNORM;
1693 }
1694 }
1695 }
1696
1697 format = si_translate_colorformat(surf->base.format);
1698 if (format == V_028C70_COLOR_INVALID) {
1699 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1700 }
1701 assert(format != V_028C70_COLOR_INVALID);
1702 swap = r600_translate_colorswap(surf->base.format);
1703 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1704 endian = V_028C70_ENDIAN_NONE;
1705 } else {
1706 endian = si_colorformat_endian_swap(format);
1707 }
1708
1709 /* blend clamp should be set for all NORM/SRGB types */
1710 if (ntype == V_028C70_NUMBER_UNORM ||
1711 ntype == V_028C70_NUMBER_SNORM ||
1712 ntype == V_028C70_NUMBER_SRGB)
1713 blend_clamp = 1;
1714
1715 /* set blend bypass according to docs if SINT/UINT or
1716 8/24 COLOR variants */
1717 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1718 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1719 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1720 blend_clamp = 0;
1721 blend_bypass = 1;
1722 }
1723
1724 color_info = S_028C70_FORMAT(format) |
1725 S_028C70_COMP_SWAP(swap) |
1726 S_028C70_BLEND_CLAMP(blend_clamp) |
1727 S_028C70_BLEND_BYPASS(blend_bypass) |
1728 S_028C70_NUMBER_TYPE(ntype) |
1729 S_028C70_ENDIAN(endian);
1730
1731 color_pitch = S_028C64_TILE_MAX(pitch);
1732
1733 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1734 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1735
1736 if (rtex->resource.b.b.nr_samples > 1) {
1737 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1738
1739 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1740 S_028C74_NUM_FRAGMENTS(log_samples);
1741
1742 if (rtex->fmask.size) {
1743 color_info |= S_028C70_COMPRESSION(1);
1744 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1745
1746 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1747
1748 if (sctx->b.chip_class == SI) {
1749 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1750 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1751 }
1752 if (sctx->b.chip_class >= CIK) {
1753 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1754 }
1755 }
1756 }
1757
1758 offset += rtex->resource.gpu_address;
1759
1760 surf->cb_color_base = offset >> 8;
1761 surf->cb_color_pitch = color_pitch;
1762 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1763 surf->cb_color_view = color_view;
1764 surf->cb_color_info = color_info;
1765 surf->cb_color_attrib = color_attrib;
1766
1767 if (rtex->fmask.size) {
1768 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1769 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1770 } else {
1771 /* This must be set for fast clear to work without FMASK. */
1772 surf->cb_color_fmask = surf->cb_color_base;
1773 surf->cb_color_fmask_slice = surf->cb_color_slice;
1774 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1775
1776 if (sctx->b.chip_class == SI) {
1777 unsigned bankh = util_logbase2(rtex->surface.bankh);
1778 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1779 }
1780
1781 if (sctx->b.chip_class >= CIK) {
1782 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1783 }
1784 }
1785
1786 /* Determine pixel shader export format */
1787 max_comp_size = si_colorformat_max_comp_size(format);
1788 if (ntype == V_028C70_NUMBER_SRGB ||
1789 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1790 max_comp_size <= 10) ||
1791 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1792 surf->export_16bpc = true;
1793 }
1794
1795 surf->color_initialized = true;
1796 }
1797
1798 static void si_init_depth_surface(struct si_context *sctx,
1799 struct r600_surface *surf)
1800 {
1801 struct si_screen *sscreen = sctx->screen;
1802 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1803 unsigned level = surf->base.u.tex.level;
1804 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1805 unsigned format, tile_mode_index, array_mode;
1806 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1807 uint32_t z_info, s_info, db_depth_info;
1808 uint64_t z_offs, s_offs;
1809 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1810
1811 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1812 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1813 case PIPE_FORMAT_X8Z24_UNORM:
1814 case PIPE_FORMAT_Z24X8_UNORM:
1815 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1816 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1817 break;
1818 case PIPE_FORMAT_Z32_FLOAT:
1819 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1820 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1821 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1822 break;
1823 case PIPE_FORMAT_Z16_UNORM:
1824 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1825 break;
1826 default:
1827 assert(0);
1828 }
1829
1830 format = si_translate_dbformat(rtex->resource.b.b.format);
1831
1832 if (format == V_028040_Z_INVALID) {
1833 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1834 }
1835 assert(format != V_028040_Z_INVALID);
1836
1837 s_offs = z_offs = rtex->resource.gpu_address;
1838 z_offs += rtex->surface.level[level].offset;
1839 s_offs += rtex->surface.stencil_level[level].offset;
1840
1841 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1842
1843 z_info = S_028040_FORMAT(format);
1844 if (rtex->resource.b.b.nr_samples > 1) {
1845 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1846 }
1847
1848 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1849 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1850 else
1851 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1852
1853 if (sctx->b.chip_class >= CIK) {
1854 switch (rtex->surface.level[level].mode) {
1855 case RADEON_SURF_MODE_2D:
1856 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1857 break;
1858 case RADEON_SURF_MODE_1D:
1859 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1860 case RADEON_SURF_MODE_LINEAR:
1861 default:
1862 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1863 break;
1864 }
1865 tile_split = rtex->surface.tile_split;
1866 stile_split = rtex->surface.stencil_tile_split;
1867 macro_aspect = rtex->surface.mtilea;
1868 bankw = rtex->surface.bankw;
1869 bankh = rtex->surface.bankh;
1870 tile_split = cik_tile_split(tile_split);
1871 stile_split = cik_tile_split(stile_split);
1872 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1873 bankw = cik_bank_wh(bankw);
1874 bankh = cik_bank_wh(bankh);
1875 nbanks = si_num_banks(sscreen, rtex);
1876 tile_mode_index = si_tile_mode_index(rtex, level, false);
1877 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1878
1879 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1880 S_02803C_PIPE_CONFIG(pipe_config) |
1881 S_02803C_BANK_WIDTH(bankw) |
1882 S_02803C_BANK_HEIGHT(bankh) |
1883 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1884 S_02803C_NUM_BANKS(nbanks);
1885 z_info |= S_028040_TILE_SPLIT(tile_split);
1886 s_info |= S_028044_TILE_SPLIT(stile_split);
1887 } else {
1888 tile_mode_index = si_tile_mode_index(rtex, level, false);
1889 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1890 tile_mode_index = si_tile_mode_index(rtex, level, true);
1891 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1892 }
1893
1894 /* HiZ aka depth buffer htile */
1895 /* use htile only for first level */
1896 if (rtex->htile_buffer && !level) {
1897 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1898 S_028040_ALLOW_EXPCLEAR(1);
1899
1900 /* This is optimal for the clear value of 1.0 and using
1901 * the LESS and LEQUAL test functions. Set this to 0
1902 * for the opposite case. This can only be changed when
1903 * clearing. */
1904 z_info |= S_028040_ZRANGE_PRECISION(1);
1905
1906 /* Use all of the htile_buffer for depth, because we don't
1907 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1908 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1909
1910 uint64_t va = rtex->htile_buffer->gpu_address;
1911 db_htile_data_base = va >> 8;
1912 db_htile_surface = S_028ABC_FULL_CACHE(1);
1913 } else {
1914 db_htile_data_base = 0;
1915 db_htile_surface = 0;
1916 }
1917
1918 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1919
1920 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1921 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1922 surf->db_htile_data_base = db_htile_data_base;
1923 surf->db_depth_info = db_depth_info;
1924 surf->db_z_info = z_info;
1925 surf->db_stencil_info = s_info;
1926 surf->db_depth_base = z_offs >> 8;
1927 surf->db_stencil_base = s_offs >> 8;
1928 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1929 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1930 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1931 levelinfo->nblk_y) / 64 - 1);
1932 surf->db_htile_surface = db_htile_surface;
1933 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1934
1935 surf->depth_initialized = true;
1936 }
1937
1938 static void si_set_framebuffer_state(struct pipe_context *ctx,
1939 const struct pipe_framebuffer_state *state)
1940 {
1941 struct si_context *sctx = (struct si_context *)ctx;
1942 struct pipe_constant_buffer constbuf = {0};
1943 struct r600_surface *surf = NULL;
1944 struct r600_texture *rtex;
1945 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
1946 int i;
1947
1948 if (sctx->framebuffer.state.nr_cbufs) {
1949 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1950 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1951 }
1952 if (sctx->framebuffer.state.zsbuf) {
1953 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1954 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1955 }
1956
1957 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1958
1959 sctx->framebuffer.export_16bpc = 0;
1960 sctx->framebuffer.compressed_cb_mask = 0;
1961 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1962 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1963 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1964 util_format_is_pure_integer(state->cbufs[0]->format);
1965
1966 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
1967 sctx->db_render_state.dirty = true;
1968
1969 for (i = 0; i < state->nr_cbufs; i++) {
1970 if (!state->cbufs[i])
1971 continue;
1972
1973 surf = (struct r600_surface*)state->cbufs[i];
1974 rtex = (struct r600_texture*)surf->base.texture;
1975
1976 if (!surf->color_initialized) {
1977 si_initialize_color_surface(sctx, surf);
1978 }
1979
1980 if (surf->export_16bpc) {
1981 sctx->framebuffer.export_16bpc |= 1 << i;
1982 }
1983
1984 if (rtex->fmask.size && rtex->cmask.size) {
1985 sctx->framebuffer.compressed_cb_mask |= 1 << i;
1986 }
1987 }
1988 /* Set the 16BPC export for possible dual-src blending. */
1989 if (i == 1 && surf && surf->export_16bpc) {
1990 sctx->framebuffer.export_16bpc |= 1 << 1;
1991 }
1992
1993 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
1994
1995 if (state->zsbuf) {
1996 surf = (struct r600_surface*)state->zsbuf;
1997
1998 if (!surf->depth_initialized) {
1999 si_init_depth_surface(sctx, surf);
2000 }
2001 }
2002
2003 si_update_fb_rs_state(sctx);
2004 si_update_fb_blend_state(sctx);
2005
2006 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2007 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2008 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2009 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2010 sctx->framebuffer.atom.dirty = true;
2011 sctx->msaa_config.dirty = true;
2012
2013 /* Set sample locations as fragment shader constants. */
2014 switch (sctx->framebuffer.nr_samples) {
2015 case 1:
2016 constbuf.user_buffer = sctx->b.sample_locations_1x;
2017 break;
2018 case 2:
2019 constbuf.user_buffer = sctx->b.sample_locations_2x;
2020 break;
2021 case 4:
2022 constbuf.user_buffer = sctx->b.sample_locations_4x;
2023 break;
2024 case 8:
2025 constbuf.user_buffer = sctx->b.sample_locations_8x;
2026 break;
2027 case 16:
2028 constbuf.user_buffer = sctx->b.sample_locations_16x;
2029 break;
2030 default:
2031 assert(0);
2032 }
2033 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2034 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2035 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2036 }
2037
2038 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2039 {
2040 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2041 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2042 unsigned i, nr_cbufs = state->nr_cbufs;
2043 struct r600_texture *tex = NULL;
2044 struct r600_surface *cb = NULL;
2045
2046 /* Colorbuffers. */
2047 for (i = 0; i < nr_cbufs; i++) {
2048 cb = (struct r600_surface*)state->cbufs[i];
2049 if (!cb) {
2050 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2051 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2052 continue;
2053 }
2054
2055 tex = (struct r600_texture *)cb->base.texture;
2056 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2057 &tex->resource, RADEON_USAGE_READWRITE,
2058 tex->surface.nsamples > 1 ?
2059 RADEON_PRIO_COLOR_BUFFER_MSAA :
2060 RADEON_PRIO_COLOR_BUFFER);
2061
2062 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2063 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2064 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2065 RADEON_PRIO_COLOR_META);
2066 }
2067
2068 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2069 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2070 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2071 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2072 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2073 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2074 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2075 radeon_emit(cs, 0); /* R_028C78 unused */
2076 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2077 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2078 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2079 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2080 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2081 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2082 }
2083 /* set CB_COLOR1_INFO for possible dual-src blending */
2084 if (i == 1 && state->cbufs[0]) {
2085 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2086 cb->cb_color_info | tex->cb_color_info);
2087 i++;
2088 }
2089 for (; i < 8 ; i++) {
2090 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2091 }
2092
2093 /* ZS buffer. */
2094 if (state->zsbuf) {
2095 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2096 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2097
2098 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2099 &rtex->resource, RADEON_USAGE_READWRITE,
2100 zb->base.texture->nr_samples > 1 ?
2101 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2102 RADEON_PRIO_DEPTH_BUFFER);
2103
2104 if (zb->db_htile_data_base) {
2105 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2106 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2107 RADEON_PRIO_DEPTH_META);
2108 }
2109
2110 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2111 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2112
2113 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2114 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2115 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2116 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2117 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2118 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2119 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2120 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2121 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2122 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2123
2124 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2125 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2126 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2127 zb->pa_su_poly_offset_db_fmt_cntl);
2128 } else {
2129 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2130 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2131 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2132 }
2133
2134 /* Framebuffer dimensions. */
2135 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2136 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2137 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2138
2139 cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
2140 }
2141
2142 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2143 {
2144 struct si_context *sctx = (struct si_context *)rctx;
2145 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2146
2147 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2148 sctx->ps_iter_samples);
2149 }
2150
2151 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2152
2153 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2154 {
2155 struct si_context *sctx = (struct si_context *)ctx;
2156
2157 if (sctx->ps_iter_samples == min_samples)
2158 return;
2159
2160 sctx->ps_iter_samples = min_samples;
2161
2162 if (sctx->framebuffer.nr_samples > 1)
2163 sctx->msaa_config.dirty = true;
2164 }
2165
2166 /*
2167 * shaders
2168 */
2169
2170 /* Compute the key for the hw shader variant */
2171 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2172 struct si_pipe_shader_selector *sel,
2173 union si_shader_key *key)
2174 {
2175 struct si_context *sctx = (struct si_context *)ctx;
2176 memset(key, 0, sizeof(*key));
2177
2178 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2179 sctx->queued.named.rasterizer) {
2180 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2181 key->vs.ucps_enabled |= 0x2;
2182 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2183 key->vs.ucps_enabled |= 0x1;
2184 }
2185
2186 if (sel->type == PIPE_SHADER_VERTEX) {
2187 unsigned i;
2188 if (!sctx->vertex_elements)
2189 return;
2190
2191 for (i = 0; i < sctx->vertex_elements->count; ++i)
2192 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2193
2194 key->vs.as_es = sctx->gs_shader != NULL;
2195 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2196 if (sel->fs_write_all)
2197 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs;
2198 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
2199
2200 if (sctx->queued.named.rasterizer) {
2201 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2202 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2203 key->ps.interp_at_sample = sctx->framebuffer.nr_samples > 1 &&
2204 sctx->ps_iter_samples == sctx->framebuffer.nr_samples;
2205
2206 if (sctx->queued.named.blend) {
2207 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2208 sctx->queued.named.rasterizer->multisample_enable &&
2209 !sctx->framebuffer.cb0_is_integer;
2210 }
2211 }
2212 if (sctx->queued.named.dsa) {
2213 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2214
2215 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2216 if (sctx->framebuffer.cb0_is_integer)
2217 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2218 } else {
2219 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2220 }
2221 }
2222 }
2223
2224 /* Select the hw shader variant depending on the current state. */
2225 int si_shader_select(struct pipe_context *ctx,
2226 struct si_pipe_shader_selector *sel)
2227 {
2228 union si_shader_key key;
2229 struct si_pipe_shader * shader = NULL;
2230 int r;
2231
2232 si_shader_selector_key(ctx, sel, &key);
2233
2234 /* Check if we don't need to change anything.
2235 * This path is also used for most shaders that don't need multiple
2236 * variants, it will cost just a computation of the key and this
2237 * test. */
2238 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2239 return 0;
2240 }
2241
2242 /* lookup if we have other variants in the list */
2243 if (sel->num_shaders > 1) {
2244 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2245
2246 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2247 p = c;
2248 c = c->next_variant;
2249 }
2250
2251 if (c) {
2252 p->next_variant = c->next_variant;
2253 shader = c;
2254 }
2255 }
2256
2257 if (shader) {
2258 shader->next_variant = sel->current;
2259 sel->current = shader;
2260 } else {
2261 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2262 shader->selector = sel;
2263 shader->key = key;
2264
2265 shader->next_variant = sel->current;
2266 sel->current = shader;
2267 r = si_pipe_shader_create(ctx, shader);
2268 if (unlikely(r)) {
2269 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2270 sel->type, r);
2271 sel->current = NULL;
2272 FREE(shader);
2273 return r;
2274 }
2275 sel->num_shaders++;
2276 }
2277
2278 return 0;
2279 }
2280
2281 static void *si_create_shader_state(struct pipe_context *ctx,
2282 const struct pipe_shader_state *state,
2283 unsigned pipe_shader_type)
2284 {
2285 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2286 int r;
2287
2288 sel->type = pipe_shader_type;
2289 sel->tokens = tgsi_dup_tokens(state->tokens);
2290 sel->so = state->stream_output;
2291
2292 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2293 struct tgsi_shader_info info;
2294
2295 tgsi_scan_shader(state->tokens, &info);
2296 sel->fs_write_all = info.color0_writes_all_cbufs;
2297 }
2298
2299 r = si_shader_select(ctx, sel);
2300 if (r) {
2301 free(sel);
2302 return NULL;
2303 }
2304
2305 return sel;
2306 }
2307
2308 static void *si_create_fs_state(struct pipe_context *ctx,
2309 const struct pipe_shader_state *state)
2310 {
2311 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2312 }
2313
2314 static void *si_create_gs_state(struct pipe_context *ctx,
2315 const struct pipe_shader_state *state)
2316 {
2317 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2318 }
2319
2320 static void *si_create_vs_state(struct pipe_context *ctx,
2321 const struct pipe_shader_state *state)
2322 {
2323 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2324 }
2325
2326 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2327 {
2328 struct si_context *sctx = (struct si_context *)ctx;
2329 struct si_pipe_shader_selector *sel = state;
2330
2331 if (sctx->vs_shader == sel)
2332 return;
2333
2334 if (!sel || !sel->current)
2335 return;
2336
2337 sctx->vs_shader = sel;
2338 }
2339
2340 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2341 {
2342 struct si_context *sctx = (struct si_context *)ctx;
2343 struct si_pipe_shader_selector *sel = state;
2344
2345 if (sctx->gs_shader == sel)
2346 return;
2347
2348 sctx->gs_shader = sel;
2349 }
2350
2351 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2352 {
2353 struct si_context *sctx = (struct si_context *)ctx;
2354 struct si_pipe_shader_selector *sel = state;
2355
2356 /* skip if supplied shader is one already in use */
2357 if (sctx->ps_shader == sel)
2358 return;
2359
2360 /* use dummy shader if supplied shader is corrupt */
2361 if (!sel || !sel->current) {
2362 if (!sctx->dummy_pixel_shader) {
2363 sctx->dummy_pixel_shader =
2364 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
2365 TGSI_SEMANTIC_GENERIC,
2366 TGSI_INTERPOLATE_CONSTANT);
2367 }
2368
2369 sel = sctx->dummy_pixel_shader;
2370 }
2371
2372 sctx->ps_shader = sel;
2373 }
2374
2375 static void si_delete_shader_selector(struct pipe_context *ctx,
2376 struct si_pipe_shader_selector *sel)
2377 {
2378 struct si_context *sctx = (struct si_context *)ctx;
2379 struct si_pipe_shader *p = sel->current, *c;
2380
2381 while (p) {
2382 c = p->next_variant;
2383 if (sel->type == PIPE_SHADER_GEOMETRY)
2384 si_pm4_delete_state(sctx, gs, p->pm4);
2385 else if (sel->type == PIPE_SHADER_FRAGMENT)
2386 si_pm4_delete_state(sctx, ps, p->pm4);
2387 else if (p->key.vs.as_es)
2388 si_pm4_delete_state(sctx, es, p->pm4);
2389 else
2390 si_pm4_delete_state(sctx, vs, p->pm4);
2391 si_pipe_shader_destroy(ctx, p);
2392 free(p);
2393 p = c;
2394 }
2395
2396 free(sel->tokens);
2397 free(sel);
2398 }
2399
2400 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2401 {
2402 struct si_context *sctx = (struct si_context *)ctx;
2403 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2404
2405 if (sctx->vs_shader == sel) {
2406 sctx->vs_shader = NULL;
2407 }
2408
2409 si_delete_shader_selector(ctx, sel);
2410 }
2411
2412 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2413 {
2414 struct si_context *sctx = (struct si_context *)ctx;
2415 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2416
2417 if (sctx->gs_shader == sel) {
2418 sctx->gs_shader = NULL;
2419 }
2420
2421 si_delete_shader_selector(ctx, sel);
2422 }
2423
2424 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2425 {
2426 struct si_context *sctx = (struct si_context *)ctx;
2427 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2428
2429 if (sctx->ps_shader == sel) {
2430 sctx->ps_shader = NULL;
2431 }
2432
2433 si_delete_shader_selector(ctx, sel);
2434 }
2435
2436 /*
2437 * Samplers
2438 */
2439
2440 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2441 struct pipe_resource *texture,
2442 const struct pipe_sampler_view *state)
2443 {
2444 struct si_context *sctx = (struct si_context*)ctx;
2445 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2446 struct r600_texture *tmp = (struct r600_texture*)texture;
2447 const struct util_format_description *desc;
2448 unsigned format, num_format;
2449 uint32_t pitch = 0;
2450 unsigned char state_swizzle[4], swizzle[4];
2451 unsigned height, depth, width;
2452 enum pipe_format pipe_format = state->format;
2453 struct radeon_surface_level *surflevel;
2454 int first_non_void;
2455 uint64_t va;
2456
2457 if (view == NULL)
2458 return NULL;
2459
2460 /* initialize base object */
2461 view->base = *state;
2462 view->base.texture = NULL;
2463 pipe_resource_reference(&view->base.texture, texture);
2464 view->base.reference.count = 1;
2465 view->base.context = ctx;
2466 view->resource = &tmp->resource;
2467
2468 /* Buffer resource. */
2469 if (texture->target == PIPE_BUFFER) {
2470 unsigned stride;
2471
2472 desc = util_format_description(state->format);
2473 first_non_void = util_format_get_first_non_void_channel(state->format);
2474 stride = desc->block.bits / 8;
2475 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2476 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2477 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2478
2479 view->state[0] = va;
2480 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2481 S_008F04_STRIDE(stride);
2482 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2483 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2484 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2485 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2486 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2487 S_008F0C_NUM_FORMAT(num_format) |
2488 S_008F0C_DATA_FORMAT(format);
2489
2490 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2491 return &view->base;
2492 }
2493
2494 state_swizzle[0] = state->swizzle_r;
2495 state_swizzle[1] = state->swizzle_g;
2496 state_swizzle[2] = state->swizzle_b;
2497 state_swizzle[3] = state->swizzle_a;
2498
2499 surflevel = tmp->surface.level;
2500
2501 /* Texturing with separate depth and stencil. */
2502 if (tmp->is_depth && !tmp->is_flushing_texture) {
2503 switch (pipe_format) {
2504 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2505 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2506 break;
2507 case PIPE_FORMAT_X8Z24_UNORM:
2508 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2509 /* Z24 is always stored like this. */
2510 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2511 break;
2512 case PIPE_FORMAT_X24S8_UINT:
2513 case PIPE_FORMAT_S8X24_UINT:
2514 case PIPE_FORMAT_X32_S8X24_UINT:
2515 pipe_format = PIPE_FORMAT_S8_UINT;
2516 surflevel = tmp->surface.stencil_level;
2517 break;
2518 default:;
2519 }
2520 }
2521
2522 desc = util_format_description(pipe_format);
2523
2524 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2525 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2526 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2527
2528 switch (pipe_format) {
2529 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2530 case PIPE_FORMAT_X24S8_UINT:
2531 case PIPE_FORMAT_X32_S8X24_UINT:
2532 case PIPE_FORMAT_X8Z24_UNORM:
2533 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2534 break;
2535 default:
2536 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2537 }
2538 } else {
2539 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2540 }
2541
2542 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2543
2544 switch (pipe_format) {
2545 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2546 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2547 break;
2548 default:
2549 if (first_non_void < 0) {
2550 if (util_format_is_compressed(pipe_format)) {
2551 switch (pipe_format) {
2552 case PIPE_FORMAT_DXT1_SRGB:
2553 case PIPE_FORMAT_DXT1_SRGBA:
2554 case PIPE_FORMAT_DXT3_SRGBA:
2555 case PIPE_FORMAT_DXT5_SRGBA:
2556 case PIPE_FORMAT_BPTC_SRGBA:
2557 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2558 break;
2559 case PIPE_FORMAT_RGTC1_SNORM:
2560 case PIPE_FORMAT_LATC1_SNORM:
2561 case PIPE_FORMAT_RGTC2_SNORM:
2562 case PIPE_FORMAT_LATC2_SNORM:
2563 /* implies float, so use SNORM/UNORM to determine
2564 whether data is signed or not */
2565 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2566 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2567 break;
2568 default:
2569 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2570 break;
2571 }
2572 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2573 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2574 } else {
2575 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2576 }
2577 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2578 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2579 } else {
2580 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2581
2582 switch (desc->channel[first_non_void].type) {
2583 case UTIL_FORMAT_TYPE_FLOAT:
2584 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2585 break;
2586 case UTIL_FORMAT_TYPE_SIGNED:
2587 if (desc->channel[first_non_void].normalized)
2588 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2589 else if (desc->channel[first_non_void].pure_integer)
2590 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2591 else
2592 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2593 break;
2594 case UTIL_FORMAT_TYPE_UNSIGNED:
2595 if (desc->channel[first_non_void].normalized)
2596 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2597 else if (desc->channel[first_non_void].pure_integer)
2598 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2599 else
2600 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2601 }
2602 }
2603 }
2604
2605 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2606 if (format == ~0) {
2607 format = 0;
2608 }
2609
2610 /* not supported any more */
2611 //endian = si_colorformat_endian_swap(format);
2612
2613 width = surflevel[0].npix_x;
2614 height = surflevel[0].npix_y;
2615 depth = surflevel[0].npix_z;
2616 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2617
2618 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2619 height = 1;
2620 depth = texture->array_size;
2621 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2622 depth = texture->array_size;
2623 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2624 depth = texture->array_size / 6;
2625
2626 va = tmp->resource.gpu_address + surflevel[0].offset;
2627 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2628
2629 view->state[0] = va >> 8;
2630 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2631 S_008F14_DATA_FORMAT(format) |
2632 S_008F14_NUM_FORMAT(num_format));
2633 view->state[2] = (S_008F18_WIDTH(width - 1) |
2634 S_008F18_HEIGHT(height - 1));
2635 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2636 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2637 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2638 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2639 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2640 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2641 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2642 util_logbase2(texture->nr_samples) :
2643 state->u.tex.last_level - tmp->mipmap_shift) |
2644 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2645 S_008F1C_POW2_PAD(texture->last_level > 0) |
2646 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2647 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2648 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2649 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2650 view->state[6] = 0;
2651 view->state[7] = 0;
2652
2653 /* Initialize the sampler view for FMASK. */
2654 if (tmp->fmask.size) {
2655 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2656 uint32_t fmask_format;
2657
2658 switch (texture->nr_samples) {
2659 case 2:
2660 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2661 break;
2662 case 4:
2663 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2664 break;
2665 case 8:
2666 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2667 break;
2668 default:
2669 assert(0);
2670 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2671 }
2672
2673 view->fmask_state[0] = va >> 8;
2674 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2675 S_008F14_DATA_FORMAT(fmask_format) |
2676 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2677 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2678 S_008F18_HEIGHT(height - 1);
2679 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2680 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2681 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2682 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2683 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2684 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2685 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2686 S_008F20_PITCH(tmp->fmask.pitch - 1);
2687 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2688 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2689 view->fmask_state[6] = 0;
2690 view->fmask_state[7] = 0;
2691 }
2692
2693 return &view->base;
2694 }
2695
2696 static void si_sampler_view_destroy(struct pipe_context *ctx,
2697 struct pipe_sampler_view *state)
2698 {
2699 struct si_pipe_sampler_view *view = (struct si_pipe_sampler_view *)state;
2700
2701 if (view->resource->b.b.target == PIPE_BUFFER)
2702 LIST_DELINIT(&view->list);
2703
2704 pipe_resource_reference(&state->texture, NULL);
2705 FREE(view);
2706 }
2707
2708 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2709 {
2710 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2711 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2712 (linear_filter &&
2713 (wrap == PIPE_TEX_WRAP_CLAMP ||
2714 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2715 }
2716
2717 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2718 {
2719 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2720 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2721
2722 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2723 state->border_color.ui[2] || state->border_color.ui[3]) &&
2724 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2725 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2726 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2727 }
2728
2729 static void *si_create_sampler_state(struct pipe_context *ctx,
2730 const struct pipe_sampler_state *state)
2731 {
2732 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2733 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2734 unsigned border_color_type;
2735
2736 if (rstate == NULL) {
2737 return NULL;
2738 }
2739
2740 if (sampler_state_needs_border_color(state))
2741 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2742 else
2743 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2744
2745 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2746 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2747 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2748 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2749 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2750 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2751 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2752 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2753 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2754 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2755 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2756 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2757 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2758 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2759
2760 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2761 memcpy(rstate->border_color, state->border_color.ui,
2762 sizeof(rstate->border_color));
2763 }
2764
2765 return rstate;
2766 }
2767
2768 /* Upload border colors and update the pointers in resource descriptors.
2769 * There can only be 4096 border colors per context.
2770 *
2771 * XXX: This is broken if the buffer gets reallocated.
2772 */
2773 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2774 void **states)
2775 {
2776 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2777 uint32_t *border_color_table = NULL;
2778 int i, j;
2779
2780 for (i = 0; i < count; i++) {
2781 if (rstates[i] &&
2782 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2783 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2784 if (!sctx->border_color_table ||
2785 ((sctx->border_color_offset + count - i) &
2786 C_008F3C_BORDER_COLOR_PTR)) {
2787 r600_resource_reference(&sctx->border_color_table, NULL);
2788 sctx->border_color_offset = 0;
2789
2790 sctx->border_color_table =
2791 si_resource_create_custom(&sctx->screen->b.b,
2792 PIPE_USAGE_DYNAMIC,
2793 4096 * 4 * 4);
2794 }
2795
2796 if (!border_color_table) {
2797 border_color_table =
2798 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2799 sctx->b.rings.gfx.cs,
2800 PIPE_TRANSFER_WRITE |
2801 PIPE_TRANSFER_UNSYNCHRONIZED);
2802 }
2803
2804 for (j = 0; j < 4; j++) {
2805 border_color_table[4 * sctx->border_color_offset + j] =
2806 util_le32_to_cpu(rstates[i]->border_color[j]);
2807 }
2808
2809 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2810 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2811 }
2812 }
2813
2814 if (border_color_table) {
2815 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2816
2817 uint64_t va_offset = sctx->border_color_table->gpu_address;
2818
2819 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2820 if (sctx->b.chip_class >= CIK)
2821 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2822 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2823 RADEON_PRIO_SHADER_DATA);
2824 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2825 }
2826 }
2827
2828 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2829 unsigned start, unsigned count,
2830 void **states)
2831 {
2832 struct si_context *sctx = (struct si_context *)ctx;
2833
2834 if (!count || shader >= SI_NUM_SHADERS)
2835 return;
2836
2837 si_set_border_colors(sctx, count, states);
2838 si_set_sampler_descriptors(sctx, shader, start, count, states);
2839 }
2840
2841 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2842 {
2843 struct si_context *sctx = (struct si_context *)ctx;
2844 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2845 struct si_pm4_state *pm4 = &state->pm4;
2846 uint16_t mask = sample_mask;
2847
2848 if (state == NULL)
2849 return;
2850
2851 state->sample_mask = mask;
2852 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2853 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2854
2855 si_pm4_set_state(sctx, sample_mask, state);
2856 }
2857
2858 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2859 {
2860 free(state);
2861 }
2862
2863 /*
2864 * Vertex elements & buffers
2865 */
2866
2867 static void *si_create_vertex_elements(struct pipe_context *ctx,
2868 unsigned count,
2869 const struct pipe_vertex_element *elements)
2870 {
2871 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2872 int i;
2873
2874 assert(count < PIPE_MAX_ATTRIBS);
2875 if (!v)
2876 return NULL;
2877
2878 v->count = count;
2879 for (i = 0; i < count; ++i) {
2880 const struct util_format_description *desc;
2881 unsigned data_format, num_format;
2882 int first_non_void;
2883
2884 desc = util_format_description(elements[i].src_format);
2885 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2886 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2887 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2888
2889 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2890 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2891 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2892 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2893 S_008F0C_NUM_FORMAT(num_format) |
2894 S_008F0C_DATA_FORMAT(data_format);
2895 v->format_size[i] = desc->block.bits / 8;
2896 }
2897 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2898
2899 return v;
2900 }
2901
2902 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2903 {
2904 struct si_context *sctx = (struct si_context *)ctx;
2905 struct si_vertex_element *v = (struct si_vertex_element*)state;
2906
2907 sctx->vertex_elements = v;
2908 sctx->vertex_buffers_dirty = true;
2909 }
2910
2911 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2912 {
2913 struct si_context *sctx = (struct si_context *)ctx;
2914
2915 if (sctx->vertex_elements == state)
2916 sctx->vertex_elements = NULL;
2917 FREE(state);
2918 }
2919
2920 static void si_set_vertex_buffers(struct pipe_context *ctx,
2921 unsigned start_slot, unsigned count,
2922 const struct pipe_vertex_buffer *buffers)
2923 {
2924 struct si_context *sctx = (struct si_context *)ctx;
2925 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2926 int i;
2927
2928 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2929
2930 if (buffers) {
2931 for (i = 0; i < count; i++) {
2932 const struct pipe_vertex_buffer *src = buffers + i;
2933 struct pipe_vertex_buffer *dsti = dst + i;
2934
2935 pipe_resource_reference(&dsti->buffer, src->buffer);
2936 dsti->buffer_offset = src->buffer_offset;
2937 dsti->stride = src->stride;
2938 }
2939 } else {
2940 for (i = 0; i < count; i++) {
2941 pipe_resource_reference(&dst[i].buffer, NULL);
2942 }
2943 }
2944 sctx->vertex_buffers_dirty = true;
2945 }
2946
2947 static void si_set_index_buffer(struct pipe_context *ctx,
2948 const struct pipe_index_buffer *ib)
2949 {
2950 struct si_context *sctx = (struct si_context *)ctx;
2951
2952 if (ib) {
2953 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2954 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2955 } else {
2956 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2957 }
2958 }
2959
2960 /*
2961 * Misc
2962 */
2963 static void si_set_polygon_stipple(struct pipe_context *ctx,
2964 const struct pipe_poly_stipple *state)
2965 {
2966 }
2967
2968 static void si_texture_barrier(struct pipe_context *ctx)
2969 {
2970 struct si_context *sctx = (struct si_context *)ctx;
2971
2972 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2973 R600_CONTEXT_FLUSH_AND_INV_CB;
2974 }
2975
2976 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2977 {
2978 struct pipe_blend_state blend;
2979
2980 memset(&blend, 0, sizeof(blend));
2981 blend.independent_blend_enable = true;
2982 blend.rt[0].colormask = 0xf;
2983 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2984 }
2985
2986 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2987 bool include_draw_vbo)
2988 {
2989 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2990 }
2991
2992 void si_init_state_functions(struct si_context *sctx)
2993 {
2994 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2995 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2996
2997 sctx->b.b.create_blend_state = si_create_blend_state;
2998 sctx->b.b.bind_blend_state = si_bind_blend_state;
2999 sctx->b.b.delete_blend_state = si_delete_blend_state;
3000 sctx->b.b.set_blend_color = si_set_blend_color;
3001
3002 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3003 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3004 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3005
3006 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3007 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3008 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3009
3010 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3011 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3012 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3013 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3014
3015 sctx->b.b.set_clip_state = si_set_clip_state;
3016 sctx->b.b.set_scissor_states = si_set_scissor_states;
3017 sctx->b.b.set_viewport_states = si_set_viewport_states;
3018 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3019
3020 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3021 sctx->b.b.get_sample_position = cayman_get_sample_position;
3022
3023 sctx->b.b.create_vs_state = si_create_vs_state;
3024 sctx->b.b.create_fs_state = si_create_fs_state;
3025 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3026 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3027 sctx->b.b.delete_vs_state = si_delete_vs_shader;
3028 sctx->b.b.delete_fs_state = si_delete_ps_shader;
3029
3030 sctx->b.b.create_gs_state = si_create_gs_state;
3031 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3032 sctx->b.b.delete_gs_state = si_delete_gs_shader;
3033
3034 sctx->b.b.create_sampler_state = si_create_sampler_state;
3035 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3036 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3037
3038 sctx->b.b.create_sampler_view = si_create_sampler_view;
3039 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3040
3041 sctx->b.b.set_sample_mask = si_set_sample_mask;
3042
3043 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3044 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3045 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3046 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3047 sctx->b.b.set_index_buffer = si_set_index_buffer;
3048
3049 sctx->b.b.texture_barrier = si_texture_barrier;
3050 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3051 sctx->b.b.set_min_samples = si_set_min_samples;
3052
3053 sctx->b.dma_copy = si_dma_copy;
3054 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3055 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3056
3057 sctx->b.b.draw_vbo = si_draw_vbo;
3058 }
3059
3060 void si_init_config(struct si_context *sctx)
3061 {
3062 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3063
3064 if (pm4 == NULL)
3065 return;
3066
3067 si_cmd_context_control(pm4);
3068
3069 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3070 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3071 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3072 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3073 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3074 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3075 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3076 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3077 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3078 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3079 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3080 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3081
3082 /* FIXME calculate these values somehow ??? */
3083 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3084 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3085 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3086
3087 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3088 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3089 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3090 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3091
3092 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3093 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3094 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3095 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3096
3097 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3098 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3099 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3100 if (sctx->b.chip_class < CIK)
3101 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3102 S_008A14_CLIP_VTX_REORDER_ENA(1));
3103
3104 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3105 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3106
3107 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3108
3109 if (sctx->b.chip_class >= CIK) {
3110 switch (sctx->screen->b.family) {
3111 case CHIP_BONAIRE:
3112 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3113 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3114 break;
3115 case CHIP_HAWAII:
3116 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3117 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3118 break;
3119 case CHIP_KAVERI:
3120 /* XXX todo */
3121 case CHIP_KABINI:
3122 /* XXX todo */
3123 case CHIP_MULLINS:
3124 /* XXX todo */
3125 default:
3126 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3127 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3128 break;
3129 }
3130 } else {
3131 switch (sctx->screen->b.family) {
3132 case CHIP_TAHITI:
3133 case CHIP_PITCAIRN:
3134 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3135 break;
3136 case CHIP_VERDE:
3137 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3138 break;
3139 case CHIP_OLAND:
3140 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3141 break;
3142 case CHIP_HAINAN:
3143 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3144 break;
3145 default:
3146 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3147 break;
3148 }
3149 }
3150
3151 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3152 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3153 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3154 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3155 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3156 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3157 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3158
3159 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3160 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3161 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3162 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3163 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3164 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3165 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3166 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3167 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3168 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3169 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3170 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3171 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3172 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3173 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3174 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3175
3176 /* There is a hang if stencil is used and fast stencil is enabled
3177 * regardless of whether HTILE is depth-only or not.
3178 */
3179 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3180 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3181 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3182 S_02800C_FAST_STENCIL_DISABLE(1));
3183
3184 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3185 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3186 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3187
3188 if (sctx->b.chip_class >= CIK) {
3189 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3190 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3191 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3192 }
3193
3194 si_pm4_set_state(sctx, init, pm4);
3195 }