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radeonsi: clean up aniso state translation
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.info.r600_num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.num_render_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case UTIL_FORMAT_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case UTIL_FORMAT_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case UTIL_FORMAT_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case UTIL_FORMAT_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case UTIL_FORMAT_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
243 * is that:
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
248 *
249 * Another reason is to avoid a hang with dual source blending.
250 */
251 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
252 {
253 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
254 struct si_state_blend *blend = sctx->queued.named.blend;
255 uint32_t cb_target_mask = 0, i;
256
257 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
258 if (sctx->framebuffer.state.cbufs[i])
259 cb_target_mask |= 0xf << (4*i);
260
261 if (blend)
262 cb_target_mask &= blend->cb_target_mask;
263
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
267 *
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
269 */
270 if (blend && blend->dual_src_blend &&
271 sctx->ps_shader.cso &&
272 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
273 cb_target_mask = 0;
274
275 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
276
277 /* STONEY-specific register settings. */
278 if (sctx->b.family == CHIP_STONEY) {
279 unsigned spi_shader_col_format =
280 sctx->ps_shader.cso ?
281 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
282 unsigned sx_ps_downconvert = 0;
283 unsigned sx_blend_opt_epsilon = 0;
284 unsigned sx_blend_opt_control = 0;
285
286 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
287 struct r600_surface *surf =
288 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
289 unsigned format, swap, spi_format, colormask;
290 bool has_alpha, has_rgb;
291
292 if (!surf)
293 continue;
294
295 format = G_028C70_FORMAT(surf->cb_color_info);
296 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
297 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
298 colormask = (cb_target_mask >> (i * 4)) & 0xf;
299
300 /* Set if RGB and A are present. */
301 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
302
303 if (format == V_028C70_COLOR_8 ||
304 format == V_028C70_COLOR_16 ||
305 format == V_028C70_COLOR_32)
306 has_rgb = !has_alpha;
307 else
308 has_rgb = true;
309
310 /* Check the colormask and export format. */
311 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
312 has_rgb = false;
313 if (!(colormask & PIPE_MASK_A))
314 has_alpha = false;
315
316 if (spi_format == V_028714_SPI_SHADER_ZERO) {
317 has_rgb = false;
318 has_alpha = false;
319 }
320
321 /* Disable value checking for disabled channels. */
322 if (!has_rgb)
323 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
324 if (!has_alpha)
325 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
326
327 /* Enable down-conversion for 32bpp and smaller formats. */
328 switch (format) {
329 case V_028C70_COLOR_8:
330 case V_028C70_COLOR_8_8:
331 case V_028C70_COLOR_8_8_8_8:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
335 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
336 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
337 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
338 }
339 break;
340
341 case V_028C70_COLOR_5_6_5:
342 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
343 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
344 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
345 }
346 break;
347
348 case V_028C70_COLOR_1_5_5_5:
349 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
350 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
351 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
352 }
353 break;
354
355 case V_028C70_COLOR_4_4_4_4:
356 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
357 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
358 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
359 }
360 break;
361
362 case V_028C70_COLOR_32:
363 if (swap == V_0280A0_SWAP_STD &&
364 spi_format == V_028714_SPI_SHADER_32_R)
365 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
366 else if (swap == V_0280A0_SWAP_ALT_REV &&
367 spi_format == V_028714_SPI_SHADER_32_AR)
368 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
369 break;
370
371 case V_028C70_COLOR_16:
372 case V_028C70_COLOR_16_16:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
377 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
378 if (swap == V_0280A0_SWAP_STD ||
379 swap == V_0280A0_SWAP_STD_REV)
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
381 else
382 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
383 }
384 break;
385
386 case V_028C70_COLOR_10_11_11:
387 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
388 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
389 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
390 }
391 break;
392
393 case V_028C70_COLOR_2_10_10_10:
394 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
395 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
396 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
397 }
398 break;
399 }
400 }
401
402 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
403 sx_ps_downconvert = 0;
404 sx_blend_opt_epsilon = 0;
405 sx_blend_opt_control = 0;
406 }
407
408 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
409 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
412 }
413 }
414
415 /*
416 * Blender functions
417 */
418
419 static uint32_t si_translate_blend_function(int blend_func)
420 {
421 switch (blend_func) {
422 case PIPE_BLEND_ADD:
423 return V_028780_COMB_DST_PLUS_SRC;
424 case PIPE_BLEND_SUBTRACT:
425 return V_028780_COMB_SRC_MINUS_DST;
426 case PIPE_BLEND_REVERSE_SUBTRACT:
427 return V_028780_COMB_DST_MINUS_SRC;
428 case PIPE_BLEND_MIN:
429 return V_028780_COMB_MIN_DST_SRC;
430 case PIPE_BLEND_MAX:
431 return V_028780_COMB_MAX_DST_SRC;
432 default:
433 R600_ERR("Unknown blend function %d\n", blend_func);
434 assert(0);
435 break;
436 }
437 return 0;
438 }
439
440 static uint32_t si_translate_blend_factor(int blend_fact)
441 {
442 switch (blend_fact) {
443 case PIPE_BLENDFACTOR_ONE:
444 return V_028780_BLEND_ONE;
445 case PIPE_BLENDFACTOR_SRC_COLOR:
446 return V_028780_BLEND_SRC_COLOR;
447 case PIPE_BLENDFACTOR_SRC_ALPHA:
448 return V_028780_BLEND_SRC_ALPHA;
449 case PIPE_BLENDFACTOR_DST_ALPHA:
450 return V_028780_BLEND_DST_ALPHA;
451 case PIPE_BLENDFACTOR_DST_COLOR:
452 return V_028780_BLEND_DST_COLOR;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE;
455 case PIPE_BLENDFACTOR_CONST_COLOR:
456 return V_028780_BLEND_CONSTANT_COLOR;
457 case PIPE_BLENDFACTOR_CONST_ALPHA:
458 return V_028780_BLEND_CONSTANT_ALPHA;
459 case PIPE_BLENDFACTOR_ZERO:
460 return V_028780_BLEND_ZERO;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
473 case PIPE_BLENDFACTOR_SRC1_COLOR:
474 return V_028780_BLEND_SRC1_COLOR;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA:
476 return V_028780_BLEND_SRC1_ALPHA;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
478 return V_028780_BLEND_INV_SRC1_COLOR;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
480 return V_028780_BLEND_INV_SRC1_ALPHA;
481 default:
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
483 assert(0);
484 break;
485 }
486 return 0;
487 }
488
489 static uint32_t si_translate_blend_opt_function(int blend_func)
490 {
491 switch (blend_func) {
492 case PIPE_BLEND_ADD:
493 return V_028760_OPT_COMB_ADD;
494 case PIPE_BLEND_SUBTRACT:
495 return V_028760_OPT_COMB_SUBTRACT;
496 case PIPE_BLEND_REVERSE_SUBTRACT:
497 return V_028760_OPT_COMB_REVSUBTRACT;
498 case PIPE_BLEND_MIN:
499 return V_028760_OPT_COMB_MIN;
500 case PIPE_BLEND_MAX:
501 return V_028760_OPT_COMB_MAX;
502 default:
503 return V_028760_OPT_COMB_BLEND_DISABLED;
504 }
505 }
506
507 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
508 {
509 switch (blend_fact) {
510 case PIPE_BLENDFACTOR_ZERO:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
512 case PIPE_BLENDFACTOR_ONE:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
514 case PIPE_BLENDFACTOR_SRC_COLOR:
515 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
518 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
520 case PIPE_BLENDFACTOR_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
525 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
527 default:
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
529 }
530 }
531
532 /**
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 */
536 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
537 unsigned *dst_factor, unsigned expected_dst,
538 unsigned replacement_src)
539 {
540 if (*src_factor == expected_dst &&
541 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
542 *src_factor = PIPE_BLENDFACTOR_ZERO;
543 *dst_factor = replacement_src;
544
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func == PIPE_BLEND_SUBTRACT)
547 *func = PIPE_BLEND_REVERSE_SUBTRACT;
548 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
549 *func = PIPE_BLEND_SUBTRACT;
550 }
551 }
552
553 static bool si_blend_factor_uses_dst(unsigned factor)
554 {
555 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
556 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
559 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
560 }
561
562 static void *si_create_blend_state_mode(struct pipe_context *ctx,
563 const struct pipe_blend_state *state,
564 unsigned mode)
565 {
566 struct si_context *sctx = (struct si_context*)ctx;
567 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
568 struct si_pm4_state *pm4 = &blend->pm4;
569 uint32_t sx_mrt_blend_opt[8] = {0};
570 uint32_t color_control = 0;
571
572 if (!blend)
573 return NULL;
574
575 blend->alpha_to_coverage = state->alpha_to_coverage;
576 blend->alpha_to_one = state->alpha_to_one;
577 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
578
579 if (state->logicop_enable) {
580 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
581 } else {
582 color_control |= S_028808_ROP3(0xcc);
583 }
584
585 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
591
592 if (state->alpha_to_coverage)
593 blend->need_src_alpha_4bit |= 0xf;
594
595 blend->cb_target_mask = 0;
596 for (int i = 0; i < 8; i++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j = state->independent_blend_enable ? i : 0;
599
600 unsigned eqRGB = state->rt[j].rgb_func;
601 unsigned srcRGB = state->rt[j].rgb_src_factor;
602 unsigned dstRGB = state->rt[j].rgb_dst_factor;
603 unsigned eqA = state->rt[j].alpha_func;
604 unsigned srcA = state->rt[j].alpha_src_factor;
605 unsigned dstA = state->rt[j].alpha_dst_factor;
606
607 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
608 unsigned blend_cntl = 0;
609
610 sx_mrt_blend_opt[i] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
613
614 if (!state->rt[j].colormask)
615 continue;
616
617 /* cb_render_state will disable unused ones */
618 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
619
620 if (!state->rt[j].blend_enable) {
621 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 continue;
623 }
624
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
627 *
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
630 */
631 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
632 PIPE_BLENDFACTOR_DST_COLOR,
633 PIPE_BLENDFACTOR_SRC_COLOR);
634 si_blend_remove_dst(&eqA, &srcA, &dstA,
635 PIPE_BLENDFACTOR_DST_COLOR,
636 PIPE_BLENDFACTOR_SRC_COLOR);
637 si_blend_remove_dst(&eqA, &srcA, &dstA,
638 PIPE_BLENDFACTOR_DST_ALPHA,
639 PIPE_BLENDFACTOR_SRC_ALPHA);
640
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
643 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
644 srcA_opt = si_translate_blend_opt_factor(srcA, true);
645 dstA_opt = si_translate_blend_opt_factor(dstA, true);
646
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650 if (si_blend_factor_uses_dst(srcA))
651 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
652
653 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
654 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
656 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
657 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
658
659 /* Set the final value. */
660 sx_mrt_blend_opt[i] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt) |
665 S_028760_ALPHA_DST_OPT(dstA_opt) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
667
668 /* Set blend state. */
669 blend_cntl |= S_028780_ENABLE(1);
670 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
671 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
672 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
673
674 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
675 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
677 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
678 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
679 }
680 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
681
682 blend->blend_enable_4bit |= 0xf << (i * 4);
683
684 /* This is only important for formats without alpha. */
685 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
687 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
689 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
690 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
691 blend->need_src_alpha_4bit |= 0xf << (i * 4);
692 }
693
694 if (blend->cb_target_mask) {
695 color_control |= S_028808_MODE(mode);
696 } else {
697 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
698 }
699
700 if (sctx->b.family == CHIP_STONEY) {
701 for (int i = 0; i < 8; i++)
702 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
703 sx_mrt_blend_opt[i]);
704
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend->dual_src_blend || state->logicop_enable ||
707 mode == V_028808_CB_RESOLVE)
708 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
709 }
710
711 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
712 return blend;
713 }
714
715 static void *si_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
719 }
720
721 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
725 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
726 }
727
728 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
729 {
730 struct si_context *sctx = (struct si_context *)ctx;
731 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
732 }
733
734 static void si_set_blend_color(struct pipe_context *ctx,
735 const struct pipe_blend_color *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738
739 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->blend_color.state = *state;
743 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
744 }
745
746 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
747 {
748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
749
750 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
751 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
752 }
753
754 /*
755 * Clipping, scissors and viewport
756 */
757
758 static void si_set_clip_state(struct pipe_context *ctx,
759 const struct pipe_clip_state *state)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_constant_buffer cb;
763
764 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
765 return;
766
767 sctx->clip_state.state = *state;
768 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
769
770 cb.buffer = NULL;
771 cb.user_buffer = state->ucp;
772 cb.buffer_offset = 0;
773 cb.buffer_size = 4*4*8;
774 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
775 pipe_resource_reference(&cb.buffer, NULL);
776 }
777
778 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
779 {
780 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
781
782 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
783 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
784 }
785
786 #define SIX_BITS 0x3F
787
788 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
789 {
790 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
791 struct tgsi_shader_info *info = si_get_vs_info(sctx);
792 unsigned window_space =
793 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
794 unsigned clipdist_mask =
795 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
796
797 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
798 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
799 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
800 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
801 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
802 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
803 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
804 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
805 info->writes_edgeflag ||
806 info->writes_layer ||
807 info->writes_viewport_index) |
808 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
809 (sctx->queued.named.rasterizer->clip_plane_enable &
810 clipdist_mask));
811 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
812 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
813 (clipdist_mask ? 0 :
814 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
815 S_028810_CLIP_DISABLE(window_space));
816
817 /* reuse needs to be set off if we write oViewport */
818 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
819 S_028AB4_REUSE_OFF(info->writes_viewport_index));
820 }
821
822 static void si_set_scissor_states(struct pipe_context *ctx,
823 unsigned start_slot,
824 unsigned num_scissors,
825 const struct pipe_scissor_state *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828 int i;
829
830 for (i = 0; i < num_scissors; i++)
831 sctx->scissors.states[start_slot + i] = state[i];
832
833 if (!sctx->queued.named.rasterizer ||
834 !sctx->queued.named.rasterizer->scissor_enable)
835 return;
836
837 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
838 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
839 }
840
841 static void si_get_scissor_from_viewport(struct pipe_viewport_state *vp,
842 struct pipe_scissor_state *scissor)
843 {
844 /* These must be signed, unlike pipe_scissor_state. */
845 int minx, miny, maxx, maxy, tmp;
846
847 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
848 minx = -vp->scale[0] + vp->translate[0];
849 miny = -vp->scale[1] + vp->translate[1];
850 maxx = vp->scale[0] + vp->translate[0];
851 maxy = vp->scale[1] + vp->translate[1];
852
853 /* r600_draw_rectangle sets this. Disable the scissor. */
854 if (minx == -1 && miny == -1 && maxx == 1 && maxy == 1) {
855 minx = miny = 0;
856 maxx = maxy = 16384;
857 }
858
859 /* Handle inverted viewports. */
860 if (minx > maxx) {
861 tmp = minx;
862 minx = maxx;
863 maxx = tmp;
864 }
865 if (miny > maxy) {
866 tmp = miny;
867 miny = maxy;
868 maxy = tmp;
869 }
870
871 scissor->minx = CLAMP(minx, 0, 16384);
872 scissor->miny = CLAMP(miny, 0, 16384);
873 scissor->maxx = CLAMP(maxx, 0, 16384);
874 scissor->maxy = CLAMP(maxy, 0, 16384);
875 }
876
877 static void si_clip_scissor(struct pipe_scissor_state *out,
878 struct pipe_scissor_state *clip)
879 {
880 out->minx = MAX2(out->minx, clip->minx);
881 out->miny = MAX2(out->miny, clip->miny);
882 out->maxx = MIN2(out->maxx, clip->maxx);
883 out->maxy = MIN2(out->maxy, clip->maxy);
884 }
885
886 static void si_emit_one_scissor(struct radeon_winsys_cs *cs,
887 struct pipe_viewport_state *vp,
888 struct pipe_scissor_state *scissor)
889 {
890 struct pipe_scissor_state final;
891
892 /* Since the guard band disables clipping, we have to clip per-pixel
893 * using a scissor.
894 */
895 si_get_scissor_from_viewport(vp, &final);
896
897 if (scissor)
898 si_clip_scissor(&final, scissor);
899
900 radeon_emit(cs, S_028250_TL_X(final.minx) |
901 S_028250_TL_Y(final.miny) |
902 S_028250_WINDOW_OFFSET_DISABLE(1));
903 radeon_emit(cs, S_028254_BR_X(final.maxx) |
904 S_028254_BR_Y(final.maxy));
905 }
906
907 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
908 {
909 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
910 struct pipe_scissor_state *states = sctx->scissors.states;
911 unsigned mask = sctx->scissors.dirty_mask;
912 bool scissor_enable = sctx->queued.named.rasterizer->scissor_enable;
913
914 /* The simple case: Only 1 viewport is active. */
915 if (!si_get_vs_info(sctx)->writes_viewport_index) {
916 if (!(mask & 1))
917 return;
918
919 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
920 si_emit_one_scissor(cs, &sctx->viewports.states[0],
921 scissor_enable ? &states[0] : NULL);
922 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
923 return;
924 }
925
926 while (mask) {
927 int start, count, i;
928
929 u_bit_scan_consecutive_range(&mask, &start, &count);
930
931 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
932 start * 4 * 2, count * 2);
933 for (i = start; i < start+count; i++) {
934 si_emit_one_scissor(cs, &sctx->viewports.states[i],
935 scissor_enable ? &states[i] : NULL);
936 }
937 }
938 sctx->scissors.dirty_mask = 0;
939 }
940
941 static void si_set_viewport_states(struct pipe_context *ctx,
942 unsigned start_slot,
943 unsigned num_viewports,
944 const struct pipe_viewport_state *state)
945 {
946 struct si_context *sctx = (struct si_context *)ctx;
947 int i;
948
949 for (i = 0; i < num_viewports; i++)
950 sctx->viewports.states[start_slot + i] = state[i];
951
952 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
953 sctx->scissors.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
954 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
955 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
956 }
957
958 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
959 {
960 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
961 struct pipe_viewport_state *states = sctx->viewports.states;
962 unsigned mask = sctx->viewports.dirty_mask;
963
964 /* The simple case: Only 1 viewport is active. */
965 if (!si_get_vs_info(sctx)->writes_viewport_index) {
966 if (!(mask & 1))
967 return;
968
969 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
970 radeon_emit(cs, fui(states[0].scale[0]));
971 radeon_emit(cs, fui(states[0].translate[0]));
972 radeon_emit(cs, fui(states[0].scale[1]));
973 radeon_emit(cs, fui(states[0].translate[1]));
974 radeon_emit(cs, fui(states[0].scale[2]));
975 radeon_emit(cs, fui(states[0].translate[2]));
976 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
977 return;
978 }
979
980 while (mask) {
981 int start, count, i;
982
983 u_bit_scan_consecutive_range(&mask, &start, &count);
984
985 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
986 start * 4 * 6, count * 6);
987 for (i = start; i < start+count; i++) {
988 radeon_emit(cs, fui(states[i].scale[0]));
989 radeon_emit(cs, fui(states[i].translate[0]));
990 radeon_emit(cs, fui(states[i].scale[1]));
991 radeon_emit(cs, fui(states[i].translate[1]));
992 radeon_emit(cs, fui(states[i].scale[2]));
993 radeon_emit(cs, fui(states[i].translate[2]));
994 }
995 }
996 sctx->viewports.dirty_mask = 0;
997 }
998
999 /*
1000 * inferred state between framebuffer and rasterizer
1001 */
1002 static void si_update_poly_offset_state(struct si_context *sctx)
1003 {
1004 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1005
1006 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
1007 return;
1008
1009 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1010 case PIPE_FORMAT_Z16_UNORM:
1011 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
1012 break;
1013 default: /* 24-bit */
1014 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
1015 break;
1016 case PIPE_FORMAT_Z32_FLOAT:
1017 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1018 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
1019 break;
1020 }
1021 }
1022
1023 /*
1024 * Rasterizer
1025 */
1026
1027 static uint32_t si_translate_fill(uint32_t func)
1028 {
1029 switch(func) {
1030 case PIPE_POLYGON_MODE_FILL:
1031 return V_028814_X_DRAW_TRIANGLES;
1032 case PIPE_POLYGON_MODE_LINE:
1033 return V_028814_X_DRAW_LINES;
1034 case PIPE_POLYGON_MODE_POINT:
1035 return V_028814_X_DRAW_POINTS;
1036 default:
1037 assert(0);
1038 return V_028814_X_DRAW_POINTS;
1039 }
1040 }
1041
1042 static void *si_create_rs_state(struct pipe_context *ctx,
1043 const struct pipe_rasterizer_state *state)
1044 {
1045 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
1046 struct si_pm4_state *pm4 = &rs->pm4;
1047 unsigned tmp, i;
1048 float psize_min, psize_max;
1049
1050 if (!rs) {
1051 return NULL;
1052 }
1053
1054 rs->scissor_enable = state->scissor;
1055 rs->two_side = state->light_twoside;
1056 rs->multisample_enable = state->multisample;
1057 rs->force_persample_interp = state->force_persample_interp;
1058 rs->clip_plane_enable = state->clip_plane_enable;
1059 rs->line_stipple_enable = state->line_stipple_enable;
1060 rs->poly_stipple_enable = state->poly_stipple_enable;
1061 rs->line_smooth = state->line_smooth;
1062 rs->poly_smooth = state->poly_smooth;
1063 rs->uses_poly_offset = state->offset_point || state->offset_line ||
1064 state->offset_tri;
1065 rs->clamp_fragment_color = state->clamp_fragment_color;
1066 rs->flatshade = state->flatshade;
1067 rs->sprite_coord_enable = state->sprite_coord_enable;
1068 rs->rasterizer_discard = state->rasterizer_discard;
1069 rs->pa_sc_line_stipple = state->line_stipple_enable ?
1070 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1071 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1072 rs->pa_cl_clip_cntl =
1073 S_028810_PS_UCP_MODE(3) |
1074 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1075 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1076 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1077 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1078 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1079
1080 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
1081 S_0286D4_FLAT_SHADE_ENA(1) |
1082 S_0286D4_PNT_SPRITE_ENA(1) |
1083 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1084 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1085 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1086 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1087 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1088
1089 /* point size 12.4 fixed point */
1090 tmp = (unsigned)(state->point_size * 8.0);
1091 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1092
1093 if (state->point_size_per_vertex) {
1094 psize_min = util_get_min_point_size(state);
1095 psize_max = 8192;
1096 } else {
1097 /* Force the point size to be as if the vertex output was disabled. */
1098 psize_min = state->point_size;
1099 psize_max = state->point_size;
1100 }
1101 /* Divide by two, because 0.5 = 1 pixel. */
1102 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1103 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
1104 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
1105
1106 tmp = (unsigned)state->line_width * 8;
1107 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
1108 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
1109 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1110 S_028A48_MSAA_ENABLE(state->multisample ||
1111 state->poly_smooth ||
1112 state->line_smooth) |
1113 S_028A48_VPORT_SCISSOR_ENABLE(1));
1114
1115 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
1116 S_028BE4_PIX_CENTER(state->half_pixel_center) |
1117 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
1118
1119 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1120 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1121 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1122 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1123 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1124 S_028814_FACE(!state->front_ccw) |
1125 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1126 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1127 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1128 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
1129 state->fill_back != PIPE_POLYGON_MODE_FILL) |
1130 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1131 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
1132 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
1133 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
1134
1135 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1136 for (i = 0; i < 3; i++) {
1137 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1138 float offset_units = state->offset_units;
1139 float offset_scale = state->offset_scale * 16.0f;
1140
1141 switch (i) {
1142 case 0: /* 16-bit zbuffer */
1143 offset_units *= 4.0f;
1144 break;
1145 case 1: /* 24-bit zbuffer */
1146 offset_units *= 2.0f;
1147 break;
1148 case 2: /* 32-bit zbuffer */
1149 offset_units *= 1.0f;
1150 break;
1151 }
1152
1153 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1154 fui(offset_scale));
1155 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1156 fui(offset_units));
1157 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1158 fui(offset_scale));
1159 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1160 fui(offset_units));
1161 }
1162
1163 return rs;
1164 }
1165
1166 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1167 {
1168 struct si_context *sctx = (struct si_context *)ctx;
1169 struct si_state_rasterizer *old_rs =
1170 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1171 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1172
1173 if (!state)
1174 return;
1175
1176 if (sctx->framebuffer.nr_samples > 1 &&
1177 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1178 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1179
1180 if (!old_rs || old_rs->scissor_enable != rs->scissor_enable) {
1181 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1182 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1183 }
1184
1185 si_pm4_bind_state(sctx, rasterizer, rs);
1186 si_update_poly_offset_state(sctx);
1187
1188 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1189 }
1190
1191 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1192 {
1193 struct si_context *sctx = (struct si_context *)ctx;
1194
1195 if (sctx->queued.named.rasterizer == state)
1196 si_pm4_bind_state(sctx, poly_offset, NULL);
1197 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1198 }
1199
1200 /*
1201 * infeered state between dsa and stencil ref
1202 */
1203 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1204 {
1205 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1206 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1207 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1208
1209 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1210 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1211 S_028430_STENCILMASK(dsa->valuemask[0]) |
1212 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1213 S_028430_STENCILOPVAL(1));
1214 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1215 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1216 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1217 S_028434_STENCILOPVAL_BF(1));
1218 }
1219
1220 static void si_set_stencil_ref(struct pipe_context *ctx,
1221 const struct pipe_stencil_ref *state)
1222 {
1223 struct si_context *sctx = (struct si_context *)ctx;
1224
1225 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1226 return;
1227
1228 sctx->stencil_ref.state = *state;
1229 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1230 }
1231
1232
1233 /*
1234 * DSA
1235 */
1236
1237 static uint32_t si_translate_stencil_op(int s_op)
1238 {
1239 switch (s_op) {
1240 case PIPE_STENCIL_OP_KEEP:
1241 return V_02842C_STENCIL_KEEP;
1242 case PIPE_STENCIL_OP_ZERO:
1243 return V_02842C_STENCIL_ZERO;
1244 case PIPE_STENCIL_OP_REPLACE:
1245 return V_02842C_STENCIL_REPLACE_TEST;
1246 case PIPE_STENCIL_OP_INCR:
1247 return V_02842C_STENCIL_ADD_CLAMP;
1248 case PIPE_STENCIL_OP_DECR:
1249 return V_02842C_STENCIL_SUB_CLAMP;
1250 case PIPE_STENCIL_OP_INCR_WRAP:
1251 return V_02842C_STENCIL_ADD_WRAP;
1252 case PIPE_STENCIL_OP_DECR_WRAP:
1253 return V_02842C_STENCIL_SUB_WRAP;
1254 case PIPE_STENCIL_OP_INVERT:
1255 return V_02842C_STENCIL_INVERT;
1256 default:
1257 R600_ERR("Unknown stencil op %d", s_op);
1258 assert(0);
1259 break;
1260 }
1261 return 0;
1262 }
1263
1264 static void *si_create_dsa_state(struct pipe_context *ctx,
1265 const struct pipe_depth_stencil_alpha_state *state)
1266 {
1267 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1268 struct si_pm4_state *pm4 = &dsa->pm4;
1269 unsigned db_depth_control;
1270 uint32_t db_stencil_control = 0;
1271
1272 if (!dsa) {
1273 return NULL;
1274 }
1275
1276 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1277 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1278 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1279 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1280
1281 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1282 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1283 S_028800_ZFUNC(state->depth.func) |
1284 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1285
1286 /* stencil */
1287 if (state->stencil[0].enabled) {
1288 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1289 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1290 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1291 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1292 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1293
1294 if (state->stencil[1].enabled) {
1295 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1296 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1297 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1298 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1299 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1300 }
1301 }
1302
1303 /* alpha */
1304 if (state->alpha.enabled) {
1305 dsa->alpha_func = state->alpha.func;
1306
1307 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1308 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1309 } else {
1310 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1311 }
1312
1313 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1314 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1315 if (state->depth.bounds_test) {
1316 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1317 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1318 }
1319
1320 return dsa;
1321 }
1322
1323 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1324 {
1325 struct si_context *sctx = (struct si_context *)ctx;
1326 struct si_state_dsa *dsa = state;
1327
1328 if (!state)
1329 return;
1330
1331 si_pm4_bind_state(sctx, dsa, dsa);
1332
1333 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1334 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1335 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1336 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1337 }
1338 }
1339
1340 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1341 {
1342 struct si_context *sctx = (struct si_context *)ctx;
1343 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1344 }
1345
1346 static void *si_create_db_flush_dsa(struct si_context *sctx)
1347 {
1348 struct pipe_depth_stencil_alpha_state dsa = {};
1349
1350 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1351 }
1352
1353 /* DB RENDER STATE */
1354
1355 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1356 {
1357 struct si_context *sctx = (struct si_context*)ctx;
1358
1359 /* Pipeline stat & streamout queries. */
1360 if (enable) {
1361 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1362 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1363 } else {
1364 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1365 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1366 }
1367
1368 /* Occlusion queries. */
1369 if (sctx->occlusion_queries_disabled != !enable) {
1370 sctx->occlusion_queries_disabled = !enable;
1371 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1372 }
1373 }
1374
1375 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1376 {
1377 struct si_context *sctx = (struct si_context*)ctx;
1378
1379 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1380 }
1381
1382 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1383 {
1384 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1385 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1386 unsigned db_shader_control;
1387
1388 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1389
1390 /* DB_RENDER_CONTROL */
1391 if (sctx->dbcb_depth_copy_enabled ||
1392 sctx->dbcb_stencil_copy_enabled) {
1393 radeon_emit(cs,
1394 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1395 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1396 S_028000_COPY_CENTROID(1) |
1397 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1398 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1399 radeon_emit(cs,
1400 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1401 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1402 } else {
1403 radeon_emit(cs,
1404 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1405 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1406 }
1407
1408 /* DB_COUNT_CONTROL (occlusion queries) */
1409 if (sctx->b.num_occlusion_queries > 0 &&
1410 !sctx->occlusion_queries_disabled) {
1411 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1412
1413 if (sctx->b.chip_class >= CIK) {
1414 radeon_emit(cs,
1415 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1416 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1417 S_028004_ZPASS_ENABLE(1) |
1418 S_028004_SLICE_EVEN_ENABLE(1) |
1419 S_028004_SLICE_ODD_ENABLE(1));
1420 } else {
1421 radeon_emit(cs,
1422 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1423 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1424 }
1425 } else {
1426 /* Disable occlusion queries. */
1427 if (sctx->b.chip_class >= CIK) {
1428 radeon_emit(cs, 0);
1429 } else {
1430 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1431 }
1432 }
1433
1434 /* DB_RENDER_OVERRIDE2 */
1435 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1436 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1437 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1438
1439 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1440 sctx->ps_db_shader_control;
1441
1442 /* Bug workaround for smoothing (overrasterization) on SI. */
1443 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1444 db_shader_control &= C_02880C_Z_ORDER;
1445 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1446 }
1447
1448 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1449 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1450 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1451
1452 if (sctx->b.family == CHIP_STONEY &&
1453 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1454 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1455
1456 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1457 db_shader_control);
1458 }
1459
1460 /*
1461 * format translation
1462 */
1463 static uint32_t si_translate_colorformat(enum pipe_format format)
1464 {
1465 const struct util_format_description *desc = util_format_description(format);
1466
1467 #define HAS_SIZE(x,y,z,w) \
1468 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1469 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1470
1471 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1472 return V_028C70_COLOR_10_11_11;
1473
1474 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1475 return V_028C70_COLOR_INVALID;
1476
1477 switch (desc->nr_channels) {
1478 case 1:
1479 switch (desc->channel[0].size) {
1480 case 8:
1481 return V_028C70_COLOR_8;
1482 case 16:
1483 return V_028C70_COLOR_16;
1484 case 32:
1485 return V_028C70_COLOR_32;
1486 }
1487 break;
1488 case 2:
1489 if (desc->channel[0].size == desc->channel[1].size) {
1490 switch (desc->channel[0].size) {
1491 case 8:
1492 return V_028C70_COLOR_8_8;
1493 case 16:
1494 return V_028C70_COLOR_16_16;
1495 case 32:
1496 return V_028C70_COLOR_32_32;
1497 }
1498 } else if (HAS_SIZE(8,24,0,0)) {
1499 return V_028C70_COLOR_24_8;
1500 } else if (HAS_SIZE(24,8,0,0)) {
1501 return V_028C70_COLOR_8_24;
1502 }
1503 break;
1504 case 3:
1505 if (HAS_SIZE(5,6,5,0)) {
1506 return V_028C70_COLOR_5_6_5;
1507 } else if (HAS_SIZE(32,8,24,0)) {
1508 return V_028C70_COLOR_X24_8_32_FLOAT;
1509 }
1510 break;
1511 case 4:
1512 if (desc->channel[0].size == desc->channel[1].size &&
1513 desc->channel[0].size == desc->channel[2].size &&
1514 desc->channel[0].size == desc->channel[3].size) {
1515 switch (desc->channel[0].size) {
1516 case 4:
1517 return V_028C70_COLOR_4_4_4_4;
1518 case 8:
1519 return V_028C70_COLOR_8_8_8_8;
1520 case 16:
1521 return V_028C70_COLOR_16_16_16_16;
1522 case 32:
1523 return V_028C70_COLOR_32_32_32_32;
1524 }
1525 } else if (HAS_SIZE(5,5,5,1)) {
1526 return V_028C70_COLOR_1_5_5_5;
1527 } else if (HAS_SIZE(10,10,10,2)) {
1528 return V_028C70_COLOR_2_10_10_10;
1529 }
1530 break;
1531 }
1532 return V_028C70_COLOR_INVALID;
1533 }
1534
1535 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1536 {
1537 if (SI_BIG_ENDIAN) {
1538 switch(colorformat) {
1539 /* 8-bit buffers. */
1540 case V_028C70_COLOR_8:
1541 return V_028C70_ENDIAN_NONE;
1542
1543 /* 16-bit buffers. */
1544 case V_028C70_COLOR_5_6_5:
1545 case V_028C70_COLOR_1_5_5_5:
1546 case V_028C70_COLOR_4_4_4_4:
1547 case V_028C70_COLOR_16:
1548 case V_028C70_COLOR_8_8:
1549 return V_028C70_ENDIAN_8IN16;
1550
1551 /* 32-bit buffers. */
1552 case V_028C70_COLOR_8_8_8_8:
1553 case V_028C70_COLOR_2_10_10_10:
1554 case V_028C70_COLOR_8_24:
1555 case V_028C70_COLOR_24_8:
1556 case V_028C70_COLOR_16_16:
1557 return V_028C70_ENDIAN_8IN32;
1558
1559 /* 64-bit buffers. */
1560 case V_028C70_COLOR_16_16_16_16:
1561 return V_028C70_ENDIAN_8IN16;
1562
1563 case V_028C70_COLOR_32_32:
1564 return V_028C70_ENDIAN_8IN32;
1565
1566 /* 128-bit buffers. */
1567 case V_028C70_COLOR_32_32_32_32:
1568 return V_028C70_ENDIAN_8IN32;
1569 default:
1570 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1571 }
1572 } else {
1573 return V_028C70_ENDIAN_NONE;
1574 }
1575 }
1576
1577 static uint32_t si_translate_dbformat(enum pipe_format format)
1578 {
1579 switch (format) {
1580 case PIPE_FORMAT_Z16_UNORM:
1581 return V_028040_Z_16;
1582 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1583 case PIPE_FORMAT_X8Z24_UNORM:
1584 case PIPE_FORMAT_Z24X8_UNORM:
1585 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1586 return V_028040_Z_24; /* deprecated on SI */
1587 case PIPE_FORMAT_Z32_FLOAT:
1588 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1589 return V_028040_Z_32_FLOAT;
1590 default:
1591 return V_028040_Z_INVALID;
1592 }
1593 }
1594
1595 /*
1596 * Texture translation
1597 */
1598
1599 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1600 enum pipe_format format,
1601 const struct util_format_description *desc,
1602 int first_non_void)
1603 {
1604 struct si_screen *sscreen = (struct si_screen*)screen;
1605 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1606 sscreen->b.info.drm_minor >= 31) ||
1607 sscreen->b.info.drm_major == 3;
1608 boolean uniform = TRUE;
1609 int i;
1610
1611 /* Colorspace (return non-RGB formats directly). */
1612 switch (desc->colorspace) {
1613 /* Depth stencil formats */
1614 case UTIL_FORMAT_COLORSPACE_ZS:
1615 switch (format) {
1616 case PIPE_FORMAT_Z16_UNORM:
1617 return V_008F14_IMG_DATA_FORMAT_16;
1618 case PIPE_FORMAT_X24S8_UINT:
1619 case PIPE_FORMAT_Z24X8_UNORM:
1620 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1621 return V_008F14_IMG_DATA_FORMAT_8_24;
1622 case PIPE_FORMAT_X8Z24_UNORM:
1623 case PIPE_FORMAT_S8X24_UINT:
1624 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1625 return V_008F14_IMG_DATA_FORMAT_24_8;
1626 case PIPE_FORMAT_S8_UINT:
1627 return V_008F14_IMG_DATA_FORMAT_8;
1628 case PIPE_FORMAT_Z32_FLOAT:
1629 return V_008F14_IMG_DATA_FORMAT_32;
1630 case PIPE_FORMAT_X32_S8X24_UINT:
1631 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1632 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1633 default:
1634 goto out_unknown;
1635 }
1636
1637 case UTIL_FORMAT_COLORSPACE_YUV:
1638 goto out_unknown; /* TODO */
1639
1640 case UTIL_FORMAT_COLORSPACE_SRGB:
1641 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1642 goto out_unknown;
1643 break;
1644
1645 default:
1646 break;
1647 }
1648
1649 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1650 if (!enable_compressed_formats)
1651 goto out_unknown;
1652
1653 switch (format) {
1654 case PIPE_FORMAT_RGTC1_SNORM:
1655 case PIPE_FORMAT_LATC1_SNORM:
1656 case PIPE_FORMAT_RGTC1_UNORM:
1657 case PIPE_FORMAT_LATC1_UNORM:
1658 return V_008F14_IMG_DATA_FORMAT_BC4;
1659 case PIPE_FORMAT_RGTC2_SNORM:
1660 case PIPE_FORMAT_LATC2_SNORM:
1661 case PIPE_FORMAT_RGTC2_UNORM:
1662 case PIPE_FORMAT_LATC2_UNORM:
1663 return V_008F14_IMG_DATA_FORMAT_BC5;
1664 default:
1665 goto out_unknown;
1666 }
1667 }
1668
1669 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1670 sscreen->b.family >= CHIP_STONEY) {
1671 switch (format) {
1672 case PIPE_FORMAT_ETC1_RGB8:
1673 case PIPE_FORMAT_ETC2_RGB8:
1674 case PIPE_FORMAT_ETC2_SRGB8:
1675 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1676 case PIPE_FORMAT_ETC2_RGB8A1:
1677 case PIPE_FORMAT_ETC2_SRGB8A1:
1678 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1679 case PIPE_FORMAT_ETC2_RGBA8:
1680 case PIPE_FORMAT_ETC2_SRGBA8:
1681 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1682 case PIPE_FORMAT_ETC2_R11_UNORM:
1683 case PIPE_FORMAT_ETC2_R11_SNORM:
1684 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1685 case PIPE_FORMAT_ETC2_RG11_UNORM:
1686 case PIPE_FORMAT_ETC2_RG11_SNORM:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1688 default:
1689 goto out_unknown;
1690 }
1691 }
1692
1693 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1694 if (!enable_compressed_formats)
1695 goto out_unknown;
1696
1697 switch (format) {
1698 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1699 case PIPE_FORMAT_BPTC_SRGBA:
1700 return V_008F14_IMG_DATA_FORMAT_BC7;
1701 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1702 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1703 return V_008F14_IMG_DATA_FORMAT_BC6;
1704 default:
1705 goto out_unknown;
1706 }
1707 }
1708
1709 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1710 switch (format) {
1711 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1712 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1713 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1714 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1715 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1716 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1717 default:
1718 goto out_unknown;
1719 }
1720 }
1721
1722 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1723 if (!enable_compressed_formats)
1724 goto out_unknown;
1725
1726 if (!util_format_s3tc_enabled) {
1727 goto out_unknown;
1728 }
1729
1730 switch (format) {
1731 case PIPE_FORMAT_DXT1_RGB:
1732 case PIPE_FORMAT_DXT1_RGBA:
1733 case PIPE_FORMAT_DXT1_SRGB:
1734 case PIPE_FORMAT_DXT1_SRGBA:
1735 return V_008F14_IMG_DATA_FORMAT_BC1;
1736 case PIPE_FORMAT_DXT3_RGBA:
1737 case PIPE_FORMAT_DXT3_SRGBA:
1738 return V_008F14_IMG_DATA_FORMAT_BC2;
1739 case PIPE_FORMAT_DXT5_RGBA:
1740 case PIPE_FORMAT_DXT5_SRGBA:
1741 return V_008F14_IMG_DATA_FORMAT_BC3;
1742 default:
1743 goto out_unknown;
1744 }
1745 }
1746
1747 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1748 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1749 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1750 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1751 }
1752
1753 /* R8G8Bx_SNORM - TODO CxV8U8 */
1754
1755 /* See whether the components are of the same size. */
1756 for (i = 1; i < desc->nr_channels; i++) {
1757 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1758 }
1759
1760 /* Non-uniform formats. */
1761 if (!uniform) {
1762 switch(desc->nr_channels) {
1763 case 3:
1764 if (desc->channel[0].size == 5 &&
1765 desc->channel[1].size == 6 &&
1766 desc->channel[2].size == 5) {
1767 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1768 }
1769 goto out_unknown;
1770 case 4:
1771 if (desc->channel[0].size == 5 &&
1772 desc->channel[1].size == 5 &&
1773 desc->channel[2].size == 5 &&
1774 desc->channel[3].size == 1) {
1775 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1776 }
1777 if (desc->channel[0].size == 10 &&
1778 desc->channel[1].size == 10 &&
1779 desc->channel[2].size == 10 &&
1780 desc->channel[3].size == 2) {
1781 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1782 }
1783 goto out_unknown;
1784 }
1785 goto out_unknown;
1786 }
1787
1788 if (first_non_void < 0 || first_non_void > 3)
1789 goto out_unknown;
1790
1791 /* uniform formats */
1792 switch (desc->channel[first_non_void].size) {
1793 case 4:
1794 switch (desc->nr_channels) {
1795 #if 0 /* Not supported for render targets */
1796 case 2:
1797 return V_008F14_IMG_DATA_FORMAT_4_4;
1798 #endif
1799 case 4:
1800 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1801 }
1802 break;
1803 case 8:
1804 switch (desc->nr_channels) {
1805 case 1:
1806 return V_008F14_IMG_DATA_FORMAT_8;
1807 case 2:
1808 return V_008F14_IMG_DATA_FORMAT_8_8;
1809 case 4:
1810 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1811 }
1812 break;
1813 case 16:
1814 switch (desc->nr_channels) {
1815 case 1:
1816 return V_008F14_IMG_DATA_FORMAT_16;
1817 case 2:
1818 return V_008F14_IMG_DATA_FORMAT_16_16;
1819 case 4:
1820 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1821 }
1822 break;
1823 case 32:
1824 switch (desc->nr_channels) {
1825 case 1:
1826 return V_008F14_IMG_DATA_FORMAT_32;
1827 case 2:
1828 return V_008F14_IMG_DATA_FORMAT_32_32;
1829 #if 0 /* Not supported for render targets */
1830 case 3:
1831 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1832 #endif
1833 case 4:
1834 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1835 }
1836 }
1837
1838 out_unknown:
1839 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1840 return ~0;
1841 }
1842
1843 static unsigned si_tex_wrap(unsigned wrap)
1844 {
1845 switch (wrap) {
1846 default:
1847 case PIPE_TEX_WRAP_REPEAT:
1848 return V_008F30_SQ_TEX_WRAP;
1849 case PIPE_TEX_WRAP_CLAMP:
1850 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1851 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1852 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1853 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1854 return V_008F30_SQ_TEX_CLAMP_BORDER;
1855 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1856 return V_008F30_SQ_TEX_MIRROR;
1857 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1858 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1859 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1860 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1861 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1862 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1863 }
1864 }
1865
1866 static unsigned si_tex_mipfilter(unsigned filter)
1867 {
1868 switch (filter) {
1869 case PIPE_TEX_MIPFILTER_NEAREST:
1870 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1871 case PIPE_TEX_MIPFILTER_LINEAR:
1872 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1873 default:
1874 case PIPE_TEX_MIPFILTER_NONE:
1875 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1876 }
1877 }
1878
1879 static unsigned si_tex_compare(unsigned compare)
1880 {
1881 switch (compare) {
1882 default:
1883 case PIPE_FUNC_NEVER:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1885 case PIPE_FUNC_LESS:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1887 case PIPE_FUNC_EQUAL:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1889 case PIPE_FUNC_LEQUAL:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1891 case PIPE_FUNC_GREATER:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1893 case PIPE_FUNC_NOTEQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1895 case PIPE_FUNC_GEQUAL:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1897 case PIPE_FUNC_ALWAYS:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1899 }
1900 }
1901
1902 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1903 unsigned nr_samples)
1904 {
1905 if (view_target == PIPE_TEXTURE_CUBE ||
1906 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1907 res_target = view_target;
1908
1909 switch (res_target) {
1910 default:
1911 case PIPE_TEXTURE_1D:
1912 return V_008F1C_SQ_RSRC_IMG_1D;
1913 case PIPE_TEXTURE_1D_ARRAY:
1914 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1915 case PIPE_TEXTURE_2D:
1916 case PIPE_TEXTURE_RECT:
1917 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1918 V_008F1C_SQ_RSRC_IMG_2D;
1919 case PIPE_TEXTURE_2D_ARRAY:
1920 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1921 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1922 case PIPE_TEXTURE_3D:
1923 return V_008F1C_SQ_RSRC_IMG_3D;
1924 case PIPE_TEXTURE_CUBE:
1925 case PIPE_TEXTURE_CUBE_ARRAY:
1926 return V_008F1C_SQ_RSRC_IMG_CUBE;
1927 }
1928 }
1929
1930 /*
1931 * Format support testing
1932 */
1933
1934 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1935 {
1936 return si_translate_texformat(screen, format, util_format_description(format),
1937 util_format_get_first_non_void_channel(format)) != ~0U;
1938 }
1939
1940 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1941 const struct util_format_description *desc,
1942 int first_non_void)
1943 {
1944 unsigned type = desc->channel[first_non_void].type;
1945 int i;
1946
1947 if (type == UTIL_FORMAT_TYPE_FIXED)
1948 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1949
1950 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1951 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1952
1953 if (desc->nr_channels == 4 &&
1954 desc->channel[0].size == 10 &&
1955 desc->channel[1].size == 10 &&
1956 desc->channel[2].size == 10 &&
1957 desc->channel[3].size == 2)
1958 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1959
1960 /* See whether the components are of the same size. */
1961 for (i = 0; i < desc->nr_channels; i++) {
1962 if (desc->channel[first_non_void].size != desc->channel[i].size)
1963 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1964 }
1965
1966 switch (desc->channel[first_non_void].size) {
1967 case 8:
1968 switch (desc->nr_channels) {
1969 case 1:
1970 return V_008F0C_BUF_DATA_FORMAT_8;
1971 case 2:
1972 return V_008F0C_BUF_DATA_FORMAT_8_8;
1973 case 3:
1974 case 4:
1975 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1976 }
1977 break;
1978 case 16:
1979 switch (desc->nr_channels) {
1980 case 1:
1981 return V_008F0C_BUF_DATA_FORMAT_16;
1982 case 2:
1983 return V_008F0C_BUF_DATA_FORMAT_16_16;
1984 case 3:
1985 case 4:
1986 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1987 }
1988 break;
1989 case 32:
1990 /* From the Southern Islands ISA documentation about MTBUF:
1991 * 'Memory reads of data in memory that is 32 or 64 bits do not
1992 * undergo any format conversion.'
1993 */
1994 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1995 !desc->channel[first_non_void].pure_integer)
1996 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1997
1998 switch (desc->nr_channels) {
1999 case 1:
2000 return V_008F0C_BUF_DATA_FORMAT_32;
2001 case 2:
2002 return V_008F0C_BUF_DATA_FORMAT_32_32;
2003 case 3:
2004 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2005 case 4:
2006 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2007 }
2008 break;
2009 }
2010
2011 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2012 }
2013
2014 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2015 const struct util_format_description *desc,
2016 int first_non_void)
2017 {
2018 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2019 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2020
2021 switch (desc->channel[first_non_void].type) {
2022 case UTIL_FORMAT_TYPE_SIGNED:
2023 if (desc->channel[first_non_void].normalized)
2024 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2025 else if (desc->channel[first_non_void].pure_integer)
2026 return V_008F0C_BUF_NUM_FORMAT_SINT;
2027 else
2028 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2029 break;
2030 case UTIL_FORMAT_TYPE_UNSIGNED:
2031 if (desc->channel[first_non_void].normalized)
2032 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2033 else if (desc->channel[first_non_void].pure_integer)
2034 return V_008F0C_BUF_NUM_FORMAT_UINT;
2035 else
2036 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2037 break;
2038 case UTIL_FORMAT_TYPE_FLOAT:
2039 default:
2040 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2041 }
2042 }
2043
2044 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
2045 {
2046 const struct util_format_description *desc;
2047 int first_non_void;
2048 unsigned data_format;
2049
2050 desc = util_format_description(format);
2051 first_non_void = util_format_get_first_non_void_channel(format);
2052 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2053 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
2054 }
2055
2056 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2057 {
2058 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2059 r600_translate_colorswap(format) != ~0U;
2060 }
2061
2062 static bool si_is_zs_format_supported(enum pipe_format format)
2063 {
2064 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2065 }
2066
2067 boolean si_is_format_supported(struct pipe_screen *screen,
2068 enum pipe_format format,
2069 enum pipe_texture_target target,
2070 unsigned sample_count,
2071 unsigned usage)
2072 {
2073 unsigned retval = 0;
2074
2075 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2076 R600_ERR("r600: unsupported texture type %d\n", target);
2077 return FALSE;
2078 }
2079
2080 if (!util_format_is_supported(format, usage))
2081 return FALSE;
2082
2083 if (sample_count > 1) {
2084 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2085 return FALSE;
2086
2087 switch (sample_count) {
2088 case 2:
2089 case 4:
2090 case 8:
2091 break;
2092 case 16:
2093 if (format == PIPE_FORMAT_NONE)
2094 return TRUE;
2095 else
2096 return FALSE;
2097 default:
2098 return FALSE;
2099 }
2100 }
2101
2102 if (usage & PIPE_BIND_SAMPLER_VIEW) {
2103 if (target == PIPE_BUFFER) {
2104 if (si_is_vertex_format_supported(screen, format))
2105 retval |= PIPE_BIND_SAMPLER_VIEW;
2106 } else {
2107 if (si_is_sampler_format_supported(screen, format))
2108 retval |= PIPE_BIND_SAMPLER_VIEW;
2109 }
2110 }
2111
2112 if ((usage & (PIPE_BIND_RENDER_TARGET |
2113 PIPE_BIND_DISPLAY_TARGET |
2114 PIPE_BIND_SCANOUT |
2115 PIPE_BIND_SHARED |
2116 PIPE_BIND_BLENDABLE)) &&
2117 si_is_colorbuffer_format_supported(format)) {
2118 retval |= usage &
2119 (PIPE_BIND_RENDER_TARGET |
2120 PIPE_BIND_DISPLAY_TARGET |
2121 PIPE_BIND_SCANOUT |
2122 PIPE_BIND_SHARED);
2123 if (!util_format_is_pure_integer(format) &&
2124 !util_format_is_depth_or_stencil(format))
2125 retval |= usage & PIPE_BIND_BLENDABLE;
2126 }
2127
2128 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2129 si_is_zs_format_supported(format)) {
2130 retval |= PIPE_BIND_DEPTH_STENCIL;
2131 }
2132
2133 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
2134 si_is_vertex_format_supported(screen, format)) {
2135 retval |= PIPE_BIND_VERTEX_BUFFER;
2136 }
2137
2138 if (usage & PIPE_BIND_TRANSFER_READ)
2139 retval |= PIPE_BIND_TRANSFER_READ;
2140 if (usage & PIPE_BIND_TRANSFER_WRITE)
2141 retval |= PIPE_BIND_TRANSFER_WRITE;
2142
2143 if ((usage & PIPE_BIND_LINEAR) &&
2144 !util_format_is_compressed(format) &&
2145 !(usage & PIPE_BIND_DEPTH_STENCIL))
2146 retval |= PIPE_BIND_LINEAR;
2147
2148 return retval == usage;
2149 }
2150
2151 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
2152 {
2153 unsigned tile_mode_index = 0;
2154
2155 if (stencil) {
2156 tile_mode_index = rtex->surface.stencil_tiling_index[level];
2157 } else {
2158 tile_mode_index = rtex->surface.tiling_index[level];
2159 }
2160 return tile_mode_index;
2161 }
2162
2163 /*
2164 * framebuffer handling
2165 */
2166
2167 static void si_choose_spi_color_formats(struct r600_surface *surf,
2168 unsigned format, unsigned swap,
2169 unsigned ntype, bool is_depth)
2170 {
2171 /* Alpha is needed for alpha-to-coverage.
2172 * Blending may be with or without alpha.
2173 */
2174 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2175 unsigned alpha = 0; /* exports alpha, but may not support blending */
2176 unsigned blend = 0; /* supports blending, but may not export alpha */
2177 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2178
2179 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2180 * Other chips have multiple choices, though they are not necessarily better.
2181 */
2182 switch (format) {
2183 case V_028C70_COLOR_5_6_5:
2184 case V_028C70_COLOR_1_5_5_5:
2185 case V_028C70_COLOR_5_5_5_1:
2186 case V_028C70_COLOR_4_4_4_4:
2187 case V_028C70_COLOR_10_11_11:
2188 case V_028C70_COLOR_11_11_10:
2189 case V_028C70_COLOR_8:
2190 case V_028C70_COLOR_8_8:
2191 case V_028C70_COLOR_8_8_8_8:
2192 case V_028C70_COLOR_10_10_10_2:
2193 case V_028C70_COLOR_2_10_10_10:
2194 if (ntype == V_028C70_NUMBER_UINT)
2195 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2196 else if (ntype == V_028C70_NUMBER_SINT)
2197 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2198 else
2199 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2200 break;
2201
2202 case V_028C70_COLOR_16:
2203 case V_028C70_COLOR_16_16:
2204 case V_028C70_COLOR_16_16_16_16:
2205 if (ntype == V_028C70_NUMBER_UNORM ||
2206 ntype == V_028C70_NUMBER_SNORM) {
2207 /* UNORM16 and SNORM16 don't support blending */
2208 if (ntype == V_028C70_NUMBER_UNORM)
2209 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2210 else
2211 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2212
2213 /* Use 32 bits per channel for blending. */
2214 if (format == V_028C70_COLOR_16) {
2215 if (swap == V_028C70_SWAP_STD) { /* R */
2216 blend = V_028714_SPI_SHADER_32_R;
2217 blend_alpha = V_028714_SPI_SHADER_32_AR;
2218 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2219 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2220 else
2221 assert(0);
2222 } else if (format == V_028C70_COLOR_16_16) {
2223 if (swap == V_028C70_SWAP_STD) { /* RG */
2224 blend = V_028714_SPI_SHADER_32_GR;
2225 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2226 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2227 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2228 else
2229 assert(0);
2230 } else /* 16_16_16_16 */
2231 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2232 } else if (ntype == V_028C70_NUMBER_UINT)
2233 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2234 else if (ntype == V_028C70_NUMBER_SINT)
2235 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2236 else if (ntype == V_028C70_NUMBER_FLOAT)
2237 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2238 else
2239 assert(0);
2240 break;
2241
2242 case V_028C70_COLOR_32:
2243 if (swap == V_028C70_SWAP_STD) { /* R */
2244 blend = normal = V_028714_SPI_SHADER_32_R;
2245 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2246 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2247 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2248 else
2249 assert(0);
2250 break;
2251
2252 case V_028C70_COLOR_32_32:
2253 if (swap == V_028C70_SWAP_STD) { /* RG */
2254 blend = normal = V_028714_SPI_SHADER_32_GR;
2255 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2256 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2257 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2258 else
2259 assert(0);
2260 break;
2261
2262 case V_028C70_COLOR_32_32_32_32:
2263 case V_028C70_COLOR_8_24:
2264 case V_028C70_COLOR_24_8:
2265 case V_028C70_COLOR_X24_8_32_FLOAT:
2266 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2267 break;
2268
2269 default:
2270 assert(0);
2271 return;
2272 }
2273
2274 /* The DB->CB copy needs 32_ABGR. */
2275 if (is_depth)
2276 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2277
2278 surf->spi_shader_col_format = normal;
2279 surf->spi_shader_col_format_alpha = alpha;
2280 surf->spi_shader_col_format_blend = blend;
2281 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2282 }
2283
2284 static void si_initialize_color_surface(struct si_context *sctx,
2285 struct r600_surface *surf)
2286 {
2287 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2288 unsigned level = surf->base.u.tex.level;
2289 uint64_t offset = rtex->surface.level[level].offset;
2290 unsigned pitch, slice;
2291 unsigned color_info, color_attrib, color_pitch, color_view;
2292 unsigned tile_mode_index;
2293 unsigned format, swap, ntype, endian;
2294 const struct util_format_description *desc;
2295 int i;
2296 unsigned blend_clamp = 0, blend_bypass = 0;
2297
2298 /* Layered rendering doesn't work with LINEAR_GENERAL.
2299 * (LINEAR_ALIGNED and others work) */
2300 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2301 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2302 offset += rtex->surface.level[level].slice_size *
2303 surf->base.u.tex.first_layer;
2304 color_view = 0;
2305 } else {
2306 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2307 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2308 }
2309
2310 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2311 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2312 if (slice) {
2313 slice = slice - 1;
2314 }
2315
2316 tile_mode_index = si_tile_mode_index(rtex, level, false);
2317
2318 desc = util_format_description(surf->base.format);
2319 for (i = 0; i < 4; i++) {
2320 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2321 break;
2322 }
2323 }
2324 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2325 ntype = V_028C70_NUMBER_FLOAT;
2326 } else {
2327 ntype = V_028C70_NUMBER_UNORM;
2328 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2329 ntype = V_028C70_NUMBER_SRGB;
2330 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2331 if (desc->channel[i].pure_integer) {
2332 ntype = V_028C70_NUMBER_SINT;
2333 } else {
2334 assert(desc->channel[i].normalized);
2335 ntype = V_028C70_NUMBER_SNORM;
2336 }
2337 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2338 if (desc->channel[i].pure_integer) {
2339 ntype = V_028C70_NUMBER_UINT;
2340 } else {
2341 assert(desc->channel[i].normalized);
2342 ntype = V_028C70_NUMBER_UNORM;
2343 }
2344 }
2345 }
2346
2347 format = si_translate_colorformat(surf->base.format);
2348 if (format == V_028C70_COLOR_INVALID) {
2349 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2350 }
2351 assert(format != V_028C70_COLOR_INVALID);
2352 swap = r600_translate_colorswap(surf->base.format);
2353 endian = si_colorformat_endian_swap(format);
2354
2355 /* blend clamp should be set for all NORM/SRGB types */
2356 if (ntype == V_028C70_NUMBER_UNORM ||
2357 ntype == V_028C70_NUMBER_SNORM ||
2358 ntype == V_028C70_NUMBER_SRGB)
2359 blend_clamp = 1;
2360
2361 /* set blend bypass according to docs if SINT/UINT or
2362 8/24 COLOR variants */
2363 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2364 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2365 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2366 blend_clamp = 0;
2367 blend_bypass = 1;
2368 }
2369
2370 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2371 (format == V_028C70_COLOR_8 ||
2372 format == V_028C70_COLOR_8_8 ||
2373 format == V_028C70_COLOR_8_8_8_8))
2374 surf->color_is_int8 = true;
2375
2376 color_info = S_028C70_FORMAT(format) |
2377 S_028C70_COMP_SWAP(swap) |
2378 S_028C70_BLEND_CLAMP(blend_clamp) |
2379 S_028C70_BLEND_BYPASS(blend_bypass) |
2380 S_028C70_NUMBER_TYPE(ntype) |
2381 S_028C70_ENDIAN(endian);
2382
2383 color_pitch = S_028C64_TILE_MAX(pitch);
2384
2385 /* Intensity is implemented as Red, so treat it that way. */
2386 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2387 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1 ||
2388 util_format_is_intensity(surf->base.format));
2389
2390 if (rtex->resource.b.b.nr_samples > 1) {
2391 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2392
2393 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2394 S_028C74_NUM_FRAGMENTS(log_samples);
2395
2396 if (rtex->fmask.size) {
2397 color_info |= S_028C70_COMPRESSION(1);
2398 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2399
2400 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2401
2402 if (sctx->b.chip_class == SI) {
2403 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2404 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2405 }
2406 if (sctx->b.chip_class >= CIK) {
2407 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2408 }
2409 }
2410 }
2411
2412 offset += rtex->resource.gpu_address;
2413
2414 surf->cb_color_base = offset >> 8;
2415 surf->cb_color_pitch = color_pitch;
2416 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2417 surf->cb_color_view = color_view;
2418 surf->cb_color_info = color_info;
2419 surf->cb_color_attrib = color_attrib;
2420
2421 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2422 unsigned max_uncompressed_block_size = 2;
2423
2424 if (rtex->surface.nsamples > 1) {
2425 if (rtex->surface.bpe == 1)
2426 max_uncompressed_block_size = 0;
2427 else if (rtex->surface.bpe == 2)
2428 max_uncompressed_block_size = 1;
2429 }
2430
2431 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2432 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2433 surf->cb_dcc_base = (rtex->resource.gpu_address +
2434 rtex->dcc_offset +
2435 rtex->surface.level[level].dcc_offset) >> 8;
2436 }
2437
2438 if (rtex->fmask.size) {
2439 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2440 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2441 } else {
2442 /* This must be set for fast clear to work without FMASK. */
2443 surf->cb_color_fmask = surf->cb_color_base;
2444 surf->cb_color_fmask_slice = surf->cb_color_slice;
2445 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2446
2447 if (sctx->b.chip_class == SI) {
2448 unsigned bankh = util_logbase2(rtex->surface.bankh);
2449 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2450 }
2451
2452 if (sctx->b.chip_class >= CIK) {
2453 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2454 }
2455 }
2456
2457 /* Determine pixel shader export format */
2458 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2459
2460 surf->color_initialized = true;
2461 }
2462
2463 static void si_init_depth_surface(struct si_context *sctx,
2464 struct r600_surface *surf)
2465 {
2466 struct si_screen *sscreen = sctx->screen;
2467 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2468 unsigned level = surf->base.u.tex.level;
2469 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2470 unsigned format, tile_mode_index, array_mode;
2471 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2472 uint32_t z_info, s_info, db_depth_info;
2473 uint64_t z_offs, s_offs;
2474 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2475
2476 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2477 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2478 case PIPE_FORMAT_X8Z24_UNORM:
2479 case PIPE_FORMAT_Z24X8_UNORM:
2480 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2481 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2482 break;
2483 case PIPE_FORMAT_Z32_FLOAT:
2484 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2485 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2486 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2487 break;
2488 case PIPE_FORMAT_Z16_UNORM:
2489 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2490 break;
2491 default:
2492 assert(0);
2493 }
2494
2495 format = si_translate_dbformat(rtex->resource.b.b.format);
2496
2497 if (format == V_028040_Z_INVALID) {
2498 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2499 }
2500 assert(format != V_028040_Z_INVALID);
2501
2502 s_offs = z_offs = rtex->resource.gpu_address;
2503 z_offs += rtex->surface.level[level].offset;
2504 s_offs += rtex->surface.stencil_level[level].offset;
2505
2506 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2507
2508 z_info = S_028040_FORMAT(format);
2509 if (rtex->resource.b.b.nr_samples > 1) {
2510 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2511 }
2512
2513 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2514 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2515 else
2516 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2517
2518 if (sctx->b.chip_class >= CIK) {
2519 switch (rtex->surface.level[level].mode) {
2520 case RADEON_SURF_MODE_2D:
2521 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2522 break;
2523 case RADEON_SURF_MODE_1D:
2524 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2525 case RADEON_SURF_MODE_LINEAR:
2526 default:
2527 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2528 break;
2529 }
2530 tile_split = rtex->surface.tile_split;
2531 stile_split = rtex->surface.stencil_tile_split;
2532 macro_aspect = rtex->surface.mtilea;
2533 bankw = rtex->surface.bankw;
2534 bankh = rtex->surface.bankh;
2535 tile_split = cik_tile_split(tile_split);
2536 stile_split = cik_tile_split(stile_split);
2537 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2538 bankw = cik_bank_wh(bankw);
2539 bankh = cik_bank_wh(bankh);
2540 nbanks = si_num_banks(sscreen, rtex);
2541 tile_mode_index = si_tile_mode_index(rtex, level, false);
2542 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2543
2544 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2545 S_02803C_PIPE_CONFIG(pipe_config) |
2546 S_02803C_BANK_WIDTH(bankw) |
2547 S_02803C_BANK_HEIGHT(bankh) |
2548 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2549 S_02803C_NUM_BANKS(nbanks);
2550 z_info |= S_028040_TILE_SPLIT(tile_split);
2551 s_info |= S_028044_TILE_SPLIT(stile_split);
2552 } else {
2553 tile_mode_index = si_tile_mode_index(rtex, level, false);
2554 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2555 tile_mode_index = si_tile_mode_index(rtex, level, true);
2556 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2557 }
2558
2559 /* HiZ aka depth buffer htile */
2560 /* use htile only for first level */
2561 if (rtex->htile_buffer && !level) {
2562 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2563 S_028040_ALLOW_EXPCLEAR(1);
2564
2565 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2566 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2567 else
2568 /* Use all of the htile_buffer for depth if there's no stencil. */
2569 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2570
2571 uint64_t va = rtex->htile_buffer->gpu_address;
2572 db_htile_data_base = va >> 8;
2573 db_htile_surface = S_028ABC_FULL_CACHE(1);
2574 } else {
2575 db_htile_data_base = 0;
2576 db_htile_surface = 0;
2577 }
2578
2579 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2580
2581 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2582 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2583 surf->db_htile_data_base = db_htile_data_base;
2584 surf->db_depth_info = db_depth_info;
2585 surf->db_z_info = z_info;
2586 surf->db_stencil_info = s_info;
2587 surf->db_depth_base = z_offs >> 8;
2588 surf->db_stencil_base = s_offs >> 8;
2589 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2590 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2591 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2592 levelinfo->nblk_y) / 64 - 1);
2593 surf->db_htile_surface = db_htile_surface;
2594 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2595
2596 surf->depth_initialized = true;
2597 }
2598
2599 static void si_set_framebuffer_state(struct pipe_context *ctx,
2600 const struct pipe_framebuffer_state *state)
2601 {
2602 struct si_context *sctx = (struct si_context *)ctx;
2603 struct pipe_constant_buffer constbuf = {0};
2604 struct r600_surface *surf = NULL;
2605 struct r600_texture *rtex;
2606 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2607 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2608 int i;
2609
2610 /* Only flush TC when changing the framebuffer state, because
2611 * the only client not using TC that can change textures is
2612 * the framebuffer.
2613 *
2614 * Flush all CB and DB caches here because all buffers can be used
2615 * for write by both TC (with shader image stores) and CB/DB.
2616 */
2617 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2618 SI_CONTEXT_INV_GLOBAL_L2 |
2619 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2620
2621 /* Take the maximum of the old and new count. If the new count is lower,
2622 * dirtying is needed to disable the unbound colorbuffers.
2623 */
2624 sctx->framebuffer.dirty_cbufs |=
2625 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2626 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2627
2628 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2629
2630 sctx->framebuffer.spi_shader_col_format = 0;
2631 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2632 sctx->framebuffer.spi_shader_col_format_blend = 0;
2633 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2634 sctx->framebuffer.color_is_int8 = 0;
2635
2636 sctx->framebuffer.compressed_cb_mask = 0;
2637 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2638 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2639 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2640 util_format_is_pure_integer(state->cbufs[0]->format);
2641
2642 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2643 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2644
2645 for (i = 0; i < state->nr_cbufs; i++) {
2646 if (!state->cbufs[i])
2647 continue;
2648
2649 surf = (struct r600_surface*)state->cbufs[i];
2650 rtex = (struct r600_texture*)surf->base.texture;
2651
2652 if (!surf->color_initialized) {
2653 si_initialize_color_surface(sctx, surf);
2654 }
2655
2656 sctx->framebuffer.spi_shader_col_format |=
2657 surf->spi_shader_col_format << (i * 4);
2658 sctx->framebuffer.spi_shader_col_format_alpha |=
2659 surf->spi_shader_col_format_alpha << (i * 4);
2660 sctx->framebuffer.spi_shader_col_format_blend |=
2661 surf->spi_shader_col_format_blend << (i * 4);
2662 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2663 surf->spi_shader_col_format_blend_alpha << (i * 4);
2664
2665 if (surf->color_is_int8)
2666 sctx->framebuffer.color_is_int8 |= 1 << i;
2667
2668 if (rtex->fmask.size && rtex->cmask.size) {
2669 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2670 }
2671 r600_context_add_resource_size(ctx, surf->base.texture);
2672 }
2673 /* Set the second SPI format for possible dual-src blending. */
2674 if (i == 1 && surf) {
2675 sctx->framebuffer.spi_shader_col_format |=
2676 surf->spi_shader_col_format << (i * 4);
2677 sctx->framebuffer.spi_shader_col_format_alpha |=
2678 surf->spi_shader_col_format_alpha << (i * 4);
2679 sctx->framebuffer.spi_shader_col_format_blend |=
2680 surf->spi_shader_col_format_blend << (i * 4);
2681 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2682 surf->spi_shader_col_format_blend_alpha << (i * 4);
2683 }
2684
2685 if (state->zsbuf) {
2686 surf = (struct r600_surface*)state->zsbuf;
2687
2688 if (!surf->depth_initialized) {
2689 si_init_depth_surface(sctx, surf);
2690 }
2691 r600_context_add_resource_size(ctx, surf->base.texture);
2692 }
2693
2694 si_update_poly_offset_state(sctx);
2695 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2696 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2697
2698 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2699 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2700 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2701
2702 /* Set sample locations as fragment shader constants. */
2703 switch (sctx->framebuffer.nr_samples) {
2704 case 1:
2705 constbuf.user_buffer = sctx->b.sample_locations_1x;
2706 break;
2707 case 2:
2708 constbuf.user_buffer = sctx->b.sample_locations_2x;
2709 break;
2710 case 4:
2711 constbuf.user_buffer = sctx->b.sample_locations_4x;
2712 break;
2713 case 8:
2714 constbuf.user_buffer = sctx->b.sample_locations_8x;
2715 break;
2716 case 16:
2717 constbuf.user_buffer = sctx->b.sample_locations_16x;
2718 break;
2719 default:
2720 R600_ERR("Requested an invalid number of samples %i.\n",
2721 sctx->framebuffer.nr_samples);
2722 assert(0);
2723 }
2724 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2725 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2726 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2727
2728 /* Smoothing (only possible with nr_samples == 1) uses the same
2729 * sample locations as the MSAA it simulates.
2730 *
2731 * Therefore, don't update the sample locations when
2732 * transitioning from no AA to smoothing-equivalent AA, and
2733 * vice versa.
2734 */
2735 if ((sctx->framebuffer.nr_samples != 1 ||
2736 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2737 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2738 old_nr_samples != 1))
2739 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2740 }
2741 }
2742
2743 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2744 {
2745 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2746 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2747 unsigned i, nr_cbufs = state->nr_cbufs;
2748 struct r600_texture *tex = NULL;
2749 struct r600_surface *cb = NULL;
2750
2751 /* Colorbuffers. */
2752 for (i = 0; i < nr_cbufs; i++) {
2753 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2754 continue;
2755
2756 cb = (struct r600_surface*)state->cbufs[i];
2757 if (!cb) {
2758 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2759 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2760 continue;
2761 }
2762
2763 tex = (struct r600_texture *)cb->base.texture;
2764 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2765 &tex->resource, RADEON_USAGE_READWRITE,
2766 tex->surface.nsamples > 1 ?
2767 RADEON_PRIO_COLOR_BUFFER_MSAA :
2768 RADEON_PRIO_COLOR_BUFFER);
2769
2770 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2771 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2772 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2773 RADEON_PRIO_CMASK);
2774 }
2775
2776 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2777 sctx->b.chip_class >= VI ? 14 : 13);
2778 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2779 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2780 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2781 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2782 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2783 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2784 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2785 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2786 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2787 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2788 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2789 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2790 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2791
2792 if (sctx->b.chip_class >= VI)
2793 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2794 }
2795 /* set CB_COLOR1_INFO for possible dual-src blending */
2796 if (i == 1 && state->cbufs[0] &&
2797 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2798 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2799 cb->cb_color_info | tex->cb_color_info);
2800 i++;
2801 }
2802 for (; i < 8 ; i++)
2803 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2804 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2805
2806 /* ZS buffer. */
2807 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2808 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2809 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2810
2811 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2812 &rtex->resource, RADEON_USAGE_READWRITE,
2813 zb->base.texture->nr_samples > 1 ?
2814 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2815 RADEON_PRIO_DEPTH_BUFFER);
2816
2817 if (zb->db_htile_data_base) {
2818 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2819 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2820 RADEON_PRIO_HTILE);
2821 }
2822
2823 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2824 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2825
2826 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2827 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2828 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2829 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2830 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2831 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2832 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2833 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2834 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2835 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2836 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2837
2838 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2839 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2840 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2841
2842 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2843 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2844 zb->pa_su_poly_offset_db_fmt_cntl);
2845 } else if (sctx->framebuffer.dirty_zsbuf) {
2846 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2847 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2848 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2849 }
2850
2851 /* Framebuffer dimensions. */
2852 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2853 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2854 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2855
2856 sctx->framebuffer.dirty_cbufs = 0;
2857 sctx->framebuffer.dirty_zsbuf = false;
2858 }
2859
2860 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2861 struct r600_atom *atom)
2862 {
2863 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2864 unsigned nr_samples = sctx->framebuffer.nr_samples;
2865
2866 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2867 SI_NUM_SMOOTH_AA_SAMPLES);
2868 }
2869
2870 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2871 {
2872 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2873
2874 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2875 sctx->ps_iter_samples,
2876 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2877 }
2878
2879
2880 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2881 {
2882 struct si_context *sctx = (struct si_context *)ctx;
2883
2884 if (sctx->ps_iter_samples == min_samples)
2885 return;
2886
2887 sctx->ps_iter_samples = min_samples;
2888
2889 if (sctx->framebuffer.nr_samples > 1)
2890 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2891 }
2892
2893 /*
2894 * Samplers
2895 */
2896
2897 /**
2898 * Build the sampler view descriptor for a buffer texture.
2899 * @param state 256-bit descriptor; only the high 128 bits are filled in
2900 */
2901 void
2902 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2903 enum pipe_format format,
2904 unsigned first_element, unsigned last_element,
2905 uint32_t *state)
2906 {
2907 const struct util_format_description *desc;
2908 int first_non_void;
2909 uint64_t va;
2910 unsigned stride;
2911 unsigned num_records;
2912 unsigned num_format, data_format;
2913
2914 desc = util_format_description(format);
2915 first_non_void = util_format_get_first_non_void_channel(format);
2916 stride = desc->block.bits / 8;
2917 va = buf->gpu_address + first_element * stride;
2918 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2919 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2920
2921 num_records = last_element + 1 - first_element;
2922 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2923
2924 if (screen->b.chip_class >= VI)
2925 num_records *= stride;
2926
2927 state[4] = va;
2928 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2929 S_008F04_STRIDE(stride);
2930 state[6] = num_records;
2931 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2932 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2933 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2934 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2935 S_008F0C_NUM_FORMAT(num_format) |
2936 S_008F0C_DATA_FORMAT(data_format);
2937 }
2938
2939 /**
2940 * Build the sampler view descriptor for a texture.
2941 */
2942 void
2943 si_make_texture_descriptor(struct si_screen *screen,
2944 struct r600_texture *tex,
2945 bool sampler,
2946 enum pipe_texture_target target,
2947 enum pipe_format pipe_format,
2948 const unsigned char state_swizzle[4],
2949 unsigned base_level, unsigned first_level, unsigned last_level,
2950 unsigned first_layer, unsigned last_layer,
2951 unsigned width, unsigned height, unsigned depth,
2952 uint32_t *state,
2953 uint32_t *fmask_state)
2954 {
2955 struct pipe_resource *res = &tex->resource.b.b;
2956 const struct radeon_surf_level *surflevel = tex->surface.level;
2957 const struct util_format_description *desc;
2958 unsigned char swizzle[4];
2959 int first_non_void;
2960 unsigned num_format, data_format, type;
2961 uint32_t pitch;
2962 uint64_t va;
2963
2964 /* Texturing with separate depth and stencil. */
2965 if (tex->is_depth && !tex->is_flushing_texture) {
2966 switch (pipe_format) {
2967 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2968 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2969 break;
2970 case PIPE_FORMAT_X8Z24_UNORM:
2971 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2972 /* Z24 is always stored like this. */
2973 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2974 break;
2975 case PIPE_FORMAT_X24S8_UINT:
2976 case PIPE_FORMAT_S8X24_UINT:
2977 case PIPE_FORMAT_X32_S8X24_UINT:
2978 pipe_format = PIPE_FORMAT_S8_UINT;
2979 surflevel = tex->surface.stencil_level;
2980 break;
2981 default:;
2982 }
2983 }
2984
2985 desc = util_format_description(pipe_format);
2986
2987 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2988 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2989 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2990
2991 switch (pipe_format) {
2992 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2993 case PIPE_FORMAT_X24S8_UINT:
2994 case PIPE_FORMAT_X32_S8X24_UINT:
2995 case PIPE_FORMAT_X8Z24_UNORM:
2996 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2997 break;
2998 default:
2999 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3000 }
3001 } else {
3002 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3003 }
3004
3005 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3006
3007 switch (pipe_format) {
3008 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3009 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3010 break;
3011 default:
3012 if (first_non_void < 0) {
3013 if (util_format_is_compressed(pipe_format)) {
3014 switch (pipe_format) {
3015 case PIPE_FORMAT_DXT1_SRGB:
3016 case PIPE_FORMAT_DXT1_SRGBA:
3017 case PIPE_FORMAT_DXT3_SRGBA:
3018 case PIPE_FORMAT_DXT5_SRGBA:
3019 case PIPE_FORMAT_BPTC_SRGBA:
3020 case PIPE_FORMAT_ETC2_SRGB8:
3021 case PIPE_FORMAT_ETC2_SRGB8A1:
3022 case PIPE_FORMAT_ETC2_SRGBA8:
3023 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3024 break;
3025 case PIPE_FORMAT_RGTC1_SNORM:
3026 case PIPE_FORMAT_LATC1_SNORM:
3027 case PIPE_FORMAT_RGTC2_SNORM:
3028 case PIPE_FORMAT_LATC2_SNORM:
3029 case PIPE_FORMAT_ETC2_R11_SNORM:
3030 case PIPE_FORMAT_ETC2_RG11_SNORM:
3031 /* implies float, so use SNORM/UNORM to determine
3032 whether data is signed or not */
3033 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3034 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3035 break;
3036 default:
3037 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3038 break;
3039 }
3040 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3041 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3042 } else {
3043 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3044 }
3045 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3046 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3047 } else {
3048 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3049
3050 switch (desc->channel[first_non_void].type) {
3051 case UTIL_FORMAT_TYPE_FLOAT:
3052 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3053 break;
3054 case UTIL_FORMAT_TYPE_SIGNED:
3055 if (desc->channel[first_non_void].normalized)
3056 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3057 else if (desc->channel[first_non_void].pure_integer)
3058 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3059 else
3060 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3061 break;
3062 case UTIL_FORMAT_TYPE_UNSIGNED:
3063 if (desc->channel[first_non_void].normalized)
3064 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3065 else if (desc->channel[first_non_void].pure_integer)
3066 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3067 else
3068 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3069 }
3070 }
3071 }
3072
3073 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3074 if (data_format == ~0) {
3075 data_format = 0;
3076 }
3077
3078 if (!sampler &&
3079 (res->target == PIPE_TEXTURE_CUBE ||
3080 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3081 res->target == PIPE_TEXTURE_3D)) {
3082 /* For the purpose of shader images, treat cube maps and 3D
3083 * textures as 2D arrays. For 3D textures, the address
3084 * calculations for mipmaps are different, so we rely on the
3085 * caller to effectively disable mipmaps.
3086 */
3087 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3088
3089 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3090 } else {
3091 type = si_tex_dim(res->target, target, res->nr_samples);
3092 }
3093
3094 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3095 height = 1;
3096 depth = res->array_size;
3097 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3098 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3099 if (sampler || res->target != PIPE_TEXTURE_3D)
3100 depth = res->array_size;
3101 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3102 depth = res->array_size / 6;
3103
3104 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
3105 va = tex->resource.gpu_address + surflevel[base_level].offset;
3106
3107 state[0] = va >> 8;
3108 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
3109 S_008F14_DATA_FORMAT(data_format) |
3110 S_008F14_NUM_FORMAT(num_format));
3111 state[2] = (S_008F18_WIDTH(width - 1) |
3112 S_008F18_HEIGHT(height - 1));
3113 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3114 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3115 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3116 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3117 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3118 0 : first_level) |
3119 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3120 util_logbase2(res->nr_samples) :
3121 last_level) |
3122 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
3123 S_008F1C_POW2_PAD(res->last_level > 0) |
3124 S_008F1C_TYPE(type));
3125 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
3126 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
3127 S_008F24_LAST_ARRAY(last_layer));
3128
3129 if (tex->dcc_offset) {
3130 unsigned swap = r600_translate_colorswap(pipe_format);
3131
3132 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3133 state[7] = (tex->resource.gpu_address +
3134 tex->dcc_offset +
3135 surflevel[base_level].dcc_offset) >> 8;
3136 } else {
3137 state[6] = 0;
3138 state[7] = 0;
3139 }
3140
3141 /* Initialize the sampler view for FMASK. */
3142 if (tex->fmask.size) {
3143 uint32_t fmask_format;
3144
3145 va = tex->resource.gpu_address + tex->fmask.offset;
3146
3147 switch (res->nr_samples) {
3148 case 2:
3149 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3150 break;
3151 case 4:
3152 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3153 break;
3154 case 8:
3155 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3156 break;
3157 default:
3158 assert(0);
3159 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3160 }
3161
3162 fmask_state[0] = va >> 8;
3163 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3164 S_008F14_DATA_FORMAT(fmask_format) |
3165 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3166 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3167 S_008F18_HEIGHT(height - 1);
3168 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3169 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3170 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3171 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3172 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3173 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3174 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3175 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3176 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3177 S_008F24_LAST_ARRAY(last_layer);
3178 fmask_state[6] = 0;
3179 fmask_state[7] = 0;
3180 }
3181 }
3182
3183 /**
3184 * Create a sampler view.
3185 *
3186 * @param ctx context
3187 * @param texture texture
3188 * @param state sampler view template
3189 * @param width0 width0 override (for compressed textures as int)
3190 * @param height0 height0 override (for compressed textures as int)
3191 * @param force_level set the base address to the level (for compressed textures)
3192 */
3193 struct pipe_sampler_view *
3194 si_create_sampler_view_custom(struct pipe_context *ctx,
3195 struct pipe_resource *texture,
3196 const struct pipe_sampler_view *state,
3197 unsigned width0, unsigned height0,
3198 unsigned force_level)
3199 {
3200 struct si_context *sctx = (struct si_context*)ctx;
3201 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3202 struct r600_texture *tmp = (struct r600_texture*)texture;
3203 unsigned base_level, first_level, last_level;
3204 unsigned char state_swizzle[4];
3205 unsigned height, depth, width;
3206 unsigned last_layer = state->u.tex.last_layer;
3207
3208 if (!view)
3209 return NULL;
3210
3211 /* initialize base object */
3212 view->base = *state;
3213 view->base.texture = NULL;
3214 view->base.reference.count = 1;
3215 view->base.context = ctx;
3216
3217 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3218 if (!texture) {
3219 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3220 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3221 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3222 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3223 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3224 return &view->base;
3225 }
3226
3227 pipe_resource_reference(&view->base.texture, texture);
3228
3229 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3230 state->format == PIPE_FORMAT_S8X24_UINT ||
3231 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3232 state->format == PIPE_FORMAT_S8_UINT)
3233 view->is_stencil_sampler = true;
3234
3235 /* Buffer resource. */
3236 if (texture->target == PIPE_BUFFER) {
3237 si_make_buffer_descriptor(sctx->screen,
3238 (struct r600_resource *)texture,
3239 state->format,
3240 state->u.buf.first_element,
3241 state->u.buf.last_element,
3242 view->state);
3243
3244 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3245 return &view->base;
3246 }
3247
3248 state_swizzle[0] = state->swizzle_r;
3249 state_swizzle[1] = state->swizzle_g;
3250 state_swizzle[2] = state->swizzle_b;
3251 state_swizzle[3] = state->swizzle_a;
3252
3253 base_level = 0;
3254 first_level = state->u.tex.first_level;
3255 last_level = state->u.tex.last_level;
3256 width = width0;
3257 height = height0;
3258 depth = texture->depth0;
3259
3260 if (force_level) {
3261 assert(force_level == first_level &&
3262 force_level == last_level);
3263 base_level = force_level;
3264 first_level = 0;
3265 last_level = 0;
3266 width = u_minify(width, force_level);
3267 height = u_minify(height, force_level);
3268 depth = u_minify(depth, force_level);
3269 }
3270
3271 /* This is not needed if state trackers set last_layer correctly. */
3272 if (state->target == PIPE_TEXTURE_1D ||
3273 state->target == PIPE_TEXTURE_2D ||
3274 state->target == PIPE_TEXTURE_RECT ||
3275 state->target == PIPE_TEXTURE_CUBE)
3276 last_layer = state->u.tex.first_layer;
3277
3278 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3279 state->format, state_swizzle,
3280 base_level, first_level, last_level,
3281 state->u.tex.first_layer, last_layer,
3282 width, height, depth,
3283 view->state, view->fmask_state);
3284
3285 return &view->base;
3286 }
3287
3288 static struct pipe_sampler_view *
3289 si_create_sampler_view(struct pipe_context *ctx,
3290 struct pipe_resource *texture,
3291 const struct pipe_sampler_view *state)
3292 {
3293 return si_create_sampler_view_custom(ctx, texture, state,
3294 texture ? texture->width0 : 0,
3295 texture ? texture->height0 : 0, 0);
3296 }
3297
3298 static void si_sampler_view_destroy(struct pipe_context *ctx,
3299 struct pipe_sampler_view *state)
3300 {
3301 struct si_sampler_view *view = (struct si_sampler_view *)state;
3302
3303 if (state->texture && state->texture->target == PIPE_BUFFER)
3304 LIST_DELINIT(&view->list);
3305
3306 pipe_resource_reference(&state->texture, NULL);
3307 FREE(view);
3308 }
3309
3310 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3311 {
3312 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3313 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3314 (linear_filter &&
3315 (wrap == PIPE_TEX_WRAP_CLAMP ||
3316 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3317 }
3318
3319 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3320 {
3321 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3322 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3323
3324 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3325 state->border_color.ui[2] || state->border_color.ui[3]) &&
3326 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3327 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3328 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3329 }
3330
3331 static void *si_create_sampler_state(struct pipe_context *ctx,
3332 const struct pipe_sampler_state *state)
3333 {
3334 struct si_context *sctx = (struct si_context *)ctx;
3335 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3336 unsigned border_color_type, border_color_index = 0;
3337
3338 if (!rstate) {
3339 return NULL;
3340 }
3341
3342 if (!sampler_state_needs_border_color(state))
3343 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3344 else if (state->border_color.f[0] == 0 &&
3345 state->border_color.f[1] == 0 &&
3346 state->border_color.f[2] == 0 &&
3347 state->border_color.f[3] == 0)
3348 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3349 else if (state->border_color.f[0] == 0 &&
3350 state->border_color.f[1] == 0 &&
3351 state->border_color.f[2] == 0 &&
3352 state->border_color.f[3] == 1)
3353 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3354 else if (state->border_color.f[0] == 1 &&
3355 state->border_color.f[1] == 1 &&
3356 state->border_color.f[2] == 1 &&
3357 state->border_color.f[3] == 1)
3358 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3359 else {
3360 int i;
3361
3362 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3363
3364 /* Check if the border has been uploaded already. */
3365 for (i = 0; i < sctx->border_color_count; i++)
3366 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3367 sizeof(state->border_color)) == 0)
3368 break;
3369
3370 if (i >= SI_MAX_BORDER_COLORS) {
3371 /* Getting 4096 unique border colors is very unlikely. */
3372 fprintf(stderr, "radeonsi: The border color table is full. "
3373 "Any new border colors will be just black. "
3374 "Please file a bug.\n");
3375 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3376 } else {
3377 if (i == sctx->border_color_count) {
3378 /* Upload a new border color. */
3379 memcpy(&sctx->border_color_table[i], &state->border_color,
3380 sizeof(state->border_color));
3381 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3382 &state->border_color,
3383 sizeof(state->border_color));
3384 sctx->border_color_count++;
3385 }
3386
3387 border_color_index = i;
3388 }
3389 }
3390
3391 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3392 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3393 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3394 S_008F30_MAX_ANISO_RATIO(r600_tex_aniso_filter(state->max_anisotropy)) |
3395 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3396 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3397 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3398 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3399 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3400 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3401 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3402 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, state->max_anisotropy)) |
3403 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, state->max_anisotropy)) |
3404 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3405 S_008F38_MIP_POINT_PRECLAMP(1) |
3406 S_008F38_DISABLE_LSB_CEIL(1) |
3407 S_008F38_FILTER_PREC_FIX(1) |
3408 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3409 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3410 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3411 return rstate;
3412 }
3413
3414 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3415 {
3416 struct si_context *sctx = (struct si_context *)ctx;
3417
3418 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3419 return;
3420
3421 sctx->sample_mask.sample_mask = sample_mask;
3422 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3423 }
3424
3425 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3426 {
3427 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3428 unsigned mask = sctx->sample_mask.sample_mask;
3429
3430 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3431 radeon_emit(cs, mask | (mask << 16));
3432 radeon_emit(cs, mask | (mask << 16));
3433 }
3434
3435 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3436 {
3437 free(state);
3438 }
3439
3440 /*
3441 * Vertex elements & buffers
3442 */
3443
3444 static void *si_create_vertex_elements(struct pipe_context *ctx,
3445 unsigned count,
3446 const struct pipe_vertex_element *elements)
3447 {
3448 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3449 int i;
3450
3451 assert(count < SI_MAX_ATTRIBS);
3452 if (!v)
3453 return NULL;
3454
3455 v->count = count;
3456 for (i = 0; i < count; ++i) {
3457 const struct util_format_description *desc;
3458 unsigned data_format, num_format;
3459 int first_non_void;
3460
3461 desc = util_format_description(elements[i].src_format);
3462 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3463 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3464 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3465
3466 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3467 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3468 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3469 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3470 S_008F0C_NUM_FORMAT(num_format) |
3471 S_008F0C_DATA_FORMAT(data_format);
3472 v->format_size[i] = desc->block.bits / 8;
3473 }
3474 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3475
3476 return v;
3477 }
3478
3479 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3480 {
3481 struct si_context *sctx = (struct si_context *)ctx;
3482 struct si_vertex_element *v = (struct si_vertex_element*)state;
3483
3484 sctx->vertex_elements = v;
3485 sctx->vertex_buffers_dirty = true;
3486 }
3487
3488 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3489 {
3490 struct si_context *sctx = (struct si_context *)ctx;
3491
3492 if (sctx->vertex_elements == state)
3493 sctx->vertex_elements = NULL;
3494 FREE(state);
3495 }
3496
3497 static void si_set_vertex_buffers(struct pipe_context *ctx,
3498 unsigned start_slot, unsigned count,
3499 const struct pipe_vertex_buffer *buffers)
3500 {
3501 struct si_context *sctx = (struct si_context *)ctx;
3502 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3503 int i;
3504
3505 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3506
3507 if (buffers) {
3508 for (i = 0; i < count; i++) {
3509 const struct pipe_vertex_buffer *src = buffers + i;
3510 struct pipe_vertex_buffer *dsti = dst + i;
3511
3512 pipe_resource_reference(&dsti->buffer, src->buffer);
3513 dsti->buffer_offset = src->buffer_offset;
3514 dsti->stride = src->stride;
3515 r600_context_add_resource_size(ctx, src->buffer);
3516 }
3517 } else {
3518 for (i = 0; i < count; i++) {
3519 pipe_resource_reference(&dst[i].buffer, NULL);
3520 }
3521 }
3522 sctx->vertex_buffers_dirty = true;
3523 }
3524
3525 static void si_set_index_buffer(struct pipe_context *ctx,
3526 const struct pipe_index_buffer *ib)
3527 {
3528 struct si_context *sctx = (struct si_context *)ctx;
3529
3530 if (ib) {
3531 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3532 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3533 r600_context_add_resource_size(ctx, ib->buffer);
3534 } else {
3535 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3536 }
3537 }
3538
3539 /*
3540 * Misc
3541 */
3542 static void si_set_polygon_stipple(struct pipe_context *ctx,
3543 const struct pipe_poly_stipple *state)
3544 {
3545 struct si_context *sctx = (struct si_context *)ctx;
3546 struct pipe_resource *tex;
3547 struct pipe_sampler_view *view;
3548 bool is_zero = true;
3549 bool is_one = true;
3550 int i;
3551
3552 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3553 * the resource is NULL/invalid. Take advantage of this fact and skip
3554 * texture allocation if the stipple pattern is constant.
3555 *
3556 * This is an optimization for the common case when stippling isn't
3557 * used but set_polygon_stipple is still called by st/mesa.
3558 */
3559 for (i = 0; i < Elements(state->stipple); i++) {
3560 is_zero = is_zero && state->stipple[i] == 0;
3561 is_one = is_one && state->stipple[i] == 0xffffffff;
3562 }
3563
3564 if (is_zero || is_one) {
3565 struct pipe_sampler_view templ = {{0}};
3566
3567 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3568 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3569 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3570 /* The pattern should be inverted in the texture. */
3571 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3572
3573 view = ctx->create_sampler_view(ctx, NULL, &templ);
3574 } else {
3575 /* Create a new texture. */
3576 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3577 if (!tex)
3578 return;
3579
3580 view = util_pstipple_create_sampler_view(ctx, tex);
3581 pipe_resource_reference(&tex, NULL);
3582 }
3583
3584 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3585 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3586 pipe_sampler_view_reference(&view, NULL);
3587
3588 /* Bind the sampler state if needed. */
3589 if (!sctx->pstipple_sampler_state) {
3590 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3591 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3592 SI_POLY_STIPPLE_SAMPLER, 1,
3593 &sctx->pstipple_sampler_state);
3594 }
3595 }
3596
3597 static void si_set_tess_state(struct pipe_context *ctx,
3598 const float default_outer_level[4],
3599 const float default_inner_level[2])
3600 {
3601 struct si_context *sctx = (struct si_context *)ctx;
3602 struct pipe_constant_buffer cb;
3603 float array[8];
3604
3605 memcpy(array, default_outer_level, sizeof(float) * 4);
3606 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3607
3608 cb.buffer = NULL;
3609 cb.user_buffer = NULL;
3610 cb.buffer_size = sizeof(array);
3611
3612 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3613 (void*)array, sizeof(array),
3614 &cb.buffer_offset);
3615
3616 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3617 SI_DRIVER_STATE_CONST_BUF, &cb);
3618 pipe_resource_reference(&cb.buffer, NULL);
3619 }
3620
3621 static void si_texture_barrier(struct pipe_context *ctx)
3622 {
3623 struct si_context *sctx = (struct si_context *)ctx;
3624
3625 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3626 SI_CONTEXT_INV_GLOBAL_L2 |
3627 SI_CONTEXT_FLUSH_AND_INV_CB;
3628 }
3629
3630 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3631 {
3632 struct si_context *sctx = (struct si_context *)ctx;
3633
3634 /* Subsequent commands must wait for all shader invocations to
3635 * complete. */
3636 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
3637
3638 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3639 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3640 SI_CONTEXT_INV_VMEM_L1;
3641
3642 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3643 PIPE_BARRIER_SHADER_BUFFER |
3644 PIPE_BARRIER_TEXTURE |
3645 PIPE_BARRIER_IMAGE |
3646 PIPE_BARRIER_STREAMOUT_BUFFER)) {
3647 /* As far as I can tell, L1 contents are written back to L2
3648 * automatically at end of shader, but the contents of other
3649 * L1 caches might still be stale. */
3650 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3651 }
3652
3653 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3654 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3655
3656 /* Indices are read through TC L2 since VI. */
3657 if (sctx->screen->b.chip_class <= CIK)
3658 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3659 }
3660
3661 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3662 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3663
3664 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3665 PIPE_BARRIER_FRAMEBUFFER |
3666 PIPE_BARRIER_INDIRECT_BUFFER)) {
3667 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3668 *
3669 * We need to make sure that TC L1 & L2 are written back to
3670 * memory, because neither CPU accesses nor CB fetches consider
3671 * TC, but there's no need to invalidate any TC cache lines. */
3672 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3673 }
3674 }
3675
3676 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3677 {
3678 struct pipe_blend_state blend;
3679
3680 memset(&blend, 0, sizeof(blend));
3681 blend.independent_blend_enable = true;
3682 blend.rt[0].colormask = 0xf;
3683 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3684 }
3685
3686 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3687 bool include_draw_vbo)
3688 {
3689 si_need_cs_space((struct si_context*)ctx);
3690 }
3691
3692 static void si_init_config(struct si_context *sctx);
3693
3694 void si_init_state_functions(struct si_context *sctx)
3695 {
3696 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3697 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3698 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3699
3700 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3701 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3702 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3703 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3704 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3705 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3706 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3707 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3708 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3709 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3710 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3711 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3712 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3713
3714 sctx->b.b.create_blend_state = si_create_blend_state;
3715 sctx->b.b.bind_blend_state = si_bind_blend_state;
3716 sctx->b.b.delete_blend_state = si_delete_blend_state;
3717 sctx->b.b.set_blend_color = si_set_blend_color;
3718
3719 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3720 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3721 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3722
3723 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3724 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3725 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3726
3727 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3728 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3729 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3730 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3731 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3732
3733 sctx->b.b.set_clip_state = si_set_clip_state;
3734 sctx->b.b.set_scissor_states = si_set_scissor_states;
3735 sctx->b.b.set_viewport_states = si_set_viewport_states;
3736 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3737
3738 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3739 sctx->b.b.get_sample_position = cayman_get_sample_position;
3740
3741 sctx->b.b.create_sampler_state = si_create_sampler_state;
3742 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3743
3744 sctx->b.b.create_sampler_view = si_create_sampler_view;
3745 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3746
3747 sctx->b.b.set_sample_mask = si_set_sample_mask;
3748
3749 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3750 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3751 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3752 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3753 sctx->b.b.set_index_buffer = si_set_index_buffer;
3754
3755 sctx->b.b.texture_barrier = si_texture_barrier;
3756 sctx->b.b.memory_barrier = si_memory_barrier;
3757 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3758 sctx->b.b.set_min_samples = si_set_min_samples;
3759 sctx->b.b.set_tess_state = si_set_tess_state;
3760
3761 sctx->b.b.set_active_query_state = si_set_active_query_state;
3762 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3763 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3764
3765 sctx->b.b.draw_vbo = si_draw_vbo;
3766
3767 if (sctx->b.chip_class >= CIK) {
3768 sctx->b.dma_copy = cik_sdma_copy;
3769 } else {
3770 sctx->b.dma_copy = si_dma_copy;
3771 }
3772
3773 si_init_config(sctx);
3774 }
3775
3776 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3777 struct r600_texture *rtex,
3778 struct radeon_bo_metadata *md)
3779 {
3780 struct si_screen *sscreen = (struct si_screen*)rscreen;
3781 struct pipe_resource *res = &rtex->resource.b.b;
3782 static const unsigned char swizzle[] = {
3783 PIPE_SWIZZLE_RED,
3784 PIPE_SWIZZLE_GREEN,
3785 PIPE_SWIZZLE_BLUE,
3786 PIPE_SWIZZLE_ALPHA
3787 };
3788 uint32_t desc[8], i;
3789 bool is_array = util_resource_is_array_texture(res);
3790
3791 /* DRM 2.x.x doesn't support this. */
3792 if (rscreen->info.drm_major != 3)
3793 return;
3794
3795 assert(rtex->fmask.size == 0);
3796
3797 /* Metadata image format format version 1:
3798 * [0] = 1 (metadata format identifier)
3799 * [1] = (VENDOR_ID << 16) | PCI_ID
3800 * [2:9] = image descriptor for the whole resource
3801 * [2] is always 0, because the base address is cleared
3802 * [9] is the DCC offset bits [39:8] from the beginning of
3803 * the buffer
3804 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3805 */
3806
3807 md->metadata[0] = 1; /* metadata image format version 1 */
3808
3809 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3810 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3811
3812 si_make_texture_descriptor(sscreen, rtex, true,
3813 res->target, res->format,
3814 swizzle, 0, 0, res->last_level, 0,
3815 is_array ? res->array_size - 1 : 0,
3816 res->width0, res->height0, res->depth0,
3817 desc, NULL);
3818
3819 /* Clear the base address and set the relative DCC offset. */
3820 desc[0] = 0;
3821 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3822 desc[7] = rtex->dcc_offset >> 8;
3823
3824 /* Dwords [2:9] contain the image descriptor. */
3825 memcpy(&md->metadata[2], desc, sizeof(desc));
3826
3827 /* Dwords [10:..] contain the mipmap level offsets. */
3828 for (i = 0; i <= res->last_level; i++)
3829 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3830
3831 md->size_metadata = (11 + res->last_level) * 4;
3832 }
3833
3834 void si_init_screen_state_functions(struct si_screen *sscreen)
3835 {
3836 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3837 }
3838
3839 static void
3840 si_write_harvested_raster_configs(struct si_context *sctx,
3841 struct si_pm4_state *pm4,
3842 unsigned raster_config,
3843 unsigned raster_config_1)
3844 {
3845 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3846 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3847 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3848 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3849 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3850 unsigned rb_per_se = num_rb / num_se;
3851 unsigned se_mask[4];
3852 unsigned se;
3853
3854 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3855 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3856 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3857 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3858
3859 assert(num_se == 1 || num_se == 2 || num_se == 4);
3860 assert(sh_per_se == 1 || sh_per_se == 2);
3861 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3862
3863 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3864 * fields are for, so I'm leaving them as their default
3865 * values. */
3866
3867 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3868 (!se_mask[2] && !se_mask[3]))) {
3869 raster_config_1 &= C_028354_SE_PAIR_MAP;
3870
3871 if (!se_mask[0] && !se_mask[1]) {
3872 raster_config_1 |=
3873 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3874 } else {
3875 raster_config_1 |=
3876 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3877 }
3878 }
3879
3880 for (se = 0; se < num_se; se++) {
3881 unsigned raster_config_se = raster_config;
3882 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3883 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3884 int idx = (se / 2) * 2;
3885
3886 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3887 raster_config_se &= C_028350_SE_MAP;
3888
3889 if (!se_mask[idx]) {
3890 raster_config_se |=
3891 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3892 } else {
3893 raster_config_se |=
3894 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3895 }
3896 }
3897
3898 pkr0_mask &= rb_mask;
3899 pkr1_mask &= rb_mask;
3900 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3901 raster_config_se &= C_028350_PKR_MAP;
3902
3903 if (!pkr0_mask) {
3904 raster_config_se |=
3905 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3906 } else {
3907 raster_config_se |=
3908 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3909 }
3910 }
3911
3912 if (rb_per_se >= 2) {
3913 unsigned rb0_mask = 1 << (se * rb_per_se);
3914 unsigned rb1_mask = rb0_mask << 1;
3915
3916 rb0_mask &= rb_mask;
3917 rb1_mask &= rb_mask;
3918 if (!rb0_mask || !rb1_mask) {
3919 raster_config_se &= C_028350_RB_MAP_PKR0;
3920
3921 if (!rb0_mask) {
3922 raster_config_se |=
3923 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3924 } else {
3925 raster_config_se |=
3926 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3927 }
3928 }
3929
3930 if (rb_per_se > 2) {
3931 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3932 rb1_mask = rb0_mask << 1;
3933 rb0_mask &= rb_mask;
3934 rb1_mask &= rb_mask;
3935 if (!rb0_mask || !rb1_mask) {
3936 raster_config_se &= C_028350_RB_MAP_PKR1;
3937
3938 if (!rb0_mask) {
3939 raster_config_se |=
3940 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3941 } else {
3942 raster_config_se |=
3943 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3944 }
3945 }
3946 }
3947 }
3948
3949 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3950 if (sctx->b.chip_class < CIK)
3951 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3952 SE_INDEX(se) | SH_BROADCAST_WRITES |
3953 INSTANCE_BROADCAST_WRITES);
3954 else
3955 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3956 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3957 S_030800_INSTANCE_BROADCAST_WRITES(1));
3958 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3959 if (sctx->b.chip_class >= CIK)
3960 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3961 }
3962
3963 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3964 if (sctx->b.chip_class < CIK)
3965 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3966 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3967 INSTANCE_BROADCAST_WRITES);
3968 else
3969 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3970 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3971 S_030800_INSTANCE_BROADCAST_WRITES(1));
3972 }
3973
3974 static void si_init_config(struct si_context *sctx)
3975 {
3976 struct si_screen *sscreen = sctx->screen;
3977 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3978 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3979 unsigned raster_config, raster_config_1;
3980 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3981 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3982 int i;
3983
3984 if (!pm4)
3985 return;
3986
3987 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3988 si_pm4_cmd_add(pm4, 0x80000000);
3989 si_pm4_cmd_add(pm4, 0x80000000);
3990 si_pm4_cmd_end(pm4, false);
3991
3992 /* This enables pipeline stat & streamout queries.
3993 * They are only disabled by blits.
3994 */
3995 si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
3996 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
3997 EVENT_INDEX(0));
3998 si_pm4_cmd_end(pm4, false);
3999
4000 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4001 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4002
4003 /* FIXME calculate these values somehow ??? */
4004 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4005 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4006 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4007
4008 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4009 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4010
4011 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4012 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4013 if (sctx->b.chip_class < CIK)
4014 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4015 S_008A14_CLIP_VTX_REORDER_ENA(1));
4016
4017 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4018 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4019
4020 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4021
4022 for (i = 0; i < 16; i++) {
4023 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
4024 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
4025 }
4026
4027 switch (sctx->screen->b.family) {
4028 case CHIP_TAHITI:
4029 case CHIP_PITCAIRN:
4030 raster_config = 0x2a00126a;
4031 raster_config_1 = 0x00000000;
4032 break;
4033 case CHIP_VERDE:
4034 raster_config = 0x0000124a;
4035 raster_config_1 = 0x00000000;
4036 break;
4037 case CHIP_OLAND:
4038 raster_config = 0x00000082;
4039 raster_config_1 = 0x00000000;
4040 break;
4041 case CHIP_HAINAN:
4042 raster_config = 0x00000000;
4043 raster_config_1 = 0x00000000;
4044 break;
4045 case CHIP_BONAIRE:
4046 raster_config = 0x16000012;
4047 raster_config_1 = 0x00000000;
4048 break;
4049 case CHIP_HAWAII:
4050 raster_config = 0x3a00161a;
4051 raster_config_1 = 0x0000002e;
4052 break;
4053 case CHIP_FIJI:
4054 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4055 /* old kernels with old tiling config */
4056 raster_config = 0x16000012;
4057 raster_config_1 = 0x0000002a;
4058 } else {
4059 raster_config = 0x3a00161a;
4060 raster_config_1 = 0x0000002e;
4061 }
4062 break;
4063 case CHIP_POLARIS10:
4064 raster_config = 0x16000012;
4065 raster_config_1 = 0x0000002a;
4066 break;
4067 case CHIP_POLARIS11:
4068 raster_config = 0x16000012;
4069 raster_config_1 = 0x00000000;
4070 break;
4071 case CHIP_TONGA:
4072 raster_config = 0x16000012;
4073 raster_config_1 = 0x0000002a;
4074 break;
4075 case CHIP_ICELAND:
4076 raster_config = 0x00000002;
4077 raster_config_1 = 0x00000000;
4078 break;
4079 case CHIP_CARRIZO:
4080 raster_config = 0x00000002;
4081 raster_config_1 = 0x00000000;
4082 break;
4083 case CHIP_KAVERI:
4084 /* KV should be 0x00000002, but that causes problems with radeon */
4085 raster_config = 0x00000000; /* 0x00000002 */
4086 raster_config_1 = 0x00000000;
4087 break;
4088 case CHIP_KABINI:
4089 case CHIP_MULLINS:
4090 case CHIP_STONEY:
4091 raster_config = 0x00000000;
4092 raster_config_1 = 0x00000000;
4093 break;
4094 default:
4095 fprintf(stderr,
4096 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4097 raster_config = 0x00000000;
4098 raster_config_1 = 0x00000000;
4099 break;
4100 }
4101
4102 /* Always use the default config when all backends are enabled
4103 * (or when we failed to determine the enabled backends).
4104 */
4105 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4106 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4107 raster_config);
4108 if (sctx->b.chip_class >= CIK)
4109 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4110 raster_config_1);
4111 } else {
4112 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4113 }
4114
4115 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4116 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4117 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4118 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4119 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4120 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4121 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4122
4123 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4124 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
4125 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4126 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4127 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4128 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
4129 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
4130 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
4131 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
4132 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4133 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4134 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4135 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
4136 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
4137 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
4138
4139 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4140 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4141 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4142
4143 if (sctx->b.chip_class >= CIK) {
4144 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4145 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4146 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4147
4148 if (sscreen->b.info.num_good_compute_units /
4149 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4150 /* Too few available compute units per SH. Disallowing
4151 * VS to run on CU0 could hurt us more than late VS
4152 * allocation would help.
4153 *
4154 * LATE_ALLOC_VS = 2 is the highest safe number.
4155 */
4156 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4157 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4158 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4159 } else {
4160 /* Set LATE_ALLOC_VS == 31. It should be less than
4161 * the number of scratch waves. Limitations:
4162 * - VS can't execute on CU0.
4163 * - If HS writes outputs to LDS, LS can't execute on CU0.
4164 */
4165 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
4166 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4167 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4168 }
4169
4170 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4171 }
4172
4173 if (sctx->b.chip_class >= VI) {
4174 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4175 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4176 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4177 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4178 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4179 }
4180
4181 if (sctx->b.family == CHIP_STONEY)
4182 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4183
4184 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4185 if (sctx->b.chip_class >= CIK)
4186 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4187 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4188 RADEON_PRIO_BORDER_COLORS);
4189
4190 si_pm4_upload_indirect_buffer(sctx, pm4);
4191 sctx->init_config = pm4;
4192 }