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radeonsi: Fix hardware state for dual source blending
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include <byteswap.h>
28
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_blitter.h"
32 #include "util/u_helpers.h"
33 #include "util/u_math.h"
34 #include "util/u_pack_color.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_format_s3tc.h"
37 #include "tgsi/tgsi_parse.h"
38 #include "radeonsi_pipe.h"
39 #include "radeonsi_shader.h"
40 #include "si_state.h"
41 #include "sid.h"
42
43 /*
44 * inferred framebuffer and blender state
45 */
46 static void si_update_fb_blend_state(struct r600_context *rctx)
47 {
48 struct si_pm4_state *pm4;
49 struct si_state_blend *blend = rctx->queued.named.blend;
50 uint32_t mask;
51
52 if (blend == NULL)
53 return;
54
55 pm4 = CALLOC_STRUCT(si_pm4_state);
56 if (pm4 == NULL)
57 return;
58
59 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
60 mask &= blend->cb_target_mask;
61 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
62
63 si_pm4_set_state(rctx, fb_blend, pm4);
64 }
65
66 /*
67 * Blender functions
68 */
69
70 static uint32_t si_translate_blend_function(int blend_func)
71 {
72 switch (blend_func) {
73 case PIPE_BLEND_ADD:
74 return V_028780_COMB_DST_PLUS_SRC;
75 case PIPE_BLEND_SUBTRACT:
76 return V_028780_COMB_SRC_MINUS_DST;
77 case PIPE_BLEND_REVERSE_SUBTRACT:
78 return V_028780_COMB_DST_MINUS_SRC;
79 case PIPE_BLEND_MIN:
80 return V_028780_COMB_MIN_DST_SRC;
81 case PIPE_BLEND_MAX:
82 return V_028780_COMB_MAX_DST_SRC;
83 default:
84 R600_ERR("Unknown blend function %d\n", blend_func);
85 assert(0);
86 break;
87 }
88 return 0;
89 }
90
91 static uint32_t si_translate_blend_factor(int blend_fact)
92 {
93 switch (blend_fact) {
94 case PIPE_BLENDFACTOR_ONE:
95 return V_028780_BLEND_ONE;
96 case PIPE_BLENDFACTOR_SRC_COLOR:
97 return V_028780_BLEND_SRC_COLOR;
98 case PIPE_BLENDFACTOR_SRC_ALPHA:
99 return V_028780_BLEND_SRC_ALPHA;
100 case PIPE_BLENDFACTOR_DST_ALPHA:
101 return V_028780_BLEND_DST_ALPHA;
102 case PIPE_BLENDFACTOR_DST_COLOR:
103 return V_028780_BLEND_DST_COLOR;
104 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
105 return V_028780_BLEND_SRC_ALPHA_SATURATE;
106 case PIPE_BLENDFACTOR_CONST_COLOR:
107 return V_028780_BLEND_CONSTANT_COLOR;
108 case PIPE_BLENDFACTOR_CONST_ALPHA:
109 return V_028780_BLEND_CONSTANT_ALPHA;
110 case PIPE_BLENDFACTOR_ZERO:
111 return V_028780_BLEND_ZERO;
112 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
113 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
114 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
115 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
116 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
117 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
118 case PIPE_BLENDFACTOR_INV_DST_COLOR:
119 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
120 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
121 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
122 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
123 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
124 case PIPE_BLENDFACTOR_SRC1_COLOR:
125 return V_028780_BLEND_SRC1_COLOR;
126 case PIPE_BLENDFACTOR_SRC1_ALPHA:
127 return V_028780_BLEND_SRC1_ALPHA;
128 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
129 return V_028780_BLEND_INV_SRC1_COLOR;
130 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
131 return V_028780_BLEND_INV_SRC1_ALPHA;
132 default:
133 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
134 assert(0);
135 break;
136 }
137 return 0;
138 }
139
140 static void *si_create_blend_state(struct pipe_context *ctx,
141 const struct pipe_blend_state *state)
142 {
143 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
144 struct si_pm4_state *pm4 = &blend->pm4;
145
146 uint32_t color_control;
147
148 if (blend == NULL)
149 return NULL;
150
151 color_control = S_028808_MODE(V_028808_CB_NORMAL);
152 if (state->logicop_enable) {
153 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
154 } else {
155 color_control |= S_028808_ROP3(0xcc);
156 }
157 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
158
159 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
160 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
161
162 blend->cb_target_mask = 0;
163 for (int i = 0; i < 8; i++) {
164 /* state->rt entries > 0 only written if independent blending */
165 const int j = state->independent_blend_enable ? i : 0;
166
167 unsigned eqRGB = state->rt[j].rgb_func;
168 unsigned srcRGB = state->rt[j].rgb_src_factor;
169 unsigned dstRGB = state->rt[j].rgb_dst_factor;
170 unsigned eqA = state->rt[j].alpha_func;
171 unsigned srcA = state->rt[j].alpha_src_factor;
172 unsigned dstA = state->rt[j].alpha_dst_factor;
173
174 unsigned blend_cntl = 0;
175
176 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
177 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
178
179 if (!state->rt[j].blend_enable) {
180 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
181 continue;
182 }
183
184 blend_cntl |= S_028780_ENABLE(1);
185 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
186 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
187 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
188
189 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
190 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
191 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
192 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
193 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
194 }
195 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
196 }
197
198 return blend;
199 }
200
201 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
202 {
203 struct r600_context *rctx = (struct r600_context *)ctx;
204 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
205 si_update_fb_blend_state(rctx);
206 }
207
208 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
209 {
210 struct r600_context *rctx = (struct r600_context *)ctx;
211 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
212 }
213
214 static void si_set_blend_color(struct pipe_context *ctx,
215 const struct pipe_blend_color *state)
216 {
217 struct r600_context *rctx = (struct r600_context *)ctx;
218 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
219
220 if (pm4 == NULL)
221 return;
222
223 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
224 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
225 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
226 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
227
228 si_pm4_set_state(rctx, blend_color, pm4);
229 }
230
231 /*
232 * Clipping, scissors and viewport
233 */
234
235 static void si_set_clip_state(struct pipe_context *ctx,
236 const struct pipe_clip_state *state)
237 {
238 struct r600_context *rctx = (struct r600_context *)ctx;
239 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
240 struct pipe_constant_buffer cb;
241
242 if (pm4 == NULL)
243 return;
244
245 for (int i = 0; i < 6; i++) {
246 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
247 fui(state->ucp[i][0]));
248 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
249 fui(state->ucp[i][1]));
250 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
251 fui(state->ucp[i][2]));
252 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
253 fui(state->ucp[i][3]));
254 }
255
256 cb.buffer = NULL;
257 cb.user_buffer = state->ucp;
258 cb.buffer_offset = 0;
259 cb.buffer_size = 4*4*8;
260 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
261 pipe_resource_reference(&cb.buffer, NULL);
262
263 si_pm4_set_state(rctx, clip, pm4);
264 }
265
266 static void si_set_scissor_state(struct pipe_context *ctx,
267 const struct pipe_scissor_state *state)
268 {
269 struct r600_context *rctx = (struct r600_context *)ctx;
270 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
271 uint32_t tl, br;
272
273 if (pm4 == NULL)
274 return;
275
276 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
277 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
278 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
279 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
280 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
281 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
282 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
283 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
284 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
285 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
286
287 si_pm4_set_state(rctx, scissor, pm4);
288 }
289
290 static void si_set_viewport_state(struct pipe_context *ctx,
291 const struct pipe_viewport_state *state)
292 {
293 struct r600_context *rctx = (struct r600_context *)ctx;
294 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
295 struct si_pm4_state *pm4 = &viewport->pm4;
296
297 if (viewport == NULL)
298 return;
299
300 viewport->viewport = *state;
301 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
302 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
303 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
304 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
305 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
306 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
307 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
308 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
309 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
310
311 si_pm4_set_state(rctx, viewport, viewport);
312 }
313
314 /*
315 * inferred state between framebuffer and rasterizer
316 */
317 static void si_update_fb_rs_state(struct r600_context *rctx)
318 {
319 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
320 struct si_pm4_state *pm4;
321 unsigned offset_db_fmt_cntl = 0, depth;
322 float offset_units;
323
324 if (!rs || !rctx->framebuffer.zsbuf)
325 return;
326
327 offset_units = rctx->queued.named.rasterizer->offset_units;
328 switch (rctx->framebuffer.zsbuf->texture->format) {
329 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
330 case PIPE_FORMAT_X8Z24_UNORM:
331 case PIPE_FORMAT_Z24X8_UNORM:
332 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
333 depth = -24;
334 offset_units *= 2.0f;
335 break;
336 case PIPE_FORMAT_Z32_FLOAT:
337 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
338 depth = -23;
339 offset_units *= 1.0f;
340 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
341 break;
342 case PIPE_FORMAT_Z16_UNORM:
343 depth = -16;
344 offset_units *= 4.0f;
345 break;
346 default:
347 return;
348 }
349
350 pm4 = CALLOC_STRUCT(si_pm4_state);
351 /* FIXME some of those reg can be computed with cso */
352 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
353 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
354 fui(rctx->queued.named.rasterizer->offset_scale));
355 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
356 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
357 fui(rctx->queued.named.rasterizer->offset_scale));
358 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
359 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
360
361 si_pm4_set_state(rctx, fb_rs, pm4);
362 }
363
364 /*
365 * Rasterizer
366 */
367
368 static uint32_t si_translate_fill(uint32_t func)
369 {
370 switch(func) {
371 case PIPE_POLYGON_MODE_FILL:
372 return V_028814_X_DRAW_TRIANGLES;
373 case PIPE_POLYGON_MODE_LINE:
374 return V_028814_X_DRAW_LINES;
375 case PIPE_POLYGON_MODE_POINT:
376 return V_028814_X_DRAW_POINTS;
377 default:
378 assert(0);
379 return V_028814_X_DRAW_POINTS;
380 }
381 }
382
383 static void *si_create_rs_state(struct pipe_context *ctx,
384 const struct pipe_rasterizer_state *state)
385 {
386 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
387 struct si_pm4_state *pm4 = &rs->pm4;
388 unsigned tmp;
389 unsigned prov_vtx = 1, polygon_dual_mode;
390 unsigned clip_rule;
391 float psize_min, psize_max;
392
393 if (rs == NULL) {
394 return NULL;
395 }
396
397 rs->two_side = state->light_twoside;
398 rs->clip_plane_enable = state->clip_plane_enable;
399
400 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
401 state->fill_back != PIPE_POLYGON_MODE_FILL);
402
403 if (state->flatshade_first)
404 prov_vtx = 0;
405
406 rs->flatshade = state->flatshade;
407 rs->sprite_coord_enable = state->sprite_coord_enable;
408 rs->pa_sc_line_stipple = state->line_stipple_enable ?
409 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
410 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
411 rs->pa_su_sc_mode_cntl =
412 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
413 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
414 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
415 S_028814_FACE(!state->front_ccw) |
416 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
417 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
418 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
419 S_028814_POLY_MODE(polygon_dual_mode) |
420 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
421 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
422 rs->pa_cl_clip_cntl =
423 S_028810_PS_UCP_MODE(3) |
424 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
425 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
426 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
427
428 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
429
430 /* offset */
431 rs->offset_units = state->offset_units;
432 rs->offset_scale = state->offset_scale * 12.0f;
433
434 tmp = S_0286D4_FLAT_SHADE_ENA(1);
435 if (state->sprite_coord_enable) {
436 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
437 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
438 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
439 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
440 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
441 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
442 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
443 }
444 }
445 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
446
447 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
448 /* point size 12.4 fixed point */
449 tmp = (unsigned)(state->point_size * 8.0);
450 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
451
452 if (state->point_size_per_vertex) {
453 psize_min = util_get_min_point_size(state);
454 psize_max = 8192;
455 } else {
456 /* Force the point size to be as if the vertex output was disabled. */
457 psize_min = state->point_size;
458 psize_max = state->point_size;
459 }
460 /* Divide by two, because 0.5 = 1 pixel. */
461 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
462 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
463 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
464
465 tmp = (unsigned)state->line_width * 8;
466 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
467 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
468 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
469
470 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
471 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
472 S_028BE4_PIX_CENTER(state->half_pixel_center));
473 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
474 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
475 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
476 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
477
478 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
479 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
480
481 return rs;
482 }
483
484 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
485 {
486 struct r600_context *rctx = (struct r600_context *)ctx;
487 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
488
489 if (state == NULL)
490 return;
491
492 // TODO
493 rctx->sprite_coord_enable = rs->sprite_coord_enable;
494 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
495 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
496
497 si_pm4_bind_state(rctx, rasterizer, rs);
498 si_update_fb_rs_state(rctx);
499 }
500
501 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
502 {
503 struct r600_context *rctx = (struct r600_context *)ctx;
504 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
505 }
506
507 /*
508 * infeered state between dsa and stencil ref
509 */
510 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
511 {
512 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
513 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
514 struct si_state_dsa *dsa = rctx->queued.named.dsa;
515
516 if (pm4 == NULL)
517 return;
518
519 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
520 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
521 S_028430_STENCILMASK(dsa->valuemask[0]) |
522 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
523 S_028430_STENCILOPVAL(1));
524 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
525 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
526 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
527 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
528 S_028434_STENCILOPVAL_BF(1));
529
530 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
531 }
532
533 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
534 const struct pipe_stencil_ref *state)
535 {
536 struct r600_context *rctx = (struct r600_context *)ctx;
537 rctx->stencil_ref = *state;
538 si_update_dsa_stencil_ref(rctx);
539 }
540
541
542 /*
543 * DSA
544 */
545
546 static uint32_t si_translate_stencil_op(int s_op)
547 {
548 switch (s_op) {
549 case PIPE_STENCIL_OP_KEEP:
550 return V_02842C_STENCIL_KEEP;
551 case PIPE_STENCIL_OP_ZERO:
552 return V_02842C_STENCIL_ZERO;
553 case PIPE_STENCIL_OP_REPLACE:
554 return V_02842C_STENCIL_REPLACE_TEST;
555 case PIPE_STENCIL_OP_INCR:
556 return V_02842C_STENCIL_ADD_CLAMP;
557 case PIPE_STENCIL_OP_DECR:
558 return V_02842C_STENCIL_SUB_CLAMP;
559 case PIPE_STENCIL_OP_INCR_WRAP:
560 return V_02842C_STENCIL_ADD_WRAP;
561 case PIPE_STENCIL_OP_DECR_WRAP:
562 return V_02842C_STENCIL_SUB_WRAP;
563 case PIPE_STENCIL_OP_INVERT:
564 return V_02842C_STENCIL_INVERT;
565 default:
566 R600_ERR("Unknown stencil op %d", s_op);
567 assert(0);
568 break;
569 }
570 return 0;
571 }
572
573 static void *si_create_dsa_state(struct pipe_context *ctx,
574 const struct pipe_depth_stencil_alpha_state *state)
575 {
576 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
577 struct si_pm4_state *pm4 = &dsa->pm4;
578 unsigned db_depth_control;
579 unsigned db_render_override, db_render_control;
580 uint32_t db_stencil_control = 0;
581
582 if (dsa == NULL) {
583 return NULL;
584 }
585
586 dsa->valuemask[0] = state->stencil[0].valuemask;
587 dsa->valuemask[1] = state->stencil[1].valuemask;
588 dsa->writemask[0] = state->stencil[0].writemask;
589 dsa->writemask[1] = state->stencil[1].writemask;
590
591 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
592 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
593 S_028800_ZFUNC(state->depth.func);
594
595 /* stencil */
596 if (state->stencil[0].enabled) {
597 db_depth_control |= S_028800_STENCIL_ENABLE(1);
598 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
599 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
600 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
601 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
602
603 if (state->stencil[1].enabled) {
604 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
605 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
606 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
607 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
608 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
609 }
610 }
611
612 /* alpha */
613 if (state->alpha.enabled) {
614 dsa->alpha_func = state->alpha.func;
615 dsa->alpha_ref = state->alpha.ref_value;
616 } else {
617 dsa->alpha_func = PIPE_FUNC_ALWAYS;
618 }
619
620 /* misc */
621 db_render_control = 0;
622 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
623 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
624 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
625 /* TODO db_render_override depends on query */
626 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
627 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
628 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
629 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
630 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
631 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
632 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
633 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
634 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
635 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
636 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
637 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
638 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
639 dsa->db_render_override = db_render_override;
640
641 return dsa;
642 }
643
644 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
645 {
646 struct r600_context *rctx = (struct r600_context *)ctx;
647 struct si_state_dsa *dsa = state;
648
649 if (state == NULL)
650 return;
651
652 si_pm4_bind_state(rctx, dsa, dsa);
653 si_update_dsa_stencil_ref(rctx);
654 }
655
656 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
657 {
658 struct r600_context *rctx = (struct r600_context *)ctx;
659 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
660 }
661
662 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
663 bool copy_stencil)
664 {
665 struct pipe_depth_stencil_alpha_state dsa;
666 struct si_state_dsa *state;
667
668 memset(&dsa, 0, sizeof(dsa));
669
670 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
671 if (copy_depth || copy_stencil) {
672 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
673 S_028000_DEPTH_COPY(copy_depth) |
674 S_028000_STENCIL_COPY(copy_stencil) |
675 S_028000_COPY_CENTROID(1));
676 } else {
677 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
678 S_028000_DEPTH_COMPRESS_DISABLE(1) |
679 S_028000_STENCIL_COMPRESS_DISABLE(1));
680 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
681 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
682 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
683 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
684 S_02800C_DISABLE_TILE_RATE_TILES(1));
685 }
686
687 return state;
688 }
689
690 /*
691 * format translation
692 */
693 static uint32_t si_translate_colorformat(enum pipe_format format)
694 {
695 switch (format) {
696 /* 8-bit buffers. */
697 case PIPE_FORMAT_A8_UNORM:
698 case PIPE_FORMAT_A8_SNORM:
699 case PIPE_FORMAT_A8_UINT:
700 case PIPE_FORMAT_A8_SINT:
701 case PIPE_FORMAT_I8_UNORM:
702 case PIPE_FORMAT_I8_SNORM:
703 case PIPE_FORMAT_I8_UINT:
704 case PIPE_FORMAT_I8_SINT:
705 case PIPE_FORMAT_L8_UNORM:
706 case PIPE_FORMAT_L8_SNORM:
707 case PIPE_FORMAT_L8_UINT:
708 case PIPE_FORMAT_L8_SINT:
709 case PIPE_FORMAT_L8_SRGB:
710 case PIPE_FORMAT_R8_UNORM:
711 case PIPE_FORMAT_R8_SNORM:
712 case PIPE_FORMAT_R8_UINT:
713 case PIPE_FORMAT_R8_SINT:
714 return V_028C70_COLOR_8;
715
716 /* 16-bit buffers. */
717 case PIPE_FORMAT_B5G6R5_UNORM:
718 return V_028C70_COLOR_5_6_5;
719
720 case PIPE_FORMAT_B5G5R5A1_UNORM:
721 case PIPE_FORMAT_B5G5R5X1_UNORM:
722 return V_028C70_COLOR_1_5_5_5;
723
724 case PIPE_FORMAT_B4G4R4A4_UNORM:
725 case PIPE_FORMAT_B4G4R4X4_UNORM:
726 return V_028C70_COLOR_4_4_4_4;
727
728 case PIPE_FORMAT_L8A8_UNORM:
729 case PIPE_FORMAT_L8A8_SNORM:
730 case PIPE_FORMAT_L8A8_UINT:
731 case PIPE_FORMAT_L8A8_SINT:
732 case PIPE_FORMAT_R8G8_SNORM:
733 case PIPE_FORMAT_R8G8_UNORM:
734 case PIPE_FORMAT_R8G8_UINT:
735 case PIPE_FORMAT_R8G8_SINT:
736 return V_028C70_COLOR_8_8;
737
738 case PIPE_FORMAT_Z16_UNORM:
739 case PIPE_FORMAT_R16_UNORM:
740 case PIPE_FORMAT_R16_SNORM:
741 case PIPE_FORMAT_R16_UINT:
742 case PIPE_FORMAT_R16_SINT:
743 case PIPE_FORMAT_R16_FLOAT:
744 case PIPE_FORMAT_L16_UNORM:
745 case PIPE_FORMAT_L16_SNORM:
746 case PIPE_FORMAT_L16_FLOAT:
747 case PIPE_FORMAT_I16_UNORM:
748 case PIPE_FORMAT_I16_SNORM:
749 case PIPE_FORMAT_I16_FLOAT:
750 case PIPE_FORMAT_A16_UNORM:
751 case PIPE_FORMAT_A16_SNORM:
752 case PIPE_FORMAT_A16_FLOAT:
753 return V_028C70_COLOR_16;
754
755 /* 32-bit buffers. */
756 case PIPE_FORMAT_A8B8G8R8_SRGB:
757 case PIPE_FORMAT_A8B8G8R8_UNORM:
758 case PIPE_FORMAT_A8R8G8B8_UNORM:
759 case PIPE_FORMAT_B8G8R8A8_SRGB:
760 case PIPE_FORMAT_B8G8R8A8_UNORM:
761 case PIPE_FORMAT_B8G8R8X8_UNORM:
762 case PIPE_FORMAT_R8G8B8A8_SNORM:
763 case PIPE_FORMAT_R8G8B8A8_UNORM:
764 case PIPE_FORMAT_R8G8B8X8_UNORM:
765 case PIPE_FORMAT_R8G8B8X8_SNORM:
766 case PIPE_FORMAT_R8G8B8X8_SRGB:
767 case PIPE_FORMAT_R8G8B8X8_UINT:
768 case PIPE_FORMAT_R8G8B8X8_SINT:
769 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
770 case PIPE_FORMAT_X8B8G8R8_UNORM:
771 case PIPE_FORMAT_X8R8G8B8_UNORM:
772 case PIPE_FORMAT_R8G8B8A8_SSCALED:
773 case PIPE_FORMAT_R8G8B8A8_USCALED:
774 case PIPE_FORMAT_R8G8B8A8_SINT:
775 case PIPE_FORMAT_R8G8B8A8_UINT:
776 return V_028C70_COLOR_8_8_8_8;
777
778 case PIPE_FORMAT_R10G10B10A2_UNORM:
779 case PIPE_FORMAT_R10G10B10X2_SNORM:
780 case PIPE_FORMAT_B10G10R10A2_UNORM:
781 case PIPE_FORMAT_B10G10R10A2_UINT:
782 case PIPE_FORMAT_B10G10R10X2_UNORM:
783 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
784 return V_028C70_COLOR_2_10_10_10;
785
786 case PIPE_FORMAT_Z24X8_UNORM:
787 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
788 return V_028C70_COLOR_8_24;
789
790 case PIPE_FORMAT_S8X24_UINT:
791 case PIPE_FORMAT_X8Z24_UNORM:
792 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
793 return V_028C70_COLOR_24_8;
794
795 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
796 return V_028C70_COLOR_X24_8_32_FLOAT;
797
798 case PIPE_FORMAT_I32_FLOAT:
799 case PIPE_FORMAT_L32_FLOAT:
800 case PIPE_FORMAT_R32_FLOAT:
801 case PIPE_FORMAT_A32_FLOAT:
802 case PIPE_FORMAT_Z32_FLOAT:
803 return V_028C70_COLOR_32;
804
805 case PIPE_FORMAT_L16A16_UNORM:
806 case PIPE_FORMAT_L16A16_SNORM:
807 case PIPE_FORMAT_L16A16_FLOAT:
808 case PIPE_FORMAT_R16G16_SSCALED:
809 case PIPE_FORMAT_R16G16_UNORM:
810 case PIPE_FORMAT_R16G16_SNORM:
811 case PIPE_FORMAT_R16G16_UINT:
812 case PIPE_FORMAT_R16G16_SINT:
813 case PIPE_FORMAT_R16G16_FLOAT:
814 return V_028C70_COLOR_16_16;
815
816 case PIPE_FORMAT_R11G11B10_FLOAT:
817 return V_028C70_COLOR_10_11_11;
818
819 /* 64-bit buffers. */
820 case PIPE_FORMAT_R16G16B16A16_UINT:
821 case PIPE_FORMAT_R16G16B16A16_SINT:
822 case PIPE_FORMAT_R16G16B16A16_USCALED:
823 case PIPE_FORMAT_R16G16B16A16_SSCALED:
824 case PIPE_FORMAT_R16G16B16A16_UNORM:
825 case PIPE_FORMAT_R16G16B16A16_SNORM:
826 case PIPE_FORMAT_R16G16B16A16_FLOAT:
827 case PIPE_FORMAT_R16G16B16X16_UNORM:
828 case PIPE_FORMAT_R16G16B16X16_SNORM:
829 case PIPE_FORMAT_R16G16B16X16_FLOAT:
830 case PIPE_FORMAT_R16G16B16X16_UINT:
831 case PIPE_FORMAT_R16G16B16X16_SINT:
832 return V_028C70_COLOR_16_16_16_16;
833
834 case PIPE_FORMAT_L32A32_FLOAT:
835 case PIPE_FORMAT_L32A32_UINT:
836 case PIPE_FORMAT_L32A32_SINT:
837 case PIPE_FORMAT_R32G32_FLOAT:
838 case PIPE_FORMAT_R32G32_USCALED:
839 case PIPE_FORMAT_R32G32_SSCALED:
840 case PIPE_FORMAT_R32G32_SINT:
841 case PIPE_FORMAT_R32G32_UINT:
842 return V_028C70_COLOR_32_32;
843
844 /* 128-bit buffers. */
845 case PIPE_FORMAT_R32G32B32A32_SNORM:
846 case PIPE_FORMAT_R32G32B32A32_UNORM:
847 case PIPE_FORMAT_R32G32B32A32_SSCALED:
848 case PIPE_FORMAT_R32G32B32A32_USCALED:
849 case PIPE_FORMAT_R32G32B32A32_SINT:
850 case PIPE_FORMAT_R32G32B32A32_UINT:
851 case PIPE_FORMAT_R32G32B32A32_FLOAT:
852 case PIPE_FORMAT_R32G32B32X32_FLOAT:
853 case PIPE_FORMAT_R32G32B32X32_UINT:
854 case PIPE_FORMAT_R32G32B32X32_SINT:
855 return V_028C70_COLOR_32_32_32_32;
856
857 /* YUV buffers. */
858 case PIPE_FORMAT_UYVY:
859 case PIPE_FORMAT_YUYV:
860 /* 96-bit buffers. */
861 case PIPE_FORMAT_R32G32B32_FLOAT:
862 /* 8-bit buffers. */
863 case PIPE_FORMAT_L4A4_UNORM:
864 case PIPE_FORMAT_R4A4_UNORM:
865 case PIPE_FORMAT_A4R4_UNORM:
866 default:
867 return V_028C70_COLOR_INVALID; /* Unsupported. */
868 }
869 }
870
871 static uint32_t si_translate_colorswap(enum pipe_format format)
872 {
873 switch (format) {
874 /* 8-bit buffers. */
875 case PIPE_FORMAT_L4A4_UNORM:
876 case PIPE_FORMAT_A4R4_UNORM:
877 return V_028C70_SWAP_ALT;
878
879 case PIPE_FORMAT_A8_UNORM:
880 case PIPE_FORMAT_A8_SNORM:
881 case PIPE_FORMAT_A8_UINT:
882 case PIPE_FORMAT_A8_SINT:
883 case PIPE_FORMAT_R4A4_UNORM:
884 return V_028C70_SWAP_ALT_REV;
885 case PIPE_FORMAT_I8_UNORM:
886 case PIPE_FORMAT_I8_SNORM:
887 case PIPE_FORMAT_L8_UNORM:
888 case PIPE_FORMAT_L8_SNORM:
889 case PIPE_FORMAT_I8_UINT:
890 case PIPE_FORMAT_I8_SINT:
891 case PIPE_FORMAT_L8_UINT:
892 case PIPE_FORMAT_L8_SINT:
893 case PIPE_FORMAT_L8_SRGB:
894 case PIPE_FORMAT_R8_UNORM:
895 case PIPE_FORMAT_R8_SNORM:
896 case PIPE_FORMAT_R8_UINT:
897 case PIPE_FORMAT_R8_SINT:
898 return V_028C70_SWAP_STD;
899
900 /* 16-bit buffers. */
901 case PIPE_FORMAT_B5G6R5_UNORM:
902 return V_028C70_SWAP_STD_REV;
903
904 case PIPE_FORMAT_B5G5R5A1_UNORM:
905 case PIPE_FORMAT_B5G5R5X1_UNORM:
906 return V_028C70_SWAP_ALT;
907
908 case PIPE_FORMAT_B4G4R4A4_UNORM:
909 case PIPE_FORMAT_B4G4R4X4_UNORM:
910 return V_028C70_SWAP_ALT;
911
912 case PIPE_FORMAT_Z16_UNORM:
913 return V_028C70_SWAP_STD;
914
915 case PIPE_FORMAT_L8A8_UNORM:
916 case PIPE_FORMAT_L8A8_SNORM:
917 case PIPE_FORMAT_L8A8_UINT:
918 case PIPE_FORMAT_L8A8_SINT:
919 return V_028C70_SWAP_ALT;
920 case PIPE_FORMAT_R8G8_SNORM:
921 case PIPE_FORMAT_R8G8_UNORM:
922 case PIPE_FORMAT_R8G8_UINT:
923 case PIPE_FORMAT_R8G8_SINT:
924 return V_028C70_SWAP_STD;
925
926 case PIPE_FORMAT_I16_UNORM:
927 case PIPE_FORMAT_I16_SNORM:
928 case PIPE_FORMAT_I16_FLOAT:
929 case PIPE_FORMAT_L16_UNORM:
930 case PIPE_FORMAT_L16_SNORM:
931 case PIPE_FORMAT_L16_FLOAT:
932 case PIPE_FORMAT_R16_UNORM:
933 case PIPE_FORMAT_R16_SNORM:
934 case PIPE_FORMAT_R16_UINT:
935 case PIPE_FORMAT_R16_SINT:
936 case PIPE_FORMAT_R16_FLOAT:
937 return V_028C70_SWAP_STD;
938
939 case PIPE_FORMAT_A16_UNORM:
940 case PIPE_FORMAT_A16_SNORM:
941 case PIPE_FORMAT_A16_FLOAT:
942 return V_028C70_SWAP_ALT_REV;
943
944 /* 32-bit buffers. */
945 case PIPE_FORMAT_A8B8G8R8_SRGB:
946 return V_028C70_SWAP_STD_REV;
947 case PIPE_FORMAT_B8G8R8A8_SRGB:
948 return V_028C70_SWAP_ALT;
949
950 case PIPE_FORMAT_B8G8R8A8_UNORM:
951 case PIPE_FORMAT_B8G8R8X8_UNORM:
952 return V_028C70_SWAP_ALT;
953
954 case PIPE_FORMAT_A8R8G8B8_UNORM:
955 case PIPE_FORMAT_X8R8G8B8_UNORM:
956 return V_028C70_SWAP_ALT_REV;
957 case PIPE_FORMAT_R8G8B8A8_SNORM:
958 case PIPE_FORMAT_R8G8B8A8_UNORM:
959 case PIPE_FORMAT_R8G8B8A8_SSCALED:
960 case PIPE_FORMAT_R8G8B8A8_USCALED:
961 case PIPE_FORMAT_R8G8B8A8_SINT:
962 case PIPE_FORMAT_R8G8B8A8_UINT:
963 case PIPE_FORMAT_R8G8B8X8_UNORM:
964 case PIPE_FORMAT_R8G8B8X8_SNORM:
965 case PIPE_FORMAT_R8G8B8X8_SRGB:
966 case PIPE_FORMAT_R8G8B8X8_UINT:
967 case PIPE_FORMAT_R8G8B8X8_SINT:
968 return V_028C70_SWAP_STD;
969
970 case PIPE_FORMAT_A8B8G8R8_UNORM:
971 case PIPE_FORMAT_X8B8G8R8_UNORM:
972 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
973 return V_028C70_SWAP_STD_REV;
974
975 case PIPE_FORMAT_Z24X8_UNORM:
976 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
977 return V_028C70_SWAP_STD;
978
979 case PIPE_FORMAT_S8X24_UINT:
980 case PIPE_FORMAT_X8Z24_UNORM:
981 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
982 return V_028C70_SWAP_STD_REV;
983
984 case PIPE_FORMAT_R10G10B10A2_UNORM:
985 case PIPE_FORMAT_R10G10B10X2_SNORM:
986 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
987 return V_028C70_SWAP_STD;
988
989 case PIPE_FORMAT_B10G10R10A2_UNORM:
990 case PIPE_FORMAT_B10G10R10A2_UINT:
991 case PIPE_FORMAT_B10G10R10X2_UNORM:
992 return V_028C70_SWAP_ALT;
993
994 case PIPE_FORMAT_R11G11B10_FLOAT:
995 case PIPE_FORMAT_I32_FLOAT:
996 case PIPE_FORMAT_L32_FLOAT:
997 case PIPE_FORMAT_R32_FLOAT:
998 case PIPE_FORMAT_R32_UINT:
999 case PIPE_FORMAT_R32_SINT:
1000 case PIPE_FORMAT_Z32_FLOAT:
1001 case PIPE_FORMAT_R16G16_FLOAT:
1002 case PIPE_FORMAT_R16G16_UNORM:
1003 case PIPE_FORMAT_R16G16_SNORM:
1004 case PIPE_FORMAT_R16G16_UINT:
1005 case PIPE_FORMAT_R16G16_SINT:
1006 return V_028C70_SWAP_STD;
1007
1008 case PIPE_FORMAT_L16A16_UNORM:
1009 case PIPE_FORMAT_L16A16_SNORM:
1010 case PIPE_FORMAT_L16A16_FLOAT:
1011 return V_028C70_SWAP_ALT;
1012
1013 case PIPE_FORMAT_A32_FLOAT:
1014 return V_028C70_SWAP_ALT_REV;
1015
1016 /* 64-bit buffers. */
1017 case PIPE_FORMAT_R32G32_FLOAT:
1018 case PIPE_FORMAT_R32G32_UINT:
1019 case PIPE_FORMAT_R32G32_SINT:
1020 case PIPE_FORMAT_R16G16B16A16_UNORM:
1021 case PIPE_FORMAT_R16G16B16A16_SNORM:
1022 case PIPE_FORMAT_R16G16B16A16_USCALED:
1023 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1024 case PIPE_FORMAT_R16G16B16A16_UINT:
1025 case PIPE_FORMAT_R16G16B16A16_SINT:
1026 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1027 case PIPE_FORMAT_R16G16B16X16_UNORM:
1028 case PIPE_FORMAT_R16G16B16X16_SNORM:
1029 case PIPE_FORMAT_R16G16B16X16_FLOAT:
1030 case PIPE_FORMAT_R16G16B16X16_UINT:
1031 case PIPE_FORMAT_R16G16B16X16_SINT:
1032 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1033 return V_028C70_SWAP_STD;
1034
1035 case PIPE_FORMAT_L32A32_FLOAT:
1036 case PIPE_FORMAT_L32A32_UINT:
1037 case PIPE_FORMAT_L32A32_SINT:
1038 return V_028C70_SWAP_ALT;
1039
1040 /* 128-bit buffers. */
1041 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1042 case PIPE_FORMAT_R32G32B32A32_SNORM:
1043 case PIPE_FORMAT_R32G32B32A32_UNORM:
1044 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1045 case PIPE_FORMAT_R32G32B32A32_USCALED:
1046 case PIPE_FORMAT_R32G32B32A32_SINT:
1047 case PIPE_FORMAT_R32G32B32A32_UINT:
1048 case PIPE_FORMAT_R32G32B32X32_FLOAT:
1049 case PIPE_FORMAT_R32G32B32X32_UINT:
1050 case PIPE_FORMAT_R32G32B32X32_SINT:
1051 return V_028C70_SWAP_STD;
1052 default:
1053 R600_ERR("unsupported colorswap format %d\n", format);
1054 return ~0U;
1055 }
1056 return ~0U;
1057 }
1058
1059 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1060 {
1061 if (R600_BIG_ENDIAN) {
1062 switch(colorformat) {
1063 /* 8-bit buffers. */
1064 case V_028C70_COLOR_8:
1065 return V_028C70_ENDIAN_NONE;
1066
1067 /* 16-bit buffers. */
1068 case V_028C70_COLOR_5_6_5:
1069 case V_028C70_COLOR_1_5_5_5:
1070 case V_028C70_COLOR_4_4_4_4:
1071 case V_028C70_COLOR_16:
1072 case V_028C70_COLOR_8_8:
1073 return V_028C70_ENDIAN_8IN16;
1074
1075 /* 32-bit buffers. */
1076 case V_028C70_COLOR_8_8_8_8:
1077 case V_028C70_COLOR_2_10_10_10:
1078 case V_028C70_COLOR_8_24:
1079 case V_028C70_COLOR_24_8:
1080 case V_028C70_COLOR_16_16:
1081 return V_028C70_ENDIAN_8IN32;
1082
1083 /* 64-bit buffers. */
1084 case V_028C70_COLOR_16_16_16_16:
1085 return V_028C70_ENDIAN_8IN16;
1086
1087 case V_028C70_COLOR_32_32:
1088 return V_028C70_ENDIAN_8IN32;
1089
1090 /* 128-bit buffers. */
1091 case V_028C70_COLOR_32_32_32_32:
1092 return V_028C70_ENDIAN_8IN32;
1093 default:
1094 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1095 }
1096 } else {
1097 return V_028C70_ENDIAN_NONE;
1098 }
1099 }
1100
1101 /* Returns the size in bits of the widest component of a CB format */
1102 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1103 {
1104 switch(colorformat) {
1105 case V_028C70_COLOR_4_4_4_4:
1106 return 4;
1107
1108 case V_028C70_COLOR_1_5_5_5:
1109 case V_028C70_COLOR_5_5_5_1:
1110 return 5;
1111
1112 case V_028C70_COLOR_5_6_5:
1113 return 6;
1114
1115 case V_028C70_COLOR_8:
1116 case V_028C70_COLOR_8_8:
1117 case V_028C70_COLOR_8_8_8_8:
1118 return 8;
1119
1120 case V_028C70_COLOR_10_10_10_2:
1121 case V_028C70_COLOR_2_10_10_10:
1122 return 10;
1123
1124 case V_028C70_COLOR_10_11_11:
1125 case V_028C70_COLOR_11_11_10:
1126 return 11;
1127
1128 case V_028C70_COLOR_16:
1129 case V_028C70_COLOR_16_16:
1130 case V_028C70_COLOR_16_16_16_16:
1131 return 16;
1132
1133 case V_028C70_COLOR_8_24:
1134 case V_028C70_COLOR_24_8:
1135 return 24;
1136
1137 case V_028C70_COLOR_32:
1138 case V_028C70_COLOR_32_32:
1139 case V_028C70_COLOR_32_32_32_32:
1140 case V_028C70_COLOR_X24_8_32_FLOAT:
1141 return 32;
1142 }
1143
1144 assert(!"Unknown maximum component size");
1145 return 0;
1146 }
1147
1148 static uint32_t si_translate_dbformat(enum pipe_format format)
1149 {
1150 switch (format) {
1151 case PIPE_FORMAT_Z16_UNORM:
1152 return V_028040_Z_16;
1153 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1154 case PIPE_FORMAT_X8Z24_UNORM:
1155 case PIPE_FORMAT_Z24X8_UNORM:
1156 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1157 return V_028040_Z_24; /* deprecated on SI */
1158 case PIPE_FORMAT_Z32_FLOAT:
1159 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1160 return V_028040_Z_32_FLOAT;
1161 default:
1162 return V_028040_Z_INVALID;
1163 }
1164 }
1165
1166 /*
1167 * Texture translation
1168 */
1169
1170 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1171 enum pipe_format format,
1172 const struct util_format_description *desc,
1173 int first_non_void)
1174 {
1175 struct r600_screen *rscreen = (struct r600_screen*)screen;
1176 bool enable_s3tc = rscreen->info.drm_minor >= 31;
1177 boolean uniform = TRUE;
1178 int i;
1179
1180 /* Colorspace (return non-RGB formats directly). */
1181 switch (desc->colorspace) {
1182 /* Depth stencil formats */
1183 case UTIL_FORMAT_COLORSPACE_ZS:
1184 switch (format) {
1185 case PIPE_FORMAT_Z16_UNORM:
1186 return V_008F14_IMG_DATA_FORMAT_16;
1187 case PIPE_FORMAT_X24S8_UINT:
1188 case PIPE_FORMAT_Z24X8_UNORM:
1189 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1190 return V_008F14_IMG_DATA_FORMAT_8_24;
1191 case PIPE_FORMAT_X8Z24_UNORM:
1192 case PIPE_FORMAT_S8X24_UINT:
1193 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1194 return V_008F14_IMG_DATA_FORMAT_24_8;
1195 case PIPE_FORMAT_S8_UINT:
1196 return V_008F14_IMG_DATA_FORMAT_8;
1197 case PIPE_FORMAT_Z32_FLOAT:
1198 return V_008F14_IMG_DATA_FORMAT_32;
1199 case PIPE_FORMAT_X32_S8X24_UINT:
1200 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1201 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1202 default:
1203 goto out_unknown;
1204 }
1205
1206 case UTIL_FORMAT_COLORSPACE_YUV:
1207 goto out_unknown; /* TODO */
1208
1209 case UTIL_FORMAT_COLORSPACE_SRGB:
1210 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1211 goto out_unknown;
1212 break;
1213
1214 default:
1215 break;
1216 }
1217
1218 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1219 if (!enable_s3tc)
1220 goto out_unknown;
1221
1222 switch (format) {
1223 case PIPE_FORMAT_RGTC1_SNORM:
1224 case PIPE_FORMAT_LATC1_SNORM:
1225 case PIPE_FORMAT_RGTC1_UNORM:
1226 case PIPE_FORMAT_LATC1_UNORM:
1227 return V_008F14_IMG_DATA_FORMAT_BC4;
1228 case PIPE_FORMAT_RGTC2_SNORM:
1229 case PIPE_FORMAT_LATC2_SNORM:
1230 case PIPE_FORMAT_RGTC2_UNORM:
1231 case PIPE_FORMAT_LATC2_UNORM:
1232 return V_008F14_IMG_DATA_FORMAT_BC5;
1233 default:
1234 goto out_unknown;
1235 }
1236 }
1237
1238 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1239
1240 if (!enable_s3tc)
1241 goto out_unknown;
1242
1243 if (!util_format_s3tc_enabled) {
1244 goto out_unknown;
1245 }
1246
1247 switch (format) {
1248 case PIPE_FORMAT_DXT1_RGB:
1249 case PIPE_FORMAT_DXT1_RGBA:
1250 case PIPE_FORMAT_DXT1_SRGB:
1251 case PIPE_FORMAT_DXT1_SRGBA:
1252 return V_008F14_IMG_DATA_FORMAT_BC1;
1253 case PIPE_FORMAT_DXT3_RGBA:
1254 case PIPE_FORMAT_DXT3_SRGBA:
1255 return V_008F14_IMG_DATA_FORMAT_BC2;
1256 case PIPE_FORMAT_DXT5_RGBA:
1257 case PIPE_FORMAT_DXT5_SRGBA:
1258 return V_008F14_IMG_DATA_FORMAT_BC3;
1259 default:
1260 goto out_unknown;
1261 }
1262 }
1263
1264 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1265 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1266 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1267 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1268 }
1269
1270 /* R8G8Bx_SNORM - TODO CxV8U8 */
1271
1272 /* See whether the components are of the same size. */
1273 for (i = 1; i < desc->nr_channels; i++) {
1274 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1275 }
1276
1277 /* Non-uniform formats. */
1278 if (!uniform) {
1279 switch(desc->nr_channels) {
1280 case 3:
1281 if (desc->channel[0].size == 5 &&
1282 desc->channel[1].size == 6 &&
1283 desc->channel[2].size == 5) {
1284 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1285 }
1286 goto out_unknown;
1287 case 4:
1288 if (desc->channel[0].size == 5 &&
1289 desc->channel[1].size == 5 &&
1290 desc->channel[2].size == 5 &&
1291 desc->channel[3].size == 1) {
1292 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1293 }
1294 if (desc->channel[0].size == 10 &&
1295 desc->channel[1].size == 10 &&
1296 desc->channel[2].size == 10 &&
1297 desc->channel[3].size == 2) {
1298 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1299 }
1300 goto out_unknown;
1301 }
1302 goto out_unknown;
1303 }
1304
1305 if (first_non_void < 0 || first_non_void > 3)
1306 goto out_unknown;
1307
1308 /* uniform formats */
1309 switch (desc->channel[first_non_void].size) {
1310 case 4:
1311 switch (desc->nr_channels) {
1312 #if 0 /* Not supported for render targets */
1313 case 2:
1314 return V_008F14_IMG_DATA_FORMAT_4_4;
1315 #endif
1316 case 4:
1317 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1318 }
1319 break;
1320 case 8:
1321 switch (desc->nr_channels) {
1322 case 1:
1323 return V_008F14_IMG_DATA_FORMAT_8;
1324 case 2:
1325 return V_008F14_IMG_DATA_FORMAT_8_8;
1326 case 4:
1327 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1328 }
1329 break;
1330 case 16:
1331 switch (desc->nr_channels) {
1332 case 1:
1333 return V_008F14_IMG_DATA_FORMAT_16;
1334 case 2:
1335 return V_008F14_IMG_DATA_FORMAT_16_16;
1336 case 4:
1337 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1338 }
1339 break;
1340 case 32:
1341 switch (desc->nr_channels) {
1342 case 1:
1343 return V_008F14_IMG_DATA_FORMAT_32;
1344 case 2:
1345 return V_008F14_IMG_DATA_FORMAT_32_32;
1346 #if 0 /* Not supported for render targets */
1347 case 3:
1348 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1349 #endif
1350 case 4:
1351 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1352 }
1353 }
1354
1355 out_unknown:
1356 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1357 return ~0;
1358 }
1359
1360 static unsigned si_tex_wrap(unsigned wrap)
1361 {
1362 switch (wrap) {
1363 default:
1364 case PIPE_TEX_WRAP_REPEAT:
1365 return V_008F30_SQ_TEX_WRAP;
1366 case PIPE_TEX_WRAP_CLAMP:
1367 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1368 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1369 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1370 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1371 return V_008F30_SQ_TEX_CLAMP_BORDER;
1372 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1373 return V_008F30_SQ_TEX_MIRROR;
1374 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1375 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1376 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1377 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1378 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1379 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1380 }
1381 }
1382
1383 static unsigned si_tex_filter(unsigned filter)
1384 {
1385 switch (filter) {
1386 default:
1387 case PIPE_TEX_FILTER_NEAREST:
1388 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1389 case PIPE_TEX_FILTER_LINEAR:
1390 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1391 }
1392 }
1393
1394 static unsigned si_tex_mipfilter(unsigned filter)
1395 {
1396 switch (filter) {
1397 case PIPE_TEX_MIPFILTER_NEAREST:
1398 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1399 case PIPE_TEX_MIPFILTER_LINEAR:
1400 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1401 default:
1402 case PIPE_TEX_MIPFILTER_NONE:
1403 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1404 }
1405 }
1406
1407 static unsigned si_tex_compare(unsigned compare)
1408 {
1409 switch (compare) {
1410 default:
1411 case PIPE_FUNC_NEVER:
1412 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1413 case PIPE_FUNC_LESS:
1414 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1415 case PIPE_FUNC_EQUAL:
1416 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1417 case PIPE_FUNC_LEQUAL:
1418 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1419 case PIPE_FUNC_GREATER:
1420 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1421 case PIPE_FUNC_NOTEQUAL:
1422 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1423 case PIPE_FUNC_GEQUAL:
1424 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1425 case PIPE_FUNC_ALWAYS:
1426 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1427 }
1428 }
1429
1430 static unsigned si_tex_dim(unsigned dim)
1431 {
1432 switch (dim) {
1433 default:
1434 case PIPE_TEXTURE_1D:
1435 return V_008F1C_SQ_RSRC_IMG_1D;
1436 case PIPE_TEXTURE_1D_ARRAY:
1437 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1438 case PIPE_TEXTURE_2D:
1439 case PIPE_TEXTURE_RECT:
1440 return V_008F1C_SQ_RSRC_IMG_2D;
1441 case PIPE_TEXTURE_2D_ARRAY:
1442 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1443 case PIPE_TEXTURE_3D:
1444 return V_008F1C_SQ_RSRC_IMG_3D;
1445 case PIPE_TEXTURE_CUBE:
1446 return V_008F1C_SQ_RSRC_IMG_CUBE;
1447 }
1448 }
1449
1450 /*
1451 * Format support testing
1452 */
1453
1454 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1455 {
1456 return si_translate_texformat(screen, format, util_format_description(format),
1457 util_format_get_first_non_void_channel(format)) != ~0U;
1458 }
1459
1460 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1461 enum pipe_format format,
1462 const struct util_format_description *desc,
1463 int first_non_void)
1464 {
1465 unsigned type = desc->channel[first_non_void].type;
1466 int i;
1467
1468 if (type == UTIL_FORMAT_TYPE_FIXED)
1469 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1470
1471 /* See whether the components are of the same size. */
1472 for (i = 0; i < desc->nr_channels; i++) {
1473 if (desc->channel[first_non_void].size != desc->channel[i].size)
1474 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1475 }
1476
1477 switch (desc->channel[first_non_void].size) {
1478 case 8:
1479 switch (desc->nr_channels) {
1480 case 1:
1481 return V_008F0C_BUF_DATA_FORMAT_8;
1482 case 2:
1483 return V_008F0C_BUF_DATA_FORMAT_8_8;
1484 case 3:
1485 case 4:
1486 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1487 }
1488 break;
1489 case 16:
1490 switch (desc->nr_channels) {
1491 case 1:
1492 return V_008F0C_BUF_DATA_FORMAT_16;
1493 case 2:
1494 return V_008F0C_BUF_DATA_FORMAT_16_16;
1495 case 3:
1496 case 4:
1497 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1498 }
1499 break;
1500 case 32:
1501 if (type != UTIL_FORMAT_TYPE_FLOAT)
1502 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1503
1504 switch (desc->nr_channels) {
1505 case 1:
1506 return V_008F0C_BUF_DATA_FORMAT_32;
1507 case 2:
1508 return V_008F0C_BUF_DATA_FORMAT_32_32;
1509 case 3:
1510 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1511 case 4:
1512 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1513 }
1514 break;
1515 }
1516
1517 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1518 }
1519
1520 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1521 {
1522 const struct util_format_description *desc;
1523 int first_non_void;
1524 unsigned data_format;
1525
1526 desc = util_format_description(format);
1527 first_non_void = util_format_get_first_non_void_channel(format);
1528 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1529 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1530 }
1531
1532 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1533 {
1534 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1535 si_translate_colorswap(format) != ~0U;
1536 }
1537
1538 static bool si_is_zs_format_supported(enum pipe_format format)
1539 {
1540 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1541 }
1542
1543 boolean si_is_format_supported(struct pipe_screen *screen,
1544 enum pipe_format format,
1545 enum pipe_texture_target target,
1546 unsigned sample_count,
1547 unsigned usage)
1548 {
1549 unsigned retval = 0;
1550
1551 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1552 R600_ERR("r600: unsupported texture type %d\n", target);
1553 return FALSE;
1554 }
1555
1556 if (!util_format_is_supported(format, usage))
1557 return FALSE;
1558
1559 /* Multisample */
1560 if (sample_count > 1)
1561 return FALSE;
1562
1563 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1564 si_is_sampler_format_supported(screen, format)) {
1565 retval |= PIPE_BIND_SAMPLER_VIEW;
1566 }
1567
1568 if ((usage & (PIPE_BIND_RENDER_TARGET |
1569 PIPE_BIND_DISPLAY_TARGET |
1570 PIPE_BIND_SCANOUT |
1571 PIPE_BIND_SHARED)) &&
1572 si_is_colorbuffer_format_supported(format)) {
1573 retval |= usage &
1574 (PIPE_BIND_RENDER_TARGET |
1575 PIPE_BIND_DISPLAY_TARGET |
1576 PIPE_BIND_SCANOUT |
1577 PIPE_BIND_SHARED);
1578 }
1579
1580 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1581 si_is_zs_format_supported(format)) {
1582 retval |= PIPE_BIND_DEPTH_STENCIL;
1583 }
1584
1585 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1586 si_is_vertex_format_supported(screen, format)) {
1587 retval |= PIPE_BIND_VERTEX_BUFFER;
1588 }
1589
1590 if (usage & PIPE_BIND_TRANSFER_READ)
1591 retval |= PIPE_BIND_TRANSFER_READ;
1592 if (usage & PIPE_BIND_TRANSFER_WRITE)
1593 retval |= PIPE_BIND_TRANSFER_WRITE;
1594
1595 return retval == usage;
1596 }
1597
1598 static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil)
1599 {
1600 unsigned tile_mode_index = 0;
1601
1602 if (stencil) {
1603 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1604 } else {
1605 tile_mode_index = rtex->surface.tiling_index[level];
1606 }
1607 return tile_mode_index;
1608 }
1609
1610 /*
1611 * framebuffer handling
1612 */
1613
1614 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1615 const struct pipe_framebuffer_state *state, int cb)
1616 {
1617 struct r600_resource_texture *rtex;
1618 struct r600_surface *surf;
1619 unsigned level = state->cbufs[cb]->u.tex.level;
1620 unsigned pitch, slice;
1621 unsigned color_info, color_attrib;
1622 unsigned tile_mode_index;
1623 unsigned format, swap, ntype, endian;
1624 uint64_t offset;
1625 const struct util_format_description *desc;
1626 int i;
1627 unsigned blend_clamp = 0, blend_bypass = 0;
1628 unsigned max_comp_size;
1629
1630 surf = (struct r600_surface *)state->cbufs[cb];
1631 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1632
1633 offset = rtex->surface.level[level].offset;
1634 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1635 offset += rtex->surface.level[level].slice_size *
1636 state->cbufs[cb]->u.tex.first_layer;
1637 }
1638 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1639 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1640 if (slice) {
1641 slice = slice - 1;
1642 }
1643
1644 tile_mode_index = si_tile_mode_index(rtex, level, false);
1645
1646 desc = util_format_description(surf->base.format);
1647 for (i = 0; i < 4; i++) {
1648 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1649 break;
1650 }
1651 }
1652 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1653 ntype = V_028C70_NUMBER_FLOAT;
1654 } else {
1655 ntype = V_028C70_NUMBER_UNORM;
1656 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1657 ntype = V_028C70_NUMBER_SRGB;
1658 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1659 if (desc->channel[i].pure_integer) {
1660 ntype = V_028C70_NUMBER_SINT;
1661 } else {
1662 assert(desc->channel[i].normalized);
1663 ntype = V_028C70_NUMBER_SNORM;
1664 }
1665 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1666 if (desc->channel[i].pure_integer) {
1667 ntype = V_028C70_NUMBER_UINT;
1668 } else {
1669 assert(desc->channel[i].normalized);
1670 ntype = V_028C70_NUMBER_UNORM;
1671 }
1672 }
1673 }
1674
1675 format = si_translate_colorformat(surf->base.format);
1676 if (format == V_028C70_COLOR_INVALID) {
1677 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1678 }
1679 assert(format != V_028C70_COLOR_INVALID);
1680 swap = si_translate_colorswap(surf->base.format);
1681 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1682 endian = V_028C70_ENDIAN_NONE;
1683 } else {
1684 endian = si_colorformat_endian_swap(format);
1685 }
1686
1687 /* blend clamp should be set for all NORM/SRGB types */
1688 if (ntype == V_028C70_NUMBER_UNORM ||
1689 ntype == V_028C70_NUMBER_SNORM ||
1690 ntype == V_028C70_NUMBER_SRGB)
1691 blend_clamp = 1;
1692
1693 /* set blend bypass according to docs if SINT/UINT or
1694 8/24 COLOR variants */
1695 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1696 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1697 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1698 blend_clamp = 0;
1699 blend_bypass = 1;
1700 }
1701
1702 color_info = S_028C70_FORMAT(format) |
1703 S_028C70_COMP_SWAP(swap) |
1704 S_028C70_BLEND_CLAMP(blend_clamp) |
1705 S_028C70_BLEND_BYPASS(blend_bypass) |
1706 S_028C70_NUMBER_TYPE(ntype) |
1707 S_028C70_ENDIAN(endian);
1708
1709 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1710 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1711
1712 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1713 offset >>= 8;
1714
1715 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1716 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1717 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1718 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1719 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1720
1721 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1722 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1723 } else {
1724 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1725 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1726 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1727 }
1728 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1729 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1730
1731 /* set CB_COLOR1_INFO for possible dual-src blending */
1732 if (state->nr_cbufs == 1) {
1733 assert(cb == 0);
1734 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1735 }
1736
1737 /* Determine pixel shader export format */
1738 max_comp_size = si_colorformat_max_comp_size(format);
1739 if (ntype == V_028C70_NUMBER_SRGB ||
1740 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1741 max_comp_size <= 10) ||
1742 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1743 rctx->export_16bpc |= 1 << cb;
1744 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1745 if (state->nr_cbufs == 1)
1746 rctx->export_16bpc |= 1 << 1;
1747 }
1748 }
1749
1750 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1751 const struct pipe_framebuffer_state *state)
1752 {
1753 struct r600_resource_texture *rtex;
1754 struct r600_surface *surf;
1755 unsigned level, pitch, slice, format, tile_mode_index;
1756 uint32_t z_info, s_info;
1757 uint64_t z_offs, s_offs;
1758
1759 if (state->zsbuf == NULL) {
1760 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1761 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1762 return;
1763 }
1764
1765 surf = (struct r600_surface *)state->zsbuf;
1766 level = surf->base.u.tex.level;
1767 rtex = (struct r600_resource_texture*)surf->base.texture;
1768
1769 format = si_translate_dbformat(rtex->real_format);
1770
1771 if (format == V_028040_Z_INVALID) {
1772 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
1773 }
1774 assert(format != V_028040_Z_INVALID);
1775
1776 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1777 z_offs += rtex->surface.level[level].offset;
1778 s_offs += rtex->surface.stencil_level[level].offset;
1779
1780 z_offs >>= 8;
1781 s_offs >>= 8;
1782
1783 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1784 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1785 if (slice) {
1786 slice = slice - 1;
1787 }
1788
1789 z_info = S_028040_FORMAT(format);
1790 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1791 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1792 else
1793 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1794
1795 tile_mode_index = si_tile_mode_index(rtex, level, false);
1796 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1797 tile_mode_index = si_tile_mode_index(rtex, level, true);
1798 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1799
1800 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1801 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1802 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1803
1804 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1));
1805 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1806 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1807
1808 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1809 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1810 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1811 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1812 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1813
1814 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1815 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1816 }
1817
1818 static void si_set_framebuffer_state(struct pipe_context *ctx,
1819 const struct pipe_framebuffer_state *state)
1820 {
1821 struct r600_context *rctx = (struct r600_context *)ctx;
1822 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1823 uint32_t tl, br;
1824 int tl_x, tl_y, br_x, br_y;
1825
1826 if (pm4 == NULL)
1827 return;
1828
1829 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1830
1831 if (state->zsbuf)
1832 si_pm4_inval_zsbuf_cache(pm4);
1833
1834 util_copy_framebuffer_state(&rctx->framebuffer, state);
1835
1836 /* build states */
1837 rctx->export_16bpc = 0;
1838 for (int i = 0; i < state->nr_cbufs; i++) {
1839 si_cb(rctx, pm4, state, i);
1840 }
1841 assert(!(rctx->export_16bpc & ~0xff));
1842 si_db(rctx, pm4, state);
1843
1844 tl_x = 0;
1845 tl_y = 0;
1846 br_x = state->width;
1847 br_y = state->height;
1848
1849 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1850 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1851
1852 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1853 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1854 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1855 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1856 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1857 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1858 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1859 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1860 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1861 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1862 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1863
1864 si_pm4_set_state(rctx, framebuffer, pm4);
1865 si_update_fb_rs_state(rctx);
1866 si_update_fb_blend_state(rctx);
1867 }
1868
1869 /*
1870 * shaders
1871 */
1872
1873 /* Compute the key for the hw shader variant */
1874 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
1875 struct si_pipe_shader_selector *sel,
1876 union si_shader_key *key)
1877 {
1878 struct r600_context *rctx = (struct r600_context *)ctx;
1879 memset(key, 0, sizeof(*key));
1880
1881 if (sel->type == PIPE_SHADER_VERTEX) {
1882 unsigned i;
1883 if (!rctx->vertex_elements)
1884 return;
1885
1886 for (i = 0; i < rctx->vertex_elements->count; ++i)
1887 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
1888
1889 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
1890 if (sel->fs_write_all)
1891 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
1892 key->ps.export_16bpc = rctx->export_16bpc;
1893 if (rctx->queued.named.rasterizer) {
1894 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
1895 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
1896 }
1897 if (rctx->queued.named.dsa) {
1898 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
1899 key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
1900 } else {
1901 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
1902 }
1903 }
1904 }
1905
1906 /* Select the hw shader variant depending on the current state.
1907 * (*dirty) is set to 1 if current variant was changed */
1908 int si_shader_select(struct pipe_context *ctx,
1909 struct si_pipe_shader_selector *sel,
1910 unsigned *dirty)
1911 {
1912 union si_shader_key key;
1913 struct si_pipe_shader * shader = NULL;
1914 int r;
1915
1916 si_shader_selector_key(ctx, sel, &key);
1917
1918 /* Check if we don't need to change anything.
1919 * This path is also used for most shaders that don't need multiple
1920 * variants, it will cost just a computation of the key and this
1921 * test. */
1922 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
1923 return 0;
1924 }
1925
1926 /* lookup if we have other variants in the list */
1927 if (sel->num_shaders > 1) {
1928 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1929
1930 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
1931 p = c;
1932 c = c->next_variant;
1933 }
1934
1935 if (c) {
1936 p->next_variant = c->next_variant;
1937 shader = c;
1938 }
1939 }
1940
1941 if (unlikely(!shader)) {
1942 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1943 shader->selector = sel;
1944 shader->key = key;
1945
1946 r = si_pipe_shader_create(ctx, shader);
1947 if (unlikely(r)) {
1948 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1949 sel->type, r);
1950 sel->current = NULL;
1951 FREE(shader);
1952 return r;
1953 }
1954
1955 /* We don't know the value of fs_write_all property until we built
1956 * at least one variant, so we may need to recompute the key (include
1957 * rctx->framebuffer.nr_cbufs) after building first variant. */
1958 if (sel->type == PIPE_SHADER_FRAGMENT &&
1959 sel->num_shaders == 0 &&
1960 shader->shader.fs_write_all) {
1961 sel->fs_write_all = 1;
1962 si_shader_selector_key(ctx, sel, &shader->key);
1963 }
1964
1965 sel->num_shaders++;
1966 }
1967
1968 if (dirty)
1969 *dirty = 1;
1970
1971 shader->next_variant = sel->current;
1972 sel->current = shader;
1973
1974 return 0;
1975 }
1976
1977 static void *si_create_shader_state(struct pipe_context *ctx,
1978 const struct pipe_shader_state *state,
1979 unsigned pipe_shader_type)
1980 {
1981 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1982 int r;
1983
1984 sel->type = pipe_shader_type;
1985 sel->tokens = tgsi_dup_tokens(state->tokens);
1986 sel->so = state->stream_output;
1987
1988 r = si_shader_select(ctx, sel, NULL);
1989 if (r) {
1990 free(sel);
1991 return NULL;
1992 }
1993
1994 return sel;
1995 }
1996
1997 static void *si_create_fs_state(struct pipe_context *ctx,
1998 const struct pipe_shader_state *state)
1999 {
2000 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2001 }
2002
2003 static void *si_create_vs_state(struct pipe_context *ctx,
2004 const struct pipe_shader_state *state)
2005 {
2006 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2007 }
2008
2009 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2010 {
2011 struct r600_context *rctx = (struct r600_context *)ctx;
2012 struct si_pipe_shader_selector *sel = state;
2013
2014 if (rctx->vs_shader == sel)
2015 return;
2016
2017 rctx->vs_shader = sel;
2018
2019 if (sel && sel->current)
2020 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2021 else
2022 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2023 }
2024
2025 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2026 {
2027 struct r600_context *rctx = (struct r600_context *)ctx;
2028 struct si_pipe_shader_selector *sel = state;
2029
2030 if (rctx->ps_shader == sel)
2031 return;
2032
2033 rctx->ps_shader = sel;
2034
2035 if (sel && sel->current)
2036 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2037 else
2038 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2039 }
2040
2041 static void si_delete_shader_selector(struct pipe_context *ctx,
2042 struct si_pipe_shader_selector *sel)
2043 {
2044 struct r600_context *rctx = (struct r600_context *)ctx;
2045 struct si_pipe_shader *p = sel->current, *c;
2046
2047 while (p) {
2048 c = p->next_variant;
2049 si_pm4_delete_state(rctx, vs, p->pm4);
2050 si_pipe_shader_destroy(ctx, p);
2051 free(p);
2052 p = c;
2053 }
2054
2055 free(sel->tokens);
2056 free(sel);
2057 }
2058
2059 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2060 {
2061 struct r600_context *rctx = (struct r600_context *)ctx;
2062 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2063
2064 if (rctx->vs_shader == sel) {
2065 rctx->vs_shader = NULL;
2066 }
2067
2068 si_delete_shader_selector(ctx, sel);
2069 }
2070
2071 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2072 {
2073 struct r600_context *rctx = (struct r600_context *)ctx;
2074 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2075
2076 if (rctx->ps_shader == sel) {
2077 rctx->ps_shader = NULL;
2078 }
2079
2080 si_delete_shader_selector(ctx, sel);
2081 }
2082
2083 /*
2084 * Samplers
2085 */
2086
2087 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2088 struct pipe_resource *texture,
2089 const struct pipe_sampler_view *state)
2090 {
2091 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2092 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2093 const struct util_format_description *desc;
2094 unsigned format, num_format;
2095 uint32_t pitch = 0;
2096 unsigned char state_swizzle[4], swizzle[4];
2097 unsigned height, depth, width;
2098 enum pipe_format pipe_format = state->format;
2099 struct radeon_surface_level *surflevel;
2100 int first_non_void;
2101 uint64_t va;
2102
2103 if (view == NULL)
2104 return NULL;
2105
2106 /* initialize base object */
2107 view->base = *state;
2108 view->base.texture = NULL;
2109 pipe_reference(NULL, &texture->reference);
2110 view->base.texture = texture;
2111 view->base.reference.count = 1;
2112 view->base.context = ctx;
2113
2114 state_swizzle[0] = state->swizzle_r;
2115 state_swizzle[1] = state->swizzle_g;
2116 state_swizzle[2] = state->swizzle_b;
2117 state_swizzle[3] = state->swizzle_a;
2118
2119 surflevel = tmp->surface.level;
2120
2121 /* Texturing with separate depth and stencil. */
2122 if (tmp->is_depth && !tmp->is_flushing_texture) {
2123 switch (pipe_format) {
2124 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2125 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2126 break;
2127 case PIPE_FORMAT_X8Z24_UNORM:
2128 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2129 /* Z24 is always stored like this. */
2130 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2131 break;
2132 case PIPE_FORMAT_X24S8_UINT:
2133 case PIPE_FORMAT_S8X24_UINT:
2134 case PIPE_FORMAT_X32_S8X24_UINT:
2135 pipe_format = PIPE_FORMAT_S8_UINT;
2136 surflevel = tmp->surface.stencil_level;
2137 break;
2138 default:;
2139 }
2140 }
2141
2142 desc = util_format_description(pipe_format);
2143
2144 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2145 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2146 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2147
2148 switch (pipe_format) {
2149 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2150 case PIPE_FORMAT_X24S8_UINT:
2151 case PIPE_FORMAT_X32_S8X24_UINT:
2152 case PIPE_FORMAT_X8Z24_UNORM:
2153 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2154 break;
2155 default:
2156 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2157 }
2158 } else {
2159 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2160 }
2161
2162 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2163
2164 switch (pipe_format) {
2165 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2166 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2167 break;
2168 default:
2169 if (first_non_void < 0) {
2170 if (util_format_is_compressed(pipe_format)) {
2171 switch (pipe_format) {
2172 case PIPE_FORMAT_DXT1_SRGB:
2173 case PIPE_FORMAT_DXT1_SRGBA:
2174 case PIPE_FORMAT_DXT3_SRGBA:
2175 case PIPE_FORMAT_DXT5_SRGBA:
2176 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2177 break;
2178 case PIPE_FORMAT_RGTC1_SNORM:
2179 case PIPE_FORMAT_LATC1_SNORM:
2180 case PIPE_FORMAT_RGTC2_SNORM:
2181 case PIPE_FORMAT_LATC2_SNORM:
2182 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2183 break;
2184 default:
2185 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2186 break;
2187 }
2188 } else {
2189 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2190 }
2191 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2192 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2193 } else {
2194 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2195
2196 switch (desc->channel[first_non_void].type) {
2197 case UTIL_FORMAT_TYPE_FLOAT:
2198 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2199 break;
2200 case UTIL_FORMAT_TYPE_SIGNED:
2201 if (desc->channel[first_non_void].normalized)
2202 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2203 else if (desc->channel[first_non_void].pure_integer)
2204 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2205 else
2206 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2207 break;
2208 case UTIL_FORMAT_TYPE_UNSIGNED:
2209 if (desc->channel[first_non_void].normalized)
2210 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2211 else if (desc->channel[first_non_void].pure_integer)
2212 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2213 else
2214 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2215 }
2216 }
2217 }
2218
2219 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2220 if (format == ~0) {
2221 format = 0;
2222 }
2223
2224 view->resource = &tmp->resource;
2225
2226 /* not supported any more */
2227 //endian = si_colorformat_endian_swap(format);
2228
2229 width = surflevel[0].npix_x;
2230 height = surflevel[0].npix_y;
2231 depth = surflevel[0].npix_z;
2232 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2233
2234 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2235 height = 1;
2236 depth = texture->array_size;
2237 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2238 depth = texture->array_size;
2239 }
2240
2241 va = r600_resource_va(ctx->screen, texture);
2242 va += surflevel[0].offset;
2243 view->state[0] = va >> 8;
2244 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2245 S_008F14_DATA_FORMAT(format) |
2246 S_008F14_NUM_FORMAT(num_format));
2247 view->state[2] = (S_008F18_WIDTH(width - 1) |
2248 S_008F18_HEIGHT(height - 1));
2249 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2250 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2251 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2252 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2253 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2254 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2255 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2256 S_008F1C_POW2_PAD(texture->last_level > 0) |
2257 S_008F1C_TYPE(si_tex_dim(texture->target)));
2258 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2259 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2260 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2261 view->state[6] = 0;
2262 view->state[7] = 0;
2263
2264 return &view->base;
2265 }
2266
2267 static void si_sampler_view_destroy(struct pipe_context *ctx,
2268 struct pipe_sampler_view *state)
2269 {
2270 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2271
2272 pipe_resource_reference(&state->texture, NULL);
2273 FREE(resource);
2274 }
2275
2276 static void *si_create_sampler_state(struct pipe_context *ctx,
2277 const struct pipe_sampler_state *state)
2278 {
2279 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2280 union util_color uc;
2281 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2282 unsigned border_color_type;
2283
2284 if (rstate == NULL) {
2285 return NULL;
2286 }
2287
2288 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2289 switch (uc.ui) {
2290 case 0x000000FF:
2291 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2292 break;
2293 case 0x00000000:
2294 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2295 break;
2296 case 0xFFFFFFFF:
2297 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2298 break;
2299 default: /* Use border color pointer */
2300 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2301 }
2302
2303 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2304 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2305 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2306 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2307 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2308 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2309 aniso_flag_offset << 16 | /* XXX */
2310 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2311 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2312 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2313 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2314 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2315 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2316 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2317 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2318
2319 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2320 memcpy(rstate->border_color, state->border_color.f,
2321 sizeof(rstate->border_color));
2322 }
2323
2324 return rstate;
2325 }
2326
2327 static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
2328 unsigned count,
2329 struct pipe_sampler_view **views,
2330 struct r600_textures_info *samplers,
2331 unsigned user_data_reg)
2332 {
2333 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2334 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2335 int i, j;
2336
2337 if (!count)
2338 goto out;
2339
2340 si_pm4_inval_texture_cache(pm4);
2341
2342 si_pm4_sh_data_begin(pm4);
2343 for (i = 0; i < count; i++) {
2344 pipe_sampler_view_reference(
2345 (struct pipe_sampler_view **)&samplers->views[i],
2346 views[i]);
2347
2348 if (views[i]) {
2349 struct r600_resource_texture *rtex =
2350 (struct r600_resource_texture*)views[i]->texture;
2351
2352 if (rtex->is_depth && !rtex->is_flushing_texture) {
2353 samplers->depth_texture_mask |= 1 << i;
2354 } else {
2355 samplers->depth_texture_mask &= ~(1 << i);
2356 }
2357
2358 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
2359 } else {
2360 samplers->depth_texture_mask &= ~(1 << i);
2361 }
2362
2363 for (j = 0; j < Elements(resource[i]->state); ++j) {
2364 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2365 }
2366 }
2367
2368 for (i = count; i < NUM_TEX_UNITS; i++) {
2369 if (samplers->views[i])
2370 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
2371 }
2372
2373 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
2374
2375 out:
2376 rctx->ps_samplers.n_views = count;
2377 return pm4;
2378 }
2379
2380 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2381 struct pipe_sampler_view **views)
2382 {
2383 struct r600_context *rctx = (struct r600_context *)ctx;
2384 struct si_pm4_state *pm4;
2385
2386 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
2387 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2388 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2389 }
2390
2391 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2392 struct pipe_sampler_view **views)
2393 {
2394 struct r600_context *rctx = (struct r600_context *)ctx;
2395 struct si_pm4_state *pm4;
2396
2397 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
2398 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2399 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2400 }
2401
2402 static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
2403 void **states,
2404 struct r600_textures_info *samplers,
2405 unsigned user_data_reg)
2406 {
2407 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2408 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2409 uint32_t *border_color_table = NULL;
2410 int i, j;
2411
2412 if (!count)
2413 goto out;
2414
2415 si_pm4_inval_texture_cache(pm4);
2416
2417 si_pm4_sh_data_begin(pm4);
2418 for (i = 0; i < count; i++) {
2419 if (rstates[i] &&
2420 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2421 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2422 if (!rctx->border_color_table ||
2423 ((rctx->border_color_offset + count - i) &
2424 C_008F3C_BORDER_COLOR_PTR)) {
2425 si_resource_reference(&rctx->border_color_table, NULL);
2426 rctx->border_color_offset = 0;
2427
2428 rctx->border_color_table =
2429 si_resource_create_custom(&rctx->screen->screen,
2430 PIPE_USAGE_STAGING,
2431 4096 * 4 * 4);
2432 }
2433
2434 if (!border_color_table) {
2435 border_color_table =
2436 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2437 rctx->cs,
2438 PIPE_TRANSFER_WRITE |
2439 PIPE_TRANSFER_UNSYNCHRONIZED);
2440 }
2441
2442 for (j = 0; j < 4; j++) {
2443 union fi border_color;
2444
2445 border_color.f = rstates[i]->border_color[j];
2446 border_color_table[4 * rctx->border_color_offset + j] =
2447 util_le32_to_cpu(border_color.i);
2448 }
2449
2450 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2451 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2452 }
2453
2454 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2455 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2456 }
2457 }
2458 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2459
2460 if (border_color_table) {
2461 uint64_t va_offset =
2462 r600_resource_va(&rctx->screen->screen,
2463 (void*)rctx->border_color_table);
2464
2465 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2466 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2467 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2468 }
2469
2470 memcpy(samplers->samplers, states, sizeof(void*) * count);
2471
2472 out:
2473 samplers->n_samplers = count;
2474 return pm4;
2475 }
2476
2477 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2478 {
2479 struct r600_context *rctx = (struct r600_context *)ctx;
2480 struct si_pm4_state *pm4;
2481
2482 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
2483 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2484 si_pm4_set_state(rctx, vs_sampler, pm4);
2485 }
2486
2487 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2488 {
2489 struct r600_context *rctx = (struct r600_context *)ctx;
2490 struct si_pm4_state *pm4;
2491
2492 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
2493 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2494 si_pm4_set_state(rctx, ps_sampler, pm4);
2495 }
2496
2497 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2498 {
2499 }
2500
2501 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2502 {
2503 free(state);
2504 }
2505
2506 /*
2507 * Constants
2508 */
2509 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2510 struct pipe_constant_buffer *input)
2511 {
2512 struct r600_context *rctx = (struct r600_context *)ctx;
2513 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2514 struct pipe_constant_buffer *cb;
2515 const uint8_t *ptr;
2516
2517 /* Note that the state tracker can unbind constant buffers by
2518 * passing NULL here.
2519 */
2520 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
2521 state->enabled_mask &= ~(1 << index);
2522 state->dirty_mask &= ~(1 << index);
2523 pipe_resource_reference(&state->cb[index].buffer, NULL);
2524 return;
2525 }
2526
2527 cb = &state->cb[index];
2528 cb->buffer_size = input->buffer_size;
2529
2530 ptr = input->user_buffer;
2531
2532 if (ptr) {
2533 /* Upload the user buffer. */
2534 if (R600_BIG_ENDIAN) {
2535 uint32_t *tmpPtr;
2536 unsigned i, size = input->buffer_size;
2537
2538 if (!(tmpPtr = malloc(size))) {
2539 R600_ERR("Failed to allocate BE swap buffer.\n");
2540 return;
2541 }
2542
2543 for (i = 0; i < size / 4; ++i) {
2544 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
2545 }
2546
2547 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
2548 free(tmpPtr);
2549 } else {
2550 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
2551 }
2552 } else {
2553 /* Setup the hw buffer. */
2554 cb->buffer_offset = input->buffer_offset;
2555 pipe_resource_reference(&cb->buffer, input->buffer);
2556 }
2557
2558 state->enabled_mask |= 1 << index;
2559 state->dirty_mask |= 1 << index;
2560 }
2561
2562 /*
2563 * Vertex elements & buffers
2564 */
2565
2566 static void *si_create_vertex_elements(struct pipe_context *ctx,
2567 unsigned count,
2568 const struct pipe_vertex_element *elements)
2569 {
2570 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2571 int i;
2572
2573 assert(count < PIPE_MAX_ATTRIBS);
2574 if (!v)
2575 return NULL;
2576
2577 v->count = count;
2578 for (i = 0; i < count; ++i) {
2579 const struct util_format_description *desc;
2580 unsigned data_format, num_format;
2581 int first_non_void;
2582
2583 desc = util_format_description(elements[i].src_format);
2584 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2585 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2586 desc, first_non_void);
2587
2588 switch (desc->channel[first_non_void].type) {
2589 case UTIL_FORMAT_TYPE_FIXED:
2590 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2591 break;
2592 case UTIL_FORMAT_TYPE_SIGNED:
2593 if (desc->channel[first_non_void].normalized)
2594 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2595 else if (desc->channel[first_non_void].pure_integer)
2596 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
2597 else
2598 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
2599 break;
2600 case UTIL_FORMAT_TYPE_UNSIGNED:
2601 if (desc->channel[first_non_void].normalized)
2602 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2603 else if (desc->channel[first_non_void].pure_integer)
2604 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
2605 else
2606 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
2607 break;
2608 case UTIL_FORMAT_TYPE_FLOAT:
2609 default:
2610 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2611 }
2612
2613 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2614 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2615 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2616 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2617 S_008F0C_NUM_FORMAT(num_format) |
2618 S_008F0C_DATA_FORMAT(data_format);
2619 }
2620 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2621
2622 return v;
2623 }
2624
2625 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2626 {
2627 struct r600_context *rctx = (struct r600_context *)ctx;
2628 struct si_vertex_element *v = (struct si_vertex_element*)state;
2629
2630 rctx->vertex_elements = v;
2631 }
2632
2633 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2634 {
2635 struct r600_context *rctx = (struct r600_context *)ctx;
2636
2637 if (rctx->vertex_elements == state)
2638 rctx->vertex_elements = NULL;
2639 FREE(state);
2640 }
2641
2642 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2643 const struct pipe_vertex_buffer *buffers)
2644 {
2645 struct r600_context *rctx = (struct r600_context *)ctx;
2646
2647 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2648 }
2649
2650 static void si_set_index_buffer(struct pipe_context *ctx,
2651 const struct pipe_index_buffer *ib)
2652 {
2653 struct r600_context *rctx = (struct r600_context *)ctx;
2654
2655 if (ib) {
2656 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2657 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2658 } else {
2659 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2660 }
2661 }
2662
2663 /*
2664 * Misc
2665 */
2666 static void si_set_polygon_stipple(struct pipe_context *ctx,
2667 const struct pipe_poly_stipple *state)
2668 {
2669 }
2670
2671 static void si_texture_barrier(struct pipe_context *ctx)
2672 {
2673 struct r600_context *rctx = (struct r600_context *)ctx;
2674 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2675
2676 si_pm4_inval_texture_cache(pm4);
2677 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2678 si_pm4_set_state(rctx, texture_barrier, pm4);
2679 }
2680
2681 void si_init_state_functions(struct r600_context *rctx)
2682 {
2683 rctx->context.create_blend_state = si_create_blend_state;
2684 rctx->context.bind_blend_state = si_bind_blend_state;
2685 rctx->context.delete_blend_state = si_delete_blend_state;
2686 rctx->context.set_blend_color = si_set_blend_color;
2687
2688 rctx->context.create_rasterizer_state = si_create_rs_state;
2689 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2690 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2691
2692 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2693 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2694 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2695 rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
2696 rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
2697 rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
2698 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
2699
2700 rctx->context.set_clip_state = si_set_clip_state;
2701 rctx->context.set_scissor_state = si_set_scissor_state;
2702 rctx->context.set_viewport_state = si_set_viewport_state;
2703 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2704
2705 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2706
2707 rctx->context.create_vs_state = si_create_vs_state;
2708 rctx->context.create_fs_state = si_create_fs_state;
2709 rctx->context.bind_vs_state = si_bind_vs_shader;
2710 rctx->context.bind_fs_state = si_bind_ps_shader;
2711 rctx->context.delete_vs_state = si_delete_vs_shader;
2712 rctx->context.delete_fs_state = si_delete_ps_shader;
2713
2714 rctx->context.create_sampler_state = si_create_sampler_state;
2715 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2716 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2717 rctx->context.delete_sampler_state = si_delete_sampler_state;
2718
2719 rctx->context.create_sampler_view = si_create_sampler_view;
2720 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2721 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2722 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2723
2724 rctx->context.set_sample_mask = si_set_sample_mask;
2725
2726 rctx->context.set_constant_buffer = si_set_constant_buffer;
2727
2728 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2729 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2730 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2731 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2732 rctx->context.set_index_buffer = si_set_index_buffer;
2733
2734 rctx->context.create_stream_output_target = si_create_so_target;
2735 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2736 rctx->context.set_stream_output_targets = si_set_so_targets;
2737
2738 rctx->context.texture_barrier = si_texture_barrier;
2739 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2740
2741 rctx->context.draw_vbo = si_draw_vbo;
2742 }
2743
2744 void si_init_config(struct r600_context *rctx)
2745 {
2746 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2747
2748 si_cmd_context_control(pm4);
2749
2750 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2751
2752 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2753 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2754 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2755 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2756 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2757 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2758 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2759 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2760 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2761 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2762 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2763 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2764 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2765 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2766 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2767 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2768 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2769 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2770 S_028AA8_SWITCH_ON_EOP(1) |
2771 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2772 S_028AA8_PRIMGROUP_SIZE(63));
2773 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2774 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2775 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2776 S_008A14_CLIP_VTX_REORDER_ENA(1));
2777
2778 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2779 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2780 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2781
2782 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2783
2784 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2785
2786 switch (rctx->screen->family) {
2787 case CHIP_TAHITI:
2788 case CHIP_PITCAIRN:
2789 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
2790 break;
2791 case CHIP_VERDE:
2792 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
2793 break;
2794 case CHIP_OLAND:
2795 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
2796 break;
2797 case CHIP_HAINAN:
2798 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
2799 break;
2800 default:
2801 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
2802 break;
2803 }
2804
2805 si_pm4_set_state(rctx, init, pm4);
2806 }