2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 unsigned img_format
:9;
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
46 #include "gfx10_format_table.h"
48 static unsigned si_map_swizzle(unsigned swizzle
)
52 return V_008F0C_SQ_SEL_Y
;
54 return V_008F0C_SQ_SEL_Z
;
56 return V_008F0C_SQ_SEL_W
;
58 return V_008F0C_SQ_SEL_0
;
60 return V_008F0C_SQ_SEL_1
;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X
;
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x
)
70 x
>= 4096 ? 0xffff : x
* 16;
74 * Inferred framebuffer and blender state.
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
79 static void si_emit_cb_render_state(struct si_context
*sctx
)
81 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
82 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
89 cb_target_mask
&= blend
->cb_target_mask
;
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
97 if (blend
&& blend
->dual_src_blend
&&
98 sctx
->ps_shader
.cso
&&
99 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
105 if (sctx
->screen
->dpbb_allowed
&&
106 sctx
->last_cb_target_mask
!= cb_target_mask
) {
107 sctx
->last_cb_target_mask
= cb_target_mask
;
109 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
110 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
113 unsigned initial_cdw
= cs
->current
.cdw
;
114 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
115 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
117 if (sctx
->chip_class
>= GFX8
) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
122 bool oc_disable
= blend
&&
123 blend
->blend_enable_4bit
& cb_target_mask
&&
124 sctx
->framebuffer
.nr_samples
>= 2;
125 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
127 radeon_opt_set_context_reg(
128 sctx
, R_028424_CB_DCC_CONTROL
,
129 SI_TRACKED_CB_DCC_CONTROL
,
130 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
131 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
132 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
133 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->has_dcc_constant_encode
));
136 /* RB+ register settings. */
137 if (sctx
->screen
->rbplus_allowed
) {
138 unsigned spi_shader_col_format
=
139 sctx
->ps_shader
.cso
?
140 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
141 unsigned sx_ps_downconvert
= 0;
142 unsigned sx_blend_opt_epsilon
= 0;
143 unsigned sx_blend_opt_control
= 0;
145 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
146 struct si_surface
*surf
=
147 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
148 unsigned format
, swap
, spi_format
, colormask
;
149 bool has_alpha
, has_rgb
;
152 /* If the color buffer is not set, the driver sets 32_R
153 * as the SPI color format, because the hw doesn't allow
154 * holes between color outputs, so also set this to
157 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
161 format
= G_028C70_FORMAT(surf
->cb_color_info
);
162 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
163 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
164 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
166 /* Set if RGB and A are present. */
167 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
169 if (format
== V_028C70_COLOR_8
||
170 format
== V_028C70_COLOR_16
||
171 format
== V_028C70_COLOR_32
)
172 has_rgb
= !has_alpha
;
176 /* Check the colormask and export format. */
177 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
179 if (!(colormask
& PIPE_MASK_A
))
182 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
187 /* Disable value checking for disabled channels. */
189 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
191 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
193 /* Enable down-conversion for 32bpp and smaller formats. */
195 case V_028C70_COLOR_8
:
196 case V_028C70_COLOR_8_8
:
197 case V_028C70_COLOR_8_8_8_8
:
198 /* For 1 and 2-channel formats, use the superset thereof. */
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
200 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
201 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
202 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
203 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
207 case V_028C70_COLOR_5_6_5
:
208 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
209 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
210 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
214 case V_028C70_COLOR_1_5_5_5
:
215 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
216 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
217 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
221 case V_028C70_COLOR_4_4_4_4
:
222 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
224 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
228 case V_028C70_COLOR_32
:
229 if (swap
== V_028C70_SWAP_STD
&&
230 spi_format
== V_028714_SPI_SHADER_32_R
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
232 else if (swap
== V_028C70_SWAP_ALT_REV
&&
233 spi_format
== V_028714_SPI_SHADER_32_AR
)
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
237 case V_028C70_COLOR_16
:
238 case V_028C70_COLOR_16_16
:
239 /* For 1-channel formats, use the superset thereof. */
240 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
241 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
242 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
243 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
244 if (swap
== V_028C70_SWAP_STD
||
245 swap
== V_028C70_SWAP_STD_REV
)
246 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
248 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
252 case V_028C70_COLOR_10_11_11
:
253 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
254 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
257 case V_028C70_COLOR_2_10_10_10
:
258 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
259 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
260 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
266 /* If there are no color outputs, the first color export is
267 * always enabled as 32_R, so also set this to enable RB+.
269 if (!sx_ps_downconvert
)
270 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
272 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
273 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
274 SI_TRACKED_SX_PS_DOWNCONVERT
,
275 sx_ps_downconvert
, sx_blend_opt_epsilon
,
276 sx_blend_opt_control
);
278 if (initial_cdw
!= cs
->current
.cdw
)
279 sctx
->context_roll
= true;
286 static uint32_t si_translate_blend_function(int blend_func
)
288 switch (blend_func
) {
290 return V_028780_COMB_DST_PLUS_SRC
;
291 case PIPE_BLEND_SUBTRACT
:
292 return V_028780_COMB_SRC_MINUS_DST
;
293 case PIPE_BLEND_REVERSE_SUBTRACT
:
294 return V_028780_COMB_DST_MINUS_SRC
;
296 return V_028780_COMB_MIN_DST_SRC
;
298 return V_028780_COMB_MAX_DST_SRC
;
300 PRINT_ERR("Unknown blend function %d\n", blend_func
);
307 static uint32_t si_translate_blend_factor(int blend_fact
)
309 switch (blend_fact
) {
310 case PIPE_BLENDFACTOR_ONE
:
311 return V_028780_BLEND_ONE
;
312 case PIPE_BLENDFACTOR_SRC_COLOR
:
313 return V_028780_BLEND_SRC_COLOR
;
314 case PIPE_BLENDFACTOR_SRC_ALPHA
:
315 return V_028780_BLEND_SRC_ALPHA
;
316 case PIPE_BLENDFACTOR_DST_ALPHA
:
317 return V_028780_BLEND_DST_ALPHA
;
318 case PIPE_BLENDFACTOR_DST_COLOR
:
319 return V_028780_BLEND_DST_COLOR
;
320 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
321 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
322 case PIPE_BLENDFACTOR_CONST_COLOR
:
323 return V_028780_BLEND_CONSTANT_COLOR
;
324 case PIPE_BLENDFACTOR_CONST_ALPHA
:
325 return V_028780_BLEND_CONSTANT_ALPHA
;
326 case PIPE_BLENDFACTOR_ZERO
:
327 return V_028780_BLEND_ZERO
;
328 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
330 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
331 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
332 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
333 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
334 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
335 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
336 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
337 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
338 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
340 case PIPE_BLENDFACTOR_SRC1_COLOR
:
341 return V_028780_BLEND_SRC1_COLOR
;
342 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
343 return V_028780_BLEND_SRC1_ALPHA
;
344 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
345 return V_028780_BLEND_INV_SRC1_COLOR
;
346 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
347 return V_028780_BLEND_INV_SRC1_ALPHA
;
349 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
356 static uint32_t si_translate_blend_opt_function(int blend_func
)
358 switch (blend_func
) {
360 return V_028760_OPT_COMB_ADD
;
361 case PIPE_BLEND_SUBTRACT
:
362 return V_028760_OPT_COMB_SUBTRACT
;
363 case PIPE_BLEND_REVERSE_SUBTRACT
:
364 return V_028760_OPT_COMB_REVSUBTRACT
;
366 return V_028760_OPT_COMB_MIN
;
368 return V_028760_OPT_COMB_MAX
;
370 return V_028760_OPT_COMB_BLEND_DISABLED
;
374 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
376 switch (blend_fact
) {
377 case PIPE_BLENDFACTOR_ZERO
:
378 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
379 case PIPE_BLENDFACTOR_ONE
:
380 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
381 case PIPE_BLENDFACTOR_SRC_COLOR
:
382 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
383 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
384 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
385 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
386 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
387 case PIPE_BLENDFACTOR_SRC_ALPHA
:
388 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
389 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
390 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
391 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
392 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
393 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
395 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
399 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
400 struct si_state_blend
*blend
,
401 enum pipe_blend_func func
,
402 enum pipe_blendfactor src
,
403 enum pipe_blendfactor dst
,
406 /* Src factor is allowed when it does not depend on Dst */
407 static const uint32_t src_allowed
=
408 (1u << PIPE_BLENDFACTOR_ONE
) |
409 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
412 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
413 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
414 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_ZERO
) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
419 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
420 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
421 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
422 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
424 if (dst
== PIPE_BLENDFACTOR_ONE
&&
425 (src_allowed
& (1u << src
))) {
426 /* Addition is commutative, but floating point addition isn't
427 * associative: subtle changes can be introduced via different
430 * Out-of-order is also non-deterministic, which means that
431 * this breaks OpenGL invariance requirements. So only enable
432 * out-of-order additive blending if explicitly allowed by a
435 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
436 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
437 blend
->commutative_4bit
|= chanmask
;
442 * Get rid of DST in the blend factors by commuting the operands:
443 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
445 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
446 unsigned *dst_factor
, unsigned expected_dst
,
447 unsigned replacement_src
)
449 if (*src_factor
== expected_dst
&&
450 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
451 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
452 *dst_factor
= replacement_src
;
454 /* Commuting the operands requires reversing subtractions. */
455 if (*func
== PIPE_BLEND_SUBTRACT
)
456 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
457 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
458 *func
= PIPE_BLEND_SUBTRACT
;
462 static bool si_blend_factor_uses_dst(unsigned factor
)
464 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
465 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
466 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
467 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
468 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
471 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
472 const struct pipe_blend_state
*state
,
475 struct si_context
*sctx
= (struct si_context
*)ctx
;
476 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
477 struct si_pm4_state
*pm4
= &blend
->pm4
;
478 uint32_t sx_mrt_blend_opt
[8] = {0};
479 uint32_t color_control
= 0;
480 bool logicop_enable
= state
->logicop_enable
&&
481 state
->logicop_func
!= PIPE_LOGICOP_COPY
;
486 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
487 blend
->alpha_to_one
= state
->alpha_to_one
;
488 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
489 blend
->logicop_enable
= logicop_enable
;
491 if (logicop_enable
) {
492 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
494 color_control
|= S_028808_ROP3(0xcc);
497 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
498 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
499 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
500 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
501 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
502 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
503 S_028B70_OFFSET_ROUND(1));
505 if (state
->alpha_to_coverage
)
506 blend
->need_src_alpha_4bit
|= 0xf;
508 blend
->cb_target_mask
= 0;
509 blend
->cb_target_enabled_4bit
= 0;
511 for (int i
= 0; i
< 8; i
++) {
512 /* state->rt entries > 0 only written if independent blending */
513 const int j
= state
->independent_blend_enable
? i
: 0;
515 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
516 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
517 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
518 unsigned eqA
= state
->rt
[j
].alpha_func
;
519 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
520 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
522 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
523 unsigned blend_cntl
= 0;
525 sx_mrt_blend_opt
[i
] =
526 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
527 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
529 /* Only set dual source blending for MRT0 to avoid a hang. */
530 if (i
>= 1 && blend
->dual_src_blend
) {
531 /* Vulkan does this for dual source blending. */
533 blend_cntl
|= S_028780_ENABLE(1);
535 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
539 /* Only addition and subtraction equations are supported with
540 * dual source blending.
542 if (blend
->dual_src_blend
&&
543 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
544 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
545 assert(!"Unsupported equation for dual source blending");
546 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
550 /* cb_render_state will disable unused ones */
551 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
552 if (state
->rt
[j
].colormask
)
553 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
555 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
556 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
560 si_blend_check_commutativity(sctx
->screen
, blend
,
561 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
562 si_blend_check_commutativity(sctx
->screen
, blend
,
563 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
565 /* Blending optimizations for RB+.
566 * These transformations don't change the behavior.
568 * First, get rid of DST in the blend factors:
569 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
571 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
572 PIPE_BLENDFACTOR_DST_COLOR
,
573 PIPE_BLENDFACTOR_SRC_COLOR
);
574 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
575 PIPE_BLENDFACTOR_DST_COLOR
,
576 PIPE_BLENDFACTOR_SRC_COLOR
);
577 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
578 PIPE_BLENDFACTOR_DST_ALPHA
,
579 PIPE_BLENDFACTOR_SRC_ALPHA
);
581 /* Look up the ideal settings from tables. */
582 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
583 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
584 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
585 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
587 /* Handle interdependencies. */
588 if (si_blend_factor_uses_dst(srcRGB
))
589 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
590 if (si_blend_factor_uses_dst(srcA
))
591 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
593 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
594 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
595 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
596 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
597 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
599 /* Set the final value. */
600 sx_mrt_blend_opt
[i
] =
601 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
602 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
603 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
604 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
605 S_028760_ALPHA_DST_OPT(dstA_opt
) |
606 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
608 /* Set blend state. */
609 blend_cntl
|= S_028780_ENABLE(1);
610 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
611 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
612 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
614 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
615 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
616 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
617 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
618 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
620 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
622 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
624 /* This is only important for formats without alpha. */
625 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
626 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
627 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
628 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
629 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
630 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
631 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
634 if (blend
->cb_target_mask
) {
635 color_control
|= S_028808_MODE(mode
);
637 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
640 if (sctx
->screen
->rbplus_allowed
) {
641 /* Disable RB+ blend optimizations for dual source blending.
644 if (blend
->dual_src_blend
) {
645 for (int i
= 0; i
< 8; i
++) {
646 sx_mrt_blend_opt
[i
] =
647 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
648 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
652 for (int i
= 0; i
< 8; i
++)
653 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
654 sx_mrt_blend_opt
[i
]);
656 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
657 if (blend
->dual_src_blend
|| logicop_enable
||
658 mode
== V_028808_CB_RESOLVE
)
659 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
662 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
666 static void *si_create_blend_state(struct pipe_context
*ctx
,
667 const struct pipe_blend_state
*state
)
669 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
672 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
674 struct si_context
*sctx
= (struct si_context
*)ctx
;
675 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
676 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
681 si_pm4_bind_state(sctx
, blend
, state
);
684 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
685 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
686 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
687 sctx
->framebuffer
.nr_samples
>= 2 &&
688 sctx
->screen
->dcc_msaa_allowed
))
689 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
692 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
693 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
694 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
695 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
696 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
697 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
698 sctx
->do_update_shaders
= true;
700 if (sctx
->screen
->dpbb_allowed
&&
702 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
703 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
704 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
705 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
707 if (sctx
->screen
->has_out_of_order_rast
&&
709 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
710 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
711 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
712 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
713 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
716 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
718 struct si_context
*sctx
= (struct si_context
*)ctx
;
719 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
722 static void si_set_blend_color(struct pipe_context
*ctx
,
723 const struct pipe_blend_color
*state
)
725 struct si_context
*sctx
= (struct si_context
*)ctx
;
726 static const struct pipe_blend_color zeros
;
728 sctx
->blend_color
.state
= *state
;
729 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
730 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
733 static void si_emit_blend_color(struct si_context
*sctx
)
735 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
737 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
738 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
745 static void si_set_clip_state(struct pipe_context
*ctx
,
746 const struct pipe_clip_state
*state
)
748 struct si_context
*sctx
= (struct si_context
*)ctx
;
749 struct pipe_constant_buffer cb
;
750 static const struct pipe_clip_state zeros
;
752 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
755 sctx
->clip_state
.state
= *state
;
756 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
757 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
760 cb
.user_buffer
= state
->ucp
;
761 cb
.buffer_offset
= 0;
762 cb
.buffer_size
= 4*4*8;
763 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
764 pipe_resource_reference(&cb
.buffer
, NULL
);
767 static void si_emit_clip_state(struct si_context
*sctx
)
769 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
771 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
772 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
775 static void si_emit_clip_regs(struct si_context
*sctx
)
777 struct si_shader
*vs
= si_get_vs_state(sctx
);
778 struct si_shader_selector
*vs_sel
= vs
->selector
;
779 struct tgsi_shader_info
*info
= &vs_sel
->info
;
780 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
781 unsigned window_space
=
782 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
783 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
784 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
785 unsigned culldist_mask
= vs_sel
->culldist_mask
;
788 if (vs
->key
.opt
.clip_disable
) {
789 assert(!info
->culldist_writemask
);
793 total_mask
= clipdist_mask
| culldist_mask
;
795 /* Clip distances on points have no effect, so need to be implemented
796 * as cull distances. This applies for the clipvertex case as well.
798 * Setting this for primitives other than points should have no adverse
801 clipdist_mask
&= rs
->clip_plane_enable
;
802 culldist_mask
|= clipdist_mask
;
804 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
805 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
806 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
807 vs_sel
->pa_cl_vs_out_cntl
|
808 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
810 clipdist_mask
| (culldist_mask
<< 8));
811 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
812 SI_TRACKED_PA_CL_CLIP_CNTL
,
813 rs
->pa_cl_clip_cntl
|
815 S_028810_CLIP_DISABLE(window_space
));
817 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
818 sctx
->context_roll
= true;
822 * inferred state between framebuffer and rasterizer
824 static void si_update_poly_offset_state(struct si_context
*sctx
)
826 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
828 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
829 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
833 /* Use the user format, not db_render_format, so that the polygon
834 * offset behaves as expected by applications.
836 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
837 case PIPE_FORMAT_Z16_UNORM
:
838 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
840 default: /* 24-bit */
841 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
843 case PIPE_FORMAT_Z32_FLOAT
:
844 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
845 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
854 static uint32_t si_translate_fill(uint32_t func
)
857 case PIPE_POLYGON_MODE_FILL
:
858 return V_028814_X_DRAW_TRIANGLES
;
859 case PIPE_POLYGON_MODE_LINE
:
860 return V_028814_X_DRAW_LINES
;
861 case PIPE_POLYGON_MODE_POINT
:
862 return V_028814_X_DRAW_POINTS
;
865 return V_028814_X_DRAW_POINTS
;
869 static void *si_create_rs_state(struct pipe_context
*ctx
,
870 const struct pipe_rasterizer_state
*state
)
872 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
873 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
874 struct si_pm4_state
*pm4
= &rs
->pm4
;
876 float psize_min
, psize_max
;
882 if (!state
->front_ccw
) {
883 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
884 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
886 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
887 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
889 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
890 rs
->provoking_vertex_first
= state
->flatshade_first
;
891 rs
->scissor_enable
= state
->scissor
;
892 rs
->clip_halfz
= state
->clip_halfz
;
893 rs
->two_side
= state
->light_twoside
;
894 rs
->multisample_enable
= state
->multisample
;
895 rs
->force_persample_interp
= state
->force_persample_interp
;
896 rs
->clip_plane_enable
= state
->clip_plane_enable
;
897 rs
->half_pixel_center
= state
->half_pixel_center
;
898 rs
->line_stipple_enable
= state
->line_stipple_enable
;
899 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
900 rs
->line_smooth
= state
->line_smooth
;
901 rs
->line_width
= state
->line_width
;
902 rs
->poly_smooth
= state
->poly_smooth
;
903 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
905 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
906 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
907 rs
->flatshade
= state
->flatshade
;
908 rs
->flatshade_first
= state
->flatshade_first
;
909 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
910 rs
->rasterizer_discard
= state
->rasterizer_discard
;
911 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
912 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
913 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
914 rs
->pa_cl_clip_cntl
=
915 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
916 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
917 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
918 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
919 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
921 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
922 S_0286D4_FLAT_SHADE_ENA(1) |
923 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
924 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
925 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
926 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
927 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
928 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
930 /* point size 12.4 fixed point */
931 tmp
= (unsigned)(state
->point_size
* 8.0);
932 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
934 if (state
->point_size_per_vertex
) {
935 psize_min
= util_get_min_point_size(state
);
936 psize_max
= SI_MAX_POINT_SIZE
;
938 /* Force the point size to be as if the vertex output was disabled. */
939 psize_min
= state
->point_size
;
940 psize_max
= state
->point_size
;
942 rs
->max_point_size
= psize_max
;
944 /* Divide by two, because 0.5 = 1 pixel. */
945 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
946 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
947 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
949 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
950 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
951 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
952 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
953 S_028A48_MSAA_ENABLE(state
->multisample
||
954 state
->poly_smooth
||
955 state
->line_smooth
) |
956 S_028A48_VPORT_SCISSOR_ENABLE(1) |
957 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
959 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
960 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
961 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
962 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
963 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
964 S_028814_FACE(!state
->front_ccw
) |
965 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
966 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
967 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
968 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
969 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
970 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
971 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
973 if (!rs
->uses_poly_offset
)
976 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
977 if (!rs
->pm4_poly_offset
) {
982 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
983 for (i
= 0; i
< 3; i
++) {
984 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
985 float offset_units
= state
->offset_units
;
986 float offset_scale
= state
->offset_scale
* 16.0f
;
987 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
989 if (!state
->offset_units_unscaled
) {
991 case 0: /* 16-bit zbuffer */
992 offset_units
*= 4.0f
;
993 pa_su_poly_offset_db_fmt_cntl
=
994 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
996 case 1: /* 24-bit zbuffer */
997 offset_units
*= 2.0f
;
998 pa_su_poly_offset_db_fmt_cntl
=
999 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1001 case 2: /* 32-bit zbuffer */
1002 offset_units
*= 1.0f
;
1003 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1004 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1009 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1011 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1013 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1015 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1017 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1018 pa_su_poly_offset_db_fmt_cntl
);
1024 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1026 struct si_context
*sctx
= (struct si_context
*)ctx
;
1027 struct si_state_rasterizer
*old_rs
=
1028 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1029 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1034 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1035 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1037 /* Update the small primitive filter workaround if necessary. */
1038 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1039 sctx
->framebuffer
.nr_samples
> 1)
1040 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1043 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1044 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1046 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1047 si_update_poly_offset_state(sctx
);
1050 old_rs
->scissor_enable
!= rs
->scissor_enable
)
1051 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1054 old_rs
->line_width
!= rs
->line_width
||
1055 old_rs
->max_point_size
!= rs
->max_point_size
||
1056 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1057 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1060 old_rs
->clip_halfz
!= rs
->clip_halfz
)
1061 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1064 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1065 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1066 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1068 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1069 rs
->line_stipple_enable
;
1072 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1073 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1074 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1075 old_rs
->flatshade
!= rs
->flatshade
||
1076 old_rs
->two_side
!= rs
->two_side
||
1077 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1078 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1079 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1080 old_rs
->line_smooth
!= rs
->line_smooth
||
1081 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1082 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1083 sctx
->do_update_shaders
= true;
1086 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1088 struct si_context
*sctx
= (struct si_context
*)ctx
;
1089 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1091 if (sctx
->queued
.named
.rasterizer
== state
)
1092 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1094 FREE(rs
->pm4_poly_offset
);
1095 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1099 * infeered state between dsa and stencil ref
1101 static void si_emit_stencil_ref(struct si_context
*sctx
)
1103 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1104 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1105 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1107 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1108 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1109 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1110 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1111 S_028430_STENCILOPVAL(1));
1112 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1113 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1114 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1115 S_028434_STENCILOPVAL_BF(1));
1118 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1119 const struct pipe_stencil_ref
*state
)
1121 struct si_context
*sctx
= (struct si_context
*)ctx
;
1123 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1126 sctx
->stencil_ref
.state
= *state
;
1127 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1135 static uint32_t si_translate_stencil_op(int s_op
)
1138 case PIPE_STENCIL_OP_KEEP
:
1139 return V_02842C_STENCIL_KEEP
;
1140 case PIPE_STENCIL_OP_ZERO
:
1141 return V_02842C_STENCIL_ZERO
;
1142 case PIPE_STENCIL_OP_REPLACE
:
1143 return V_02842C_STENCIL_REPLACE_TEST
;
1144 case PIPE_STENCIL_OP_INCR
:
1145 return V_02842C_STENCIL_ADD_CLAMP
;
1146 case PIPE_STENCIL_OP_DECR
:
1147 return V_02842C_STENCIL_SUB_CLAMP
;
1148 case PIPE_STENCIL_OP_INCR_WRAP
:
1149 return V_02842C_STENCIL_ADD_WRAP
;
1150 case PIPE_STENCIL_OP_DECR_WRAP
:
1151 return V_02842C_STENCIL_SUB_WRAP
;
1152 case PIPE_STENCIL_OP_INVERT
:
1153 return V_02842C_STENCIL_INVERT
;
1155 PRINT_ERR("Unknown stencil op %d", s_op
);
1162 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1164 return s
->enabled
&& s
->writemask
&&
1165 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1166 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1167 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1170 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1172 /* REPLACE is normally order invariant, except when the stencil
1173 * reference value is written by the fragment shader. Tracking this
1174 * interaction does not seem worth the effort, so be conservative. */
1175 return op
!= PIPE_STENCIL_OP_INCR
&&
1176 op
!= PIPE_STENCIL_OP_DECR
&&
1177 op
!= PIPE_STENCIL_OP_REPLACE
;
1180 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1181 * invariant in the sense that the set of passing fragments as well as the
1182 * final stencil buffer result does not depend on the order of fragments. */
1183 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1185 return !state
->enabled
|| !state
->writemask
||
1186 /* The following assumes that Z writes are disabled. */
1187 (state
->func
== PIPE_FUNC_ALWAYS
&&
1188 si_order_invariant_stencil_op(state
->zpass_op
) &&
1189 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1190 (state
->func
== PIPE_FUNC_NEVER
&&
1191 si_order_invariant_stencil_op(state
->fail_op
));
1194 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1195 const struct pipe_depth_stencil_alpha_state
*state
)
1197 struct si_context
*sctx
= (struct si_context
*)ctx
;
1198 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1199 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1200 unsigned db_depth_control
;
1201 uint32_t db_stencil_control
= 0;
1207 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1208 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1209 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1210 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1212 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1213 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1214 S_028800_ZFUNC(state
->depth
.func
) |
1215 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1218 if (state
->stencil
[0].enabled
) {
1219 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1220 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1221 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1222 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1223 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1225 if (state
->stencil
[1].enabled
) {
1226 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1227 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1228 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1229 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1230 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1235 if (state
->alpha
.enabled
) {
1236 dsa
->alpha_func
= state
->alpha
.func
;
1238 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1239 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1241 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1244 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1245 if (state
->stencil
[0].enabled
)
1246 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1247 if (state
->depth
.bounds_test
) {
1248 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1249 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1252 dsa
->depth_enabled
= state
->depth
.enabled
;
1253 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1254 state
->depth
.writemask
;
1255 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1256 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1257 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1258 si_dsa_writes_stencil(&state
->stencil
[1]));
1259 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1260 dsa
->stencil_write_enabled
;
1262 bool zfunc_is_ordered
=
1263 state
->depth
.func
== PIPE_FUNC_NEVER
||
1264 state
->depth
.func
== PIPE_FUNC_LESS
||
1265 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1266 state
->depth
.func
== PIPE_FUNC_GREATER
||
1267 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1269 bool nozwrite_and_order_invariant_stencil
=
1270 !dsa
->db_can_write
||
1271 (!dsa
->depth_write_enabled
&&
1272 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1273 si_order_invariant_stencil_state(&state
->stencil
[1]));
1275 dsa
->order_invariance
[1].zs
=
1276 nozwrite_and_order_invariant_stencil
||
1277 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1278 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1280 dsa
->order_invariance
[1].pass_set
=
1281 nozwrite_and_order_invariant_stencil
||
1282 (!dsa
->stencil_write_enabled
&&
1283 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1284 state
->depth
.func
== PIPE_FUNC_NEVER
));
1285 dsa
->order_invariance
[0].pass_set
=
1286 !dsa
->depth_write_enabled
||
1287 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1288 state
->depth
.func
== PIPE_FUNC_NEVER
);
1290 dsa
->order_invariance
[1].pass_last
=
1291 sctx
->screen
->assume_no_z_fights
&&
1292 !dsa
->stencil_write_enabled
&&
1293 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1294 dsa
->order_invariance
[0].pass_last
=
1295 sctx
->screen
->assume_no_z_fights
&&
1296 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1301 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1303 struct si_context
*sctx
= (struct si_context
*)ctx
;
1304 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1305 struct si_state_dsa
*dsa
= state
;
1310 si_pm4_bind_state(sctx
, dsa
, dsa
);
1312 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1313 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1314 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1315 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1318 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1319 sctx
->do_update_shaders
= true;
1321 if (sctx
->screen
->dpbb_allowed
&&
1323 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1324 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1325 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1326 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1328 if (sctx
->screen
->has_out_of_order_rast
&&
1330 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1331 sizeof(old_dsa
->order_invariance
))))
1332 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1335 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1337 struct si_context
*sctx
= (struct si_context
*)ctx
;
1338 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1341 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1343 struct pipe_depth_stencil_alpha_state dsa
= {};
1345 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1348 /* DB RENDER STATE */
1350 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1352 struct si_context
*sctx
= (struct si_context
*)ctx
;
1354 /* Pipeline stat & streamout queries. */
1356 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1357 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1359 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1360 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1363 /* Occlusion queries. */
1364 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1365 sctx
->occlusion_queries_disabled
= !enable
;
1366 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1370 void si_set_occlusion_query_state(struct si_context
*sctx
,
1371 bool old_perfect_enable
)
1373 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1375 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1377 if (perfect_enable
!= old_perfect_enable
)
1378 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1381 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1383 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1385 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1386 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1388 st
->saved_ssbo_writable_mask
= 0;
1390 for (unsigned i
= 0; i
< 3; i
++) {
1391 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1392 (1u << si_get_shaderbuf_slot(i
)))
1393 st
->saved_ssbo_writable_mask
|= 1 << i
;
1397 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1399 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1401 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1402 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1404 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1405 st
->saved_ssbo_writable_mask
);
1406 for (unsigned i
= 0; i
< 3; ++i
)
1407 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1410 static void si_emit_db_render_state(struct si_context
*sctx
)
1412 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1413 unsigned db_shader_control
, db_render_control
, db_count_control
;
1414 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1416 /* DB_RENDER_CONTROL */
1417 if (sctx
->dbcb_depth_copy_enabled
||
1418 sctx
->dbcb_stencil_copy_enabled
) {
1420 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1421 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1422 S_028000_COPY_CENTROID(1) |
1423 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1424 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1426 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1427 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1430 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1431 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1434 /* DB_COUNT_CONTROL (occlusion queries) */
1435 if (sctx
->num_occlusion_queries
> 0 &&
1436 !sctx
->occlusion_queries_disabled
) {
1437 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1438 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1440 if (sctx
->chip_class
>= GFX7
) {
1441 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1443 /* Stoney doesn't increment occlusion query counters
1444 * if the sample rate is 16x. Use 8x sample rate instead.
1446 if (sctx
->family
== CHIP_STONEY
)
1447 log_sample_rate
= MIN2(log_sample_rate
, 3);
1450 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1451 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1452 S_028004_SAMPLE_RATE(log_sample_rate
) |
1453 S_028004_ZPASS_ENABLE(1) |
1454 S_028004_SLICE_EVEN_ENABLE(1) |
1455 S_028004_SLICE_ODD_ENABLE(1);
1458 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1459 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1462 /* Disable occlusion queries. */
1463 if (sctx
->chip_class
>= GFX7
) {
1464 db_count_control
= 0;
1466 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1470 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1471 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1474 /* DB_RENDER_OVERRIDE2 */
1475 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1476 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1477 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1478 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1479 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1481 db_shader_control
= sctx
->ps_db_shader_control
;
1483 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1484 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1485 db_shader_control
&= C_02880C_Z_ORDER
;
1486 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1489 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1490 if (!rs
->multisample_enable
)
1491 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1493 if (sctx
->screen
->has_rbplus
&&
1494 !sctx
->screen
->rbplus_allowed
)
1495 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1497 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1498 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1500 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1501 sctx
->context_roll
= true;
1505 * format translation
1507 static uint32_t si_translate_colorformat(enum pipe_format format
)
1509 const struct util_format_description
*desc
= util_format_description(format
);
1511 return V_028C70_COLOR_INVALID
;
1513 #define HAS_SIZE(x,y,z,w) \
1514 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1515 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1517 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1518 return V_028C70_COLOR_10_11_11
;
1520 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1521 return V_028C70_COLOR_INVALID
;
1523 /* hw cannot support mixed formats (except depth/stencil, since
1524 * stencil is not written to). */
1525 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1526 return V_028C70_COLOR_INVALID
;
1528 switch (desc
->nr_channels
) {
1530 switch (desc
->channel
[0].size
) {
1532 return V_028C70_COLOR_8
;
1534 return V_028C70_COLOR_16
;
1536 return V_028C70_COLOR_32
;
1540 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1541 switch (desc
->channel
[0].size
) {
1543 return V_028C70_COLOR_8_8
;
1545 return V_028C70_COLOR_16_16
;
1547 return V_028C70_COLOR_32_32
;
1549 } else if (HAS_SIZE(8,24,0,0)) {
1550 return V_028C70_COLOR_24_8
;
1551 } else if (HAS_SIZE(24,8,0,0)) {
1552 return V_028C70_COLOR_8_24
;
1556 if (HAS_SIZE(5,6,5,0)) {
1557 return V_028C70_COLOR_5_6_5
;
1558 } else if (HAS_SIZE(32,8,24,0)) {
1559 return V_028C70_COLOR_X24_8_32_FLOAT
;
1563 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1564 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1565 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1566 switch (desc
->channel
[0].size
) {
1568 return V_028C70_COLOR_4_4_4_4
;
1570 return V_028C70_COLOR_8_8_8_8
;
1572 return V_028C70_COLOR_16_16_16_16
;
1574 return V_028C70_COLOR_32_32_32_32
;
1576 } else if (HAS_SIZE(5,5,5,1)) {
1577 return V_028C70_COLOR_1_5_5_5
;
1578 } else if (HAS_SIZE(1,5,5,5)) {
1579 return V_028C70_COLOR_5_5_5_1
;
1580 } else if (HAS_SIZE(10,10,10,2)) {
1581 return V_028C70_COLOR_2_10_10_10
;
1585 return V_028C70_COLOR_INVALID
;
1588 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1590 if (SI_BIG_ENDIAN
) {
1591 switch(colorformat
) {
1592 /* 8-bit buffers. */
1593 case V_028C70_COLOR_8
:
1594 return V_028C70_ENDIAN_NONE
;
1596 /* 16-bit buffers. */
1597 case V_028C70_COLOR_5_6_5
:
1598 case V_028C70_COLOR_1_5_5_5
:
1599 case V_028C70_COLOR_4_4_4_4
:
1600 case V_028C70_COLOR_16
:
1601 case V_028C70_COLOR_8_8
:
1602 return V_028C70_ENDIAN_8IN16
;
1604 /* 32-bit buffers. */
1605 case V_028C70_COLOR_8_8_8_8
:
1606 case V_028C70_COLOR_2_10_10_10
:
1607 case V_028C70_COLOR_8_24
:
1608 case V_028C70_COLOR_24_8
:
1609 case V_028C70_COLOR_16_16
:
1610 return V_028C70_ENDIAN_8IN32
;
1612 /* 64-bit buffers. */
1613 case V_028C70_COLOR_16_16_16_16
:
1614 return V_028C70_ENDIAN_8IN16
;
1616 case V_028C70_COLOR_32_32
:
1617 return V_028C70_ENDIAN_8IN32
;
1619 /* 128-bit buffers. */
1620 case V_028C70_COLOR_32_32_32_32
:
1621 return V_028C70_ENDIAN_8IN32
;
1623 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1626 return V_028C70_ENDIAN_NONE
;
1630 static uint32_t si_translate_dbformat(enum pipe_format format
)
1633 case PIPE_FORMAT_Z16_UNORM
:
1634 return V_028040_Z_16
;
1635 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1636 case PIPE_FORMAT_X8Z24_UNORM
:
1637 case PIPE_FORMAT_Z24X8_UNORM
:
1638 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1639 return V_028040_Z_24
; /* deprecated on AMD GCN */
1640 case PIPE_FORMAT_Z32_FLOAT
:
1641 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1642 return V_028040_Z_32_FLOAT
;
1644 return V_028040_Z_INVALID
;
1649 * Texture translation
1652 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1653 enum pipe_format format
,
1654 const struct util_format_description
*desc
,
1657 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1658 bool uniform
= true;
1661 assert(sscreen
->info
.chip_class
<= GFX9
);
1663 /* Colorspace (return non-RGB formats directly). */
1664 switch (desc
->colorspace
) {
1665 /* Depth stencil formats */
1666 case UTIL_FORMAT_COLORSPACE_ZS
:
1668 case PIPE_FORMAT_Z16_UNORM
:
1669 return V_008F14_IMG_DATA_FORMAT_16
;
1670 case PIPE_FORMAT_X24S8_UINT
:
1671 case PIPE_FORMAT_S8X24_UINT
:
1673 * Implemented as an 8_8_8_8 data format to fix texture
1674 * gathers in stencil sampling. This affects at least
1675 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1677 if (sscreen
->info
.chip_class
<= GFX8
)
1678 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1680 if (format
== PIPE_FORMAT_X24S8_UINT
)
1681 return V_008F14_IMG_DATA_FORMAT_8_24
;
1683 return V_008F14_IMG_DATA_FORMAT_24_8
;
1684 case PIPE_FORMAT_Z24X8_UNORM
:
1685 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1686 return V_008F14_IMG_DATA_FORMAT_8_24
;
1687 case PIPE_FORMAT_X8Z24_UNORM
:
1688 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1689 return V_008F14_IMG_DATA_FORMAT_24_8
;
1690 case PIPE_FORMAT_S8_UINT
:
1691 return V_008F14_IMG_DATA_FORMAT_8
;
1692 case PIPE_FORMAT_Z32_FLOAT
:
1693 return V_008F14_IMG_DATA_FORMAT_32
;
1694 case PIPE_FORMAT_X32_S8X24_UINT
:
1695 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1696 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1701 case UTIL_FORMAT_COLORSPACE_YUV
:
1702 goto out_unknown
; /* TODO */
1704 case UTIL_FORMAT_COLORSPACE_SRGB
:
1705 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1713 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1714 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1718 case PIPE_FORMAT_RGTC1_SNORM
:
1719 case PIPE_FORMAT_LATC1_SNORM
:
1720 case PIPE_FORMAT_RGTC1_UNORM
:
1721 case PIPE_FORMAT_LATC1_UNORM
:
1722 return V_008F14_IMG_DATA_FORMAT_BC4
;
1723 case PIPE_FORMAT_RGTC2_SNORM
:
1724 case PIPE_FORMAT_LATC2_SNORM
:
1725 case PIPE_FORMAT_RGTC2_UNORM
:
1726 case PIPE_FORMAT_LATC2_UNORM
:
1727 return V_008F14_IMG_DATA_FORMAT_BC5
;
1733 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1734 (sscreen
->info
.family
== CHIP_STONEY
||
1735 sscreen
->info
.family
== CHIP_VEGA10
||
1736 sscreen
->info
.family
== CHIP_RAVEN
)) {
1738 case PIPE_FORMAT_ETC1_RGB8
:
1739 case PIPE_FORMAT_ETC2_RGB8
:
1740 case PIPE_FORMAT_ETC2_SRGB8
:
1741 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1742 case PIPE_FORMAT_ETC2_RGB8A1
:
1743 case PIPE_FORMAT_ETC2_SRGB8A1
:
1744 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1745 case PIPE_FORMAT_ETC2_RGBA8
:
1746 case PIPE_FORMAT_ETC2_SRGBA8
:
1747 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1748 case PIPE_FORMAT_ETC2_R11_UNORM
:
1749 case PIPE_FORMAT_ETC2_R11_SNORM
:
1750 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1751 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1752 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1753 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1759 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1760 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1764 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1765 case PIPE_FORMAT_BPTC_SRGBA
:
1766 return V_008F14_IMG_DATA_FORMAT_BC7
;
1767 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1768 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1769 return V_008F14_IMG_DATA_FORMAT_BC6
;
1775 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1777 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1778 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1779 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1780 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1781 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1782 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1788 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1789 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1793 case PIPE_FORMAT_DXT1_RGB
:
1794 case PIPE_FORMAT_DXT1_RGBA
:
1795 case PIPE_FORMAT_DXT1_SRGB
:
1796 case PIPE_FORMAT_DXT1_SRGBA
:
1797 return V_008F14_IMG_DATA_FORMAT_BC1
;
1798 case PIPE_FORMAT_DXT3_RGBA
:
1799 case PIPE_FORMAT_DXT3_SRGBA
:
1800 return V_008F14_IMG_DATA_FORMAT_BC2
;
1801 case PIPE_FORMAT_DXT5_RGBA
:
1802 case PIPE_FORMAT_DXT5_SRGBA
:
1803 return V_008F14_IMG_DATA_FORMAT_BC3
;
1809 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1810 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1811 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1812 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1815 /* R8G8Bx_SNORM - TODO CxV8U8 */
1817 /* hw cannot support mixed formats (except depth/stencil, since only
1819 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1822 /* See whether the components are of the same size. */
1823 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1824 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1827 /* Non-uniform formats. */
1829 switch(desc
->nr_channels
) {
1831 if (desc
->channel
[0].size
== 5 &&
1832 desc
->channel
[1].size
== 6 &&
1833 desc
->channel
[2].size
== 5) {
1834 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1838 if (desc
->channel
[0].size
== 5 &&
1839 desc
->channel
[1].size
== 5 &&
1840 desc
->channel
[2].size
== 5 &&
1841 desc
->channel
[3].size
== 1) {
1842 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1844 if (desc
->channel
[0].size
== 1 &&
1845 desc
->channel
[1].size
== 5 &&
1846 desc
->channel
[2].size
== 5 &&
1847 desc
->channel
[3].size
== 5) {
1848 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1850 if (desc
->channel
[0].size
== 10 &&
1851 desc
->channel
[1].size
== 10 &&
1852 desc
->channel
[2].size
== 10 &&
1853 desc
->channel
[3].size
== 2) {
1854 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1861 if (first_non_void
< 0 || first_non_void
> 3)
1864 /* uniform formats */
1865 switch (desc
->channel
[first_non_void
].size
) {
1867 switch (desc
->nr_channels
) {
1868 #if 0 /* Not supported for render targets */
1870 return V_008F14_IMG_DATA_FORMAT_4_4
;
1873 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1877 switch (desc
->nr_channels
) {
1879 return V_008F14_IMG_DATA_FORMAT_8
;
1881 return V_008F14_IMG_DATA_FORMAT_8_8
;
1883 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1887 switch (desc
->nr_channels
) {
1889 return V_008F14_IMG_DATA_FORMAT_16
;
1891 return V_008F14_IMG_DATA_FORMAT_16_16
;
1893 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1897 switch (desc
->nr_channels
) {
1899 return V_008F14_IMG_DATA_FORMAT_32
;
1901 return V_008F14_IMG_DATA_FORMAT_32_32
;
1902 #if 0 /* Not supported for render targets */
1904 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1907 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1915 static unsigned si_tex_wrap(unsigned wrap
)
1919 case PIPE_TEX_WRAP_REPEAT
:
1920 return V_008F30_SQ_TEX_WRAP
;
1921 case PIPE_TEX_WRAP_CLAMP
:
1922 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1923 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1924 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1925 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1926 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1927 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1928 return V_008F30_SQ_TEX_MIRROR
;
1929 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1930 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1931 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1932 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1933 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1934 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1938 static unsigned si_tex_mipfilter(unsigned filter
)
1941 case PIPE_TEX_MIPFILTER_NEAREST
:
1942 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1943 case PIPE_TEX_MIPFILTER_LINEAR
:
1944 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1946 case PIPE_TEX_MIPFILTER_NONE
:
1947 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1951 static unsigned si_tex_compare(unsigned compare
)
1955 case PIPE_FUNC_NEVER
:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1957 case PIPE_FUNC_LESS
:
1958 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1959 case PIPE_FUNC_EQUAL
:
1960 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1961 case PIPE_FUNC_LEQUAL
:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1963 case PIPE_FUNC_GREATER
:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1965 case PIPE_FUNC_NOTEQUAL
:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1967 case PIPE_FUNC_GEQUAL
:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1969 case PIPE_FUNC_ALWAYS
:
1970 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1974 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1975 unsigned view_target
, unsigned nr_samples
)
1977 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1979 if (view_target
== PIPE_TEXTURE_CUBE
||
1980 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1981 res_target
= view_target
;
1982 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1983 else if (res_target
== PIPE_TEXTURE_CUBE
||
1984 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1985 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1987 /* GFX9 allocates 1D textures as 2D. */
1988 if ((res_target
== PIPE_TEXTURE_1D
||
1989 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1990 sscreen
->info
.chip_class
== GFX9
&&
1991 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1992 if (res_target
== PIPE_TEXTURE_1D
)
1993 res_target
= PIPE_TEXTURE_2D
;
1995 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1998 switch (res_target
) {
2000 case PIPE_TEXTURE_1D
:
2001 return V_008F1C_SQ_RSRC_IMG_1D
;
2002 case PIPE_TEXTURE_1D_ARRAY
:
2003 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
2004 case PIPE_TEXTURE_2D
:
2005 case PIPE_TEXTURE_RECT
:
2006 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
2007 V_008F1C_SQ_RSRC_IMG_2D
;
2008 case PIPE_TEXTURE_2D_ARRAY
:
2009 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
2010 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2011 case PIPE_TEXTURE_3D
:
2012 return V_008F1C_SQ_RSRC_IMG_3D
;
2013 case PIPE_TEXTURE_CUBE
:
2014 case PIPE_TEXTURE_CUBE_ARRAY
:
2015 return V_008F1C_SQ_RSRC_IMG_CUBE
;
2020 * Format support testing
2023 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
2025 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2027 if (sscreen
->info
.chip_class
>= GFX10
) {
2028 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2029 if (!fmt
->img_format
|| fmt
->buffers_only
)
2034 const struct util_format_description
*desc
= util_format_description(format
);
2038 return si_translate_texformat(screen
, format
, desc
,
2039 util_format_get_first_non_void_channel(format
)) != ~0U;
2042 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
2043 const struct util_format_description
*desc
,
2048 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2050 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2051 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
2053 assert(first_non_void
>= 0);
2055 if (desc
->nr_channels
== 4 &&
2056 desc
->channel
[0].size
== 10 &&
2057 desc
->channel
[1].size
== 10 &&
2058 desc
->channel
[2].size
== 10 &&
2059 desc
->channel
[3].size
== 2)
2060 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
2062 /* See whether the components are of the same size. */
2063 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2064 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2065 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2068 switch (desc
->channel
[first_non_void
].size
) {
2070 switch (desc
->nr_channels
) {
2072 case 3: /* 3 loads */
2073 return V_008F0C_BUF_DATA_FORMAT_8
;
2075 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2077 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2081 switch (desc
->nr_channels
) {
2083 case 3: /* 3 loads */
2084 return V_008F0C_BUF_DATA_FORMAT_16
;
2086 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2088 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2092 switch (desc
->nr_channels
) {
2094 return V_008F0C_BUF_DATA_FORMAT_32
;
2096 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2098 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2100 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2104 /* Legacy double formats. */
2105 switch (desc
->nr_channels
) {
2106 case 1: /* 1 load */
2107 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2108 case 2: /* 1 load */
2109 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2110 case 3: /* 3 loads */
2111 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2112 case 4: /* 2 loads */
2113 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2118 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2121 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2122 const struct util_format_description
*desc
,
2125 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2127 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2128 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2130 assert(first_non_void
>= 0);
2132 switch (desc
->channel
[first_non_void
].type
) {
2133 case UTIL_FORMAT_TYPE_SIGNED
:
2134 case UTIL_FORMAT_TYPE_FIXED
:
2135 if (desc
->channel
[first_non_void
].size
>= 32 ||
2136 desc
->channel
[first_non_void
].pure_integer
)
2137 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2138 else if (desc
->channel
[first_non_void
].normalized
)
2139 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2141 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2143 case UTIL_FORMAT_TYPE_UNSIGNED
:
2144 if (desc
->channel
[first_non_void
].size
>= 32 ||
2145 desc
->channel
[first_non_void
].pure_integer
)
2146 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2147 else if (desc
->channel
[first_non_void
].normalized
)
2148 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2150 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2152 case UTIL_FORMAT_TYPE_FLOAT
:
2154 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2158 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2159 enum pipe_format format
,
2162 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2163 const struct util_format_description
*desc
;
2165 unsigned data_format
;
2167 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2168 PIPE_BIND_SAMPLER_VIEW
|
2169 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2171 desc
= util_format_description(format
);
2175 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2176 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2177 * for read-only access (with caveats surrounding bounds checks), but
2178 * obviously fails for write access which we have to implement for
2179 * shader images. Luckily, OpenGL doesn't expect this to be supported
2180 * anyway, and so the only impact is on PBO uploads / downloads, which
2181 * shouldn't be expected to be fast for GL_RGB anyway.
2183 if (desc
->block
.bits
== 3 * 8 ||
2184 desc
->block
.bits
== 3 * 16) {
2185 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2186 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2192 if (sscreen
->info
.chip_class
>= GFX10
) {
2193 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2194 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2199 first_non_void
= util_format_get_first_non_void_channel(format
);
2200 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2201 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2207 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2209 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2210 si_translate_colorswap(format
, false) != ~0U;
2213 static bool si_is_zs_format_supported(enum pipe_format format
)
2215 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2218 static bool si_is_format_supported(struct pipe_screen
*screen
,
2219 enum pipe_format format
,
2220 enum pipe_texture_target target
,
2221 unsigned sample_count
,
2222 unsigned storage_sample_count
,
2225 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2226 unsigned retval
= 0;
2228 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2229 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2233 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2236 if (sample_count
> 1) {
2237 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2240 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2243 /* Only power-of-two sample counts are supported. */
2244 if (!util_is_power_of_two_or_zero(sample_count
) ||
2245 !util_is_power_of_two_or_zero(storage_sample_count
))
2248 /* MSAA support without framebuffer attachments. */
2249 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2252 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2253 util_format_is_depth_or_stencil(format
)) {
2254 /* Color without EQAA or depth/stencil. */
2255 if (sample_count
> 8 ||
2256 sample_count
!= storage_sample_count
)
2259 /* Color with EQAA. */
2260 if (sample_count
> 16 ||
2261 storage_sample_count
> 8)
2266 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2267 PIPE_BIND_SHADER_IMAGE
)) {
2268 if (target
== PIPE_BUFFER
) {
2269 retval
|= si_is_vertex_format_supported(
2270 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2271 PIPE_BIND_SHADER_IMAGE
));
2273 if (si_is_sampler_format_supported(screen
, format
))
2274 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2275 PIPE_BIND_SHADER_IMAGE
);
2279 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2280 PIPE_BIND_DISPLAY_TARGET
|
2283 PIPE_BIND_BLENDABLE
)) &&
2284 si_is_colorbuffer_format_supported(format
)) {
2286 (PIPE_BIND_RENDER_TARGET
|
2287 PIPE_BIND_DISPLAY_TARGET
|
2290 if (!util_format_is_pure_integer(format
) &&
2291 !util_format_is_depth_or_stencil(format
))
2292 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2295 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2296 si_is_zs_format_supported(format
)) {
2297 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2300 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2301 retval
|= si_is_vertex_format_supported(screen
, format
,
2302 PIPE_BIND_VERTEX_BUFFER
);
2305 if ((usage
& PIPE_BIND_LINEAR
) &&
2306 !util_format_is_compressed(format
) &&
2307 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2308 retval
|= PIPE_BIND_LINEAR
;
2310 return retval
== usage
;
2314 * framebuffer handling
2317 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2318 unsigned format
, unsigned swap
,
2319 unsigned ntype
, bool is_depth
)
2321 /* Alpha is needed for alpha-to-coverage.
2322 * Blending may be with or without alpha.
2324 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2325 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2326 unsigned blend
= 0; /* supports blending, but may not export alpha */
2327 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2329 /* Choose the SPI color formats. These are required values for RB+.
2330 * Other chips have multiple choices, though they are not necessarily better.
2333 case V_028C70_COLOR_5_6_5
:
2334 case V_028C70_COLOR_1_5_5_5
:
2335 case V_028C70_COLOR_5_5_5_1
:
2336 case V_028C70_COLOR_4_4_4_4
:
2337 case V_028C70_COLOR_10_11_11
:
2338 case V_028C70_COLOR_11_11_10
:
2339 case V_028C70_COLOR_8
:
2340 case V_028C70_COLOR_8_8
:
2341 case V_028C70_COLOR_8_8_8_8
:
2342 case V_028C70_COLOR_10_10_10_2
:
2343 case V_028C70_COLOR_2_10_10_10
:
2344 if (ntype
== V_028C70_NUMBER_UINT
)
2345 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2346 else if (ntype
== V_028C70_NUMBER_SINT
)
2347 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2349 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2352 case V_028C70_COLOR_16
:
2353 case V_028C70_COLOR_16_16
:
2354 case V_028C70_COLOR_16_16_16_16
:
2355 if (ntype
== V_028C70_NUMBER_UNORM
||
2356 ntype
== V_028C70_NUMBER_SNORM
) {
2357 /* UNORM16 and SNORM16 don't support blending */
2358 if (ntype
== V_028C70_NUMBER_UNORM
)
2359 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2361 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2363 /* Use 32 bits per channel for blending. */
2364 if (format
== V_028C70_COLOR_16
) {
2365 if (swap
== V_028C70_SWAP_STD
) { /* R */
2366 blend
= V_028714_SPI_SHADER_32_R
;
2367 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2368 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2369 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2372 } else if (format
== V_028C70_COLOR_16_16
) {
2373 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2374 blend
= V_028714_SPI_SHADER_32_GR
;
2375 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2376 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2377 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2380 } else /* 16_16_16_16 */
2381 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2382 } else if (ntype
== V_028C70_NUMBER_UINT
)
2383 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2384 else if (ntype
== V_028C70_NUMBER_SINT
)
2385 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2386 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2387 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2392 case V_028C70_COLOR_32
:
2393 if (swap
== V_028C70_SWAP_STD
) { /* R */
2394 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2395 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2396 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2397 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2402 case V_028C70_COLOR_32_32
:
2403 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2404 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2405 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2406 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2407 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2412 case V_028C70_COLOR_32_32_32_32
:
2413 case V_028C70_COLOR_8_24
:
2414 case V_028C70_COLOR_24_8
:
2415 case V_028C70_COLOR_X24_8_32_FLOAT
:
2416 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2424 /* The DB->CB copy needs 32_ABGR. */
2426 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2428 surf
->spi_shader_col_format
= normal
;
2429 surf
->spi_shader_col_format_alpha
= alpha
;
2430 surf
->spi_shader_col_format_blend
= blend
;
2431 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2434 static void si_initialize_color_surface(struct si_context
*sctx
,
2435 struct si_surface
*surf
)
2437 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2438 unsigned color_info
, color_attrib
;
2439 unsigned format
, swap
, ntype
, endian
;
2440 const struct util_format_description
*desc
;
2442 unsigned blend_clamp
= 0, blend_bypass
= 0;
2444 desc
= util_format_description(surf
->base
.format
);
2445 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2446 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2450 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2451 ntype
= V_028C70_NUMBER_FLOAT
;
2453 ntype
= V_028C70_NUMBER_UNORM
;
2454 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2455 ntype
= V_028C70_NUMBER_SRGB
;
2456 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2457 if (desc
->channel
[firstchan
].pure_integer
) {
2458 ntype
= V_028C70_NUMBER_SINT
;
2460 assert(desc
->channel
[firstchan
].normalized
);
2461 ntype
= V_028C70_NUMBER_SNORM
;
2463 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2464 if (desc
->channel
[firstchan
].pure_integer
) {
2465 ntype
= V_028C70_NUMBER_UINT
;
2467 assert(desc
->channel
[firstchan
].normalized
);
2468 ntype
= V_028C70_NUMBER_UNORM
;
2473 format
= si_translate_colorformat(surf
->base
.format
);
2474 if (format
== V_028C70_COLOR_INVALID
) {
2475 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2477 assert(format
!= V_028C70_COLOR_INVALID
);
2478 swap
= si_translate_colorswap(surf
->base
.format
, false);
2479 endian
= si_colorformat_endian_swap(format
);
2481 /* blend clamp should be set for all NORM/SRGB types */
2482 if (ntype
== V_028C70_NUMBER_UNORM
||
2483 ntype
== V_028C70_NUMBER_SNORM
||
2484 ntype
== V_028C70_NUMBER_SRGB
)
2487 /* set blend bypass according to docs if SINT/UINT or
2488 8/24 COLOR variants */
2489 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2490 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2491 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2496 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2497 if (format
== V_028C70_COLOR_8
||
2498 format
== V_028C70_COLOR_8_8
||
2499 format
== V_028C70_COLOR_8_8_8_8
)
2500 surf
->color_is_int8
= true;
2501 else if (format
== V_028C70_COLOR_10_10_10_2
||
2502 format
== V_028C70_COLOR_2_10_10_10
)
2503 surf
->color_is_int10
= true;
2506 color_info
= S_028C70_FORMAT(format
) |
2507 S_028C70_COMP_SWAP(swap
) |
2508 S_028C70_BLEND_CLAMP(blend_clamp
) |
2509 S_028C70_BLEND_BYPASS(blend_bypass
) |
2510 S_028C70_SIMPLE_FLOAT(1) |
2511 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2512 ntype
!= V_028C70_NUMBER_SNORM
&&
2513 ntype
!= V_028C70_NUMBER_SRGB
&&
2514 format
!= V_028C70_COLOR_8_24
&&
2515 format
!= V_028C70_COLOR_24_8
) |
2516 S_028C70_NUMBER_TYPE(ntype
) |
2517 S_028C70_ENDIAN(endian
);
2519 /* Intensity is implemented as Red, so treat it that way. */
2520 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2521 util_format_is_intensity(surf
->base
.format
));
2523 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2524 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2525 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2527 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2528 S_028C74_NUM_FRAGMENTS(log_fragments
);
2530 if (tex
->fmask_offset
) {
2531 color_info
|= S_028C70_COMPRESSION(1);
2532 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2534 if (sctx
->chip_class
== GFX6
) {
2535 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2536 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2541 if (sctx
->chip_class
>= GFX10
) {
2542 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2544 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2545 64 for APU because all of our APUs to date use DIMMs which have
2546 a request granularity size of 64B while all other chips have a
2548 if (!sctx
->screen
->info
.has_dedicated_vram
)
2549 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2551 surf
->cb_dcc_control
=
2552 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2553 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2554 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2555 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2556 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2557 } else if (sctx
->chip_class
>= GFX8
) {
2558 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2559 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2561 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2562 64 for APU because all of our APUs to date use DIMMs which have
2563 a request granularity size of 64B while all other chips have a
2565 if (!sctx
->screen
->info
.has_dedicated_vram
)
2566 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2568 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2569 if (tex
->surface
.bpe
== 1)
2570 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2571 else if (tex
->surface
.bpe
== 2)
2572 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2575 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2576 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2577 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2580 /* This must be set for fast clear to work without FMASK. */
2581 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2582 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2583 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2586 /* GFX10 field has the same base shift as the GFX6 field */
2587 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2588 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2589 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2591 if (sctx
->chip_class
>= GFX10
) {
2592 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2594 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2595 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2596 S_028EE0_RESOURCE_LEVEL(1);
2597 } else if (sctx
->chip_class
== GFX9
) {
2598 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2599 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2600 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2603 if (sctx
->chip_class
>= GFX9
) {
2604 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2605 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2606 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2609 surf
->cb_color_view
= color_view
;
2610 surf
->cb_color_info
= color_info
;
2611 surf
->cb_color_attrib
= color_attrib
;
2613 /* Determine pixel shader export format */
2614 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2616 surf
->color_initialized
= true;
2619 static void si_init_depth_surface(struct si_context
*sctx
,
2620 struct si_surface
*surf
)
2622 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2623 unsigned level
= surf
->base
.u
.tex
.level
;
2624 unsigned format
, stencil_format
;
2625 uint32_t z_info
, s_info
;
2627 format
= si_translate_dbformat(tex
->db_render_format
);
2628 stencil_format
= tex
->surface
.has_stencil
?
2629 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2631 assert(format
!= V_028040_Z_INVALID
);
2632 if (format
== V_028040_Z_INVALID
)
2633 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2635 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2636 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2637 surf
->db_htile_data_base
= 0;
2638 surf
->db_htile_surface
= 0;
2640 if (sctx
->chip_class
>= GFX10
) {
2641 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2642 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2645 if (sctx
->chip_class
>= GFX9
) {
2646 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2647 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2648 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2649 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2650 z_info
= S_028038_FORMAT(format
) |
2651 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2652 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2653 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2654 s_info
= S_02803C_FORMAT(stencil_format
) |
2655 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2657 if (sctx
->chip_class
== GFX9
) {
2658 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2659 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2661 surf
->db_depth_view
|= S_028008_MIPID(level
);
2662 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2663 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2665 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2666 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2667 S_028038_ALLOW_EXPCLEAR(1);
2669 if (tex
->tc_compatible_htile
) {
2670 unsigned max_zplanes
= 4;
2672 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2673 tex
->buffer
.b
.b
.nr_samples
> 1)
2676 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2678 if (sctx
->chip_class
>= GFX10
) {
2679 z_info
|= S_028040_ITERATE_FLUSH(1);
2680 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2682 z_info
|= S_028038_ITERATE_FLUSH(1);
2683 s_info
|= S_02803C_ITERATE_FLUSH(1);
2687 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2688 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2689 * See that for explanation.
2691 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2693 /* Use all HTILE for depth if there's no stencil. */
2694 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2697 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2698 tex
->htile_offset
) >> 8;
2699 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2700 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2701 if (sctx
->chip_class
== GFX9
) {
2702 surf
->db_htile_surface
|=
2703 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2708 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2710 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2712 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2713 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2714 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2715 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2717 z_info
= S_028040_FORMAT(format
) |
2718 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2719 s_info
= S_028044_FORMAT(stencil_format
);
2720 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2722 if (sctx
->chip_class
>= GFX7
) {
2723 struct radeon_info
*info
= &sctx
->screen
->info
;
2724 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2725 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2726 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2727 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2728 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2729 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2731 surf
->db_depth_info
|=
2732 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2733 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2734 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2735 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2736 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2737 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2738 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2739 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2741 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2742 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2743 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2744 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2747 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2748 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2749 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2750 levelinfo
->nblk_y
) / 64 - 1);
2752 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2753 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2754 S_028040_ALLOW_EXPCLEAR(1);
2756 if (tex
->surface
.has_stencil
) {
2757 /* Workaround: For a not yet understood reason, the
2758 * combination of MSAA, fast stencil clear and stencil
2759 * decompress messes with subsequent stencil buffer
2760 * uses. Problem was reproduced on Verde, Bonaire,
2761 * Tonga, and Carrizo.
2763 * Disabling EXPCLEAR works around the problem.
2765 * Check piglit's arb_texture_multisample-stencil-clear
2766 * test if you want to try changing this.
2768 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2769 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2770 } else if (!tex
->tc_compatible_htile
) {
2771 /* Use all of the htile_buffer for depth if there's no stencil.
2772 * This must not be set when TC-compatible HTILE is enabled
2775 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2778 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2779 tex
->htile_offset
) >> 8;
2780 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2782 if (tex
->tc_compatible_htile
) {
2783 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2785 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2786 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2787 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2788 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2789 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2791 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2796 surf
->db_z_info
= z_info
;
2797 surf
->db_stencil_info
= s_info
;
2799 surf
->depth_initialized
= true;
2802 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2804 if (sctx
->decompression_enabled
)
2807 if (sctx
->framebuffer
.state
.zsbuf
) {
2808 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2809 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2811 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2813 if (tex
->surface
.has_stencil
)
2814 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2817 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2818 while (compressed_cb_mask
) {
2819 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2820 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2821 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2823 if (tex
->fmask_offset
)
2824 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2825 if (tex
->dcc_gather_statistics
)
2826 tex
->separate_dcc_dirty
= true;
2830 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2832 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2833 struct si_surface
*surf
= NULL
;
2834 struct si_texture
*tex
;
2836 if (!state
->cbufs
[i
])
2838 surf
= (struct si_surface
*)state
->cbufs
[i
];
2839 tex
= (struct si_texture
*)surf
->base
.texture
;
2841 p_atomic_dec(&tex
->framebuffers_bound
);
2845 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2846 const struct pipe_framebuffer_state
*state
)
2848 struct si_context
*sctx
= (struct si_context
*)ctx
;
2849 struct si_surface
*surf
= NULL
;
2850 struct si_texture
*tex
;
2851 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2852 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2853 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2854 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2855 bool old_has_stencil
=
2857 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2858 bool unbound
= false;
2861 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2862 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2863 * We could implement the full workaround here, but it's a useless case.
2865 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2866 unreachable("the framebuffer shouldn't have zero area");
2870 si_update_fb_dirtiness_after_rendering(sctx
);
2872 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2873 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2876 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2877 if (tex
->dcc_gather_statistics
)
2878 vi_separate_dcc_stop_query(sctx
, tex
);
2881 /* Disable DCC if the formats are incompatible. */
2882 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2883 if (!state
->cbufs
[i
])
2886 surf
= (struct si_surface
*)state
->cbufs
[i
];
2887 tex
= (struct si_texture
*)surf
->base
.texture
;
2889 if (!surf
->dcc_incompatible
)
2892 /* Since the DCC decompression calls back into set_framebuffer-
2893 * _state, we need to unbind the framebuffer, so that
2894 * vi_separate_dcc_stop_query isn't called twice with the same
2898 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2902 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2903 if (!si_texture_disable_dcc(sctx
, tex
))
2904 si_decompress_dcc(sctx
, tex
);
2906 surf
->dcc_incompatible
= false;
2909 /* Only flush TC when changing the framebuffer state, because
2910 * the only client not using TC that can change textures is
2913 * Wait for compute shaders because of possible transitions:
2914 * - FB write -> shader read
2915 * - shader write -> FB read
2917 * DB caches are flushed on demand (using si_decompress_textures).
2919 * When MSAA is enabled, CB and TC caches are flushed on demand
2920 * (after FMASK decompression). Shader write -> FB read transitions
2921 * cannot happen for MSAA textures, because MSAA shader images are
2924 * Only flush and wait for CB if there is actually a bound color buffer.
2926 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2927 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2928 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2929 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2932 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2934 /* u_blitter doesn't invoke depth decompression when it does multiple
2935 * blits in a row, but the only case when it matters for DB is when
2936 * doing generate_mipmap. So here we flush DB manually between
2937 * individual generate_mipmap blits.
2938 * Note that lower mipmap levels aren't compressed.
2940 if (sctx
->generate_mipmap_for_depth
) {
2941 si_make_DB_shader_coherent(sctx
, 1, false,
2942 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2943 } else if (sctx
->chip_class
== GFX9
) {
2944 /* It appears that DB metadata "leaks" in a sequence of:
2946 * - DCC decompress for shader image writes (with DB disabled)
2947 * - render with DEPTH_BEFORE_SHADER=1
2948 * Flushing DB metadata works around the problem.
2950 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2953 /* Take the maximum of the old and new count. If the new count is lower,
2954 * dirtying is needed to disable the unbound colorbuffers.
2956 sctx
->framebuffer
.dirty_cbufs
|=
2957 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2958 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2960 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2961 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2963 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2964 sctx
->framebuffer
.spi_shader_col_format
= 0;
2965 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2966 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2967 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2968 sctx
->framebuffer
.color_is_int8
= 0;
2969 sctx
->framebuffer
.color_is_int10
= 0;
2971 sctx
->framebuffer
.compressed_cb_mask
= 0;
2972 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2973 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2974 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2975 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2976 sctx
->framebuffer
.any_dst_linear
= false;
2977 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2978 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2979 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2980 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2982 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2983 if (!state
->cbufs
[i
])
2986 surf
= (struct si_surface
*)state
->cbufs
[i
];
2987 tex
= (struct si_texture
*)surf
->base
.texture
;
2989 if (!surf
->color_initialized
) {
2990 si_initialize_color_surface(sctx
, surf
);
2993 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2994 sctx
->framebuffer
.spi_shader_col_format
|=
2995 surf
->spi_shader_col_format
<< (i
* 4);
2996 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2997 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2998 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2999 surf
->spi_shader_col_format_blend
<< (i
* 4);
3000 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
3001 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
3003 if (surf
->color_is_int8
)
3004 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
3005 if (surf
->color_is_int10
)
3006 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
3008 if (tex
->fmask_offset
)
3009 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3011 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
3013 /* Don't update nr_color_samples for non-AA buffers.
3014 * (e.g. destination of MSAA resolve)
3016 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
3017 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
3018 sctx
->framebuffer
.nr_color_samples
=
3019 MIN2(sctx
->framebuffer
.nr_color_samples
,
3020 tex
->buffer
.b
.b
.nr_storage_samples
);
3021 sctx
->framebuffer
.nr_color_samples
=
3022 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
3025 if (tex
->surface
.is_linear
)
3026 sctx
->framebuffer
.any_dst_linear
= true;
3028 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
3029 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
3031 if (sctx
->chip_class
>= GFX9
&&
3032 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
3033 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
3036 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3038 p_atomic_inc(&tex
->framebuffers_bound
);
3040 if (tex
->dcc_gather_statistics
) {
3041 /* Dirty tracking must be enabled for DCC usage analysis. */
3042 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3043 vi_separate_dcc_start_query(sctx
, tex
);
3046 /* Update the minimum but don't keep 0. */
3047 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3048 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3049 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
3052 /* For optimal DCC performance. */
3053 if (sctx
->chip_class
>= GFX10
)
3054 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
3056 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
3058 struct si_texture
*zstex
= NULL
;
3061 surf
= (struct si_surface
*)state
->zsbuf
;
3062 zstex
= (struct si_texture
*)surf
->base
.texture
;
3064 if (!surf
->depth_initialized
) {
3065 si_init_depth_surface(sctx
, surf
);
3068 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
,
3070 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
3072 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3074 /* Update the minimum but don't keep 0. */
3075 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3076 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3077 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
3080 si_update_ps_colorbuf0_slot(sctx
);
3081 si_update_poly_offset_state(sctx
);
3082 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3083 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
3085 if (sctx
->screen
->dpbb_allowed
)
3086 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3088 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
3089 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3091 if (sctx
->screen
->has_out_of_order_rast
&&
3092 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
3093 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
3094 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
3095 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3097 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
3098 struct pipe_constant_buffer constbuf
= {0};
3100 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3101 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3103 constbuf
.buffer
= sctx
->sample_pos_buffer
;
3105 /* Set sample locations as fragment shader constants. */
3106 switch (sctx
->framebuffer
.nr_samples
) {
3108 constbuf
.buffer_offset
= 0;
3111 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
3112 (ubyte
*)sctx
->sample_positions
.x1
;
3115 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
3116 (ubyte
*)sctx
->sample_positions
.x1
;
3119 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
3120 (ubyte
*)sctx
->sample_positions
.x1
;
3123 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3124 (ubyte
*)sctx
->sample_positions
.x1
;
3127 PRINT_ERR("Requested an invalid number of samples %i.\n",
3128 sctx
->framebuffer
.nr_samples
);
3131 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3132 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3134 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3137 sctx
->do_update_shaders
= true;
3139 if (!sctx
->decompression_enabled
) {
3140 /* Prevent textures decompression when the framebuffer state
3141 * changes come from the decompression passes themselves.
3143 sctx
->need_check_render_feedback
= true;
3147 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3149 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3150 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3151 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3152 struct si_texture
*tex
= NULL
;
3153 struct si_surface
*cb
= NULL
;
3154 unsigned cb_color_info
= 0;
3157 for (i
= 0; i
< nr_cbufs
; i
++) {
3158 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3159 unsigned cb_color_attrib
;
3161 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3164 cb
= (struct si_surface
*)state
->cbufs
[i
];
3166 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3167 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3171 tex
= (struct si_texture
*)cb
->base
.texture
;
3172 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3173 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3174 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3175 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3176 RADEON_PRIO_COLOR_BUFFER
);
3178 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3179 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3180 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3181 RADEON_PRIO_SEPARATE_META
);
3184 if (tex
->dcc_separate_buffer
)
3185 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3186 tex
->dcc_separate_buffer
,
3187 RADEON_USAGE_READWRITE
,
3188 RADEON_PRIO_SEPARATE_META
);
3190 /* Compute mutable surface parameters. */
3191 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3193 cb_color_cmask
= tex
->cmask_base_address_reg
;
3195 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3196 cb_color_attrib
= cb
->cb_color_attrib
;
3198 if (cb
->base
.u
.tex
.level
> 0)
3199 cb_color_info
&= C_028C70_FAST_CLEAR
;
3201 if (tex
->fmask_offset
) {
3202 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3203 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3207 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3208 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3209 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3210 state
->cbufs
[1] == &cb
->base
&&
3211 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3213 if (!is_msaa_resolve_dst
)
3214 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3216 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3217 tex
->dcc_offset
) >> 8;
3219 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3220 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3221 cb_dcc_base
|= dcc_tile_swizzle
;
3224 if (sctx
->chip_class
>= GFX10
) {
3225 unsigned cb_color_attrib3
;
3227 /* Set mutable surface parameters. */
3228 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3229 cb_color_base
|= tex
->surface
.tile_swizzle
;
3230 if (!tex
->fmask_offset
)
3231 cb_color_fmask
= cb_color_base
;
3232 if (cb
->base
.u
.tex
.level
> 0)
3233 cb_color_cmask
= cb_color_base
;
3235 cb_color_attrib3
= cb
->cb_color_attrib3
|
3236 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3237 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3238 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3239 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3241 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3242 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3243 radeon_emit(cs
, 0); /* hole */
3244 radeon_emit(cs
, 0); /* hole */
3245 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3246 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3247 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3248 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3249 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3250 radeon_emit(cs
, 0); /* hole */
3251 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3252 radeon_emit(cs
, 0); /* hole */
3253 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3254 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3255 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3257 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4,
3258 cb_color_base
>> 32);
3259 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3260 cb_color_cmask
>> 32);
3261 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3262 cb_color_fmask
>> 32);
3263 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4,
3265 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4,
3266 cb
->cb_color_attrib2
);
3267 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4,
3269 } else if (sctx
->chip_class
== GFX9
) {
3270 struct gfx9_surf_meta_flags meta
;
3272 if (tex
->dcc_offset
)
3273 meta
= tex
->surface
.u
.gfx9
.dcc
;
3275 meta
= tex
->surface
.u
.gfx9
.cmask
;
3277 /* Set mutable surface parameters. */
3278 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3279 cb_color_base
|= tex
->surface
.tile_swizzle
;
3280 if (!tex
->fmask_offset
)
3281 cb_color_fmask
= cb_color_base
;
3282 if (cb
->base
.u
.tex
.level
> 0)
3283 cb_color_cmask
= cb_color_base
;
3284 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3285 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3286 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3287 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3289 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3290 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3291 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3292 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3293 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3294 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3295 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3296 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3297 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3298 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3299 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3300 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3301 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3302 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3303 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3304 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3306 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3307 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3309 /* Compute mutable surface parameters (GFX6-GFX8). */
3310 const struct legacy_surf_level
*level_info
=
3311 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3312 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3313 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3315 cb_color_base
+= level_info
->offset
>> 8;
3316 /* Only macrotiled modes can set tile swizzle. */
3317 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3318 cb_color_base
|= tex
->surface
.tile_swizzle
;
3320 if (!tex
->fmask_offset
)
3321 cb_color_fmask
= cb_color_base
;
3322 if (cb
->base
.u
.tex
.level
> 0)
3323 cb_color_cmask
= cb_color_base
;
3325 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3327 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3328 slice_tile_max
= level_info
->nblk_x
*
3329 level_info
->nblk_y
/ 64 - 1;
3330 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3332 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3333 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3334 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3336 if (tex
->fmask_offset
) {
3337 if (sctx
->chip_class
>= GFX7
)
3338 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3339 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3340 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3342 /* This must be set for fast clear to work without FMASK. */
3343 if (sctx
->chip_class
>= GFX7
)
3344 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3345 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3346 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3349 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3350 sctx
->chip_class
>= GFX8
? 14 : 13);
3351 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3352 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3353 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3354 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3355 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3356 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3357 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3358 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3359 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3360 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3361 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3362 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3363 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3365 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3366 radeon_emit(cs
, cb_dcc_base
);
3370 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3371 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3374 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3375 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3376 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3378 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3379 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3380 zb
->base
.texture
->nr_samples
> 1 ?
3381 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3382 RADEON_PRIO_DEPTH_BUFFER
);
3384 if (sctx
->chip_class
>= GFX10
) {
3385 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3386 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3388 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3389 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3390 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3391 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3392 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3393 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3394 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3395 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3396 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3398 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3399 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3400 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3401 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3402 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3403 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3404 } else if (sctx
->chip_class
== GFX9
) {
3405 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3406 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3407 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3408 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3410 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3411 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3412 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3413 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3414 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3415 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3416 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3417 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3418 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3419 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3420 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3421 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3423 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3424 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3425 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3427 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3429 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3430 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3431 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3432 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3433 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3434 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3435 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3436 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3437 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3438 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3439 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3442 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3443 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3444 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3446 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3447 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3448 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3449 if (sctx
->chip_class
== GFX9
)
3450 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3452 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3454 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3455 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3458 /* Framebuffer dimensions. */
3459 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3460 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3461 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3463 if (sctx
->screen
->dfsm_allowed
) {
3464 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3465 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3468 sctx
->framebuffer
.dirty_cbufs
= 0;
3469 sctx
->framebuffer
.dirty_zsbuf
= false;
3472 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3474 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3475 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3476 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3477 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3479 /* Smoothing (only possible with nr_samples == 1) uses the same
3480 * sample locations as the MSAA it simulates.
3482 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3483 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3485 /* On Polaris, the small primitive filter uses the sample locations
3486 * even when MSAA is off, so we need to make sure they're set to 0.
3488 * GFX10 uses sample locations unconditionally, so they always need
3491 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
||
3492 sctx
->chip_class
>= GFX10
) &&
3493 nr_samples
!= sctx
->sample_locs_num_samples
) {
3494 sctx
->sample_locs_num_samples
= nr_samples
;
3495 si_emit_sample_locations(cs
, nr_samples
);
3498 if (sctx
->family
>= CHIP_POLARIS10
) {
3499 unsigned small_prim_filter_cntl
=
3500 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3502 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3504 /* The alternative of setting sample locations to 0 would
3505 * require a DB flush to avoid Z errors, see
3506 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3508 if (has_msaa_sample_loc_bug
&&
3509 sctx
->framebuffer
.nr_samples
> 1 &&
3510 !rs
->multisample_enable
)
3511 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3513 radeon_opt_set_context_reg(sctx
,
3514 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3515 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3516 small_prim_filter_cntl
);
3519 /* The exclusion bits can be set to improve rasterization efficiency
3520 * if no sample lies on the pixel boundary (-8 sample offset).
3522 bool exclusion
= sctx
->chip_class
>= GFX7
&&
3523 (!rs
->multisample_enable
|| nr_samples
!= 16);
3524 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3525 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3526 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3527 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3530 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3532 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3533 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3535 if (!sctx
->screen
->has_out_of_order_rast
)
3538 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3541 colormask
&= blend
->cb_target_enabled_4bit
;
3546 /* Conservative: No logic op. */
3547 if (colormask
&& blend
->logicop_enable
)
3550 struct si_dsa_order_invariance dsa_order_invariant
= {
3551 .zs
= true, .pass_set
= true, .pass_last
= false
3554 if (sctx
->framebuffer
.state
.zsbuf
) {
3555 struct si_texture
*zstex
=
3556 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3557 bool has_stencil
= zstex
->surface
.has_stencil
;
3558 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3559 if (!dsa_order_invariant
.zs
)
3562 /* The set of PS invocations is always order invariant,
3563 * except when early Z/S tests are requested. */
3564 if (sctx
->ps_shader
.cso
&&
3565 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3566 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3567 !dsa_order_invariant
.pass_set
)
3570 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3571 !dsa_order_invariant
.pass_set
)
3578 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3581 /* Only commutative blending. */
3582 if (blendmask
& ~blend
->commutative_4bit
)
3585 if (!dsa_order_invariant
.pass_set
)
3589 if (colormask
& ~blendmask
) {
3590 if (!dsa_order_invariant
.pass_last
)
3597 static void si_emit_msaa_config(struct si_context
*sctx
)
3599 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3600 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3601 /* 33% faster rendering to linear color buffers */
3602 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3603 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3604 unsigned sc_mode_cntl_1
=
3605 S_028A4C_WALK_SIZE(dst_is_linear
) |
3606 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3607 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3608 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3609 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3611 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3612 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3613 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3614 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3615 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3616 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3617 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3618 S_028804_INCOHERENT_EQAA_READS(1) |
3619 S_028804_INTERPOLATE_COMP_Z(1) |
3620 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3621 unsigned coverage_samples
, color_samples
, z_samples
;
3622 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3624 /* S: Coverage samples (up to 16x):
3625 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3626 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3628 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3629 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3630 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3631 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3632 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3635 * F: Color samples (up to 8x, must be <= coverage samples):
3636 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3637 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3639 * Can be anything between coverage and color samples:
3640 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3641 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3642 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3643 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3644 * # All are currently set the same as coverage samples.
3646 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3647 * flag for undefined color samples. A shader-based resolve must handle unknowns
3648 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3649 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3650 * useful. The CB resolve always drops unknowns.
3652 * Sensible AA configurations:
3653 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3654 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3655 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3656 * EQAA 8s 8z 8f = 8x MSAA
3657 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3658 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3659 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3660 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3661 * EQAA 4s 4z 4f = 4x MSAA
3662 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3663 * EQAA 2s 2z 2f = 2x MSAA
3665 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3666 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3667 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3669 if (sctx
->framebuffer
.state
.zsbuf
) {
3670 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3671 z_samples
= MAX2(1, z_samples
);
3673 z_samples
= coverage_samples
;
3675 } else if (sctx
->smoothing_enabled
) {
3676 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3678 coverage_samples
= color_samples
= z_samples
= 1;
3681 /* Required by OpenGL line rasterization.
3683 * TODO: We should also enable perpendicular endcaps for AA lines,
3684 * but that requires implementing line stippling in the pixel
3685 * shader. SC can only do line stippling with axis-aligned
3688 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3689 unsigned sc_aa_config
= 0;
3691 if (coverage_samples
> 1) {
3692 /* distance from the pixel center, indexed by log2(nr_samples) */
3693 static unsigned max_dist
[] = {
3700 unsigned log_samples
= util_logbase2(coverage_samples
);
3701 unsigned log_z_samples
= util_logbase2(z_samples
);
3702 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3703 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3705 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3706 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3707 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3708 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3710 if (sctx
->framebuffer
.nr_samples
> 1) {
3711 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3712 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3713 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3714 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3715 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3716 } else if (sctx
->smoothing_enabled
) {
3717 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3721 unsigned initial_cdw
= cs
->current
.cdw
;
3723 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3724 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3725 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3727 /* R_028804_DB_EQAA */
3728 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3730 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3731 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3732 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3734 if (initial_cdw
!= cs
->current
.cdw
) {
3735 sctx
->context_roll
= true;
3737 /* GFX9: Flush DFSM when the AA mode changes. */
3738 if (sctx
->screen
->dfsm_allowed
) {
3739 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3740 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3745 void si_update_ps_iter_samples(struct si_context
*sctx
)
3747 if (sctx
->framebuffer
.nr_samples
> 1)
3748 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3749 if (sctx
->screen
->dpbb_allowed
)
3750 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3753 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3755 struct si_context
*sctx
= (struct si_context
*)ctx
;
3757 /* The hardware can only do sample shading with 2^n samples. */
3758 min_samples
= util_next_power_of_two(min_samples
);
3760 if (sctx
->ps_iter_samples
== min_samples
)
3763 sctx
->ps_iter_samples
= min_samples
;
3764 sctx
->do_update_shaders
= true;
3766 si_update_ps_iter_samples(sctx
);
3774 * Build the sampler view descriptor for a buffer texture.
3775 * @param state 256-bit descriptor; only the high 128 bits are filled in
3778 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3779 enum pipe_format format
,
3780 unsigned offset
, unsigned size
,
3783 const struct util_format_description
*desc
;
3785 unsigned num_records
;
3787 desc
= util_format_description(format
);
3788 stride
= desc
->block
.bits
/ 8;
3790 num_records
= size
/ stride
;
3791 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3793 /* The NUM_RECORDS field has a different meaning depending on the chip,
3794 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3797 * - If STRIDE == 0, it's in byte units.
3798 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3801 * - For SMEM and STRIDE == 0, it's in byte units.
3802 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3803 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3804 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3805 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3806 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3807 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3808 * That way the same descriptor can be used by both SMEM and VMEM.
3811 * - For SMEM and STRIDE == 0, it's in byte units.
3812 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3813 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3814 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3816 if (screen
->info
.chip_class
== GFX9
&& HAVE_LLVM
< 0x0800)
3817 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3818 * from STRIDE to bytes. This works around it by setting
3819 * NUM_RECORDS to at least the size of one element, so that
3820 * the first element is readable when IDXEN == 0.
3822 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3823 else if (screen
->info
.chip_class
== GFX8
)
3824 num_records
*= stride
;
3827 state
[5] = S_008F04_STRIDE(stride
);
3828 state
[6] = num_records
;
3829 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3830 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3831 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3832 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3834 if (screen
->info
.chip_class
>= GFX10
) {
3835 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3837 /* OOB_SELECT chooses the out-of-bounds check:
3838 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3839 * - 1: index >= NUM_RECORDS
3840 * - 2: NUM_RECORDS == 0
3841 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3842 * else: swizzle_address >= NUM_RECORDS
3844 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3845 S_008F0C_OOB_SELECT(0) |
3846 S_008F0C_RESOURCE_LEVEL(1);
3849 unsigned num_format
, data_format
;
3851 first_non_void
= util_format_get_first_non_void_channel(format
);
3852 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3853 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3855 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) |
3856 S_008F0C_DATA_FORMAT(data_format
);
3860 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3862 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3864 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3865 /* For the pre-defined border color values (white, opaque
3866 * black, transparent black), the only thing that matters is
3867 * that the alpha channel winds up in the correct place
3868 * (because the RGB channels are all the same) so either of
3869 * these enumerations will work.
3871 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3872 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3874 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3875 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3876 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3877 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3879 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3880 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3881 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3882 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3883 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3890 * Build the sampler view descriptor for a texture.
3893 gfx10_make_texture_descriptor(struct si_screen
*screen
,
3894 struct si_texture
*tex
,
3896 enum pipe_texture_target target
,
3897 enum pipe_format pipe_format
,
3898 const unsigned char state_swizzle
[4],
3899 unsigned first_level
, unsigned last_level
,
3900 unsigned first_layer
, unsigned last_layer
,
3901 unsigned width
, unsigned height
, unsigned depth
,
3903 uint32_t *fmask_state
)
3905 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3906 const struct util_format_description
*desc
;
3907 unsigned img_format
;
3908 unsigned char swizzle
[4];
3912 desc
= util_format_description(pipe_format
);
3913 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3915 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3916 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3917 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3918 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3919 bool is_stencil
= false;
3921 switch (pipe_format
) {
3922 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3923 case PIPE_FORMAT_X32_S8X24_UINT
:
3924 case PIPE_FORMAT_X8Z24_UNORM
:
3925 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3928 case PIPE_FORMAT_X24S8_UINT
:
3930 * X24S8 is implemented as an 8_8_8_8 data format, to
3931 * fix texture gathers. This affects at least
3932 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3934 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3938 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3939 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3942 if (tex
->upgraded_depth
&& !is_stencil
) {
3943 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3944 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3947 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3951 (res
->target
== PIPE_TEXTURE_CUBE
||
3952 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3953 /* For the purpose of shader images, treat cube maps as 2D
3956 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3958 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3961 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3963 depth
= res
->array_size
;
3964 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3965 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3966 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3967 depth
= res
->array_size
;
3968 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3969 depth
= res
->array_size
/ 6;
3972 state
[1] = S_00A004_FORMAT(img_format
) |
3973 S_00A004_WIDTH_LO(width
- 1);
3974 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
3975 S_00A008_HEIGHT(height
- 1) |
3976 S_00A008_RESOURCE_LEVEL(1);
3977 state
[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3978 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3979 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3980 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3981 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ?
3983 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ?
3984 util_logbase2(res
->nr_samples
) :
3986 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) |
3987 S_00A00C_TYPE(type
);
3988 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3989 * to know the total number of layers.
3991 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
)
3992 ? depth
- 1 : last_layer
) |
3993 S_00A010_BASE_ARRAY(first_layer
);
3994 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3995 S_00A014_MAX_MIP(res
->nr_samples
> 1 ?
3996 util_logbase2(res
->nr_samples
) :
3997 tex
->buffer
.b
.b
.last_level
) |
3998 S_00A014_PERF_MOD(4);
4002 if (tex
->dcc_offset
) {
4003 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
4004 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
4005 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4008 /* Initialize the sampler view for FMASK. */
4009 if (tex
->fmask_offset
) {
4012 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4014 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4015 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4017 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
4020 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
4023 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
4026 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
4029 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
4032 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
4035 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
4038 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
4041 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
4044 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
4047 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
4050 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
4053 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
4056 unreachable("invalid nr_samples");
4059 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4060 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
4061 S_00A004_FORMAT(format
) |
4062 S_00A004_WIDTH_LO(width
- 1);
4063 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
4064 S_00A008_HEIGHT(height
- 1) |
4065 S_00A008_RESOURCE_LEVEL(1);
4066 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4067 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4068 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4069 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4070 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4071 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4072 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
4073 S_00A010_BASE_ARRAY(first_layer
);
4075 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
4081 * Build the sampler view descriptor for a texture (SI-GFX9).
4084 si_make_texture_descriptor(struct si_screen
*screen
,
4085 struct si_texture
*tex
,
4087 enum pipe_texture_target target
,
4088 enum pipe_format pipe_format
,
4089 const unsigned char state_swizzle
[4],
4090 unsigned first_level
, unsigned last_level
,
4091 unsigned first_layer
, unsigned last_layer
,
4092 unsigned width
, unsigned height
, unsigned depth
,
4094 uint32_t *fmask_state
)
4096 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
4097 const struct util_format_description
*desc
;
4098 unsigned char swizzle
[4];
4100 unsigned num_format
, data_format
, type
, num_samples
;
4103 desc
= util_format_description(pipe_format
);
4105 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
4106 MAX2(1, res
->nr_samples
) :
4107 MAX2(1, res
->nr_storage_samples
);
4109 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
4110 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
4111 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
4112 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
4114 switch (pipe_format
) {
4115 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4116 case PIPE_FORMAT_X32_S8X24_UINT
:
4117 case PIPE_FORMAT_X8Z24_UNORM
:
4118 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4120 case PIPE_FORMAT_X24S8_UINT
:
4122 * X24S8 is implemented as an 8_8_8_8 data format, to
4123 * fix texture gathers. This affects at least
4124 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4126 if (screen
->info
.chip_class
<= GFX8
)
4127 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
4129 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4132 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
4135 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
4138 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
4140 switch (pipe_format
) {
4141 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4142 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4145 if (first_non_void
< 0) {
4146 if (util_format_is_compressed(pipe_format
)) {
4147 switch (pipe_format
) {
4148 case PIPE_FORMAT_DXT1_SRGB
:
4149 case PIPE_FORMAT_DXT1_SRGBA
:
4150 case PIPE_FORMAT_DXT3_SRGBA
:
4151 case PIPE_FORMAT_DXT5_SRGBA
:
4152 case PIPE_FORMAT_BPTC_SRGBA
:
4153 case PIPE_FORMAT_ETC2_SRGB8
:
4154 case PIPE_FORMAT_ETC2_SRGB8A1
:
4155 case PIPE_FORMAT_ETC2_SRGBA8
:
4156 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4158 case PIPE_FORMAT_RGTC1_SNORM
:
4159 case PIPE_FORMAT_LATC1_SNORM
:
4160 case PIPE_FORMAT_RGTC2_SNORM
:
4161 case PIPE_FORMAT_LATC2_SNORM
:
4162 case PIPE_FORMAT_ETC2_R11_SNORM
:
4163 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4164 /* implies float, so use SNORM/UNORM to determine
4165 whether data is signed or not */
4166 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4167 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4170 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4173 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4174 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4176 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4178 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4179 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4181 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4183 switch (desc
->channel
[first_non_void
].type
) {
4184 case UTIL_FORMAT_TYPE_FLOAT
:
4185 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4187 case UTIL_FORMAT_TYPE_SIGNED
:
4188 if (desc
->channel
[first_non_void
].normalized
)
4189 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4190 else if (desc
->channel
[first_non_void
].pure_integer
)
4191 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4193 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4195 case UTIL_FORMAT_TYPE_UNSIGNED
:
4196 if (desc
->channel
[first_non_void
].normalized
)
4197 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4198 else if (desc
->channel
[first_non_void
].pure_integer
)
4199 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4201 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4206 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4207 if (data_format
== ~0) {
4211 /* S8 with Z32 HTILE needs a special format. */
4212 if (screen
->info
.chip_class
== GFX9
&&
4213 pipe_format
== PIPE_FORMAT_S8_UINT
&&
4214 tex
->tc_compatible_htile
)
4215 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4218 (res
->target
== PIPE_TEXTURE_CUBE
||
4219 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4220 (screen
->info
.chip_class
<= GFX8
&&
4221 res
->target
== PIPE_TEXTURE_3D
))) {
4222 /* For the purpose of shader images, treat cube maps and 3D
4223 * textures as 2D arrays. For 3D textures, the address
4224 * calculations for mipmaps are different, so we rely on the
4225 * caller to effectively disable mipmaps.
4227 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4229 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4231 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4234 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4236 depth
= res
->array_size
;
4237 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
4238 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4239 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4240 depth
= res
->array_size
;
4241 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4242 depth
= res
->array_size
/ 6;
4245 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
4246 S_008F14_NUM_FORMAT(num_format
));
4247 state
[2] = (S_008F18_WIDTH(width
- 1) |
4248 S_008F18_HEIGHT(height
- 1) |
4249 S_008F18_PERF_MOD(4));
4250 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4251 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4252 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4253 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4254 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4255 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
4256 util_logbase2(num_samples
) :
4258 S_008F1C_TYPE(type
));
4260 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4264 if (screen
->info
.chip_class
== GFX9
) {
4265 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4267 /* Depth is the the last accessible layer on Gfx9.
4268 * The hw doesn't need to know the total number of layers.
4270 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4271 state
[4] |= S_008F20_DEPTH(depth
- 1);
4273 state
[4] |= S_008F20_DEPTH(last_layer
);
4275 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4276 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
4277 util_logbase2(num_samples
) :
4278 tex
->buffer
.b
.b
.last_level
);
4280 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4281 state
[4] |= S_008F20_DEPTH(depth
- 1);
4282 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4285 if (tex
->dcc_offset
) {
4286 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4288 /* The last dword is unused by hw. The shader uses it to clear
4289 * bits in the first dword of sampler state.
4291 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4292 if (first_level
== last_level
)
4293 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4295 state
[7] = 0xffffffff;
4299 /* Initialize the sampler view for FMASK. */
4300 if (tex
->fmask_offset
) {
4301 uint32_t data_format
, num_format
;
4303 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4305 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4306 if (screen
->info
.chip_class
== GFX9
) {
4307 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4308 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4310 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4313 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4316 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4319 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4322 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4325 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4328 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4331 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4334 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4337 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4340 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4343 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4346 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4349 unreachable("invalid nr_samples");
4352 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4354 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4357 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4360 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4363 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4366 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4369 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4372 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4375 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4378 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4381 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4384 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4387 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4390 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4393 unreachable("invalid nr_samples");
4395 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4399 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4400 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
4401 S_008F14_DATA_FORMAT(data_format
) |
4402 S_008F14_NUM_FORMAT(num_format
);
4403 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
4404 S_008F18_HEIGHT(height
- 1);
4405 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4406 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4407 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4408 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4409 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4411 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4415 if (screen
->info
.chip_class
== GFX9
) {
4416 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4417 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4418 S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4419 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4420 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4422 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4423 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4424 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4425 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4431 * Create a sampler view.
4433 * @param ctx context
4434 * @param texture texture
4435 * @param state sampler view template
4436 * @param width0 width0 override (for compressed textures as int)
4437 * @param height0 height0 override (for compressed textures as int)
4438 * @param force_level set the base address to the level (for compressed textures)
4440 struct pipe_sampler_view
*
4441 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4442 struct pipe_resource
*texture
,
4443 const struct pipe_sampler_view
*state
,
4444 unsigned width0
, unsigned height0
,
4445 unsigned force_level
)
4447 struct si_context
*sctx
= (struct si_context
*)ctx
;
4448 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4449 struct si_texture
*tex
= (struct si_texture
*)texture
;
4450 unsigned base_level
, first_level
, last_level
;
4451 unsigned char state_swizzle
[4];
4452 unsigned height
, depth
, width
;
4453 unsigned last_layer
= state
->u
.tex
.last_layer
;
4454 enum pipe_format pipe_format
;
4455 const struct legacy_surf_level
*surflevel
;
4460 /* initialize base object */
4461 view
->base
= *state
;
4462 view
->base
.texture
= NULL
;
4463 view
->base
.reference
.count
= 1;
4464 view
->base
.context
= ctx
;
4467 pipe_resource_reference(&view
->base
.texture
, texture
);
4469 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4470 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4471 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4472 state
->format
== PIPE_FORMAT_S8_UINT
)
4473 view
->is_stencil_sampler
= true;
4475 /* Buffer resource. */
4476 if (texture
->target
== PIPE_BUFFER
) {
4477 si_make_buffer_descriptor(sctx
->screen
,
4478 si_resource(texture
),
4480 state
->u
.buf
.offset
,
4486 state_swizzle
[0] = state
->swizzle_r
;
4487 state_swizzle
[1] = state
->swizzle_g
;
4488 state_swizzle
[2] = state
->swizzle_b
;
4489 state_swizzle
[3] = state
->swizzle_a
;
4492 first_level
= state
->u
.tex
.first_level
;
4493 last_level
= state
->u
.tex
.last_level
;
4496 depth
= texture
->depth0
;
4498 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4499 assert(force_level
== first_level
&&
4500 force_level
== last_level
);
4501 base_level
= force_level
;
4504 width
= u_minify(width
, force_level
);
4505 height
= u_minify(height
, force_level
);
4506 depth
= u_minify(depth
, force_level
);
4509 /* This is not needed if state trackers set last_layer correctly. */
4510 if (state
->target
== PIPE_TEXTURE_1D
||
4511 state
->target
== PIPE_TEXTURE_2D
||
4512 state
->target
== PIPE_TEXTURE_RECT
||
4513 state
->target
== PIPE_TEXTURE_CUBE
)
4514 last_layer
= state
->u
.tex
.first_layer
;
4516 /* Texturing with separate depth and stencil. */
4517 pipe_format
= state
->format
;
4519 /* Depth/stencil texturing sometimes needs separate texture. */
4520 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4521 if (!tex
->flushed_depth_texture
&&
4522 !si_init_flushed_depth_texture(ctx
, texture
)) {
4523 pipe_resource_reference(&view
->base
.texture
, NULL
);
4528 assert(tex
->flushed_depth_texture
);
4530 /* Override format for the case where the flushed texture
4531 * contains only Z or only S.
4533 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4534 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4536 tex
= tex
->flushed_depth_texture
;
4539 surflevel
= tex
->surface
.u
.legacy
.level
;
4541 if (tex
->db_compatible
) {
4542 if (!view
->is_stencil_sampler
)
4543 pipe_format
= tex
->db_render_format
;
4545 switch (pipe_format
) {
4546 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4547 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4549 case PIPE_FORMAT_X8Z24_UNORM
:
4550 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4551 /* Z24 is always stored like this for DB
4554 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4556 case PIPE_FORMAT_X24S8_UINT
:
4557 case PIPE_FORMAT_S8X24_UINT
:
4558 case PIPE_FORMAT_X32_S8X24_UINT
:
4559 pipe_format
= PIPE_FORMAT_S8_UINT
;
4560 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4566 view
->dcc_incompatible
=
4567 vi_dcc_formats_are_incompatible(texture
,
4568 state
->u
.tex
.first_level
,
4571 sctx
->screen
->make_texture_descriptor(sctx
->screen
, tex
, true,
4572 state
->target
, pipe_format
, state_swizzle
,
4573 first_level
, last_level
,
4574 state
->u
.tex
.first_layer
, last_layer
,
4575 width
, height
, depth
,
4576 view
->state
, view
->fmask_state
);
4578 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4579 view
->is_integer
= false;
4581 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4582 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4585 /* Whether the number format is {U,S}{SCALED,INT} */
4587 (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4588 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4589 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4593 view
->base_level_info
= &surflevel
[base_level
];
4594 view
->base_level
= base_level
;
4595 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4599 static struct pipe_sampler_view
*
4600 si_create_sampler_view(struct pipe_context
*ctx
,
4601 struct pipe_resource
*texture
,
4602 const struct pipe_sampler_view
*state
)
4604 return si_create_sampler_view_custom(ctx
, texture
, state
,
4605 texture
? texture
->width0
: 0,
4606 texture
? texture
->height0
: 0, 0);
4609 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4610 struct pipe_sampler_view
*state
)
4612 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4614 pipe_resource_reference(&state
->texture
, NULL
);
4618 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4620 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4621 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4623 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4624 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4627 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4628 const struct pipe_sampler_state
*state
,
4629 const union pipe_color_union
*color
,
4632 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4633 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4635 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4636 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4637 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4638 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4640 #define simple_border_types(elt) \
4642 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4643 color->elt[2] == 0 && color->elt[3] == 0) \
4644 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4645 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4646 color->elt[2] == 0 && color->elt[3] == 1) \
4647 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4648 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4649 color->elt[2] == 1 && color->elt[3] == 1) \
4650 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4654 simple_border_types(ui
);
4656 simple_border_types(f
);
4658 #undef simple_border_types
4662 /* Check if the border has been uploaded already. */
4663 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4664 if (memcmp(&sctx
->border_color_table
[i
], color
,
4665 sizeof(*color
)) == 0)
4668 if (i
>= SI_MAX_BORDER_COLORS
) {
4669 /* Getting 4096 unique border colors is very unlikely. */
4670 fprintf(stderr
, "radeonsi: The border color table is full. "
4671 "Any new border colors will be just black. "
4672 "Please file a bug.\n");
4673 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4676 if (i
== sctx
->border_color_count
) {
4677 /* Upload a new border color. */
4678 memcpy(&sctx
->border_color_table
[i
], color
,
4680 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4681 color
, sizeof(*color
));
4682 sctx
->border_color_count
++;
4685 return S_008F3C_BORDER_COLOR_PTR(i
) |
4686 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4689 static inline int S_FIXED(float value
, unsigned frac_bits
)
4691 return value
* (1 << frac_bits
);
4694 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4696 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4697 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4698 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4700 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4701 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4704 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4717 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4718 const struct pipe_sampler_state
*state
)
4720 struct si_context
*sctx
= (struct si_context
*)ctx
;
4721 struct si_screen
*sscreen
= sctx
->screen
;
4722 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4723 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4724 : state
->max_anisotropy
;
4725 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4726 union pipe_color_union clamped_border_color
;
4733 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4735 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4736 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4737 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4738 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4739 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4740 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4741 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4742 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4743 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4744 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4745 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4746 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4747 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4748 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4749 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4750 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4751 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4752 S_008F38_MIP_POINT_PRECLAMP(0));
4753 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4755 if (sscreen
->info
.chip_class
>= GFX10
) {
4756 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4758 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4759 S_008F38_FILTER_PREC_FIX(1) |
4760 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4763 /* Create sampler resource for integer textures. */
4764 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4765 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4767 /* Create sampler resource for upgraded depth textures. */
4768 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4770 for (unsigned i
= 0; i
< 4; ++i
) {
4771 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4772 * when the border color is 1.0. */
4773 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4776 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4777 if (sscreen
->info
.chip_class
<= GFX9
)
4778 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4780 rstate
->upgraded_depth_val
[3] =
4781 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4787 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4789 struct si_context
*sctx
= (struct si_context
*)ctx
;
4791 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4794 sctx
->sample_mask
= sample_mask
;
4795 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4798 static void si_emit_sample_mask(struct si_context
*sctx
)
4800 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4801 unsigned mask
= sctx
->sample_mask
;
4803 /* Needed for line and polygon smoothing as well as for the Polaris
4804 * small primitive filter. We expect the state tracker to take care of
4807 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4808 (mask
& 1 && sctx
->blitter
->running
));
4810 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4811 radeon_emit(cs
, mask
| (mask
<< 16));
4812 radeon_emit(cs
, mask
| (mask
<< 16));
4815 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4818 struct si_sampler_state
*s
= state
;
4820 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4827 * Vertex elements & buffers
4830 struct si_fast_udiv_info32
4831 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4833 struct util_fast_udiv_info info
=
4834 util_compute_fast_udiv_info(D
, num_bits
, 32);
4836 struct si_fast_udiv_info32 result
= {
4845 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4847 const struct pipe_vertex_element
*elements
)
4849 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4850 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4851 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4852 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4853 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4854 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4855 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4856 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4857 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4860 assert(count
<= SI_MAX_ATTRIBS
);
4865 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4867 for (i
= 0; i
< count
; ++i
) {
4868 const struct util_format_description
*desc
;
4869 const struct util_format_channel_description
*channel
;
4871 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4873 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4878 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4879 if (instance_divisor
) {
4880 v
->uses_instance_divisors
= true;
4882 if (instance_divisor
== 1) {
4883 v
->instance_divisor_is_one
|= 1u << i
;
4885 v
->instance_divisor_is_fetched
|= 1u << i
;
4886 divisor_factors
[i
] =
4887 si_compute_fast_udiv_info32(instance_divisor
, 32);
4891 if (!used
[vbo_index
]) {
4892 v
->first_vb_use_mask
|= 1 << i
;
4893 used
[vbo_index
] = true;
4896 desc
= util_format_description(elements
[i
].src_format
);
4897 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4898 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4900 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4901 v
->src_offset
[i
] = elements
[i
].src_offset
;
4902 v
->vertex_buffer_index
[i
] = vbo_index
;
4904 bool always_fix
= false;
4905 union si_vs_fix_fetch fix_fetch
;
4906 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4909 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4912 switch (channel
->type
) {
4913 case UTIL_FORMAT_TYPE_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4914 case UTIL_FORMAT_TYPE_FIXED
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
; break;
4915 case UTIL_FORMAT_TYPE_SIGNED
: {
4916 if (channel
->pure_integer
)
4917 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4918 else if (channel
->normalized
)
4919 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4921 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4924 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4925 if (channel
->pure_integer
)
4926 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4927 else if (channel
->normalized
)
4928 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4930 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4933 default: unreachable("bad format type");
4936 switch (elements
[i
].src_format
) {
4937 case PIPE_FORMAT_R11G11B10_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4938 default: unreachable("bad other format");
4942 if (desc
->channel
[0].size
== 10) {
4943 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4944 log_hw_load_size
= 2;
4946 /* The hardware always treats the 2-bit alpha channel as
4947 * unsigned, so a shader workaround is needed. The affected
4948 * chips are GFX8 and older except Stoney (GFX8.1).
4950 always_fix
= sscreen
->info
.chip_class
<= GFX8
&&
4951 sscreen
->info
.family
!= CHIP_STONEY
&&
4952 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4953 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4954 fix_fetch
.u
.log_size
= 3; /* special encoding */
4955 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4956 log_hw_load_size
= 2;
4958 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4959 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4962 * - doubles (multiple loads + truncate to float)
4963 * - 32-bit requiring a conversion
4966 (fix_fetch
.u
.log_size
== 3) ||
4967 (fix_fetch
.u
.log_size
== 2 &&
4968 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4969 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4970 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4972 /* Also fixup 8_8_8 and 16_16_16. */
4973 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4975 log_hw_load_size
= fix_fetch
.u
.log_size
;
4979 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4980 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4981 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4982 fix_fetch
.u
.reverse
= 1;
4985 /* Force the workaround for unaligned access here already if the
4986 * offset relative to the vertex buffer base is unaligned.
4988 * There is a theoretical case in which this is too conservative:
4989 * if the vertex buffer's offset is also unaligned in just the
4990 * right way, we end up with an aligned address after all.
4991 * However, this case should be extremely rare in practice (it
4992 * won't happen in well-behaved applications), and taking it
4993 * into account would complicate the fast path (where everything
4994 * is nicely aligned).
4996 bool check_alignment
=
4997 log_hw_load_size
>= 1 &&
4998 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
== GFX10
);
4999 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
5001 if (check_alignment
&&
5002 (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
5005 if (always_fix
|| check_alignment
|| opencode
)
5006 v
->fix_fetch
[i
] = fix_fetch
.bits
;
5009 v
->fix_fetch_opencode
|= 1 << i
;
5010 if (opencode
|| always_fix
)
5011 v
->fix_fetch_always
|= 1 << i
;
5013 if (check_alignment
&& !opencode
) {
5014 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
5016 v
->fix_fetch_unaligned
|= 1 << i
;
5017 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
5018 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
5021 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
5022 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
5023 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
5024 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
5026 if (sscreen
->info
.chip_class
>= GFX10
) {
5027 const struct gfx10_format
*fmt
=
5028 &gfx10_format_table
[elements
[i
].src_format
];
5029 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
5030 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) |
5031 S_008F0C_RESOURCE_LEVEL(1);
5033 unsigned data_format
, num_format
;
5034 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
5035 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
5036 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) |
5037 S_008F0C_DATA_FORMAT(data_format
);
5041 if (v
->instance_divisor_is_fetched
) {
5042 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
5044 v
->instance_divisor_factor_buffer
=
5045 (struct si_resource
*)
5046 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
5047 num_divisors
* sizeof(divisor_factors
[0]));
5048 if (!v
->instance_divisor_factor_buffer
) {
5052 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
5053 NULL
, PIPE_TRANSFER_WRITE
);
5054 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
5059 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
5061 struct si_context
*sctx
= (struct si_context
*)ctx
;
5062 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
5063 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5065 sctx
->vertex_elements
= v
;
5066 sctx
->vertex_buffers_dirty
= true;
5070 old
->count
!= v
->count
||
5071 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
5072 /* we don't check which divisors changed */
5073 v
->uses_instance_divisors
||
5074 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) & sctx
->vertex_buffer_unaligned
||
5075 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
5076 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
5077 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
5078 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5079 * functions of fix_fetch and the src_offset alignment.
5080 * If they change and fix_fetch doesn't, it must be due to different
5081 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5082 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
5083 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
5084 sctx
->do_update_shaders
= true;
5086 if (v
&& v
->instance_divisor_is_fetched
) {
5087 struct pipe_constant_buffer cb
;
5089 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
5090 cb
.user_buffer
= NULL
;
5091 cb
.buffer_offset
= 0;
5092 cb
.buffer_size
= 0xffffffff;
5093 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
5097 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
5099 struct si_context
*sctx
= (struct si_context
*)ctx
;
5100 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5102 if (sctx
->vertex_elements
== state
)
5103 sctx
->vertex_elements
= NULL
;
5104 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
5108 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
5109 unsigned start_slot
, unsigned count
,
5110 const struct pipe_vertex_buffer
*buffers
)
5112 struct si_context
*sctx
= (struct si_context
*)ctx
;
5113 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
5114 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
5115 uint32_t unaligned
= orig_unaligned
;
5118 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
5121 for (i
= 0; i
< count
; i
++) {
5122 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
5123 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
5124 struct pipe_resource
*buf
= src
->buffer
.resource
;
5126 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
5127 dsti
->buffer_offset
= src
->buffer_offset
;
5128 dsti
->stride
= src
->stride
;
5129 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
5130 unaligned
|= 1 << (start_slot
+ i
);
5132 unaligned
&= ~(1 << (start_slot
+ i
));
5134 si_context_add_resource_size(sctx
, buf
);
5136 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
5139 for (i
= 0; i
< count
; i
++) {
5140 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
5142 unaligned
&= ~u_bit_consecutive(start_slot
, count
);
5144 sctx
->vertex_buffers_dirty
= true;
5145 sctx
->vertex_buffer_unaligned
= unaligned
;
5147 /* Check whether alignment may have changed in a way that requires
5148 * shader changes. This check is conservative: a vertex buffer can only
5149 * trigger a shader change if the misalignment amount changes (e.g.
5150 * from byte-aligned to short-aligned), but we only keep track of
5151 * whether buffers are at least dword-aligned, since that should always
5152 * be the case in well-behaved applications anyway.
5154 if (sctx
->vertex_elements
&&
5155 (sctx
->vertex_elements
->vb_alignment_check_mask
&
5156 (unaligned
| orig_unaligned
) & u_bit_consecutive(start_slot
, count
)))
5157 sctx
->do_update_shaders
= true;
5164 static void si_set_tess_state(struct pipe_context
*ctx
,
5165 const float default_outer_level
[4],
5166 const float default_inner_level
[2])
5168 struct si_context
*sctx
= (struct si_context
*)ctx
;
5169 struct pipe_constant_buffer cb
;
5172 memcpy(array
, default_outer_level
, sizeof(float) * 4);
5173 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
5176 cb
.user_buffer
= NULL
;
5177 cb
.buffer_size
= sizeof(array
);
5179 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
5180 (void*)array
, sizeof(array
),
5183 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
5184 pipe_resource_reference(&cb
.buffer
, NULL
);
5187 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5189 struct si_context
*sctx
= (struct si_context
*)ctx
;
5191 si_update_fb_dirtiness_after_rendering(sctx
);
5193 /* Multisample surfaces are flushed in si_decompress_textures. */
5194 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5195 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5196 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5197 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5201 /* This only ensures coherency for shader image/buffer stores. */
5202 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5204 struct si_context
*sctx
= (struct si_context
*)ctx
;
5206 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5209 /* Subsequent commands must wait for all shader invocations to
5211 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
5212 SI_CONTEXT_CS_PARTIAL_FLUSH
;
5214 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5215 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
|
5216 SI_CONTEXT_INV_VCACHE
;
5218 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
5219 PIPE_BARRIER_SHADER_BUFFER
|
5220 PIPE_BARRIER_TEXTURE
|
5221 PIPE_BARRIER_IMAGE
|
5222 PIPE_BARRIER_STREAMOUT_BUFFER
|
5223 PIPE_BARRIER_GLOBAL_BUFFER
)) {
5224 /* As far as I can tell, L1 contents are written back to L2
5225 * automatically at end of shader, but the contents of other
5226 * L1 caches might still be stale. */
5227 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5230 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5231 /* Indices are read through TC L2 since GFX8.
5234 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5235 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5238 /* MSAA color, any depth and any stencil are flushed in
5239 * si_decompress_textures when needed.
5241 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
5242 sctx
->framebuffer
.uncompressed_cb_mask
) {
5243 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5245 if (sctx
->chip_class
<= GFX8
)
5246 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5249 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5250 if (sctx
->screen
->info
.chip_class
<= GFX8
&&
5251 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5252 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5255 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5257 struct pipe_blend_state blend
;
5259 memset(&blend
, 0, sizeof(blend
));
5260 blend
.independent_blend_enable
= true;
5261 blend
.rt
[0].colormask
= 0xf;
5262 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5265 static void si_init_config(struct si_context
*sctx
);
5267 void si_init_state_compute_functions(struct si_context
*sctx
)
5269 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5270 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5271 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5272 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5273 sctx
->b
.memory_barrier
= si_memory_barrier
;
5276 void si_init_state_functions(struct si_context
*sctx
)
5278 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5279 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5280 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5281 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5282 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5283 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5284 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5285 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5286 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5287 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5288 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5290 sctx
->b
.create_blend_state
= si_create_blend_state
;
5291 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5292 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5293 sctx
->b
.set_blend_color
= si_set_blend_color
;
5295 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5296 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5297 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5299 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5300 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5301 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5303 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5304 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5305 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5306 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5307 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5309 sctx
->b
.set_clip_state
= si_set_clip_state
;
5310 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5312 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5314 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5316 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5317 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5318 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5319 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5321 sctx
->b
.texture_barrier
= si_texture_barrier
;
5322 sctx
->b
.set_min_samples
= si_set_min_samples
;
5323 sctx
->b
.set_tess_state
= si_set_tess_state
;
5325 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5327 si_init_config(sctx
);
5330 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5332 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5334 if (sscreen
->info
.chip_class
>= GFX10
) {
5335 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5337 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5341 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
5342 struct si_pm4_state
*pm4
, unsigned value
)
5344 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
:
5345 R_00802C_GRBM_GFX_INDEX
;
5346 si_pm4_set_reg(pm4
, reg
, value
);
5349 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
5350 struct si_pm4_state
*pm4
, unsigned se
)
5352 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5353 si_set_grbm_gfx_index(sctx
, pm4
,
5354 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5355 S_030800_SE_INDEX(se
)) |
5356 S_030800_SH_BROADCAST_WRITES(1) |
5357 S_030800_INSTANCE_BROADCAST_WRITES(1));
5361 si_write_harvested_raster_configs(struct si_context
*sctx
,
5362 struct si_pm4_state
*pm4
,
5363 unsigned raster_config
,
5364 unsigned raster_config_1
)
5366 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5367 unsigned raster_config_se
[4];
5370 ac_get_harvested_configs(&sctx
->screen
->info
,
5375 for (se
= 0; se
< num_se
; se
++) {
5376 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5377 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5379 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5381 if (sctx
->chip_class
>= GFX7
) {
5382 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5386 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5388 struct si_screen
*sscreen
= sctx
->screen
;
5389 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5390 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5391 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5392 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5394 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5395 /* Always use the default config when all backends are enabled
5396 * (or when we failed to determine the enabled backends).
5398 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
5400 if (sctx
->chip_class
>= GFX7
)
5401 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
5404 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5408 static void si_init_config(struct si_context
*sctx
)
5410 struct si_screen
*sscreen
= sctx
->screen
;
5411 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5412 bool has_clear_state
= sscreen
->has_clear_state
;
5413 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5418 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5419 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5420 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5421 si_pm4_cmd_end(pm4
, false);
5423 if (has_clear_state
) {
5424 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5425 si_pm4_cmd_add(pm4
, 0);
5426 si_pm4_cmd_end(pm4
, false);
5429 if (sctx
->chip_class
<= GFX8
)
5430 si_set_raster_config(sctx
, pm4
);
5432 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5433 if (!has_clear_state
)
5434 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5436 /* FIXME calculate these values somehow ??? */
5437 if (sctx
->chip_class
<= GFX8
) {
5438 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5439 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5442 if (!has_clear_state
) {
5443 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5444 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5445 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5448 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5449 if (!has_clear_state
)
5450 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5451 if (sctx
->chip_class
< GFX7
)
5452 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
5453 S_008A14_CLIP_VTX_REORDER_ENA(1));
5455 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5456 * I don't know why. Deduced by trial and error.
5458 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5459 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5460 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5461 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5462 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5463 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5464 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5465 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5466 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5469 if (!has_clear_state
) {
5470 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5471 S_028230_ER_TRI(0xA) |
5472 S_028230_ER_POINT(0xA) |
5473 S_028230_ER_RECT(0xA) |
5474 /* Required by DX10_DIAMOND_TEST_ENA: */
5475 S_028230_ER_LINE_LR(0x1A) |
5476 S_028230_ER_LINE_RL(0x26) |
5477 S_028230_ER_LINE_TB(0xA) |
5478 S_028230_ER_LINE_BT(0xA));
5479 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5480 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5481 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5482 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5483 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5486 if (sctx
->chip_class
>= GFX10
) {
5487 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5488 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5489 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5490 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5491 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5492 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5493 } else if (sctx
->chip_class
== GFX9
) {
5494 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5495 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5496 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5498 /* These registers, when written, also overwrite the CLEAR_STATE
5499 * context, so we can't rely on CLEAR_STATE setting them.
5500 * It would be an issue if there was another UMD changing them.
5502 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5503 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5504 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5507 if (sctx
->chip_class
>= GFX7
) {
5508 if (sctx
->chip_class
>= GFX10
) {
5509 /* Logical CUs 16 - 31 */
5510 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
5511 S_00B404_CU_EN(0xffff));
5512 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
5513 S_00B104_CU_EN(0xffff));
5514 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
5515 S_00B004_CU_EN(0xffff));
5518 if (sctx
->chip_class
>= GFX9
) {
5519 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5520 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5522 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5523 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5524 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5525 S_00B41C_WAVE_LIMIT(0x3F));
5526 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5527 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5529 /* If this is 0, Bonaire can hang even if GS isn't being used.
5530 * Other chips are unaffected. These are suboptimal values,
5531 * but we don't use on-chip GS.
5533 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5534 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5535 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5538 /* Compute LATE_ALLOC_VS.LIMIT. */
5539 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5540 unsigned late_alloc_limit
; /* The limit is per SH. */
5542 if (sctx
->family
== CHIP_KABINI
) {
5543 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5544 } else if (num_cu_per_sh
<= 4) {
5545 /* Too few available compute units per SH. Disallowing
5546 * VS to run on one CU could hurt us more than late VS
5547 * allocation would help.
5549 * 2 is the highest safe number that allows us to keep
5552 late_alloc_limit
= 2;
5554 /* This is a good initial value, allowing 1 late_alloc
5555 * wave per SIMD on num_cu - 2.
5557 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5560 unsigned cu_mask_vs
= 0xffff;
5561 unsigned cu_mask_gs
= 0xffff;
5563 if (late_alloc_limit
> 2) {
5564 if (sctx
->chip_class
>= GFX10
) {
5565 /* CU2 & CU3 disabled because of the dual CU design */
5566 cu_mask_vs
= 0xfff3;
5567 cu_mask_gs
= 0xfff3; /* NGG only */
5569 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5573 /* VS can't execute on one CU if the limit is > 2. */
5574 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5575 S_00B118_CU_EN(cu_mask_vs
) |
5576 S_00B118_WAVE_LIMIT(0x3F));
5577 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5578 S_00B11C_LIMIT(late_alloc_limit
));
5580 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5581 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5583 if (sctx
->chip_class
>= GFX10
) {
5584 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
5585 S_00B204_CU_EN(0xffff) |
5586 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit
));
5589 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5590 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5593 if (sctx
->chip_class
>= GFX10
) {
5594 /* Break up a pixel wave if it contains deallocs for more than
5595 * half the parameter cache.
5597 * To avoid a deadlock where pixel waves aren't launched
5598 * because they're waiting for more pixels while the frontend
5599 * is stuck waiting for PC space, the maximum allowed value is
5600 * the size of the PC minus the largest possible allocation for
5601 * a single primitive shader subgroup.
5603 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
,
5604 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5605 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5606 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5607 sscreen
->info
.pa_sc_tile_steering_override
);
5609 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5610 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5611 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5612 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5613 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5614 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5615 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5616 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD
));
5618 si_pm4_set_reg(pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5619 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5620 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5621 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5622 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5623 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5624 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5625 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5626 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5627 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5629 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5630 S_00B0C0_SOFT_GROUPING_EN(1) |
5631 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5632 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5636 if (sctx
->chip_class
>= GFX8
) {
5637 unsigned vgt_tess_distribution
;
5639 vgt_tess_distribution
=
5640 S_028B50_ACCUM_ISOLINE(32) |
5641 S_028B50_ACCUM_TRI(11) |
5642 S_028B50_ACCUM_QUAD(11) |
5643 S_028B50_DONUT_SPLIT(16);
5645 /* Testing with Unigine Heaven extreme tesselation yielded best results
5646 * with TRAP_SPLIT = 3.
5648 if (sctx
->family
== CHIP_FIJI
||
5649 sctx
->family
>= CHIP_POLARIS10
)
5650 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5652 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5653 } else if (!has_clear_state
) {
5654 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5655 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5658 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5659 if (sctx
->chip_class
>= GFX7
) {
5660 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5661 S_028084_ADDRESS(border_color_va
>> 40));
5663 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5664 RADEON_PRIO_BORDER_COLORS
);
5666 if (sctx
->chip_class
>= GFX9
) {
5667 unsigned num_se
= sscreen
->info
.max_se
;
5668 unsigned pc_lines
= 0;
5669 unsigned max_alloc_count
= 0;
5671 switch (sctx
->family
) {
5690 if (sctx
->chip_class
>= GFX10
) {
5691 max_alloc_count
= pc_lines
/ 3;
5693 max_alloc_count
= MIN2(128, pc_lines
/ (4 * num_se
));
5696 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5697 S_028C48_MAX_ALLOC_COUNT(max_alloc_count
) |
5698 S_028C48_MAX_PRIM_PER_BATCH(1023));
5699 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5700 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5701 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5704 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5705 sctx
->init_config
= pm4
;