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radeonsi: replace si_vertex_elements::elements with separate fields
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 struct si_state_blend *old_blend = sctx->queued.named.blend;
607 struct si_state_blend *blend = (struct si_state_blend *)state;
608
609 if (!state)
610 return;
611
612 if (!old_blend ||
613 old_blend->cb_target_mask != blend->cb_target_mask ||
614 old_blend->dual_src_blend != blend->dual_src_blend)
615 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
616
617 si_pm4_bind_state(sctx, blend, state);
618
619 if (!old_blend ||
620 old_blend->cb_target_mask != blend->cb_target_mask ||
621 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
622 old_blend->alpha_to_one != blend->alpha_to_one ||
623 old_blend->dual_src_blend != blend->dual_src_blend ||
624 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
625 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
626 sctx->do_update_shaders = true;
627 }
628
629 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
630 {
631 struct si_context *sctx = (struct si_context *)ctx;
632 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
633 }
634
635 static void si_set_blend_color(struct pipe_context *ctx,
636 const struct pipe_blend_color *state)
637 {
638 struct si_context *sctx = (struct si_context *)ctx;
639
640 sctx->blend_color.state = *state;
641 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
642 }
643
644 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
645 {
646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
647
648 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
649 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
650 }
651
652 /*
653 * Clipping
654 */
655
656 static void si_set_clip_state(struct pipe_context *ctx,
657 const struct pipe_clip_state *state)
658 {
659 struct si_context *sctx = (struct si_context *)ctx;
660 struct pipe_constant_buffer cb;
661
662 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
663 return;
664
665 sctx->clip_state.state = *state;
666 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
667
668 cb.buffer = NULL;
669 cb.user_buffer = state->ucp;
670 cb.buffer_offset = 0;
671 cb.buffer_size = 4*4*8;
672 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
673 pipe_resource_reference(&cb.buffer, NULL);
674 }
675
676 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
677 {
678 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
679
680 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
681 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
682 }
683
684 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
685 {
686 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
687 struct si_shader *vs = si_get_vs_state(sctx);
688 struct si_shader_selector *vs_sel = vs->selector;
689 struct tgsi_shader_info *info = &vs_sel->info;
690 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
691 unsigned window_space =
692 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
693 unsigned clipdist_mask = vs_sel->clipdist_mask;
694 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
695 unsigned culldist_mask = vs_sel->culldist_mask;
696 unsigned total_mask;
697
698 if (vs->key.opt.clip_disable) {
699 assert(!info->culldist_writemask);
700 clipdist_mask = 0;
701 culldist_mask = 0;
702 }
703 total_mask = clipdist_mask | culldist_mask;
704
705 /* Clip distances on points have no effect, so need to be implemented
706 * as cull distances. This applies for the clipvertex case as well.
707 *
708 * Setting this for primitives other than points should have no adverse
709 * effects.
710 */
711 clipdist_mask &= rs->clip_plane_enable;
712 culldist_mask |= clipdist_mask;
713
714 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
715 vs_sel->pa_cl_vs_out_cntl |
716 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
717 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
718 clipdist_mask | (culldist_mask << 8));
719 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
720 rs->pa_cl_clip_cntl |
721 ucp_mask |
722 S_028810_CLIP_DISABLE(window_space));
723
724 if (sctx->b.chip_class <= VI) {
725 /* reuse needs to be set off if we write oViewport */
726 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
727 S_028AB4_REUSE_OFF(info->writes_viewport_index));
728 }
729 }
730
731 /*
732 * inferred state between framebuffer and rasterizer
733 */
734 static void si_update_poly_offset_state(struct si_context *sctx)
735 {
736 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
737
738 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
739 si_pm4_bind_state(sctx, poly_offset, NULL);
740 return;
741 }
742
743 /* Use the user format, not db_render_format, so that the polygon
744 * offset behaves as expected by applications.
745 */
746 switch (sctx->framebuffer.state.zsbuf->texture->format) {
747 case PIPE_FORMAT_Z16_UNORM:
748 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
749 break;
750 default: /* 24-bit */
751 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
752 break;
753 case PIPE_FORMAT_Z32_FLOAT:
754 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
755 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
756 break;
757 }
758 }
759
760 /*
761 * Rasterizer
762 */
763
764 static uint32_t si_translate_fill(uint32_t func)
765 {
766 switch(func) {
767 case PIPE_POLYGON_MODE_FILL:
768 return V_028814_X_DRAW_TRIANGLES;
769 case PIPE_POLYGON_MODE_LINE:
770 return V_028814_X_DRAW_LINES;
771 case PIPE_POLYGON_MODE_POINT:
772 return V_028814_X_DRAW_POINTS;
773 default:
774 assert(0);
775 return V_028814_X_DRAW_POINTS;
776 }
777 }
778
779 static void *si_create_rs_state(struct pipe_context *ctx,
780 const struct pipe_rasterizer_state *state)
781 {
782 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
783 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
784 struct si_pm4_state *pm4 = &rs->pm4;
785 unsigned tmp, i;
786 float psize_min, psize_max;
787
788 if (!rs) {
789 return NULL;
790 }
791
792 rs->scissor_enable = state->scissor;
793 rs->clip_halfz = state->clip_halfz;
794 rs->two_side = state->light_twoside;
795 rs->multisample_enable = state->multisample;
796 rs->force_persample_interp = state->force_persample_interp;
797 rs->clip_plane_enable = state->clip_plane_enable;
798 rs->line_stipple_enable = state->line_stipple_enable;
799 rs->poly_stipple_enable = state->poly_stipple_enable;
800 rs->line_smooth = state->line_smooth;
801 rs->poly_smooth = state->poly_smooth;
802 rs->uses_poly_offset = state->offset_point || state->offset_line ||
803 state->offset_tri;
804 rs->clamp_fragment_color = state->clamp_fragment_color;
805 rs->clamp_vertex_color = state->clamp_vertex_color;
806 rs->flatshade = state->flatshade;
807 rs->sprite_coord_enable = state->sprite_coord_enable;
808 rs->rasterizer_discard = state->rasterizer_discard;
809 rs->pa_sc_line_stipple = state->line_stipple_enable ?
810 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
811 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
812 rs->pa_cl_clip_cntl =
813 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
814 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
815 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
816 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
817 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
818
819 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
820 S_0286D4_FLAT_SHADE_ENA(1) |
821 S_0286D4_PNT_SPRITE_ENA(1) |
822 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
823 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
824 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
825 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
826 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
827
828 /* point size 12.4 fixed point */
829 tmp = (unsigned)(state->point_size * 8.0);
830 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
831
832 if (state->point_size_per_vertex) {
833 psize_min = util_get_min_point_size(state);
834 psize_max = 8192;
835 } else {
836 /* Force the point size to be as if the vertex output was disabled. */
837 psize_min = state->point_size;
838 psize_max = state->point_size;
839 }
840 /* Divide by two, because 0.5 = 1 pixel. */
841 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
842 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
843 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
844
845 tmp = (unsigned)state->line_width * 8;
846 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
847 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
848 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
849 S_028A48_MSAA_ENABLE(state->multisample ||
850 state->poly_smooth ||
851 state->line_smooth) |
852 S_028A48_VPORT_SCISSOR_ENABLE(1) |
853 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
854
855 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
856 S_028BE4_PIX_CENTER(state->half_pixel_center) |
857 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
858
859 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
860 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
861 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
862 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
863 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
864 S_028814_FACE(!state->front_ccw) |
865 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
866 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
867 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
868 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
869 state->fill_back != PIPE_POLYGON_MODE_FILL) |
870 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
871 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
872
873 if (!rs->uses_poly_offset)
874 return rs;
875
876 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
877 if (!rs->pm4_poly_offset) {
878 FREE(rs);
879 return NULL;
880 }
881
882 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
883 for (i = 0; i < 3; i++) {
884 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
885 float offset_units = state->offset_units;
886 float offset_scale = state->offset_scale * 16.0f;
887 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
888
889 if (!state->offset_units_unscaled) {
890 switch (i) {
891 case 0: /* 16-bit zbuffer */
892 offset_units *= 4.0f;
893 pa_su_poly_offset_db_fmt_cntl =
894 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
895 break;
896 case 1: /* 24-bit zbuffer */
897 offset_units *= 2.0f;
898 pa_su_poly_offset_db_fmt_cntl =
899 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
900 break;
901 case 2: /* 32-bit zbuffer */
902 offset_units *= 1.0f;
903 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
904 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
905 break;
906 }
907 }
908
909 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
910 fui(offset_scale));
911 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
912 fui(offset_units));
913 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
914 fui(offset_scale));
915 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
916 fui(offset_units));
917 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
918 pa_su_poly_offset_db_fmt_cntl);
919 }
920
921 return rs;
922 }
923
924 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
925 {
926 struct si_context *sctx = (struct si_context *)ctx;
927 struct si_state_rasterizer *old_rs =
928 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
929 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
930
931 if (!state)
932 return;
933
934 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
935 si_mark_atom_dirty(sctx, &sctx->db_render_state);
936
937 /* Update the small primitive filter workaround if necessary. */
938 if (sctx->screen->has_msaa_sample_loc_bug &&
939 sctx->framebuffer.nr_samples > 1)
940 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
941 }
942
943 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
944 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
945
946 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
947
948 si_pm4_bind_state(sctx, rasterizer, rs);
949 si_update_poly_offset_state(sctx);
950
951 if (!old_rs ||
952 old_rs->clip_plane_enable != rs->clip_plane_enable ||
953 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
954 si_mark_atom_dirty(sctx, &sctx->clip_regs);
955
956 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
957 rs->line_stipple_enable;
958
959 if (!old_rs ||
960 old_rs->clip_plane_enable != rs->clip_plane_enable ||
961 old_rs->rasterizer_discard != rs->rasterizer_discard ||
962 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
963 old_rs->flatshade != rs->flatshade ||
964 old_rs->two_side != rs->two_side ||
965 old_rs->multisample_enable != rs->multisample_enable ||
966 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
967 old_rs->poly_smooth != rs->poly_smooth ||
968 old_rs->line_smooth != rs->line_smooth ||
969 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
970 old_rs->force_persample_interp != rs->force_persample_interp)
971 sctx->do_update_shaders = true;
972 }
973
974 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
975 {
976 struct si_context *sctx = (struct si_context *)ctx;
977 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
978
979 if (sctx->queued.named.rasterizer == state)
980 si_pm4_bind_state(sctx, poly_offset, NULL);
981
982 FREE(rs->pm4_poly_offset);
983 si_pm4_delete_state(sctx, rasterizer, rs);
984 }
985
986 /*
987 * infeered state between dsa and stencil ref
988 */
989 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
990 {
991 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
992 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
993 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
994
995 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
996 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
997 S_028430_STENCILMASK(dsa->valuemask[0]) |
998 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
999 S_028430_STENCILOPVAL(1));
1000 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1001 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1002 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1003 S_028434_STENCILOPVAL_BF(1));
1004 }
1005
1006 static void si_set_stencil_ref(struct pipe_context *ctx,
1007 const struct pipe_stencil_ref *state)
1008 {
1009 struct si_context *sctx = (struct si_context *)ctx;
1010
1011 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1012 return;
1013
1014 sctx->stencil_ref.state = *state;
1015 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1016 }
1017
1018
1019 /*
1020 * DSA
1021 */
1022
1023 static uint32_t si_translate_stencil_op(int s_op)
1024 {
1025 switch (s_op) {
1026 case PIPE_STENCIL_OP_KEEP:
1027 return V_02842C_STENCIL_KEEP;
1028 case PIPE_STENCIL_OP_ZERO:
1029 return V_02842C_STENCIL_ZERO;
1030 case PIPE_STENCIL_OP_REPLACE:
1031 return V_02842C_STENCIL_REPLACE_TEST;
1032 case PIPE_STENCIL_OP_INCR:
1033 return V_02842C_STENCIL_ADD_CLAMP;
1034 case PIPE_STENCIL_OP_DECR:
1035 return V_02842C_STENCIL_SUB_CLAMP;
1036 case PIPE_STENCIL_OP_INCR_WRAP:
1037 return V_02842C_STENCIL_ADD_WRAP;
1038 case PIPE_STENCIL_OP_DECR_WRAP:
1039 return V_02842C_STENCIL_SUB_WRAP;
1040 case PIPE_STENCIL_OP_INVERT:
1041 return V_02842C_STENCIL_INVERT;
1042 default:
1043 R600_ERR("Unknown stencil op %d", s_op);
1044 assert(0);
1045 break;
1046 }
1047 return 0;
1048 }
1049
1050 static void *si_create_dsa_state(struct pipe_context *ctx,
1051 const struct pipe_depth_stencil_alpha_state *state)
1052 {
1053 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1054 struct si_pm4_state *pm4 = &dsa->pm4;
1055 unsigned db_depth_control;
1056 uint32_t db_stencil_control = 0;
1057
1058 if (!dsa) {
1059 return NULL;
1060 }
1061
1062 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1063 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1064 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1065 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1066
1067 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1068 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1069 S_028800_ZFUNC(state->depth.func) |
1070 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1071
1072 /* stencil */
1073 if (state->stencil[0].enabled) {
1074 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1075 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1076 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1077 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1078 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1079
1080 if (state->stencil[1].enabled) {
1081 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1082 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1083 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1084 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1085 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1086 }
1087 }
1088
1089 /* alpha */
1090 if (state->alpha.enabled) {
1091 dsa->alpha_func = state->alpha.func;
1092
1093 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1094 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1095 } else {
1096 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1097 }
1098
1099 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1100 if (state->stencil[0].enabled)
1101 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1102 if (state->depth.bounds_test) {
1103 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1104 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1105 }
1106
1107 return dsa;
1108 }
1109
1110 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1111 {
1112 struct si_context *sctx = (struct si_context *)ctx;
1113 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1114 struct si_state_dsa *dsa = state;
1115
1116 if (!state)
1117 return;
1118
1119 si_pm4_bind_state(sctx, dsa, dsa);
1120
1121 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1122 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1123 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1124 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1125 }
1126
1127 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1128 sctx->do_update_shaders = true;
1129 }
1130
1131 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1132 {
1133 struct si_context *sctx = (struct si_context *)ctx;
1134 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1135 }
1136
1137 static void *si_create_db_flush_dsa(struct si_context *sctx)
1138 {
1139 struct pipe_depth_stencil_alpha_state dsa = {};
1140
1141 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1142 }
1143
1144 /* DB RENDER STATE */
1145
1146 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1147 {
1148 struct si_context *sctx = (struct si_context*)ctx;
1149
1150 /* Pipeline stat & streamout queries. */
1151 if (enable) {
1152 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1153 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1154 } else {
1155 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1156 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1157 }
1158
1159 /* Occlusion queries. */
1160 if (sctx->occlusion_queries_disabled != !enable) {
1161 sctx->occlusion_queries_disabled = !enable;
1162 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1163 }
1164 }
1165
1166 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1167 {
1168 struct si_context *sctx = (struct si_context*)ctx;
1169
1170 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1171 }
1172
1173 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1174 {
1175 struct si_context *sctx = (struct si_context*)ctx;
1176
1177 st->saved_compute = sctx->cs_shader_state.program;
1178
1179 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1180 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1181 }
1182
1183 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1184 {
1185 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1186 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1187 unsigned db_shader_control;
1188
1189 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1190
1191 /* DB_RENDER_CONTROL */
1192 if (sctx->dbcb_depth_copy_enabled ||
1193 sctx->dbcb_stencil_copy_enabled) {
1194 radeon_emit(cs,
1195 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1196 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1197 S_028000_COPY_CENTROID(1) |
1198 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1199 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1200 radeon_emit(cs,
1201 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1202 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1203 } else {
1204 radeon_emit(cs,
1205 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1206 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1207 }
1208
1209 /* DB_COUNT_CONTROL (occlusion queries) */
1210 if (sctx->b.num_occlusion_queries > 0 &&
1211 !sctx->occlusion_queries_disabled) {
1212 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1213
1214 if (sctx->b.chip_class >= CIK) {
1215 radeon_emit(cs,
1216 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1217 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1218 S_028004_ZPASS_ENABLE(1) |
1219 S_028004_SLICE_EVEN_ENABLE(1) |
1220 S_028004_SLICE_ODD_ENABLE(1));
1221 } else {
1222 radeon_emit(cs,
1223 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1224 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1225 }
1226 } else {
1227 /* Disable occlusion queries. */
1228 if (sctx->b.chip_class >= CIK) {
1229 radeon_emit(cs, 0);
1230 } else {
1231 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1232 }
1233 }
1234
1235 /* DB_RENDER_OVERRIDE2 */
1236 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1237 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1238 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1239 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1240
1241 db_shader_control = sctx->ps_db_shader_control;
1242
1243 /* Bug workaround for smoothing (overrasterization) on SI. */
1244 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1245 db_shader_control &= C_02880C_Z_ORDER;
1246 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1247 }
1248
1249 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1250 if (!rs || !rs->multisample_enable)
1251 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1252
1253 if (sctx->screen->b.has_rbplus &&
1254 !sctx->screen->b.rbplus_allowed)
1255 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1256
1257 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1258 db_shader_control);
1259 }
1260
1261 /*
1262 * format translation
1263 */
1264 static uint32_t si_translate_colorformat(enum pipe_format format)
1265 {
1266 const struct util_format_description *desc = util_format_description(format);
1267
1268 #define HAS_SIZE(x,y,z,w) \
1269 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1270 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1271
1272 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1273 return V_028C70_COLOR_10_11_11;
1274
1275 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1276 return V_028C70_COLOR_INVALID;
1277
1278 /* hw cannot support mixed formats (except depth/stencil, since
1279 * stencil is not written to). */
1280 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1281 return V_028C70_COLOR_INVALID;
1282
1283 switch (desc->nr_channels) {
1284 case 1:
1285 switch (desc->channel[0].size) {
1286 case 8:
1287 return V_028C70_COLOR_8;
1288 case 16:
1289 return V_028C70_COLOR_16;
1290 case 32:
1291 return V_028C70_COLOR_32;
1292 }
1293 break;
1294 case 2:
1295 if (desc->channel[0].size == desc->channel[1].size) {
1296 switch (desc->channel[0].size) {
1297 case 8:
1298 return V_028C70_COLOR_8_8;
1299 case 16:
1300 return V_028C70_COLOR_16_16;
1301 case 32:
1302 return V_028C70_COLOR_32_32;
1303 }
1304 } else if (HAS_SIZE(8,24,0,0)) {
1305 return V_028C70_COLOR_24_8;
1306 } else if (HAS_SIZE(24,8,0,0)) {
1307 return V_028C70_COLOR_8_24;
1308 }
1309 break;
1310 case 3:
1311 if (HAS_SIZE(5,6,5,0)) {
1312 return V_028C70_COLOR_5_6_5;
1313 } else if (HAS_SIZE(32,8,24,0)) {
1314 return V_028C70_COLOR_X24_8_32_FLOAT;
1315 }
1316 break;
1317 case 4:
1318 if (desc->channel[0].size == desc->channel[1].size &&
1319 desc->channel[0].size == desc->channel[2].size &&
1320 desc->channel[0].size == desc->channel[3].size) {
1321 switch (desc->channel[0].size) {
1322 case 4:
1323 return V_028C70_COLOR_4_4_4_4;
1324 case 8:
1325 return V_028C70_COLOR_8_8_8_8;
1326 case 16:
1327 return V_028C70_COLOR_16_16_16_16;
1328 case 32:
1329 return V_028C70_COLOR_32_32_32_32;
1330 }
1331 } else if (HAS_SIZE(5,5,5,1)) {
1332 return V_028C70_COLOR_1_5_5_5;
1333 } else if (HAS_SIZE(10,10,10,2)) {
1334 return V_028C70_COLOR_2_10_10_10;
1335 }
1336 break;
1337 }
1338 return V_028C70_COLOR_INVALID;
1339 }
1340
1341 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1342 {
1343 if (SI_BIG_ENDIAN) {
1344 switch(colorformat) {
1345 /* 8-bit buffers. */
1346 case V_028C70_COLOR_8:
1347 return V_028C70_ENDIAN_NONE;
1348
1349 /* 16-bit buffers. */
1350 case V_028C70_COLOR_5_6_5:
1351 case V_028C70_COLOR_1_5_5_5:
1352 case V_028C70_COLOR_4_4_4_4:
1353 case V_028C70_COLOR_16:
1354 case V_028C70_COLOR_8_8:
1355 return V_028C70_ENDIAN_8IN16;
1356
1357 /* 32-bit buffers. */
1358 case V_028C70_COLOR_8_8_8_8:
1359 case V_028C70_COLOR_2_10_10_10:
1360 case V_028C70_COLOR_8_24:
1361 case V_028C70_COLOR_24_8:
1362 case V_028C70_COLOR_16_16:
1363 return V_028C70_ENDIAN_8IN32;
1364
1365 /* 64-bit buffers. */
1366 case V_028C70_COLOR_16_16_16_16:
1367 return V_028C70_ENDIAN_8IN16;
1368
1369 case V_028C70_COLOR_32_32:
1370 return V_028C70_ENDIAN_8IN32;
1371
1372 /* 128-bit buffers. */
1373 case V_028C70_COLOR_32_32_32_32:
1374 return V_028C70_ENDIAN_8IN32;
1375 default:
1376 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1377 }
1378 } else {
1379 return V_028C70_ENDIAN_NONE;
1380 }
1381 }
1382
1383 static uint32_t si_translate_dbformat(enum pipe_format format)
1384 {
1385 switch (format) {
1386 case PIPE_FORMAT_Z16_UNORM:
1387 return V_028040_Z_16;
1388 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1389 case PIPE_FORMAT_X8Z24_UNORM:
1390 case PIPE_FORMAT_Z24X8_UNORM:
1391 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1392 return V_028040_Z_24; /* deprecated on SI */
1393 case PIPE_FORMAT_Z32_FLOAT:
1394 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1395 return V_028040_Z_32_FLOAT;
1396 default:
1397 return V_028040_Z_INVALID;
1398 }
1399 }
1400
1401 /*
1402 * Texture translation
1403 */
1404
1405 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1406 enum pipe_format format,
1407 const struct util_format_description *desc,
1408 int first_non_void)
1409 {
1410 struct si_screen *sscreen = (struct si_screen*)screen;
1411 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1412 sscreen->b.info.drm_minor >= 31) ||
1413 sscreen->b.info.drm_major == 3;
1414 bool uniform = true;
1415 int i;
1416
1417 /* Colorspace (return non-RGB formats directly). */
1418 switch (desc->colorspace) {
1419 /* Depth stencil formats */
1420 case UTIL_FORMAT_COLORSPACE_ZS:
1421 switch (format) {
1422 case PIPE_FORMAT_Z16_UNORM:
1423 return V_008F14_IMG_DATA_FORMAT_16;
1424 case PIPE_FORMAT_X24S8_UINT:
1425 case PIPE_FORMAT_S8X24_UINT:
1426 /*
1427 * Implemented as an 8_8_8_8 data format to fix texture
1428 * gathers in stencil sampling. This affects at least
1429 * GL45-CTS.texture_cube_map_array.sampling on VI.
1430 */
1431 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1432 case PIPE_FORMAT_Z24X8_UNORM:
1433 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1434 return V_008F14_IMG_DATA_FORMAT_8_24;
1435 case PIPE_FORMAT_X8Z24_UNORM:
1436 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1437 return V_008F14_IMG_DATA_FORMAT_24_8;
1438 case PIPE_FORMAT_S8_UINT:
1439 return V_008F14_IMG_DATA_FORMAT_8;
1440 case PIPE_FORMAT_Z32_FLOAT:
1441 return V_008F14_IMG_DATA_FORMAT_32;
1442 case PIPE_FORMAT_X32_S8X24_UINT:
1443 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1444 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1445 default:
1446 goto out_unknown;
1447 }
1448
1449 case UTIL_FORMAT_COLORSPACE_YUV:
1450 goto out_unknown; /* TODO */
1451
1452 case UTIL_FORMAT_COLORSPACE_SRGB:
1453 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1454 goto out_unknown;
1455 break;
1456
1457 default:
1458 break;
1459 }
1460
1461 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1462 if (!enable_compressed_formats)
1463 goto out_unknown;
1464
1465 switch (format) {
1466 case PIPE_FORMAT_RGTC1_SNORM:
1467 case PIPE_FORMAT_LATC1_SNORM:
1468 case PIPE_FORMAT_RGTC1_UNORM:
1469 case PIPE_FORMAT_LATC1_UNORM:
1470 return V_008F14_IMG_DATA_FORMAT_BC4;
1471 case PIPE_FORMAT_RGTC2_SNORM:
1472 case PIPE_FORMAT_LATC2_SNORM:
1473 case PIPE_FORMAT_RGTC2_UNORM:
1474 case PIPE_FORMAT_LATC2_UNORM:
1475 return V_008F14_IMG_DATA_FORMAT_BC5;
1476 default:
1477 goto out_unknown;
1478 }
1479 }
1480
1481 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1482 (sscreen->b.family == CHIP_STONEY ||
1483 sscreen->b.chip_class >= GFX9)) {
1484 switch (format) {
1485 case PIPE_FORMAT_ETC1_RGB8:
1486 case PIPE_FORMAT_ETC2_RGB8:
1487 case PIPE_FORMAT_ETC2_SRGB8:
1488 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1489 case PIPE_FORMAT_ETC2_RGB8A1:
1490 case PIPE_FORMAT_ETC2_SRGB8A1:
1491 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1492 case PIPE_FORMAT_ETC2_RGBA8:
1493 case PIPE_FORMAT_ETC2_SRGBA8:
1494 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1495 case PIPE_FORMAT_ETC2_R11_UNORM:
1496 case PIPE_FORMAT_ETC2_R11_SNORM:
1497 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1498 case PIPE_FORMAT_ETC2_RG11_UNORM:
1499 case PIPE_FORMAT_ETC2_RG11_SNORM:
1500 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1501 default:
1502 goto out_unknown;
1503 }
1504 }
1505
1506 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1507 if (!enable_compressed_formats)
1508 goto out_unknown;
1509
1510 switch (format) {
1511 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1512 case PIPE_FORMAT_BPTC_SRGBA:
1513 return V_008F14_IMG_DATA_FORMAT_BC7;
1514 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1515 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1516 return V_008F14_IMG_DATA_FORMAT_BC6;
1517 default:
1518 goto out_unknown;
1519 }
1520 }
1521
1522 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1523 switch (format) {
1524 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1525 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1526 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1527 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1528 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1529 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1530 default:
1531 goto out_unknown;
1532 }
1533 }
1534
1535 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1536 if (!enable_compressed_formats)
1537 goto out_unknown;
1538
1539 if (!util_format_s3tc_enabled) {
1540 goto out_unknown;
1541 }
1542
1543 switch (format) {
1544 case PIPE_FORMAT_DXT1_RGB:
1545 case PIPE_FORMAT_DXT1_RGBA:
1546 case PIPE_FORMAT_DXT1_SRGB:
1547 case PIPE_FORMAT_DXT1_SRGBA:
1548 return V_008F14_IMG_DATA_FORMAT_BC1;
1549 case PIPE_FORMAT_DXT3_RGBA:
1550 case PIPE_FORMAT_DXT3_SRGBA:
1551 return V_008F14_IMG_DATA_FORMAT_BC2;
1552 case PIPE_FORMAT_DXT5_RGBA:
1553 case PIPE_FORMAT_DXT5_SRGBA:
1554 return V_008F14_IMG_DATA_FORMAT_BC3;
1555 default:
1556 goto out_unknown;
1557 }
1558 }
1559
1560 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1561 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1562 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1563 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1564 }
1565
1566 /* R8G8Bx_SNORM - TODO CxV8U8 */
1567
1568 /* hw cannot support mixed formats (except depth/stencil, since only
1569 * depth is read).*/
1570 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1571 goto out_unknown;
1572
1573 /* See whether the components are of the same size. */
1574 for (i = 1; i < desc->nr_channels; i++) {
1575 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1576 }
1577
1578 /* Non-uniform formats. */
1579 if (!uniform) {
1580 switch(desc->nr_channels) {
1581 case 3:
1582 if (desc->channel[0].size == 5 &&
1583 desc->channel[1].size == 6 &&
1584 desc->channel[2].size == 5) {
1585 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1586 }
1587 goto out_unknown;
1588 case 4:
1589 if (desc->channel[0].size == 5 &&
1590 desc->channel[1].size == 5 &&
1591 desc->channel[2].size == 5 &&
1592 desc->channel[3].size == 1) {
1593 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1594 }
1595 if (desc->channel[0].size == 10 &&
1596 desc->channel[1].size == 10 &&
1597 desc->channel[2].size == 10 &&
1598 desc->channel[3].size == 2) {
1599 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1600 }
1601 goto out_unknown;
1602 }
1603 goto out_unknown;
1604 }
1605
1606 if (first_non_void < 0 || first_non_void > 3)
1607 goto out_unknown;
1608
1609 /* uniform formats */
1610 switch (desc->channel[first_non_void].size) {
1611 case 4:
1612 switch (desc->nr_channels) {
1613 #if 0 /* Not supported for render targets */
1614 case 2:
1615 return V_008F14_IMG_DATA_FORMAT_4_4;
1616 #endif
1617 case 4:
1618 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1619 }
1620 break;
1621 case 8:
1622 switch (desc->nr_channels) {
1623 case 1:
1624 return V_008F14_IMG_DATA_FORMAT_8;
1625 case 2:
1626 return V_008F14_IMG_DATA_FORMAT_8_8;
1627 case 4:
1628 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1629 }
1630 break;
1631 case 16:
1632 switch (desc->nr_channels) {
1633 case 1:
1634 return V_008F14_IMG_DATA_FORMAT_16;
1635 case 2:
1636 return V_008F14_IMG_DATA_FORMAT_16_16;
1637 case 4:
1638 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1639 }
1640 break;
1641 case 32:
1642 switch (desc->nr_channels) {
1643 case 1:
1644 return V_008F14_IMG_DATA_FORMAT_32;
1645 case 2:
1646 return V_008F14_IMG_DATA_FORMAT_32_32;
1647 #if 0 /* Not supported for render targets */
1648 case 3:
1649 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1650 #endif
1651 case 4:
1652 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1653 }
1654 }
1655
1656 out_unknown:
1657 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1658 return ~0;
1659 }
1660
1661 static unsigned si_tex_wrap(unsigned wrap)
1662 {
1663 switch (wrap) {
1664 default:
1665 case PIPE_TEX_WRAP_REPEAT:
1666 return V_008F30_SQ_TEX_WRAP;
1667 case PIPE_TEX_WRAP_CLAMP:
1668 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1669 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1670 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1671 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1672 return V_008F30_SQ_TEX_CLAMP_BORDER;
1673 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1674 return V_008F30_SQ_TEX_MIRROR;
1675 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1676 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1677 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1678 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1679 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1680 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1681 }
1682 }
1683
1684 static unsigned si_tex_mipfilter(unsigned filter)
1685 {
1686 switch (filter) {
1687 case PIPE_TEX_MIPFILTER_NEAREST:
1688 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1689 case PIPE_TEX_MIPFILTER_LINEAR:
1690 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1691 default:
1692 case PIPE_TEX_MIPFILTER_NONE:
1693 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1694 }
1695 }
1696
1697 static unsigned si_tex_compare(unsigned compare)
1698 {
1699 switch (compare) {
1700 default:
1701 case PIPE_FUNC_NEVER:
1702 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1703 case PIPE_FUNC_LESS:
1704 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1705 case PIPE_FUNC_EQUAL:
1706 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1707 case PIPE_FUNC_LEQUAL:
1708 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1709 case PIPE_FUNC_GREATER:
1710 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1711 case PIPE_FUNC_NOTEQUAL:
1712 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1713 case PIPE_FUNC_GEQUAL:
1714 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1715 case PIPE_FUNC_ALWAYS:
1716 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1717 }
1718 }
1719
1720 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1721 unsigned view_target, unsigned nr_samples)
1722 {
1723 unsigned res_target = rtex->resource.b.b.target;
1724
1725 if (view_target == PIPE_TEXTURE_CUBE ||
1726 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1727 res_target = view_target;
1728 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1729 else if (res_target == PIPE_TEXTURE_CUBE ||
1730 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1731 res_target = PIPE_TEXTURE_2D_ARRAY;
1732
1733 /* GFX9 allocates 1D textures as 2D. */
1734 if ((res_target == PIPE_TEXTURE_1D ||
1735 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1736 sscreen->b.chip_class >= GFX9 &&
1737 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1738 if (res_target == PIPE_TEXTURE_1D)
1739 res_target = PIPE_TEXTURE_2D;
1740 else
1741 res_target = PIPE_TEXTURE_2D_ARRAY;
1742 }
1743
1744 switch (res_target) {
1745 default:
1746 case PIPE_TEXTURE_1D:
1747 return V_008F1C_SQ_RSRC_IMG_1D;
1748 case PIPE_TEXTURE_1D_ARRAY:
1749 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1750 case PIPE_TEXTURE_2D:
1751 case PIPE_TEXTURE_RECT:
1752 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1753 V_008F1C_SQ_RSRC_IMG_2D;
1754 case PIPE_TEXTURE_2D_ARRAY:
1755 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1756 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1757 case PIPE_TEXTURE_3D:
1758 return V_008F1C_SQ_RSRC_IMG_3D;
1759 case PIPE_TEXTURE_CUBE:
1760 case PIPE_TEXTURE_CUBE_ARRAY:
1761 return V_008F1C_SQ_RSRC_IMG_CUBE;
1762 }
1763 }
1764
1765 /*
1766 * Format support testing
1767 */
1768
1769 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1770 {
1771 return si_translate_texformat(screen, format, util_format_description(format),
1772 util_format_get_first_non_void_channel(format)) != ~0U;
1773 }
1774
1775 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1776 const struct util_format_description *desc,
1777 int first_non_void)
1778 {
1779 int i;
1780
1781 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1782 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1783
1784 assert(first_non_void >= 0);
1785
1786 if (desc->nr_channels == 4 &&
1787 desc->channel[0].size == 10 &&
1788 desc->channel[1].size == 10 &&
1789 desc->channel[2].size == 10 &&
1790 desc->channel[3].size == 2)
1791 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1792
1793 /* See whether the components are of the same size. */
1794 for (i = 0; i < desc->nr_channels; i++) {
1795 if (desc->channel[first_non_void].size != desc->channel[i].size)
1796 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1797 }
1798
1799 switch (desc->channel[first_non_void].size) {
1800 case 8:
1801 switch (desc->nr_channels) {
1802 case 1:
1803 case 3: /* 3 loads */
1804 return V_008F0C_BUF_DATA_FORMAT_8;
1805 case 2:
1806 return V_008F0C_BUF_DATA_FORMAT_8_8;
1807 case 4:
1808 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1809 }
1810 break;
1811 case 16:
1812 switch (desc->nr_channels) {
1813 case 1:
1814 case 3: /* 3 loads */
1815 return V_008F0C_BUF_DATA_FORMAT_16;
1816 case 2:
1817 return V_008F0C_BUF_DATA_FORMAT_16_16;
1818 case 4:
1819 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1820 }
1821 break;
1822 case 32:
1823 switch (desc->nr_channels) {
1824 case 1:
1825 return V_008F0C_BUF_DATA_FORMAT_32;
1826 case 2:
1827 return V_008F0C_BUF_DATA_FORMAT_32_32;
1828 case 3:
1829 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1830 case 4:
1831 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1832 }
1833 break;
1834 case 64:
1835 /* Legacy double formats. */
1836 switch (desc->nr_channels) {
1837 case 1: /* 1 load */
1838 return V_008F0C_BUF_DATA_FORMAT_32_32;
1839 case 2: /* 1 load */
1840 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1841 case 3: /* 3 loads */
1842 return V_008F0C_BUF_DATA_FORMAT_32_32;
1843 case 4: /* 2 loads */
1844 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1845 }
1846 break;
1847 }
1848
1849 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1850 }
1851
1852 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1853 const struct util_format_description *desc,
1854 int first_non_void)
1855 {
1856 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1857 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1858
1859 assert(first_non_void >= 0);
1860
1861 switch (desc->channel[first_non_void].type) {
1862 case UTIL_FORMAT_TYPE_SIGNED:
1863 case UTIL_FORMAT_TYPE_FIXED:
1864 if (desc->channel[first_non_void].size >= 32 ||
1865 desc->channel[first_non_void].pure_integer)
1866 return V_008F0C_BUF_NUM_FORMAT_SINT;
1867 else if (desc->channel[first_non_void].normalized)
1868 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1869 else
1870 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1871 break;
1872 case UTIL_FORMAT_TYPE_UNSIGNED:
1873 if (desc->channel[first_non_void].size >= 32 ||
1874 desc->channel[first_non_void].pure_integer)
1875 return V_008F0C_BUF_NUM_FORMAT_UINT;
1876 else if (desc->channel[first_non_void].normalized)
1877 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1878 else
1879 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1880 break;
1881 case UTIL_FORMAT_TYPE_FLOAT:
1882 default:
1883 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1884 }
1885 }
1886
1887 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1888 enum pipe_format format,
1889 unsigned usage)
1890 {
1891 const struct util_format_description *desc;
1892 int first_non_void;
1893 unsigned data_format;
1894
1895 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1896 PIPE_BIND_SAMPLER_VIEW |
1897 PIPE_BIND_VERTEX_BUFFER)) == 0);
1898
1899 desc = util_format_description(format);
1900
1901 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1902 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1903 * for read-only access (with caveats surrounding bounds checks), but
1904 * obviously fails for write access which we have to implement for
1905 * shader images. Luckily, OpenGL doesn't expect this to be supported
1906 * anyway, and so the only impact is on PBO uploads / downloads, which
1907 * shouldn't be expected to be fast for GL_RGB anyway.
1908 */
1909 if (desc->block.bits == 3 * 8 ||
1910 desc->block.bits == 3 * 16) {
1911 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1912 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1913 if (!usage)
1914 return 0;
1915 }
1916 }
1917
1918 first_non_void = util_format_get_first_non_void_channel(format);
1919 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1920 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1921 return 0;
1922
1923 return usage;
1924 }
1925
1926 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1927 {
1928 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1929 r600_translate_colorswap(format, false) != ~0U;
1930 }
1931
1932 static bool si_is_zs_format_supported(enum pipe_format format)
1933 {
1934 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1935 }
1936
1937 static boolean si_is_format_supported(struct pipe_screen *screen,
1938 enum pipe_format format,
1939 enum pipe_texture_target target,
1940 unsigned sample_count,
1941 unsigned usage)
1942 {
1943 unsigned retval = 0;
1944
1945 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1946 R600_ERR("r600: unsupported texture type %d\n", target);
1947 return false;
1948 }
1949
1950 if (!util_format_is_supported(format, usage))
1951 return false;
1952
1953 if (sample_count > 1) {
1954 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1955 return false;
1956
1957 if (usage & PIPE_BIND_SHADER_IMAGE)
1958 return false;
1959
1960 switch (sample_count) {
1961 case 2:
1962 case 4:
1963 case 8:
1964 break;
1965 case 16:
1966 if (format == PIPE_FORMAT_NONE)
1967 return true;
1968 else
1969 return false;
1970 default:
1971 return false;
1972 }
1973 }
1974
1975 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1976 PIPE_BIND_SHADER_IMAGE)) {
1977 if (target == PIPE_BUFFER) {
1978 retval |= si_is_vertex_format_supported(
1979 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1980 PIPE_BIND_SHADER_IMAGE));
1981 } else {
1982 if (si_is_sampler_format_supported(screen, format))
1983 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1984 PIPE_BIND_SHADER_IMAGE);
1985 }
1986 }
1987
1988 if ((usage & (PIPE_BIND_RENDER_TARGET |
1989 PIPE_BIND_DISPLAY_TARGET |
1990 PIPE_BIND_SCANOUT |
1991 PIPE_BIND_SHARED |
1992 PIPE_BIND_BLENDABLE)) &&
1993 si_is_colorbuffer_format_supported(format)) {
1994 retval |= usage &
1995 (PIPE_BIND_RENDER_TARGET |
1996 PIPE_BIND_DISPLAY_TARGET |
1997 PIPE_BIND_SCANOUT |
1998 PIPE_BIND_SHARED);
1999 if (!util_format_is_pure_integer(format) &&
2000 !util_format_is_depth_or_stencil(format))
2001 retval |= usage & PIPE_BIND_BLENDABLE;
2002 }
2003
2004 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2005 si_is_zs_format_supported(format)) {
2006 retval |= PIPE_BIND_DEPTH_STENCIL;
2007 }
2008
2009 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2010 retval |= si_is_vertex_format_supported(screen, format,
2011 PIPE_BIND_VERTEX_BUFFER);
2012 }
2013
2014 if ((usage & PIPE_BIND_LINEAR) &&
2015 !util_format_is_compressed(format) &&
2016 !(usage & PIPE_BIND_DEPTH_STENCIL))
2017 retval |= PIPE_BIND_LINEAR;
2018
2019 return retval == usage;
2020 }
2021
2022 /*
2023 * framebuffer handling
2024 */
2025
2026 static void si_choose_spi_color_formats(struct r600_surface *surf,
2027 unsigned format, unsigned swap,
2028 unsigned ntype, bool is_depth)
2029 {
2030 /* Alpha is needed for alpha-to-coverage.
2031 * Blending may be with or without alpha.
2032 */
2033 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2034 unsigned alpha = 0; /* exports alpha, but may not support blending */
2035 unsigned blend = 0; /* supports blending, but may not export alpha */
2036 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2037
2038 /* Choose the SPI color formats. These are required values for RB+.
2039 * Other chips have multiple choices, though they are not necessarily better.
2040 */
2041 switch (format) {
2042 case V_028C70_COLOR_5_6_5:
2043 case V_028C70_COLOR_1_5_5_5:
2044 case V_028C70_COLOR_5_5_5_1:
2045 case V_028C70_COLOR_4_4_4_4:
2046 case V_028C70_COLOR_10_11_11:
2047 case V_028C70_COLOR_11_11_10:
2048 case V_028C70_COLOR_8:
2049 case V_028C70_COLOR_8_8:
2050 case V_028C70_COLOR_8_8_8_8:
2051 case V_028C70_COLOR_10_10_10_2:
2052 case V_028C70_COLOR_2_10_10_10:
2053 if (ntype == V_028C70_NUMBER_UINT)
2054 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2055 else if (ntype == V_028C70_NUMBER_SINT)
2056 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2057 else
2058 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2059 break;
2060
2061 case V_028C70_COLOR_16:
2062 case V_028C70_COLOR_16_16:
2063 case V_028C70_COLOR_16_16_16_16:
2064 if (ntype == V_028C70_NUMBER_UNORM ||
2065 ntype == V_028C70_NUMBER_SNORM) {
2066 /* UNORM16 and SNORM16 don't support blending */
2067 if (ntype == V_028C70_NUMBER_UNORM)
2068 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2069 else
2070 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2071
2072 /* Use 32 bits per channel for blending. */
2073 if (format == V_028C70_COLOR_16) {
2074 if (swap == V_028C70_SWAP_STD) { /* R */
2075 blend = V_028714_SPI_SHADER_32_R;
2076 blend_alpha = V_028714_SPI_SHADER_32_AR;
2077 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2078 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2079 else
2080 assert(0);
2081 } else if (format == V_028C70_COLOR_16_16) {
2082 if (swap == V_028C70_SWAP_STD) { /* RG */
2083 blend = V_028714_SPI_SHADER_32_GR;
2084 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2085 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2086 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2087 else
2088 assert(0);
2089 } else /* 16_16_16_16 */
2090 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2091 } else if (ntype == V_028C70_NUMBER_UINT)
2092 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2093 else if (ntype == V_028C70_NUMBER_SINT)
2094 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2095 else if (ntype == V_028C70_NUMBER_FLOAT)
2096 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2097 else
2098 assert(0);
2099 break;
2100
2101 case V_028C70_COLOR_32:
2102 if (swap == V_028C70_SWAP_STD) { /* R */
2103 blend = normal = V_028714_SPI_SHADER_32_R;
2104 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2105 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2106 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2107 else
2108 assert(0);
2109 break;
2110
2111 case V_028C70_COLOR_32_32:
2112 if (swap == V_028C70_SWAP_STD) { /* RG */
2113 blend = normal = V_028714_SPI_SHADER_32_GR;
2114 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2115 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2116 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2117 else
2118 assert(0);
2119 break;
2120
2121 case V_028C70_COLOR_32_32_32_32:
2122 case V_028C70_COLOR_8_24:
2123 case V_028C70_COLOR_24_8:
2124 case V_028C70_COLOR_X24_8_32_FLOAT:
2125 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2126 break;
2127
2128 default:
2129 assert(0);
2130 return;
2131 }
2132
2133 /* The DB->CB copy needs 32_ABGR. */
2134 if (is_depth)
2135 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2136
2137 surf->spi_shader_col_format = normal;
2138 surf->spi_shader_col_format_alpha = alpha;
2139 surf->spi_shader_col_format_blend = blend;
2140 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2141 }
2142
2143 static void si_initialize_color_surface(struct si_context *sctx,
2144 struct r600_surface *surf)
2145 {
2146 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2147 unsigned color_info, color_attrib, color_view;
2148 unsigned format, swap, ntype, endian;
2149 const struct util_format_description *desc;
2150 int i;
2151 unsigned blend_clamp = 0, blend_bypass = 0;
2152
2153 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2154 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2155
2156 desc = util_format_description(surf->base.format);
2157 for (i = 0; i < 4; i++) {
2158 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2159 break;
2160 }
2161 }
2162 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2163 ntype = V_028C70_NUMBER_FLOAT;
2164 } else {
2165 ntype = V_028C70_NUMBER_UNORM;
2166 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2167 ntype = V_028C70_NUMBER_SRGB;
2168 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2169 if (desc->channel[i].pure_integer) {
2170 ntype = V_028C70_NUMBER_SINT;
2171 } else {
2172 assert(desc->channel[i].normalized);
2173 ntype = V_028C70_NUMBER_SNORM;
2174 }
2175 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2176 if (desc->channel[i].pure_integer) {
2177 ntype = V_028C70_NUMBER_UINT;
2178 } else {
2179 assert(desc->channel[i].normalized);
2180 ntype = V_028C70_NUMBER_UNORM;
2181 }
2182 }
2183 }
2184
2185 format = si_translate_colorformat(surf->base.format);
2186 if (format == V_028C70_COLOR_INVALID) {
2187 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2188 }
2189 assert(format != V_028C70_COLOR_INVALID);
2190 swap = r600_translate_colorswap(surf->base.format, false);
2191 endian = si_colorformat_endian_swap(format);
2192
2193 /* blend clamp should be set for all NORM/SRGB types */
2194 if (ntype == V_028C70_NUMBER_UNORM ||
2195 ntype == V_028C70_NUMBER_SNORM ||
2196 ntype == V_028C70_NUMBER_SRGB)
2197 blend_clamp = 1;
2198
2199 /* set blend bypass according to docs if SINT/UINT or
2200 8/24 COLOR variants */
2201 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2202 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2203 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2204 blend_clamp = 0;
2205 blend_bypass = 1;
2206 }
2207
2208 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2209 if (format == V_028C70_COLOR_8 ||
2210 format == V_028C70_COLOR_8_8 ||
2211 format == V_028C70_COLOR_8_8_8_8)
2212 surf->color_is_int8 = true;
2213 else if (format == V_028C70_COLOR_10_10_10_2 ||
2214 format == V_028C70_COLOR_2_10_10_10)
2215 surf->color_is_int10 = true;
2216 }
2217
2218 color_info = S_028C70_FORMAT(format) |
2219 S_028C70_COMP_SWAP(swap) |
2220 S_028C70_BLEND_CLAMP(blend_clamp) |
2221 S_028C70_BLEND_BYPASS(blend_bypass) |
2222 S_028C70_SIMPLE_FLOAT(1) |
2223 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2224 ntype != V_028C70_NUMBER_SNORM &&
2225 ntype != V_028C70_NUMBER_SRGB &&
2226 format != V_028C70_COLOR_8_24 &&
2227 format != V_028C70_COLOR_24_8) |
2228 S_028C70_NUMBER_TYPE(ntype) |
2229 S_028C70_ENDIAN(endian);
2230
2231 /* Intensity is implemented as Red, so treat it that way. */
2232 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2233 util_format_is_intensity(surf->base.format));
2234
2235 if (rtex->resource.b.b.nr_samples > 1) {
2236 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2237
2238 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2239 S_028C74_NUM_FRAGMENTS(log_samples);
2240
2241 if (rtex->fmask.size) {
2242 color_info |= S_028C70_COMPRESSION(1);
2243 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2244
2245 if (sctx->b.chip_class == SI) {
2246 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2247 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2248 }
2249 }
2250 }
2251
2252 surf->cb_color_view = color_view;
2253 surf->cb_color_info = color_info;
2254 surf->cb_color_attrib = color_attrib;
2255
2256 if (sctx->b.chip_class >= VI) {
2257 unsigned max_uncompressed_block_size = 2;
2258
2259 if (rtex->resource.b.b.nr_samples > 1) {
2260 if (rtex->surface.bpe == 1)
2261 max_uncompressed_block_size = 0;
2262 else if (rtex->surface.bpe == 2)
2263 max_uncompressed_block_size = 1;
2264 }
2265
2266 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2267 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2268 }
2269
2270 /* This must be set for fast clear to work without FMASK. */
2271 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2272 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2273 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2274 }
2275
2276 if (sctx->b.chip_class >= GFX9) {
2277 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2278
2279 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2280 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2281 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2282 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2283 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2284 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2285 }
2286
2287 /* Determine pixel shader export format */
2288 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2289
2290 surf->color_initialized = true;
2291 }
2292
2293 static void si_init_depth_surface(struct si_context *sctx,
2294 struct r600_surface *surf)
2295 {
2296 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2297 unsigned level = surf->base.u.tex.level;
2298 unsigned format, stencil_format;
2299 uint32_t z_info, s_info;
2300
2301 format = si_translate_dbformat(rtex->db_render_format);
2302 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2303 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2304
2305 assert(format != V_028040_Z_INVALID);
2306 if (format == V_028040_Z_INVALID)
2307 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2308
2309 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2310 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2311 surf->db_htile_data_base = 0;
2312 surf->db_htile_surface = 0;
2313
2314 if (sctx->b.chip_class >= GFX9) {
2315 assert(rtex->surface.u.gfx9.surf_offset == 0);
2316 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2317 surf->db_stencil_base = (rtex->resource.gpu_address +
2318 rtex->surface.u.gfx9.stencil_offset) >> 8;
2319 z_info = S_028038_FORMAT(format) |
2320 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2321 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2322 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2323 s_info = S_02803C_FORMAT(stencil_format) |
2324 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2325 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2326 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2327 surf->db_depth_view |= S_028008_MIPID(level);
2328 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2329 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2330
2331 /* Only use HTILE for the first level. */
2332 if (rtex->htile_offset && !level) {
2333 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2334 S_028038_ALLOW_EXPCLEAR(1);
2335
2336 if (rtex->tc_compatible_htile) {
2337 unsigned max_zplanes = 4;
2338
2339 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2340 rtex->resource.b.b.nr_samples > 1)
2341 max_zplanes = 2;
2342
2343 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2344 S_028038_ITERATE_FLUSH(1);
2345 s_info |= S_02803C_ITERATE_FLUSH(1);
2346 }
2347
2348 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2349 /* Stencil buffer workaround ported from the SI-CI-VI code.
2350 * See that for explanation.
2351 */
2352 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2353 } else {
2354 /* Use all HTILE for depth if there's no stencil. */
2355 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2356 }
2357
2358 surf->db_htile_data_base = (rtex->resource.gpu_address +
2359 rtex->htile_offset) >> 8;
2360 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2361 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2362 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2363 }
2364 } else {
2365 /* SI-CI-VI */
2366 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2367
2368 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2369
2370 surf->db_depth_base = (rtex->resource.gpu_address +
2371 rtex->surface.u.legacy.level[level].offset) >> 8;
2372 surf->db_stencil_base = (rtex->resource.gpu_address +
2373 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2374
2375 z_info = S_028040_FORMAT(format) |
2376 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2377 s_info = S_028044_FORMAT(stencil_format);
2378 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2379
2380 if (sctx->b.chip_class >= CIK) {
2381 struct radeon_info *info = &sctx->screen->b.info;
2382 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2383 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2384 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2385 unsigned tile_mode = info->si_tile_mode_array[index];
2386 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2387 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2388
2389 surf->db_depth_info |=
2390 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2391 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2392 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2393 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2394 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2395 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2396 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2397 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2398 } else {
2399 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2400 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2401 tile_mode_index = si_tile_mode_index(rtex, level, true);
2402 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2403 }
2404
2405 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2406 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2407 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2408 levelinfo->nblk_y) / 64 - 1);
2409
2410 /* Only use HTILE for the first level. */
2411 if (rtex->htile_offset && !level) {
2412 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2413 S_028040_ALLOW_EXPCLEAR(1);
2414
2415 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2416 /* Workaround: For a not yet understood reason, the
2417 * combination of MSAA, fast stencil clear and stencil
2418 * decompress messes with subsequent stencil buffer
2419 * uses. Problem was reproduced on Verde, Bonaire,
2420 * Tonga, and Carrizo.
2421 *
2422 * Disabling EXPCLEAR works around the problem.
2423 *
2424 * Check piglit's arb_texture_multisample-stencil-clear
2425 * test if you want to try changing this.
2426 */
2427 if (rtex->resource.b.b.nr_samples <= 1)
2428 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2429 } else if (!rtex->tc_compatible_htile) {
2430 /* Use all of the htile_buffer for depth if there's no stencil.
2431 * This must not be set when TC-compatible HTILE is enabled
2432 * due to a hw bug.
2433 */
2434 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2435 }
2436
2437 surf->db_htile_data_base = (rtex->resource.gpu_address +
2438 rtex->htile_offset) >> 8;
2439 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2440
2441 if (rtex->tc_compatible_htile) {
2442 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2443
2444 if (rtex->resource.b.b.nr_samples <= 1)
2445 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2446 else if (rtex->resource.b.b.nr_samples <= 4)
2447 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2448 else
2449 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2450 }
2451 }
2452 }
2453
2454 surf->db_z_info = z_info;
2455 surf->db_stencil_info = s_info;
2456
2457 surf->depth_initialized = true;
2458 }
2459
2460 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2461 {
2462 for (int i = 0; i < state->nr_cbufs; ++i) {
2463 struct r600_surface *surf = NULL;
2464 struct r600_texture *rtex;
2465
2466 if (!state->cbufs[i])
2467 continue;
2468 surf = (struct r600_surface*)state->cbufs[i];
2469 rtex = (struct r600_texture*)surf->base.texture;
2470
2471 p_atomic_dec(&rtex->framebuffers_bound);
2472 }
2473 }
2474
2475 static void si_set_framebuffer_state(struct pipe_context *ctx,
2476 const struct pipe_framebuffer_state *state)
2477 {
2478 struct si_context *sctx = (struct si_context *)ctx;
2479 struct pipe_constant_buffer constbuf = {0};
2480 struct r600_surface *surf = NULL;
2481 struct r600_texture *rtex;
2482 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2483 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2484 bool unbound = false;
2485 int i;
2486
2487 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2488 if (!sctx->framebuffer.state.cbufs[i])
2489 continue;
2490
2491 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2492 if (rtex->dcc_gather_statistics)
2493 vi_separate_dcc_stop_query(ctx, rtex);
2494 }
2495
2496 /* Disable DCC if the formats are incompatible. */
2497 for (i = 0; i < state->nr_cbufs; i++) {
2498 if (!state->cbufs[i])
2499 continue;
2500
2501 surf = (struct r600_surface*)state->cbufs[i];
2502 rtex = (struct r600_texture*)surf->base.texture;
2503
2504 if (!surf->dcc_incompatible)
2505 continue;
2506
2507 /* Since the DCC decompression calls back into set_framebuffer-
2508 * _state, we need to unbind the framebuffer, so that
2509 * vi_separate_dcc_stop_query isn't called twice with the same
2510 * color buffer.
2511 */
2512 if (!unbound) {
2513 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2514 unbound = true;
2515 }
2516
2517 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2518 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2519 sctx->b.decompress_dcc(ctx, rtex);
2520
2521 surf->dcc_incompatible = false;
2522 }
2523
2524 /* Only flush TC when changing the framebuffer state, because
2525 * the only client not using TC that can change textures is
2526 * the framebuffer.
2527 *
2528 * Flush all CB and DB caches here because all buffers can be used
2529 * for write by both TC (with shader image stores) and CB/DB.
2530 */
2531 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2532 SI_CONTEXT_INV_GLOBAL_L2 |
2533 SI_CONTEXT_FLUSH_AND_INV_CB |
2534 SI_CONTEXT_FLUSH_AND_INV_DB |
2535 SI_CONTEXT_CS_PARTIAL_FLUSH;
2536
2537 /* Take the maximum of the old and new count. If the new count is lower,
2538 * dirtying is needed to disable the unbound colorbuffers.
2539 */
2540 sctx->framebuffer.dirty_cbufs |=
2541 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2542 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2543
2544 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2545 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2546
2547 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2548 sctx->framebuffer.spi_shader_col_format = 0;
2549 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2550 sctx->framebuffer.spi_shader_col_format_blend = 0;
2551 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2552 sctx->framebuffer.color_is_int8 = 0;
2553 sctx->framebuffer.color_is_int10 = 0;
2554
2555 sctx->framebuffer.compressed_cb_mask = 0;
2556 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2557 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2558 sctx->framebuffer.any_dst_linear = false;
2559
2560 for (i = 0; i < state->nr_cbufs; i++) {
2561 if (!state->cbufs[i])
2562 continue;
2563
2564 surf = (struct r600_surface*)state->cbufs[i];
2565 rtex = (struct r600_texture*)surf->base.texture;
2566
2567 if (!surf->color_initialized) {
2568 si_initialize_color_surface(sctx, surf);
2569 }
2570
2571 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2572 sctx->framebuffer.spi_shader_col_format |=
2573 surf->spi_shader_col_format << (i * 4);
2574 sctx->framebuffer.spi_shader_col_format_alpha |=
2575 surf->spi_shader_col_format_alpha << (i * 4);
2576 sctx->framebuffer.spi_shader_col_format_blend |=
2577 surf->spi_shader_col_format_blend << (i * 4);
2578 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2579 surf->spi_shader_col_format_blend_alpha << (i * 4);
2580
2581 if (surf->color_is_int8)
2582 sctx->framebuffer.color_is_int8 |= 1 << i;
2583 if (surf->color_is_int10)
2584 sctx->framebuffer.color_is_int10 |= 1 << i;
2585
2586 if (rtex->fmask.size) {
2587 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2588 }
2589
2590 if (rtex->surface.is_linear)
2591 sctx->framebuffer.any_dst_linear = true;
2592
2593 r600_context_add_resource_size(ctx, surf->base.texture);
2594
2595 p_atomic_inc(&rtex->framebuffers_bound);
2596
2597 if (rtex->dcc_gather_statistics) {
2598 /* Dirty tracking must be enabled for DCC usage analysis. */
2599 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2600 vi_separate_dcc_start_query(ctx, rtex);
2601 }
2602 }
2603
2604 if (state->zsbuf) {
2605 surf = (struct r600_surface*)state->zsbuf;
2606 rtex = (struct r600_texture*)surf->base.texture;
2607
2608 if (!surf->depth_initialized) {
2609 si_init_depth_surface(sctx, surf);
2610 }
2611 r600_context_add_resource_size(ctx, surf->base.texture);
2612 }
2613
2614 si_update_poly_offset_state(sctx);
2615 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2616 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2617
2618 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2619 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2620
2621 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2622 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2623 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2624
2625 /* Set sample locations as fragment shader constants. */
2626 switch (sctx->framebuffer.nr_samples) {
2627 case 1:
2628 constbuf.user_buffer = sctx->b.sample_locations_1x;
2629 break;
2630 case 2:
2631 constbuf.user_buffer = sctx->b.sample_locations_2x;
2632 break;
2633 case 4:
2634 constbuf.user_buffer = sctx->b.sample_locations_4x;
2635 break;
2636 case 8:
2637 constbuf.user_buffer = sctx->b.sample_locations_8x;
2638 break;
2639 case 16:
2640 constbuf.user_buffer = sctx->b.sample_locations_16x;
2641 break;
2642 default:
2643 R600_ERR("Requested an invalid number of samples %i.\n",
2644 sctx->framebuffer.nr_samples);
2645 assert(0);
2646 }
2647 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2648 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2649
2650 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2651 }
2652
2653 sctx->do_update_shaders = true;
2654
2655 if (!sctx->decompression_enabled) {
2656 /* Prevent textures decompression when the framebuffer state
2657 * changes come from the decompression passes themselves.
2658 */
2659 sctx->need_check_render_feedback = true;
2660 sctx->framebuffer.do_update_surf_dirtiness = true;
2661 }
2662 }
2663
2664 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2665 {
2666 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2667 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2668 unsigned i, nr_cbufs = state->nr_cbufs;
2669 struct r600_texture *tex = NULL;
2670 struct r600_surface *cb = NULL;
2671 unsigned cb_color_info = 0;
2672
2673 /* Colorbuffers. */
2674 for (i = 0; i < nr_cbufs; i++) {
2675 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2676 unsigned cb_color_attrib;
2677
2678 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2679 continue;
2680
2681 cb = (struct r600_surface*)state->cbufs[i];
2682 if (!cb) {
2683 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2684 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2685 continue;
2686 }
2687
2688 tex = (struct r600_texture *)cb->base.texture;
2689 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2690 &tex->resource, RADEON_USAGE_READWRITE,
2691 tex->resource.b.b.nr_samples > 1 ?
2692 RADEON_PRIO_COLOR_BUFFER_MSAA :
2693 RADEON_PRIO_COLOR_BUFFER);
2694
2695 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2696 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2697 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2698 RADEON_PRIO_CMASK);
2699 }
2700
2701 if (tex->dcc_separate_buffer)
2702 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2703 tex->dcc_separate_buffer,
2704 RADEON_USAGE_READWRITE,
2705 RADEON_PRIO_DCC);
2706
2707 /* Compute mutable surface parameters. */
2708 cb_color_base = tex->resource.gpu_address >> 8;
2709 cb_color_fmask = cb_color_base;
2710 cb_dcc_base = 0;
2711 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2712 cb_color_attrib = cb->cb_color_attrib;
2713
2714 if (tex->fmask.size)
2715 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2716
2717 /* Set up DCC. */
2718 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2719 bool is_msaa_resolve_dst = state->cbufs[0] &&
2720 state->cbufs[0]->texture->nr_samples > 1 &&
2721 state->cbufs[1] == &cb->base &&
2722 state->cbufs[1]->texture->nr_samples <= 1;
2723
2724 if (!is_msaa_resolve_dst)
2725 cb_color_info |= S_028C70_DCC_ENABLE(1);
2726
2727 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2728 tex->dcc_offset) >> 8;
2729 }
2730
2731 if (sctx->b.chip_class >= GFX9) {
2732 struct gfx9_surf_meta_flags meta;
2733
2734 if (tex->dcc_offset)
2735 meta = tex->surface.u.gfx9.dcc;
2736 else
2737 meta = tex->surface.u.gfx9.cmask;
2738
2739 /* Set mutable surface parameters. */
2740 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2741 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2742 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2743 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2744 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2745
2746 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2747 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2748 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2749 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2750 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2751 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2752 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2753 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2754 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2755 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2756 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2757 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2758 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2759 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2760 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2761 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2762
2763 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2764 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2765 } else {
2766 /* Compute mutable surface parameters (SI-CI-VI). */
2767 const struct legacy_surf_level *level_info =
2768 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2769 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2770 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2771
2772 cb_color_base += level_info->offset >> 8;
2773 if (cb_dcc_base)
2774 cb_dcc_base += level_info->dcc_offset >> 8;
2775
2776 pitch_tile_max = level_info->nblk_x / 8 - 1;
2777 slice_tile_max = level_info->nblk_x *
2778 level_info->nblk_y / 64 - 1;
2779 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2780
2781 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2782 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2783 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2784
2785 if (tex->fmask.size) {
2786 if (sctx->b.chip_class >= CIK)
2787 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2788 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2789 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2790 } else {
2791 /* This must be set for fast clear to work without FMASK. */
2792 if (sctx->b.chip_class >= CIK)
2793 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2794 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2795 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2796 }
2797
2798 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2799 sctx->b.chip_class >= VI ? 14 : 13);
2800 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2801 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2802 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2803 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2804 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2805 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2806 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2807 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2808 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2809 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2810 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2811 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2812 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2813
2814 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2815 radeon_emit(cs, cb_dcc_base);
2816 }
2817 }
2818 for (; i < 8 ; i++)
2819 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2820 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2821
2822 /* ZS buffer. */
2823 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2824 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2825 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2826
2827 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2828 &rtex->resource, RADEON_USAGE_READWRITE,
2829 zb->base.texture->nr_samples > 1 ?
2830 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2831 RADEON_PRIO_DEPTH_BUFFER);
2832
2833 if (sctx->b.chip_class >= GFX9) {
2834 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2835 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2836 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2837 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2838
2839 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2840 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2841 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2842 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2843 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2844 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2845 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2846 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2847 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2848 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2849 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2850 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2851
2852 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2853 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2854 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2855 } else {
2856 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2857
2858 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2859 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2860 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2861 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2862 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2863 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2864 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2865 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2866 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2867 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2868 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2869 }
2870
2871 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2872 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2873 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2874
2875 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2876 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2877 } else if (sctx->framebuffer.dirty_zsbuf) {
2878 if (sctx->b.chip_class >= GFX9)
2879 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2880 else
2881 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2882
2883 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2884 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2885 }
2886
2887 /* Framebuffer dimensions. */
2888 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2889 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2890 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2891
2892 if (sctx->b.chip_class >= GFX9) {
2893 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2894 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2895 }
2896
2897 sctx->framebuffer.dirty_cbufs = 0;
2898 sctx->framebuffer.dirty_zsbuf = false;
2899 }
2900
2901 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2902 struct r600_atom *atom)
2903 {
2904 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2905 unsigned nr_samples = sctx->framebuffer.nr_samples;
2906 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2907
2908 /* Smoothing (only possible with nr_samples == 1) uses the same
2909 * sample locations as the MSAA it simulates.
2910 */
2911 if (nr_samples <= 1 && sctx->smoothing_enabled)
2912 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2913
2914 /* On Polaris, the small primitive filter uses the sample locations
2915 * even when MSAA is off, so we need to make sure they're set to 0.
2916 */
2917 if (has_msaa_sample_loc_bug)
2918 nr_samples = MAX2(nr_samples, 1);
2919
2920 if (nr_samples >= 1 &&
2921 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2922 sctx->msaa_sample_locs.nr_samples = nr_samples;
2923 cayman_emit_msaa_sample_locs(cs, nr_samples);
2924 }
2925
2926 if (sctx->b.family >= CHIP_POLARIS10) {
2927 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2928 unsigned small_prim_filter_cntl =
2929 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2930 /* line bug */
2931 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2932
2933 /* The alternative of setting sample locations to 0 would
2934 * require a DB flush to avoid Z errors, see
2935 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2936 */
2937 if (has_msaa_sample_loc_bug &&
2938 sctx->framebuffer.nr_samples > 1 &&
2939 rs && !rs->multisample_enable)
2940 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2941
2942 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2943 small_prim_filter_cntl);
2944 }
2945 }
2946
2947 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2948 {
2949 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2950 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2951 /* 33% faster rendering to linear color buffers */
2952 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2953 unsigned sc_mode_cntl_1 =
2954 S_028A4C_WALK_SIZE(dst_is_linear) |
2955 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2956 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2957 /* always 1: */
2958 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2959 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2960 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2961 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2962 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2963 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2964
2965 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2966 sctx->ps_iter_samples,
2967 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2968 sc_mode_cntl_1);
2969
2970 /* GFX9: Flush DFSM when the AA mode changes. */
2971 if (sctx->b.chip_class >= GFX9) {
2972 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2973 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2974 }
2975 }
2976
2977 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2978 {
2979 struct si_context *sctx = (struct si_context *)ctx;
2980
2981 if (sctx->ps_iter_samples == min_samples)
2982 return;
2983
2984 sctx->ps_iter_samples = min_samples;
2985 sctx->do_update_shaders = true;
2986
2987 if (sctx->framebuffer.nr_samples > 1)
2988 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2989 }
2990
2991 /*
2992 * Samplers
2993 */
2994
2995 /**
2996 * Build the sampler view descriptor for a buffer texture.
2997 * @param state 256-bit descriptor; only the high 128 bits are filled in
2998 */
2999 void
3000 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3001 enum pipe_format format,
3002 unsigned offset, unsigned size,
3003 uint32_t *state)
3004 {
3005 const struct util_format_description *desc;
3006 int first_non_void;
3007 unsigned stride;
3008 unsigned num_records;
3009 unsigned num_format, data_format;
3010
3011 desc = util_format_description(format);
3012 first_non_void = util_format_get_first_non_void_channel(format);
3013 stride = desc->block.bits / 8;
3014 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3015 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3016
3017 num_records = size / stride;
3018 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3019
3020 /* The NUM_RECORDS field has a different meaning depending on the chip,
3021 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3022 *
3023 * SI-CIK:
3024 * - If STRIDE == 0, it's in byte units.
3025 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3026 *
3027 * VI:
3028 * - For SMEM and STRIDE == 0, it's in byte units.
3029 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3030 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3031 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3032 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3033 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3034 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3035 * That way the same descriptor can be used by both SMEM and VMEM.
3036 *
3037 * GFX9:
3038 * - For SMEM and STRIDE == 0, it's in byte units.
3039 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3040 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3041 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3042 */
3043 if (screen->b.chip_class >= GFX9)
3044 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3045 * from STRIDE to bytes. This works around it by setting
3046 * NUM_RECORDS to at least the size of one element, so that
3047 * the first element is readable when IDXEN == 0.
3048 *
3049 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3050 * IDXEN is enforced?
3051 */
3052 num_records = num_records ? MAX2(num_records, stride) : 0;
3053 else if (screen->b.chip_class == VI)
3054 num_records *= stride;
3055
3056 state[4] = 0;
3057 state[5] = S_008F04_STRIDE(stride);
3058 state[6] = num_records;
3059 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3060 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3061 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3062 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3063 S_008F0C_NUM_FORMAT(num_format) |
3064 S_008F0C_DATA_FORMAT(data_format);
3065 }
3066
3067 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3068 {
3069 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3070
3071 if (swizzle[3] == PIPE_SWIZZLE_X) {
3072 /* For the pre-defined border color values (white, opaque
3073 * black, transparent black), the only thing that matters is
3074 * that the alpha channel winds up in the correct place
3075 * (because the RGB channels are all the same) so either of
3076 * these enumerations will work.
3077 */
3078 if (swizzle[2] == PIPE_SWIZZLE_Y)
3079 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3080 else
3081 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3082 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3083 if (swizzle[1] == PIPE_SWIZZLE_Y)
3084 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3085 else
3086 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3087 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3088 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3089 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3090 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3091 }
3092
3093 return bc_swizzle;
3094 }
3095
3096 /**
3097 * Build the sampler view descriptor for a texture.
3098 */
3099 void
3100 si_make_texture_descriptor(struct si_screen *screen,
3101 struct r600_texture *tex,
3102 bool sampler,
3103 enum pipe_texture_target target,
3104 enum pipe_format pipe_format,
3105 const unsigned char state_swizzle[4],
3106 unsigned first_level, unsigned last_level,
3107 unsigned first_layer, unsigned last_layer,
3108 unsigned width, unsigned height, unsigned depth,
3109 uint32_t *state,
3110 uint32_t *fmask_state)
3111 {
3112 struct pipe_resource *res = &tex->resource.b.b;
3113 const struct util_format_description *base_desc, *desc;
3114 unsigned char swizzle[4];
3115 int first_non_void;
3116 unsigned num_format, data_format, type;
3117 uint64_t va;
3118
3119 desc = util_format_description(pipe_format);
3120 base_desc = util_format_description(res->format);
3121
3122 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3123 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3124 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3125 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3126
3127 switch (pipe_format) {
3128 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3129 case PIPE_FORMAT_X32_S8X24_UINT:
3130 case PIPE_FORMAT_X8Z24_UNORM:
3131 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3132 break;
3133 case PIPE_FORMAT_X24S8_UINT:
3134 /*
3135 * X24S8 is implemented as an 8_8_8_8 data format, to
3136 * fix texture gathers. This affects at least
3137 * GL45-CTS.texture_cube_map_array.sampling on VI.
3138 */
3139 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3140 break;
3141 default:
3142 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3143 }
3144 } else {
3145 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3146 }
3147
3148 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3149
3150 switch (pipe_format) {
3151 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3152 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3153 break;
3154 default:
3155 if (first_non_void < 0) {
3156 if (util_format_is_compressed(pipe_format)) {
3157 switch (pipe_format) {
3158 case PIPE_FORMAT_DXT1_SRGB:
3159 case PIPE_FORMAT_DXT1_SRGBA:
3160 case PIPE_FORMAT_DXT3_SRGBA:
3161 case PIPE_FORMAT_DXT5_SRGBA:
3162 case PIPE_FORMAT_BPTC_SRGBA:
3163 case PIPE_FORMAT_ETC2_SRGB8:
3164 case PIPE_FORMAT_ETC2_SRGB8A1:
3165 case PIPE_FORMAT_ETC2_SRGBA8:
3166 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3167 break;
3168 case PIPE_FORMAT_RGTC1_SNORM:
3169 case PIPE_FORMAT_LATC1_SNORM:
3170 case PIPE_FORMAT_RGTC2_SNORM:
3171 case PIPE_FORMAT_LATC2_SNORM:
3172 case PIPE_FORMAT_ETC2_R11_SNORM:
3173 case PIPE_FORMAT_ETC2_RG11_SNORM:
3174 /* implies float, so use SNORM/UNORM to determine
3175 whether data is signed or not */
3176 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3177 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3178 break;
3179 default:
3180 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3181 break;
3182 }
3183 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3184 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3185 } else {
3186 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3187 }
3188 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3189 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3190 } else {
3191 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3192
3193 switch (desc->channel[first_non_void].type) {
3194 case UTIL_FORMAT_TYPE_FLOAT:
3195 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3196 break;
3197 case UTIL_FORMAT_TYPE_SIGNED:
3198 if (desc->channel[first_non_void].normalized)
3199 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3200 else if (desc->channel[first_non_void].pure_integer)
3201 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3202 else
3203 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3204 break;
3205 case UTIL_FORMAT_TYPE_UNSIGNED:
3206 if (desc->channel[first_non_void].normalized)
3207 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3208 else if (desc->channel[first_non_void].pure_integer)
3209 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3210 else
3211 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3212 }
3213 }
3214 }
3215
3216 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3217 if (data_format == ~0) {
3218 data_format = 0;
3219 }
3220
3221 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3222 if (screen->b.chip_class >= GFX9 &&
3223 util_format_has_depth(desc) &&
3224 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3225 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3226 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3227 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3228 }
3229
3230 if (!sampler &&
3231 (res->target == PIPE_TEXTURE_CUBE ||
3232 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3233 (screen->b.chip_class <= VI &&
3234 res->target == PIPE_TEXTURE_3D))) {
3235 /* For the purpose of shader images, treat cube maps and 3D
3236 * textures as 2D arrays. For 3D textures, the address
3237 * calculations for mipmaps are different, so we rely on the
3238 * caller to effectively disable mipmaps.
3239 */
3240 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3241
3242 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3243 } else {
3244 type = si_tex_dim(screen, tex, target, res->nr_samples);
3245 }
3246
3247 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3248 height = 1;
3249 depth = res->array_size;
3250 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3251 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3252 if (sampler || res->target != PIPE_TEXTURE_3D)
3253 depth = res->array_size;
3254 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3255 depth = res->array_size / 6;
3256
3257 state[0] = 0;
3258 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3259 S_008F14_NUM_FORMAT_GFX6(num_format));
3260 state[2] = (S_008F18_WIDTH(width - 1) |
3261 S_008F18_HEIGHT(height - 1) |
3262 S_008F18_PERF_MOD(4));
3263 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3264 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3265 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3266 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3267 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3268 0 : first_level) |
3269 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3270 util_logbase2(res->nr_samples) :
3271 last_level) |
3272 S_008F1C_TYPE(type));
3273 state[4] = 0;
3274 state[5] = S_008F24_BASE_ARRAY(first_layer);
3275 state[6] = 0;
3276 state[7] = 0;
3277
3278 if (screen->b.chip_class >= GFX9) {
3279 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3280
3281 /* Depth is the the last accessible layer on Gfx9.
3282 * The hw doesn't need to know the total number of layers.
3283 */
3284 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3285 state[4] |= S_008F20_DEPTH(depth - 1);
3286 else
3287 state[4] |= S_008F20_DEPTH(last_layer);
3288
3289 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3290 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3291 util_logbase2(res->nr_samples) :
3292 tex->resource.b.b.last_level);
3293 } else {
3294 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3295 state[4] |= S_008F20_DEPTH(depth - 1);
3296 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3297 }
3298
3299 if (tex->dcc_offset) {
3300 unsigned swap = r600_translate_colorswap(pipe_format, false);
3301
3302 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3303 } else {
3304 /* The last dword is unused by hw. The shader uses it to clear
3305 * bits in the first dword of sampler state.
3306 */
3307 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3308 if (first_level == last_level)
3309 state[7] = C_008F30_MAX_ANISO_RATIO;
3310 else
3311 state[7] = 0xffffffff;
3312 }
3313 }
3314
3315 /* Initialize the sampler view for FMASK. */
3316 if (tex->fmask.size) {
3317 uint32_t data_format, num_format;
3318
3319 va = tex->resource.gpu_address + tex->fmask.offset;
3320
3321 if (screen->b.chip_class >= GFX9) {
3322 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3323 switch (res->nr_samples) {
3324 case 2:
3325 num_format = V_008F14_IMG_FMASK_8_2_2;
3326 break;
3327 case 4:
3328 num_format = V_008F14_IMG_FMASK_8_4_4;
3329 break;
3330 case 8:
3331 num_format = V_008F14_IMG_FMASK_32_8_8;
3332 break;
3333 default:
3334 unreachable("invalid nr_samples");
3335 }
3336 } else {
3337 switch (res->nr_samples) {
3338 case 2:
3339 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3340 break;
3341 case 4:
3342 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3343 break;
3344 case 8:
3345 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3346 break;
3347 default:
3348 unreachable("invalid nr_samples");
3349 }
3350 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3351 }
3352
3353 fmask_state[0] = va >> 8;
3354 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3355 S_008F14_DATA_FORMAT_GFX6(data_format) |
3356 S_008F14_NUM_FORMAT_GFX6(num_format);
3357 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3358 S_008F18_HEIGHT(height - 1);
3359 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3360 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3361 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3362 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3363 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3364 fmask_state[4] = 0;
3365 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3366 fmask_state[6] = 0;
3367 fmask_state[7] = 0;
3368
3369 if (screen->b.chip_class >= GFX9) {
3370 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3371 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3372 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3373 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3374 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3375 } else {
3376 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3377 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3378 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3379 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3380 }
3381 }
3382 }
3383
3384 /**
3385 * Create a sampler view.
3386 *
3387 * @param ctx context
3388 * @param texture texture
3389 * @param state sampler view template
3390 * @param width0 width0 override (for compressed textures as int)
3391 * @param height0 height0 override (for compressed textures as int)
3392 * @param force_level set the base address to the level (for compressed textures)
3393 */
3394 struct pipe_sampler_view *
3395 si_create_sampler_view_custom(struct pipe_context *ctx,
3396 struct pipe_resource *texture,
3397 const struct pipe_sampler_view *state,
3398 unsigned width0, unsigned height0,
3399 unsigned force_level)
3400 {
3401 struct si_context *sctx = (struct si_context*)ctx;
3402 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3403 struct r600_texture *tmp = (struct r600_texture*)texture;
3404 unsigned base_level, first_level, last_level;
3405 unsigned char state_swizzle[4];
3406 unsigned height, depth, width;
3407 unsigned last_layer = state->u.tex.last_layer;
3408 enum pipe_format pipe_format;
3409 const struct legacy_surf_level *surflevel;
3410
3411 if (!view)
3412 return NULL;
3413
3414 /* initialize base object */
3415 view->base = *state;
3416 view->base.texture = NULL;
3417 view->base.reference.count = 1;
3418 view->base.context = ctx;
3419
3420 assert(texture);
3421 pipe_resource_reference(&view->base.texture, texture);
3422
3423 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3424 state->format == PIPE_FORMAT_S8X24_UINT ||
3425 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3426 state->format == PIPE_FORMAT_S8_UINT)
3427 view->is_stencil_sampler = true;
3428
3429 /* Buffer resource. */
3430 if (texture->target == PIPE_BUFFER) {
3431 si_make_buffer_descriptor(sctx->screen,
3432 (struct r600_resource *)texture,
3433 state->format,
3434 state->u.buf.offset,
3435 state->u.buf.size,
3436 view->state);
3437 return &view->base;
3438 }
3439
3440 state_swizzle[0] = state->swizzle_r;
3441 state_swizzle[1] = state->swizzle_g;
3442 state_swizzle[2] = state->swizzle_b;
3443 state_swizzle[3] = state->swizzle_a;
3444
3445 base_level = 0;
3446 first_level = state->u.tex.first_level;
3447 last_level = state->u.tex.last_level;
3448 width = width0;
3449 height = height0;
3450 depth = texture->depth0;
3451
3452 if (sctx->b.chip_class <= VI && force_level) {
3453 assert(force_level == first_level &&
3454 force_level == last_level);
3455 base_level = force_level;
3456 first_level = 0;
3457 last_level = 0;
3458 width = u_minify(width, force_level);
3459 height = u_minify(height, force_level);
3460 depth = u_minify(depth, force_level);
3461 }
3462
3463 /* This is not needed if state trackers set last_layer correctly. */
3464 if (state->target == PIPE_TEXTURE_1D ||
3465 state->target == PIPE_TEXTURE_2D ||
3466 state->target == PIPE_TEXTURE_RECT ||
3467 state->target == PIPE_TEXTURE_CUBE)
3468 last_layer = state->u.tex.first_layer;
3469
3470 /* Texturing with separate depth and stencil. */
3471 pipe_format = state->format;
3472
3473 /* Depth/stencil texturing sometimes needs separate texture. */
3474 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3475 if (!tmp->flushed_depth_texture &&
3476 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3477 pipe_resource_reference(&view->base.texture, NULL);
3478 FREE(view);
3479 return NULL;
3480 }
3481
3482 assert(tmp->flushed_depth_texture);
3483
3484 /* Override format for the case where the flushed texture
3485 * contains only Z or only S.
3486 */
3487 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3488 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3489
3490 tmp = tmp->flushed_depth_texture;
3491 }
3492
3493 surflevel = tmp->surface.u.legacy.level;
3494
3495 if (tmp->db_compatible) {
3496 if (!view->is_stencil_sampler)
3497 pipe_format = tmp->db_render_format;
3498
3499 switch (pipe_format) {
3500 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3501 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3502 break;
3503 case PIPE_FORMAT_X8Z24_UNORM:
3504 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3505 /* Z24 is always stored like this for DB
3506 * compatibility.
3507 */
3508 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3509 break;
3510 case PIPE_FORMAT_X24S8_UINT:
3511 case PIPE_FORMAT_S8X24_UINT:
3512 case PIPE_FORMAT_X32_S8X24_UINT:
3513 pipe_format = PIPE_FORMAT_S8_UINT;
3514 surflevel = tmp->surface.u.legacy.stencil_level;
3515 break;
3516 default:;
3517 }
3518 }
3519
3520 view->dcc_incompatible =
3521 vi_dcc_formats_are_incompatible(texture,
3522 state->u.tex.first_level,
3523 state->format);
3524
3525 si_make_texture_descriptor(sctx->screen, tmp, true,
3526 state->target, pipe_format, state_swizzle,
3527 first_level, last_level,
3528 state->u.tex.first_layer, last_layer,
3529 width, height, depth,
3530 view->state, view->fmask_state);
3531
3532 view->base_level_info = &surflevel[base_level];
3533 view->base_level = base_level;
3534 view->block_width = util_format_get_blockwidth(pipe_format);
3535 return &view->base;
3536 }
3537
3538 static struct pipe_sampler_view *
3539 si_create_sampler_view(struct pipe_context *ctx,
3540 struct pipe_resource *texture,
3541 const struct pipe_sampler_view *state)
3542 {
3543 return si_create_sampler_view_custom(ctx, texture, state,
3544 texture ? texture->width0 : 0,
3545 texture ? texture->height0 : 0, 0);
3546 }
3547
3548 static void si_sampler_view_destroy(struct pipe_context *ctx,
3549 struct pipe_sampler_view *state)
3550 {
3551 struct si_sampler_view *view = (struct si_sampler_view *)state;
3552
3553 pipe_resource_reference(&state->texture, NULL);
3554 FREE(view);
3555 }
3556
3557 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3558 {
3559 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3560 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3561 (linear_filter &&
3562 (wrap == PIPE_TEX_WRAP_CLAMP ||
3563 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3564 }
3565
3566 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3567 {
3568 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3569 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3570
3571 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3572 state->border_color.ui[2] || state->border_color.ui[3]) &&
3573 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3574 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3575 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3576 }
3577
3578 static void *si_create_sampler_state(struct pipe_context *ctx,
3579 const struct pipe_sampler_state *state)
3580 {
3581 struct si_context *sctx = (struct si_context *)ctx;
3582 struct r600_common_screen *rscreen = sctx->b.screen;
3583 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3584 unsigned border_color_type, border_color_index = 0;
3585 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3586 : state->max_anisotropy;
3587 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3588
3589 if (!rstate) {
3590 return NULL;
3591 }
3592
3593 if (!sampler_state_needs_border_color(state))
3594 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3595 else if (state->border_color.f[0] == 0 &&
3596 state->border_color.f[1] == 0 &&
3597 state->border_color.f[2] == 0 &&
3598 state->border_color.f[3] == 0)
3599 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3600 else if (state->border_color.f[0] == 0 &&
3601 state->border_color.f[1] == 0 &&
3602 state->border_color.f[2] == 0 &&
3603 state->border_color.f[3] == 1)
3604 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3605 else if (state->border_color.f[0] == 1 &&
3606 state->border_color.f[1] == 1 &&
3607 state->border_color.f[2] == 1 &&
3608 state->border_color.f[3] == 1)
3609 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3610 else {
3611 int i;
3612
3613 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3614
3615 /* Check if the border has been uploaded already. */
3616 for (i = 0; i < sctx->border_color_count; i++)
3617 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3618 sizeof(state->border_color)) == 0)
3619 break;
3620
3621 if (i >= SI_MAX_BORDER_COLORS) {
3622 /* Getting 4096 unique border colors is very unlikely. */
3623 fprintf(stderr, "radeonsi: The border color table is full. "
3624 "Any new border colors will be just black. "
3625 "Please file a bug.\n");
3626 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3627 } else {
3628 if (i == sctx->border_color_count) {
3629 /* Upload a new border color. */
3630 memcpy(&sctx->border_color_table[i], &state->border_color,
3631 sizeof(state->border_color));
3632 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3633 &state->border_color,
3634 sizeof(state->border_color));
3635 sctx->border_color_count++;
3636 }
3637
3638 border_color_index = i;
3639 }
3640 }
3641
3642 #ifdef DEBUG
3643 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3644 #endif
3645 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3646 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3647 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3648 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3649 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3650 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3651 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3652 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3653 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3654 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3655 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3656 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3657 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3658 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3659 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3660 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3661 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3662 S_008F38_MIP_POINT_PRECLAMP(1) |
3663 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3664 S_008F38_FILTER_PREC_FIX(1) |
3665 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3666 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3667 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3668 return rstate;
3669 }
3670
3671 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3672 {
3673 struct si_context *sctx = (struct si_context *)ctx;
3674
3675 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3676 return;
3677
3678 sctx->sample_mask.sample_mask = sample_mask;
3679 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3680 }
3681
3682 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3683 {
3684 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3685 unsigned mask = sctx->sample_mask.sample_mask;
3686
3687 /* Needed for line and polygon smoothing as well as for the Polaris
3688 * small primitive filter. We expect the state tracker to take care of
3689 * this for us.
3690 */
3691 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3692 (mask & 1 && sctx->blitter->running));
3693
3694 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3695 radeon_emit(cs, mask | (mask << 16));
3696 radeon_emit(cs, mask | (mask << 16));
3697 }
3698
3699 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3700 {
3701 #ifdef DEBUG
3702 struct si_sampler_state *s = state;
3703
3704 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3705 s->magic = 0;
3706 #endif
3707 free(state);
3708 }
3709
3710 /*
3711 * Vertex elements & buffers
3712 */
3713
3714 static void *si_create_vertex_elements(struct pipe_context *ctx,
3715 unsigned count,
3716 const struct pipe_vertex_element *elements)
3717 {
3718 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3719 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
3720 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3721 int i;
3722
3723 assert(count <= SI_MAX_ATTRIBS);
3724 if (!v)
3725 return NULL;
3726
3727 v->count = count;
3728 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3729
3730 for (i = 0; i < count; ++i) {
3731 const struct util_format_description *desc;
3732 const struct util_format_channel_description *channel;
3733 unsigned data_format, num_format;
3734 int first_non_void;
3735 unsigned vbo_index = elements[i].vertex_buffer_index;
3736 unsigned char swizzle[4];
3737
3738 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3739 FREE(v);
3740 return NULL;
3741 }
3742
3743 if (elements[i].instance_divisor) {
3744 v->uses_instance_divisors = true;
3745 v->instance_divisors[i] = elements[i].instance_divisor;
3746 }
3747
3748 if (!used[vbo_index]) {
3749 v->first_vb_use_mask |= 1 << i;
3750 used[vbo_index] = true;
3751 }
3752
3753 desc = util_format_description(elements[i].src_format);
3754 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3755 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3756 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3757 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3758 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3759
3760 v->format_size[i] = desc->block.bits / 8;
3761 v->src_offset[i] = elements[i].src_offset;
3762 v->vertex_buffer_index[i] = vbo_index;
3763
3764 /* The hardware always treats the 2-bit alpha channel as
3765 * unsigned, so a shader workaround is needed. The affected
3766 * chips are VI and older except Stoney (GFX8.1).
3767 */
3768 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3769 sscreen->b.chip_class <= VI &&
3770 sscreen->b.family != CHIP_STONEY) {
3771 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3772 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3773 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3774 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3775 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3776 /* This isn't actually used in OpenGL. */
3777 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3778 }
3779 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3780 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3781 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3782 else
3783 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3784 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3785 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3786 if (channel->normalized) {
3787 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3788 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3789 else
3790 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3791 } else {
3792 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3793 }
3794 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3795 if (channel->normalized) {
3796 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3797 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3798 else
3799 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3800 } else {
3801 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3802 }
3803 }
3804 } else if (channel && channel->size == 64 &&
3805 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3806 switch (desc->nr_channels) {
3807 case 1:
3808 case 2:
3809 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3810 swizzle[0] = PIPE_SWIZZLE_X;
3811 swizzle[1] = PIPE_SWIZZLE_Y;
3812 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3813 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3814 break;
3815 case 3:
3816 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3817 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3818 swizzle[1] = PIPE_SWIZZLE_Y;
3819 swizzle[2] = PIPE_SWIZZLE_0;
3820 swizzle[3] = PIPE_SWIZZLE_0;
3821 break;
3822 case 4:
3823 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3824 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3825 swizzle[1] = PIPE_SWIZZLE_Y;
3826 swizzle[2] = PIPE_SWIZZLE_Z;
3827 swizzle[3] = PIPE_SWIZZLE_W;
3828 break;
3829 default:
3830 assert(0);
3831 }
3832 } else if (channel && desc->nr_channels == 3) {
3833 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3834
3835 if (channel->size == 8) {
3836 if (channel->pure_integer)
3837 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3838 else
3839 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3840 } else if (channel->size == 16) {
3841 if (channel->pure_integer)
3842 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3843 else
3844 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3845 }
3846 }
3847
3848 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3849 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3850 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3851 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3852 S_008F0C_NUM_FORMAT(num_format) |
3853 S_008F0C_DATA_FORMAT(data_format);
3854 }
3855 return v;
3856 }
3857
3858 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3859 {
3860 struct si_context *sctx = (struct si_context *)ctx;
3861 struct si_vertex_elements *old = sctx->vertex_elements;
3862 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
3863
3864 sctx->vertex_elements = v;
3865 sctx->vertex_buffers_dirty = true;
3866
3867 if (v &&
3868 (!old ||
3869 old->count != v->count ||
3870 old->uses_instance_divisors != v->uses_instance_divisors ||
3871 v->uses_instance_divisors || /* we don't check which divisors changed */
3872 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
3873 sctx->do_update_shaders = true;
3874 }
3875
3876 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3877 {
3878 struct si_context *sctx = (struct si_context *)ctx;
3879
3880 if (sctx->vertex_elements == state)
3881 sctx->vertex_elements = NULL;
3882 FREE(state);
3883 }
3884
3885 static void si_set_vertex_buffers(struct pipe_context *ctx,
3886 unsigned start_slot, unsigned count,
3887 const struct pipe_vertex_buffer *buffers)
3888 {
3889 struct si_context *sctx = (struct si_context *)ctx;
3890 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3891 int i;
3892
3893 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3894
3895 if (buffers) {
3896 for (i = 0; i < count; i++) {
3897 const struct pipe_vertex_buffer *src = buffers + i;
3898 struct pipe_vertex_buffer *dsti = dst + i;
3899 struct pipe_resource *buf = src->buffer.resource;
3900
3901 pipe_resource_reference(&dsti->buffer.resource, buf);
3902 dsti->buffer_offset = src->buffer_offset;
3903 dsti->stride = src->stride;
3904 r600_context_add_resource_size(ctx, buf);
3905 if (buf)
3906 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3907 }
3908 } else {
3909 for (i = 0; i < count; i++) {
3910 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3911 }
3912 }
3913 sctx->vertex_buffers_dirty = true;
3914 }
3915
3916 /*
3917 * Misc
3918 */
3919
3920 static void si_set_tess_state(struct pipe_context *ctx,
3921 const float default_outer_level[4],
3922 const float default_inner_level[2])
3923 {
3924 struct si_context *sctx = (struct si_context *)ctx;
3925 struct pipe_constant_buffer cb;
3926 float array[8];
3927
3928 memcpy(array, default_outer_level, sizeof(float) * 4);
3929 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3930
3931 cb.buffer = NULL;
3932 cb.user_buffer = NULL;
3933 cb.buffer_size = sizeof(array);
3934
3935 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3936 (void*)array, sizeof(array),
3937 &cb.buffer_offset);
3938
3939 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3940 pipe_resource_reference(&cb.buffer, NULL);
3941 }
3942
3943 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3944 {
3945 struct si_context *sctx = (struct si_context *)ctx;
3946
3947 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3948 SI_CONTEXT_INV_GLOBAL_L2 |
3949 SI_CONTEXT_FLUSH_AND_INV_CB;
3950 sctx->framebuffer.do_update_surf_dirtiness = true;
3951 }
3952
3953 /* This only ensures coherency for shader image/buffer stores. */
3954 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3955 {
3956 struct si_context *sctx = (struct si_context *)ctx;
3957
3958 /* Subsequent commands must wait for all shader invocations to
3959 * complete. */
3960 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3961 SI_CONTEXT_CS_PARTIAL_FLUSH;
3962
3963 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3964 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3965 SI_CONTEXT_INV_VMEM_L1;
3966
3967 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3968 PIPE_BARRIER_SHADER_BUFFER |
3969 PIPE_BARRIER_TEXTURE |
3970 PIPE_BARRIER_IMAGE |
3971 PIPE_BARRIER_STREAMOUT_BUFFER |
3972 PIPE_BARRIER_GLOBAL_BUFFER)) {
3973 /* As far as I can tell, L1 contents are written back to L2
3974 * automatically at end of shader, but the contents of other
3975 * L1 caches might still be stale. */
3976 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3977 }
3978
3979 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3980 /* Indices are read through TC L2 since VI.
3981 * L1 isn't used.
3982 */
3983 if (sctx->screen->b.chip_class <= CIK)
3984 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3985 }
3986
3987 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3988 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3989 SI_CONTEXT_FLUSH_AND_INV_DB;
3990
3991 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3992 PIPE_BARRIER_INDIRECT_BUFFER))
3993 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3994 }
3995
3996 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3997 {
3998 struct pipe_blend_state blend;
3999
4000 memset(&blend, 0, sizeof(blend));
4001 blend.independent_blend_enable = true;
4002 blend.rt[0].colormask = 0xf;
4003 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4004 }
4005
4006 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4007 bool include_draw_vbo)
4008 {
4009 si_need_cs_space((struct si_context*)ctx);
4010 }
4011
4012 static void si_init_config(struct si_context *sctx);
4013
4014 void si_init_state_functions(struct si_context *sctx)
4015 {
4016 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4017 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4018 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4019 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4020 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4021
4022 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4023 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4024 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4025 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4026 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4027 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4028 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4029 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4030 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4031 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4032
4033 sctx->b.b.create_blend_state = si_create_blend_state;
4034 sctx->b.b.bind_blend_state = si_bind_blend_state;
4035 sctx->b.b.delete_blend_state = si_delete_blend_state;
4036 sctx->b.b.set_blend_color = si_set_blend_color;
4037
4038 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4039 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4040 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4041
4042 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4043 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4044 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4045
4046 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4047 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4048 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4049 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4050 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4051
4052 sctx->b.b.set_clip_state = si_set_clip_state;
4053 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4054
4055 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4056 sctx->b.b.get_sample_position = cayman_get_sample_position;
4057
4058 sctx->b.b.create_sampler_state = si_create_sampler_state;
4059 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4060
4061 sctx->b.b.create_sampler_view = si_create_sampler_view;
4062 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4063
4064 sctx->b.b.set_sample_mask = si_set_sample_mask;
4065
4066 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4067 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4068 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4069 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4070
4071 sctx->b.b.texture_barrier = si_texture_barrier;
4072 sctx->b.b.memory_barrier = si_memory_barrier;
4073 sctx->b.b.set_min_samples = si_set_min_samples;
4074 sctx->b.b.set_tess_state = si_set_tess_state;
4075
4076 sctx->b.b.set_active_query_state = si_set_active_query_state;
4077 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4078 sctx->b.save_qbo_state = si_save_qbo_state;
4079 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4080
4081 sctx->b.b.draw_vbo = si_draw_vbo;
4082
4083 si_init_config(sctx);
4084 }
4085
4086 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4087 {
4088 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4089 }
4090
4091 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4092 struct r600_texture *rtex,
4093 struct radeon_bo_metadata *md)
4094 {
4095 struct si_screen *sscreen = (struct si_screen*)rscreen;
4096 struct pipe_resource *res = &rtex->resource.b.b;
4097 static const unsigned char swizzle[] = {
4098 PIPE_SWIZZLE_X,
4099 PIPE_SWIZZLE_Y,
4100 PIPE_SWIZZLE_Z,
4101 PIPE_SWIZZLE_W
4102 };
4103 uint32_t desc[8], i;
4104 bool is_array = util_resource_is_array_texture(res);
4105
4106 /* DRM 2.x.x doesn't support this. */
4107 if (rscreen->info.drm_major != 3)
4108 return;
4109
4110 assert(rtex->dcc_separate_buffer == NULL);
4111 assert(rtex->fmask.size == 0);
4112
4113 /* Metadata image format format version 1:
4114 * [0] = 1 (metadata format identifier)
4115 * [1] = (VENDOR_ID << 16) | PCI_ID
4116 * [2:9] = image descriptor for the whole resource
4117 * [2] is always 0, because the base address is cleared
4118 * [9] is the DCC offset bits [39:8] from the beginning of
4119 * the buffer
4120 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4121 */
4122
4123 md->metadata[0] = 1; /* metadata image format version 1 */
4124
4125 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4126 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4127
4128 si_make_texture_descriptor(sscreen, rtex, true,
4129 res->target, res->format,
4130 swizzle, 0, res->last_level, 0,
4131 is_array ? res->array_size - 1 : 0,
4132 res->width0, res->height0, res->depth0,
4133 desc, NULL);
4134
4135 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4136 0, 0, rtex->surface.blk_w, false, desc);
4137
4138 /* Clear the base address and set the relative DCC offset. */
4139 desc[0] = 0;
4140 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4141 desc[7] = rtex->dcc_offset >> 8;
4142
4143 /* Dwords [2:9] contain the image descriptor. */
4144 memcpy(&md->metadata[2], desc, sizeof(desc));
4145 md->size_metadata = 10 * 4;
4146
4147 /* Dwords [10:..] contain the mipmap level offsets. */
4148 if (rscreen->chip_class <= VI) {
4149 for (i = 0; i <= res->last_level; i++)
4150 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4151
4152 md->size_metadata += (1 + res->last_level) * 4;
4153 }
4154 }
4155
4156 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4157 struct r600_texture *rtex,
4158 struct radeon_bo_metadata *md)
4159 {
4160 uint32_t *desc = &md->metadata[2];
4161
4162 if (rscreen->chip_class < VI)
4163 return;
4164
4165 /* Return if DCC is enabled. The texture should be set up with it
4166 * already.
4167 */
4168 if (md->size_metadata >= 11 * 4 &&
4169 md->metadata[0] != 0 &&
4170 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4171 G_008F28_COMPRESSION_EN(desc[6])) {
4172 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4173 return;
4174 }
4175
4176 /* Disable DCC. These are always set by texture_from_handle and must
4177 * be cleared here.
4178 */
4179 rtex->dcc_offset = 0;
4180 }
4181
4182 void si_init_screen_state_functions(struct si_screen *sscreen)
4183 {
4184 sscreen->b.b.is_format_supported = si_is_format_supported;
4185 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4186 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4187 }
4188
4189 static void
4190 si_write_harvested_raster_configs(struct si_context *sctx,
4191 struct si_pm4_state *pm4,
4192 unsigned raster_config,
4193 unsigned raster_config_1)
4194 {
4195 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4196 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4197 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4198 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4199 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4200 unsigned rb_per_se = num_rb / num_se;
4201 unsigned se_mask[4];
4202 unsigned se;
4203
4204 se_mask[0] = ((1 << rb_per_se) - 1);
4205 se_mask[1] = (se_mask[0] << rb_per_se);
4206 se_mask[2] = (se_mask[1] << rb_per_se);
4207 se_mask[3] = (se_mask[2] << rb_per_se);
4208
4209 se_mask[0] &= rb_mask;
4210 se_mask[1] &= rb_mask;
4211 se_mask[2] &= rb_mask;
4212 se_mask[3] &= rb_mask;
4213
4214 assert(num_se == 1 || num_se == 2 || num_se == 4);
4215 assert(sh_per_se == 1 || sh_per_se == 2);
4216 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4217
4218 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4219 * fields are for, so I'm leaving them as their default
4220 * values. */
4221
4222 for (se = 0; se < num_se; se++) {
4223 unsigned raster_config_se = raster_config;
4224 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4225 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4226 int idx = (se / 2) * 2;
4227
4228 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4229 raster_config_se &= C_028350_SE_MAP;
4230
4231 if (!se_mask[idx]) {
4232 raster_config_se |=
4233 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4234 } else {
4235 raster_config_se |=
4236 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4237 }
4238 }
4239
4240 pkr0_mask &= rb_mask;
4241 pkr1_mask &= rb_mask;
4242 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4243 raster_config_se &= C_028350_PKR_MAP;
4244
4245 if (!pkr0_mask) {
4246 raster_config_se |=
4247 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4248 } else {
4249 raster_config_se |=
4250 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4251 }
4252 }
4253
4254 if (rb_per_se >= 2) {
4255 unsigned rb0_mask = 1 << (se * rb_per_se);
4256 unsigned rb1_mask = rb0_mask << 1;
4257
4258 rb0_mask &= rb_mask;
4259 rb1_mask &= rb_mask;
4260 if (!rb0_mask || !rb1_mask) {
4261 raster_config_se &= C_028350_RB_MAP_PKR0;
4262
4263 if (!rb0_mask) {
4264 raster_config_se |=
4265 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4266 } else {
4267 raster_config_se |=
4268 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4269 }
4270 }
4271
4272 if (rb_per_se > 2) {
4273 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4274 rb1_mask = rb0_mask << 1;
4275 rb0_mask &= rb_mask;
4276 rb1_mask &= rb_mask;
4277 if (!rb0_mask || !rb1_mask) {
4278 raster_config_se &= C_028350_RB_MAP_PKR1;
4279
4280 if (!rb0_mask) {
4281 raster_config_se |=
4282 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4283 } else {
4284 raster_config_se |=
4285 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4286 }
4287 }
4288 }
4289 }
4290
4291 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4292 if (sctx->b.chip_class < CIK)
4293 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4294 SE_INDEX(se) | SH_BROADCAST_WRITES |
4295 INSTANCE_BROADCAST_WRITES);
4296 else
4297 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4298 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4299 S_030800_INSTANCE_BROADCAST_WRITES(1));
4300 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4301 }
4302
4303 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4304 if (sctx->b.chip_class < CIK)
4305 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4306 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4307 INSTANCE_BROADCAST_WRITES);
4308 else {
4309 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4310 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4311 S_030800_INSTANCE_BROADCAST_WRITES(1));
4312
4313 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4314 (!se_mask[2] && !se_mask[3]))) {
4315 raster_config_1 &= C_028354_SE_PAIR_MAP;
4316
4317 if (!se_mask[0] && !se_mask[1]) {
4318 raster_config_1 |=
4319 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4320 } else {
4321 raster_config_1 |=
4322 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4323 }
4324 }
4325
4326 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4327 }
4328 }
4329
4330 static void si_init_config(struct si_context *sctx)
4331 {
4332 struct si_screen *sscreen = sctx->screen;
4333 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4334 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4335 unsigned raster_config, raster_config_1;
4336 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4337 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4338
4339 if (!pm4)
4340 return;
4341
4342 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4343 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4344 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4345 si_pm4_cmd_end(pm4, false);
4346
4347 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4348 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4349
4350 /* FIXME calculate these values somehow ??? */
4351 if (sctx->b.chip_class <= VI) {
4352 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4353 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4354 }
4355 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4356
4357 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4358 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4359
4360 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4361 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4362 if (sctx->b.chip_class >= GFX9)
4363 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4364 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4365 if (sctx->b.chip_class < CIK)
4366 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4367 S_008A14_CLIP_VTX_REORDER_ENA(1));
4368
4369 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4370 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4371
4372 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4373
4374 switch (sctx->screen->b.family) {
4375 case CHIP_TAHITI:
4376 case CHIP_PITCAIRN:
4377 raster_config = 0x2a00126a;
4378 raster_config_1 = 0x00000000;
4379 break;
4380 case CHIP_VERDE:
4381 raster_config = 0x0000124a;
4382 raster_config_1 = 0x00000000;
4383 break;
4384 case CHIP_OLAND:
4385 raster_config = 0x00000082;
4386 raster_config_1 = 0x00000000;
4387 break;
4388 case CHIP_HAINAN:
4389 raster_config = 0x00000000;
4390 raster_config_1 = 0x00000000;
4391 break;
4392 case CHIP_BONAIRE:
4393 raster_config = 0x16000012;
4394 raster_config_1 = 0x00000000;
4395 break;
4396 case CHIP_HAWAII:
4397 raster_config = 0x3a00161a;
4398 raster_config_1 = 0x0000002e;
4399 break;
4400 case CHIP_FIJI:
4401 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4402 /* old kernels with old tiling config */
4403 raster_config = 0x16000012;
4404 raster_config_1 = 0x0000002a;
4405 } else {
4406 raster_config = 0x3a00161a;
4407 raster_config_1 = 0x0000002e;
4408 }
4409 break;
4410 case CHIP_POLARIS10:
4411 raster_config = 0x16000012;
4412 raster_config_1 = 0x0000002a;
4413 break;
4414 case CHIP_POLARIS11:
4415 case CHIP_POLARIS12:
4416 raster_config = 0x16000012;
4417 raster_config_1 = 0x00000000;
4418 break;
4419 case CHIP_TONGA:
4420 raster_config = 0x16000012;
4421 raster_config_1 = 0x0000002a;
4422 break;
4423 case CHIP_ICELAND:
4424 if (num_rb == 1)
4425 raster_config = 0x00000000;
4426 else
4427 raster_config = 0x00000002;
4428 raster_config_1 = 0x00000000;
4429 break;
4430 case CHIP_CARRIZO:
4431 raster_config = 0x00000002;
4432 raster_config_1 = 0x00000000;
4433 break;
4434 case CHIP_KAVERI:
4435 /* KV should be 0x00000002, but that causes problems with radeon */
4436 raster_config = 0x00000000; /* 0x00000002 */
4437 raster_config_1 = 0x00000000;
4438 break;
4439 case CHIP_KABINI:
4440 case CHIP_MULLINS:
4441 case CHIP_STONEY:
4442 raster_config = 0x00000000;
4443 raster_config_1 = 0x00000000;
4444 break;
4445 default:
4446 if (sctx->b.chip_class <= VI) {
4447 fprintf(stderr,
4448 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4449 raster_config = 0x00000000;
4450 raster_config_1 = 0x00000000;
4451 }
4452 break;
4453 }
4454
4455 if (sctx->b.chip_class <= VI) {
4456 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4457 /* Always use the default config when all backends are enabled
4458 * (or when we failed to determine the enabled backends).
4459 */
4460 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4461 raster_config);
4462 if (sctx->b.chip_class >= CIK)
4463 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4464 raster_config_1);
4465 } else {
4466 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4467 }
4468 }
4469
4470 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4471 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4472 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4473 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4474 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4475 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4476 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4477
4478 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4479 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4480 S_028230_ER_TRI(0xA) |
4481 S_028230_ER_POINT(0xA) |
4482 S_028230_ER_RECT(0xA) |
4483 /* Required by DX10_DIAMOND_TEST_ENA: */
4484 S_028230_ER_LINE_LR(0x1A) |
4485 S_028230_ER_LINE_RL(0x26) |
4486 S_028230_ER_LINE_TB(0xA) |
4487 S_028230_ER_LINE_BT(0xA));
4488 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4489 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4490 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4491 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4492 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4493 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4494 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4495
4496 if (sctx->b.chip_class >= GFX9) {
4497 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4498 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4499 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4500 } else {
4501 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4502 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4503 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4504 }
4505
4506 if (sctx->b.chip_class >= CIK) {
4507 if (sctx->b.chip_class >= GFX9) {
4508 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4509 } else {
4510 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4511 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4512 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4513
4514 /* If this is 0, Bonaire can hang even if GS isn't being used.
4515 * Other chips are unaffected. These are suboptimal values,
4516 * but we don't use on-chip GS.
4517 */
4518 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4519 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4520 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4521 }
4522 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4523
4524 if (sscreen->b.info.num_good_compute_units /
4525 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4526 /* Too few available compute units per SH. Disallowing
4527 * VS to run on CU0 could hurt us more than late VS
4528 * allocation would help.
4529 *
4530 * LATE_ALLOC_VS = 2 is the highest safe number.
4531 */
4532 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4533 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4534 } else {
4535 /* Set LATE_ALLOC_VS == 31. It should be less than
4536 * the number of scratch waves. Limitations:
4537 * - VS can't execute on CU0.
4538 * - If HS writes outputs to LDS, LS can't execute on CU0.
4539 */
4540 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4541 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4542 }
4543
4544 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4545 }
4546
4547 if (sctx->b.chip_class >= VI) {
4548 unsigned vgt_tess_distribution;
4549
4550 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4551 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4552 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4553 if (sctx->b.family < CHIP_POLARIS10)
4554 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4555 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4556
4557 vgt_tess_distribution =
4558 S_028B50_ACCUM_ISOLINE(32) |
4559 S_028B50_ACCUM_TRI(11) |
4560 S_028B50_ACCUM_QUAD(11) |
4561 S_028B50_DONUT_SPLIT(16);
4562
4563 /* Testing with Unigine Heaven extreme tesselation yielded best results
4564 * with TRAP_SPLIT = 3.
4565 */
4566 if (sctx->b.family == CHIP_FIJI ||
4567 sctx->b.family >= CHIP_POLARIS10)
4568 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4569
4570 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4571 } else {
4572 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4573 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4574 }
4575
4576 if (sctx->screen->b.has_rbplus)
4577 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4578
4579 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4580 if (sctx->b.chip_class >= CIK)
4581 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4582 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4583 RADEON_PRIO_BORDER_COLORS);
4584
4585 if (sctx->b.chip_class >= GFX9) {
4586 unsigned num_se = sscreen->b.info.max_se;
4587 unsigned pc_lines = 0;
4588
4589 switch (sctx->b.family) {
4590 case CHIP_VEGA10:
4591 pc_lines = 4096;
4592 break;
4593 case CHIP_RAVEN:
4594 pc_lines = 1024;
4595 break;
4596 default:
4597 assert(0);
4598 }
4599
4600 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4601 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4602 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4603 /* TODO: We can use this to disable RBs for rendering to GART: */
4604 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4605 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4606 /* TODO: Enable the binner: */
4607 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4608 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4609 S_028C44_DISABLE_START_OF_PRIM(1));
4610 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4611 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4612 S_028C48_MAX_PRIM_PER_BATCH(1023));
4613 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4614 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4615 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4616 }
4617
4618 si_pm4_upload_indirect_buffer(sctx, pm4);
4619 sctx->init_config = pm4;
4620 }