projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: add checks for a NULL pixel shader
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend->dual_src_blend &&
269 sctx->ps_shader.cso &&
270 (sctx->ps_shader.cso->ps_colors_written & 0x3) != 0x3)
271 mask = 0;
272
273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
274 }
275
276 /*
277 * Blender functions
278 */
279
280 static uint32_t si_translate_blend_function(int blend_func)
281 {
282 switch (blend_func) {
283 case PIPE_BLEND_ADD:
284 return V_028780_COMB_DST_PLUS_SRC;
285 case PIPE_BLEND_SUBTRACT:
286 return V_028780_COMB_SRC_MINUS_DST;
287 case PIPE_BLEND_REVERSE_SUBTRACT:
288 return V_028780_COMB_DST_MINUS_SRC;
289 case PIPE_BLEND_MIN:
290 return V_028780_COMB_MIN_DST_SRC;
291 case PIPE_BLEND_MAX:
292 return V_028780_COMB_MAX_DST_SRC;
293 default:
294 R600_ERR("Unknown blend function %d\n", blend_func);
295 assert(0);
296 break;
297 }
298 return 0;
299 }
300
301 static uint32_t si_translate_blend_factor(int blend_fact)
302 {
303 switch (blend_fact) {
304 case PIPE_BLENDFACTOR_ONE:
305 return V_028780_BLEND_ONE;
306 case PIPE_BLENDFACTOR_SRC_COLOR:
307 return V_028780_BLEND_SRC_COLOR;
308 case PIPE_BLENDFACTOR_SRC_ALPHA:
309 return V_028780_BLEND_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case PIPE_BLENDFACTOR_DST_COLOR:
313 return V_028780_BLEND_DST_COLOR;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE;
316 case PIPE_BLENDFACTOR_CONST_COLOR:
317 return V_028780_BLEND_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_CONST_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_ZERO:
321 return V_028780_BLEND_ZERO;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
334 case PIPE_BLENDFACTOR_SRC1_COLOR:
335 return V_028780_BLEND_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA:
337 return V_028780_BLEND_SRC1_ALPHA;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
339 return V_028780_BLEND_INV_SRC1_COLOR;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
341 return V_028780_BLEND_INV_SRC1_ALPHA;
342 default:
343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
344 assert(0);
345 break;
346 }
347 return 0;
348 }
349
350 static void *si_create_blend_state_mode(struct pipe_context *ctx,
351 const struct pipe_blend_state *state,
352 unsigned mode)
353 {
354 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
355 struct si_pm4_state *pm4 = &blend->pm4;
356
357 uint32_t color_control = 0;
358
359 if (blend == NULL)
360 return NULL;
361
362 blend->alpha_to_one = state->alpha_to_one;
363 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
364
365 if (state->logicop_enable) {
366 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
367 } else {
368 color_control |= S_028808_ROP3(0xcc);
369 }
370
371 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
372 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
373 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
374 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
375 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
376 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
377
378 blend->cb_target_mask = 0;
379 for (int i = 0; i < 8; i++) {
380 /* state->rt entries > 0 only written if independent blending */
381 const int j = state->independent_blend_enable ? i : 0;
382
383 unsigned eqRGB = state->rt[j].rgb_func;
384 unsigned srcRGB = state->rt[j].rgb_src_factor;
385 unsigned dstRGB = state->rt[j].rgb_dst_factor;
386 unsigned eqA = state->rt[j].alpha_func;
387 unsigned srcA = state->rt[j].alpha_src_factor;
388 unsigned dstA = state->rt[j].alpha_dst_factor;
389
390 unsigned blend_cntl = 0;
391
392 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
393 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
394
395 if (!state->rt[j].blend_enable) {
396 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
397 continue;
398 }
399
400 blend_cntl |= S_028780_ENABLE(1);
401 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
402 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
403 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
404
405 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
406 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
407 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
408 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
409 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
410 }
411 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
412 }
413
414 if (blend->cb_target_mask) {
415 color_control |= S_028808_MODE(mode);
416 } else {
417 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
418 }
419 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
420
421 return blend;
422 }
423
424 static void *si_create_blend_state(struct pipe_context *ctx,
425 const struct pipe_blend_state *state)
426 {
427 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
428 }
429
430 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
431 {
432 struct si_context *sctx = (struct si_context *)ctx;
433 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
434 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
435 }
436
437 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
438 {
439 struct si_context *sctx = (struct si_context *)ctx;
440 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
441 }
442
443 static void si_set_blend_color(struct pipe_context *ctx,
444 const struct pipe_blend_color *state)
445 {
446 struct si_context *sctx = (struct si_context *)ctx;
447
448 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
449 return;
450
451 sctx->blend_color.state = *state;
452 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
453 }
454
455 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
456 {
457 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
458
459 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
460 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
461 }
462
463 /*
464 * Clipping, scissors and viewport
465 */
466
467 static void si_set_clip_state(struct pipe_context *ctx,
468 const struct pipe_clip_state *state)
469 {
470 struct si_context *sctx = (struct si_context *)ctx;
471 struct pipe_constant_buffer cb;
472
473 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
474 return;
475
476 sctx->clip_state.state = *state;
477 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
478
479 cb.buffer = NULL;
480 cb.user_buffer = state->ucp;
481 cb.buffer_offset = 0;
482 cb.buffer_size = 4*4*8;
483 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
484 pipe_resource_reference(&cb.buffer, NULL);
485 }
486
487 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
488 {
489 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
490
491 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
492 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
493 }
494
495 #define SIX_BITS 0x3F
496
497 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
498 {
499 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
500 struct tgsi_shader_info *info = si_get_vs_info(sctx);
501 unsigned window_space =
502 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
503 unsigned clipdist_mask =
504 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
505
506 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
507 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
508 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
509 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
510 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
511 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
512 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
513 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
514 info->writes_edgeflag ||
515 info->writes_layer ||
516 info->writes_viewport_index) |
517 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
518 (sctx->queued.named.rasterizer->clip_plane_enable &
519 clipdist_mask));
520 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
521 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
522 (clipdist_mask ? 0 :
523 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
524 S_028810_CLIP_DISABLE(window_space));
525 }
526
527 static void si_set_scissor_states(struct pipe_context *ctx,
528 unsigned start_slot,
529 unsigned num_scissors,
530 const struct pipe_scissor_state *state)
531 {
532 struct si_context *sctx = (struct si_context *)ctx;
533 int i;
534
535 for (i = 0; i < num_scissors; i++)
536 sctx->scissors.states[start_slot + i] = state[i];
537
538 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
539 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
540 }
541
542 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
543 {
544 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
545 struct pipe_scissor_state *states = sctx->scissors.states;
546 unsigned mask = sctx->scissors.dirty_mask;
547
548 /* The simple case: Only 1 viewport is active. */
549 if (mask & 1 &&
550 !si_get_vs_info(sctx)->writes_viewport_index) {
551 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
552 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
553 S_028250_TL_Y(states[0].miny) |
554 S_028250_WINDOW_OFFSET_DISABLE(1));
555 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
556 S_028254_BR_Y(states[0].maxy));
557 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
558 return;
559 }
560
561 while (mask) {
562 int start, count, i;
563
564 u_bit_scan_consecutive_range(&mask, &start, &count);
565
566 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
567 start * 4 * 2, count * 2);
568 for (i = start; i < start+count; i++) {
569 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
570 S_028250_TL_Y(states[i].miny) |
571 S_028250_WINDOW_OFFSET_DISABLE(1));
572 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
573 S_028254_BR_Y(states[i].maxy));
574 }
575 }
576 sctx->scissors.dirty_mask = 0;
577 }
578
579 static void si_set_viewport_states(struct pipe_context *ctx,
580 unsigned start_slot,
581 unsigned num_viewports,
582 const struct pipe_viewport_state *state)
583 {
584 struct si_context *sctx = (struct si_context *)ctx;
585 int i;
586
587 for (i = 0; i < num_viewports; i++)
588 sctx->viewports.states[start_slot + i] = state[i];
589
590 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
591 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
592 }
593
594 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
595 {
596 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
597 struct pipe_viewport_state *states = sctx->viewports.states;
598 unsigned mask = sctx->viewports.dirty_mask;
599
600 /* The simple case: Only 1 viewport is active. */
601 if (mask & 1 &&
602 !si_get_vs_info(sctx)->writes_viewport_index) {
603 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
604 radeon_emit(cs, fui(states[0].scale[0]));
605 radeon_emit(cs, fui(states[0].translate[0]));
606 radeon_emit(cs, fui(states[0].scale[1]));
607 radeon_emit(cs, fui(states[0].translate[1]));
608 radeon_emit(cs, fui(states[0].scale[2]));
609 radeon_emit(cs, fui(states[0].translate[2]));
610 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
611 return;
612 }
613
614 while (mask) {
615 int start, count, i;
616
617 u_bit_scan_consecutive_range(&mask, &start, &count);
618
619 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
620 start * 4 * 6, count * 6);
621 for (i = start; i < start+count; i++) {
622 radeon_emit(cs, fui(states[i].scale[0]));
623 radeon_emit(cs, fui(states[i].translate[0]));
624 radeon_emit(cs, fui(states[i].scale[1]));
625 radeon_emit(cs, fui(states[i].translate[1]));
626 radeon_emit(cs, fui(states[i].scale[2]));
627 radeon_emit(cs, fui(states[i].translate[2]));
628 }
629 }
630 sctx->viewports.dirty_mask = 0;
631 }
632
633 /*
634 * inferred state between framebuffer and rasterizer
635 */
636 static void si_update_poly_offset_state(struct si_context *sctx)
637 {
638 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
639
640 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
641 return;
642
643 switch (sctx->framebuffer.state.zsbuf->texture->format) {
644 case PIPE_FORMAT_Z16_UNORM:
645 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
646 break;
647 default: /* 24-bit */
648 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
649 break;
650 case PIPE_FORMAT_Z32_FLOAT:
651 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
652 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
653 break;
654 }
655 }
656
657 /*
658 * Rasterizer
659 */
660
661 static uint32_t si_translate_fill(uint32_t func)
662 {
663 switch(func) {
664 case PIPE_POLYGON_MODE_FILL:
665 return V_028814_X_DRAW_TRIANGLES;
666 case PIPE_POLYGON_MODE_LINE:
667 return V_028814_X_DRAW_LINES;
668 case PIPE_POLYGON_MODE_POINT:
669 return V_028814_X_DRAW_POINTS;
670 default:
671 assert(0);
672 return V_028814_X_DRAW_POINTS;
673 }
674 }
675
676 static void *si_create_rs_state(struct pipe_context *ctx,
677 const struct pipe_rasterizer_state *state)
678 {
679 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
680 struct si_pm4_state *pm4 = &rs->pm4;
681 unsigned tmp, i;
682 float psize_min, psize_max;
683
684 if (rs == NULL) {
685 return NULL;
686 }
687
688 rs->two_side = state->light_twoside;
689 rs->multisample_enable = state->multisample;
690 rs->force_persample_interp = state->force_persample_interp;
691 rs->clip_plane_enable = state->clip_plane_enable;
692 rs->line_stipple_enable = state->line_stipple_enable;
693 rs->poly_stipple_enable = state->poly_stipple_enable;
694 rs->line_smooth = state->line_smooth;
695 rs->poly_smooth = state->poly_smooth;
696 rs->uses_poly_offset = state->offset_point || state->offset_line ||
697 state->offset_tri;
698 rs->clamp_fragment_color = state->clamp_fragment_color;
699 rs->flatshade = state->flatshade;
700 rs->sprite_coord_enable = state->sprite_coord_enable;
701 rs->pa_sc_line_stipple = state->line_stipple_enable ?
702 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
703 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
704 rs->pa_cl_clip_cntl =
705 S_028810_PS_UCP_MODE(3) |
706 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
707 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
708 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
709 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
710 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
711
712 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
713 S_0286D4_FLAT_SHADE_ENA(1) |
714 S_0286D4_PNT_SPRITE_ENA(1) |
715 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
716 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
717 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
718 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
719 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
720
721 /* point size 12.4 fixed point */
722 tmp = (unsigned)(state->point_size * 8.0);
723 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
724
725 if (state->point_size_per_vertex) {
726 psize_min = util_get_min_point_size(state);
727 psize_max = 8192;
728 } else {
729 /* Force the point size to be as if the vertex output was disabled. */
730 psize_min = state->point_size;
731 psize_max = state->point_size;
732 }
733 /* Divide by two, because 0.5 = 1 pixel. */
734 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
735 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
736 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
737
738 tmp = (unsigned)state->line_width * 8;
739 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
740 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
741 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
742 S_028A48_MSAA_ENABLE(state->multisample ||
743 state->poly_smooth ||
744 state->line_smooth) |
745 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
746
747 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
748 S_028BE4_PIX_CENTER(state->half_pixel_center) |
749 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
750
751 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
752 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
753 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
754 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
755 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
756 S_028814_FACE(!state->front_ccw) |
757 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
758 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
759 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
760 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
761 state->fill_back != PIPE_POLYGON_MODE_FILL) |
762 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
763 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
764 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
765 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
766
767 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
768 for (i = 0; i < 3; i++) {
769 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
770 float offset_units = state->offset_units;
771 float offset_scale = state->offset_scale * 16.0f;
772
773 switch (i) {
774 case 0: /* 16-bit zbuffer */
775 offset_units *= 4.0f;
776 break;
777 case 1: /* 24-bit zbuffer */
778 offset_units *= 2.0f;
779 break;
780 case 2: /* 32-bit zbuffer */
781 offset_units *= 1.0f;
782 break;
783 }
784
785 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
786 fui(offset_scale));
787 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
788 fui(offset_units));
789 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
790 fui(offset_scale));
791 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
792 fui(offset_units));
793 }
794
795 return rs;
796 }
797
798 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
799 {
800 struct si_context *sctx = (struct si_context *)ctx;
801 struct si_state_rasterizer *old_rs =
802 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
803 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
804
805 if (state == NULL)
806 return;
807
808 if (sctx->framebuffer.nr_samples > 1 &&
809 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
810 si_mark_atom_dirty(sctx, &sctx->db_render_state);
811
812 si_pm4_bind_state(sctx, rasterizer, rs);
813 si_update_poly_offset_state(sctx);
814
815 si_mark_atom_dirty(sctx, &sctx->clip_regs);
816 }
817
818 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
819 {
820 struct si_context *sctx = (struct si_context *)ctx;
821
822 if (sctx->queued.named.rasterizer == state)
823 si_pm4_bind_state(sctx, poly_offset, NULL);
824 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
825 }
826
827 /*
828 * infeered state between dsa and stencil ref
829 */
830 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
831 {
832 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
833 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
834 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
835
836 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
837 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
838 S_028430_STENCILMASK(dsa->valuemask[0]) |
839 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
840 S_028430_STENCILOPVAL(1));
841 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
842 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
843 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
844 S_028434_STENCILOPVAL_BF(1));
845 }
846
847 static void si_set_stencil_ref(struct pipe_context *ctx,
848 const struct pipe_stencil_ref *state)
849 {
850 struct si_context *sctx = (struct si_context *)ctx;
851
852 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
853 return;
854
855 sctx->stencil_ref.state = *state;
856 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
857 }
858
859
860 /*
861 * DSA
862 */
863
864 static uint32_t si_translate_stencil_op(int s_op)
865 {
866 switch (s_op) {
867 case PIPE_STENCIL_OP_KEEP:
868 return V_02842C_STENCIL_KEEP;
869 case PIPE_STENCIL_OP_ZERO:
870 return V_02842C_STENCIL_ZERO;
871 case PIPE_STENCIL_OP_REPLACE:
872 return V_02842C_STENCIL_REPLACE_TEST;
873 case PIPE_STENCIL_OP_INCR:
874 return V_02842C_STENCIL_ADD_CLAMP;
875 case PIPE_STENCIL_OP_DECR:
876 return V_02842C_STENCIL_SUB_CLAMP;
877 case PIPE_STENCIL_OP_INCR_WRAP:
878 return V_02842C_STENCIL_ADD_WRAP;
879 case PIPE_STENCIL_OP_DECR_WRAP:
880 return V_02842C_STENCIL_SUB_WRAP;
881 case PIPE_STENCIL_OP_INVERT:
882 return V_02842C_STENCIL_INVERT;
883 default:
884 R600_ERR("Unknown stencil op %d", s_op);
885 assert(0);
886 break;
887 }
888 return 0;
889 }
890
891 static void *si_create_dsa_state(struct pipe_context *ctx,
892 const struct pipe_depth_stencil_alpha_state *state)
893 {
894 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
895 struct si_pm4_state *pm4 = &dsa->pm4;
896 unsigned db_depth_control;
897 uint32_t db_stencil_control = 0;
898
899 if (dsa == NULL) {
900 return NULL;
901 }
902
903 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
904 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
905 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
906 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
907
908 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
909 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
910 S_028800_ZFUNC(state->depth.func) |
911 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
912
913 /* stencil */
914 if (state->stencil[0].enabled) {
915 db_depth_control |= S_028800_STENCIL_ENABLE(1);
916 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
917 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
918 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
919 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
920
921 if (state->stencil[1].enabled) {
922 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
923 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
924 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
925 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
926 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
927 }
928 }
929
930 /* alpha */
931 if (state->alpha.enabled) {
932 dsa->alpha_func = state->alpha.func;
933
934 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
935 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
936 } else {
937 dsa->alpha_func = PIPE_FUNC_ALWAYS;
938 }
939
940 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
941 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
942 if (state->depth.bounds_test) {
943 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
944 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
945 }
946
947 return dsa;
948 }
949
950 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
951 {
952 struct si_context *sctx = (struct si_context *)ctx;
953 struct si_state_dsa *dsa = state;
954
955 if (state == NULL)
956 return;
957
958 si_pm4_bind_state(sctx, dsa, dsa);
959
960 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
961 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
962 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
963 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
964 }
965 }
966
967 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
968 {
969 struct si_context *sctx = (struct si_context *)ctx;
970 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
971 }
972
973 static void *si_create_db_flush_dsa(struct si_context *sctx)
974 {
975 struct pipe_depth_stencil_alpha_state dsa = {};
976
977 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
978 }
979
980 /* DB RENDER STATE */
981
982 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
983 {
984 struct si_context *sctx = (struct si_context*)ctx;
985
986 si_mark_atom_dirty(sctx, &sctx->db_render_state);
987 }
988
989 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
990 {
991 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
992 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
993 unsigned db_shader_control;
994
995 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
996
997 /* DB_RENDER_CONTROL */
998 if (sctx->dbcb_depth_copy_enabled ||
999 sctx->dbcb_stencil_copy_enabled) {
1000 radeon_emit(cs,
1001 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1002 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1003 S_028000_COPY_CENTROID(1) |
1004 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1005 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1006 radeon_emit(cs,
1007 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1008 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1009 } else if (sctx->db_depth_clear) {
1010 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1011 } else {
1012 radeon_emit(cs, 0);
1013 }
1014
1015 /* DB_COUNT_CONTROL (occlusion queries) */
1016 if (sctx->b.num_occlusion_queries > 0) {
1017 if (sctx->b.chip_class >= CIK) {
1018 radeon_emit(cs,
1019 S_028004_PERFECT_ZPASS_COUNTS(1) |
1020 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1021 S_028004_ZPASS_ENABLE(1) |
1022 S_028004_SLICE_EVEN_ENABLE(1) |
1023 S_028004_SLICE_ODD_ENABLE(1));
1024 } else {
1025 radeon_emit(cs,
1026 S_028004_PERFECT_ZPASS_COUNTS(1) |
1027 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1028 }
1029 } else {
1030 /* Disable occlusion queries. */
1031 if (sctx->b.chip_class >= CIK) {
1032 radeon_emit(cs, 0);
1033 } else {
1034 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1035 }
1036 }
1037
1038 /* DB_RENDER_OVERRIDE2 */
1039 if (sctx->db_depth_disable_expclear) {
1040 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1041 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1042 } else {
1043 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1044 }
1045
1046 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1047 sctx->ps_db_shader_control;
1048
1049 /* Bug workaround for smoothing (overrasterization) on SI. */
1050 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1051 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1052 else
1053 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1054
1055 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1056 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1057 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1058
1059 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1060 db_shader_control);
1061 }
1062
1063 /*
1064 * format translation
1065 */
1066 static uint32_t si_translate_colorformat(enum pipe_format format)
1067 {
1068 const struct util_format_description *desc = util_format_description(format);
1069
1070 #define HAS_SIZE(x,y,z,w) \
1071 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1072 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1073
1074 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1075 return V_028C70_COLOR_10_11_11;
1076
1077 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1078 return V_028C70_COLOR_INVALID;
1079
1080 switch (desc->nr_channels) {
1081 case 1:
1082 switch (desc->channel[0].size) {
1083 case 8:
1084 return V_028C70_COLOR_8;
1085 case 16:
1086 return V_028C70_COLOR_16;
1087 case 32:
1088 return V_028C70_COLOR_32;
1089 }
1090 break;
1091 case 2:
1092 if (desc->channel[0].size == desc->channel[1].size) {
1093 switch (desc->channel[0].size) {
1094 case 8:
1095 return V_028C70_COLOR_8_8;
1096 case 16:
1097 return V_028C70_COLOR_16_16;
1098 case 32:
1099 return V_028C70_COLOR_32_32;
1100 }
1101 } else if (HAS_SIZE(8,24,0,0)) {
1102 return V_028C70_COLOR_24_8;
1103 } else if (HAS_SIZE(24,8,0,0)) {
1104 return V_028C70_COLOR_8_24;
1105 }
1106 break;
1107 case 3:
1108 if (HAS_SIZE(5,6,5,0)) {
1109 return V_028C70_COLOR_5_6_5;
1110 } else if (HAS_SIZE(32,8,24,0)) {
1111 return V_028C70_COLOR_X24_8_32_FLOAT;
1112 }
1113 break;
1114 case 4:
1115 if (desc->channel[0].size == desc->channel[1].size &&
1116 desc->channel[0].size == desc->channel[2].size &&
1117 desc->channel[0].size == desc->channel[3].size) {
1118 switch (desc->channel[0].size) {
1119 case 4:
1120 return V_028C70_COLOR_4_4_4_4;
1121 case 8:
1122 return V_028C70_COLOR_8_8_8_8;
1123 case 16:
1124 return V_028C70_COLOR_16_16_16_16;
1125 case 32:
1126 return V_028C70_COLOR_32_32_32_32;
1127 }
1128 } else if (HAS_SIZE(5,5,5,1)) {
1129 return V_028C70_COLOR_1_5_5_5;
1130 } else if (HAS_SIZE(10,10,10,2)) {
1131 return V_028C70_COLOR_2_10_10_10;
1132 }
1133 break;
1134 }
1135 return V_028C70_COLOR_INVALID;
1136 }
1137
1138 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1139 {
1140 if (SI_BIG_ENDIAN) {
1141 switch(colorformat) {
1142 /* 8-bit buffers. */
1143 case V_028C70_COLOR_8:
1144 return V_028C70_ENDIAN_NONE;
1145
1146 /* 16-bit buffers. */
1147 case V_028C70_COLOR_5_6_5:
1148 case V_028C70_COLOR_1_5_5_5:
1149 case V_028C70_COLOR_4_4_4_4:
1150 case V_028C70_COLOR_16:
1151 case V_028C70_COLOR_8_8:
1152 return V_028C70_ENDIAN_8IN16;
1153
1154 /* 32-bit buffers. */
1155 case V_028C70_COLOR_8_8_8_8:
1156 case V_028C70_COLOR_2_10_10_10:
1157 case V_028C70_COLOR_8_24:
1158 case V_028C70_COLOR_24_8:
1159 case V_028C70_COLOR_16_16:
1160 return V_028C70_ENDIAN_8IN32;
1161
1162 /* 64-bit buffers. */
1163 case V_028C70_COLOR_16_16_16_16:
1164 return V_028C70_ENDIAN_8IN16;
1165
1166 case V_028C70_COLOR_32_32:
1167 return V_028C70_ENDIAN_8IN32;
1168
1169 /* 128-bit buffers. */
1170 case V_028C70_COLOR_32_32_32_32:
1171 return V_028C70_ENDIAN_8IN32;
1172 default:
1173 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1174 }
1175 } else {
1176 return V_028C70_ENDIAN_NONE;
1177 }
1178 }
1179
1180 /* Returns the size in bits of the widest component of a CB format */
1181 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1182 {
1183 switch(colorformat) {
1184 case V_028C70_COLOR_4_4_4_4:
1185 return 4;
1186
1187 case V_028C70_COLOR_1_5_5_5:
1188 case V_028C70_COLOR_5_5_5_1:
1189 return 5;
1190
1191 case V_028C70_COLOR_5_6_5:
1192 return 6;
1193
1194 case V_028C70_COLOR_8:
1195 case V_028C70_COLOR_8_8:
1196 case V_028C70_COLOR_8_8_8_8:
1197 return 8;
1198
1199 case V_028C70_COLOR_10_10_10_2:
1200 case V_028C70_COLOR_2_10_10_10:
1201 return 10;
1202
1203 case V_028C70_COLOR_10_11_11:
1204 case V_028C70_COLOR_11_11_10:
1205 return 11;
1206
1207 case V_028C70_COLOR_16:
1208 case V_028C70_COLOR_16_16:
1209 case V_028C70_COLOR_16_16_16_16:
1210 return 16;
1211
1212 case V_028C70_COLOR_8_24:
1213 case V_028C70_COLOR_24_8:
1214 return 24;
1215
1216 case V_028C70_COLOR_32:
1217 case V_028C70_COLOR_32_32:
1218 case V_028C70_COLOR_32_32_32_32:
1219 case V_028C70_COLOR_X24_8_32_FLOAT:
1220 return 32;
1221 }
1222
1223 assert(!"Unknown maximum component size");
1224 return 0;
1225 }
1226
1227 static uint32_t si_translate_dbformat(enum pipe_format format)
1228 {
1229 switch (format) {
1230 case PIPE_FORMAT_Z16_UNORM:
1231 return V_028040_Z_16;
1232 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1233 case PIPE_FORMAT_X8Z24_UNORM:
1234 case PIPE_FORMAT_Z24X8_UNORM:
1235 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1236 return V_028040_Z_24; /* deprecated on SI */
1237 case PIPE_FORMAT_Z32_FLOAT:
1238 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1239 return V_028040_Z_32_FLOAT;
1240 default:
1241 return V_028040_Z_INVALID;
1242 }
1243 }
1244
1245 /*
1246 * Texture translation
1247 */
1248
1249 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1250 enum pipe_format format,
1251 const struct util_format_description *desc,
1252 int first_non_void)
1253 {
1254 struct si_screen *sscreen = (struct si_screen*)screen;
1255 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1256 sscreen->b.info.drm_minor >= 31) ||
1257 sscreen->b.info.drm_major == 3;
1258 boolean uniform = TRUE;
1259 int i;
1260
1261 /* Colorspace (return non-RGB formats directly). */
1262 switch (desc->colorspace) {
1263 /* Depth stencil formats */
1264 case UTIL_FORMAT_COLORSPACE_ZS:
1265 switch (format) {
1266 case PIPE_FORMAT_Z16_UNORM:
1267 return V_008F14_IMG_DATA_FORMAT_16;
1268 case PIPE_FORMAT_X24S8_UINT:
1269 case PIPE_FORMAT_Z24X8_UNORM:
1270 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1271 return V_008F14_IMG_DATA_FORMAT_8_24;
1272 case PIPE_FORMAT_X8Z24_UNORM:
1273 case PIPE_FORMAT_S8X24_UINT:
1274 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1275 return V_008F14_IMG_DATA_FORMAT_24_8;
1276 case PIPE_FORMAT_S8_UINT:
1277 return V_008F14_IMG_DATA_FORMAT_8;
1278 case PIPE_FORMAT_Z32_FLOAT:
1279 return V_008F14_IMG_DATA_FORMAT_32;
1280 case PIPE_FORMAT_X32_S8X24_UINT:
1281 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1282 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1283 default:
1284 goto out_unknown;
1285 }
1286
1287 case UTIL_FORMAT_COLORSPACE_YUV:
1288 goto out_unknown; /* TODO */
1289
1290 case UTIL_FORMAT_COLORSPACE_SRGB:
1291 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1292 goto out_unknown;
1293 break;
1294
1295 default:
1296 break;
1297 }
1298
1299 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1300 if (!enable_compressed_formats)
1301 goto out_unknown;
1302
1303 switch (format) {
1304 case PIPE_FORMAT_RGTC1_SNORM:
1305 case PIPE_FORMAT_LATC1_SNORM:
1306 case PIPE_FORMAT_RGTC1_UNORM:
1307 case PIPE_FORMAT_LATC1_UNORM:
1308 return V_008F14_IMG_DATA_FORMAT_BC4;
1309 case PIPE_FORMAT_RGTC2_SNORM:
1310 case PIPE_FORMAT_LATC2_SNORM:
1311 case PIPE_FORMAT_RGTC2_UNORM:
1312 case PIPE_FORMAT_LATC2_UNORM:
1313 return V_008F14_IMG_DATA_FORMAT_BC5;
1314 default:
1315 goto out_unknown;
1316 }
1317 }
1318
1319 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1320 if (!enable_compressed_formats)
1321 goto out_unknown;
1322
1323 switch (format) {
1324 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1325 case PIPE_FORMAT_BPTC_SRGBA:
1326 return V_008F14_IMG_DATA_FORMAT_BC7;
1327 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1328 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1329 return V_008F14_IMG_DATA_FORMAT_BC6;
1330 default:
1331 goto out_unknown;
1332 }
1333 }
1334
1335 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1336 switch (format) {
1337 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1338 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1339 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1340 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1341 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1342 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1343 default:
1344 goto out_unknown;
1345 }
1346 }
1347
1348 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1349 if (!enable_compressed_formats)
1350 goto out_unknown;
1351
1352 if (!util_format_s3tc_enabled) {
1353 goto out_unknown;
1354 }
1355
1356 switch (format) {
1357 case PIPE_FORMAT_DXT1_RGB:
1358 case PIPE_FORMAT_DXT1_RGBA:
1359 case PIPE_FORMAT_DXT1_SRGB:
1360 case PIPE_FORMAT_DXT1_SRGBA:
1361 return V_008F14_IMG_DATA_FORMAT_BC1;
1362 case PIPE_FORMAT_DXT3_RGBA:
1363 case PIPE_FORMAT_DXT3_SRGBA:
1364 return V_008F14_IMG_DATA_FORMAT_BC2;
1365 case PIPE_FORMAT_DXT5_RGBA:
1366 case PIPE_FORMAT_DXT5_SRGBA:
1367 return V_008F14_IMG_DATA_FORMAT_BC3;
1368 default:
1369 goto out_unknown;
1370 }
1371 }
1372
1373 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1374 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1375 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1376 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1377 }
1378
1379 /* R8G8Bx_SNORM - TODO CxV8U8 */
1380
1381 /* See whether the components are of the same size. */
1382 for (i = 1; i < desc->nr_channels; i++) {
1383 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1384 }
1385
1386 /* Non-uniform formats. */
1387 if (!uniform) {
1388 switch(desc->nr_channels) {
1389 case 3:
1390 if (desc->channel[0].size == 5 &&
1391 desc->channel[1].size == 6 &&
1392 desc->channel[2].size == 5) {
1393 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1394 }
1395 goto out_unknown;
1396 case 4:
1397 if (desc->channel[0].size == 5 &&
1398 desc->channel[1].size == 5 &&
1399 desc->channel[2].size == 5 &&
1400 desc->channel[3].size == 1) {
1401 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1402 }
1403 if (desc->channel[0].size == 10 &&
1404 desc->channel[1].size == 10 &&
1405 desc->channel[2].size == 10 &&
1406 desc->channel[3].size == 2) {
1407 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1408 }
1409 goto out_unknown;
1410 }
1411 goto out_unknown;
1412 }
1413
1414 if (first_non_void < 0 || first_non_void > 3)
1415 goto out_unknown;
1416
1417 /* uniform formats */
1418 switch (desc->channel[first_non_void].size) {
1419 case 4:
1420 switch (desc->nr_channels) {
1421 #if 0 /* Not supported for render targets */
1422 case 2:
1423 return V_008F14_IMG_DATA_FORMAT_4_4;
1424 #endif
1425 case 4:
1426 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1427 }
1428 break;
1429 case 8:
1430 switch (desc->nr_channels) {
1431 case 1:
1432 return V_008F14_IMG_DATA_FORMAT_8;
1433 case 2:
1434 return V_008F14_IMG_DATA_FORMAT_8_8;
1435 case 4:
1436 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1437 }
1438 break;
1439 case 16:
1440 switch (desc->nr_channels) {
1441 case 1:
1442 return V_008F14_IMG_DATA_FORMAT_16;
1443 case 2:
1444 return V_008F14_IMG_DATA_FORMAT_16_16;
1445 case 4:
1446 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1447 }
1448 break;
1449 case 32:
1450 switch (desc->nr_channels) {
1451 case 1:
1452 return V_008F14_IMG_DATA_FORMAT_32;
1453 case 2:
1454 return V_008F14_IMG_DATA_FORMAT_32_32;
1455 #if 0 /* Not supported for render targets */
1456 case 3:
1457 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1458 #endif
1459 case 4:
1460 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1461 }
1462 }
1463
1464 out_unknown:
1465 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1466 return ~0;
1467 }
1468
1469 static unsigned si_tex_wrap(unsigned wrap)
1470 {
1471 switch (wrap) {
1472 default:
1473 case PIPE_TEX_WRAP_REPEAT:
1474 return V_008F30_SQ_TEX_WRAP;
1475 case PIPE_TEX_WRAP_CLAMP:
1476 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1477 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1478 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1479 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1480 return V_008F30_SQ_TEX_CLAMP_BORDER;
1481 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1482 return V_008F30_SQ_TEX_MIRROR;
1483 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1484 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1485 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1486 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1487 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1488 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1489 }
1490 }
1491
1492 static unsigned si_tex_filter(unsigned filter)
1493 {
1494 switch (filter) {
1495 default:
1496 case PIPE_TEX_FILTER_NEAREST:
1497 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1498 case PIPE_TEX_FILTER_LINEAR:
1499 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1500 }
1501 }
1502
1503 static unsigned si_tex_mipfilter(unsigned filter)
1504 {
1505 switch (filter) {
1506 case PIPE_TEX_MIPFILTER_NEAREST:
1507 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1508 case PIPE_TEX_MIPFILTER_LINEAR:
1509 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1510 default:
1511 case PIPE_TEX_MIPFILTER_NONE:
1512 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1513 }
1514 }
1515
1516 static unsigned si_tex_compare(unsigned compare)
1517 {
1518 switch (compare) {
1519 default:
1520 case PIPE_FUNC_NEVER:
1521 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1522 case PIPE_FUNC_LESS:
1523 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1524 case PIPE_FUNC_EQUAL:
1525 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1526 case PIPE_FUNC_LEQUAL:
1527 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1528 case PIPE_FUNC_GREATER:
1529 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1530 case PIPE_FUNC_NOTEQUAL:
1531 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1532 case PIPE_FUNC_GEQUAL:
1533 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1534 case PIPE_FUNC_ALWAYS:
1535 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1536 }
1537 }
1538
1539 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1540 unsigned nr_samples)
1541 {
1542 if (view_target == PIPE_TEXTURE_CUBE ||
1543 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1544 res_target = view_target;
1545
1546 switch (res_target) {
1547 default:
1548 case PIPE_TEXTURE_1D:
1549 return V_008F1C_SQ_RSRC_IMG_1D;
1550 case PIPE_TEXTURE_1D_ARRAY:
1551 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1552 case PIPE_TEXTURE_2D:
1553 case PIPE_TEXTURE_RECT:
1554 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1555 V_008F1C_SQ_RSRC_IMG_2D;
1556 case PIPE_TEXTURE_2D_ARRAY:
1557 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1558 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1559 case PIPE_TEXTURE_3D:
1560 return V_008F1C_SQ_RSRC_IMG_3D;
1561 case PIPE_TEXTURE_CUBE:
1562 case PIPE_TEXTURE_CUBE_ARRAY:
1563 return V_008F1C_SQ_RSRC_IMG_CUBE;
1564 }
1565 }
1566
1567 /*
1568 * Format support testing
1569 */
1570
1571 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1572 {
1573 return si_translate_texformat(screen, format, util_format_description(format),
1574 util_format_get_first_non_void_channel(format)) != ~0U;
1575 }
1576
1577 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1578 const struct util_format_description *desc,
1579 int first_non_void)
1580 {
1581 unsigned type = desc->channel[first_non_void].type;
1582 int i;
1583
1584 if (type == UTIL_FORMAT_TYPE_FIXED)
1585 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1586
1587 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1588 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1589
1590 if (desc->nr_channels == 4 &&
1591 desc->channel[0].size == 10 &&
1592 desc->channel[1].size == 10 &&
1593 desc->channel[2].size == 10 &&
1594 desc->channel[3].size == 2)
1595 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1596
1597 /* See whether the components are of the same size. */
1598 for (i = 0; i < desc->nr_channels; i++) {
1599 if (desc->channel[first_non_void].size != desc->channel[i].size)
1600 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1601 }
1602
1603 switch (desc->channel[first_non_void].size) {
1604 case 8:
1605 switch (desc->nr_channels) {
1606 case 1:
1607 return V_008F0C_BUF_DATA_FORMAT_8;
1608 case 2:
1609 return V_008F0C_BUF_DATA_FORMAT_8_8;
1610 case 3:
1611 case 4:
1612 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1613 }
1614 break;
1615 case 16:
1616 switch (desc->nr_channels) {
1617 case 1:
1618 return V_008F0C_BUF_DATA_FORMAT_16;
1619 case 2:
1620 return V_008F0C_BUF_DATA_FORMAT_16_16;
1621 case 3:
1622 case 4:
1623 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1624 }
1625 break;
1626 case 32:
1627 /* From the Southern Islands ISA documentation about MTBUF:
1628 * 'Memory reads of data in memory that is 32 or 64 bits do not
1629 * undergo any format conversion.'
1630 */
1631 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1632 !desc->channel[first_non_void].pure_integer)
1633 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1634
1635 switch (desc->nr_channels) {
1636 case 1:
1637 return V_008F0C_BUF_DATA_FORMAT_32;
1638 case 2:
1639 return V_008F0C_BUF_DATA_FORMAT_32_32;
1640 case 3:
1641 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1642 case 4:
1643 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1644 }
1645 break;
1646 }
1647
1648 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1649 }
1650
1651 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1652 const struct util_format_description *desc,
1653 int first_non_void)
1654 {
1655 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1656 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1657
1658 switch (desc->channel[first_non_void].type) {
1659 case UTIL_FORMAT_TYPE_SIGNED:
1660 if (desc->channel[first_non_void].normalized)
1661 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1662 else if (desc->channel[first_non_void].pure_integer)
1663 return V_008F0C_BUF_NUM_FORMAT_SINT;
1664 else
1665 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1666 break;
1667 case UTIL_FORMAT_TYPE_UNSIGNED:
1668 if (desc->channel[first_non_void].normalized)
1669 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1670 else if (desc->channel[first_non_void].pure_integer)
1671 return V_008F0C_BUF_NUM_FORMAT_UINT;
1672 else
1673 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1674 break;
1675 case UTIL_FORMAT_TYPE_FLOAT:
1676 default:
1677 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1678 }
1679 }
1680
1681 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1682 {
1683 const struct util_format_description *desc;
1684 int first_non_void;
1685 unsigned data_format;
1686
1687 desc = util_format_description(format);
1688 first_non_void = util_format_get_first_non_void_channel(format);
1689 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1690 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1691 }
1692
1693 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1694 {
1695 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1696 r600_translate_colorswap(format) != ~0U;
1697 }
1698
1699 static bool si_is_zs_format_supported(enum pipe_format format)
1700 {
1701 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1702 }
1703
1704 boolean si_is_format_supported(struct pipe_screen *screen,
1705 enum pipe_format format,
1706 enum pipe_texture_target target,
1707 unsigned sample_count,
1708 unsigned usage)
1709 {
1710 unsigned retval = 0;
1711
1712 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1713 R600_ERR("r600: unsupported texture type %d\n", target);
1714 return FALSE;
1715 }
1716
1717 if (!util_format_is_supported(format, usage))
1718 return FALSE;
1719
1720 if (sample_count > 1) {
1721 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1722 return FALSE;
1723
1724 switch (sample_count) {
1725 case 2:
1726 case 4:
1727 case 8:
1728 break;
1729 default:
1730 return FALSE;
1731 }
1732 }
1733
1734 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1735 if (target == PIPE_BUFFER) {
1736 if (si_is_vertex_format_supported(screen, format))
1737 retval |= PIPE_BIND_SAMPLER_VIEW;
1738 } else {
1739 if (si_is_sampler_format_supported(screen, format))
1740 retval |= PIPE_BIND_SAMPLER_VIEW;
1741 }
1742 }
1743
1744 if ((usage & (PIPE_BIND_RENDER_TARGET |
1745 PIPE_BIND_DISPLAY_TARGET |
1746 PIPE_BIND_SCANOUT |
1747 PIPE_BIND_SHARED |
1748 PIPE_BIND_BLENDABLE)) &&
1749 si_is_colorbuffer_format_supported(format)) {
1750 retval |= usage &
1751 (PIPE_BIND_RENDER_TARGET |
1752 PIPE_BIND_DISPLAY_TARGET |
1753 PIPE_BIND_SCANOUT |
1754 PIPE_BIND_SHARED);
1755 if (!util_format_is_pure_integer(format) &&
1756 !util_format_is_depth_or_stencil(format))
1757 retval |= usage & PIPE_BIND_BLENDABLE;
1758 }
1759
1760 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1761 si_is_zs_format_supported(format)) {
1762 retval |= PIPE_BIND_DEPTH_STENCIL;
1763 }
1764
1765 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1766 si_is_vertex_format_supported(screen, format)) {
1767 retval |= PIPE_BIND_VERTEX_BUFFER;
1768 }
1769
1770 if (usage & PIPE_BIND_TRANSFER_READ)
1771 retval |= PIPE_BIND_TRANSFER_READ;
1772 if (usage & PIPE_BIND_TRANSFER_WRITE)
1773 retval |= PIPE_BIND_TRANSFER_WRITE;
1774
1775 return retval == usage;
1776 }
1777
1778 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1779 {
1780 unsigned tile_mode_index = 0;
1781
1782 if (stencil) {
1783 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1784 } else {
1785 tile_mode_index = rtex->surface.tiling_index[level];
1786 }
1787 return tile_mode_index;
1788 }
1789
1790 /*
1791 * framebuffer handling
1792 */
1793
1794 static void si_initialize_color_surface(struct si_context *sctx,
1795 struct r600_surface *surf)
1796 {
1797 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1798 unsigned level = surf->base.u.tex.level;
1799 uint64_t offset = rtex->surface.level[level].offset;
1800 unsigned pitch, slice;
1801 unsigned color_info, color_attrib, color_pitch, color_view;
1802 unsigned tile_mode_index;
1803 unsigned format, swap, ntype, endian;
1804 const struct util_format_description *desc;
1805 int i;
1806 unsigned blend_clamp = 0, blend_bypass = 0;
1807 unsigned max_comp_size;
1808
1809 /* Layered rendering doesn't work with LINEAR_GENERAL.
1810 * (LINEAR_ALIGNED and others work) */
1811 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1812 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1813 offset += rtex->surface.level[level].slice_size *
1814 surf->base.u.tex.first_layer;
1815 color_view = 0;
1816 } else {
1817 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1818 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1819 }
1820
1821 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1822 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1823 if (slice) {
1824 slice = slice - 1;
1825 }
1826
1827 tile_mode_index = si_tile_mode_index(rtex, level, false);
1828
1829 desc = util_format_description(surf->base.format);
1830 for (i = 0; i < 4; i++) {
1831 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1832 break;
1833 }
1834 }
1835 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1836 ntype = V_028C70_NUMBER_FLOAT;
1837 } else {
1838 ntype = V_028C70_NUMBER_UNORM;
1839 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1840 ntype = V_028C70_NUMBER_SRGB;
1841 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1842 if (desc->channel[i].pure_integer) {
1843 ntype = V_028C70_NUMBER_SINT;
1844 } else {
1845 assert(desc->channel[i].normalized);
1846 ntype = V_028C70_NUMBER_SNORM;
1847 }
1848 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1849 if (desc->channel[i].pure_integer) {
1850 ntype = V_028C70_NUMBER_UINT;
1851 } else {
1852 assert(desc->channel[i].normalized);
1853 ntype = V_028C70_NUMBER_UNORM;
1854 }
1855 }
1856 }
1857
1858 format = si_translate_colorformat(surf->base.format);
1859 if (format == V_028C70_COLOR_INVALID) {
1860 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1861 }
1862 assert(format != V_028C70_COLOR_INVALID);
1863 swap = r600_translate_colorswap(surf->base.format);
1864 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1865 endian = V_028C70_ENDIAN_NONE;
1866 } else {
1867 endian = si_colorformat_endian_swap(format);
1868 }
1869
1870 /* blend clamp should be set for all NORM/SRGB types */
1871 if (ntype == V_028C70_NUMBER_UNORM ||
1872 ntype == V_028C70_NUMBER_SNORM ||
1873 ntype == V_028C70_NUMBER_SRGB)
1874 blend_clamp = 1;
1875
1876 /* set blend bypass according to docs if SINT/UINT or
1877 8/24 COLOR variants */
1878 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1879 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1880 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1881 blend_clamp = 0;
1882 blend_bypass = 1;
1883 }
1884
1885 color_info = S_028C70_FORMAT(format) |
1886 S_028C70_COMP_SWAP(swap) |
1887 S_028C70_BLEND_CLAMP(blend_clamp) |
1888 S_028C70_BLEND_BYPASS(blend_bypass) |
1889 S_028C70_NUMBER_TYPE(ntype) |
1890 S_028C70_ENDIAN(endian);
1891
1892 color_pitch = S_028C64_TILE_MAX(pitch);
1893
1894 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1895 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1896
1897 if (rtex->resource.b.b.nr_samples > 1) {
1898 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1899
1900 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1901 S_028C74_NUM_FRAGMENTS(log_samples);
1902
1903 if (rtex->fmask.size) {
1904 color_info |= S_028C70_COMPRESSION(1);
1905 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1906
1907 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1908
1909 if (sctx->b.chip_class == SI) {
1910 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1911 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1912 }
1913 if (sctx->b.chip_class >= CIK) {
1914 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1915 }
1916 }
1917 }
1918
1919 offset += rtex->resource.gpu_address;
1920
1921 surf->cb_color_base = offset >> 8;
1922 surf->cb_color_pitch = color_pitch;
1923 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1924 surf->cb_color_view = color_view;
1925 surf->cb_color_info = color_info;
1926 surf->cb_color_attrib = color_attrib;
1927
1928 if (sctx->b.chip_class >= VI)
1929 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1930
1931 if (rtex->fmask.size) {
1932 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1933 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1934 } else {
1935 /* This must be set for fast clear to work without FMASK. */
1936 surf->cb_color_fmask = surf->cb_color_base;
1937 surf->cb_color_fmask_slice = surf->cb_color_slice;
1938 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1939
1940 if (sctx->b.chip_class == SI) {
1941 unsigned bankh = util_logbase2(rtex->surface.bankh);
1942 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1943 }
1944
1945 if (sctx->b.chip_class >= CIK) {
1946 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1947 }
1948 }
1949
1950 /* Determine pixel shader export format */
1951 max_comp_size = si_colorformat_max_comp_size(format);
1952 if (ntype == V_028C70_NUMBER_SRGB ||
1953 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1954 max_comp_size <= 10) ||
1955 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1956 surf->export_16bpc = true;
1957 }
1958
1959 surf->color_initialized = true;
1960 }
1961
1962 static void si_init_depth_surface(struct si_context *sctx,
1963 struct r600_surface *surf)
1964 {
1965 struct si_screen *sscreen = sctx->screen;
1966 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1967 unsigned level = surf->base.u.tex.level;
1968 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1969 unsigned format, tile_mode_index, array_mode;
1970 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1971 uint32_t z_info, s_info, db_depth_info;
1972 uint64_t z_offs, s_offs;
1973 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1974
1975 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1976 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1977 case PIPE_FORMAT_X8Z24_UNORM:
1978 case PIPE_FORMAT_Z24X8_UNORM:
1979 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1980 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1981 break;
1982 case PIPE_FORMAT_Z32_FLOAT:
1983 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1984 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1985 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1986 break;
1987 case PIPE_FORMAT_Z16_UNORM:
1988 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1989 break;
1990 default:
1991 assert(0);
1992 }
1993
1994 format = si_translate_dbformat(rtex->resource.b.b.format);
1995
1996 if (format == V_028040_Z_INVALID) {
1997 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1998 }
1999 assert(format != V_028040_Z_INVALID);
2000
2001 s_offs = z_offs = rtex->resource.gpu_address;
2002 z_offs += rtex->surface.level[level].offset;
2003 s_offs += rtex->surface.stencil_level[level].offset;
2004
2005 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2006
2007 z_info = S_028040_FORMAT(format);
2008 if (rtex->resource.b.b.nr_samples > 1) {
2009 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2010 }
2011
2012 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2013 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2014 else
2015 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2016
2017 if (sctx->b.chip_class >= CIK) {
2018 switch (rtex->surface.level[level].mode) {
2019 case RADEON_SURF_MODE_2D:
2020 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2021 break;
2022 case RADEON_SURF_MODE_1D:
2023 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2024 case RADEON_SURF_MODE_LINEAR:
2025 default:
2026 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2027 break;
2028 }
2029 tile_split = rtex->surface.tile_split;
2030 stile_split = rtex->surface.stencil_tile_split;
2031 macro_aspect = rtex->surface.mtilea;
2032 bankw = rtex->surface.bankw;
2033 bankh = rtex->surface.bankh;
2034 tile_split = cik_tile_split(tile_split);
2035 stile_split = cik_tile_split(stile_split);
2036 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2037 bankw = cik_bank_wh(bankw);
2038 bankh = cik_bank_wh(bankh);
2039 nbanks = si_num_banks(sscreen, rtex);
2040 tile_mode_index = si_tile_mode_index(rtex, level, false);
2041 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2042
2043 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2044 S_02803C_PIPE_CONFIG(pipe_config) |
2045 S_02803C_BANK_WIDTH(bankw) |
2046 S_02803C_BANK_HEIGHT(bankh) |
2047 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2048 S_02803C_NUM_BANKS(nbanks);
2049 z_info |= S_028040_TILE_SPLIT(tile_split);
2050 s_info |= S_028044_TILE_SPLIT(stile_split);
2051 } else {
2052 tile_mode_index = si_tile_mode_index(rtex, level, false);
2053 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2054 tile_mode_index = si_tile_mode_index(rtex, level, true);
2055 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2056 }
2057
2058 /* HiZ aka depth buffer htile */
2059 /* use htile only for first level */
2060 if (rtex->htile_buffer && !level) {
2061 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2062 S_028040_ALLOW_EXPCLEAR(1);
2063
2064 /* Use all of the htile_buffer for depth, because we don't
2065 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2066 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2067
2068 uint64_t va = rtex->htile_buffer->gpu_address;
2069 db_htile_data_base = va >> 8;
2070 db_htile_surface = S_028ABC_FULL_CACHE(1);
2071 } else {
2072 db_htile_data_base = 0;
2073 db_htile_surface = 0;
2074 }
2075
2076 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2077
2078 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2079 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2080 surf->db_htile_data_base = db_htile_data_base;
2081 surf->db_depth_info = db_depth_info;
2082 surf->db_z_info = z_info;
2083 surf->db_stencil_info = s_info;
2084 surf->db_depth_base = z_offs >> 8;
2085 surf->db_stencil_base = s_offs >> 8;
2086 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2087 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2088 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2089 levelinfo->nblk_y) / 64 - 1);
2090 surf->db_htile_surface = db_htile_surface;
2091 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2092
2093 surf->depth_initialized = true;
2094 }
2095
2096 static void si_set_framebuffer_state(struct pipe_context *ctx,
2097 const struct pipe_framebuffer_state *state)
2098 {
2099 struct si_context *sctx = (struct si_context *)ctx;
2100 struct pipe_constant_buffer constbuf = {0};
2101 struct r600_surface *surf = NULL;
2102 struct r600_texture *rtex;
2103 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2104 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2105 int i;
2106
2107 /* Only flush TC when changing the framebuffer state, because
2108 * the only client not using TC that can change textures is
2109 * the framebuffer.
2110 *
2111 * Flush all CB and DB caches here because all buffers can be used
2112 * for write by both TC (with shader image stores) and CB/DB.
2113 */
2114 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2115 SI_CONTEXT_INV_TC_L2 |
2116 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2117
2118 /* Take the maximum of the old and new count. If the new count is lower,
2119 * dirtying is needed to disable the unbound colorbuffers.
2120 */
2121 sctx->framebuffer.dirty_cbufs |=
2122 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2123 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2124
2125 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2126
2127 sctx->framebuffer.export_16bpc = 0;
2128 sctx->framebuffer.compressed_cb_mask = 0;
2129 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2130 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2131 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2132 util_format_is_pure_integer(state->cbufs[0]->format);
2133
2134 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2135 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2136
2137 for (i = 0; i < state->nr_cbufs; i++) {
2138 if (!state->cbufs[i])
2139 continue;
2140
2141 surf = (struct r600_surface*)state->cbufs[i];
2142 rtex = (struct r600_texture*)surf->base.texture;
2143
2144 if (!surf->color_initialized) {
2145 si_initialize_color_surface(sctx, surf);
2146 }
2147
2148 if (surf->export_16bpc) {
2149 sctx->framebuffer.export_16bpc |= 1 << i;
2150 }
2151
2152 if (rtex->fmask.size && rtex->cmask.size) {
2153 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2154 }
2155 r600_context_add_resource_size(ctx, surf->base.texture);
2156 }
2157 /* Set the 16BPC export for possible dual-src blending. */
2158 if (i == 1 && surf && surf->export_16bpc) {
2159 sctx->framebuffer.export_16bpc |= 1 << 1;
2160 }
2161
2162 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2163
2164 if (state->zsbuf) {
2165 surf = (struct r600_surface*)state->zsbuf;
2166
2167 if (!surf->depth_initialized) {
2168 si_init_depth_surface(sctx, surf);
2169 }
2170 r600_context_add_resource_size(ctx, surf->base.texture);
2171 }
2172
2173 si_update_poly_offset_state(sctx);
2174 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2175 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2176
2177 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2178 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2179 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2180
2181 /* Set sample locations as fragment shader constants. */
2182 switch (sctx->framebuffer.nr_samples) {
2183 case 1:
2184 constbuf.user_buffer = sctx->b.sample_locations_1x;
2185 break;
2186 case 2:
2187 constbuf.user_buffer = sctx->b.sample_locations_2x;
2188 break;
2189 case 4:
2190 constbuf.user_buffer = sctx->b.sample_locations_4x;
2191 break;
2192 case 8:
2193 constbuf.user_buffer = sctx->b.sample_locations_8x;
2194 break;
2195 case 16:
2196 constbuf.user_buffer = sctx->b.sample_locations_16x;
2197 break;
2198 default:
2199 assert(0);
2200 }
2201 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2202 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2203 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2204
2205 /* Smoothing (only possible with nr_samples == 1) uses the same
2206 * sample locations as the MSAA it simulates.
2207 *
2208 * Therefore, don't update the sample locations when
2209 * transitioning from no AA to smoothing-equivalent AA, and
2210 * vice versa.
2211 */
2212 if ((sctx->framebuffer.nr_samples != 1 ||
2213 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2214 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2215 old_nr_samples != 1))
2216 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2217 }
2218 }
2219
2220 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2221 {
2222 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2223 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2224 unsigned i, nr_cbufs = state->nr_cbufs;
2225 struct r600_texture *tex = NULL;
2226 struct r600_surface *cb = NULL;
2227
2228 /* Colorbuffers. */
2229 for (i = 0; i < nr_cbufs; i++) {
2230 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2231 continue;
2232
2233 cb = (struct r600_surface*)state->cbufs[i];
2234 if (!cb) {
2235 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2236 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2237 continue;
2238 }
2239
2240 tex = (struct r600_texture *)cb->base.texture;
2241 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2242 &tex->resource, RADEON_USAGE_READWRITE,
2243 tex->surface.nsamples > 1 ?
2244 RADEON_PRIO_COLOR_BUFFER_MSAA :
2245 RADEON_PRIO_COLOR_BUFFER);
2246
2247 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2249 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2250 RADEON_PRIO_CMASK);
2251 }
2252
2253 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2254 sctx->b.chip_class >= VI ? 14 : 13);
2255 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2256 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2257 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2258 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2259 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2260 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2261 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2262 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2263 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2264 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2265 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2266 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2267 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2268
2269 if (sctx->b.chip_class >= VI)
2270 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2271 }
2272 /* set CB_COLOR1_INFO for possible dual-src blending */
2273 if (i == 1 && state->cbufs[0] &&
2274 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2275 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2276 cb->cb_color_info | tex->cb_color_info);
2277 i++;
2278 }
2279 for (; i < 8 ; i++)
2280 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2281 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2282
2283 /* ZS buffer. */
2284 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2285 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2286 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2287
2288 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2289 &rtex->resource, RADEON_USAGE_READWRITE,
2290 zb->base.texture->nr_samples > 1 ?
2291 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2292 RADEON_PRIO_DEPTH_BUFFER);
2293
2294 if (zb->db_htile_data_base) {
2295 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2296 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2297 RADEON_PRIO_HTILE);
2298 }
2299
2300 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2301 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2302
2303 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2304 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2305 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2306 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2307 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2308 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2309 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2310 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2311 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2312 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2313 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2314
2315 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2316 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2317 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2318 zb->pa_su_poly_offset_db_fmt_cntl);
2319 } else if (sctx->framebuffer.dirty_zsbuf) {
2320 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2321 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2322 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2323 }
2324
2325 /* Framebuffer dimensions. */
2326 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2327 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2328 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2329
2330 sctx->framebuffer.dirty_cbufs = 0;
2331 sctx->framebuffer.dirty_zsbuf = false;
2332 }
2333
2334 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2335 struct r600_atom *atom)
2336 {
2337 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2338 unsigned nr_samples = sctx->framebuffer.nr_samples;
2339
2340 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2341 SI_NUM_SMOOTH_AA_SAMPLES);
2342 }
2343
2344 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2345 {
2346 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2347
2348 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2349 sctx->ps_iter_samples,
2350 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2351 }
2352
2353
2354 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2355 {
2356 struct si_context *sctx = (struct si_context *)ctx;
2357
2358 if (sctx->ps_iter_samples == min_samples)
2359 return;
2360
2361 sctx->ps_iter_samples = min_samples;
2362
2363 if (sctx->framebuffer.nr_samples > 1)
2364 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2365 }
2366
2367 /*
2368 * Samplers
2369 */
2370
2371 /**
2372 * Create a sampler view.
2373 *
2374 * @param ctx context
2375 * @param texture texture
2376 * @param state sampler view template
2377 * @param width0 width0 override (for compressed textures as int)
2378 * @param height0 height0 override (for compressed textures as int)
2379 * @param force_level set the base address to the level (for compressed textures)
2380 */
2381 struct pipe_sampler_view *
2382 si_create_sampler_view_custom(struct pipe_context *ctx,
2383 struct pipe_resource *texture,
2384 const struct pipe_sampler_view *state,
2385 unsigned width0, unsigned height0,
2386 unsigned force_level)
2387 {
2388 struct si_context *sctx = (struct si_context*)ctx;
2389 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2390 struct r600_texture *tmp = (struct r600_texture*)texture;
2391 const struct util_format_description *desc;
2392 unsigned format, num_format, base_level, first_level, last_level;
2393 uint32_t pitch = 0;
2394 unsigned char state_swizzle[4], swizzle[4];
2395 unsigned height, depth, width;
2396 enum pipe_format pipe_format = state->format;
2397 struct radeon_surf_level *surflevel;
2398 int first_non_void;
2399 uint64_t va;
2400 unsigned last_layer = state->u.tex.last_layer;
2401
2402 if (view == NULL)
2403 return NULL;
2404
2405 /* initialize base object */
2406 view->base = *state;
2407 view->base.texture = NULL;
2408 view->base.reference.count = 1;
2409 view->base.context = ctx;
2410
2411 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2412 if (!texture) {
2413 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2414 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2415 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2416 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2417 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2418 return &view->base;
2419 }
2420
2421 pipe_resource_reference(&view->base.texture, texture);
2422 view->resource = &tmp->resource;
2423
2424 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2425 state->format == PIPE_FORMAT_S8X24_UINT ||
2426 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2427 state->format == PIPE_FORMAT_S8_UINT)
2428 view->is_stencil_sampler = true;
2429
2430 /* Buffer resource. */
2431 if (texture->target == PIPE_BUFFER) {
2432 unsigned stride, num_records;
2433
2434 desc = util_format_description(state->format);
2435 first_non_void = util_format_get_first_non_void_channel(state->format);
2436 stride = desc->block.bits / 8;
2437 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2438 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2439 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2440
2441 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2442 num_records = MIN2(num_records, texture->width0 / stride);
2443
2444 if (sctx->b.chip_class >= VI)
2445 num_records *= stride;
2446
2447 view->state[4] = va;
2448 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2449 S_008F04_STRIDE(stride);
2450 view->state[6] = num_records;
2451 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2452 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2453 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2454 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2455 S_008F0C_NUM_FORMAT(num_format) |
2456 S_008F0C_DATA_FORMAT(format);
2457
2458 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2459 return &view->base;
2460 }
2461
2462 state_swizzle[0] = state->swizzle_r;
2463 state_swizzle[1] = state->swizzle_g;
2464 state_swizzle[2] = state->swizzle_b;
2465 state_swizzle[3] = state->swizzle_a;
2466
2467 surflevel = tmp->surface.level;
2468
2469 /* Texturing with separate depth and stencil. */
2470 if (tmp->is_depth && !tmp->is_flushing_texture) {
2471 switch (pipe_format) {
2472 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2473 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2474 break;
2475 case PIPE_FORMAT_X8Z24_UNORM:
2476 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2477 /* Z24 is always stored like this. */
2478 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2479 break;
2480 case PIPE_FORMAT_X24S8_UINT:
2481 case PIPE_FORMAT_S8X24_UINT:
2482 case PIPE_FORMAT_X32_S8X24_UINT:
2483 pipe_format = PIPE_FORMAT_S8_UINT;
2484 surflevel = tmp->surface.stencil_level;
2485 break;
2486 default:;
2487 }
2488 }
2489
2490 desc = util_format_description(pipe_format);
2491
2492 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2493 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2494 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2495
2496 switch (pipe_format) {
2497 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2498 case PIPE_FORMAT_X24S8_UINT:
2499 case PIPE_FORMAT_X32_S8X24_UINT:
2500 case PIPE_FORMAT_X8Z24_UNORM:
2501 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2502 break;
2503 default:
2504 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2505 }
2506 } else {
2507 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2508 }
2509
2510 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2511
2512 switch (pipe_format) {
2513 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2514 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2515 break;
2516 default:
2517 if (first_non_void < 0) {
2518 if (util_format_is_compressed(pipe_format)) {
2519 switch (pipe_format) {
2520 case PIPE_FORMAT_DXT1_SRGB:
2521 case PIPE_FORMAT_DXT1_SRGBA:
2522 case PIPE_FORMAT_DXT3_SRGBA:
2523 case PIPE_FORMAT_DXT5_SRGBA:
2524 case PIPE_FORMAT_BPTC_SRGBA:
2525 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2526 break;
2527 case PIPE_FORMAT_RGTC1_SNORM:
2528 case PIPE_FORMAT_LATC1_SNORM:
2529 case PIPE_FORMAT_RGTC2_SNORM:
2530 case PIPE_FORMAT_LATC2_SNORM:
2531 /* implies float, so use SNORM/UNORM to determine
2532 whether data is signed or not */
2533 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2534 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2535 break;
2536 default:
2537 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2538 break;
2539 }
2540 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2541 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2542 } else {
2543 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2544 }
2545 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2546 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2547 } else {
2548 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2549
2550 switch (desc->channel[first_non_void].type) {
2551 case UTIL_FORMAT_TYPE_FLOAT:
2552 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2553 break;
2554 case UTIL_FORMAT_TYPE_SIGNED:
2555 if (desc->channel[first_non_void].normalized)
2556 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2557 else if (desc->channel[first_non_void].pure_integer)
2558 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2559 else
2560 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2561 break;
2562 case UTIL_FORMAT_TYPE_UNSIGNED:
2563 if (desc->channel[first_non_void].normalized)
2564 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2565 else if (desc->channel[first_non_void].pure_integer)
2566 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2567 else
2568 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2569 }
2570 }
2571 }
2572
2573 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2574 if (format == ~0) {
2575 format = 0;
2576 }
2577
2578 base_level = 0;
2579 first_level = state->u.tex.first_level;
2580 last_level = state->u.tex.last_level;
2581 width = width0;
2582 height = height0;
2583 depth = texture->depth0;
2584
2585 if (force_level) {
2586 assert(force_level == first_level &&
2587 force_level == last_level);
2588 base_level = force_level;
2589 first_level = 0;
2590 last_level = 0;
2591 width = u_minify(width, force_level);
2592 height = u_minify(height, force_level);
2593 depth = u_minify(depth, force_level);
2594 }
2595
2596 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2597
2598 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2599 height = 1;
2600 depth = texture->array_size;
2601 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2602 depth = texture->array_size;
2603 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2604 depth = texture->array_size / 6;
2605
2606 /* This is not needed if state trackers set last_layer correctly. */
2607 if (state->target == PIPE_TEXTURE_1D ||
2608 state->target == PIPE_TEXTURE_2D ||
2609 state->target == PIPE_TEXTURE_RECT ||
2610 state->target == PIPE_TEXTURE_CUBE)
2611 last_layer = state->u.tex.first_layer;
2612
2613 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2614
2615 view->state[0] = va >> 8;
2616 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2617 S_008F14_DATA_FORMAT(format) |
2618 S_008F14_NUM_FORMAT(num_format));
2619 view->state[2] = (S_008F18_WIDTH(width - 1) |
2620 S_008F18_HEIGHT(height - 1));
2621 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2622 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2623 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2624 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2625 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2626 0 : first_level) |
2627 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2628 util_logbase2(texture->nr_samples) :
2629 last_level) |
2630 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2631 S_008F1C_POW2_PAD(texture->last_level > 0) |
2632 S_008F1C_TYPE(si_tex_dim(texture->target, state->target,
2633 texture->nr_samples)));
2634 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2635 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2636 S_008F24_LAST_ARRAY(last_layer));
2637 view->state[6] = 0;
2638 view->state[7] = 0;
2639
2640 /* Initialize the sampler view for FMASK. */
2641 if (tmp->fmask.size) {
2642 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2643 uint32_t fmask_format;
2644
2645 switch (texture->nr_samples) {
2646 case 2:
2647 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2648 break;
2649 case 4:
2650 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2651 break;
2652 case 8:
2653 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2654 break;
2655 default:
2656 assert(0);
2657 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2658 }
2659
2660 view->fmask_state[0] = va >> 8;
2661 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2662 S_008F14_DATA_FORMAT(fmask_format) |
2663 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2664 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2665 S_008F18_HEIGHT(height - 1);
2666 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2667 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2668 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2669 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2670 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2671 S_008F1C_TYPE(si_tex_dim(texture->target,
2672 state->target, 0));
2673 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2674 S_008F20_PITCH(tmp->fmask.pitch - 1);
2675 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2676 S_008F24_LAST_ARRAY(last_layer);
2677 view->fmask_state[6] = 0;
2678 view->fmask_state[7] = 0;
2679 }
2680
2681 return &view->base;
2682 }
2683
2684 static struct pipe_sampler_view *
2685 si_create_sampler_view(struct pipe_context *ctx,
2686 struct pipe_resource *texture,
2687 const struct pipe_sampler_view *state)
2688 {
2689 return si_create_sampler_view_custom(ctx, texture, state,
2690 texture ? texture->width0 : 0,
2691 texture ? texture->height0 : 0, 0);
2692 }
2693
2694 static void si_sampler_view_destroy(struct pipe_context *ctx,
2695 struct pipe_sampler_view *state)
2696 {
2697 struct si_sampler_view *view = (struct si_sampler_view *)state;
2698
2699 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2700 LIST_DELINIT(&view->list);
2701
2702 pipe_resource_reference(&state->texture, NULL);
2703 FREE(view);
2704 }
2705
2706 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2707 {
2708 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2709 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2710 (linear_filter &&
2711 (wrap == PIPE_TEX_WRAP_CLAMP ||
2712 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2713 }
2714
2715 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2716 {
2717 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2718 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2719
2720 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2721 state->border_color.ui[2] || state->border_color.ui[3]) &&
2722 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2723 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2724 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2725 }
2726
2727 static void *si_create_sampler_state(struct pipe_context *ctx,
2728 const struct pipe_sampler_state *state)
2729 {
2730 struct si_context *sctx = (struct si_context *)ctx;
2731 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2732 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2733 unsigned border_color_type, border_color_index = 0;
2734
2735 if (rstate == NULL) {
2736 return NULL;
2737 }
2738
2739 if (!sampler_state_needs_border_color(state))
2740 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2741 else if (state->border_color.f[0] == 0 &&
2742 state->border_color.f[1] == 0 &&
2743 state->border_color.f[2] == 0 &&
2744 state->border_color.f[3] == 0)
2745 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2746 else if (state->border_color.f[0] == 0 &&
2747 state->border_color.f[1] == 0 &&
2748 state->border_color.f[2] == 0 &&
2749 state->border_color.f[3] == 1)
2750 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2751 else if (state->border_color.f[0] == 1 &&
2752 state->border_color.f[1] == 1 &&
2753 state->border_color.f[2] == 1 &&
2754 state->border_color.f[3] == 1)
2755 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2756 else {
2757 int i;
2758
2759 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2760
2761 /* Check if the border has been uploaded already. */
2762 for (i = 0; i < sctx->border_color_count; i++)
2763 if (memcmp(&sctx->border_color_table[i], &state->border_color,
2764 sizeof(state->border_color)) == 0)
2765 break;
2766
2767 if (i >= SI_MAX_BORDER_COLORS) {
2768 /* Getting 4096 unique border colors is very unlikely. */
2769 fprintf(stderr, "radeonsi: The border color table is full. "
2770 "Any new border colors will be just black. "
2771 "Please file a bug.\n");
2772 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2773 } else {
2774 if (i == sctx->border_color_count) {
2775 /* Upload a new border color. */
2776 memcpy(&sctx->border_color_table[i], &state->border_color,
2777 sizeof(state->border_color));
2778 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
2779 &state->border_color,
2780 sizeof(state->border_color));
2781 sctx->border_color_count++;
2782 }
2783
2784 border_color_index = i;
2785 }
2786 }
2787
2788 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2789 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2790 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2791 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2792 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2793 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2794 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2795 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2796 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2797 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2798 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2799 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2800 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2801 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
2802 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2803 return rstate;
2804 }
2805
2806 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2807 {
2808 struct si_context *sctx = (struct si_context *)ctx;
2809
2810 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2811 return;
2812
2813 sctx->sample_mask.sample_mask = sample_mask;
2814 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2815 }
2816
2817 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2818 {
2819 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2820 unsigned mask = sctx->sample_mask.sample_mask;
2821
2822 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2823 radeon_emit(cs, mask | (mask << 16));
2824 radeon_emit(cs, mask | (mask << 16));
2825 }
2826
2827 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2828 {
2829 free(state);
2830 }
2831
2832 /*
2833 * Vertex elements & buffers
2834 */
2835
2836 static void *si_create_vertex_elements(struct pipe_context *ctx,
2837 unsigned count,
2838 const struct pipe_vertex_element *elements)
2839 {
2840 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2841 int i;
2842
2843 assert(count < SI_MAX_ATTRIBS);
2844 if (!v)
2845 return NULL;
2846
2847 v->count = count;
2848 for (i = 0; i < count; ++i) {
2849 const struct util_format_description *desc;
2850 unsigned data_format, num_format;
2851 int first_non_void;
2852
2853 desc = util_format_description(elements[i].src_format);
2854 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2855 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2856 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2857
2858 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2859 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2860 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2861 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2862 S_008F0C_NUM_FORMAT(num_format) |
2863 S_008F0C_DATA_FORMAT(data_format);
2864 v->format_size[i] = desc->block.bits / 8;
2865 }
2866 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2867
2868 return v;
2869 }
2870
2871 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2872 {
2873 struct si_context *sctx = (struct si_context *)ctx;
2874 struct si_vertex_element *v = (struct si_vertex_element*)state;
2875
2876 sctx->vertex_elements = v;
2877 sctx->vertex_buffers_dirty = true;
2878 }
2879
2880 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2881 {
2882 struct si_context *sctx = (struct si_context *)ctx;
2883
2884 if (sctx->vertex_elements == state)
2885 sctx->vertex_elements = NULL;
2886 FREE(state);
2887 }
2888
2889 static void si_set_vertex_buffers(struct pipe_context *ctx,
2890 unsigned start_slot, unsigned count,
2891 const struct pipe_vertex_buffer *buffers)
2892 {
2893 struct si_context *sctx = (struct si_context *)ctx;
2894 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2895 int i;
2896
2897 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2898
2899 if (buffers) {
2900 for (i = 0; i < count; i++) {
2901 const struct pipe_vertex_buffer *src = buffers + i;
2902 struct pipe_vertex_buffer *dsti = dst + i;
2903
2904 pipe_resource_reference(&dsti->buffer, src->buffer);
2905 dsti->buffer_offset = src->buffer_offset;
2906 dsti->stride = src->stride;
2907 r600_context_add_resource_size(ctx, src->buffer);
2908 }
2909 } else {
2910 for (i = 0; i < count; i++) {
2911 pipe_resource_reference(&dst[i].buffer, NULL);
2912 }
2913 }
2914 sctx->vertex_buffers_dirty = true;
2915 }
2916
2917 static void si_set_index_buffer(struct pipe_context *ctx,
2918 const struct pipe_index_buffer *ib)
2919 {
2920 struct si_context *sctx = (struct si_context *)ctx;
2921
2922 if (ib) {
2923 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2924 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2925 r600_context_add_resource_size(ctx, ib->buffer);
2926 } else {
2927 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2928 }
2929 }
2930
2931 /*
2932 * Misc
2933 */
2934 static void si_set_polygon_stipple(struct pipe_context *ctx,
2935 const struct pipe_poly_stipple *state)
2936 {
2937 struct si_context *sctx = (struct si_context *)ctx;
2938 struct pipe_resource *tex;
2939 struct pipe_sampler_view *view;
2940 bool is_zero = true;
2941 bool is_one = true;
2942 int i;
2943
2944 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2945 * the resource is NULL/invalid. Take advantage of this fact and skip
2946 * texture allocation if the stipple pattern is constant.
2947 *
2948 * This is an optimization for the common case when stippling isn't
2949 * used but set_polygon_stipple is still called by st/mesa.
2950 */
2951 for (i = 0; i < Elements(state->stipple); i++) {
2952 is_zero = is_zero && state->stipple[i] == 0;
2953 is_one = is_one && state->stipple[i] == 0xffffffff;
2954 }
2955
2956 if (is_zero || is_one) {
2957 struct pipe_sampler_view templ = {{0}};
2958
2959 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2960 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2961 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2962 /* The pattern should be inverted in the texture. */
2963 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2964
2965 view = ctx->create_sampler_view(ctx, NULL, &templ);
2966 } else {
2967 /* Create a new texture. */
2968 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2969 if (!tex)
2970 return;
2971
2972 view = util_pstipple_create_sampler_view(ctx, tex);
2973 pipe_resource_reference(&tex, NULL);
2974 }
2975
2976 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2977 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2978 pipe_sampler_view_reference(&view, NULL);
2979
2980 /* Bind the sampler state if needed. */
2981 if (!sctx->pstipple_sampler_state) {
2982 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2983 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2984 SI_POLY_STIPPLE_SAMPLER, 1,
2985 &sctx->pstipple_sampler_state);
2986 }
2987 }
2988
2989 static void si_set_tess_state(struct pipe_context *ctx,
2990 const float default_outer_level[4],
2991 const float default_inner_level[2])
2992 {
2993 struct si_context *sctx = (struct si_context *)ctx;
2994 struct pipe_constant_buffer cb;
2995 float array[8];
2996
2997 memcpy(array, default_outer_level, sizeof(float) * 4);
2998 memcpy(array+4, default_inner_level, sizeof(float) * 2);
2999
3000 cb.buffer = NULL;
3001 cb.user_buffer = NULL;
3002 cb.buffer_size = sizeof(array);
3003
3004 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3005 (void*)array, sizeof(array),
3006 &cb.buffer_offset);
3007
3008 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3009 SI_DRIVER_STATE_CONST_BUF, &cb);
3010 pipe_resource_reference(&cb.buffer, NULL);
3011 }
3012
3013 static void si_texture_barrier(struct pipe_context *ctx)
3014 {
3015 struct si_context *sctx = (struct si_context *)ctx;
3016
3017 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3018 SI_CONTEXT_INV_TC_L2 |
3019 SI_CONTEXT_FLUSH_AND_INV_CB;
3020 }
3021
3022 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3023 {
3024 struct pipe_blend_state blend;
3025
3026 memset(&blend, 0, sizeof(blend));
3027 blend.independent_blend_enable = true;
3028 blend.rt[0].colormask = 0xf;
3029 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3030 }
3031
3032 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3033 bool include_draw_vbo)
3034 {
3035 si_need_cs_space((struct si_context*)ctx);
3036 }
3037
3038 static void si_init_config(struct si_context *sctx);
3039
3040 void si_init_state_functions(struct si_context *sctx)
3041 {
3042 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3043 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3044
3045 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3046 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3047 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3048 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3049 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3050 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3051 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3052 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3053 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3054 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3055 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3056 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3057 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3058
3059 sctx->b.b.create_blend_state = si_create_blend_state;
3060 sctx->b.b.bind_blend_state = si_bind_blend_state;
3061 sctx->b.b.delete_blend_state = si_delete_blend_state;
3062 sctx->b.b.set_blend_color = si_set_blend_color;
3063
3064 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3065 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3066 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3067
3068 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3069 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3070 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3071
3072 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3073 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3074 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3075 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3076
3077 sctx->b.b.set_clip_state = si_set_clip_state;
3078 sctx->b.b.set_scissor_states = si_set_scissor_states;
3079 sctx->b.b.set_viewport_states = si_set_viewport_states;
3080 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3081
3082 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3083 sctx->b.b.get_sample_position = cayman_get_sample_position;
3084
3085 sctx->b.b.create_sampler_state = si_create_sampler_state;
3086 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3087
3088 sctx->b.b.create_sampler_view = si_create_sampler_view;
3089 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3090
3091 sctx->b.b.set_sample_mask = si_set_sample_mask;
3092
3093 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3094 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3095 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3096 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3097 sctx->b.b.set_index_buffer = si_set_index_buffer;
3098
3099 sctx->b.b.texture_barrier = si_texture_barrier;
3100 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3101 sctx->b.b.set_min_samples = si_set_min_samples;
3102 sctx->b.b.set_tess_state = si_set_tess_state;
3103
3104 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3105 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3106
3107 sctx->b.b.draw_vbo = si_draw_vbo;
3108
3109 if (sctx->b.chip_class >= CIK) {
3110 sctx->b.dma_copy = cik_sdma_copy;
3111 } else {
3112 sctx->b.dma_copy = si_dma_copy;
3113 }
3114
3115 si_init_config(sctx);
3116 }
3117
3118 static void
3119 si_write_harvested_raster_configs(struct si_context *sctx,
3120 struct si_pm4_state *pm4,
3121 unsigned raster_config,
3122 unsigned raster_config_1)
3123 {
3124 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3125 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3126 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3127 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3128 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3129 unsigned rb_per_se = num_rb / num_se;
3130 unsigned se_mask[4];
3131 unsigned se;
3132
3133 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3134 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3135 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3136 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3137
3138 assert(num_se == 1 || num_se == 2 || num_se == 4);
3139 assert(sh_per_se == 1 || sh_per_se == 2);
3140 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3141
3142 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3143 * fields are for, so I'm leaving them as their default
3144 * values. */
3145
3146 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3147 (!se_mask[2] && !se_mask[3]))) {
3148 raster_config_1 &= C_028354_SE_PAIR_MAP;
3149
3150 if (!se_mask[0] && !se_mask[1]) {
3151 raster_config_1 |=
3152 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3153 } else {
3154 raster_config_1 |=
3155 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3156 }
3157 }
3158
3159 for (se = 0; se < num_se; se++) {
3160 unsigned raster_config_se = raster_config;
3161 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3162 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3163 int idx = (se / 2) * 2;
3164
3165 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3166 raster_config_se &= C_028350_SE_MAP;
3167
3168 if (!se_mask[idx]) {
3169 raster_config_se |=
3170 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3171 } else {
3172 raster_config_se |=
3173 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3174 }
3175 }
3176
3177 pkr0_mask &= rb_mask;
3178 pkr1_mask &= rb_mask;
3179 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3180 raster_config_se &= C_028350_PKR_MAP;
3181
3182 if (!pkr0_mask) {
3183 raster_config_se |=
3184 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3185 } else {
3186 raster_config_se |=
3187 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3188 }
3189 }
3190
3191 if (rb_per_se >= 2) {
3192 unsigned rb0_mask = 1 << (se * rb_per_se);
3193 unsigned rb1_mask = rb0_mask << 1;
3194
3195 rb0_mask &= rb_mask;
3196 rb1_mask &= rb_mask;
3197 if (!rb0_mask || !rb1_mask) {
3198 raster_config_se &= C_028350_RB_MAP_PKR0;
3199
3200 if (!rb0_mask) {
3201 raster_config_se |=
3202 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3203 } else {
3204 raster_config_se |=
3205 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3206 }
3207 }
3208
3209 if (rb_per_se > 2) {
3210 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3211 rb1_mask = rb0_mask << 1;
3212 rb0_mask &= rb_mask;
3213 rb1_mask &= rb_mask;
3214 if (!rb0_mask || !rb1_mask) {
3215 raster_config_se &= C_028350_RB_MAP_PKR1;
3216
3217 if (!rb0_mask) {
3218 raster_config_se |=
3219 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3220 } else {
3221 raster_config_se |=
3222 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3223 }
3224 }
3225 }
3226 }
3227
3228 /* GRBM_GFX_INDEX is privileged on VI */
3229 if (sctx->b.chip_class <= CIK)
3230 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3231 SE_INDEX(se) | SH_BROADCAST_WRITES |
3232 INSTANCE_BROADCAST_WRITES);
3233 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3234 if (sctx->b.chip_class >= CIK)
3235 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3236 }
3237
3238 /* GRBM_GFX_INDEX is privileged on VI */
3239 if (sctx->b.chip_class <= CIK)
3240 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3241 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3242 INSTANCE_BROADCAST_WRITES);
3243 }
3244
3245 static void si_init_config(struct si_context *sctx)
3246 {
3247 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3248 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3249 unsigned raster_config, raster_config_1;
3250 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3251 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3252 int i;
3253
3254 if (pm4 == NULL)
3255 return;
3256
3257 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3258 si_pm4_cmd_add(pm4, 0x80000000);
3259 si_pm4_cmd_add(pm4, 0x80000000);
3260 si_pm4_cmd_end(pm4, false);
3261
3262 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3263 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3264
3265 /* FIXME calculate these values somehow ??? */
3266 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3267 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3268 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3269
3270 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3271 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3272
3273 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3274 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3275 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3276 if (sctx->b.chip_class < CIK)
3277 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3278 S_008A14_CLIP_VTX_REORDER_ENA(1));
3279
3280 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3281 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3282
3283 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3284
3285 for (i = 0; i < 16; i++) {
3286 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3287 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3288 }
3289
3290 switch (sctx->screen->b.family) {
3291 case CHIP_TAHITI:
3292 case CHIP_PITCAIRN:
3293 raster_config = 0x2a00126a;
3294 raster_config_1 = 0x00000000;
3295 break;
3296 case CHIP_VERDE:
3297 raster_config = 0x0000124a;
3298 raster_config_1 = 0x00000000;
3299 break;
3300 case CHIP_OLAND:
3301 raster_config = 0x00000082;
3302 raster_config_1 = 0x00000000;
3303 break;
3304 case CHIP_HAINAN:
3305 raster_config = 0x00000000;
3306 raster_config_1 = 0x00000000;
3307 break;
3308 case CHIP_BONAIRE:
3309 raster_config = 0x16000012;
3310 raster_config_1 = 0x00000000;
3311 break;
3312 case CHIP_HAWAII:
3313 raster_config = 0x3a00161a;
3314 raster_config_1 = 0x0000002e;
3315 break;
3316 case CHIP_FIJI:
3317 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3318 raster_config = 0x16000012; /* 0x3a00161a */
3319 raster_config_1 = 0x0000002a; /* 0x0000002e */
3320 break;
3321 case CHIP_TONGA:
3322 raster_config = 0x16000012;
3323 raster_config_1 = 0x0000002a;
3324 break;
3325 case CHIP_ICELAND:
3326 raster_config = 0x00000002;
3327 raster_config_1 = 0x00000000;
3328 break;
3329 case CHIP_CARRIZO:
3330 raster_config = 0x00000002;
3331 raster_config_1 = 0x00000000;
3332 break;
3333 case CHIP_KAVERI:
3334 /* KV should be 0x00000002, but that causes problems with radeon */
3335 raster_config = 0x00000000; /* 0x00000002 */
3336 raster_config_1 = 0x00000000;
3337 break;
3338 case CHIP_KABINI:
3339 case CHIP_MULLINS:
3340 case CHIP_STONEY:
3341 raster_config = 0x00000000;
3342 raster_config_1 = 0x00000000;
3343 break;
3344 default:
3345 fprintf(stderr,
3346 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3347 raster_config = 0x00000000;
3348 raster_config_1 = 0x00000000;
3349 break;
3350 }
3351
3352 /* Always use the default config when all backends are enabled
3353 * (or when we failed to determine the enabled backends).
3354 */
3355 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3356 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3357 raster_config);
3358 if (sctx->b.chip_class >= CIK)
3359 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3360 raster_config_1);
3361 } else {
3362 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3363 }
3364
3365 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3366 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3367 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3368 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3369 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3370 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3371 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3372
3373 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3374 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3375 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3376 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3377 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3378 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3379 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3380 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3381 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3382 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3383 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3384 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3385 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3386
3387 /* There is a hang if stencil is used and fast stencil is enabled
3388 * regardless of whether HTILE is depth-only or not.
3389 */
3390 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3391 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3392 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3393 S_02800C_FAST_STENCIL_DISABLE(1));
3394
3395 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3396 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3397 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3398
3399 if (sctx->b.chip_class >= CIK) {
3400 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3401 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3402 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3403 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3404 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3405 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3406 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3407 }
3408
3409 if (sctx->b.chip_class >= VI) {
3410 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3411 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3412 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3413 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3414 }
3415
3416 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3417 if (sctx->b.chip_class >= CIK)
3418 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3419 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3420 RADEON_PRIO_BORDER_COLORS);
3421
3422 si_pm4_upload_indirect_buffer(sctx, pm4);
3423 sctx->init_config = pm4;
3424 }