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radeonsi: add support for Hawaii asics (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528 rs->line_stipple_enable = state->line_stipple_enable;
529
530 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
531 state->fill_back != PIPE_POLYGON_MODE_FILL);
532
533 if (state->flatshade_first)
534 prov_vtx = 0;
535
536 rs->flatshade = state->flatshade;
537 rs->sprite_coord_enable = state->sprite_coord_enable;
538 rs->pa_sc_line_stipple = state->line_stipple_enable ?
539 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
540 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
541 rs->pa_su_sc_mode_cntl =
542 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
543 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
544 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
545 S_028814_FACE(!state->front_ccw) |
546 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
548 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
549 S_028814_POLY_MODE(polygon_dual_mode) |
550 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
551 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
552 rs->pa_cl_clip_cntl =
553 S_028810_PS_UCP_MODE(3) |
554 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
555 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
556 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
557 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
558
559 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
560
561 /* offset */
562 rs->offset_units = state->offset_units;
563 rs->offset_scale = state->offset_scale * 12.0f;
564
565 tmp = S_0286D4_FLAT_SHADE_ENA(1);
566 if (state->sprite_coord_enable) {
567 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
568 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
569 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
570 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
571 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
572 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
573 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
574 }
575 }
576 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
577
578 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
579 /* point size 12.4 fixed point */
580 tmp = (unsigned)(state->point_size * 8.0);
581 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
582
583 if (state->point_size_per_vertex) {
584 psize_min = util_get_min_point_size(state);
585 psize_max = 8192;
586 } else {
587 /* Force the point size to be as if the vertex output was disabled. */
588 psize_min = state->point_size;
589 psize_max = state->point_size;
590 }
591 /* Divide by two, because 0.5 = 1 pixel. */
592 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
593 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
594 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
595
596 tmp = (unsigned)state->line_width * 8;
597 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
598 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
599 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
600 S_028A48_MSAA_ENABLE(state->multisample));
601
602 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
603 S_028BE4_PIX_CENTER(state->half_pixel_center) |
604 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
605 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
608 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
609
610 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
611 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
612
613 return rs;
614 }
615
616 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
617 {
618 struct r600_context *rctx = (struct r600_context *)ctx;
619 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
620
621 if (state == NULL)
622 return;
623
624 // TODO
625 rctx->sprite_coord_enable = rs->sprite_coord_enable;
626 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
627 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
628
629 si_pm4_bind_state(rctx, rasterizer, rs);
630 si_update_fb_rs_state(rctx);
631 }
632
633 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
634 {
635 struct r600_context *rctx = (struct r600_context *)ctx;
636 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
637 }
638
639 /*
640 * infeered state between dsa and stencil ref
641 */
642 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
643 {
644 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
645 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
646 struct si_state_dsa *dsa = rctx->queued.named.dsa;
647
648 if (pm4 == NULL)
649 return;
650
651 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
652 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
653 S_028430_STENCILMASK(dsa->valuemask[0]) |
654 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
655 S_028430_STENCILOPVAL(1));
656 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
657 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
658 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
659 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
660 S_028434_STENCILOPVAL_BF(1));
661
662 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
663 }
664
665 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
666 const struct pipe_stencil_ref *state)
667 {
668 struct r600_context *rctx = (struct r600_context *)ctx;
669 rctx->stencil_ref = *state;
670 si_update_dsa_stencil_ref(rctx);
671 }
672
673
674 /*
675 * DSA
676 */
677
678 static uint32_t si_translate_stencil_op(int s_op)
679 {
680 switch (s_op) {
681 case PIPE_STENCIL_OP_KEEP:
682 return V_02842C_STENCIL_KEEP;
683 case PIPE_STENCIL_OP_ZERO:
684 return V_02842C_STENCIL_ZERO;
685 case PIPE_STENCIL_OP_REPLACE:
686 return V_02842C_STENCIL_REPLACE_TEST;
687 case PIPE_STENCIL_OP_INCR:
688 return V_02842C_STENCIL_ADD_CLAMP;
689 case PIPE_STENCIL_OP_DECR:
690 return V_02842C_STENCIL_SUB_CLAMP;
691 case PIPE_STENCIL_OP_INCR_WRAP:
692 return V_02842C_STENCIL_ADD_WRAP;
693 case PIPE_STENCIL_OP_DECR_WRAP:
694 return V_02842C_STENCIL_SUB_WRAP;
695 case PIPE_STENCIL_OP_INVERT:
696 return V_02842C_STENCIL_INVERT;
697 default:
698 R600_ERR("Unknown stencil op %d", s_op);
699 assert(0);
700 break;
701 }
702 return 0;
703 }
704
705 static void *si_create_dsa_state(struct pipe_context *ctx,
706 const struct pipe_depth_stencil_alpha_state *state)
707 {
708 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
709 struct si_pm4_state *pm4 = &dsa->pm4;
710 unsigned db_depth_control;
711 unsigned db_render_override, db_render_control;
712 uint32_t db_stencil_control = 0;
713
714 if (dsa == NULL) {
715 return NULL;
716 }
717
718 dsa->valuemask[0] = state->stencil[0].valuemask;
719 dsa->valuemask[1] = state->stencil[1].valuemask;
720 dsa->writemask[0] = state->stencil[0].writemask;
721 dsa->writemask[1] = state->stencil[1].writemask;
722
723 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
724 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
725 S_028800_ZFUNC(state->depth.func);
726
727 /* stencil */
728 if (state->stencil[0].enabled) {
729 db_depth_control |= S_028800_STENCIL_ENABLE(1);
730 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
731 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
732 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
733 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
734
735 if (state->stencil[1].enabled) {
736 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
737 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
738 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
739 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
740 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
741 }
742 }
743
744 /* alpha */
745 if (state->alpha.enabled) {
746 dsa->alpha_func = state->alpha.func;
747 dsa->alpha_ref = state->alpha.ref_value;
748
749 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
750 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
751 } else {
752 dsa->alpha_func = PIPE_FUNC_ALWAYS;
753 }
754
755 /* misc */
756 db_render_control = 0;
757 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
758 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
759 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
760 /* TODO db_render_override depends on query */
761 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
762 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
763 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
764 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
765 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
766 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
767 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
768 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
769 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
770 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
771 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
772 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
773 dsa->db_render_override = db_render_override;
774
775 return dsa;
776 }
777
778 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
779 {
780 struct r600_context *rctx = (struct r600_context *)ctx;
781 struct si_state_dsa *dsa = state;
782
783 if (state == NULL)
784 return;
785
786 si_pm4_bind_state(rctx, dsa, dsa);
787 si_update_dsa_stencil_ref(rctx);
788 }
789
790 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
791 {
792 struct r600_context *rctx = (struct r600_context *)ctx;
793 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
794 }
795
796 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
797 bool copy_stencil, int sample)
798 {
799 struct pipe_depth_stencil_alpha_state dsa;
800 struct si_state_dsa *state;
801
802 memset(&dsa, 0, sizeof(dsa));
803
804 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
805 if (copy_depth || copy_stencil) {
806 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
807 S_028000_DEPTH_COPY(copy_depth) |
808 S_028000_STENCIL_COPY(copy_stencil) |
809 S_028000_COPY_CENTROID(1) |
810 S_028000_COPY_SAMPLE(sample));
811 } else {
812 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
813 S_028000_DEPTH_COMPRESS_DISABLE(1) |
814 S_028000_STENCIL_COMPRESS_DISABLE(1));
815 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
816 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
817 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
818 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
819 S_02800C_DISABLE_TILE_RATE_TILES(1));
820 }
821
822 return state;
823 }
824
825 /*
826 * format translation
827 */
828 static uint32_t si_translate_colorformat(enum pipe_format format)
829 {
830 const struct util_format_description *desc = util_format_description(format);
831
832 #define HAS_SIZE(x,y,z,w) \
833 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
834 desc->channel[2].size == (z) && desc->channel[3].size == (w))
835
836 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
837 return V_028C70_COLOR_10_11_11;
838
839 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
840 return V_028C70_COLOR_INVALID;
841
842 switch (desc->nr_channels) {
843 case 1:
844 switch (desc->channel[0].size) {
845 case 8:
846 return V_028C70_COLOR_8;
847 case 16:
848 return V_028C70_COLOR_16;
849 case 32:
850 return V_028C70_COLOR_32;
851 }
852 break;
853 case 2:
854 if (desc->channel[0].size == desc->channel[1].size) {
855 switch (desc->channel[0].size) {
856 case 8:
857 return V_028C70_COLOR_8_8;
858 case 16:
859 return V_028C70_COLOR_16_16;
860 case 32:
861 return V_028C70_COLOR_32_32;
862 }
863 } else if (HAS_SIZE(8,24,0,0)) {
864 return V_028C70_COLOR_24_8;
865 } else if (HAS_SIZE(24,8,0,0)) {
866 return V_028C70_COLOR_8_24;
867 }
868 break;
869 case 3:
870 if (HAS_SIZE(5,6,5,0)) {
871 return V_028C70_COLOR_5_6_5;
872 } else if (HAS_SIZE(32,8,24,0)) {
873 return V_028C70_COLOR_X24_8_32_FLOAT;
874 }
875 break;
876 case 4:
877 if (desc->channel[0].size == desc->channel[1].size &&
878 desc->channel[0].size == desc->channel[2].size &&
879 desc->channel[0].size == desc->channel[3].size) {
880 switch (desc->channel[0].size) {
881 case 4:
882 return V_028C70_COLOR_4_4_4_4;
883 case 8:
884 return V_028C70_COLOR_8_8_8_8;
885 case 16:
886 return V_028C70_COLOR_16_16_16_16;
887 case 32:
888 return V_028C70_COLOR_32_32_32_32;
889 }
890 } else if (HAS_SIZE(5,5,5,1)) {
891 return V_028C70_COLOR_1_5_5_5;
892 } else if (HAS_SIZE(10,10,10,2)) {
893 return V_028C70_COLOR_2_10_10_10;
894 }
895 break;
896 }
897 return V_028C70_COLOR_INVALID;
898 }
899
900 static uint32_t si_translate_colorswap(enum pipe_format format)
901 {
902 const struct util_format_description *desc = util_format_description(format);
903
904 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
905
906 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
907 return V_028C70_SWAP_STD;
908
909 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
910 return ~0;
911
912 switch (desc->nr_channels) {
913 case 1:
914 if (HAS_SWIZZLE(0,X))
915 return V_028C70_SWAP_STD; /* X___ */
916 else if (HAS_SWIZZLE(3,X))
917 return V_028C70_SWAP_ALT_REV; /* ___X */
918 break;
919 case 2:
920 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
921 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
922 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
923 return V_028C70_SWAP_STD; /* XY__ */
924 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
925 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
926 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
927 return V_028C70_SWAP_STD_REV; /* YX__ */
928 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
929 return V_028C70_SWAP_ALT; /* X__Y */
930 break;
931 case 3:
932 if (HAS_SWIZZLE(0,X))
933 return V_028C70_SWAP_STD; /* XYZ */
934 else if (HAS_SWIZZLE(0,Z))
935 return V_028C70_SWAP_STD_REV; /* ZYX */
936 break;
937 case 4:
938 /* check the middle channels, the 1st and 4th channel can be NONE */
939 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
940 return V_028C70_SWAP_STD; /* XYZW */
941 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
942 return V_028C70_SWAP_STD_REV; /* WZYX */
943 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
944 return V_028C70_SWAP_ALT; /* ZYXW */
945 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
946 return V_028C70_SWAP_ALT_REV; /* WXYZ */
947 break;
948 }
949 return ~0U;
950 }
951
952 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
953 {
954 if (R600_BIG_ENDIAN) {
955 switch(colorformat) {
956 /* 8-bit buffers. */
957 case V_028C70_COLOR_8:
958 return V_028C70_ENDIAN_NONE;
959
960 /* 16-bit buffers. */
961 case V_028C70_COLOR_5_6_5:
962 case V_028C70_COLOR_1_5_5_5:
963 case V_028C70_COLOR_4_4_4_4:
964 case V_028C70_COLOR_16:
965 case V_028C70_COLOR_8_8:
966 return V_028C70_ENDIAN_8IN16;
967
968 /* 32-bit buffers. */
969 case V_028C70_COLOR_8_8_8_8:
970 case V_028C70_COLOR_2_10_10_10:
971 case V_028C70_COLOR_8_24:
972 case V_028C70_COLOR_24_8:
973 case V_028C70_COLOR_16_16:
974 return V_028C70_ENDIAN_8IN32;
975
976 /* 64-bit buffers. */
977 case V_028C70_COLOR_16_16_16_16:
978 return V_028C70_ENDIAN_8IN16;
979
980 case V_028C70_COLOR_32_32:
981 return V_028C70_ENDIAN_8IN32;
982
983 /* 128-bit buffers. */
984 case V_028C70_COLOR_32_32_32_32:
985 return V_028C70_ENDIAN_8IN32;
986 default:
987 return V_028C70_ENDIAN_NONE; /* Unsupported. */
988 }
989 } else {
990 return V_028C70_ENDIAN_NONE;
991 }
992 }
993
994 /* Returns the size in bits of the widest component of a CB format */
995 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
996 {
997 switch(colorformat) {
998 case V_028C70_COLOR_4_4_4_4:
999 return 4;
1000
1001 case V_028C70_COLOR_1_5_5_5:
1002 case V_028C70_COLOR_5_5_5_1:
1003 return 5;
1004
1005 case V_028C70_COLOR_5_6_5:
1006 return 6;
1007
1008 case V_028C70_COLOR_8:
1009 case V_028C70_COLOR_8_8:
1010 case V_028C70_COLOR_8_8_8_8:
1011 return 8;
1012
1013 case V_028C70_COLOR_10_10_10_2:
1014 case V_028C70_COLOR_2_10_10_10:
1015 return 10;
1016
1017 case V_028C70_COLOR_10_11_11:
1018 case V_028C70_COLOR_11_11_10:
1019 return 11;
1020
1021 case V_028C70_COLOR_16:
1022 case V_028C70_COLOR_16_16:
1023 case V_028C70_COLOR_16_16_16_16:
1024 return 16;
1025
1026 case V_028C70_COLOR_8_24:
1027 case V_028C70_COLOR_24_8:
1028 return 24;
1029
1030 case V_028C70_COLOR_32:
1031 case V_028C70_COLOR_32_32:
1032 case V_028C70_COLOR_32_32_32_32:
1033 case V_028C70_COLOR_X24_8_32_FLOAT:
1034 return 32;
1035 }
1036
1037 assert(!"Unknown maximum component size");
1038 return 0;
1039 }
1040
1041 static uint32_t si_translate_dbformat(enum pipe_format format)
1042 {
1043 switch (format) {
1044 case PIPE_FORMAT_Z16_UNORM:
1045 return V_028040_Z_16;
1046 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1047 case PIPE_FORMAT_X8Z24_UNORM:
1048 case PIPE_FORMAT_Z24X8_UNORM:
1049 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1050 return V_028040_Z_24; /* deprecated on SI */
1051 case PIPE_FORMAT_Z32_FLOAT:
1052 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1053 return V_028040_Z_32_FLOAT;
1054 default:
1055 return V_028040_Z_INVALID;
1056 }
1057 }
1058
1059 /*
1060 * Texture translation
1061 */
1062
1063 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1064 enum pipe_format format,
1065 const struct util_format_description *desc,
1066 int first_non_void)
1067 {
1068 struct r600_screen *rscreen = (struct r600_screen*)screen;
1069 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1070 boolean uniform = TRUE;
1071 int i;
1072
1073 /* Colorspace (return non-RGB formats directly). */
1074 switch (desc->colorspace) {
1075 /* Depth stencil formats */
1076 case UTIL_FORMAT_COLORSPACE_ZS:
1077 switch (format) {
1078 case PIPE_FORMAT_Z16_UNORM:
1079 return V_008F14_IMG_DATA_FORMAT_16;
1080 case PIPE_FORMAT_X24S8_UINT:
1081 case PIPE_FORMAT_Z24X8_UNORM:
1082 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1083 return V_008F14_IMG_DATA_FORMAT_8_24;
1084 case PIPE_FORMAT_X8Z24_UNORM:
1085 case PIPE_FORMAT_S8X24_UINT:
1086 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1087 return V_008F14_IMG_DATA_FORMAT_24_8;
1088 case PIPE_FORMAT_S8_UINT:
1089 return V_008F14_IMG_DATA_FORMAT_8;
1090 case PIPE_FORMAT_Z32_FLOAT:
1091 return V_008F14_IMG_DATA_FORMAT_32;
1092 case PIPE_FORMAT_X32_S8X24_UINT:
1093 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1094 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1095 default:
1096 goto out_unknown;
1097 }
1098
1099 case UTIL_FORMAT_COLORSPACE_YUV:
1100 goto out_unknown; /* TODO */
1101
1102 case UTIL_FORMAT_COLORSPACE_SRGB:
1103 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1104 goto out_unknown;
1105 break;
1106
1107 default:
1108 break;
1109 }
1110
1111 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1112 if (!enable_s3tc)
1113 goto out_unknown;
1114
1115 switch (format) {
1116 case PIPE_FORMAT_RGTC1_SNORM:
1117 case PIPE_FORMAT_LATC1_SNORM:
1118 case PIPE_FORMAT_RGTC1_UNORM:
1119 case PIPE_FORMAT_LATC1_UNORM:
1120 return V_008F14_IMG_DATA_FORMAT_BC4;
1121 case PIPE_FORMAT_RGTC2_SNORM:
1122 case PIPE_FORMAT_LATC2_SNORM:
1123 case PIPE_FORMAT_RGTC2_UNORM:
1124 case PIPE_FORMAT_LATC2_UNORM:
1125 return V_008F14_IMG_DATA_FORMAT_BC5;
1126 default:
1127 goto out_unknown;
1128 }
1129 }
1130
1131 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1132
1133 if (!enable_s3tc)
1134 goto out_unknown;
1135
1136 if (!util_format_s3tc_enabled) {
1137 goto out_unknown;
1138 }
1139
1140 switch (format) {
1141 case PIPE_FORMAT_DXT1_RGB:
1142 case PIPE_FORMAT_DXT1_RGBA:
1143 case PIPE_FORMAT_DXT1_SRGB:
1144 case PIPE_FORMAT_DXT1_SRGBA:
1145 return V_008F14_IMG_DATA_FORMAT_BC1;
1146 case PIPE_FORMAT_DXT3_RGBA:
1147 case PIPE_FORMAT_DXT3_SRGBA:
1148 return V_008F14_IMG_DATA_FORMAT_BC2;
1149 case PIPE_FORMAT_DXT5_RGBA:
1150 case PIPE_FORMAT_DXT5_SRGBA:
1151 return V_008F14_IMG_DATA_FORMAT_BC3;
1152 default:
1153 goto out_unknown;
1154 }
1155 }
1156
1157 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1158 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1159 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1160 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1161 }
1162
1163 /* R8G8Bx_SNORM - TODO CxV8U8 */
1164
1165 /* See whether the components are of the same size. */
1166 for (i = 1; i < desc->nr_channels; i++) {
1167 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1168 }
1169
1170 /* Non-uniform formats. */
1171 if (!uniform) {
1172 switch(desc->nr_channels) {
1173 case 3:
1174 if (desc->channel[0].size == 5 &&
1175 desc->channel[1].size == 6 &&
1176 desc->channel[2].size == 5) {
1177 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1178 }
1179 goto out_unknown;
1180 case 4:
1181 if (desc->channel[0].size == 5 &&
1182 desc->channel[1].size == 5 &&
1183 desc->channel[2].size == 5 &&
1184 desc->channel[3].size == 1) {
1185 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1186 }
1187 if (desc->channel[0].size == 10 &&
1188 desc->channel[1].size == 10 &&
1189 desc->channel[2].size == 10 &&
1190 desc->channel[3].size == 2) {
1191 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1192 }
1193 goto out_unknown;
1194 }
1195 goto out_unknown;
1196 }
1197
1198 if (first_non_void < 0 || first_non_void > 3)
1199 goto out_unknown;
1200
1201 /* uniform formats */
1202 switch (desc->channel[first_non_void].size) {
1203 case 4:
1204 switch (desc->nr_channels) {
1205 #if 0 /* Not supported for render targets */
1206 case 2:
1207 return V_008F14_IMG_DATA_FORMAT_4_4;
1208 #endif
1209 case 4:
1210 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1211 }
1212 break;
1213 case 8:
1214 switch (desc->nr_channels) {
1215 case 1:
1216 return V_008F14_IMG_DATA_FORMAT_8;
1217 case 2:
1218 return V_008F14_IMG_DATA_FORMAT_8_8;
1219 case 4:
1220 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1221 }
1222 break;
1223 case 16:
1224 switch (desc->nr_channels) {
1225 case 1:
1226 return V_008F14_IMG_DATA_FORMAT_16;
1227 case 2:
1228 return V_008F14_IMG_DATA_FORMAT_16_16;
1229 case 4:
1230 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1231 }
1232 break;
1233 case 32:
1234 switch (desc->nr_channels) {
1235 case 1:
1236 return V_008F14_IMG_DATA_FORMAT_32;
1237 case 2:
1238 return V_008F14_IMG_DATA_FORMAT_32_32;
1239 #if 0 /* Not supported for render targets */
1240 case 3:
1241 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1242 #endif
1243 case 4:
1244 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1245 }
1246 }
1247
1248 out_unknown:
1249 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1250 return ~0;
1251 }
1252
1253 static unsigned si_tex_wrap(unsigned wrap)
1254 {
1255 switch (wrap) {
1256 default:
1257 case PIPE_TEX_WRAP_REPEAT:
1258 return V_008F30_SQ_TEX_WRAP;
1259 case PIPE_TEX_WRAP_CLAMP:
1260 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1261 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1262 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1263 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1264 return V_008F30_SQ_TEX_CLAMP_BORDER;
1265 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1266 return V_008F30_SQ_TEX_MIRROR;
1267 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1268 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1269 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1270 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1271 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1272 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1273 }
1274 }
1275
1276 static unsigned si_tex_filter(unsigned filter)
1277 {
1278 switch (filter) {
1279 default:
1280 case PIPE_TEX_FILTER_NEAREST:
1281 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1282 case PIPE_TEX_FILTER_LINEAR:
1283 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1284 }
1285 }
1286
1287 static unsigned si_tex_mipfilter(unsigned filter)
1288 {
1289 switch (filter) {
1290 case PIPE_TEX_MIPFILTER_NEAREST:
1291 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1292 case PIPE_TEX_MIPFILTER_LINEAR:
1293 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1294 default:
1295 case PIPE_TEX_MIPFILTER_NONE:
1296 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1297 }
1298 }
1299
1300 static unsigned si_tex_compare(unsigned compare)
1301 {
1302 switch (compare) {
1303 default:
1304 case PIPE_FUNC_NEVER:
1305 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1306 case PIPE_FUNC_LESS:
1307 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1308 case PIPE_FUNC_EQUAL:
1309 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1310 case PIPE_FUNC_LEQUAL:
1311 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1312 case PIPE_FUNC_GREATER:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1314 case PIPE_FUNC_NOTEQUAL:
1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1316 case PIPE_FUNC_GEQUAL:
1317 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1318 case PIPE_FUNC_ALWAYS:
1319 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1320 }
1321 }
1322
1323 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1324 {
1325 switch (dim) {
1326 default:
1327 case PIPE_TEXTURE_1D:
1328 return V_008F1C_SQ_RSRC_IMG_1D;
1329 case PIPE_TEXTURE_1D_ARRAY:
1330 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1331 case PIPE_TEXTURE_2D:
1332 case PIPE_TEXTURE_RECT:
1333 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1334 V_008F1C_SQ_RSRC_IMG_2D;
1335 case PIPE_TEXTURE_2D_ARRAY:
1336 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1337 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1338 case PIPE_TEXTURE_3D:
1339 return V_008F1C_SQ_RSRC_IMG_3D;
1340 case PIPE_TEXTURE_CUBE:
1341 return V_008F1C_SQ_RSRC_IMG_CUBE;
1342 }
1343 }
1344
1345 /*
1346 * Format support testing
1347 */
1348
1349 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1350 {
1351 return si_translate_texformat(screen, format, util_format_description(format),
1352 util_format_get_first_non_void_channel(format)) != ~0U;
1353 }
1354
1355 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1356 const struct util_format_description *desc,
1357 int first_non_void)
1358 {
1359 unsigned type = desc->channel[first_non_void].type;
1360 int i;
1361
1362 if (type == UTIL_FORMAT_TYPE_FIXED)
1363 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1364
1365 if (desc->nr_channels == 4 &&
1366 desc->channel[0].size == 10 &&
1367 desc->channel[1].size == 10 &&
1368 desc->channel[2].size == 10 &&
1369 desc->channel[3].size == 2)
1370 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1371
1372 /* See whether the components are of the same size. */
1373 for (i = 0; i < desc->nr_channels; i++) {
1374 if (desc->channel[first_non_void].size != desc->channel[i].size)
1375 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1376 }
1377
1378 switch (desc->channel[first_non_void].size) {
1379 case 8:
1380 switch (desc->nr_channels) {
1381 case 1:
1382 return V_008F0C_BUF_DATA_FORMAT_8;
1383 case 2:
1384 return V_008F0C_BUF_DATA_FORMAT_8_8;
1385 case 3:
1386 case 4:
1387 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1388 }
1389 break;
1390 case 16:
1391 switch (desc->nr_channels) {
1392 case 1:
1393 return V_008F0C_BUF_DATA_FORMAT_16;
1394 case 2:
1395 return V_008F0C_BUF_DATA_FORMAT_16_16;
1396 case 3:
1397 case 4:
1398 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1399 }
1400 break;
1401 case 32:
1402 /* From the Southern Islands ISA documentation about MTBUF:
1403 * 'Memory reads of data in memory that is 32 or 64 bits do not
1404 * undergo any format conversion.'
1405 */
1406 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1407 !desc->channel[first_non_void].pure_integer)
1408 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1409
1410 switch (desc->nr_channels) {
1411 case 1:
1412 return V_008F0C_BUF_DATA_FORMAT_32;
1413 case 2:
1414 return V_008F0C_BUF_DATA_FORMAT_32_32;
1415 case 3:
1416 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1417 case 4:
1418 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1419 }
1420 break;
1421 }
1422
1423 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1424 }
1425
1426 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1427 const struct util_format_description *desc,
1428 int first_non_void)
1429 {
1430 switch (desc->channel[first_non_void].type) {
1431 case UTIL_FORMAT_TYPE_SIGNED:
1432 if (desc->channel[first_non_void].normalized)
1433 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1434 else if (desc->channel[first_non_void].pure_integer)
1435 return V_008F0C_BUF_NUM_FORMAT_SINT;
1436 else
1437 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1438 break;
1439 case UTIL_FORMAT_TYPE_UNSIGNED:
1440 if (desc->channel[first_non_void].normalized)
1441 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1442 else if (desc->channel[first_non_void].pure_integer)
1443 return V_008F0C_BUF_NUM_FORMAT_UINT;
1444 else
1445 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1446 break;
1447 case UTIL_FORMAT_TYPE_FLOAT:
1448 default:
1449 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1450 }
1451 }
1452
1453 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1454 {
1455 const struct util_format_description *desc;
1456 int first_non_void;
1457 unsigned data_format;
1458
1459 desc = util_format_description(format);
1460 first_non_void = util_format_get_first_non_void_channel(format);
1461 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1462 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1463 }
1464
1465 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1466 {
1467 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1468 si_translate_colorswap(format) != ~0U;
1469 }
1470
1471 static bool si_is_zs_format_supported(enum pipe_format format)
1472 {
1473 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1474 }
1475
1476 boolean si_is_format_supported(struct pipe_screen *screen,
1477 enum pipe_format format,
1478 enum pipe_texture_target target,
1479 unsigned sample_count,
1480 unsigned usage)
1481 {
1482 struct r600_screen *rscreen = (struct r600_screen *)screen;
1483 unsigned retval = 0;
1484
1485 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1486 R600_ERR("r600: unsupported texture type %d\n", target);
1487 return FALSE;
1488 }
1489
1490 if (!util_format_is_supported(format, usage))
1491 return FALSE;
1492
1493 if (sample_count > 1) {
1494 if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI)
1495 return FALSE;
1496
1497 switch (sample_count) {
1498 case 2:
1499 case 4:
1500 case 8:
1501 break;
1502 default:
1503 return FALSE;
1504 }
1505 }
1506
1507 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1508 if (target == PIPE_BUFFER) {
1509 if (si_is_vertex_format_supported(screen, format))
1510 retval |= PIPE_BIND_SAMPLER_VIEW;
1511 } else {
1512 if (si_is_sampler_format_supported(screen, format))
1513 retval |= PIPE_BIND_SAMPLER_VIEW;
1514 }
1515 }
1516
1517 if ((usage & (PIPE_BIND_RENDER_TARGET |
1518 PIPE_BIND_DISPLAY_TARGET |
1519 PIPE_BIND_SCANOUT |
1520 PIPE_BIND_SHARED)) &&
1521 si_is_colorbuffer_format_supported(format)) {
1522 retval |= usage &
1523 (PIPE_BIND_RENDER_TARGET |
1524 PIPE_BIND_DISPLAY_TARGET |
1525 PIPE_BIND_SCANOUT |
1526 PIPE_BIND_SHARED);
1527 }
1528
1529 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1530 si_is_zs_format_supported(format)) {
1531 retval |= PIPE_BIND_DEPTH_STENCIL;
1532 }
1533
1534 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1535 si_is_vertex_format_supported(screen, format)) {
1536 retval |= PIPE_BIND_VERTEX_BUFFER;
1537 }
1538
1539 if (usage & PIPE_BIND_TRANSFER_READ)
1540 retval |= PIPE_BIND_TRANSFER_READ;
1541 if (usage & PIPE_BIND_TRANSFER_WRITE)
1542 retval |= PIPE_BIND_TRANSFER_WRITE;
1543
1544 return retval == usage;
1545 }
1546
1547 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1548 {
1549 unsigned tile_mode_index = 0;
1550
1551 if (stencil) {
1552 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1553 } else {
1554 tile_mode_index = rtex->surface.tiling_index[level];
1555 }
1556 return tile_mode_index;
1557 }
1558
1559 /*
1560 * framebuffer handling
1561 */
1562
1563 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1564 const struct pipe_framebuffer_state *state, int cb)
1565 {
1566 struct r600_texture *rtex;
1567 struct r600_surface *surf;
1568 unsigned level = state->cbufs[cb]->u.tex.level;
1569 unsigned pitch, slice;
1570 unsigned color_info, color_attrib;
1571 unsigned tile_mode_index;
1572 unsigned format, swap, ntype, endian;
1573 uint64_t offset;
1574 const struct util_format_description *desc;
1575 int i;
1576 unsigned blend_clamp = 0, blend_bypass = 0;
1577 unsigned max_comp_size;
1578
1579 surf = (struct r600_surface *)state->cbufs[cb];
1580 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1581
1582 offset = rtex->surface.level[level].offset;
1583 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1584 offset += rtex->surface.level[level].slice_size *
1585 state->cbufs[cb]->u.tex.first_layer;
1586 }
1587 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1588 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1589 if (slice) {
1590 slice = slice - 1;
1591 }
1592
1593 tile_mode_index = si_tile_mode_index(rtex, level, false);
1594
1595 desc = util_format_description(surf->base.format);
1596 for (i = 0; i < 4; i++) {
1597 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1598 break;
1599 }
1600 }
1601 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1602 ntype = V_028C70_NUMBER_FLOAT;
1603 } else {
1604 ntype = V_028C70_NUMBER_UNORM;
1605 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1606 ntype = V_028C70_NUMBER_SRGB;
1607 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1608 if (desc->channel[i].pure_integer) {
1609 ntype = V_028C70_NUMBER_SINT;
1610 } else {
1611 assert(desc->channel[i].normalized);
1612 ntype = V_028C70_NUMBER_SNORM;
1613 }
1614 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1615 if (desc->channel[i].pure_integer) {
1616 ntype = V_028C70_NUMBER_UINT;
1617 } else {
1618 assert(desc->channel[i].normalized);
1619 ntype = V_028C70_NUMBER_UNORM;
1620 }
1621 }
1622 }
1623
1624 format = si_translate_colorformat(surf->base.format);
1625 if (format == V_028C70_COLOR_INVALID) {
1626 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1627 }
1628 assert(format != V_028C70_COLOR_INVALID);
1629 swap = si_translate_colorswap(surf->base.format);
1630 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1631 endian = V_028C70_ENDIAN_NONE;
1632 } else {
1633 endian = si_colorformat_endian_swap(format);
1634 }
1635
1636 /* blend clamp should be set for all NORM/SRGB types */
1637 if (ntype == V_028C70_NUMBER_UNORM ||
1638 ntype == V_028C70_NUMBER_SNORM ||
1639 ntype == V_028C70_NUMBER_SRGB)
1640 blend_clamp = 1;
1641
1642 /* set blend bypass according to docs if SINT/UINT or
1643 8/24 COLOR variants */
1644 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1645 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1646 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1647 blend_clamp = 0;
1648 blend_bypass = 1;
1649 }
1650
1651 color_info = S_028C70_FORMAT(format) |
1652 S_028C70_COMP_SWAP(swap) |
1653 S_028C70_BLEND_CLAMP(blend_clamp) |
1654 S_028C70_BLEND_BYPASS(blend_bypass) |
1655 S_028C70_NUMBER_TYPE(ntype) |
1656 S_028C70_ENDIAN(endian);
1657
1658 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1659 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1660
1661 if (rtex->resource.b.b.nr_samples > 1) {
1662 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1663
1664 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1665 S_028C74_NUM_FRAGMENTS(log_samples);
1666
1667 if (rtex->fmask.size) {
1668 color_info |= S_028C70_COMPRESSION(1);
1669 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1670
1671 /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */
1672 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) |
1673 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1674 }
1675 }
1676
1677 if (rtex->cmask.size) {
1678 color_info |= S_028C70_FAST_CLEAR(1);
1679 }
1680
1681 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1682 offset >>= 8;
1683
1684 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1685 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1686 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1687 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1688 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1689
1690 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1691 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1692 } else {
1693 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1694 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1695 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1696 }
1697 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1698 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1699
1700 if (rtex->cmask.size) {
1701 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1702 offset + (rtex->cmask.offset >> 8));
1703 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1704 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1705 }
1706 if (rtex->fmask.size) {
1707 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1708 offset + (rtex->fmask.offset >> 8));
1709 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1710 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1711 }
1712
1713 /* set CB_COLOR1_INFO for possible dual-src blending */
1714 if (state->nr_cbufs == 1) {
1715 assert(cb == 0);
1716 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1717 }
1718
1719 /* Determine pixel shader export format */
1720 max_comp_size = si_colorformat_max_comp_size(format);
1721 if (ntype == V_028C70_NUMBER_SRGB ||
1722 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1723 max_comp_size <= 10) ||
1724 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1725 rctx->export_16bpc |= 1 << cb;
1726 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1727 if (state->nr_cbufs == 1)
1728 rctx->export_16bpc |= 1 << 1;
1729 }
1730 }
1731
1732 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1733 const struct pipe_framebuffer_state *state)
1734 {
1735 struct r600_screen *rscreen = rctx->screen;
1736 struct r600_texture *rtex;
1737 struct r600_surface *surf;
1738 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1739 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1740 uint32_t z_info, s_info, db_depth_info;
1741 uint64_t z_offs, s_offs;
1742
1743 if (state->zsbuf == NULL) {
1744 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1745 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1746 return;
1747 }
1748
1749 surf = (struct r600_surface *)state->zsbuf;
1750 level = surf->base.u.tex.level;
1751 rtex = (struct r600_texture*)surf->base.texture;
1752
1753 format = si_translate_dbformat(rtex->resource.b.b.format);
1754
1755 if (format == V_028040_Z_INVALID) {
1756 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1757 }
1758 assert(format != V_028040_Z_INVALID);
1759
1760 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1761 z_offs += rtex->surface.level[level].offset;
1762 s_offs += rtex->surface.stencil_level[level].offset;
1763
1764 z_offs >>= 8;
1765 s_offs >>= 8;
1766
1767 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1768 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1769 if (slice) {
1770 slice = slice - 1;
1771 }
1772
1773 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1774
1775 z_info = S_028040_FORMAT(format);
1776 if (rtex->resource.b.b.nr_samples > 1) {
1777 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1778 }
1779
1780 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1781 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1782 else
1783 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1784
1785 if (rctx->b.chip_class >= CIK) {
1786 switch (rtex->surface.level[level].mode) {
1787 case RADEON_SURF_MODE_2D:
1788 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1789 break;
1790 case RADEON_SURF_MODE_1D:
1791 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1792 case RADEON_SURF_MODE_LINEAR:
1793 default:
1794 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1795 break;
1796 }
1797 tile_split = rtex->surface.tile_split;
1798 stile_split = rtex->surface.stencil_tile_split;
1799 macro_aspect = rtex->surface.mtilea;
1800 bankw = rtex->surface.bankw;
1801 bankh = rtex->surface.bankh;
1802 tile_split = cik_tile_split(tile_split);
1803 stile_split = cik_tile_split(stile_split);
1804 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1805 bankw = cik_bank_wh(bankw);
1806 bankh = cik_bank_wh(bankh);
1807 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1808 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1809 rscreen->b.info.r600_num_backends);
1810
1811 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1812 S_02803C_PIPE_CONFIG(pipe_config) |
1813 S_02803C_BANK_WIDTH(bankw) |
1814 S_02803C_BANK_HEIGHT(bankh) |
1815 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1816 S_02803C_NUM_BANKS(nbanks);
1817 z_info |= S_028040_TILE_SPLIT(tile_split);
1818 s_info |= S_028044_TILE_SPLIT(stile_split);
1819 } else {
1820 tile_mode_index = si_tile_mode_index(rtex, level, false);
1821 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1822 tile_mode_index = si_tile_mode_index(rtex, level, true);
1823 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1824 }
1825
1826 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1827 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1828 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1829
1830 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1831 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1832 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1833
1834 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1835 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1836 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1837 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1838 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1839
1840 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1841 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1842 }
1843
1844 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1845 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1846 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1847 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1848 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1849
1850 /* 2xMSAA
1851 * There are two locations (-4, 4), (4, -4). */
1852 static uint32_t sample_locs_2x[] = {
1853 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1854 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1855 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1856 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1857 };
1858 static unsigned max_dist_2x = 4;
1859 /* 4xMSAA
1860 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1861 static uint32_t sample_locs_4x[] = {
1862 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1863 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1864 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1865 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1866 };
1867 static unsigned max_dist_4x = 6;
1868 /* Cayman/SI 8xMSAA */
1869 static uint32_t cm_sample_locs_8x[] = {
1870 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1871 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1872 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1873 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1874 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1875 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1876 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1877 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1878 };
1879 static unsigned cm_max_dist_8x = 8;
1880 /* Cayman/SI 16xMSAA */
1881 static uint32_t cm_sample_locs_16x[] = {
1882 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1883 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1884 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1885 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1886 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1887 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1888 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1889 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1890 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1891 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1892 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1893 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1894 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1895 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1896 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1897 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1898 };
1899 static unsigned cm_max_dist_16x = 8;
1900
1901 static void si_get_sample_position(struct pipe_context *ctx,
1902 unsigned sample_count,
1903 unsigned sample_index,
1904 float *out_value)
1905 {
1906 int offset, index;
1907 struct {
1908 int idx:4;
1909 } val;
1910 switch (sample_count) {
1911 case 1:
1912 default:
1913 out_value[0] = out_value[1] = 0.5;
1914 break;
1915 case 2:
1916 offset = 4 * (sample_index * 2);
1917 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1918 out_value[0] = (float)(val.idx + 8) / 16.0f;
1919 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1920 out_value[1] = (float)(val.idx + 8) / 16.0f;
1921 break;
1922 case 4:
1923 offset = 4 * (sample_index * 2);
1924 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1925 out_value[0] = (float)(val.idx + 8) / 16.0f;
1926 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1927 out_value[1] = (float)(val.idx + 8) / 16.0f;
1928 break;
1929 case 8:
1930 offset = 4 * (sample_index % 4 * 2);
1931 index = (sample_index / 4) * 4;
1932 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1933 out_value[0] = (float)(val.idx + 8) / 16.0f;
1934 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1935 out_value[1] = (float)(val.idx + 8) / 16.0f;
1936 break;
1937 case 16:
1938 offset = 4 * (sample_index % 4 * 2);
1939 index = (sample_index / 4) * 4;
1940 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1941 out_value[0] = (float)(val.idx + 8) / 16.0f;
1942 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1943 out_value[1] = (float)(val.idx + 8) / 16.0f;
1944 break;
1945 }
1946 }
1947
1948 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1949 {
1950 unsigned max_dist = 0;
1951
1952 switch (nr_samples) {
1953 default:
1954 nr_samples = 0;
1955 break;
1956 case 2:
1957 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1958 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1959 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1960 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1961 max_dist = max_dist_2x;
1962 break;
1963 case 4:
1964 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1965 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1966 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1967 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1968 max_dist = max_dist_4x;
1969 break;
1970 case 8:
1971 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1972 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1973 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1974 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1975 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1976 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1977 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1978 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1979 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1980 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1981 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1982 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
1983 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
1984 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
1985 max_dist = cm_max_dist_8x;
1986 break;
1987 case 16:
1988 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
1989 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
1990 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
1991 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
1992 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
1993 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
1994 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
1995 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
1996 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
1997 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
1998 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
1999 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2000 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2001 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2002 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2003 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2004 max_dist = cm_max_dist_16x;
2005 break;
2006 }
2007
2008 if (nr_samples > 1) {
2009 unsigned log_samples = util_logbase2(nr_samples);
2010
2011 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2012 S_028BDC_LAST_PIXEL(1) |
2013 S_028BDC_EXPAND_LINE_WIDTH(1));
2014 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2015 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2016 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2017 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2018
2019 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2020 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2021 S_028804_PS_ITER_SAMPLES(log_samples) |
2022 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2023 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2024 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2025 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2026 } else {
2027 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2028 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2029
2030 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2031 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2032 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2033 }
2034 }
2035
2036 static void si_set_framebuffer_state(struct pipe_context *ctx,
2037 const struct pipe_framebuffer_state *state)
2038 {
2039 struct r600_context *rctx = (struct r600_context *)ctx;
2040 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2041 uint32_t tl, br;
2042 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2043
2044 if (pm4 == NULL)
2045 return;
2046
2047 if (rctx->framebuffer.nr_cbufs) {
2048 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2049 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2050 }
2051 if (rctx->framebuffer.zsbuf) {
2052 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2053 }
2054
2055 util_copy_framebuffer_state(&rctx->framebuffer, state);
2056
2057 /* build states */
2058 rctx->export_16bpc = 0;
2059 rctx->fb_compressed_cb_mask = 0;
2060 for (i = 0; i < state->nr_cbufs; i++) {
2061 struct r600_texture *rtex =
2062 (struct r600_texture*)state->cbufs[i]->texture;
2063
2064 si_cb(rctx, pm4, state, i);
2065
2066 if (rtex->fmask.size || rtex->cmask.size) {
2067 rctx->fb_compressed_cb_mask |= 1 << i;
2068 }
2069 }
2070 for (; i < 8; i++) {
2071 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2072 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2073 }
2074
2075 assert(!(rctx->export_16bpc & ~0xff));
2076 si_db(rctx, pm4, state);
2077
2078 tl_x = 0;
2079 tl_y = 0;
2080 br_x = state->width;
2081 br_y = state->height;
2082
2083 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2084 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2085
2086 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2087 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2088 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2089 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2090 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2091 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2092 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2093 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2094 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2095 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2096
2097 if (state->nr_cbufs)
2098 nr_samples = state->cbufs[0]->texture->nr_samples;
2099 else if (state->zsbuf)
2100 nr_samples = state->zsbuf->texture->nr_samples;
2101 else
2102 nr_samples = 0;
2103
2104 si_set_msaa_state(rctx, pm4, nr_samples);
2105 rctx->fb_log_samples = util_logbase2(nr_samples);
2106 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2107 util_format_is_pure_integer(state->cbufs[0]->format);
2108
2109 si_pm4_set_state(rctx, framebuffer, pm4);
2110 si_update_fb_rs_state(rctx);
2111 si_update_fb_blend_state(rctx);
2112 }
2113
2114 /*
2115 * shaders
2116 */
2117
2118 /* Compute the key for the hw shader variant */
2119 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2120 struct si_pipe_shader_selector *sel,
2121 union si_shader_key *key)
2122 {
2123 struct r600_context *rctx = (struct r600_context *)ctx;
2124 memset(key, 0, sizeof(*key));
2125
2126 if (sel->type == PIPE_SHADER_VERTEX) {
2127 unsigned i;
2128 if (!rctx->vertex_elements)
2129 return;
2130
2131 for (i = 0; i < rctx->vertex_elements->count; ++i)
2132 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2133
2134 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2135 key->vs.ucps_enabled |= 0x2;
2136 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2137 key->vs.ucps_enabled |= 0x1;
2138 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2139 if (sel->fs_write_all)
2140 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2141 key->ps.export_16bpc = rctx->export_16bpc;
2142
2143 if (rctx->queued.named.rasterizer) {
2144 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2145 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2146
2147 if (rctx->queued.named.blend) {
2148 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2149 rctx->queued.named.rasterizer->multisample_enable &&
2150 !rctx->fb_cb0_is_integer;
2151 }
2152 }
2153 if (rctx->queued.named.dsa) {
2154 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2155
2156 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2157 if (rctx->framebuffer.nr_cbufs &&
2158 rctx->framebuffer.cbufs[0] &&
2159 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2160 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2161 } else {
2162 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2163 }
2164 }
2165 }
2166
2167 /* Select the hw shader variant depending on the current state.
2168 * (*dirty) is set to 1 if current variant was changed */
2169 int si_shader_select(struct pipe_context *ctx,
2170 struct si_pipe_shader_selector *sel,
2171 unsigned *dirty)
2172 {
2173 union si_shader_key key;
2174 struct si_pipe_shader * shader = NULL;
2175 int r;
2176
2177 si_shader_selector_key(ctx, sel, &key);
2178
2179 /* Check if we don't need to change anything.
2180 * This path is also used for most shaders that don't need multiple
2181 * variants, it will cost just a computation of the key and this
2182 * test. */
2183 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2184 return 0;
2185 }
2186
2187 /* lookup if we have other variants in the list */
2188 if (sel->num_shaders > 1) {
2189 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2190
2191 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2192 p = c;
2193 c = c->next_variant;
2194 }
2195
2196 if (c) {
2197 p->next_variant = c->next_variant;
2198 shader = c;
2199 }
2200 }
2201
2202 if (unlikely(!shader)) {
2203 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2204 shader->selector = sel;
2205 shader->key = key;
2206
2207 r = si_pipe_shader_create(ctx, shader);
2208 if (unlikely(r)) {
2209 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2210 sel->type, r);
2211 sel->current = NULL;
2212 FREE(shader);
2213 return r;
2214 }
2215
2216 /* We don't know the value of fs_write_all property until we built
2217 * at least one variant, so we may need to recompute the key (include
2218 * rctx->framebuffer.nr_cbufs) after building first variant. */
2219 if (sel->type == PIPE_SHADER_FRAGMENT &&
2220 sel->num_shaders == 0 &&
2221 shader->shader.fs_write_all) {
2222 sel->fs_write_all = 1;
2223 si_shader_selector_key(ctx, sel, &shader->key);
2224 }
2225
2226 sel->num_shaders++;
2227 }
2228
2229 if (dirty)
2230 *dirty = 1;
2231
2232 shader->next_variant = sel->current;
2233 sel->current = shader;
2234
2235 return 0;
2236 }
2237
2238 static void *si_create_shader_state(struct pipe_context *ctx,
2239 const struct pipe_shader_state *state,
2240 unsigned pipe_shader_type)
2241 {
2242 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2243 int r;
2244
2245 sel->type = pipe_shader_type;
2246 sel->tokens = tgsi_dup_tokens(state->tokens);
2247 sel->so = state->stream_output;
2248
2249 r = si_shader_select(ctx, sel, NULL);
2250 if (r) {
2251 free(sel);
2252 return NULL;
2253 }
2254
2255 return sel;
2256 }
2257
2258 static void *si_create_fs_state(struct pipe_context *ctx,
2259 const struct pipe_shader_state *state)
2260 {
2261 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2262 }
2263
2264 static void *si_create_vs_state(struct pipe_context *ctx,
2265 const struct pipe_shader_state *state)
2266 {
2267 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2268 }
2269
2270 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2271 {
2272 struct r600_context *rctx = (struct r600_context *)ctx;
2273 struct si_pipe_shader_selector *sel = state;
2274
2275 if (rctx->vs_shader == sel)
2276 return;
2277
2278 rctx->vs_shader = sel;
2279
2280 if (sel && sel->current) {
2281 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2282 rctx->b.streamout.stride_in_dw = sel->so.stride;
2283 } else {
2284 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2285 }
2286
2287 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2288 }
2289
2290 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2291 {
2292 struct r600_context *rctx = (struct r600_context *)ctx;
2293 struct si_pipe_shader_selector *sel = state;
2294
2295 if (rctx->ps_shader == sel)
2296 return;
2297
2298 rctx->ps_shader = sel;
2299
2300 if (sel && sel->current)
2301 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2302 else
2303 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2304
2305 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2306 }
2307
2308 static void si_delete_shader_selector(struct pipe_context *ctx,
2309 struct si_pipe_shader_selector *sel)
2310 {
2311 struct r600_context *rctx = (struct r600_context *)ctx;
2312 struct si_pipe_shader *p = sel->current, *c;
2313
2314 while (p) {
2315 c = p->next_variant;
2316 si_pm4_delete_state(rctx, vs, p->pm4);
2317 si_pipe_shader_destroy(ctx, p);
2318 free(p);
2319 p = c;
2320 }
2321
2322 free(sel->tokens);
2323 free(sel);
2324 }
2325
2326 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2327 {
2328 struct r600_context *rctx = (struct r600_context *)ctx;
2329 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2330
2331 if (rctx->vs_shader == sel) {
2332 rctx->vs_shader = NULL;
2333 }
2334
2335 si_delete_shader_selector(ctx, sel);
2336 }
2337
2338 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2339 {
2340 struct r600_context *rctx = (struct r600_context *)ctx;
2341 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2342
2343 if (rctx->ps_shader == sel) {
2344 rctx->ps_shader = NULL;
2345 }
2346
2347 si_delete_shader_selector(ctx, sel);
2348 }
2349
2350 /*
2351 * Samplers
2352 */
2353
2354 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2355 struct pipe_resource *texture,
2356 const struct pipe_sampler_view *state)
2357 {
2358 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2359 struct r600_texture *tmp = (struct r600_texture*)texture;
2360 const struct util_format_description *desc;
2361 unsigned format, num_format;
2362 uint32_t pitch = 0;
2363 unsigned char state_swizzle[4], swizzle[4];
2364 unsigned height, depth, width;
2365 enum pipe_format pipe_format = state->format;
2366 struct radeon_surface_level *surflevel;
2367 int first_non_void;
2368 uint64_t va;
2369
2370 if (view == NULL)
2371 return NULL;
2372
2373 /* initialize base object */
2374 view->base = *state;
2375 view->base.texture = NULL;
2376 pipe_resource_reference(&view->base.texture, texture);
2377 view->base.reference.count = 1;
2378 view->base.context = ctx;
2379 view->resource = &tmp->resource;
2380
2381 /* Buffer resource. */
2382 if (texture->target == PIPE_BUFFER) {
2383 unsigned stride;
2384
2385 desc = util_format_description(state->format);
2386 first_non_void = util_format_get_first_non_void_channel(state->format);
2387 stride = desc->block.bits / 8;
2388 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2389 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2390 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2391
2392 view->state[0] = va;
2393 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2394 S_008F04_STRIDE(stride);
2395 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2396 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2397 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2398 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2399 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2400 S_008F0C_NUM_FORMAT(num_format) |
2401 S_008F0C_DATA_FORMAT(format);
2402 return &view->base;
2403 }
2404
2405 state_swizzle[0] = state->swizzle_r;
2406 state_swizzle[1] = state->swizzle_g;
2407 state_swizzle[2] = state->swizzle_b;
2408 state_swizzle[3] = state->swizzle_a;
2409
2410 surflevel = tmp->surface.level;
2411
2412 /* Texturing with separate depth and stencil. */
2413 if (tmp->is_depth && !tmp->is_flushing_texture) {
2414 switch (pipe_format) {
2415 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2416 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2417 break;
2418 case PIPE_FORMAT_X8Z24_UNORM:
2419 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2420 /* Z24 is always stored like this. */
2421 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2422 break;
2423 case PIPE_FORMAT_X24S8_UINT:
2424 case PIPE_FORMAT_S8X24_UINT:
2425 case PIPE_FORMAT_X32_S8X24_UINT:
2426 pipe_format = PIPE_FORMAT_S8_UINT;
2427 surflevel = tmp->surface.stencil_level;
2428 break;
2429 default:;
2430 }
2431 }
2432
2433 desc = util_format_description(pipe_format);
2434
2435 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2436 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2437 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2438
2439 switch (pipe_format) {
2440 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2441 case PIPE_FORMAT_X24S8_UINT:
2442 case PIPE_FORMAT_X32_S8X24_UINT:
2443 case PIPE_FORMAT_X8Z24_UNORM:
2444 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2445 break;
2446 default:
2447 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2448 }
2449 } else {
2450 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2451 }
2452
2453 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2454
2455 switch (pipe_format) {
2456 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2457 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2458 break;
2459 default:
2460 if (first_non_void < 0) {
2461 if (util_format_is_compressed(pipe_format)) {
2462 switch (pipe_format) {
2463 case PIPE_FORMAT_DXT1_SRGB:
2464 case PIPE_FORMAT_DXT1_SRGBA:
2465 case PIPE_FORMAT_DXT3_SRGBA:
2466 case PIPE_FORMAT_DXT5_SRGBA:
2467 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2468 break;
2469 case PIPE_FORMAT_RGTC1_SNORM:
2470 case PIPE_FORMAT_LATC1_SNORM:
2471 case PIPE_FORMAT_RGTC2_SNORM:
2472 case PIPE_FORMAT_LATC2_SNORM:
2473 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2474 break;
2475 default:
2476 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2477 break;
2478 }
2479 } else {
2480 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2481 }
2482 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2483 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2484 } else {
2485 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2486
2487 switch (desc->channel[first_non_void].type) {
2488 case UTIL_FORMAT_TYPE_FLOAT:
2489 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2490 break;
2491 case UTIL_FORMAT_TYPE_SIGNED:
2492 if (desc->channel[first_non_void].normalized)
2493 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2494 else if (desc->channel[first_non_void].pure_integer)
2495 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2496 else
2497 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2498 break;
2499 case UTIL_FORMAT_TYPE_UNSIGNED:
2500 if (desc->channel[first_non_void].normalized)
2501 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2502 else if (desc->channel[first_non_void].pure_integer)
2503 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2504 else
2505 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2506 }
2507 }
2508 }
2509
2510 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2511 if (format == ~0) {
2512 format = 0;
2513 }
2514
2515 /* not supported any more */
2516 //endian = si_colorformat_endian_swap(format);
2517
2518 width = surflevel[0].npix_x;
2519 height = surflevel[0].npix_y;
2520 depth = surflevel[0].npix_z;
2521 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2522
2523 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2524 height = 1;
2525 depth = texture->array_size;
2526 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2527 depth = texture->array_size;
2528 }
2529
2530 va = r600_resource_va(ctx->screen, texture);
2531 va += surflevel[0].offset;
2532 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2533 view->state[0] = va >> 8;
2534 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2535 S_008F14_DATA_FORMAT(format) |
2536 S_008F14_NUM_FORMAT(num_format));
2537 view->state[2] = (S_008F18_WIDTH(width - 1) |
2538 S_008F18_HEIGHT(height - 1));
2539 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2540 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2541 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2542 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2543 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2544 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2545 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2546 util_logbase2(texture->nr_samples) :
2547 state->u.tex.last_level - tmp->mipmap_shift) |
2548 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2549 S_008F1C_POW2_PAD(texture->last_level > 0) |
2550 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2551 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2552 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2553 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2554 view->state[6] = 0;
2555 view->state[7] = 0;
2556
2557 /* Initialize the sampler view for FMASK. */
2558 if (tmp->fmask.size) {
2559 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2560 uint32_t fmask_format;
2561
2562 switch (texture->nr_samples) {
2563 case 2:
2564 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2565 break;
2566 case 4:
2567 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2568 break;
2569 case 8:
2570 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2571 break;
2572 default:
2573 assert(0);
2574 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2575 }
2576
2577 view->fmask_state[0] = va >> 8;
2578 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2579 S_008F14_DATA_FORMAT(fmask_format) |
2580 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2581 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2582 S_008F18_HEIGHT(height - 1);
2583 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2584 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2585 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2586 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2587 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2588 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2589 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2590 S_008F20_PITCH(tmp->fmask.pitch - 1);
2591 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2592 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2593 view->fmask_state[6] = 0;
2594 view->fmask_state[7] = 0;
2595 }
2596
2597 return &view->base;
2598 }
2599
2600 static void si_sampler_view_destroy(struct pipe_context *ctx,
2601 struct pipe_sampler_view *state)
2602 {
2603 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2604
2605 pipe_resource_reference(&state->texture, NULL);
2606 FREE(resource);
2607 }
2608
2609 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2610 {
2611 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2612 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2613 (linear_filter &&
2614 (wrap == PIPE_TEX_WRAP_CLAMP ||
2615 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2616 }
2617
2618 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2619 {
2620 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2621 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2622
2623 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2624 state->border_color.ui[2] || state->border_color.ui[3]) &&
2625 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2626 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2627 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2628 }
2629
2630 static void *si_create_sampler_state(struct pipe_context *ctx,
2631 const struct pipe_sampler_state *state)
2632 {
2633 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2634 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2635 unsigned border_color_type;
2636
2637 if (rstate == NULL) {
2638 return NULL;
2639 }
2640
2641 if (sampler_state_needs_border_color(state))
2642 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2643 else
2644 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2645
2646 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2647 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2648 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2649 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2650 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2651 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2652 aniso_flag_offset << 16 | /* XXX */
2653 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2654 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2655 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2656 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2657 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2658 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2659 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2660 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2661
2662 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2663 memcpy(rstate->border_color, state->border_color.ui,
2664 sizeof(rstate->border_color));
2665 }
2666
2667 return rstate;
2668 }
2669
2670 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2671 * the si_set_sampler_view calls. LTO might help too. */
2672 static void si_set_sampler_views(struct pipe_context *ctx,
2673 unsigned shader, unsigned start,
2674 unsigned count,
2675 struct pipe_sampler_view **views)
2676 {
2677 struct r600_context *rctx = (struct r600_context *)ctx;
2678 struct r600_textures_info *samplers = &rctx->samplers[shader];
2679 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2680 int i;
2681
2682 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2683 return;
2684
2685 assert(start == 0);
2686
2687 for (i = 0; i < count; i++) {
2688 if (!views[i]) {
2689 samplers->depth_texture_mask &= ~(1 << i);
2690 samplers->compressed_colortex_mask &= ~(1 << i);
2691 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2692 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2693 NULL, NULL);
2694 continue;
2695 }
2696
2697 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2698
2699 if (views[i]->texture->target != PIPE_BUFFER) {
2700 struct r600_texture *rtex =
2701 (struct r600_texture*)views[i]->texture;
2702
2703 if (rtex->is_depth && !rtex->is_flushing_texture) {
2704 samplers->depth_texture_mask |= 1 << i;
2705 } else {
2706 samplers->depth_texture_mask &= ~(1 << i);
2707 }
2708 if (rtex->cmask.size || rtex->fmask.size) {
2709 samplers->compressed_colortex_mask |= 1 << i;
2710 } else {
2711 samplers->compressed_colortex_mask &= ~(1 << i);
2712 }
2713
2714 if (rtex->fmask.size) {
2715 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2716 views[i], rviews[i]->fmask_state);
2717 } else {
2718 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2719 NULL, NULL);
2720 }
2721 }
2722 }
2723 for (; i < samplers->n_views; i++) {
2724 samplers->depth_texture_mask &= ~(1 << i);
2725 samplers->compressed_colortex_mask &= ~(1 << i);
2726 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2727 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2728 NULL, NULL);
2729 }
2730
2731 samplers->n_views = count;
2732 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2733 }
2734
2735 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2736 void **states,
2737 struct r600_textures_info *samplers,
2738 unsigned user_data_reg)
2739 {
2740 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2741 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2742 uint32_t *border_color_table = NULL;
2743 int i, j;
2744
2745 if (!count)
2746 goto out;
2747
2748 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2749
2750 si_pm4_sh_data_begin(pm4);
2751 for (i = 0; i < count; i++) {
2752 if (rstates[i] &&
2753 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2754 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2755 if (!rctx->border_color_table ||
2756 ((rctx->border_color_offset + count - i) &
2757 C_008F3C_BORDER_COLOR_PTR)) {
2758 r600_resource_reference(&rctx->border_color_table, NULL);
2759 rctx->border_color_offset = 0;
2760
2761 rctx->border_color_table =
2762 r600_resource_create_custom(&rctx->screen->b.b,
2763 PIPE_USAGE_STAGING,
2764 4096 * 4 * 4);
2765 }
2766
2767 if (!border_color_table) {
2768 border_color_table =
2769 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2770 rctx->b.rings.gfx.cs,
2771 PIPE_TRANSFER_WRITE |
2772 PIPE_TRANSFER_UNSYNCHRONIZED);
2773 }
2774
2775 for (j = 0; j < 4; j++) {
2776 border_color_table[4 * rctx->border_color_offset + j] =
2777 util_le32_to_cpu(rstates[i]->border_color[j]);
2778 }
2779
2780 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2781 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2782 }
2783
2784 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2785 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2786 }
2787 }
2788 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2789
2790 if (border_color_table) {
2791 uint64_t va_offset =
2792 r600_resource_va(&rctx->screen->b.b,
2793 (void*)rctx->border_color_table);
2794
2795 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2796 if (rctx->b.chip_class >= CIK)
2797 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2798 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2799 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2800 }
2801
2802 memcpy(samplers->samplers, states, sizeof(void*) * count);
2803
2804 out:
2805 samplers->n_samplers = count;
2806 return pm4;
2807 }
2808
2809 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2810 {
2811 struct r600_context *rctx = (struct r600_context *)ctx;
2812 struct si_pm4_state *pm4;
2813
2814 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2815 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2816 si_pm4_set_state(rctx, vs_sampler, pm4);
2817 }
2818
2819 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2820 {
2821 struct r600_context *rctx = (struct r600_context *)ctx;
2822 struct si_pm4_state *pm4;
2823
2824 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2825 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2826 si_pm4_set_state(rctx, ps_sampler, pm4);
2827 }
2828
2829
2830 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2831 unsigned start, unsigned count,
2832 void **states)
2833 {
2834 assert(start == 0);
2835
2836 switch (shader) {
2837 case PIPE_SHADER_VERTEX:
2838 si_bind_vs_sampler_states(ctx, count, states);
2839 break;
2840 case PIPE_SHADER_FRAGMENT:
2841 si_bind_ps_sampler_states(ctx, count, states);
2842 break;
2843 default:
2844 ;
2845 }
2846 }
2847
2848
2849
2850 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2851 {
2852 struct r600_context *rctx = (struct r600_context *)ctx;
2853 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2854 uint16_t mask = sample_mask;
2855
2856 if (pm4 == NULL)
2857 return;
2858
2859 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2860 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2861
2862 si_pm4_set_state(rctx, sample_mask, pm4);
2863 }
2864
2865 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2866 {
2867 free(state);
2868 }
2869
2870 /*
2871 * Vertex elements & buffers
2872 */
2873
2874 static void *si_create_vertex_elements(struct pipe_context *ctx,
2875 unsigned count,
2876 const struct pipe_vertex_element *elements)
2877 {
2878 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2879 int i;
2880
2881 assert(count < PIPE_MAX_ATTRIBS);
2882 if (!v)
2883 return NULL;
2884
2885 v->count = count;
2886 for (i = 0; i < count; ++i) {
2887 const struct util_format_description *desc;
2888 unsigned data_format, num_format;
2889 int first_non_void;
2890
2891 desc = util_format_description(elements[i].src_format);
2892 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2893 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2894 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2895
2896 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2897 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2898 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2899 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2900 S_008F0C_NUM_FORMAT(num_format) |
2901 S_008F0C_DATA_FORMAT(data_format);
2902 }
2903 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2904
2905 return v;
2906 }
2907
2908 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2909 {
2910 struct r600_context *rctx = (struct r600_context *)ctx;
2911 struct si_vertex_element *v = (struct si_vertex_element*)state;
2912
2913 rctx->vertex_elements = v;
2914 }
2915
2916 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2917 {
2918 struct r600_context *rctx = (struct r600_context *)ctx;
2919
2920 if (rctx->vertex_elements == state)
2921 rctx->vertex_elements = NULL;
2922 FREE(state);
2923 }
2924
2925 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2926 const struct pipe_vertex_buffer *buffers)
2927 {
2928 struct r600_context *rctx = (struct r600_context *)ctx;
2929
2930 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2931 }
2932
2933 static void si_set_index_buffer(struct pipe_context *ctx,
2934 const struct pipe_index_buffer *ib)
2935 {
2936 struct r600_context *rctx = (struct r600_context *)ctx;
2937
2938 if (ib) {
2939 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2940 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2941 } else {
2942 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2943 }
2944 }
2945
2946 /*
2947 * Misc
2948 */
2949 static void si_set_polygon_stipple(struct pipe_context *ctx,
2950 const struct pipe_poly_stipple *state)
2951 {
2952 }
2953
2954 static void si_texture_barrier(struct pipe_context *ctx)
2955 {
2956 struct r600_context *rctx = (struct r600_context *)ctx;
2957
2958 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2959 R600_CONTEXT_FLUSH_AND_INV_CB;
2960 }
2961
2962 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2963 {
2964 struct pipe_blend_state blend;
2965
2966 memset(&blend, 0, sizeof(blend));
2967 blend.independent_blend_enable = true;
2968 blend.rt[0].colormask = 0xf;
2969 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2970 }
2971
2972 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2973 struct pipe_resource *texture,
2974 const struct pipe_surface *surf_tmpl)
2975 {
2976 struct r600_texture *rtex = (struct r600_texture*)texture;
2977 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2978 unsigned level = surf_tmpl->u.tex.level;
2979
2980 if (surface == NULL)
2981 return NULL;
2982
2983 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2984 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2985 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
2986
2987 pipe_reference_init(&surface->base.reference, 1);
2988 pipe_resource_reference(&surface->base.texture, texture);
2989 surface->base.context = pipe;
2990 surface->base.format = surf_tmpl->format;
2991 surface->base.width = rtex->surface.level[level].npix_x;
2992 surface->base.height = rtex->surface.level[level].npix_y;
2993 surface->base.texture = texture;
2994 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
2995 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
2996 surface->base.u.tex.level = level;
2997
2998 return &surface->base;
2999 }
3000
3001 static void r600_surface_destroy(struct pipe_context *pipe,
3002 struct pipe_surface *surface)
3003 {
3004 pipe_resource_reference(&surface->texture, NULL);
3005 FREE(surface);
3006 }
3007
3008 static boolean si_dma_copy(struct pipe_context *ctx,
3009 struct pipe_resource *dst,
3010 unsigned dst_level,
3011 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3012 struct pipe_resource *src,
3013 unsigned src_level,
3014 const struct pipe_box *src_box)
3015 {
3016 /* XXX implement this or share evergreen_dma_blit with r600g */
3017 return FALSE;
3018 }
3019
3020 void si_init_state_functions(struct r600_context *rctx)
3021 {
3022 int i;
3023
3024 rctx->b.b.create_blend_state = si_create_blend_state;
3025 rctx->b.b.bind_blend_state = si_bind_blend_state;
3026 rctx->b.b.delete_blend_state = si_delete_blend_state;
3027 rctx->b.b.set_blend_color = si_set_blend_color;
3028
3029 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3030 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3031 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3032
3033 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3034 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3035 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3036
3037 for (i = 0; i < 8; i++) {
3038 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3039 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3040 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3041 }
3042 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3043 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3044 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3045
3046 rctx->b.b.set_clip_state = si_set_clip_state;
3047 rctx->b.b.set_scissor_states = si_set_scissor_states;
3048 rctx->b.b.set_viewport_states = si_set_viewport_states;
3049 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3050
3051 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3052 rctx->b.b.get_sample_position = si_get_sample_position;
3053
3054 rctx->b.b.create_vs_state = si_create_vs_state;
3055 rctx->b.b.create_fs_state = si_create_fs_state;
3056 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3057 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3058 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3059 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3060
3061 rctx->b.b.create_sampler_state = si_create_sampler_state;
3062 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3063 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3064
3065 rctx->b.b.create_sampler_view = si_create_sampler_view;
3066 rctx->b.b.set_sampler_views = si_set_sampler_views;
3067 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3068
3069 rctx->b.b.set_sample_mask = si_set_sample_mask;
3070
3071 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3072 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3073 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3074 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3075 rctx->b.b.set_index_buffer = si_set_index_buffer;
3076
3077 rctx->b.b.texture_barrier = si_texture_barrier;
3078 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3079 rctx->b.b.create_surface = r600_create_surface;
3080 rctx->b.b.surface_destroy = r600_surface_destroy;
3081 rctx->b.dma_copy = si_dma_copy;
3082
3083 rctx->b.b.draw_vbo = si_draw_vbo;
3084 }
3085
3086 void si_init_config(struct r600_context *rctx)
3087 {
3088 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3089
3090 if (pm4 == NULL)
3091 return;
3092
3093 si_cmd_context_control(pm4);
3094
3095 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3096
3097 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3098 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3099 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3100 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3101 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3102 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3103 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3104 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3105 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3106 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3107 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3108 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3109 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3110 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3111 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3112 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3113 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3114 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3115 if (rctx->b.chip_class == SI) {
3116 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3117 S_028AA8_SWITCH_ON_EOP(1) |
3118 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3119 S_028AA8_PRIMGROUP_SIZE(63));
3120 }
3121 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3122 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3123 if (rctx->b.chip_class < CIK)
3124 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3125 S_008A14_CLIP_VTX_REORDER_ENA(1));
3126
3127 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3128 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3129 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3130
3131 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3132
3133 if (rctx->b.chip_class >= CIK) {
3134 switch (rctx->screen->b.family) {
3135 case CHIP_BONAIRE:
3136 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3137 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3138 break;
3139 case CHIP_HAWAII:
3140 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3141 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3142 break;
3143 case CHIP_KAVERI:
3144 /* XXX todo */
3145 case CHIP_KABINI:
3146 /* XXX todo */
3147 default:
3148 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3149 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3150 break;
3151 }
3152 } else {
3153 switch (rctx->screen->b.family) {
3154 case CHIP_TAHITI:
3155 case CHIP_PITCAIRN:
3156 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3157 break;
3158 case CHIP_VERDE:
3159 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3160 break;
3161 case CHIP_OLAND:
3162 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3163 break;
3164 case CHIP_HAINAN:
3165 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3166 break;
3167 default:
3168 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3169 break;
3170 }
3171 }
3172
3173 si_pm4_set_state(rctx, init, pm4);
3174 }