2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
37 static unsigned si_map_swizzle(unsigned swizzle
)
41 return V_008F0C_SQ_SEL_Y
;
43 return V_008F0C_SQ_SEL_Z
;
45 return V_008F0C_SQ_SEL_W
;
47 return V_008F0C_SQ_SEL_0
;
49 return V_008F0C_SQ_SEL_1
;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X
;
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x
)
59 x
>= 4096 ? 0xffff : x
* 16;
63 * Inferred framebuffer and blender state.
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
68 static void si_emit_cb_render_state(struct si_context
*sctx
)
70 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
71 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
78 cb_target_mask
&= blend
->cb_target_mask
;
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
86 if (blend
&& blend
->dual_src_blend
&&
87 sctx
->ps_shader
.cso
&&
88 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
94 if (sctx
->screen
->dfsm_allowed
&&
95 sctx
->last_cb_target_mask
!= cb_target_mask
) {
96 sctx
->last_cb_target_mask
= cb_target_mask
;
98 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
99 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
102 unsigned initial_cdw
= cs
->current
.cdw
;
103 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
104 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
106 if (sctx
->chip_class
>= VI
) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
111 bool oc_disable
= (sctx
->chip_class
== VI
||
112 sctx
->chip_class
== GFX9
) &&
114 blend
->blend_enable_4bit
& cb_target_mask
&&
115 sctx
->framebuffer
.nr_samples
>= 2;
116 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
118 radeon_opt_set_context_reg(
119 sctx
, R_028424_CB_DCC_CONTROL
,
120 SI_TRACKED_CB_DCC_CONTROL
,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->has_dcc_constant_encode
));
127 /* RB+ register settings. */
128 if (sctx
->screen
->rbplus_allowed
) {
129 unsigned spi_shader_col_format
=
130 sctx
->ps_shader
.cso
?
131 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
132 unsigned sx_ps_downconvert
= 0;
133 unsigned sx_blend_opt_epsilon
= 0;
134 unsigned sx_blend_opt_control
= 0;
136 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
137 struct si_surface
*surf
=
138 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
139 unsigned format
, swap
, spi_format
, colormask
;
140 bool has_alpha
, has_rgb
;
145 format
= G_028C70_FORMAT(surf
->cb_color_info
);
146 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
147 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
148 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
150 /* Set if RGB and A are present. */
151 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
153 if (format
== V_028C70_COLOR_8
||
154 format
== V_028C70_COLOR_16
||
155 format
== V_028C70_COLOR_32
)
156 has_rgb
= !has_alpha
;
160 /* Check the colormask and export format. */
161 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
163 if (!(colormask
& PIPE_MASK_A
))
166 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
171 /* Disable value checking for disabled channels. */
173 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
175 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
177 /* Enable down-conversion for 32bpp and smaller formats. */
179 case V_028C70_COLOR_8
:
180 case V_028C70_COLOR_8_8
:
181 case V_028C70_COLOR_8_8_8_8
:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
184 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
185 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
186 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
187 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
191 case V_028C70_COLOR_5_6_5
:
192 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
193 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
194 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
198 case V_028C70_COLOR_1_5_5_5
:
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
200 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
201 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
205 case V_028C70_COLOR_4_4_4_4
:
206 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
207 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
208 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
212 case V_028C70_COLOR_32
:
213 if (swap
== V_028C70_SWAP_STD
&&
214 spi_format
== V_028714_SPI_SHADER_32_R
)
215 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
216 else if (swap
== V_028C70_SWAP_ALT_REV
&&
217 spi_format
== V_028714_SPI_SHADER_32_AR
)
218 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
221 case V_028C70_COLOR_16
:
222 case V_028C70_COLOR_16_16
:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
225 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
226 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
227 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
228 if (swap
== V_028C70_SWAP_STD
||
229 swap
== V_028C70_SWAP_STD_REV
)
230 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
232 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
236 case V_028C70_COLOR_10_11_11
:
237 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
238 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
239 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
243 case V_028C70_COLOR_2_10_10_10
:
244 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
246 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
254 SI_TRACKED_SX_PS_DOWNCONVERT
,
255 sx_ps_downconvert
, sx_blend_opt_epsilon
,
256 sx_blend_opt_control
);
258 if (initial_cdw
!= cs
->current
.cdw
)
259 sctx
->context_roll_counter
++;
266 static uint32_t si_translate_blend_function(int blend_func
)
268 switch (blend_func
) {
270 return V_028780_COMB_DST_PLUS_SRC
;
271 case PIPE_BLEND_SUBTRACT
:
272 return V_028780_COMB_SRC_MINUS_DST
;
273 case PIPE_BLEND_REVERSE_SUBTRACT
:
274 return V_028780_COMB_DST_MINUS_SRC
;
276 return V_028780_COMB_MIN_DST_SRC
;
278 return V_028780_COMB_MAX_DST_SRC
;
280 PRINT_ERR("Unknown blend function %d\n", blend_func
);
287 static uint32_t si_translate_blend_factor(int blend_fact
)
289 switch (blend_fact
) {
290 case PIPE_BLENDFACTOR_ONE
:
291 return V_028780_BLEND_ONE
;
292 case PIPE_BLENDFACTOR_SRC_COLOR
:
293 return V_028780_BLEND_SRC_COLOR
;
294 case PIPE_BLENDFACTOR_SRC_ALPHA
:
295 return V_028780_BLEND_SRC_ALPHA
;
296 case PIPE_BLENDFACTOR_DST_ALPHA
:
297 return V_028780_BLEND_DST_ALPHA
;
298 case PIPE_BLENDFACTOR_DST_COLOR
:
299 return V_028780_BLEND_DST_COLOR
;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
302 case PIPE_BLENDFACTOR_CONST_COLOR
:
303 return V_028780_BLEND_CONSTANT_COLOR
;
304 case PIPE_BLENDFACTOR_CONST_ALPHA
:
305 return V_028780_BLEND_CONSTANT_ALPHA
;
306 case PIPE_BLENDFACTOR_ZERO
:
307 return V_028780_BLEND_ZERO
;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
320 case PIPE_BLENDFACTOR_SRC1_COLOR
:
321 return V_028780_BLEND_SRC1_COLOR
;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
323 return V_028780_BLEND_SRC1_ALPHA
;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
325 return V_028780_BLEND_INV_SRC1_COLOR
;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
327 return V_028780_BLEND_INV_SRC1_ALPHA
;
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
336 static uint32_t si_translate_blend_opt_function(int blend_func
)
338 switch (blend_func
) {
340 return V_028760_OPT_COMB_ADD
;
341 case PIPE_BLEND_SUBTRACT
:
342 return V_028760_OPT_COMB_SUBTRACT
;
343 case PIPE_BLEND_REVERSE_SUBTRACT
:
344 return V_028760_OPT_COMB_REVSUBTRACT
;
346 return V_028760_OPT_COMB_MIN
;
348 return V_028760_OPT_COMB_MAX
;
350 return V_028760_OPT_COMB_BLEND_DISABLED
;
354 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
356 switch (blend_fact
) {
357 case PIPE_BLENDFACTOR_ZERO
:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
359 case PIPE_BLENDFACTOR_ONE
:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
361 case PIPE_BLENDFACTOR_SRC_COLOR
:
362 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
365 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
367 case PIPE_BLENDFACTOR_SRC_ALPHA
:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
372 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
379 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
380 struct si_state_blend
*blend
,
381 enum pipe_blend_func func
,
382 enum pipe_blendfactor src
,
383 enum pipe_blendfactor dst
,
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed
=
388 (1u << PIPE_BLENDFACTOR_ONE
) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
396 (1u << PIPE_BLENDFACTOR_ZERO
) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
404 if (dst
== PIPE_BLENDFACTOR_ONE
&&
405 (src_allowed
& (1u << src
))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
415 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
416 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
417 blend
->commutative_4bit
|= chanmask
;
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
425 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
426 unsigned *dst_factor
, unsigned expected_dst
,
427 unsigned replacement_src
)
429 if (*src_factor
== expected_dst
&&
430 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
431 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
432 *dst_factor
= replacement_src
;
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func
== PIPE_BLEND_SUBTRACT
)
436 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
437 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
438 *func
= PIPE_BLEND_SUBTRACT
;
442 static bool si_blend_factor_uses_dst(unsigned factor
)
444 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
445 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
446 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
447 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
448 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
451 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
452 const struct pipe_blend_state
*state
,
455 struct si_context
*sctx
= (struct si_context
*)ctx
;
456 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
457 struct si_pm4_state
*pm4
= &blend
->pm4
;
458 uint32_t sx_mrt_blend_opt
[8] = {0};
459 uint32_t color_control
= 0;
464 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
465 blend
->alpha_to_one
= state
->alpha_to_one
;
466 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
467 blend
->logicop_enable
= state
->logicop_enable
;
469 if (state
->logicop_enable
) {
470 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
472 color_control
|= S_028808_ROP3(0xcc);
475 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
481 S_028B70_OFFSET_ROUND(1));
483 if (state
->alpha_to_coverage
)
484 blend
->need_src_alpha_4bit
|= 0xf;
486 blend
->cb_target_mask
= 0;
487 blend
->cb_target_enabled_4bit
= 0;
489 for (int i
= 0; i
< 8; i
++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j
= state
->independent_blend_enable
? i
: 0;
493 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
494 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
495 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
496 unsigned eqA
= state
->rt
[j
].alpha_func
;
497 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
498 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
500 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
501 unsigned blend_cntl
= 0;
503 sx_mrt_blend_opt
[i
] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i
>= 1 && blend
->dual_src_blend
) {
509 /* Vulkan does this for dual source blending. */
511 blend_cntl
|= S_028780_ENABLE(1);
513 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
520 if (blend
->dual_src_blend
&&
521 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
522 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
528 /* cb_render_state will disable unused ones */
529 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
530 if (state
->rt
[j
].colormask
)
531 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
533 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
534 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
538 si_blend_check_commutativity(sctx
->screen
, blend
,
539 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
540 si_blend_check_commutativity(sctx
->screen
, blend
,
541 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
549 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
550 PIPE_BLENDFACTOR_DST_COLOR
,
551 PIPE_BLENDFACTOR_SRC_COLOR
);
552 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
553 PIPE_BLENDFACTOR_DST_COLOR
,
554 PIPE_BLENDFACTOR_SRC_COLOR
);
555 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
556 PIPE_BLENDFACTOR_DST_ALPHA
,
557 PIPE_BLENDFACTOR_SRC_ALPHA
);
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
561 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
562 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
563 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB
))
567 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
568 if (si_blend_factor_uses_dst(srcA
))
569 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
571 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
572 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
573 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
574 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
575 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
577 /* Set the final value. */
578 sx_mrt_blend_opt
[i
] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
583 S_028760_ALPHA_DST_OPT(dstA_opt
) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
586 /* Set blend state. */
587 blend_cntl
|= S_028780_ENABLE(1);
588 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
589 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
590 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
592 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
593 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
595 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
596 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
598 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
600 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
602 /* This is only important for formats without alpha. */
603 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
604 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
605 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
606 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
607 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
608 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
609 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
612 if (blend
->cb_target_mask
) {
613 color_control
|= S_028808_MODE(mode
);
615 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
618 if (sctx
->screen
->rbplus_allowed
) {
619 /* Disable RB+ blend optimizations for dual source blending.
622 if (blend
->dual_src_blend
) {
623 for (int i
= 0; i
< 8; i
++) {
624 sx_mrt_blend_opt
[i
] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
630 for (int i
= 0; i
< 8; i
++)
631 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
632 sx_mrt_blend_opt
[i
]);
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend
->dual_src_blend
|| state
->logicop_enable
||
636 mode
== V_028808_CB_RESOLVE
)
637 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
640 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
644 static void *si_create_blend_state(struct pipe_context
*ctx
,
645 const struct pipe_blend_state
*state
)
647 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
650 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
652 struct si_context
*sctx
= (struct si_context
*)ctx
;
653 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
654 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
659 si_pm4_bind_state(sctx
, blend
, state
);
662 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
663 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
664 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
665 sctx
->framebuffer
.nr_samples
>= 2 &&
666 sctx
->screen
->dcc_msaa_allowed
))
667 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
670 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
671 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
672 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
673 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
674 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
675 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
676 sctx
->do_update_shaders
= true;
678 if (sctx
->screen
->dpbb_allowed
&&
680 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
681 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
682 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
683 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
685 if (sctx
->screen
->has_out_of_order_rast
&&
687 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
688 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
689 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
690 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
691 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
694 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
696 struct si_context
*sctx
= (struct si_context
*)ctx
;
697 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
700 static void si_set_blend_color(struct pipe_context
*ctx
,
701 const struct pipe_blend_color
*state
)
703 struct si_context
*sctx
= (struct si_context
*)ctx
;
704 static const struct pipe_blend_color zeros
;
706 sctx
->blend_color
.state
= *state
;
707 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
708 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
711 static void si_emit_blend_color(struct si_context
*sctx
)
713 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
715 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
716 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
723 static void si_set_clip_state(struct pipe_context
*ctx
,
724 const struct pipe_clip_state
*state
)
726 struct si_context
*sctx
= (struct si_context
*)ctx
;
727 struct pipe_constant_buffer cb
;
728 static const struct pipe_clip_state zeros
;
730 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
733 sctx
->clip_state
.state
= *state
;
734 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
735 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
738 cb
.user_buffer
= state
->ucp
;
739 cb
.buffer_offset
= 0;
740 cb
.buffer_size
= 4*4*8;
741 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
742 pipe_resource_reference(&cb
.buffer
, NULL
);
745 static void si_emit_clip_state(struct si_context
*sctx
)
747 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
749 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
750 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
753 static void si_emit_clip_regs(struct si_context
*sctx
)
755 struct si_shader
*vs
= si_get_vs_state(sctx
);
756 struct si_shader_selector
*vs_sel
= vs
->selector
;
757 struct tgsi_shader_info
*info
= &vs_sel
->info
;
758 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
759 unsigned window_space
=
760 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
761 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
762 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
763 unsigned culldist_mask
= vs_sel
->culldist_mask
;
766 if (vs
->key
.opt
.clip_disable
) {
767 assert(!info
->culldist_writemask
);
771 total_mask
= clipdist_mask
| culldist_mask
;
773 /* Clip distances on points have no effect, so need to be implemented
774 * as cull distances. This applies for the clipvertex case as well.
776 * Setting this for primitives other than points should have no adverse
779 clipdist_mask
&= rs
->clip_plane_enable
;
780 culldist_mask
|= clipdist_mask
;
782 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
783 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
784 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
785 vs_sel
->pa_cl_vs_out_cntl
|
786 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
787 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
788 clipdist_mask
| (culldist_mask
<< 8));
789 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
790 SI_TRACKED_PA_CL_CLIP_CNTL
,
791 rs
->pa_cl_clip_cntl
|
793 S_028810_CLIP_DISABLE(window_space
));
795 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
796 sctx
->context_roll_counter
++;
800 * inferred state between framebuffer and rasterizer
802 static void si_update_poly_offset_state(struct si_context
*sctx
)
804 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
806 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
807 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
811 /* Use the user format, not db_render_format, so that the polygon
812 * offset behaves as expected by applications.
814 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
815 case PIPE_FORMAT_Z16_UNORM
:
816 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
818 default: /* 24-bit */
819 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
821 case PIPE_FORMAT_Z32_FLOAT
:
822 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
823 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
832 static uint32_t si_translate_fill(uint32_t func
)
835 case PIPE_POLYGON_MODE_FILL
:
836 return V_028814_X_DRAW_TRIANGLES
;
837 case PIPE_POLYGON_MODE_LINE
:
838 return V_028814_X_DRAW_LINES
;
839 case PIPE_POLYGON_MODE_POINT
:
840 return V_028814_X_DRAW_POINTS
;
843 return V_028814_X_DRAW_POINTS
;
847 static void *si_create_rs_state(struct pipe_context
*ctx
,
848 const struct pipe_rasterizer_state
*state
)
850 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
851 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
852 struct si_pm4_state
*pm4
= &rs
->pm4
;
854 float psize_min
, psize_max
;
860 rs
->scissor_enable
= state
->scissor
;
861 rs
->clip_halfz
= state
->clip_halfz
;
862 rs
->two_side
= state
->light_twoside
;
863 rs
->multisample_enable
= state
->multisample
;
864 rs
->force_persample_interp
= state
->force_persample_interp
;
865 rs
->clip_plane_enable
= state
->clip_plane_enable
;
866 rs
->half_pixel_center
= state
->half_pixel_center
;
867 rs
->line_stipple_enable
= state
->line_stipple_enable
;
868 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
869 rs
->line_smooth
= state
->line_smooth
;
870 rs
->line_width
= state
->line_width
;
871 rs
->poly_smooth
= state
->poly_smooth
;
872 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
874 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
875 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
876 rs
->flatshade
= state
->flatshade
;
877 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
878 rs
->rasterizer_discard
= state
->rasterizer_discard
;
879 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
880 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
881 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
882 rs
->pa_cl_clip_cntl
=
883 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
884 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
885 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
886 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
887 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
889 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
890 S_0286D4_FLAT_SHADE_ENA(1) |
891 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
892 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
893 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
894 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
895 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
896 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
898 /* point size 12.4 fixed point */
899 tmp
= (unsigned)(state
->point_size
* 8.0);
900 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
902 if (state
->point_size_per_vertex
) {
903 psize_min
= util_get_min_point_size(state
);
904 psize_max
= SI_MAX_POINT_SIZE
;
906 /* Force the point size to be as if the vertex output was disabled. */
907 psize_min
= state
->point_size
;
908 psize_max
= state
->point_size
;
910 rs
->max_point_size
= psize_max
;
912 /* Divide by two, because 0.5 = 1 pixel. */
913 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
914 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
915 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
917 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
918 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
919 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
920 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
921 S_028A48_MSAA_ENABLE(state
->multisample
||
922 state
->poly_smooth
||
923 state
->line_smooth
) |
924 S_028A48_VPORT_SCISSOR_ENABLE(1) |
925 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
927 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
928 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
929 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
930 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
931 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
932 S_028814_FACE(!state
->front_ccw
) |
933 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
934 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
935 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
936 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
937 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
938 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
939 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
941 if (!rs
->uses_poly_offset
)
944 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
945 if (!rs
->pm4_poly_offset
) {
950 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
951 for (i
= 0; i
< 3; i
++) {
952 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
953 float offset_units
= state
->offset_units
;
954 float offset_scale
= state
->offset_scale
* 16.0f
;
955 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
957 if (!state
->offset_units_unscaled
) {
959 case 0: /* 16-bit zbuffer */
960 offset_units
*= 4.0f
;
961 pa_su_poly_offset_db_fmt_cntl
=
962 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
964 case 1: /* 24-bit zbuffer */
965 offset_units
*= 2.0f
;
966 pa_su_poly_offset_db_fmt_cntl
=
967 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
969 case 2: /* 32-bit zbuffer */
970 offset_units
*= 1.0f
;
971 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
972 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
977 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
979 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
981 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
983 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
985 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
986 pa_su_poly_offset_db_fmt_cntl
);
992 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
994 struct si_context
*sctx
= (struct si_context
*)ctx
;
995 struct si_state_rasterizer
*old_rs
=
996 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
997 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1002 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1003 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1005 /* Update the small primitive filter workaround if necessary. */
1006 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1007 sctx
->framebuffer
.nr_samples
> 1)
1008 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1011 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1012 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1014 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1015 si_update_poly_offset_state(sctx
);
1018 old_rs
->scissor_enable
!= rs
->scissor_enable
) {
1019 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1020 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1024 old_rs
->line_width
!= rs
->line_width
||
1025 old_rs
->max_point_size
!= rs
->max_point_size
||
1026 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1027 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1030 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1031 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1032 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1036 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1037 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1038 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1040 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1041 rs
->line_stipple_enable
;
1044 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1045 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1046 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1047 old_rs
->flatshade
!= rs
->flatshade
||
1048 old_rs
->two_side
!= rs
->two_side
||
1049 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1050 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1051 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1052 old_rs
->line_smooth
!= rs
->line_smooth
||
1053 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1054 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1055 sctx
->do_update_shaders
= true;
1058 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1060 struct si_context
*sctx
= (struct si_context
*)ctx
;
1061 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1063 if (sctx
->queued
.named
.rasterizer
== state
)
1064 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1066 FREE(rs
->pm4_poly_offset
);
1067 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1071 * infeered state between dsa and stencil ref
1073 static void si_emit_stencil_ref(struct si_context
*sctx
)
1075 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1076 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1077 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1079 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1080 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1081 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1082 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1083 S_028430_STENCILOPVAL(1));
1084 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1085 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1086 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1087 S_028434_STENCILOPVAL_BF(1));
1090 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1091 const struct pipe_stencil_ref
*state
)
1093 struct si_context
*sctx
= (struct si_context
*)ctx
;
1095 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1098 sctx
->stencil_ref
.state
= *state
;
1099 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1107 static uint32_t si_translate_stencil_op(int s_op
)
1110 case PIPE_STENCIL_OP_KEEP
:
1111 return V_02842C_STENCIL_KEEP
;
1112 case PIPE_STENCIL_OP_ZERO
:
1113 return V_02842C_STENCIL_ZERO
;
1114 case PIPE_STENCIL_OP_REPLACE
:
1115 return V_02842C_STENCIL_REPLACE_TEST
;
1116 case PIPE_STENCIL_OP_INCR
:
1117 return V_02842C_STENCIL_ADD_CLAMP
;
1118 case PIPE_STENCIL_OP_DECR
:
1119 return V_02842C_STENCIL_SUB_CLAMP
;
1120 case PIPE_STENCIL_OP_INCR_WRAP
:
1121 return V_02842C_STENCIL_ADD_WRAP
;
1122 case PIPE_STENCIL_OP_DECR_WRAP
:
1123 return V_02842C_STENCIL_SUB_WRAP
;
1124 case PIPE_STENCIL_OP_INVERT
:
1125 return V_02842C_STENCIL_INVERT
;
1127 PRINT_ERR("Unknown stencil op %d", s_op
);
1134 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1136 return s
->enabled
&& s
->writemask
&&
1137 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1138 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1139 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1142 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1144 /* REPLACE is normally order invariant, except when the stencil
1145 * reference value is written by the fragment shader. Tracking this
1146 * interaction does not seem worth the effort, so be conservative. */
1147 return op
!= PIPE_STENCIL_OP_INCR
&&
1148 op
!= PIPE_STENCIL_OP_DECR
&&
1149 op
!= PIPE_STENCIL_OP_REPLACE
;
1152 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1153 * invariant in the sense that the set of passing fragments as well as the
1154 * final stencil buffer result does not depend on the order of fragments. */
1155 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1157 return !state
->enabled
|| !state
->writemask
||
1158 /* The following assumes that Z writes are disabled. */
1159 (state
->func
== PIPE_FUNC_ALWAYS
&&
1160 si_order_invariant_stencil_op(state
->zpass_op
) &&
1161 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1162 (state
->func
== PIPE_FUNC_NEVER
&&
1163 si_order_invariant_stencil_op(state
->fail_op
));
1166 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1167 const struct pipe_depth_stencil_alpha_state
*state
)
1169 struct si_context
*sctx
= (struct si_context
*)ctx
;
1170 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1171 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1172 unsigned db_depth_control
;
1173 uint32_t db_stencil_control
= 0;
1179 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1180 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1181 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1182 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1184 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1185 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1186 S_028800_ZFUNC(state
->depth
.func
) |
1187 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1190 if (state
->stencil
[0].enabled
) {
1191 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1192 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1193 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1194 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1195 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1197 if (state
->stencil
[1].enabled
) {
1198 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1199 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1200 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1201 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1202 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1207 if (state
->alpha
.enabled
) {
1208 dsa
->alpha_func
= state
->alpha
.func
;
1210 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1211 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1213 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1216 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1217 if (state
->stencil
[0].enabled
)
1218 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1219 if (state
->depth
.bounds_test
) {
1220 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1221 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1224 dsa
->depth_enabled
= state
->depth
.enabled
;
1225 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1226 state
->depth
.writemask
;
1227 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1228 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1229 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1230 si_dsa_writes_stencil(&state
->stencil
[1]));
1231 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1232 dsa
->stencil_write_enabled
;
1234 bool zfunc_is_ordered
=
1235 state
->depth
.func
== PIPE_FUNC_NEVER
||
1236 state
->depth
.func
== PIPE_FUNC_LESS
||
1237 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1238 state
->depth
.func
== PIPE_FUNC_GREATER
||
1239 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1241 bool nozwrite_and_order_invariant_stencil
=
1242 !dsa
->db_can_write
||
1243 (!dsa
->depth_write_enabled
&&
1244 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1245 si_order_invariant_stencil_state(&state
->stencil
[1]));
1247 dsa
->order_invariance
[1].zs
=
1248 nozwrite_and_order_invariant_stencil
||
1249 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1250 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1252 dsa
->order_invariance
[1].pass_set
=
1253 nozwrite_and_order_invariant_stencil
||
1254 (!dsa
->stencil_write_enabled
&&
1255 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1256 state
->depth
.func
== PIPE_FUNC_NEVER
));
1257 dsa
->order_invariance
[0].pass_set
=
1258 !dsa
->depth_write_enabled
||
1259 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1260 state
->depth
.func
== PIPE_FUNC_NEVER
);
1262 dsa
->order_invariance
[1].pass_last
=
1263 sctx
->screen
->assume_no_z_fights
&&
1264 !dsa
->stencil_write_enabled
&&
1265 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1266 dsa
->order_invariance
[0].pass_last
=
1267 sctx
->screen
->assume_no_z_fights
&&
1268 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1273 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1275 struct si_context
*sctx
= (struct si_context
*)ctx
;
1276 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1277 struct si_state_dsa
*dsa
= state
;
1282 si_pm4_bind_state(sctx
, dsa
, dsa
);
1284 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1285 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1286 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1287 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1290 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1291 sctx
->do_update_shaders
= true;
1293 if (sctx
->screen
->dpbb_allowed
&&
1295 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1296 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1297 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1298 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1300 if (sctx
->screen
->has_out_of_order_rast
&&
1302 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1303 sizeof(old_dsa
->order_invariance
))))
1304 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1307 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1309 struct si_context
*sctx
= (struct si_context
*)ctx
;
1310 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1313 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1315 struct pipe_depth_stencil_alpha_state dsa
= {};
1317 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1320 /* DB RENDER STATE */
1322 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1324 struct si_context
*sctx
= (struct si_context
*)ctx
;
1326 /* Pipeline stat & streamout queries. */
1328 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1329 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1331 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1332 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1335 /* Occlusion queries. */
1336 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1337 sctx
->occlusion_queries_disabled
= !enable
;
1338 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1342 void si_set_occlusion_query_state(struct si_context
*sctx
,
1343 bool old_perfect_enable
)
1345 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1347 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1349 if (perfect_enable
!= old_perfect_enable
)
1350 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1353 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1355 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1357 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1358 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1361 static void si_emit_db_render_state(struct si_context
*sctx
)
1363 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1364 unsigned db_shader_control
, db_render_control
, db_count_control
;
1365 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1367 /* DB_RENDER_CONTROL */
1368 if (sctx
->dbcb_depth_copy_enabled
||
1369 sctx
->dbcb_stencil_copy_enabled
) {
1371 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1372 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1373 S_028000_COPY_CENTROID(1) |
1374 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1375 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1377 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1378 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1381 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1382 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1385 /* DB_COUNT_CONTROL (occlusion queries) */
1386 if (sctx
->num_occlusion_queries
> 0 &&
1387 !sctx
->occlusion_queries_disabled
) {
1388 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1390 if (sctx
->chip_class
>= CIK
) {
1391 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1393 /* Stoney doesn't increment occlusion query counters
1394 * if the sample rate is 16x. Use 8x sample rate instead.
1396 if (sctx
->family
== CHIP_STONEY
)
1397 log_sample_rate
= MIN2(log_sample_rate
, 3);
1400 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1401 S_028004_SAMPLE_RATE(log_sample_rate
) |
1402 S_028004_ZPASS_ENABLE(1) |
1403 S_028004_SLICE_EVEN_ENABLE(1) |
1404 S_028004_SLICE_ODD_ENABLE(1);
1407 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1408 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1411 /* Disable occlusion queries. */
1412 if (sctx
->chip_class
>= CIK
) {
1413 db_count_control
= 0;
1415 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1419 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1420 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1423 /* DB_RENDER_OVERRIDE2 */
1424 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1425 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1426 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1427 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1428 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1430 db_shader_control
= sctx
->ps_db_shader_control
;
1432 /* Bug workaround for smoothing (overrasterization) on SI. */
1433 if (sctx
->chip_class
== SI
&& sctx
->smoothing_enabled
) {
1434 db_shader_control
&= C_02880C_Z_ORDER
;
1435 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1438 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1439 if (!rs
->multisample_enable
)
1440 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1442 if (sctx
->screen
->has_rbplus
&&
1443 !sctx
->screen
->rbplus_allowed
)
1444 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1446 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1447 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1449 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1450 sctx
->context_roll_counter
++;
1454 * format translation
1456 static uint32_t si_translate_colorformat(enum pipe_format format
)
1458 const struct util_format_description
*desc
= util_format_description(format
);
1460 return V_028C70_COLOR_INVALID
;
1462 #define HAS_SIZE(x,y,z,w) \
1463 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1464 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1466 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1467 return V_028C70_COLOR_10_11_11
;
1469 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1470 return V_028C70_COLOR_INVALID
;
1472 /* hw cannot support mixed formats (except depth/stencil, since
1473 * stencil is not written to). */
1474 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1475 return V_028C70_COLOR_INVALID
;
1477 switch (desc
->nr_channels
) {
1479 switch (desc
->channel
[0].size
) {
1481 return V_028C70_COLOR_8
;
1483 return V_028C70_COLOR_16
;
1485 return V_028C70_COLOR_32
;
1489 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1490 switch (desc
->channel
[0].size
) {
1492 return V_028C70_COLOR_8_8
;
1494 return V_028C70_COLOR_16_16
;
1496 return V_028C70_COLOR_32_32
;
1498 } else if (HAS_SIZE(8,24,0,0)) {
1499 return V_028C70_COLOR_24_8
;
1500 } else if (HAS_SIZE(24,8,0,0)) {
1501 return V_028C70_COLOR_8_24
;
1505 if (HAS_SIZE(5,6,5,0)) {
1506 return V_028C70_COLOR_5_6_5
;
1507 } else if (HAS_SIZE(32,8,24,0)) {
1508 return V_028C70_COLOR_X24_8_32_FLOAT
;
1512 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1513 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1514 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1515 switch (desc
->channel
[0].size
) {
1517 return V_028C70_COLOR_4_4_4_4
;
1519 return V_028C70_COLOR_8_8_8_8
;
1521 return V_028C70_COLOR_16_16_16_16
;
1523 return V_028C70_COLOR_32_32_32_32
;
1525 } else if (HAS_SIZE(5,5,5,1)) {
1526 return V_028C70_COLOR_1_5_5_5
;
1527 } else if (HAS_SIZE(1,5,5,5)) {
1528 return V_028C70_COLOR_5_5_5_1
;
1529 } else if (HAS_SIZE(10,10,10,2)) {
1530 return V_028C70_COLOR_2_10_10_10
;
1534 return V_028C70_COLOR_INVALID
;
1537 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1539 if (SI_BIG_ENDIAN
) {
1540 switch(colorformat
) {
1541 /* 8-bit buffers. */
1542 case V_028C70_COLOR_8
:
1543 return V_028C70_ENDIAN_NONE
;
1545 /* 16-bit buffers. */
1546 case V_028C70_COLOR_5_6_5
:
1547 case V_028C70_COLOR_1_5_5_5
:
1548 case V_028C70_COLOR_4_4_4_4
:
1549 case V_028C70_COLOR_16
:
1550 case V_028C70_COLOR_8_8
:
1551 return V_028C70_ENDIAN_8IN16
;
1553 /* 32-bit buffers. */
1554 case V_028C70_COLOR_8_8_8_8
:
1555 case V_028C70_COLOR_2_10_10_10
:
1556 case V_028C70_COLOR_8_24
:
1557 case V_028C70_COLOR_24_8
:
1558 case V_028C70_COLOR_16_16
:
1559 return V_028C70_ENDIAN_8IN32
;
1561 /* 64-bit buffers. */
1562 case V_028C70_COLOR_16_16_16_16
:
1563 return V_028C70_ENDIAN_8IN16
;
1565 case V_028C70_COLOR_32_32
:
1566 return V_028C70_ENDIAN_8IN32
;
1568 /* 128-bit buffers. */
1569 case V_028C70_COLOR_32_32_32_32
:
1570 return V_028C70_ENDIAN_8IN32
;
1572 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1575 return V_028C70_ENDIAN_NONE
;
1579 static uint32_t si_translate_dbformat(enum pipe_format format
)
1582 case PIPE_FORMAT_Z16_UNORM
:
1583 return V_028040_Z_16
;
1584 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1585 case PIPE_FORMAT_X8Z24_UNORM
:
1586 case PIPE_FORMAT_Z24X8_UNORM
:
1587 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1588 return V_028040_Z_24
; /* deprecated on SI */
1589 case PIPE_FORMAT_Z32_FLOAT
:
1590 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1591 return V_028040_Z_32_FLOAT
;
1593 return V_028040_Z_INVALID
;
1598 * Texture translation
1601 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1602 enum pipe_format format
,
1603 const struct util_format_description
*desc
,
1606 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1607 bool uniform
= true;
1610 /* Colorspace (return non-RGB formats directly). */
1611 switch (desc
->colorspace
) {
1612 /* Depth stencil formats */
1613 case UTIL_FORMAT_COLORSPACE_ZS
:
1615 case PIPE_FORMAT_Z16_UNORM
:
1616 return V_008F14_IMG_DATA_FORMAT_16
;
1617 case PIPE_FORMAT_X24S8_UINT
:
1618 case PIPE_FORMAT_S8X24_UINT
:
1620 * Implemented as an 8_8_8_8 data format to fix texture
1621 * gathers in stencil sampling. This affects at least
1622 * GL45-CTS.texture_cube_map_array.sampling on VI.
1624 if (sscreen
->info
.chip_class
<= VI
)
1625 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1627 if (format
== PIPE_FORMAT_X24S8_UINT
)
1628 return V_008F14_IMG_DATA_FORMAT_8_24
;
1630 return V_008F14_IMG_DATA_FORMAT_24_8
;
1631 case PIPE_FORMAT_Z24X8_UNORM
:
1632 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1633 return V_008F14_IMG_DATA_FORMAT_8_24
;
1634 case PIPE_FORMAT_X8Z24_UNORM
:
1635 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1636 return V_008F14_IMG_DATA_FORMAT_24_8
;
1637 case PIPE_FORMAT_S8_UINT
:
1638 return V_008F14_IMG_DATA_FORMAT_8
;
1639 case PIPE_FORMAT_Z32_FLOAT
:
1640 return V_008F14_IMG_DATA_FORMAT_32
;
1641 case PIPE_FORMAT_X32_S8X24_UINT
:
1642 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1643 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1648 case UTIL_FORMAT_COLORSPACE_YUV
:
1649 goto out_unknown
; /* TODO */
1651 case UTIL_FORMAT_COLORSPACE_SRGB
:
1652 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1660 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1661 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1665 case PIPE_FORMAT_RGTC1_SNORM
:
1666 case PIPE_FORMAT_LATC1_SNORM
:
1667 case PIPE_FORMAT_RGTC1_UNORM
:
1668 case PIPE_FORMAT_LATC1_UNORM
:
1669 return V_008F14_IMG_DATA_FORMAT_BC4
;
1670 case PIPE_FORMAT_RGTC2_SNORM
:
1671 case PIPE_FORMAT_LATC2_SNORM
:
1672 case PIPE_FORMAT_RGTC2_UNORM
:
1673 case PIPE_FORMAT_LATC2_UNORM
:
1674 return V_008F14_IMG_DATA_FORMAT_BC5
;
1680 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1681 (sscreen
->info
.family
== CHIP_STONEY
||
1682 sscreen
->info
.family
== CHIP_VEGA10
||
1683 sscreen
->info
.family
== CHIP_RAVEN
)) {
1685 case PIPE_FORMAT_ETC1_RGB8
:
1686 case PIPE_FORMAT_ETC2_RGB8
:
1687 case PIPE_FORMAT_ETC2_SRGB8
:
1688 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1689 case PIPE_FORMAT_ETC2_RGB8A1
:
1690 case PIPE_FORMAT_ETC2_SRGB8A1
:
1691 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1692 case PIPE_FORMAT_ETC2_RGBA8
:
1693 case PIPE_FORMAT_ETC2_SRGBA8
:
1694 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1695 case PIPE_FORMAT_ETC2_R11_UNORM
:
1696 case PIPE_FORMAT_ETC2_R11_SNORM
:
1697 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1698 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1699 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1700 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1706 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1707 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1711 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1712 case PIPE_FORMAT_BPTC_SRGBA
:
1713 return V_008F14_IMG_DATA_FORMAT_BC7
;
1714 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1715 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1716 return V_008F14_IMG_DATA_FORMAT_BC6
;
1722 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1724 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1725 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1726 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1727 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1728 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1729 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1735 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1736 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1740 case PIPE_FORMAT_DXT1_RGB
:
1741 case PIPE_FORMAT_DXT1_RGBA
:
1742 case PIPE_FORMAT_DXT1_SRGB
:
1743 case PIPE_FORMAT_DXT1_SRGBA
:
1744 return V_008F14_IMG_DATA_FORMAT_BC1
;
1745 case PIPE_FORMAT_DXT3_RGBA
:
1746 case PIPE_FORMAT_DXT3_SRGBA
:
1747 return V_008F14_IMG_DATA_FORMAT_BC2
;
1748 case PIPE_FORMAT_DXT5_RGBA
:
1749 case PIPE_FORMAT_DXT5_SRGBA
:
1750 return V_008F14_IMG_DATA_FORMAT_BC3
;
1756 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1757 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1758 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1759 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1762 /* R8G8Bx_SNORM - TODO CxV8U8 */
1764 /* hw cannot support mixed formats (except depth/stencil, since only
1766 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1769 /* See whether the components are of the same size. */
1770 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1771 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1774 /* Non-uniform formats. */
1776 switch(desc
->nr_channels
) {
1778 if (desc
->channel
[0].size
== 5 &&
1779 desc
->channel
[1].size
== 6 &&
1780 desc
->channel
[2].size
== 5) {
1781 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1785 if (desc
->channel
[0].size
== 5 &&
1786 desc
->channel
[1].size
== 5 &&
1787 desc
->channel
[2].size
== 5 &&
1788 desc
->channel
[3].size
== 1) {
1789 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1791 if (desc
->channel
[0].size
== 1 &&
1792 desc
->channel
[1].size
== 5 &&
1793 desc
->channel
[2].size
== 5 &&
1794 desc
->channel
[3].size
== 5) {
1795 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1797 if (desc
->channel
[0].size
== 10 &&
1798 desc
->channel
[1].size
== 10 &&
1799 desc
->channel
[2].size
== 10 &&
1800 desc
->channel
[3].size
== 2) {
1801 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1808 if (first_non_void
< 0 || first_non_void
> 3)
1811 /* uniform formats */
1812 switch (desc
->channel
[first_non_void
].size
) {
1814 switch (desc
->nr_channels
) {
1815 #if 0 /* Not supported for render targets */
1817 return V_008F14_IMG_DATA_FORMAT_4_4
;
1820 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1824 switch (desc
->nr_channels
) {
1826 return V_008F14_IMG_DATA_FORMAT_8
;
1828 return V_008F14_IMG_DATA_FORMAT_8_8
;
1830 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1834 switch (desc
->nr_channels
) {
1836 return V_008F14_IMG_DATA_FORMAT_16
;
1838 return V_008F14_IMG_DATA_FORMAT_16_16
;
1840 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1844 switch (desc
->nr_channels
) {
1846 return V_008F14_IMG_DATA_FORMAT_32
;
1848 return V_008F14_IMG_DATA_FORMAT_32_32
;
1849 #if 0 /* Not supported for render targets */
1851 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1854 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1862 static unsigned si_tex_wrap(unsigned wrap
)
1866 case PIPE_TEX_WRAP_REPEAT
:
1867 return V_008F30_SQ_TEX_WRAP
;
1868 case PIPE_TEX_WRAP_CLAMP
:
1869 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1870 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1871 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1872 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1873 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1874 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1875 return V_008F30_SQ_TEX_MIRROR
;
1876 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1877 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1878 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1879 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1880 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1881 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1885 static unsigned si_tex_mipfilter(unsigned filter
)
1888 case PIPE_TEX_MIPFILTER_NEAREST
:
1889 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1890 case PIPE_TEX_MIPFILTER_LINEAR
:
1891 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1893 case PIPE_TEX_MIPFILTER_NONE
:
1894 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1898 static unsigned si_tex_compare(unsigned compare
)
1902 case PIPE_FUNC_NEVER
:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1904 case PIPE_FUNC_LESS
:
1905 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1906 case PIPE_FUNC_EQUAL
:
1907 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1908 case PIPE_FUNC_LEQUAL
:
1909 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1910 case PIPE_FUNC_GREATER
:
1911 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1912 case PIPE_FUNC_NOTEQUAL
:
1913 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1914 case PIPE_FUNC_GEQUAL
:
1915 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1916 case PIPE_FUNC_ALWAYS
:
1917 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1921 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1922 unsigned view_target
, unsigned nr_samples
)
1924 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1926 if (view_target
== PIPE_TEXTURE_CUBE
||
1927 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1928 res_target
= view_target
;
1929 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1930 else if (res_target
== PIPE_TEXTURE_CUBE
||
1931 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1932 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1934 /* GFX9 allocates 1D textures as 2D. */
1935 if ((res_target
== PIPE_TEXTURE_1D
||
1936 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1937 sscreen
->info
.chip_class
>= GFX9
&&
1938 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1939 if (res_target
== PIPE_TEXTURE_1D
)
1940 res_target
= PIPE_TEXTURE_2D
;
1942 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1945 switch (res_target
) {
1947 case PIPE_TEXTURE_1D
:
1948 return V_008F1C_SQ_RSRC_IMG_1D
;
1949 case PIPE_TEXTURE_1D_ARRAY
:
1950 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1951 case PIPE_TEXTURE_2D
:
1952 case PIPE_TEXTURE_RECT
:
1953 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1954 V_008F1C_SQ_RSRC_IMG_2D
;
1955 case PIPE_TEXTURE_2D_ARRAY
:
1956 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1957 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1958 case PIPE_TEXTURE_3D
:
1959 return V_008F1C_SQ_RSRC_IMG_3D
;
1960 case PIPE_TEXTURE_CUBE
:
1961 case PIPE_TEXTURE_CUBE_ARRAY
:
1962 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1967 * Format support testing
1970 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1972 const struct util_format_description
*desc
= util_format_description(format
);
1976 return si_translate_texformat(screen
, format
, desc
,
1977 util_format_get_first_non_void_channel(format
)) != ~0U;
1980 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1981 const struct util_format_description
*desc
,
1986 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1987 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1989 assert(first_non_void
>= 0);
1991 if (desc
->nr_channels
== 4 &&
1992 desc
->channel
[0].size
== 10 &&
1993 desc
->channel
[1].size
== 10 &&
1994 desc
->channel
[2].size
== 10 &&
1995 desc
->channel
[3].size
== 2)
1996 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1998 /* See whether the components are of the same size. */
1999 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2000 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2001 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2004 switch (desc
->channel
[first_non_void
].size
) {
2006 switch (desc
->nr_channels
) {
2008 case 3: /* 3 loads */
2009 return V_008F0C_BUF_DATA_FORMAT_8
;
2011 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2013 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2017 switch (desc
->nr_channels
) {
2019 case 3: /* 3 loads */
2020 return V_008F0C_BUF_DATA_FORMAT_16
;
2022 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2024 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2028 switch (desc
->nr_channels
) {
2030 return V_008F0C_BUF_DATA_FORMAT_32
;
2032 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2034 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2036 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2040 /* Legacy double formats. */
2041 switch (desc
->nr_channels
) {
2042 case 1: /* 1 load */
2043 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2044 case 2: /* 1 load */
2045 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2046 case 3: /* 3 loads */
2047 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2048 case 4: /* 2 loads */
2049 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2054 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2057 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2058 const struct util_format_description
*desc
,
2061 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2062 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2064 assert(first_non_void
>= 0);
2066 switch (desc
->channel
[first_non_void
].type
) {
2067 case UTIL_FORMAT_TYPE_SIGNED
:
2068 case UTIL_FORMAT_TYPE_FIXED
:
2069 if (desc
->channel
[first_non_void
].size
>= 32 ||
2070 desc
->channel
[first_non_void
].pure_integer
)
2071 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2072 else if (desc
->channel
[first_non_void
].normalized
)
2073 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2075 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2077 case UTIL_FORMAT_TYPE_UNSIGNED
:
2078 if (desc
->channel
[first_non_void
].size
>= 32 ||
2079 desc
->channel
[first_non_void
].pure_integer
)
2080 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2081 else if (desc
->channel
[first_non_void
].normalized
)
2082 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2084 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2086 case UTIL_FORMAT_TYPE_FLOAT
:
2088 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2092 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2093 enum pipe_format format
,
2096 const struct util_format_description
*desc
;
2098 unsigned data_format
;
2100 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2101 PIPE_BIND_SAMPLER_VIEW
|
2102 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2104 desc
= util_format_description(format
);
2108 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2109 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2110 * for read-only access (with caveats surrounding bounds checks), but
2111 * obviously fails for write access which we have to implement for
2112 * shader images. Luckily, OpenGL doesn't expect this to be supported
2113 * anyway, and so the only impact is on PBO uploads / downloads, which
2114 * shouldn't be expected to be fast for GL_RGB anyway.
2116 if (desc
->block
.bits
== 3 * 8 ||
2117 desc
->block
.bits
== 3 * 16) {
2118 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2119 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2125 first_non_void
= util_format_get_first_non_void_channel(format
);
2126 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2127 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2133 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2135 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2136 si_translate_colorswap(format
, false) != ~0U;
2139 static bool si_is_zs_format_supported(enum pipe_format format
)
2141 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2144 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2145 enum pipe_format format
,
2146 enum pipe_texture_target target
,
2147 unsigned sample_count
,
2148 unsigned storage_sample_count
,
2151 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2152 unsigned retval
= 0;
2154 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2155 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2159 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2162 if (sample_count
> 1) {
2163 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2166 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2169 /* Only power-of-two sample counts are supported. */
2170 if (!util_is_power_of_two_or_zero(sample_count
) ||
2171 !util_is_power_of_two_or_zero(storage_sample_count
))
2174 /* MSAA support without framebuffer attachments. */
2175 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2178 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2179 util_format_is_depth_or_stencil(format
)) {
2180 /* Color without EQAA or depth/stencil. */
2181 if (sample_count
> 8 ||
2182 sample_count
!= storage_sample_count
)
2185 /* Color with EQAA. */
2186 if (sample_count
> 16 ||
2187 storage_sample_count
> 8)
2192 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2193 PIPE_BIND_SHADER_IMAGE
)) {
2194 if (target
== PIPE_BUFFER
) {
2195 retval
|= si_is_vertex_format_supported(
2196 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2197 PIPE_BIND_SHADER_IMAGE
));
2199 if (si_is_sampler_format_supported(screen
, format
))
2200 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2201 PIPE_BIND_SHADER_IMAGE
);
2205 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2206 PIPE_BIND_DISPLAY_TARGET
|
2209 PIPE_BIND_BLENDABLE
)) &&
2210 si_is_colorbuffer_format_supported(format
)) {
2212 (PIPE_BIND_RENDER_TARGET
|
2213 PIPE_BIND_DISPLAY_TARGET
|
2216 if (!util_format_is_pure_integer(format
) &&
2217 !util_format_is_depth_or_stencil(format
))
2218 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2221 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2222 si_is_zs_format_supported(format
)) {
2223 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2226 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2227 retval
|= si_is_vertex_format_supported(screen
, format
,
2228 PIPE_BIND_VERTEX_BUFFER
);
2231 if ((usage
& PIPE_BIND_LINEAR
) &&
2232 !util_format_is_compressed(format
) &&
2233 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2234 retval
|= PIPE_BIND_LINEAR
;
2236 return retval
== usage
;
2240 * framebuffer handling
2243 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2244 unsigned format
, unsigned swap
,
2245 unsigned ntype
, bool is_depth
)
2247 /* Alpha is needed for alpha-to-coverage.
2248 * Blending may be with or without alpha.
2250 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2251 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2252 unsigned blend
= 0; /* supports blending, but may not export alpha */
2253 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2255 /* Choose the SPI color formats. These are required values for RB+.
2256 * Other chips have multiple choices, though they are not necessarily better.
2259 case V_028C70_COLOR_5_6_5
:
2260 case V_028C70_COLOR_1_5_5_5
:
2261 case V_028C70_COLOR_5_5_5_1
:
2262 case V_028C70_COLOR_4_4_4_4
:
2263 case V_028C70_COLOR_10_11_11
:
2264 case V_028C70_COLOR_11_11_10
:
2265 case V_028C70_COLOR_8
:
2266 case V_028C70_COLOR_8_8
:
2267 case V_028C70_COLOR_8_8_8_8
:
2268 case V_028C70_COLOR_10_10_10_2
:
2269 case V_028C70_COLOR_2_10_10_10
:
2270 if (ntype
== V_028C70_NUMBER_UINT
)
2271 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2272 else if (ntype
== V_028C70_NUMBER_SINT
)
2273 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2275 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2278 case V_028C70_COLOR_16
:
2279 case V_028C70_COLOR_16_16
:
2280 case V_028C70_COLOR_16_16_16_16
:
2281 if (ntype
== V_028C70_NUMBER_UNORM
||
2282 ntype
== V_028C70_NUMBER_SNORM
) {
2283 /* UNORM16 and SNORM16 don't support blending */
2284 if (ntype
== V_028C70_NUMBER_UNORM
)
2285 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2287 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2289 /* Use 32 bits per channel for blending. */
2290 if (format
== V_028C70_COLOR_16
) {
2291 if (swap
== V_028C70_SWAP_STD
) { /* R */
2292 blend
= V_028714_SPI_SHADER_32_R
;
2293 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2294 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2295 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2298 } else if (format
== V_028C70_COLOR_16_16
) {
2299 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2300 blend
= V_028714_SPI_SHADER_32_GR
;
2301 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2302 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2303 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2306 } else /* 16_16_16_16 */
2307 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2308 } else if (ntype
== V_028C70_NUMBER_UINT
)
2309 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2310 else if (ntype
== V_028C70_NUMBER_SINT
)
2311 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2312 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2313 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2318 case V_028C70_COLOR_32
:
2319 if (swap
== V_028C70_SWAP_STD
) { /* R */
2320 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2321 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2322 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2323 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2328 case V_028C70_COLOR_32_32
:
2329 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2330 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2331 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2332 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2333 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2338 case V_028C70_COLOR_32_32_32_32
:
2339 case V_028C70_COLOR_8_24
:
2340 case V_028C70_COLOR_24_8
:
2341 case V_028C70_COLOR_X24_8_32_FLOAT
:
2342 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2350 /* The DB->CB copy needs 32_ABGR. */
2352 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2354 surf
->spi_shader_col_format
= normal
;
2355 surf
->spi_shader_col_format_alpha
= alpha
;
2356 surf
->spi_shader_col_format_blend
= blend
;
2357 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2360 static void si_initialize_color_surface(struct si_context
*sctx
,
2361 struct si_surface
*surf
)
2363 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2364 unsigned color_info
, color_attrib
;
2365 unsigned format
, swap
, ntype
, endian
;
2366 const struct util_format_description
*desc
;
2368 unsigned blend_clamp
= 0, blend_bypass
= 0;
2370 desc
= util_format_description(surf
->base
.format
);
2371 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2372 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2376 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2377 ntype
= V_028C70_NUMBER_FLOAT
;
2379 ntype
= V_028C70_NUMBER_UNORM
;
2380 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2381 ntype
= V_028C70_NUMBER_SRGB
;
2382 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2383 if (desc
->channel
[firstchan
].pure_integer
) {
2384 ntype
= V_028C70_NUMBER_SINT
;
2386 assert(desc
->channel
[firstchan
].normalized
);
2387 ntype
= V_028C70_NUMBER_SNORM
;
2389 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2390 if (desc
->channel
[firstchan
].pure_integer
) {
2391 ntype
= V_028C70_NUMBER_UINT
;
2393 assert(desc
->channel
[firstchan
].normalized
);
2394 ntype
= V_028C70_NUMBER_UNORM
;
2399 format
= si_translate_colorformat(surf
->base
.format
);
2400 if (format
== V_028C70_COLOR_INVALID
) {
2401 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2403 assert(format
!= V_028C70_COLOR_INVALID
);
2404 swap
= si_translate_colorswap(surf
->base
.format
, false);
2405 endian
= si_colorformat_endian_swap(format
);
2407 /* blend clamp should be set for all NORM/SRGB types */
2408 if (ntype
== V_028C70_NUMBER_UNORM
||
2409 ntype
== V_028C70_NUMBER_SNORM
||
2410 ntype
== V_028C70_NUMBER_SRGB
)
2413 /* set blend bypass according to docs if SINT/UINT or
2414 8/24 COLOR variants */
2415 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2416 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2417 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2422 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2423 if (format
== V_028C70_COLOR_8
||
2424 format
== V_028C70_COLOR_8_8
||
2425 format
== V_028C70_COLOR_8_8_8_8
)
2426 surf
->color_is_int8
= true;
2427 else if (format
== V_028C70_COLOR_10_10_10_2
||
2428 format
== V_028C70_COLOR_2_10_10_10
)
2429 surf
->color_is_int10
= true;
2432 color_info
= S_028C70_FORMAT(format
) |
2433 S_028C70_COMP_SWAP(swap
) |
2434 S_028C70_BLEND_CLAMP(blend_clamp
) |
2435 S_028C70_BLEND_BYPASS(blend_bypass
) |
2436 S_028C70_SIMPLE_FLOAT(1) |
2437 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2438 ntype
!= V_028C70_NUMBER_SNORM
&&
2439 ntype
!= V_028C70_NUMBER_SRGB
&&
2440 format
!= V_028C70_COLOR_8_24
&&
2441 format
!= V_028C70_COLOR_24_8
) |
2442 S_028C70_NUMBER_TYPE(ntype
) |
2443 S_028C70_ENDIAN(endian
);
2445 /* Intensity is implemented as Red, so treat it that way. */
2446 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2447 util_format_is_intensity(surf
->base
.format
));
2449 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2450 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2451 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2453 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2454 S_028C74_NUM_FRAGMENTS(log_fragments
);
2456 if (tex
->surface
.fmask_size
) {
2457 color_info
|= S_028C70_COMPRESSION(1);
2458 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2460 if (sctx
->chip_class
== SI
) {
2461 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2462 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2467 if (sctx
->chip_class
>= VI
) {
2468 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2469 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2471 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2472 64 for APU because all of our APUs to date use DIMMs which have
2473 a request granularity size of 64B while all other chips have a
2475 if (!sctx
->screen
->info
.has_dedicated_vram
)
2476 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2478 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2479 if (tex
->surface
.bpe
== 1)
2480 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2481 else if (tex
->surface
.bpe
== 2)
2482 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2485 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2486 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2487 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2490 /* This must be set for fast clear to work without FMASK. */
2491 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== SI
) {
2492 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2493 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2496 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2497 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2499 if (sctx
->chip_class
>= GFX9
) {
2500 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2502 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2503 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2504 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2505 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2506 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2507 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2510 surf
->cb_color_view
= color_view
;
2511 surf
->cb_color_info
= color_info
;
2512 surf
->cb_color_attrib
= color_attrib
;
2514 /* Determine pixel shader export format */
2515 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2517 surf
->color_initialized
= true;
2520 static void si_init_depth_surface(struct si_context
*sctx
,
2521 struct si_surface
*surf
)
2523 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2524 unsigned level
= surf
->base
.u
.tex
.level
;
2525 unsigned format
, stencil_format
;
2526 uint32_t z_info
, s_info
;
2528 format
= si_translate_dbformat(tex
->db_render_format
);
2529 stencil_format
= tex
->surface
.has_stencil
?
2530 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2532 assert(format
!= V_028040_Z_INVALID
);
2533 if (format
== V_028040_Z_INVALID
)
2534 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2536 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2537 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2538 surf
->db_htile_data_base
= 0;
2539 surf
->db_htile_surface
= 0;
2541 if (sctx
->chip_class
>= GFX9
) {
2542 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2543 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2544 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2545 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2546 z_info
= S_028038_FORMAT(format
) |
2547 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2548 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2549 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2550 s_info
= S_02803C_FORMAT(stencil_format
) |
2551 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2552 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2553 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2554 surf
->db_depth_view
|= S_028008_MIPID(level
);
2555 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2556 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2558 if (si_htile_enabled(tex
, level
)) {
2559 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2560 S_028038_ALLOW_EXPCLEAR(1);
2562 if (tex
->tc_compatible_htile
) {
2563 unsigned max_zplanes
= 4;
2565 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2566 tex
->buffer
.b
.b
.nr_samples
> 1)
2569 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2570 S_028038_ITERATE_FLUSH(1);
2571 s_info
|= S_02803C_ITERATE_FLUSH(1);
2574 if (tex
->surface
.has_stencil
) {
2575 /* Stencil buffer workaround ported from the SI-CI-VI code.
2576 * See that for explanation.
2578 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2580 /* Use all HTILE for depth if there's no stencil. */
2581 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2584 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2585 tex
->htile_offset
) >> 8;
2586 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2587 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2588 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2592 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2594 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2596 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2597 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2598 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2599 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2601 z_info
= S_028040_FORMAT(format
) |
2602 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2603 s_info
= S_028044_FORMAT(stencil_format
);
2604 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2606 if (sctx
->chip_class
>= CIK
) {
2607 struct radeon_info
*info
= &sctx
->screen
->info
;
2608 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2609 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2610 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2611 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2612 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2613 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2615 surf
->db_depth_info
|=
2616 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2617 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2618 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2619 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2620 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2621 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2622 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2623 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2625 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2626 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2627 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2628 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2631 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2632 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2633 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2634 levelinfo
->nblk_y
) / 64 - 1);
2636 if (si_htile_enabled(tex
, level
)) {
2637 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2638 S_028040_ALLOW_EXPCLEAR(1);
2640 if (tex
->surface
.has_stencil
) {
2641 /* Workaround: For a not yet understood reason, the
2642 * combination of MSAA, fast stencil clear and stencil
2643 * decompress messes with subsequent stencil buffer
2644 * uses. Problem was reproduced on Verde, Bonaire,
2645 * Tonga, and Carrizo.
2647 * Disabling EXPCLEAR works around the problem.
2649 * Check piglit's arb_texture_multisample-stencil-clear
2650 * test if you want to try changing this.
2652 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2653 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2654 } else if (!tex
->tc_compatible_htile
) {
2655 /* Use all of the htile_buffer for depth if there's no stencil.
2656 * This must not be set when TC-compatible HTILE is enabled
2659 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2662 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2663 tex
->htile_offset
) >> 8;
2664 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2666 if (tex
->tc_compatible_htile
) {
2667 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2669 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2670 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2671 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2672 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2673 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2675 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2680 surf
->db_z_info
= z_info
;
2681 surf
->db_stencil_info
= s_info
;
2683 surf
->depth_initialized
= true;
2686 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2688 if (sctx
->decompression_enabled
)
2691 if (sctx
->framebuffer
.state
.zsbuf
) {
2692 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2693 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2695 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2697 if (tex
->surface
.has_stencil
)
2698 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2701 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2702 while (compressed_cb_mask
) {
2703 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2704 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2705 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2707 if (tex
->surface
.fmask_size
)
2708 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2709 if (tex
->dcc_gather_statistics
)
2710 tex
->separate_dcc_dirty
= true;
2714 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2716 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2717 struct si_surface
*surf
= NULL
;
2718 struct si_texture
*tex
;
2720 if (!state
->cbufs
[i
])
2722 surf
= (struct si_surface
*)state
->cbufs
[i
];
2723 tex
= (struct si_texture
*)surf
->base
.texture
;
2725 p_atomic_dec(&tex
->framebuffers_bound
);
2729 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2730 const struct pipe_framebuffer_state
*state
)
2732 struct si_context
*sctx
= (struct si_context
*)ctx
;
2733 struct si_surface
*surf
= NULL
;
2734 struct si_texture
*tex
;
2735 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2736 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2737 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2738 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2739 bool old_has_stencil
=
2741 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2742 bool unbound
= false;
2745 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2746 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2747 * We could implement the full workaround here, but it's a useless case.
2749 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2750 unreachable("the framebuffer shouldn't have zero area");
2754 si_update_fb_dirtiness_after_rendering(sctx
);
2756 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2757 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2760 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2761 if (tex
->dcc_gather_statistics
)
2762 vi_separate_dcc_stop_query(sctx
, tex
);
2765 /* Disable DCC if the formats are incompatible. */
2766 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2767 if (!state
->cbufs
[i
])
2770 surf
= (struct si_surface
*)state
->cbufs
[i
];
2771 tex
= (struct si_texture
*)surf
->base
.texture
;
2773 if (!surf
->dcc_incompatible
)
2776 /* Since the DCC decompression calls back into set_framebuffer-
2777 * _state, we need to unbind the framebuffer, so that
2778 * vi_separate_dcc_stop_query isn't called twice with the same
2782 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2786 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2787 if (!si_texture_disable_dcc(sctx
, tex
))
2788 si_decompress_dcc(sctx
, tex
);
2790 surf
->dcc_incompatible
= false;
2793 /* Only flush TC when changing the framebuffer state, because
2794 * the only client not using TC that can change textures is
2797 * Wait for compute shaders because of possible transitions:
2798 * - FB write -> shader read
2799 * - shader write -> FB read
2801 * DB caches are flushed on demand (using si_decompress_textures).
2803 * When MSAA is enabled, CB and TC caches are flushed on demand
2804 * (after FMASK decompression). Shader write -> FB read transitions
2805 * cannot happen for MSAA textures, because MSAA shader images are
2808 * Only flush and wait for CB if there is actually a bound color buffer.
2810 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2811 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2812 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2813 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2816 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2818 /* u_blitter doesn't invoke depth decompression when it does multiple
2819 * blits in a row, but the only case when it matters for DB is when
2820 * doing generate_mipmap. So here we flush DB manually between
2821 * individual generate_mipmap blits.
2822 * Note that lower mipmap levels aren't compressed.
2824 if (sctx
->generate_mipmap_for_depth
) {
2825 si_make_DB_shader_coherent(sctx
, 1, false,
2826 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2827 } else if (sctx
->chip_class
== GFX9
) {
2828 /* It appears that DB metadata "leaks" in a sequence of:
2830 * - DCC decompress for shader image writes (with DB disabled)
2831 * - render with DEPTH_BEFORE_SHADER=1
2832 * Flushing DB metadata works around the problem.
2834 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2837 /* Take the maximum of the old and new count. If the new count is lower,
2838 * dirtying is needed to disable the unbound colorbuffers.
2840 sctx
->framebuffer
.dirty_cbufs
|=
2841 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2842 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2844 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2845 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2847 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2848 sctx
->framebuffer
.spi_shader_col_format
= 0;
2849 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2850 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2851 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2852 sctx
->framebuffer
.color_is_int8
= 0;
2853 sctx
->framebuffer
.color_is_int10
= 0;
2855 sctx
->framebuffer
.compressed_cb_mask
= 0;
2856 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2857 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2858 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2859 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2860 sctx
->framebuffer
.any_dst_linear
= false;
2861 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2862 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2863 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2864 unsigned num_bpp64_colorbufs
= 0;
2866 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2867 if (!state
->cbufs
[i
])
2870 surf
= (struct si_surface
*)state
->cbufs
[i
];
2871 tex
= (struct si_texture
*)surf
->base
.texture
;
2873 if (!surf
->color_initialized
) {
2874 si_initialize_color_surface(sctx
, surf
);
2877 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2878 sctx
->framebuffer
.spi_shader_col_format
|=
2879 surf
->spi_shader_col_format
<< (i
* 4);
2880 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2881 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2882 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2883 surf
->spi_shader_col_format_blend
<< (i
* 4);
2884 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2885 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2887 if (surf
->color_is_int8
)
2888 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2889 if (surf
->color_is_int10
)
2890 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2892 if (tex
->surface
.fmask_size
)
2893 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2895 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2897 /* Don't update nr_color_samples for non-AA buffers.
2898 * (e.g. destination of MSAA resolve)
2900 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2901 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2902 sctx
->framebuffer
.nr_color_samples
=
2903 MIN2(sctx
->framebuffer
.nr_color_samples
,
2904 tex
->buffer
.b
.b
.nr_storage_samples
);
2905 sctx
->framebuffer
.nr_color_samples
=
2906 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2909 if (tex
->surface
.is_linear
)
2910 sctx
->framebuffer
.any_dst_linear
= true;
2911 if (tex
->surface
.bpe
>= 8)
2912 num_bpp64_colorbufs
++;
2914 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
2915 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2917 if (sctx
->chip_class
>= GFX9
&&
2918 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
2919 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
2922 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2924 p_atomic_inc(&tex
->framebuffers_bound
);
2926 if (tex
->dcc_gather_statistics
) {
2927 /* Dirty tracking must be enabled for DCC usage analysis. */
2928 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2929 vi_separate_dcc_start_query(sctx
, tex
);
2933 /* For optimal DCC performance. */
2934 if (sctx
->chip_class
== VI
)
2935 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2936 else if (num_bpp64_colorbufs
>= 5)
2937 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 8;
2939 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2941 struct si_texture
*zstex
= NULL
;
2944 surf
= (struct si_surface
*)state
->zsbuf
;
2945 zstex
= (struct si_texture
*)surf
->base
.texture
;
2947 if (!surf
->depth_initialized
) {
2948 si_init_depth_surface(sctx
, surf
);
2951 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2952 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2954 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2957 si_update_ps_colorbuf0_slot(sctx
);
2958 si_update_poly_offset_state(sctx
);
2959 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2960 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2962 if (sctx
->screen
->dpbb_allowed
)
2963 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2965 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2966 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2968 if (sctx
->screen
->has_out_of_order_rast
&&
2969 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2970 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2971 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2972 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2974 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2975 struct pipe_constant_buffer constbuf
= {0};
2977 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2978 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2980 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2982 /* Set sample locations as fragment shader constants. */
2983 switch (sctx
->framebuffer
.nr_samples
) {
2985 constbuf
.buffer_offset
= 0;
2988 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
2989 (ubyte
*)sctx
->sample_positions
.x1
;
2992 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
2993 (ubyte
*)sctx
->sample_positions
.x1
;
2996 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
2997 (ubyte
*)sctx
->sample_positions
.x1
;
3000 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3001 (ubyte
*)sctx
->sample_positions
.x1
;
3004 PRINT_ERR("Requested an invalid number of samples %i.\n",
3005 sctx
->framebuffer
.nr_samples
);
3008 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3009 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3011 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3014 sctx
->do_update_shaders
= true;
3016 if (!sctx
->decompression_enabled
) {
3017 /* Prevent textures decompression when the framebuffer state
3018 * changes come from the decompression passes themselves.
3020 sctx
->need_check_render_feedback
= true;
3024 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3026 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3027 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3028 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3029 struct si_texture
*tex
= NULL
;
3030 struct si_surface
*cb
= NULL
;
3031 unsigned cb_color_info
= 0;
3034 for (i
= 0; i
< nr_cbufs
; i
++) {
3035 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3036 unsigned cb_color_attrib
;
3038 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3041 cb
= (struct si_surface
*)state
->cbufs
[i
];
3043 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3044 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3048 tex
= (struct si_texture
*)cb
->base
.texture
;
3049 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3050 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3051 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3052 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3053 RADEON_PRIO_COLOR_BUFFER
);
3055 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3056 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3057 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3058 RADEON_PRIO_SEPARATE_META
);
3061 if (tex
->dcc_separate_buffer
)
3062 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3063 tex
->dcc_separate_buffer
,
3064 RADEON_USAGE_READWRITE
,
3065 RADEON_PRIO_SEPARATE_META
);
3067 /* Compute mutable surface parameters. */
3068 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3070 cb_color_cmask
= tex
->cmask_base_address_reg
;
3072 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3073 cb_color_attrib
= cb
->cb_color_attrib
;
3075 if (cb
->base
.u
.tex
.level
> 0)
3076 cb_color_info
&= C_028C70_FAST_CLEAR
;
3078 if (tex
->surface
.fmask_size
) {
3079 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3080 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3084 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3085 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3086 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3087 state
->cbufs
[1] == &cb
->base
&&
3088 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3090 if (!is_msaa_resolve_dst
)
3091 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3093 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3094 tex
->dcc_offset
) >> 8;
3095 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3098 if (sctx
->chip_class
>= GFX9
) {
3099 struct gfx9_surf_meta_flags meta
;
3101 if (tex
->dcc_offset
)
3102 meta
= tex
->surface
.u
.gfx9
.dcc
;
3104 meta
= tex
->surface
.u
.gfx9
.cmask
;
3106 /* Set mutable surface parameters. */
3107 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3108 cb_color_base
|= tex
->surface
.tile_swizzle
;
3109 if (!tex
->surface
.fmask_size
)
3110 cb_color_fmask
= cb_color_base
;
3111 if (cb
->base
.u
.tex
.level
> 0)
3112 cb_color_cmask
= cb_color_base
;
3113 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3114 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3115 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3116 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3118 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3119 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3120 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3121 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3122 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3123 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3124 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3125 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3126 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3127 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3128 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3129 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3130 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3131 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3132 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3133 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3135 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3136 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3138 /* Compute mutable surface parameters (SI-CI-VI). */
3139 const struct legacy_surf_level
*level_info
=
3140 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3141 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3142 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3144 cb_color_base
+= level_info
->offset
>> 8;
3145 /* Only macrotiled modes can set tile swizzle. */
3146 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3147 cb_color_base
|= tex
->surface
.tile_swizzle
;
3149 if (!tex
->surface
.fmask_size
)
3150 cb_color_fmask
= cb_color_base
;
3151 if (cb
->base
.u
.tex
.level
> 0)
3152 cb_color_cmask
= cb_color_base
;
3154 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3156 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3157 slice_tile_max
= level_info
->nblk_x
*
3158 level_info
->nblk_y
/ 64 - 1;
3159 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3161 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3162 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3163 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3165 if (tex
->surface
.fmask_size
) {
3166 if (sctx
->chip_class
>= CIK
)
3167 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3168 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3169 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3171 /* This must be set for fast clear to work without FMASK. */
3172 if (sctx
->chip_class
>= CIK
)
3173 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3174 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3175 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3178 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3179 sctx
->chip_class
>= VI
? 14 : 13);
3180 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3181 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3182 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3183 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3184 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3185 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3186 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3187 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3188 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3189 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3190 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3191 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3192 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3194 if (sctx
->chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3195 radeon_emit(cs
, cb_dcc_base
);
3199 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3200 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3203 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3204 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3205 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3207 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3208 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3209 zb
->base
.texture
->nr_samples
> 1 ?
3210 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3211 RADEON_PRIO_DEPTH_BUFFER
);
3213 if (sctx
->chip_class
>= GFX9
) {
3214 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3215 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3216 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3217 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3219 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3220 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3221 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3222 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3223 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3224 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3225 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3226 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3227 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3228 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3229 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3230 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3232 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3233 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3234 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3236 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3238 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3239 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3240 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3241 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3242 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3243 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3244 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3245 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3246 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3247 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3248 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3251 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3252 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3253 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3255 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3256 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3257 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3258 if (sctx
->chip_class
>= GFX9
)
3259 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3261 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3263 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3264 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3267 /* Framebuffer dimensions. */
3268 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3269 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3270 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3272 if (sctx
->screen
->dfsm_allowed
) {
3273 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3274 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3277 sctx
->framebuffer
.dirty_cbufs
= 0;
3278 sctx
->framebuffer
.dirty_zsbuf
= false;
3281 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3283 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3284 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3285 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3286 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3288 /* Smoothing (only possible with nr_samples == 1) uses the same
3289 * sample locations as the MSAA it simulates.
3291 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3292 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3294 /* On Polaris, the small primitive filter uses the sample locations
3295 * even when MSAA is off, so we need to make sure they're set to 0.
3297 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
) &&
3298 nr_samples
!= sctx
->sample_locs_num_samples
) {
3299 sctx
->sample_locs_num_samples
= nr_samples
;
3300 si_emit_sample_locations(cs
, nr_samples
);
3303 if (sctx
->family
>= CHIP_POLARIS10
) {
3304 unsigned small_prim_filter_cntl
=
3305 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3307 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3309 /* The alternative of setting sample locations to 0 would
3310 * require a DB flush to avoid Z errors, see
3311 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3313 if (has_msaa_sample_loc_bug
&&
3314 sctx
->framebuffer
.nr_samples
> 1 &&
3315 !rs
->multisample_enable
)
3316 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3318 radeon_opt_set_context_reg(sctx
,
3319 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3320 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3321 small_prim_filter_cntl
);
3324 /* The exclusion bits can be set to improve rasterization efficiency
3325 * if no sample lies on the pixel boundary (-8 sample offset).
3327 bool exclusion
= sctx
->chip_class
>= CIK
&&
3328 (!rs
->multisample_enable
|| nr_samples
!= 16);
3329 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3330 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3331 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3332 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3335 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3337 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3338 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3340 if (!sctx
->screen
->has_out_of_order_rast
)
3343 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3346 colormask
&= blend
->cb_target_enabled_4bit
;
3351 /* Conservative: No logic op. */
3352 if (colormask
&& blend
->logicop_enable
)
3355 struct si_dsa_order_invariance dsa_order_invariant
= {
3356 .zs
= true, .pass_set
= true, .pass_last
= false
3359 if (sctx
->framebuffer
.state
.zsbuf
) {
3360 struct si_texture
*zstex
=
3361 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3362 bool has_stencil
= zstex
->surface
.has_stencil
;
3363 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3364 if (!dsa_order_invariant
.zs
)
3367 /* The set of PS invocations is always order invariant,
3368 * except when early Z/S tests are requested. */
3369 if (sctx
->ps_shader
.cso
&&
3370 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3371 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3372 !dsa_order_invariant
.pass_set
)
3375 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3376 !dsa_order_invariant
.pass_set
)
3383 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3386 /* Only commutative blending. */
3387 if (blendmask
& ~blend
->commutative_4bit
)
3390 if (!dsa_order_invariant
.pass_set
)
3394 if (colormask
& ~blendmask
) {
3395 if (!dsa_order_invariant
.pass_last
)
3402 static void si_emit_msaa_config(struct si_context
*sctx
)
3404 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3405 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3406 /* 33% faster rendering to linear color buffers */
3407 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3408 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3409 unsigned sc_mode_cntl_1
=
3410 S_028A4C_WALK_SIZE(dst_is_linear
) |
3411 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3412 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3413 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3414 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3416 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3417 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3418 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3419 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3420 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3421 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3422 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3423 S_028804_INCOHERENT_EQAA_READS(1) |
3424 S_028804_INTERPOLATE_COMP_Z(1) |
3425 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3426 unsigned coverage_samples
, color_samples
, z_samples
;
3428 /* S: Coverage samples (up to 16x):
3429 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3430 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3432 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3433 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3434 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3435 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3436 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3439 * F: Color samples (up to 8x, must be <= coverage samples):
3440 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3441 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3443 * Can be anything between coverage and color samples:
3444 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3445 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3446 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3447 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3448 * # All are currently set the same as coverage samples.
3450 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3451 * flag for undefined color samples. A shader-based resolve must handle unknowns
3452 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3453 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3454 * useful. The CB resolve always drops unknowns.
3456 * Sensible AA configurations:
3457 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3458 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3459 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3460 * EQAA 8s 8z 8f = 8x MSAA
3461 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3462 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3463 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3464 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3465 * EQAA 4s 4z 4f = 4x MSAA
3466 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3467 * EQAA 2s 2z 2f = 2x MSAA
3469 if (sctx
->framebuffer
.nr_samples
> 1) {
3470 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3471 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3473 if (sctx
->framebuffer
.state
.zsbuf
) {
3474 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3475 z_samples
= MAX2(1, z_samples
);
3477 z_samples
= coverage_samples
;
3479 } else if (sctx
->smoothing_enabled
) {
3480 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3482 coverage_samples
= color_samples
= z_samples
= 1;
3485 /* Required by OpenGL line rasterization.
3487 * TODO: We should also enable perpendicular endcaps for AA lines,
3488 * but that requires implementing line stippling in the pixel
3489 * shader. SC can only do line stippling with axis-aligned
3492 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3493 unsigned sc_aa_config
= 0;
3495 if (coverage_samples
> 1) {
3496 /* distance from the pixel center, indexed by log2(nr_samples) */
3497 static unsigned max_dist
[] = {
3504 unsigned log_samples
= util_logbase2(coverage_samples
);
3505 unsigned log_z_samples
= util_logbase2(z_samples
);
3506 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3507 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3509 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3510 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3511 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3512 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3514 if (sctx
->framebuffer
.nr_samples
> 1) {
3515 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3516 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3517 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3518 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3519 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3520 } else if (sctx
->smoothing_enabled
) {
3521 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3525 unsigned initial_cdw
= cs
->current
.cdw
;
3527 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3528 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3529 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3531 /* R_028804_DB_EQAA */
3532 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3534 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3535 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3536 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3538 if (initial_cdw
!= cs
->current
.cdw
) {
3539 sctx
->context_roll_counter
++;
3541 /* GFX9: Flush DFSM when the AA mode changes. */
3542 if (sctx
->screen
->dfsm_allowed
) {
3543 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3544 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3549 void si_update_ps_iter_samples(struct si_context
*sctx
)
3551 if (sctx
->framebuffer
.nr_samples
> 1)
3552 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3553 if (sctx
->screen
->dpbb_allowed
)
3554 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3557 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3559 struct si_context
*sctx
= (struct si_context
*)ctx
;
3561 /* The hardware can only do sample shading with 2^n samples. */
3562 min_samples
= util_next_power_of_two(min_samples
);
3564 if (sctx
->ps_iter_samples
== min_samples
)
3567 sctx
->ps_iter_samples
= min_samples
;
3568 sctx
->do_update_shaders
= true;
3570 si_update_ps_iter_samples(sctx
);
3578 * Build the sampler view descriptor for a buffer texture.
3579 * @param state 256-bit descriptor; only the high 128 bits are filled in
3582 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3583 enum pipe_format format
,
3584 unsigned offset
, unsigned size
,
3587 const struct util_format_description
*desc
;
3590 unsigned num_records
;
3591 unsigned num_format
, data_format
;
3593 desc
= util_format_description(format
);
3594 first_non_void
= util_format_get_first_non_void_channel(format
);
3595 stride
= desc
->block
.bits
/ 8;
3596 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3597 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3599 num_records
= size
/ stride
;
3600 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3602 /* The NUM_RECORDS field has a different meaning depending on the chip,
3603 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3606 * - If STRIDE == 0, it's in byte units.
3607 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3610 * - For SMEM and STRIDE == 0, it's in byte units.
3611 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3612 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3613 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3614 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3615 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3616 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3617 * That way the same descriptor can be used by both SMEM and VMEM.
3620 * - For SMEM and STRIDE == 0, it's in byte units.
3621 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3622 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3623 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3625 if (screen
->info
.chip_class
>= GFX9
&& HAVE_LLVM
< 0x0800)
3626 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3627 * from STRIDE to bytes. This works around it by setting
3628 * NUM_RECORDS to at least the size of one element, so that
3629 * the first element is readable when IDXEN == 0.
3631 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3632 else if (screen
->info
.chip_class
== VI
)
3633 num_records
*= stride
;
3636 state
[5] = S_008F04_STRIDE(stride
);
3637 state
[6] = num_records
;
3638 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3639 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3640 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3641 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3642 S_008F0C_NUM_FORMAT(num_format
) |
3643 S_008F0C_DATA_FORMAT(data_format
);
3646 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3648 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3650 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3651 /* For the pre-defined border color values (white, opaque
3652 * black, transparent black), the only thing that matters is
3653 * that the alpha channel winds up in the correct place
3654 * (because the RGB channels are all the same) so either of
3655 * these enumerations will work.
3657 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3658 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3660 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3661 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3662 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3663 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3665 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3666 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3667 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3668 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3669 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3676 * Build the sampler view descriptor for a texture.
3679 si_make_texture_descriptor(struct si_screen
*screen
,
3680 struct si_texture
*tex
,
3682 enum pipe_texture_target target
,
3683 enum pipe_format pipe_format
,
3684 const unsigned char state_swizzle
[4],
3685 unsigned first_level
, unsigned last_level
,
3686 unsigned first_layer
, unsigned last_layer
,
3687 unsigned width
, unsigned height
, unsigned depth
,
3689 uint32_t *fmask_state
)
3691 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3692 const struct util_format_description
*desc
;
3693 unsigned char swizzle
[4];
3695 unsigned num_format
, data_format
, type
, num_samples
;
3698 desc
= util_format_description(pipe_format
);
3700 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
3701 MAX2(1, res
->nr_samples
) :
3702 MAX2(1, res
->nr_storage_samples
);
3704 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3705 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3706 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3707 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3709 switch (pipe_format
) {
3710 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3711 case PIPE_FORMAT_X32_S8X24_UINT
:
3712 case PIPE_FORMAT_X8Z24_UNORM
:
3713 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3715 case PIPE_FORMAT_X24S8_UINT
:
3717 * X24S8 is implemented as an 8_8_8_8 data format, to
3718 * fix texture gathers. This affects at least
3719 * GL45-CTS.texture_cube_map_array.sampling on VI.
3721 if (screen
->info
.chip_class
<= VI
)
3722 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3724 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3727 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3730 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3733 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3735 switch (pipe_format
) {
3736 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3737 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3740 if (first_non_void
< 0) {
3741 if (util_format_is_compressed(pipe_format
)) {
3742 switch (pipe_format
) {
3743 case PIPE_FORMAT_DXT1_SRGB
:
3744 case PIPE_FORMAT_DXT1_SRGBA
:
3745 case PIPE_FORMAT_DXT3_SRGBA
:
3746 case PIPE_FORMAT_DXT5_SRGBA
:
3747 case PIPE_FORMAT_BPTC_SRGBA
:
3748 case PIPE_FORMAT_ETC2_SRGB8
:
3749 case PIPE_FORMAT_ETC2_SRGB8A1
:
3750 case PIPE_FORMAT_ETC2_SRGBA8
:
3751 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3753 case PIPE_FORMAT_RGTC1_SNORM
:
3754 case PIPE_FORMAT_LATC1_SNORM
:
3755 case PIPE_FORMAT_RGTC2_SNORM
:
3756 case PIPE_FORMAT_LATC2_SNORM
:
3757 case PIPE_FORMAT_ETC2_R11_SNORM
:
3758 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3759 /* implies float, so use SNORM/UNORM to determine
3760 whether data is signed or not */
3761 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3762 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3765 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3768 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3769 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3771 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3773 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3774 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3776 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3778 switch (desc
->channel
[first_non_void
].type
) {
3779 case UTIL_FORMAT_TYPE_FLOAT
:
3780 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3782 case UTIL_FORMAT_TYPE_SIGNED
:
3783 if (desc
->channel
[first_non_void
].normalized
)
3784 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3785 else if (desc
->channel
[first_non_void
].pure_integer
)
3786 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3788 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3790 case UTIL_FORMAT_TYPE_UNSIGNED
:
3791 if (desc
->channel
[first_non_void
].normalized
)
3792 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3793 else if (desc
->channel
[first_non_void
].pure_integer
)
3794 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3796 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3801 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3802 if (data_format
== ~0) {
3806 /* S8 with Z32 HTILE needs a special format. */
3807 if (screen
->info
.chip_class
>= GFX9
&&
3808 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3809 tex
->tc_compatible_htile
)
3810 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3813 (res
->target
== PIPE_TEXTURE_CUBE
||
3814 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3815 (screen
->info
.chip_class
<= VI
&&
3816 res
->target
== PIPE_TEXTURE_3D
))) {
3817 /* For the purpose of shader images, treat cube maps and 3D
3818 * textures as 2D arrays. For 3D textures, the address
3819 * calculations for mipmaps are different, so we rely on the
3820 * caller to effectively disable mipmaps.
3822 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3824 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3826 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
3829 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3831 depth
= res
->array_size
;
3832 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3833 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3834 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3835 depth
= res
->array_size
;
3836 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3837 depth
= res
->array_size
/ 6;
3840 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3841 S_008F14_NUM_FORMAT_GFX6(num_format
));
3842 state
[2] = (S_008F18_WIDTH(width
- 1) |
3843 S_008F18_HEIGHT(height
- 1) |
3844 S_008F18_PERF_MOD(4));
3845 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3846 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3847 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3848 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3849 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
3850 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
3851 util_logbase2(num_samples
) :
3853 S_008F1C_TYPE(type
));
3855 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3859 if (screen
->info
.chip_class
>= GFX9
) {
3860 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3862 /* Depth is the the last accessible layer on Gfx9.
3863 * The hw doesn't need to know the total number of layers.
3865 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3866 state
[4] |= S_008F20_DEPTH(depth
- 1);
3868 state
[4] |= S_008F20_DEPTH(last_layer
);
3870 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3871 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
3872 util_logbase2(num_samples
) :
3873 tex
->buffer
.b
.b
.last_level
);
3875 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3876 state
[4] |= S_008F20_DEPTH(depth
- 1);
3877 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3880 if (tex
->dcc_offset
) {
3881 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
3883 /* The last dword is unused by hw. The shader uses it to clear
3884 * bits in the first dword of sampler state.
3886 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3887 if (first_level
== last_level
)
3888 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3890 state
[7] = 0xffffffff;
3894 /* Initialize the sampler view for FMASK. */
3895 if (tex
->surface
.fmask_size
) {
3896 uint32_t data_format
, num_format
;
3898 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3900 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3901 if (screen
->info
.chip_class
>= GFX9
) {
3902 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3903 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3905 num_format
= V_008F14_IMG_FMASK_8_2_1
;
3908 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3911 num_format
= V_008F14_IMG_FMASK_8_4_1
;
3914 num_format
= V_008F14_IMG_FMASK_8_4_2
;
3917 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3920 num_format
= V_008F14_IMG_FMASK_8_8_1
;
3923 num_format
= V_008F14_IMG_FMASK_16_8_2
;
3926 num_format
= V_008F14_IMG_FMASK_32_8_4
;
3929 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3932 num_format
= V_008F14_IMG_FMASK_16_16_1
;
3935 num_format
= V_008F14_IMG_FMASK_32_16_2
;
3938 num_format
= V_008F14_IMG_FMASK_64_16_4
;
3941 num_format
= V_008F14_IMG_FMASK_64_16_8
;
3944 unreachable("invalid nr_samples");
3947 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3949 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
3952 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3955 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
3958 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
3961 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3964 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
3967 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
3970 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
3973 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3976 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
3979 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
3982 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
3985 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
3988 unreachable("invalid nr_samples");
3990 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3994 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3995 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3996 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3997 S_008F14_NUM_FORMAT_GFX6(num_format
);
3998 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3999 S_008F18_HEIGHT(height
- 1);
4000 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4001 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4002 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4003 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4004 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4006 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4010 if (screen
->info
.chip_class
>= GFX9
) {
4011 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4012 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4013 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4014 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4015 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4017 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4018 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4019 S_008F20_PITCH_GFX6(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4020 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4026 * Create a sampler view.
4028 * @param ctx context
4029 * @param texture texture
4030 * @param state sampler view template
4031 * @param width0 width0 override (for compressed textures as int)
4032 * @param height0 height0 override (for compressed textures as int)
4033 * @param force_level set the base address to the level (for compressed textures)
4035 struct pipe_sampler_view
*
4036 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4037 struct pipe_resource
*texture
,
4038 const struct pipe_sampler_view
*state
,
4039 unsigned width0
, unsigned height0
,
4040 unsigned force_level
)
4042 struct si_context
*sctx
= (struct si_context
*)ctx
;
4043 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4044 struct si_texture
*tex
= (struct si_texture
*)texture
;
4045 unsigned base_level
, first_level
, last_level
;
4046 unsigned char state_swizzle
[4];
4047 unsigned height
, depth
, width
;
4048 unsigned last_layer
= state
->u
.tex
.last_layer
;
4049 enum pipe_format pipe_format
;
4050 const struct legacy_surf_level
*surflevel
;
4055 /* initialize base object */
4056 view
->base
= *state
;
4057 view
->base
.texture
= NULL
;
4058 view
->base
.reference
.count
= 1;
4059 view
->base
.context
= ctx
;
4062 pipe_resource_reference(&view
->base
.texture
, texture
);
4064 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4065 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4066 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4067 state
->format
== PIPE_FORMAT_S8_UINT
)
4068 view
->is_stencil_sampler
= true;
4070 /* Buffer resource. */
4071 if (texture
->target
== PIPE_BUFFER
) {
4072 si_make_buffer_descriptor(sctx
->screen
,
4073 si_resource(texture
),
4075 state
->u
.buf
.offset
,
4081 state_swizzle
[0] = state
->swizzle_r
;
4082 state_swizzle
[1] = state
->swizzle_g
;
4083 state_swizzle
[2] = state
->swizzle_b
;
4084 state_swizzle
[3] = state
->swizzle_a
;
4087 first_level
= state
->u
.tex
.first_level
;
4088 last_level
= state
->u
.tex
.last_level
;
4091 depth
= texture
->depth0
;
4093 if (sctx
->chip_class
<= VI
&& force_level
) {
4094 assert(force_level
== first_level
&&
4095 force_level
== last_level
);
4096 base_level
= force_level
;
4099 width
= u_minify(width
, force_level
);
4100 height
= u_minify(height
, force_level
);
4101 depth
= u_minify(depth
, force_level
);
4104 /* This is not needed if state trackers set last_layer correctly. */
4105 if (state
->target
== PIPE_TEXTURE_1D
||
4106 state
->target
== PIPE_TEXTURE_2D
||
4107 state
->target
== PIPE_TEXTURE_RECT
||
4108 state
->target
== PIPE_TEXTURE_CUBE
)
4109 last_layer
= state
->u
.tex
.first_layer
;
4111 /* Texturing with separate depth and stencil. */
4112 pipe_format
= state
->format
;
4114 /* Depth/stencil texturing sometimes needs separate texture. */
4115 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4116 if (!tex
->flushed_depth_texture
&&
4117 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
4118 pipe_resource_reference(&view
->base
.texture
, NULL
);
4123 assert(tex
->flushed_depth_texture
);
4125 /* Override format for the case where the flushed texture
4126 * contains only Z or only S.
4128 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4129 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4131 tex
= tex
->flushed_depth_texture
;
4134 surflevel
= tex
->surface
.u
.legacy
.level
;
4136 if (tex
->db_compatible
) {
4137 if (!view
->is_stencil_sampler
)
4138 pipe_format
= tex
->db_render_format
;
4140 switch (pipe_format
) {
4141 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4142 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4144 case PIPE_FORMAT_X8Z24_UNORM
:
4145 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4146 /* Z24 is always stored like this for DB
4149 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4151 case PIPE_FORMAT_X24S8_UINT
:
4152 case PIPE_FORMAT_S8X24_UINT
:
4153 case PIPE_FORMAT_X32_S8X24_UINT
:
4154 pipe_format
= PIPE_FORMAT_S8_UINT
;
4155 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4161 view
->dcc_incompatible
=
4162 vi_dcc_formats_are_incompatible(texture
,
4163 state
->u
.tex
.first_level
,
4166 si_make_texture_descriptor(sctx
->screen
, tex
, true,
4167 state
->target
, pipe_format
, state_swizzle
,
4168 first_level
, last_level
,
4169 state
->u
.tex
.first_layer
, last_layer
,
4170 width
, height
, depth
,
4171 view
->state
, view
->fmask_state
);
4173 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
4175 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
4176 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
4177 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
4178 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
4179 view
->base_level_info
= &surflevel
[base_level
];
4180 view
->base_level
= base_level
;
4181 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4185 static struct pipe_sampler_view
*
4186 si_create_sampler_view(struct pipe_context
*ctx
,
4187 struct pipe_resource
*texture
,
4188 const struct pipe_sampler_view
*state
)
4190 return si_create_sampler_view_custom(ctx
, texture
, state
,
4191 texture
? texture
->width0
: 0,
4192 texture
? texture
->height0
: 0, 0);
4195 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4196 struct pipe_sampler_view
*state
)
4198 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4200 pipe_resource_reference(&state
->texture
, NULL
);
4204 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4206 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4207 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4209 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4210 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4213 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4214 const struct pipe_sampler_state
*state
,
4215 const union pipe_color_union
*color
,
4218 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4219 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4221 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4222 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4223 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4224 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4226 #define simple_border_types(elt) \
4228 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4229 color->elt[2] == 0 && color->elt[3] == 0) \
4230 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4231 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4232 color->elt[2] == 0 && color->elt[3] == 1) \
4233 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4234 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4235 color->elt[2] == 1 && color->elt[3] == 1) \
4236 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4240 simple_border_types(ui
);
4242 simple_border_types(f
);
4244 #undef simple_border_types
4248 /* Check if the border has been uploaded already. */
4249 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4250 if (memcmp(&sctx
->border_color_table
[i
], color
,
4251 sizeof(*color
)) == 0)
4254 if (i
>= SI_MAX_BORDER_COLORS
) {
4255 /* Getting 4096 unique border colors is very unlikely. */
4256 fprintf(stderr
, "radeonsi: The border color table is full. "
4257 "Any new border colors will be just black. "
4258 "Please file a bug.\n");
4259 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4262 if (i
== sctx
->border_color_count
) {
4263 /* Upload a new border color. */
4264 memcpy(&sctx
->border_color_table
[i
], color
,
4266 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4267 color
, sizeof(*color
));
4268 sctx
->border_color_count
++;
4271 return S_008F3C_BORDER_COLOR_PTR(i
) |
4272 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4275 static inline int S_FIXED(float value
, unsigned frac_bits
)
4277 return value
* (1 << frac_bits
);
4280 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4282 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4283 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4284 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4286 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4287 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4290 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4303 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4304 const struct pipe_sampler_state
*state
)
4306 struct si_context
*sctx
= (struct si_context
*)ctx
;
4307 struct si_screen
*sscreen
= sctx
->screen
;
4308 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4309 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4310 : state
->max_anisotropy
;
4311 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4312 union pipe_color_union clamped_border_color
;
4319 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4321 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4322 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4323 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4324 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4325 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4326 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4327 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4328 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4329 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4330 S_008F30_COMPAT_MODE(sctx
->chip_class
>= VI
));
4331 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4332 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4333 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4334 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4335 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4336 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4337 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4338 S_008F38_MIP_POINT_PRECLAMP(0) |
4339 S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= VI
) |
4340 S_008F38_FILTER_PREC_FIX(1) |
4341 S_008F38_ANISO_OVERRIDE(sctx
->chip_class
>= VI
));
4342 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4344 /* Create sampler resource for integer textures. */
4345 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4346 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4348 /* Create sampler resource for upgraded depth textures. */
4349 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4351 for (unsigned i
= 0; i
< 4; ++i
) {
4352 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4353 * when the border color is 1.0. */
4354 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4357 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4358 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4360 rstate
->upgraded_depth_val
[3] =
4361 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4362 S_008F3C_UPGRADED_DEPTH(1);
4367 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4369 struct si_context
*sctx
= (struct si_context
*)ctx
;
4371 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4374 sctx
->sample_mask
= sample_mask
;
4375 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4378 static void si_emit_sample_mask(struct si_context
*sctx
)
4380 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4381 unsigned mask
= sctx
->sample_mask
;
4383 /* Needed for line and polygon smoothing as well as for the Polaris
4384 * small primitive filter. We expect the state tracker to take care of
4387 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4388 (mask
& 1 && sctx
->blitter
->running
));
4390 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4391 radeon_emit(cs
, mask
| (mask
<< 16));
4392 radeon_emit(cs
, mask
| (mask
<< 16));
4395 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4398 struct si_sampler_state
*s
= state
;
4400 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4407 * Vertex elements & buffers
4410 struct util_fast_udiv_info32
{
4411 unsigned multiplier
; /* the "magic number" multiplier */
4412 unsigned pre_shift
; /* shift for the dividend before multiplying */
4413 unsigned post_shift
; /* shift for the dividend after multiplying */
4414 int increment
; /* 0 or 1; if set then increment the numerator, using one of
4415 the two strategies */
4418 static struct util_fast_udiv_info32
4419 util_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4421 struct util_fast_udiv_info info
=
4422 util_compute_fast_udiv_info(D
, num_bits
, 32);
4424 struct util_fast_udiv_info32 result
= {
4433 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4435 const struct pipe_vertex_element
*elements
)
4437 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4438 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4439 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4440 struct util_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4441 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32
) == 16);
4442 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4443 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4444 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4445 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4448 assert(count
<= SI_MAX_ATTRIBS
);
4453 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4455 for (i
= 0; i
< count
; ++i
) {
4456 const struct util_format_description
*desc
;
4457 const struct util_format_channel_description
*channel
;
4458 unsigned data_format
, num_format
;
4460 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4461 unsigned char swizzle
[4];
4463 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4468 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4469 if (instance_divisor
) {
4470 v
->uses_instance_divisors
= true;
4472 if (instance_divisor
== 1) {
4473 v
->instance_divisor_is_one
|= 1u << i
;
4475 v
->instance_divisor_is_fetched
|= 1u << i
;
4476 divisor_factors
[i
] =
4477 util_compute_fast_udiv_info32(instance_divisor
, 32);
4481 if (!used
[vbo_index
]) {
4482 v
->first_vb_use_mask
|= 1 << i
;
4483 used
[vbo_index
] = true;
4486 desc
= util_format_description(elements
[i
].src_format
);
4487 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4488 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4489 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4490 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4491 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4493 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4494 v
->src_offset
[i
] = elements
[i
].src_offset
;
4495 v
->vertex_buffer_index
[i
] = vbo_index
;
4497 /* The hardware always treats the 2-bit alpha channel as
4498 * unsigned, so a shader workaround is needed. The affected
4499 * chips are VI and older except Stoney (GFX8.1).
4501 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4502 sscreen
->info
.chip_class
<= VI
&&
4503 sscreen
->info
.family
!= CHIP_STONEY
) {
4504 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4505 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4506 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4507 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4508 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4509 /* This isn't actually used in OpenGL. */
4510 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4512 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4513 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4514 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4516 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4517 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4518 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4519 if (channel
->normalized
) {
4520 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4521 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4523 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4525 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4527 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4528 if (channel
->normalized
) {
4529 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4530 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4532 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4534 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4537 } else if (channel
&& channel
->size
== 64 &&
4538 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4539 switch (desc
->nr_channels
) {
4542 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4543 swizzle
[0] = PIPE_SWIZZLE_X
;
4544 swizzle
[1] = PIPE_SWIZZLE_Y
;
4545 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4546 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4549 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4550 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4551 swizzle
[1] = PIPE_SWIZZLE_Y
;
4552 swizzle
[2] = PIPE_SWIZZLE_0
;
4553 swizzle
[3] = PIPE_SWIZZLE_0
;
4556 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4557 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4558 swizzle
[1] = PIPE_SWIZZLE_Y
;
4559 swizzle
[2] = PIPE_SWIZZLE_Z
;
4560 swizzle
[3] = PIPE_SWIZZLE_W
;
4565 } else if (channel
&& desc
->nr_channels
== 3) {
4566 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4568 if (channel
->size
== 8) {
4569 if (channel
->pure_integer
)
4570 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4572 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4573 } else if (channel
->size
== 16) {
4574 if (channel
->pure_integer
)
4575 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4577 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4581 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4582 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4583 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4584 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4585 S_008F0C_NUM_FORMAT(num_format
) |
4586 S_008F0C_DATA_FORMAT(data_format
);
4589 if (v
->instance_divisor_is_fetched
) {
4590 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4592 v
->instance_divisor_factor_buffer
=
4593 (struct si_resource
*)
4594 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
4595 num_divisors
* sizeof(divisor_factors
[0]));
4596 if (!v
->instance_divisor_factor_buffer
) {
4600 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
4601 NULL
, PIPE_TRANSFER_WRITE
);
4602 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4607 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4609 struct si_context
*sctx
= (struct si_context
*)ctx
;
4610 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4611 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4613 sctx
->vertex_elements
= v
;
4614 sctx
->vertex_buffers_dirty
= true;
4618 old
->count
!= v
->count
||
4619 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4620 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4621 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4622 sctx
->do_update_shaders
= true;
4624 if (v
&& v
->instance_divisor_is_fetched
) {
4625 struct pipe_constant_buffer cb
;
4627 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4628 cb
.user_buffer
= NULL
;
4629 cb
.buffer_offset
= 0;
4630 cb
.buffer_size
= 0xffffffff;
4631 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4635 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4637 struct si_context
*sctx
= (struct si_context
*)ctx
;
4638 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4640 if (sctx
->vertex_elements
== state
)
4641 sctx
->vertex_elements
= NULL
;
4642 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4646 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4647 unsigned start_slot
, unsigned count
,
4648 const struct pipe_vertex_buffer
*buffers
)
4650 struct si_context
*sctx
= (struct si_context
*)ctx
;
4651 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4654 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4657 for (i
= 0; i
< count
; i
++) {
4658 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4659 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4660 struct pipe_resource
*buf
= src
->buffer
.resource
;
4662 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4663 dsti
->buffer_offset
= src
->buffer_offset
;
4664 dsti
->stride
= src
->stride
;
4665 si_context_add_resource_size(sctx
, buf
);
4667 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4670 for (i
= 0; i
< count
; i
++) {
4671 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4674 sctx
->vertex_buffers_dirty
= true;
4681 static void si_set_tess_state(struct pipe_context
*ctx
,
4682 const float default_outer_level
[4],
4683 const float default_inner_level
[2])
4685 struct si_context
*sctx
= (struct si_context
*)ctx
;
4686 struct pipe_constant_buffer cb
;
4689 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4690 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4693 cb
.user_buffer
= NULL
;
4694 cb
.buffer_size
= sizeof(array
);
4696 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
4697 (void*)array
, sizeof(array
),
4700 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4701 pipe_resource_reference(&cb
.buffer
, NULL
);
4704 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4706 struct si_context
*sctx
= (struct si_context
*)ctx
;
4708 si_update_fb_dirtiness_after_rendering(sctx
);
4710 /* Multisample surfaces are flushed in si_decompress_textures. */
4711 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
4712 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4713 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
4714 sctx
->framebuffer
.all_DCC_pipe_aligned
);
4718 /* This only ensures coherency for shader image/buffer stores. */
4719 void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4721 struct si_context
*sctx
= (struct si_context
*)ctx
;
4723 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
4726 /* Subsequent commands must wait for all shader invocations to
4728 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4729 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4731 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4732 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
|
4733 SI_CONTEXT_INV_VMEM_L1
;
4735 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4736 PIPE_BARRIER_SHADER_BUFFER
|
4737 PIPE_BARRIER_TEXTURE
|
4738 PIPE_BARRIER_IMAGE
|
4739 PIPE_BARRIER_STREAMOUT_BUFFER
|
4740 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4741 /* As far as I can tell, L1 contents are written back to L2
4742 * automatically at end of shader, but the contents of other
4743 * L1 caches might still be stale. */
4744 sctx
->flags
|= SI_CONTEXT_INV_VMEM_L1
;
4747 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4748 /* Indices are read through TC L2 since VI.
4751 if (sctx
->screen
->info
.chip_class
<= CIK
)
4752 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4755 /* MSAA color, any depth and any stencil are flushed in
4756 * si_decompress_textures when needed.
4758 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4759 sctx
->framebuffer
.uncompressed_cb_mask
) {
4760 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4762 if (sctx
->chip_class
<= VI
)
4763 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4766 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4767 if (sctx
->screen
->info
.chip_class
<= VI
&&
4768 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4769 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4772 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4774 struct pipe_blend_state blend
;
4776 memset(&blend
, 0, sizeof(blend
));
4777 blend
.independent_blend_enable
= true;
4778 blend
.rt
[0].colormask
= 0xf;
4779 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4782 static void si_init_config(struct si_context
*sctx
);
4784 void si_init_state_functions(struct si_context
*sctx
)
4786 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
4787 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
4788 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
4789 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
4790 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
4791 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
4792 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
4793 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
4794 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
4795 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
4796 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
4798 sctx
->b
.create_blend_state
= si_create_blend_state
;
4799 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4800 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4801 sctx
->b
.set_blend_color
= si_set_blend_color
;
4803 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4804 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4805 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4807 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4808 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4809 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4811 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4812 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4813 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4814 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4815 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4817 sctx
->b
.set_clip_state
= si_set_clip_state
;
4818 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
4820 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
4822 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4823 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4825 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4826 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4828 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
4830 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
4831 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4832 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4833 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
4835 sctx
->b
.texture_barrier
= si_texture_barrier
;
4836 sctx
->b
.set_min_samples
= si_set_min_samples
;
4837 sctx
->b
.set_tess_state
= si_set_tess_state
;
4839 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
4841 si_init_config(sctx
);
4844 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4846 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4849 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4850 struct si_pm4_state
*pm4
, unsigned value
)
4852 unsigned reg
= sctx
->chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4853 R_00802C_GRBM_GFX_INDEX
;
4854 si_pm4_set_reg(pm4
, reg
, value
);
4857 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4858 struct si_pm4_state
*pm4
, unsigned se
)
4860 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4861 si_set_grbm_gfx_index(sctx
, pm4
,
4862 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4863 S_030800_SE_INDEX(se
)) |
4864 S_030800_SH_BROADCAST_WRITES(1) |
4865 S_030800_INSTANCE_BROADCAST_WRITES(1));
4869 si_write_harvested_raster_configs(struct si_context
*sctx
,
4870 struct si_pm4_state
*pm4
,
4871 unsigned raster_config
,
4872 unsigned raster_config_1
)
4874 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4875 unsigned raster_config_se
[4];
4878 ac_get_harvested_configs(&sctx
->screen
->info
,
4883 for (se
= 0; se
< num_se
; se
++) {
4884 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4885 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
4887 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4889 if (sctx
->chip_class
>= CIK
) {
4890 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4894 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4896 struct si_screen
*sscreen
= sctx
->screen
;
4897 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
4898 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
4899 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
4900 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
4902 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4903 /* Always use the default config when all backends are enabled
4904 * (or when we failed to determine the enabled backends).
4906 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4908 if (sctx
->chip_class
>= CIK
)
4909 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4912 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4916 static void si_init_config(struct si_context
*sctx
)
4918 struct si_screen
*sscreen
= sctx
->screen
;
4919 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4920 bool has_clear_state
= sscreen
->has_clear_state
;
4921 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4923 /* SI, radeon kernel disabled CLEAR_STATE. */
4924 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
||
4925 sscreen
->info
.drm_major
!= 3);
4930 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4931 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4932 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4933 si_pm4_cmd_end(pm4
, false);
4935 if (has_clear_state
) {
4936 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4937 si_pm4_cmd_add(pm4
, 0);
4938 si_pm4_cmd_end(pm4
, false);
4941 if (sctx
->chip_class
<= VI
)
4942 si_set_raster_config(sctx
, pm4
);
4944 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4945 if (!has_clear_state
)
4946 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4948 /* FIXME calculate these values somehow ??? */
4949 if (sctx
->chip_class
<= VI
) {
4950 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4951 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4954 if (!has_clear_state
) {
4955 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4956 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4957 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4960 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4961 if (!has_clear_state
)
4962 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4963 if (sctx
->chip_class
< CIK
)
4964 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4965 S_008A14_CLIP_VTX_REORDER_ENA(1));
4967 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4968 * I don't know why. Deduced by trial and error.
4970 if (sctx
->chip_class
<= CIK
) {
4971 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4972 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4973 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4974 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4975 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4976 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4977 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4978 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4981 if (!has_clear_state
) {
4982 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4983 S_028230_ER_TRI(0xA) |
4984 S_028230_ER_POINT(0xA) |
4985 S_028230_ER_RECT(0xA) |
4986 /* Required by DX10_DIAMOND_TEST_ENA: */
4987 S_028230_ER_LINE_LR(0x1A) |
4988 S_028230_ER_LINE_RL(0x26) |
4989 S_028230_ER_LINE_TB(0xA) |
4990 S_028230_ER_LINE_BT(0xA));
4991 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4992 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4993 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4994 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4995 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4998 if (sctx
->chip_class
>= GFX9
) {
4999 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5000 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5001 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5003 /* These registers, when written, also overwrite the CLEAR_STATE
5004 * context, so we can't rely on CLEAR_STATE setting them.
5005 * It would be an issue if there was another UMD changing them.
5007 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5008 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5009 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5012 if (sctx
->chip_class
>= CIK
) {
5013 if (sctx
->chip_class
>= GFX9
) {
5014 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5015 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5017 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5018 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5019 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5020 S_00B41C_WAVE_LIMIT(0x3F));
5021 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5022 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5024 /* If this is 0, Bonaire can hang even if GS isn't being used.
5025 * Other chips are unaffected. These are suboptimal values,
5026 * but we don't use on-chip GS.
5028 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5029 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5030 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5032 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5033 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5035 /* Compute LATE_ALLOC_VS.LIMIT. */
5036 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5037 unsigned late_alloc_limit
; /* The limit is per SH. */
5039 if (sctx
->family
== CHIP_KABINI
) {
5040 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5041 } else if (num_cu_per_sh
<= 4) {
5042 /* Too few available compute units per SH. Disallowing
5043 * VS to run on one CU could hurt us more than late VS
5044 * allocation would help.
5046 * 2 is the highest safe number that allows us to keep
5049 late_alloc_limit
= 2;
5051 /* This is a good initial value, allowing 1 late_alloc
5052 * wave per SIMD on num_cu - 2.
5054 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5056 /* The limit is 0-based, so 0 means 1. */
5057 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
5058 late_alloc_limit
-= 1;
5061 /* VS can't execute on one CU if the limit is > 2. */
5062 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5063 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
5064 S_00B118_WAVE_LIMIT(0x3F));
5065 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5066 S_00B11C_LIMIT(late_alloc_limit
));
5067 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5068 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5071 if (sctx
->chip_class
>= VI
) {
5072 unsigned vgt_tess_distribution
;
5074 vgt_tess_distribution
=
5075 S_028B50_ACCUM_ISOLINE(32) |
5076 S_028B50_ACCUM_TRI(11) |
5077 S_028B50_ACCUM_QUAD(11) |
5078 S_028B50_DONUT_SPLIT(16);
5080 /* Testing with Unigine Heaven extreme tesselation yielded best results
5081 * with TRAP_SPLIT = 3.
5083 if (sctx
->family
== CHIP_FIJI
||
5084 sctx
->family
>= CHIP_POLARIS10
)
5085 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5087 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5088 } else if (!has_clear_state
) {
5089 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5090 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5093 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5094 if (sctx
->chip_class
>= CIK
) {
5095 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5096 S_028084_ADDRESS(border_color_va
>> 40));
5098 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5099 RADEON_PRIO_BORDER_COLORS
);
5101 if (sctx
->chip_class
>= GFX9
) {
5102 unsigned num_se
= sscreen
->info
.max_se
;
5103 unsigned pc_lines
= 0;
5105 switch (sctx
->family
) {
5119 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5120 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5121 S_028C48_MAX_PRIM_PER_BATCH(1023));
5122 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5123 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5124 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5127 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5128 sctx
->init_config
= pm4
;