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radeonsi: emit VS_STATE register explicitly from si_draw_vbo
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
607 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
608 sctx->do_update_shaders = true;
609 }
610
611 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
612 {
613 struct si_context *sctx = (struct si_context *)ctx;
614 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
615 }
616
617 static void si_set_blend_color(struct pipe_context *ctx,
618 const struct pipe_blend_color *state)
619 {
620 struct si_context *sctx = (struct si_context *)ctx;
621
622 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
623 return;
624
625 sctx->blend_color.state = *state;
626 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
627 }
628
629 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
630 {
631 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
632
633 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
634 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
635 }
636
637 /*
638 * Clipping
639 */
640
641 static void si_set_clip_state(struct pipe_context *ctx,
642 const struct pipe_clip_state *state)
643 {
644 struct si_context *sctx = (struct si_context *)ctx;
645 struct pipe_constant_buffer cb;
646
647 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
648 return;
649
650 sctx->clip_state.state = *state;
651 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
652
653 cb.buffer = NULL;
654 cb.user_buffer = state->ucp;
655 cb.buffer_offset = 0;
656 cb.buffer_size = 4*4*8;
657 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
658 pipe_resource_reference(&cb.buffer, NULL);
659 }
660
661 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
662 {
663 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
664
665 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
666 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
667 }
668
669 #define SIX_BITS 0x3F
670
671 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
672 {
673 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
674 struct si_shader *vs = si_get_vs_state(sctx);
675 struct tgsi_shader_info *info = si_get_vs_info(sctx);
676 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
677 unsigned window_space =
678 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
679 unsigned clipdist_mask =
680 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
681 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
682 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
683 unsigned total_mask;
684 bool misc_vec_ena;
685
686 if (vs->key.opt.hw_vs.clip_disable) {
687 assert(!info->culldist_writemask);
688 clipdist_mask = 0;
689 culldist_mask = 0;
690 }
691 total_mask = clipdist_mask | culldist_mask;
692
693 /* Clip distances on points have no effect, so need to be implemented
694 * as cull distances. This applies for the clipvertex case as well.
695 *
696 * Setting this for primitives other than points should have no adverse
697 * effects.
698 */
699 clipdist_mask &= rs->clip_plane_enable;
700 culldist_mask |= clipdist_mask;
701
702 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
703 info->writes_layer || info->writes_viewport_index;
704
705 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
706 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
707 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
708 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
709 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
710 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
711 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
712 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
713 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
714 clipdist_mask | (culldist_mask << 8));
715 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
716 rs->pa_cl_clip_cntl |
717 ucp_mask |
718 S_028810_CLIP_DISABLE(window_space));
719
720 /* reuse needs to be set off if we write oViewport */
721 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
722 S_028AB4_REUSE_OFF(info->writes_viewport_index));
723 }
724
725 /*
726 * inferred state between framebuffer and rasterizer
727 */
728 static void si_update_poly_offset_state(struct si_context *sctx)
729 {
730 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
731
732 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
733 si_pm4_bind_state(sctx, poly_offset, NULL);
734 return;
735 }
736
737 /* Use the user format, not db_render_format, so that the polygon
738 * offset behaves as expected by applications.
739 */
740 switch (sctx->framebuffer.state.zsbuf->texture->format) {
741 case PIPE_FORMAT_Z16_UNORM:
742 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
743 break;
744 default: /* 24-bit */
745 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
746 break;
747 case PIPE_FORMAT_Z32_FLOAT:
748 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
749 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
750 break;
751 }
752 }
753
754 /*
755 * Rasterizer
756 */
757
758 static uint32_t si_translate_fill(uint32_t func)
759 {
760 switch(func) {
761 case PIPE_POLYGON_MODE_FILL:
762 return V_028814_X_DRAW_TRIANGLES;
763 case PIPE_POLYGON_MODE_LINE:
764 return V_028814_X_DRAW_LINES;
765 case PIPE_POLYGON_MODE_POINT:
766 return V_028814_X_DRAW_POINTS;
767 default:
768 assert(0);
769 return V_028814_X_DRAW_POINTS;
770 }
771 }
772
773 static void *si_create_rs_state(struct pipe_context *ctx,
774 const struct pipe_rasterizer_state *state)
775 {
776 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
777 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
778 struct si_pm4_state *pm4 = &rs->pm4;
779 unsigned tmp, i;
780 float psize_min, psize_max;
781
782 if (!rs) {
783 return NULL;
784 }
785
786 rs->scissor_enable = state->scissor;
787 rs->clip_halfz = state->clip_halfz;
788 rs->two_side = state->light_twoside;
789 rs->multisample_enable = state->multisample;
790 rs->force_persample_interp = state->force_persample_interp;
791 rs->clip_plane_enable = state->clip_plane_enable;
792 rs->line_stipple_enable = state->line_stipple_enable;
793 rs->poly_stipple_enable = state->poly_stipple_enable;
794 rs->line_smooth = state->line_smooth;
795 rs->poly_smooth = state->poly_smooth;
796 rs->uses_poly_offset = state->offset_point || state->offset_line ||
797 state->offset_tri;
798 rs->clamp_fragment_color = state->clamp_fragment_color;
799 rs->clamp_vertex_color = state->clamp_vertex_color;
800 rs->flatshade = state->flatshade;
801 rs->sprite_coord_enable = state->sprite_coord_enable;
802 rs->rasterizer_discard = state->rasterizer_discard;
803 rs->pa_sc_line_stipple = state->line_stipple_enable ?
804 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
805 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
806 rs->pa_cl_clip_cntl =
807 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
808 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
809 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
810 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
811 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
812
813 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
814 S_0286D4_FLAT_SHADE_ENA(1) |
815 S_0286D4_PNT_SPRITE_ENA(1) |
816 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
817 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
818 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
819 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
820 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
821
822 /* point size 12.4 fixed point */
823 tmp = (unsigned)(state->point_size * 8.0);
824 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
825
826 if (state->point_size_per_vertex) {
827 psize_min = util_get_min_point_size(state);
828 psize_max = 8192;
829 } else {
830 /* Force the point size to be as if the vertex output was disabled. */
831 psize_min = state->point_size;
832 psize_max = state->point_size;
833 }
834 /* Divide by two, because 0.5 = 1 pixel. */
835 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
836 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
837 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
838
839 tmp = (unsigned)state->line_width * 8;
840 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
841 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
842 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
843 S_028A48_MSAA_ENABLE(state->multisample ||
844 state->poly_smooth ||
845 state->line_smooth) |
846 S_028A48_VPORT_SCISSOR_ENABLE(1) |
847 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
848
849 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
850 S_028BE4_PIX_CENTER(state->half_pixel_center) |
851 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
852
853 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
854 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
855 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
856 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
857 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
858 S_028814_FACE(!state->front_ccw) |
859 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
860 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
861 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
862 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
863 state->fill_back != PIPE_POLYGON_MODE_FILL) |
864 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
865 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
866
867 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
868 for (i = 0; i < 3; i++) {
869 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
870 float offset_units = state->offset_units;
871 float offset_scale = state->offset_scale * 16.0f;
872 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
873
874 if (!state->offset_units_unscaled) {
875 switch (i) {
876 case 0: /* 16-bit zbuffer */
877 offset_units *= 4.0f;
878 pa_su_poly_offset_db_fmt_cntl =
879 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
880 break;
881 case 1: /* 24-bit zbuffer */
882 offset_units *= 2.0f;
883 pa_su_poly_offset_db_fmt_cntl =
884 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
885 break;
886 case 2: /* 32-bit zbuffer */
887 offset_units *= 1.0f;
888 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
889 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
890 break;
891 }
892 }
893
894 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
895 fui(offset_scale));
896 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
897 fui(offset_units));
898 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
899 fui(offset_scale));
900 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
901 fui(offset_units));
902 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
903 pa_su_poly_offset_db_fmt_cntl);
904 }
905
906 return rs;
907 }
908
909 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
910 {
911 struct si_context *sctx = (struct si_context *)ctx;
912 struct si_state_rasterizer *old_rs =
913 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
914 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
915
916 if (!state)
917 return;
918
919 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
920 si_mark_atom_dirty(sctx, &sctx->db_render_state);
921
922 /* Update the small primitive filter workaround if necessary. */
923 if (sctx->screen->has_msaa_sample_loc_bug &&
924 sctx->framebuffer.nr_samples > 1)
925 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
926 }
927
928 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
929 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
930
931 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
932
933 si_pm4_bind_state(sctx, rasterizer, rs);
934 si_update_poly_offset_state(sctx);
935
936 si_mark_atom_dirty(sctx, &sctx->clip_regs);
937 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
938 rs->line_stipple_enable;
939 sctx->do_update_shaders = true;
940 }
941
942 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
943 {
944 struct si_context *sctx = (struct si_context *)ctx;
945
946 if (sctx->queued.named.rasterizer == state)
947 si_pm4_bind_state(sctx, poly_offset, NULL);
948 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
949 }
950
951 /*
952 * infeered state between dsa and stencil ref
953 */
954 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
955 {
956 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
957 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
958 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
959
960 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
961 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
962 S_028430_STENCILMASK(dsa->valuemask[0]) |
963 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
964 S_028430_STENCILOPVAL(1));
965 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
966 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
967 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
968 S_028434_STENCILOPVAL_BF(1));
969 }
970
971 static void si_set_stencil_ref(struct pipe_context *ctx,
972 const struct pipe_stencil_ref *state)
973 {
974 struct si_context *sctx = (struct si_context *)ctx;
975
976 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
977 return;
978
979 sctx->stencil_ref.state = *state;
980 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
981 }
982
983
984 /*
985 * DSA
986 */
987
988 static uint32_t si_translate_stencil_op(int s_op)
989 {
990 switch (s_op) {
991 case PIPE_STENCIL_OP_KEEP:
992 return V_02842C_STENCIL_KEEP;
993 case PIPE_STENCIL_OP_ZERO:
994 return V_02842C_STENCIL_ZERO;
995 case PIPE_STENCIL_OP_REPLACE:
996 return V_02842C_STENCIL_REPLACE_TEST;
997 case PIPE_STENCIL_OP_INCR:
998 return V_02842C_STENCIL_ADD_CLAMP;
999 case PIPE_STENCIL_OP_DECR:
1000 return V_02842C_STENCIL_SUB_CLAMP;
1001 case PIPE_STENCIL_OP_INCR_WRAP:
1002 return V_02842C_STENCIL_ADD_WRAP;
1003 case PIPE_STENCIL_OP_DECR_WRAP:
1004 return V_02842C_STENCIL_SUB_WRAP;
1005 case PIPE_STENCIL_OP_INVERT:
1006 return V_02842C_STENCIL_INVERT;
1007 default:
1008 R600_ERR("Unknown stencil op %d", s_op);
1009 assert(0);
1010 break;
1011 }
1012 return 0;
1013 }
1014
1015 static void *si_create_dsa_state(struct pipe_context *ctx,
1016 const struct pipe_depth_stencil_alpha_state *state)
1017 {
1018 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1019 struct si_pm4_state *pm4 = &dsa->pm4;
1020 unsigned db_depth_control;
1021 uint32_t db_stencil_control = 0;
1022
1023 if (!dsa) {
1024 return NULL;
1025 }
1026
1027 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1028 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1029 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1030 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1031
1032 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1033 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1034 S_028800_ZFUNC(state->depth.func) |
1035 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1036
1037 /* stencil */
1038 if (state->stencil[0].enabled) {
1039 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1040 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1041 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1042 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1043 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1044
1045 if (state->stencil[1].enabled) {
1046 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1047 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1048 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1049 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1050 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1051 }
1052 }
1053
1054 /* alpha */
1055 if (state->alpha.enabled) {
1056 dsa->alpha_func = state->alpha.func;
1057
1058 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1059 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1060 } else {
1061 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1062 }
1063
1064 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1065 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1066 if (state->depth.bounds_test) {
1067 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1068 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1069 }
1070
1071 return dsa;
1072 }
1073
1074 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1075 {
1076 struct si_context *sctx = (struct si_context *)ctx;
1077 struct si_state_dsa *dsa = state;
1078
1079 if (!state)
1080 return;
1081
1082 si_pm4_bind_state(sctx, dsa, dsa);
1083
1084 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1085 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1086 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1087 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1088 }
1089 sctx->do_update_shaders = true;
1090 }
1091
1092 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1093 {
1094 struct si_context *sctx = (struct si_context *)ctx;
1095 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1096 }
1097
1098 static void *si_create_db_flush_dsa(struct si_context *sctx)
1099 {
1100 struct pipe_depth_stencil_alpha_state dsa = {};
1101
1102 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1103 }
1104
1105 /* DB RENDER STATE */
1106
1107 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1108 {
1109 struct si_context *sctx = (struct si_context*)ctx;
1110
1111 /* Pipeline stat & streamout queries. */
1112 if (enable) {
1113 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1114 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1115 } else {
1116 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1117 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1118 }
1119
1120 /* Occlusion queries. */
1121 if (sctx->occlusion_queries_disabled != !enable) {
1122 sctx->occlusion_queries_disabled = !enable;
1123 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1124 }
1125 }
1126
1127 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1128 {
1129 struct si_context *sctx = (struct si_context*)ctx;
1130
1131 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1132 }
1133
1134 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1135 {
1136 struct si_context *sctx = (struct si_context*)ctx;
1137
1138 st->saved_compute = sctx->cs_shader_state.program;
1139
1140 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1141 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1142 }
1143
1144 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1145 {
1146 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1147 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1148 unsigned db_shader_control;
1149
1150 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1151
1152 /* DB_RENDER_CONTROL */
1153 if (sctx->dbcb_depth_copy_enabled ||
1154 sctx->dbcb_stencil_copy_enabled) {
1155 radeon_emit(cs,
1156 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1157 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1158 S_028000_COPY_CENTROID(1) |
1159 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1160 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1161 radeon_emit(cs,
1162 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1163 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1164 } else {
1165 radeon_emit(cs,
1166 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1167 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1168 }
1169
1170 /* DB_COUNT_CONTROL (occlusion queries) */
1171 if (sctx->b.num_occlusion_queries > 0 &&
1172 !sctx->occlusion_queries_disabled) {
1173 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1174
1175 if (sctx->b.chip_class >= CIK) {
1176 radeon_emit(cs,
1177 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1178 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1179 S_028004_ZPASS_ENABLE(1) |
1180 S_028004_SLICE_EVEN_ENABLE(1) |
1181 S_028004_SLICE_ODD_ENABLE(1));
1182 } else {
1183 radeon_emit(cs,
1184 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1185 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1186 }
1187 } else {
1188 /* Disable occlusion queries. */
1189 if (sctx->b.chip_class >= CIK) {
1190 radeon_emit(cs, 0);
1191 } else {
1192 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1193 }
1194 }
1195
1196 /* DB_RENDER_OVERRIDE2 */
1197 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1198 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1199 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1200 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1201
1202 db_shader_control = sctx->ps_db_shader_control;
1203
1204 /* Bug workaround for smoothing (overrasterization) on SI. */
1205 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1206 db_shader_control &= C_02880C_Z_ORDER;
1207 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1208 }
1209
1210 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1211 if (!rs || !rs->multisample_enable)
1212 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1213
1214 if (sctx->screen->b.has_rbplus &&
1215 !sctx->screen->b.rbplus_allowed)
1216 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1217
1218 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1219 db_shader_control);
1220 }
1221
1222 /*
1223 * format translation
1224 */
1225 static uint32_t si_translate_colorformat(enum pipe_format format)
1226 {
1227 const struct util_format_description *desc = util_format_description(format);
1228
1229 #define HAS_SIZE(x,y,z,w) \
1230 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1231 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1232
1233 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1234 return V_028C70_COLOR_10_11_11;
1235
1236 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1237 return V_028C70_COLOR_INVALID;
1238
1239 /* hw cannot support mixed formats (except depth/stencil, since
1240 * stencil is not written to). */
1241 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1242 return V_028C70_COLOR_INVALID;
1243
1244 switch (desc->nr_channels) {
1245 case 1:
1246 switch (desc->channel[0].size) {
1247 case 8:
1248 return V_028C70_COLOR_8;
1249 case 16:
1250 return V_028C70_COLOR_16;
1251 case 32:
1252 return V_028C70_COLOR_32;
1253 }
1254 break;
1255 case 2:
1256 if (desc->channel[0].size == desc->channel[1].size) {
1257 switch (desc->channel[0].size) {
1258 case 8:
1259 return V_028C70_COLOR_8_8;
1260 case 16:
1261 return V_028C70_COLOR_16_16;
1262 case 32:
1263 return V_028C70_COLOR_32_32;
1264 }
1265 } else if (HAS_SIZE(8,24,0,0)) {
1266 return V_028C70_COLOR_24_8;
1267 } else if (HAS_SIZE(24,8,0,0)) {
1268 return V_028C70_COLOR_8_24;
1269 }
1270 break;
1271 case 3:
1272 if (HAS_SIZE(5,6,5,0)) {
1273 return V_028C70_COLOR_5_6_5;
1274 } else if (HAS_SIZE(32,8,24,0)) {
1275 return V_028C70_COLOR_X24_8_32_FLOAT;
1276 }
1277 break;
1278 case 4:
1279 if (desc->channel[0].size == desc->channel[1].size &&
1280 desc->channel[0].size == desc->channel[2].size &&
1281 desc->channel[0].size == desc->channel[3].size) {
1282 switch (desc->channel[0].size) {
1283 case 4:
1284 return V_028C70_COLOR_4_4_4_4;
1285 case 8:
1286 return V_028C70_COLOR_8_8_8_8;
1287 case 16:
1288 return V_028C70_COLOR_16_16_16_16;
1289 case 32:
1290 return V_028C70_COLOR_32_32_32_32;
1291 }
1292 } else if (HAS_SIZE(5,5,5,1)) {
1293 return V_028C70_COLOR_1_5_5_5;
1294 } else if (HAS_SIZE(10,10,10,2)) {
1295 return V_028C70_COLOR_2_10_10_10;
1296 }
1297 break;
1298 }
1299 return V_028C70_COLOR_INVALID;
1300 }
1301
1302 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1303 {
1304 if (SI_BIG_ENDIAN) {
1305 switch(colorformat) {
1306 /* 8-bit buffers. */
1307 case V_028C70_COLOR_8:
1308 return V_028C70_ENDIAN_NONE;
1309
1310 /* 16-bit buffers. */
1311 case V_028C70_COLOR_5_6_5:
1312 case V_028C70_COLOR_1_5_5_5:
1313 case V_028C70_COLOR_4_4_4_4:
1314 case V_028C70_COLOR_16:
1315 case V_028C70_COLOR_8_8:
1316 return V_028C70_ENDIAN_8IN16;
1317
1318 /* 32-bit buffers. */
1319 case V_028C70_COLOR_8_8_8_8:
1320 case V_028C70_COLOR_2_10_10_10:
1321 case V_028C70_COLOR_8_24:
1322 case V_028C70_COLOR_24_8:
1323 case V_028C70_COLOR_16_16:
1324 return V_028C70_ENDIAN_8IN32;
1325
1326 /* 64-bit buffers. */
1327 case V_028C70_COLOR_16_16_16_16:
1328 return V_028C70_ENDIAN_8IN16;
1329
1330 case V_028C70_COLOR_32_32:
1331 return V_028C70_ENDIAN_8IN32;
1332
1333 /* 128-bit buffers. */
1334 case V_028C70_COLOR_32_32_32_32:
1335 return V_028C70_ENDIAN_8IN32;
1336 default:
1337 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1338 }
1339 } else {
1340 return V_028C70_ENDIAN_NONE;
1341 }
1342 }
1343
1344 static uint32_t si_translate_dbformat(enum pipe_format format)
1345 {
1346 switch (format) {
1347 case PIPE_FORMAT_Z16_UNORM:
1348 return V_028040_Z_16;
1349 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1350 case PIPE_FORMAT_X8Z24_UNORM:
1351 case PIPE_FORMAT_Z24X8_UNORM:
1352 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1353 return V_028040_Z_24; /* deprecated on SI */
1354 case PIPE_FORMAT_Z32_FLOAT:
1355 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1356 return V_028040_Z_32_FLOAT;
1357 default:
1358 return V_028040_Z_INVALID;
1359 }
1360 }
1361
1362 /*
1363 * Texture translation
1364 */
1365
1366 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1367 enum pipe_format format,
1368 const struct util_format_description *desc,
1369 int first_non_void)
1370 {
1371 struct si_screen *sscreen = (struct si_screen*)screen;
1372 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1373 sscreen->b.info.drm_minor >= 31) ||
1374 sscreen->b.info.drm_major == 3;
1375 bool uniform = true;
1376 int i;
1377
1378 /* Colorspace (return non-RGB formats directly). */
1379 switch (desc->colorspace) {
1380 /* Depth stencil formats */
1381 case UTIL_FORMAT_COLORSPACE_ZS:
1382 switch (format) {
1383 case PIPE_FORMAT_Z16_UNORM:
1384 return V_008F14_IMG_DATA_FORMAT_16;
1385 case PIPE_FORMAT_X24S8_UINT:
1386 case PIPE_FORMAT_S8X24_UINT:
1387 /*
1388 * Implemented as an 8_8_8_8 data format to fix texture
1389 * gathers in stencil sampling. This affects at least
1390 * GL45-CTS.texture_cube_map_array.sampling on VI.
1391 */
1392 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1393 case PIPE_FORMAT_Z24X8_UNORM:
1394 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1395 return V_008F14_IMG_DATA_FORMAT_8_24;
1396 case PIPE_FORMAT_X8Z24_UNORM:
1397 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1398 return V_008F14_IMG_DATA_FORMAT_24_8;
1399 case PIPE_FORMAT_S8_UINT:
1400 return V_008F14_IMG_DATA_FORMAT_8;
1401 case PIPE_FORMAT_Z32_FLOAT:
1402 return V_008F14_IMG_DATA_FORMAT_32;
1403 case PIPE_FORMAT_X32_S8X24_UINT:
1404 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1405 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1406 default:
1407 goto out_unknown;
1408 }
1409
1410 case UTIL_FORMAT_COLORSPACE_YUV:
1411 goto out_unknown; /* TODO */
1412
1413 case UTIL_FORMAT_COLORSPACE_SRGB:
1414 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1415 goto out_unknown;
1416 break;
1417
1418 default:
1419 break;
1420 }
1421
1422 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1423 if (!enable_compressed_formats)
1424 goto out_unknown;
1425
1426 switch (format) {
1427 case PIPE_FORMAT_RGTC1_SNORM:
1428 case PIPE_FORMAT_LATC1_SNORM:
1429 case PIPE_FORMAT_RGTC1_UNORM:
1430 case PIPE_FORMAT_LATC1_UNORM:
1431 return V_008F14_IMG_DATA_FORMAT_BC4;
1432 case PIPE_FORMAT_RGTC2_SNORM:
1433 case PIPE_FORMAT_LATC2_SNORM:
1434 case PIPE_FORMAT_RGTC2_UNORM:
1435 case PIPE_FORMAT_LATC2_UNORM:
1436 return V_008F14_IMG_DATA_FORMAT_BC5;
1437 default:
1438 goto out_unknown;
1439 }
1440 }
1441
1442 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1443 (sscreen->b.family == CHIP_STONEY ||
1444 sscreen->b.chip_class >= GFX9)) {
1445 switch (format) {
1446 case PIPE_FORMAT_ETC1_RGB8:
1447 case PIPE_FORMAT_ETC2_RGB8:
1448 case PIPE_FORMAT_ETC2_SRGB8:
1449 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1450 case PIPE_FORMAT_ETC2_RGB8A1:
1451 case PIPE_FORMAT_ETC2_SRGB8A1:
1452 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1453 case PIPE_FORMAT_ETC2_RGBA8:
1454 case PIPE_FORMAT_ETC2_SRGBA8:
1455 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1456 case PIPE_FORMAT_ETC2_R11_UNORM:
1457 case PIPE_FORMAT_ETC2_R11_SNORM:
1458 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1459 case PIPE_FORMAT_ETC2_RG11_UNORM:
1460 case PIPE_FORMAT_ETC2_RG11_SNORM:
1461 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1462 default:
1463 goto out_unknown;
1464 }
1465 }
1466
1467 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1468 if (!enable_compressed_formats)
1469 goto out_unknown;
1470
1471 switch (format) {
1472 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1473 case PIPE_FORMAT_BPTC_SRGBA:
1474 return V_008F14_IMG_DATA_FORMAT_BC7;
1475 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1476 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1477 return V_008F14_IMG_DATA_FORMAT_BC6;
1478 default:
1479 goto out_unknown;
1480 }
1481 }
1482
1483 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1484 switch (format) {
1485 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1486 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1487 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1488 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1489 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1490 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1491 default:
1492 goto out_unknown;
1493 }
1494 }
1495
1496 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1497 if (!enable_compressed_formats)
1498 goto out_unknown;
1499
1500 if (!util_format_s3tc_enabled) {
1501 goto out_unknown;
1502 }
1503
1504 switch (format) {
1505 case PIPE_FORMAT_DXT1_RGB:
1506 case PIPE_FORMAT_DXT1_RGBA:
1507 case PIPE_FORMAT_DXT1_SRGB:
1508 case PIPE_FORMAT_DXT1_SRGBA:
1509 return V_008F14_IMG_DATA_FORMAT_BC1;
1510 case PIPE_FORMAT_DXT3_RGBA:
1511 case PIPE_FORMAT_DXT3_SRGBA:
1512 return V_008F14_IMG_DATA_FORMAT_BC2;
1513 case PIPE_FORMAT_DXT5_RGBA:
1514 case PIPE_FORMAT_DXT5_SRGBA:
1515 return V_008F14_IMG_DATA_FORMAT_BC3;
1516 default:
1517 goto out_unknown;
1518 }
1519 }
1520
1521 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1522 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1523 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1524 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1525 }
1526
1527 /* R8G8Bx_SNORM - TODO CxV8U8 */
1528
1529 /* hw cannot support mixed formats (except depth/stencil, since only
1530 * depth is read).*/
1531 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1532 goto out_unknown;
1533
1534 /* See whether the components are of the same size. */
1535 for (i = 1; i < desc->nr_channels; i++) {
1536 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1537 }
1538
1539 /* Non-uniform formats. */
1540 if (!uniform) {
1541 switch(desc->nr_channels) {
1542 case 3:
1543 if (desc->channel[0].size == 5 &&
1544 desc->channel[1].size == 6 &&
1545 desc->channel[2].size == 5) {
1546 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1547 }
1548 goto out_unknown;
1549 case 4:
1550 if (desc->channel[0].size == 5 &&
1551 desc->channel[1].size == 5 &&
1552 desc->channel[2].size == 5 &&
1553 desc->channel[3].size == 1) {
1554 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1555 }
1556 if (desc->channel[0].size == 10 &&
1557 desc->channel[1].size == 10 &&
1558 desc->channel[2].size == 10 &&
1559 desc->channel[3].size == 2) {
1560 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1561 }
1562 goto out_unknown;
1563 }
1564 goto out_unknown;
1565 }
1566
1567 if (first_non_void < 0 || first_non_void > 3)
1568 goto out_unknown;
1569
1570 /* uniform formats */
1571 switch (desc->channel[first_non_void].size) {
1572 case 4:
1573 switch (desc->nr_channels) {
1574 #if 0 /* Not supported for render targets */
1575 case 2:
1576 return V_008F14_IMG_DATA_FORMAT_4_4;
1577 #endif
1578 case 4:
1579 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1580 }
1581 break;
1582 case 8:
1583 switch (desc->nr_channels) {
1584 case 1:
1585 return V_008F14_IMG_DATA_FORMAT_8;
1586 case 2:
1587 return V_008F14_IMG_DATA_FORMAT_8_8;
1588 case 4:
1589 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1590 }
1591 break;
1592 case 16:
1593 switch (desc->nr_channels) {
1594 case 1:
1595 return V_008F14_IMG_DATA_FORMAT_16;
1596 case 2:
1597 return V_008F14_IMG_DATA_FORMAT_16_16;
1598 case 4:
1599 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1600 }
1601 break;
1602 case 32:
1603 switch (desc->nr_channels) {
1604 case 1:
1605 return V_008F14_IMG_DATA_FORMAT_32;
1606 case 2:
1607 return V_008F14_IMG_DATA_FORMAT_32_32;
1608 #if 0 /* Not supported for render targets */
1609 case 3:
1610 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1611 #endif
1612 case 4:
1613 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1614 }
1615 }
1616
1617 out_unknown:
1618 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1619 return ~0;
1620 }
1621
1622 static unsigned si_tex_wrap(unsigned wrap)
1623 {
1624 switch (wrap) {
1625 default:
1626 case PIPE_TEX_WRAP_REPEAT:
1627 return V_008F30_SQ_TEX_WRAP;
1628 case PIPE_TEX_WRAP_CLAMP:
1629 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1630 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1631 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1632 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1633 return V_008F30_SQ_TEX_CLAMP_BORDER;
1634 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1635 return V_008F30_SQ_TEX_MIRROR;
1636 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1637 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1638 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1639 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1640 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1641 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1642 }
1643 }
1644
1645 static unsigned si_tex_mipfilter(unsigned filter)
1646 {
1647 switch (filter) {
1648 case PIPE_TEX_MIPFILTER_NEAREST:
1649 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1650 case PIPE_TEX_MIPFILTER_LINEAR:
1651 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1652 default:
1653 case PIPE_TEX_MIPFILTER_NONE:
1654 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1655 }
1656 }
1657
1658 static unsigned si_tex_compare(unsigned compare)
1659 {
1660 switch (compare) {
1661 default:
1662 case PIPE_FUNC_NEVER:
1663 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1664 case PIPE_FUNC_LESS:
1665 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1666 case PIPE_FUNC_EQUAL:
1667 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1668 case PIPE_FUNC_LEQUAL:
1669 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1670 case PIPE_FUNC_GREATER:
1671 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1672 case PIPE_FUNC_NOTEQUAL:
1673 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1674 case PIPE_FUNC_GEQUAL:
1675 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1676 case PIPE_FUNC_ALWAYS:
1677 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1678 }
1679 }
1680
1681 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1682 unsigned view_target, unsigned nr_samples)
1683 {
1684 unsigned res_target = rtex->resource.b.b.target;
1685
1686 if (view_target == PIPE_TEXTURE_CUBE ||
1687 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1688 res_target = view_target;
1689 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1690 else if (res_target == PIPE_TEXTURE_CUBE ||
1691 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1692 res_target = PIPE_TEXTURE_2D_ARRAY;
1693
1694 /* GFX9 allocates 1D textures as 2D. */
1695 if ((res_target == PIPE_TEXTURE_1D ||
1696 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1697 sscreen->b.chip_class >= GFX9 &&
1698 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1699 if (res_target == PIPE_TEXTURE_1D)
1700 res_target = PIPE_TEXTURE_2D;
1701 else
1702 res_target = PIPE_TEXTURE_2D_ARRAY;
1703 }
1704
1705 switch (res_target) {
1706 default:
1707 case PIPE_TEXTURE_1D:
1708 return V_008F1C_SQ_RSRC_IMG_1D;
1709 case PIPE_TEXTURE_1D_ARRAY:
1710 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1711 case PIPE_TEXTURE_2D:
1712 case PIPE_TEXTURE_RECT:
1713 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1714 V_008F1C_SQ_RSRC_IMG_2D;
1715 case PIPE_TEXTURE_2D_ARRAY:
1716 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1717 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1718 case PIPE_TEXTURE_3D:
1719 return V_008F1C_SQ_RSRC_IMG_3D;
1720 case PIPE_TEXTURE_CUBE:
1721 case PIPE_TEXTURE_CUBE_ARRAY:
1722 return V_008F1C_SQ_RSRC_IMG_CUBE;
1723 }
1724 }
1725
1726 /*
1727 * Format support testing
1728 */
1729
1730 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1731 {
1732 return si_translate_texformat(screen, format, util_format_description(format),
1733 util_format_get_first_non_void_channel(format)) != ~0U;
1734 }
1735
1736 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1737 const struct util_format_description *desc,
1738 int first_non_void)
1739 {
1740 int i;
1741
1742 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1743 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1744
1745 assert(first_non_void >= 0);
1746
1747 if (desc->nr_channels == 4 &&
1748 desc->channel[0].size == 10 &&
1749 desc->channel[1].size == 10 &&
1750 desc->channel[2].size == 10 &&
1751 desc->channel[3].size == 2)
1752 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1753
1754 /* See whether the components are of the same size. */
1755 for (i = 0; i < desc->nr_channels; i++) {
1756 if (desc->channel[first_non_void].size != desc->channel[i].size)
1757 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1758 }
1759
1760 switch (desc->channel[first_non_void].size) {
1761 case 8:
1762 switch (desc->nr_channels) {
1763 case 1:
1764 case 3: /* 3 loads */
1765 return V_008F0C_BUF_DATA_FORMAT_8;
1766 case 2:
1767 return V_008F0C_BUF_DATA_FORMAT_8_8;
1768 case 4:
1769 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1770 }
1771 break;
1772 case 16:
1773 switch (desc->nr_channels) {
1774 case 1:
1775 case 3: /* 3 loads */
1776 return V_008F0C_BUF_DATA_FORMAT_16;
1777 case 2:
1778 return V_008F0C_BUF_DATA_FORMAT_16_16;
1779 case 4:
1780 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1781 }
1782 break;
1783 case 32:
1784 switch (desc->nr_channels) {
1785 case 1:
1786 return V_008F0C_BUF_DATA_FORMAT_32;
1787 case 2:
1788 return V_008F0C_BUF_DATA_FORMAT_32_32;
1789 case 3:
1790 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1791 case 4:
1792 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1793 }
1794 break;
1795 case 64:
1796 /* Legacy double formats. */
1797 switch (desc->nr_channels) {
1798 case 1: /* 1 load */
1799 return V_008F0C_BUF_DATA_FORMAT_32_32;
1800 case 2: /* 1 load */
1801 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1802 case 3: /* 3 loads */
1803 return V_008F0C_BUF_DATA_FORMAT_32_32;
1804 case 4: /* 2 loads */
1805 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1806 }
1807 break;
1808 }
1809
1810 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1811 }
1812
1813 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1814 const struct util_format_description *desc,
1815 int first_non_void)
1816 {
1817 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1818 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1819
1820 assert(first_non_void >= 0);
1821
1822 switch (desc->channel[first_non_void].type) {
1823 case UTIL_FORMAT_TYPE_SIGNED:
1824 case UTIL_FORMAT_TYPE_FIXED:
1825 if (desc->channel[first_non_void].size >= 32 ||
1826 desc->channel[first_non_void].pure_integer)
1827 return V_008F0C_BUF_NUM_FORMAT_SINT;
1828 else if (desc->channel[first_non_void].normalized)
1829 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1830 else
1831 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1832 break;
1833 case UTIL_FORMAT_TYPE_UNSIGNED:
1834 if (desc->channel[first_non_void].size >= 32 ||
1835 desc->channel[first_non_void].pure_integer)
1836 return V_008F0C_BUF_NUM_FORMAT_UINT;
1837 else if (desc->channel[first_non_void].normalized)
1838 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1839 else
1840 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1841 break;
1842 case UTIL_FORMAT_TYPE_FLOAT:
1843 default:
1844 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1845 }
1846 }
1847
1848 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1849 enum pipe_format format,
1850 unsigned usage)
1851 {
1852 const struct util_format_description *desc;
1853 int first_non_void;
1854 unsigned data_format;
1855
1856 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1857 PIPE_BIND_SAMPLER_VIEW |
1858 PIPE_BIND_VERTEX_BUFFER)) == 0);
1859
1860 desc = util_format_description(format);
1861
1862 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1863 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1864 * for read-only access (with caveats surrounding bounds checks), but
1865 * obviously fails for write access which we have to implement for
1866 * shader images. Luckily, OpenGL doesn't expect this to be supported
1867 * anyway, and so the only impact is on PBO uploads / downloads, which
1868 * shouldn't be expected to be fast for GL_RGB anyway.
1869 */
1870 if (desc->block.bits == 3 * 8 ||
1871 desc->block.bits == 3 * 16) {
1872 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1873 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1874 if (!usage)
1875 return 0;
1876 }
1877 }
1878
1879 first_non_void = util_format_get_first_non_void_channel(format);
1880 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1881 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1882 return 0;
1883
1884 return usage;
1885 }
1886
1887 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1888 {
1889 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1890 r600_translate_colorswap(format, false) != ~0U;
1891 }
1892
1893 static bool si_is_zs_format_supported(enum pipe_format format)
1894 {
1895 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1896 }
1897
1898 static boolean si_is_format_supported(struct pipe_screen *screen,
1899 enum pipe_format format,
1900 enum pipe_texture_target target,
1901 unsigned sample_count,
1902 unsigned usage)
1903 {
1904 unsigned retval = 0;
1905
1906 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1907 R600_ERR("r600: unsupported texture type %d\n", target);
1908 return false;
1909 }
1910
1911 if (!util_format_is_supported(format, usage))
1912 return false;
1913
1914 if (sample_count > 1) {
1915 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1916 return false;
1917
1918 if (usage & PIPE_BIND_SHADER_IMAGE)
1919 return false;
1920
1921 switch (sample_count) {
1922 case 2:
1923 case 4:
1924 case 8:
1925 break;
1926 case 16:
1927 if (format == PIPE_FORMAT_NONE)
1928 return true;
1929 else
1930 return false;
1931 default:
1932 return false;
1933 }
1934 }
1935
1936 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1937 PIPE_BIND_SHADER_IMAGE)) {
1938 if (target == PIPE_BUFFER) {
1939 retval |= si_is_vertex_format_supported(
1940 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1941 PIPE_BIND_SHADER_IMAGE));
1942 } else {
1943 if (si_is_sampler_format_supported(screen, format))
1944 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1945 PIPE_BIND_SHADER_IMAGE);
1946 }
1947 }
1948
1949 if ((usage & (PIPE_BIND_RENDER_TARGET |
1950 PIPE_BIND_DISPLAY_TARGET |
1951 PIPE_BIND_SCANOUT |
1952 PIPE_BIND_SHARED |
1953 PIPE_BIND_BLENDABLE)) &&
1954 si_is_colorbuffer_format_supported(format)) {
1955 retval |= usage &
1956 (PIPE_BIND_RENDER_TARGET |
1957 PIPE_BIND_DISPLAY_TARGET |
1958 PIPE_BIND_SCANOUT |
1959 PIPE_BIND_SHARED);
1960 if (!util_format_is_pure_integer(format) &&
1961 !util_format_is_depth_or_stencil(format))
1962 retval |= usage & PIPE_BIND_BLENDABLE;
1963 }
1964
1965 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1966 si_is_zs_format_supported(format)) {
1967 retval |= PIPE_BIND_DEPTH_STENCIL;
1968 }
1969
1970 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1971 retval |= si_is_vertex_format_supported(screen, format,
1972 PIPE_BIND_VERTEX_BUFFER);
1973 }
1974
1975 if ((usage & PIPE_BIND_LINEAR) &&
1976 !util_format_is_compressed(format) &&
1977 !(usage & PIPE_BIND_DEPTH_STENCIL))
1978 retval |= PIPE_BIND_LINEAR;
1979
1980 return retval == usage;
1981 }
1982
1983 /*
1984 * framebuffer handling
1985 */
1986
1987 static void si_choose_spi_color_formats(struct r600_surface *surf,
1988 unsigned format, unsigned swap,
1989 unsigned ntype, bool is_depth)
1990 {
1991 /* Alpha is needed for alpha-to-coverage.
1992 * Blending may be with or without alpha.
1993 */
1994 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1995 unsigned alpha = 0; /* exports alpha, but may not support blending */
1996 unsigned blend = 0; /* supports blending, but may not export alpha */
1997 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1998
1999 /* Choose the SPI color formats. These are required values for RB+.
2000 * Other chips have multiple choices, though they are not necessarily better.
2001 */
2002 switch (format) {
2003 case V_028C70_COLOR_5_6_5:
2004 case V_028C70_COLOR_1_5_5_5:
2005 case V_028C70_COLOR_5_5_5_1:
2006 case V_028C70_COLOR_4_4_4_4:
2007 case V_028C70_COLOR_10_11_11:
2008 case V_028C70_COLOR_11_11_10:
2009 case V_028C70_COLOR_8:
2010 case V_028C70_COLOR_8_8:
2011 case V_028C70_COLOR_8_8_8_8:
2012 case V_028C70_COLOR_10_10_10_2:
2013 case V_028C70_COLOR_2_10_10_10:
2014 if (ntype == V_028C70_NUMBER_UINT)
2015 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2016 else if (ntype == V_028C70_NUMBER_SINT)
2017 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2018 else
2019 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2020 break;
2021
2022 case V_028C70_COLOR_16:
2023 case V_028C70_COLOR_16_16:
2024 case V_028C70_COLOR_16_16_16_16:
2025 if (ntype == V_028C70_NUMBER_UNORM ||
2026 ntype == V_028C70_NUMBER_SNORM) {
2027 /* UNORM16 and SNORM16 don't support blending */
2028 if (ntype == V_028C70_NUMBER_UNORM)
2029 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2030 else
2031 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2032
2033 /* Use 32 bits per channel for blending. */
2034 if (format == V_028C70_COLOR_16) {
2035 if (swap == V_028C70_SWAP_STD) { /* R */
2036 blend = V_028714_SPI_SHADER_32_R;
2037 blend_alpha = V_028714_SPI_SHADER_32_AR;
2038 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2039 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2040 else
2041 assert(0);
2042 } else if (format == V_028C70_COLOR_16_16) {
2043 if (swap == V_028C70_SWAP_STD) { /* RG */
2044 blend = V_028714_SPI_SHADER_32_GR;
2045 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2046 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2047 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2048 else
2049 assert(0);
2050 } else /* 16_16_16_16 */
2051 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2052 } else if (ntype == V_028C70_NUMBER_UINT)
2053 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2054 else if (ntype == V_028C70_NUMBER_SINT)
2055 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2056 else if (ntype == V_028C70_NUMBER_FLOAT)
2057 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2058 else
2059 assert(0);
2060 break;
2061
2062 case V_028C70_COLOR_32:
2063 if (swap == V_028C70_SWAP_STD) { /* R */
2064 blend = normal = V_028714_SPI_SHADER_32_R;
2065 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2066 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2067 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2068 else
2069 assert(0);
2070 break;
2071
2072 case V_028C70_COLOR_32_32:
2073 if (swap == V_028C70_SWAP_STD) { /* RG */
2074 blend = normal = V_028714_SPI_SHADER_32_GR;
2075 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2076 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2077 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2078 else
2079 assert(0);
2080 break;
2081
2082 case V_028C70_COLOR_32_32_32_32:
2083 case V_028C70_COLOR_8_24:
2084 case V_028C70_COLOR_24_8:
2085 case V_028C70_COLOR_X24_8_32_FLOAT:
2086 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2087 break;
2088
2089 default:
2090 assert(0);
2091 return;
2092 }
2093
2094 /* The DB->CB copy needs 32_ABGR. */
2095 if (is_depth)
2096 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2097
2098 surf->spi_shader_col_format = normal;
2099 surf->spi_shader_col_format_alpha = alpha;
2100 surf->spi_shader_col_format_blend = blend;
2101 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2102 }
2103
2104 static void si_initialize_color_surface(struct si_context *sctx,
2105 struct r600_surface *surf)
2106 {
2107 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2108 unsigned color_info, color_attrib, color_view;
2109 unsigned format, swap, ntype, endian;
2110 const struct util_format_description *desc;
2111 int i;
2112 unsigned blend_clamp = 0, blend_bypass = 0;
2113
2114 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2115 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2116
2117 desc = util_format_description(surf->base.format);
2118 for (i = 0; i < 4; i++) {
2119 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2120 break;
2121 }
2122 }
2123 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2124 ntype = V_028C70_NUMBER_FLOAT;
2125 } else {
2126 ntype = V_028C70_NUMBER_UNORM;
2127 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2128 ntype = V_028C70_NUMBER_SRGB;
2129 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2130 if (desc->channel[i].pure_integer) {
2131 ntype = V_028C70_NUMBER_SINT;
2132 } else {
2133 assert(desc->channel[i].normalized);
2134 ntype = V_028C70_NUMBER_SNORM;
2135 }
2136 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2137 if (desc->channel[i].pure_integer) {
2138 ntype = V_028C70_NUMBER_UINT;
2139 } else {
2140 assert(desc->channel[i].normalized);
2141 ntype = V_028C70_NUMBER_UNORM;
2142 }
2143 }
2144 }
2145
2146 format = si_translate_colorformat(surf->base.format);
2147 if (format == V_028C70_COLOR_INVALID) {
2148 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2149 }
2150 assert(format != V_028C70_COLOR_INVALID);
2151 swap = r600_translate_colorswap(surf->base.format, false);
2152 endian = si_colorformat_endian_swap(format);
2153
2154 /* blend clamp should be set for all NORM/SRGB types */
2155 if (ntype == V_028C70_NUMBER_UNORM ||
2156 ntype == V_028C70_NUMBER_SNORM ||
2157 ntype == V_028C70_NUMBER_SRGB)
2158 blend_clamp = 1;
2159
2160 /* set blend bypass according to docs if SINT/UINT or
2161 8/24 COLOR variants */
2162 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2163 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2164 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2165 blend_clamp = 0;
2166 blend_bypass = 1;
2167 }
2168
2169 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2170 if (format == V_028C70_COLOR_8 ||
2171 format == V_028C70_COLOR_8_8 ||
2172 format == V_028C70_COLOR_8_8_8_8)
2173 surf->color_is_int8 = true;
2174 else if (format == V_028C70_COLOR_10_10_10_2 ||
2175 format == V_028C70_COLOR_2_10_10_10)
2176 surf->color_is_int10 = true;
2177 }
2178
2179 color_info = S_028C70_FORMAT(format) |
2180 S_028C70_COMP_SWAP(swap) |
2181 S_028C70_BLEND_CLAMP(blend_clamp) |
2182 S_028C70_BLEND_BYPASS(blend_bypass) |
2183 S_028C70_SIMPLE_FLOAT(1) |
2184 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2185 ntype != V_028C70_NUMBER_SNORM &&
2186 ntype != V_028C70_NUMBER_SRGB &&
2187 format != V_028C70_COLOR_8_24 &&
2188 format != V_028C70_COLOR_24_8) |
2189 S_028C70_NUMBER_TYPE(ntype) |
2190 S_028C70_ENDIAN(endian);
2191
2192 /* Intensity is implemented as Red, so treat it that way. */
2193 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2194 util_format_is_intensity(surf->base.format));
2195
2196 if (rtex->resource.b.b.nr_samples > 1) {
2197 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2198
2199 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2200 S_028C74_NUM_FRAGMENTS(log_samples);
2201
2202 if (rtex->fmask.size) {
2203 color_info |= S_028C70_COMPRESSION(1);
2204 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2205
2206 if (sctx->b.chip_class == SI) {
2207 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2208 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2209 }
2210 }
2211 }
2212
2213 surf->cb_color_view = color_view;
2214 surf->cb_color_info = color_info;
2215 surf->cb_color_attrib = color_attrib;
2216
2217 if (sctx->b.chip_class >= VI) {
2218 unsigned max_uncompressed_block_size = 2;
2219
2220 if (rtex->resource.b.b.nr_samples > 1) {
2221 if (rtex->surface.bpe == 1)
2222 max_uncompressed_block_size = 0;
2223 else if (rtex->surface.bpe == 2)
2224 max_uncompressed_block_size = 1;
2225 }
2226
2227 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2228 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2229 }
2230
2231 /* This must be set for fast clear to work without FMASK. */
2232 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2233 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2234 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2235 }
2236
2237 if (sctx->b.chip_class >= GFX9) {
2238 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2239
2240 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2241 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2242 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2243 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2244 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2245 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2246 }
2247
2248 /* Determine pixel shader export format */
2249 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2250
2251 surf->color_initialized = true;
2252 }
2253
2254 static void si_init_depth_surface(struct si_context *sctx,
2255 struct r600_surface *surf)
2256 {
2257 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2258 unsigned level = surf->base.u.tex.level;
2259 unsigned format, stencil_format;
2260 uint32_t z_info, s_info;
2261
2262 format = si_translate_dbformat(rtex->db_render_format);
2263 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2264 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2265
2266 assert(format != V_028040_Z_INVALID);
2267 if (format == V_028040_Z_INVALID)
2268 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2269
2270 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2271 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2272 surf->db_htile_data_base = 0;
2273 surf->db_htile_surface = 0;
2274
2275 if (sctx->b.chip_class >= GFX9) {
2276 assert(rtex->surface.u.gfx9.surf_offset == 0);
2277 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2278 surf->db_stencil_base = (rtex->resource.gpu_address +
2279 rtex->surface.u.gfx9.stencil_offset) >> 8;
2280 z_info = S_028038_FORMAT(format) |
2281 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2282 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2283 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2284 s_info = S_02803C_FORMAT(stencil_format) |
2285 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2286 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2287 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2288 surf->db_depth_view |= S_028008_MIPID(level);
2289 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2290 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2291
2292 /* Only use HTILE for the first level. */
2293 if (rtex->htile_buffer && !level) {
2294 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2295 S_028038_ALLOW_EXPCLEAR(1);
2296
2297 if (rtex->tc_compatible_htile) {
2298 unsigned max_zplanes = 4;
2299
2300 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2301 rtex->resource.b.b.nr_samples > 1)
2302 max_zplanes = 2;
2303
2304 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2305 S_028038_ITERATE_FLUSH(1);
2306 s_info |= S_02803C_ITERATE_FLUSH(1);
2307 }
2308
2309 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2310 /* Stencil buffer workaround ported from the SI-CI-VI code.
2311 * See that for explanation.
2312 */
2313 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2314 } else {
2315 /* Use all HTILE for depth if there's no stencil. */
2316 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2317 }
2318
2319 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2320 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2321 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2322 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2323 }
2324 } else {
2325 /* SI-CI-VI */
2326 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2327
2328 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2329
2330 surf->db_depth_base = (rtex->resource.gpu_address +
2331 rtex->surface.u.legacy.level[level].offset) >> 8;
2332 surf->db_stencil_base = (rtex->resource.gpu_address +
2333 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2334
2335 z_info = S_028040_FORMAT(format) |
2336 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2337 s_info = S_028044_FORMAT(stencil_format);
2338 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2339
2340 if (sctx->b.chip_class >= CIK) {
2341 struct radeon_info *info = &sctx->screen->b.info;
2342 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2343 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2344 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2345 unsigned tile_mode = info->si_tile_mode_array[index];
2346 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2347 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2348
2349 surf->db_depth_info |=
2350 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2351 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2352 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2353 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2354 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2355 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2356 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2357 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2358 } else {
2359 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2360 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2361 tile_mode_index = si_tile_mode_index(rtex, level, true);
2362 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2363 }
2364
2365 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2366 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2367 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2368 levelinfo->nblk_y) / 64 - 1);
2369
2370 /* Only use HTILE for the first level. */
2371 if (rtex->htile_buffer && !level) {
2372 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2373 S_028040_ALLOW_EXPCLEAR(1);
2374
2375 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2376 /* Workaround: For a not yet understood reason, the
2377 * combination of MSAA, fast stencil clear and stencil
2378 * decompress messes with subsequent stencil buffer
2379 * uses. Problem was reproduced on Verde, Bonaire,
2380 * Tonga, and Carrizo.
2381 *
2382 * Disabling EXPCLEAR works around the problem.
2383 *
2384 * Check piglit's arb_texture_multisample-stencil-clear
2385 * test if you want to try changing this.
2386 */
2387 if (rtex->resource.b.b.nr_samples <= 1)
2388 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2389 } else if (!rtex->tc_compatible_htile) {
2390 /* Use all of the htile_buffer for depth if there's no stencil.
2391 * This must not be set when TC-compatible HTILE is enabled
2392 * due to a hw bug.
2393 */
2394 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2395 }
2396
2397 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2398 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2399
2400 if (rtex->tc_compatible_htile) {
2401 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2402
2403 if (rtex->resource.b.b.nr_samples <= 1)
2404 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2405 else if (rtex->resource.b.b.nr_samples <= 4)
2406 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2407 else
2408 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2409 }
2410 }
2411 }
2412
2413 surf->db_z_info = z_info;
2414 surf->db_stencil_info = s_info;
2415
2416 surf->depth_initialized = true;
2417 }
2418
2419 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2420 {
2421 for (int i = 0; i < state->nr_cbufs; ++i) {
2422 struct r600_surface *surf = NULL;
2423 struct r600_texture *rtex;
2424
2425 if (!state->cbufs[i])
2426 continue;
2427 surf = (struct r600_surface*)state->cbufs[i];
2428 rtex = (struct r600_texture*)surf->base.texture;
2429
2430 p_atomic_dec(&rtex->framebuffers_bound);
2431 }
2432 }
2433
2434 static void si_set_framebuffer_state(struct pipe_context *ctx,
2435 const struct pipe_framebuffer_state *state)
2436 {
2437 struct si_context *sctx = (struct si_context *)ctx;
2438 struct pipe_constant_buffer constbuf = {0};
2439 struct r600_surface *surf = NULL;
2440 struct r600_texture *rtex;
2441 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2442 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2443 bool unbound = false;
2444 int i;
2445
2446 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2447 if (!sctx->framebuffer.state.cbufs[i])
2448 continue;
2449
2450 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2451 if (rtex->dcc_gather_statistics)
2452 vi_separate_dcc_stop_query(ctx, rtex);
2453 }
2454
2455 /* Disable DCC if the formats are incompatible. */
2456 for (i = 0; i < state->nr_cbufs; i++) {
2457 if (!state->cbufs[i])
2458 continue;
2459
2460 surf = (struct r600_surface*)state->cbufs[i];
2461 rtex = (struct r600_texture*)surf->base.texture;
2462
2463 if (!surf->dcc_incompatible)
2464 continue;
2465
2466 /* Since the DCC decompression calls back into set_framebuffer-
2467 * _state, we need to unbind the framebuffer, so that
2468 * vi_separate_dcc_stop_query isn't called twice with the same
2469 * color buffer.
2470 */
2471 if (!unbound) {
2472 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2473 unbound = true;
2474 }
2475
2476 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2477 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2478 sctx->b.decompress_dcc(ctx, rtex);
2479
2480 surf->dcc_incompatible = false;
2481 }
2482
2483 /* Only flush TC when changing the framebuffer state, because
2484 * the only client not using TC that can change textures is
2485 * the framebuffer.
2486 *
2487 * Flush all CB and DB caches here because all buffers can be used
2488 * for write by both TC (with shader image stores) and CB/DB.
2489 */
2490 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2491 SI_CONTEXT_INV_GLOBAL_L2 |
2492 SI_CONTEXT_FLUSH_AND_INV_CB |
2493 SI_CONTEXT_FLUSH_AND_INV_DB |
2494 SI_CONTEXT_CS_PARTIAL_FLUSH;
2495
2496 /* Take the maximum of the old and new count. If the new count is lower,
2497 * dirtying is needed to disable the unbound colorbuffers.
2498 */
2499 sctx->framebuffer.dirty_cbufs |=
2500 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2501 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2502
2503 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2504 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2505
2506 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2507 sctx->framebuffer.spi_shader_col_format = 0;
2508 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2509 sctx->framebuffer.spi_shader_col_format_blend = 0;
2510 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2511 sctx->framebuffer.color_is_int8 = 0;
2512 sctx->framebuffer.color_is_int10 = 0;
2513
2514 sctx->framebuffer.compressed_cb_mask = 0;
2515 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2516 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2517 sctx->framebuffer.any_dst_linear = false;
2518
2519 for (i = 0; i < state->nr_cbufs; i++) {
2520 if (!state->cbufs[i])
2521 continue;
2522
2523 surf = (struct r600_surface*)state->cbufs[i];
2524 rtex = (struct r600_texture*)surf->base.texture;
2525
2526 if (!surf->color_initialized) {
2527 si_initialize_color_surface(sctx, surf);
2528 }
2529
2530 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2531 sctx->framebuffer.spi_shader_col_format |=
2532 surf->spi_shader_col_format << (i * 4);
2533 sctx->framebuffer.spi_shader_col_format_alpha |=
2534 surf->spi_shader_col_format_alpha << (i * 4);
2535 sctx->framebuffer.spi_shader_col_format_blend |=
2536 surf->spi_shader_col_format_blend << (i * 4);
2537 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2538 surf->spi_shader_col_format_blend_alpha << (i * 4);
2539
2540 if (surf->color_is_int8)
2541 sctx->framebuffer.color_is_int8 |= 1 << i;
2542 if (surf->color_is_int10)
2543 sctx->framebuffer.color_is_int10 |= 1 << i;
2544
2545 if (rtex->fmask.size) {
2546 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2547 }
2548
2549 if (rtex->surface.is_linear)
2550 sctx->framebuffer.any_dst_linear = true;
2551
2552 r600_context_add_resource_size(ctx, surf->base.texture);
2553
2554 p_atomic_inc(&rtex->framebuffers_bound);
2555
2556 if (rtex->dcc_gather_statistics) {
2557 /* Dirty tracking must be enabled for DCC usage analysis. */
2558 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2559 vi_separate_dcc_start_query(ctx, rtex);
2560 }
2561 }
2562
2563 if (state->zsbuf) {
2564 surf = (struct r600_surface*)state->zsbuf;
2565 rtex = (struct r600_texture*)surf->base.texture;
2566
2567 if (!surf->depth_initialized) {
2568 si_init_depth_surface(sctx, surf);
2569 }
2570 r600_context_add_resource_size(ctx, surf->base.texture);
2571 }
2572
2573 si_update_poly_offset_state(sctx);
2574 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2575 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2576
2577 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2578 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2579
2580 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2581 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2582 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2583
2584 /* Set sample locations as fragment shader constants. */
2585 switch (sctx->framebuffer.nr_samples) {
2586 case 1:
2587 constbuf.user_buffer = sctx->b.sample_locations_1x;
2588 break;
2589 case 2:
2590 constbuf.user_buffer = sctx->b.sample_locations_2x;
2591 break;
2592 case 4:
2593 constbuf.user_buffer = sctx->b.sample_locations_4x;
2594 break;
2595 case 8:
2596 constbuf.user_buffer = sctx->b.sample_locations_8x;
2597 break;
2598 case 16:
2599 constbuf.user_buffer = sctx->b.sample_locations_16x;
2600 break;
2601 default:
2602 R600_ERR("Requested an invalid number of samples %i.\n",
2603 sctx->framebuffer.nr_samples);
2604 assert(0);
2605 }
2606 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2607 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2608
2609 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2610 }
2611
2612 sctx->need_check_render_feedback = true;
2613 sctx->do_update_shaders = true;
2614 sctx->framebuffer.do_update_surf_dirtiness = true;
2615 }
2616
2617 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2618 {
2619 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2620 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2621 unsigned i, nr_cbufs = state->nr_cbufs;
2622 struct r600_texture *tex = NULL;
2623 struct r600_surface *cb = NULL;
2624 unsigned cb_color_info = 0;
2625
2626 /* Colorbuffers. */
2627 for (i = 0; i < nr_cbufs; i++) {
2628 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2629 unsigned cb_color_attrib;
2630
2631 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2632 continue;
2633
2634 cb = (struct r600_surface*)state->cbufs[i];
2635 if (!cb) {
2636 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2637 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2638 continue;
2639 }
2640
2641 tex = (struct r600_texture *)cb->base.texture;
2642 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2643 &tex->resource, RADEON_USAGE_READWRITE,
2644 tex->resource.b.b.nr_samples > 1 ?
2645 RADEON_PRIO_COLOR_BUFFER_MSAA :
2646 RADEON_PRIO_COLOR_BUFFER);
2647
2648 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2649 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2650 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2651 RADEON_PRIO_CMASK);
2652 }
2653
2654 if (tex->dcc_separate_buffer)
2655 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2656 tex->dcc_separate_buffer,
2657 RADEON_USAGE_READWRITE,
2658 RADEON_PRIO_DCC);
2659
2660 /* Compute mutable surface parameters. */
2661 cb_color_base = tex->resource.gpu_address >> 8;
2662 cb_color_fmask = cb_color_base;
2663 cb_dcc_base = 0;
2664 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2665 cb_color_attrib = cb->cb_color_attrib;
2666
2667 if (tex->fmask.size)
2668 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2669
2670 /* Set up DCC. */
2671 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2672 bool is_msaa_resolve_dst = state->cbufs[0] &&
2673 state->cbufs[0]->texture->nr_samples > 1 &&
2674 state->cbufs[1] == &cb->base &&
2675 state->cbufs[1]->texture->nr_samples <= 1;
2676
2677 if (!is_msaa_resolve_dst)
2678 cb_color_info |= S_028C70_DCC_ENABLE(1);
2679
2680 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2681 tex->dcc_offset) >> 8;
2682 }
2683
2684 if (sctx->b.chip_class >= GFX9) {
2685 struct gfx9_surf_meta_flags meta;
2686
2687 if (tex->dcc_offset)
2688 meta = tex->surface.u.gfx9.dcc;
2689 else
2690 meta = tex->surface.u.gfx9.cmask;
2691
2692 /* Set mutable surface parameters. */
2693 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2694 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2695 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2696 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2697 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2698
2699 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2700 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2701 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2702 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2703 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2704 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2705 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2706 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2707 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2708 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2709 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2710 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2711 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2712 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2713 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2714 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2715
2716 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2717 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2718 } else {
2719 /* Compute mutable surface parameters (SI-CI-VI). */
2720 const struct legacy_surf_level *level_info =
2721 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2722 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2723 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2724
2725 cb_color_base += level_info->offset >> 8;
2726 if (cb_dcc_base)
2727 cb_dcc_base += level_info->dcc_offset >> 8;
2728
2729 pitch_tile_max = level_info->nblk_x / 8 - 1;
2730 slice_tile_max = level_info->nblk_x *
2731 level_info->nblk_y / 64 - 1;
2732 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2733
2734 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2735 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2736 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2737
2738 if (tex->fmask.size) {
2739 if (sctx->b.chip_class >= CIK)
2740 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2741 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2742 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2743 } else {
2744 /* This must be set for fast clear to work without FMASK. */
2745 if (sctx->b.chip_class >= CIK)
2746 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2747 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2748 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2749 }
2750
2751 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2752 sctx->b.chip_class >= VI ? 14 : 13);
2753 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2754 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2755 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2756 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2757 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2758 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2759 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2760 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2761 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2762 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2763 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2764 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2765 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2766
2767 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2768 radeon_emit(cs, cb_dcc_base);
2769 }
2770 }
2771 for (; i < 8 ; i++)
2772 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2773 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2774
2775 /* ZS buffer. */
2776 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2777 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2778 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2779
2780 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2781 &rtex->resource, RADEON_USAGE_READWRITE,
2782 zb->base.texture->nr_samples > 1 ?
2783 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2784 RADEON_PRIO_DEPTH_BUFFER);
2785
2786 if (zb->db_htile_data_base) {
2787 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2788 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2789 RADEON_PRIO_HTILE);
2790 }
2791
2792 if (sctx->b.chip_class >= GFX9) {
2793 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2794 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2795 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2796 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2797
2798 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2799 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2800 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2801 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2802 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2803 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2804 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2805 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2806 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2807 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2808 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2809 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2810
2811 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2812 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2813 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2814 } else {
2815 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2816
2817 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2818 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2819 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2820 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2821 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2822 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2823 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2824 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2825 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2826 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2827 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2828 }
2829
2830 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2831 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2832 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2833
2834 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2835 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2836 } else if (sctx->framebuffer.dirty_zsbuf) {
2837 if (sctx->b.chip_class >= GFX9)
2838 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2839 else
2840 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2841
2842 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2843 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2844 }
2845
2846 /* Framebuffer dimensions. */
2847 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2848 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2849 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2850
2851 if (sctx->b.chip_class >= GFX9) {
2852 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2853 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2854 }
2855
2856 sctx->framebuffer.dirty_cbufs = 0;
2857 sctx->framebuffer.dirty_zsbuf = false;
2858 }
2859
2860 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2861 struct r600_atom *atom)
2862 {
2863 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2864 unsigned nr_samples = sctx->framebuffer.nr_samples;
2865 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2866
2867 /* Smoothing (only possible with nr_samples == 1) uses the same
2868 * sample locations as the MSAA it simulates.
2869 */
2870 if (nr_samples <= 1 && sctx->smoothing_enabled)
2871 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2872
2873 /* On Polaris, the small primitive filter uses the sample locations
2874 * even when MSAA is off, so we need to make sure they're set to 0.
2875 */
2876 if (has_msaa_sample_loc_bug)
2877 nr_samples = MAX2(nr_samples, 1);
2878
2879 if (nr_samples >= 1 &&
2880 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2881 sctx->msaa_sample_locs.nr_samples = nr_samples;
2882 cayman_emit_msaa_sample_locs(cs, nr_samples);
2883 }
2884
2885 if (sctx->b.family >= CHIP_POLARIS10) {
2886 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2887 unsigned small_prim_filter_cntl =
2888 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2889 /* line bug */
2890 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2891
2892 /* The alternative of setting sample locations to 0 would
2893 * require a DB flush to avoid Z errors, see
2894 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2895 */
2896 if (has_msaa_sample_loc_bug &&
2897 sctx->framebuffer.nr_samples > 1 &&
2898 rs && !rs->multisample_enable)
2899 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2900
2901 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2902 small_prim_filter_cntl);
2903 }
2904 }
2905
2906 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2907 {
2908 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2909 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2910 /* 33% faster rendering to linear color buffers */
2911 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2912 unsigned sc_mode_cntl_1 =
2913 S_028A4C_WALK_SIZE(dst_is_linear) |
2914 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2915 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2916 /* always 1: */
2917 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2918 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2919 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2920 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2921 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2922 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2923
2924 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2925 sctx->ps_iter_samples,
2926 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2927 sc_mode_cntl_1);
2928
2929 /* GFX9: Flush DFSM when the AA mode changes. */
2930 if (sctx->b.chip_class >= GFX9) {
2931 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2932 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2933 }
2934 }
2935
2936 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2937 {
2938 struct si_context *sctx = (struct si_context *)ctx;
2939
2940 if (sctx->ps_iter_samples == min_samples)
2941 return;
2942
2943 sctx->ps_iter_samples = min_samples;
2944 sctx->do_update_shaders = true;
2945
2946 if (sctx->framebuffer.nr_samples > 1)
2947 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2948 }
2949
2950 /*
2951 * Samplers
2952 */
2953
2954 /**
2955 * Build the sampler view descriptor for a buffer texture.
2956 * @param state 256-bit descriptor; only the high 128 bits are filled in
2957 */
2958 void
2959 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2960 enum pipe_format format,
2961 unsigned offset, unsigned size,
2962 uint32_t *state)
2963 {
2964 const struct util_format_description *desc;
2965 int first_non_void;
2966 unsigned stride;
2967 unsigned num_records;
2968 unsigned num_format, data_format;
2969
2970 desc = util_format_description(format);
2971 first_non_void = util_format_get_first_non_void_channel(format);
2972 stride = desc->block.bits / 8;
2973 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2974 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2975
2976 num_records = size / stride;
2977 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2978
2979 if (screen->b.chip_class == VI)
2980 num_records *= stride;
2981
2982 state[4] = 0;
2983 state[5] = S_008F04_STRIDE(stride);
2984 state[6] = num_records;
2985 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2986 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2987 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2988 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2989 S_008F0C_NUM_FORMAT(num_format) |
2990 S_008F0C_DATA_FORMAT(data_format);
2991 }
2992
2993 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
2994 {
2995 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2996
2997 if (swizzle[3] == PIPE_SWIZZLE_X) {
2998 /* For the pre-defined border color values (white, opaque
2999 * black, transparent black), the only thing that matters is
3000 * that the alpha channel winds up in the correct place
3001 * (because the RGB channels are all the same) so either of
3002 * these enumerations will work.
3003 */
3004 if (swizzle[2] == PIPE_SWIZZLE_Y)
3005 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3006 else
3007 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3008 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3009 if (swizzle[1] == PIPE_SWIZZLE_Y)
3010 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3011 else
3012 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3013 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3014 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3015 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3016 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3017 }
3018
3019 return bc_swizzle;
3020 }
3021
3022 /**
3023 * Build the sampler view descriptor for a texture.
3024 */
3025 void
3026 si_make_texture_descriptor(struct si_screen *screen,
3027 struct r600_texture *tex,
3028 bool sampler,
3029 enum pipe_texture_target target,
3030 enum pipe_format pipe_format,
3031 const unsigned char state_swizzle[4],
3032 unsigned first_level, unsigned last_level,
3033 unsigned first_layer, unsigned last_layer,
3034 unsigned width, unsigned height, unsigned depth,
3035 uint32_t *state,
3036 uint32_t *fmask_state)
3037 {
3038 struct pipe_resource *res = &tex->resource.b.b;
3039 const struct util_format_description *base_desc, *desc;
3040 unsigned char swizzle[4];
3041 int first_non_void;
3042 unsigned num_format, data_format, type;
3043 uint64_t va;
3044
3045 desc = util_format_description(pipe_format);
3046 base_desc = util_format_description(res->format);
3047
3048 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3049 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3050 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3051 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3052
3053 switch (pipe_format) {
3054 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3055 case PIPE_FORMAT_X32_S8X24_UINT:
3056 case PIPE_FORMAT_X8Z24_UNORM:
3057 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3058 break;
3059 case PIPE_FORMAT_X24S8_UINT:
3060 /*
3061 * X24S8 is implemented as an 8_8_8_8 data format, to
3062 * fix texture gathers. This affects at least
3063 * GL45-CTS.texture_cube_map_array.sampling on VI.
3064 */
3065 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3066 break;
3067 default:
3068 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3069 }
3070 } else {
3071 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3072 }
3073
3074 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3075
3076 switch (pipe_format) {
3077 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3078 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3079 break;
3080 default:
3081 if (first_non_void < 0) {
3082 if (util_format_is_compressed(pipe_format)) {
3083 switch (pipe_format) {
3084 case PIPE_FORMAT_DXT1_SRGB:
3085 case PIPE_FORMAT_DXT1_SRGBA:
3086 case PIPE_FORMAT_DXT3_SRGBA:
3087 case PIPE_FORMAT_DXT5_SRGBA:
3088 case PIPE_FORMAT_BPTC_SRGBA:
3089 case PIPE_FORMAT_ETC2_SRGB8:
3090 case PIPE_FORMAT_ETC2_SRGB8A1:
3091 case PIPE_FORMAT_ETC2_SRGBA8:
3092 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3093 break;
3094 case PIPE_FORMAT_RGTC1_SNORM:
3095 case PIPE_FORMAT_LATC1_SNORM:
3096 case PIPE_FORMAT_RGTC2_SNORM:
3097 case PIPE_FORMAT_LATC2_SNORM:
3098 case PIPE_FORMAT_ETC2_R11_SNORM:
3099 case PIPE_FORMAT_ETC2_RG11_SNORM:
3100 /* implies float, so use SNORM/UNORM to determine
3101 whether data is signed or not */
3102 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3103 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3104 break;
3105 default:
3106 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3107 break;
3108 }
3109 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3110 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3111 } else {
3112 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3113 }
3114 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3115 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3116 } else {
3117 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3118
3119 switch (desc->channel[first_non_void].type) {
3120 case UTIL_FORMAT_TYPE_FLOAT:
3121 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3122 break;
3123 case UTIL_FORMAT_TYPE_SIGNED:
3124 if (desc->channel[first_non_void].normalized)
3125 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3126 else if (desc->channel[first_non_void].pure_integer)
3127 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3128 else
3129 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3130 break;
3131 case UTIL_FORMAT_TYPE_UNSIGNED:
3132 if (desc->channel[first_non_void].normalized)
3133 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3134 else if (desc->channel[first_non_void].pure_integer)
3135 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3136 else
3137 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3138 }
3139 }
3140 }
3141
3142 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3143 if (data_format == ~0) {
3144 data_format = 0;
3145 }
3146
3147 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3148 if (screen->b.chip_class >= GFX9 &&
3149 util_format_has_depth(desc) &&
3150 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3151 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3152 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3153 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3154 }
3155
3156 if (!sampler &&
3157 (res->target == PIPE_TEXTURE_CUBE ||
3158 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3159 res->target == PIPE_TEXTURE_3D)) {
3160 /* For the purpose of shader images, treat cube maps and 3D
3161 * textures as 2D arrays. For 3D textures, the address
3162 * calculations for mipmaps are different, so we rely on the
3163 * caller to effectively disable mipmaps.
3164 */
3165 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3166
3167 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3168 } else {
3169 type = si_tex_dim(screen, tex, target, res->nr_samples);
3170 }
3171
3172 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3173 height = 1;
3174 depth = res->array_size;
3175 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3176 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3177 if (sampler || res->target != PIPE_TEXTURE_3D)
3178 depth = res->array_size;
3179 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3180 depth = res->array_size / 6;
3181
3182 state[0] = 0;
3183 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3184 S_008F14_NUM_FORMAT_GFX6(num_format));
3185 state[2] = (S_008F18_WIDTH(width - 1) |
3186 S_008F18_HEIGHT(height - 1) |
3187 S_008F18_PERF_MOD(4));
3188 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3189 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3190 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3191 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3192 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3193 0 : first_level) |
3194 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3195 util_logbase2(res->nr_samples) :
3196 last_level) |
3197 S_008F1C_TYPE(type));
3198 state[4] = 0;
3199 state[5] = S_008F24_BASE_ARRAY(first_layer);
3200 state[6] = 0;
3201 state[7] = 0;
3202
3203 if (screen->b.chip_class >= GFX9) {
3204 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3205
3206 /* Depth is the the last accessible layer on Gfx9.
3207 * The hw doesn't need to know the total number of layers.
3208 */
3209 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3210 state[4] |= S_008F20_DEPTH(depth - 1);
3211 else
3212 state[4] |= S_008F20_DEPTH(last_layer);
3213
3214 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3215 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3216 util_logbase2(res->nr_samples) :
3217 tex->resource.b.b.last_level);
3218 } else {
3219 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3220 state[4] |= S_008F20_DEPTH(depth - 1);
3221 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3222 }
3223
3224 if (tex->dcc_offset) {
3225 unsigned swap = r600_translate_colorswap(pipe_format, false);
3226
3227 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3228 } else {
3229 /* The last dword is unused by hw. The shader uses it to clear
3230 * bits in the first dword of sampler state.
3231 */
3232 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3233 if (first_level == last_level)
3234 state[7] = C_008F30_MAX_ANISO_RATIO;
3235 else
3236 state[7] = 0xffffffff;
3237 }
3238 }
3239
3240 /* Initialize the sampler view for FMASK. */
3241 if (tex->fmask.size) {
3242 uint32_t data_format, num_format;
3243
3244 va = tex->resource.gpu_address + tex->fmask.offset;
3245
3246 if (screen->b.chip_class >= GFX9) {
3247 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3248 switch (res->nr_samples) {
3249 case 2:
3250 num_format = V_008F14_IMG_FMASK_8_2_2;
3251 break;
3252 case 4:
3253 num_format = V_008F14_IMG_FMASK_8_4_4;
3254 break;
3255 case 8:
3256 num_format = V_008F14_IMG_FMASK_32_8_8;
3257 break;
3258 default:
3259 unreachable("invalid nr_samples");
3260 }
3261 } else {
3262 switch (res->nr_samples) {
3263 case 2:
3264 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3265 break;
3266 case 4:
3267 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3268 break;
3269 case 8:
3270 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3271 break;
3272 default:
3273 unreachable("invalid nr_samples");
3274 }
3275 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3276 }
3277
3278 fmask_state[0] = va >> 8;
3279 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3280 S_008F14_DATA_FORMAT_GFX6(data_format) |
3281 S_008F14_NUM_FORMAT_GFX6(num_format);
3282 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3283 S_008F18_HEIGHT(height - 1);
3284 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3285 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3286 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3287 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3288 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3289 fmask_state[4] = 0;
3290 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3291 fmask_state[6] = 0;
3292 fmask_state[7] = 0;
3293
3294 if (screen->b.chip_class >= GFX9) {
3295 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3296 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3297 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3298 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3299 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3300 } else {
3301 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3302 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3303 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3304 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3305 }
3306 }
3307 }
3308
3309 /**
3310 * Create a sampler view.
3311 *
3312 * @param ctx context
3313 * @param texture texture
3314 * @param state sampler view template
3315 * @param width0 width0 override (for compressed textures as int)
3316 * @param height0 height0 override (for compressed textures as int)
3317 * @param force_level set the base address to the level (for compressed textures)
3318 */
3319 struct pipe_sampler_view *
3320 si_create_sampler_view_custom(struct pipe_context *ctx,
3321 struct pipe_resource *texture,
3322 const struct pipe_sampler_view *state,
3323 unsigned width0, unsigned height0,
3324 unsigned force_level)
3325 {
3326 struct si_context *sctx = (struct si_context*)ctx;
3327 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3328 struct r600_texture *tmp = (struct r600_texture*)texture;
3329 unsigned base_level, first_level, last_level;
3330 unsigned char state_swizzle[4];
3331 unsigned height, depth, width;
3332 unsigned last_layer = state->u.tex.last_layer;
3333 enum pipe_format pipe_format;
3334 const struct legacy_surf_level *surflevel;
3335
3336 if (!view)
3337 return NULL;
3338
3339 /* initialize base object */
3340 view->base = *state;
3341 view->base.texture = NULL;
3342 view->base.reference.count = 1;
3343 view->base.context = ctx;
3344
3345 assert(texture);
3346 pipe_resource_reference(&view->base.texture, texture);
3347
3348 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3349 state->format == PIPE_FORMAT_S8X24_UINT ||
3350 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3351 state->format == PIPE_FORMAT_S8_UINT)
3352 view->is_stencil_sampler = true;
3353
3354 /* Buffer resource. */
3355 if (texture->target == PIPE_BUFFER) {
3356 si_make_buffer_descriptor(sctx->screen,
3357 (struct r600_resource *)texture,
3358 state->format,
3359 state->u.buf.offset,
3360 state->u.buf.size,
3361 view->state);
3362 return &view->base;
3363 }
3364
3365 state_swizzle[0] = state->swizzle_r;
3366 state_swizzle[1] = state->swizzle_g;
3367 state_swizzle[2] = state->swizzle_b;
3368 state_swizzle[3] = state->swizzle_a;
3369
3370 base_level = 0;
3371 first_level = state->u.tex.first_level;
3372 last_level = state->u.tex.last_level;
3373 width = width0;
3374 height = height0;
3375 depth = texture->depth0;
3376
3377 if (sctx->b.chip_class <= VI && force_level) {
3378 assert(force_level == first_level &&
3379 force_level == last_level);
3380 base_level = force_level;
3381 first_level = 0;
3382 last_level = 0;
3383 width = u_minify(width, force_level);
3384 height = u_minify(height, force_level);
3385 depth = u_minify(depth, force_level);
3386 }
3387
3388 /* This is not needed if state trackers set last_layer correctly. */
3389 if (state->target == PIPE_TEXTURE_1D ||
3390 state->target == PIPE_TEXTURE_2D ||
3391 state->target == PIPE_TEXTURE_RECT ||
3392 state->target == PIPE_TEXTURE_CUBE)
3393 last_layer = state->u.tex.first_layer;
3394
3395 /* Texturing with separate depth and stencil. */
3396 pipe_format = state->format;
3397
3398 /* Depth/stencil texturing sometimes needs separate texture. */
3399 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3400 if (!tmp->flushed_depth_texture &&
3401 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3402 pipe_resource_reference(&view->base.texture, NULL);
3403 FREE(view);
3404 return NULL;
3405 }
3406
3407 assert(tmp->flushed_depth_texture);
3408
3409 /* Override format for the case where the flushed texture
3410 * contains only Z or only S.
3411 */
3412 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3413 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3414
3415 tmp = tmp->flushed_depth_texture;
3416 }
3417
3418 surflevel = tmp->surface.u.legacy.level;
3419
3420 if (tmp->db_compatible) {
3421 if (!view->is_stencil_sampler)
3422 pipe_format = tmp->db_render_format;
3423
3424 switch (pipe_format) {
3425 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3426 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3427 break;
3428 case PIPE_FORMAT_X8Z24_UNORM:
3429 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3430 /* Z24 is always stored like this for DB
3431 * compatibility.
3432 */
3433 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3434 break;
3435 case PIPE_FORMAT_X24S8_UINT:
3436 case PIPE_FORMAT_S8X24_UINT:
3437 case PIPE_FORMAT_X32_S8X24_UINT:
3438 pipe_format = PIPE_FORMAT_S8_UINT;
3439 surflevel = tmp->surface.u.legacy.stencil_level;
3440 break;
3441 default:;
3442 }
3443 }
3444
3445 view->dcc_incompatible =
3446 vi_dcc_formats_are_incompatible(texture,
3447 state->u.tex.first_level,
3448 state->format);
3449
3450 si_make_texture_descriptor(sctx->screen, tmp, true,
3451 state->target, pipe_format, state_swizzle,
3452 first_level, last_level,
3453 state->u.tex.first_layer, last_layer,
3454 width, height, depth,
3455 view->state, view->fmask_state);
3456
3457 view->base_level_info = &surflevel[base_level];
3458 view->base_level = base_level;
3459 view->block_width = util_format_get_blockwidth(pipe_format);
3460 return &view->base;
3461 }
3462
3463 static struct pipe_sampler_view *
3464 si_create_sampler_view(struct pipe_context *ctx,
3465 struct pipe_resource *texture,
3466 const struct pipe_sampler_view *state)
3467 {
3468 return si_create_sampler_view_custom(ctx, texture, state,
3469 texture ? texture->width0 : 0,
3470 texture ? texture->height0 : 0, 0);
3471 }
3472
3473 static void si_sampler_view_destroy(struct pipe_context *ctx,
3474 struct pipe_sampler_view *state)
3475 {
3476 struct si_sampler_view *view = (struct si_sampler_view *)state;
3477
3478 pipe_resource_reference(&state->texture, NULL);
3479 FREE(view);
3480 }
3481
3482 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3483 {
3484 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3485 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3486 (linear_filter &&
3487 (wrap == PIPE_TEX_WRAP_CLAMP ||
3488 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3489 }
3490
3491 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3492 {
3493 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3494 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3495
3496 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3497 state->border_color.ui[2] || state->border_color.ui[3]) &&
3498 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3499 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3500 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3501 }
3502
3503 static void *si_create_sampler_state(struct pipe_context *ctx,
3504 const struct pipe_sampler_state *state)
3505 {
3506 struct si_context *sctx = (struct si_context *)ctx;
3507 struct r600_common_screen *rscreen = sctx->b.screen;
3508 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3509 unsigned border_color_type, border_color_index = 0;
3510 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3511 : state->max_anisotropy;
3512 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3513
3514 if (!rstate) {
3515 return NULL;
3516 }
3517
3518 if (!sampler_state_needs_border_color(state))
3519 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3520 else if (state->border_color.f[0] == 0 &&
3521 state->border_color.f[1] == 0 &&
3522 state->border_color.f[2] == 0 &&
3523 state->border_color.f[3] == 0)
3524 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3525 else if (state->border_color.f[0] == 0 &&
3526 state->border_color.f[1] == 0 &&
3527 state->border_color.f[2] == 0 &&
3528 state->border_color.f[3] == 1)
3529 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3530 else if (state->border_color.f[0] == 1 &&
3531 state->border_color.f[1] == 1 &&
3532 state->border_color.f[2] == 1 &&
3533 state->border_color.f[3] == 1)
3534 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3535 else {
3536 int i;
3537
3538 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3539
3540 /* Check if the border has been uploaded already. */
3541 for (i = 0; i < sctx->border_color_count; i++)
3542 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3543 sizeof(state->border_color)) == 0)
3544 break;
3545
3546 if (i >= SI_MAX_BORDER_COLORS) {
3547 /* Getting 4096 unique border colors is very unlikely. */
3548 fprintf(stderr, "radeonsi: The border color table is full. "
3549 "Any new border colors will be just black. "
3550 "Please file a bug.\n");
3551 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3552 } else {
3553 if (i == sctx->border_color_count) {
3554 /* Upload a new border color. */
3555 memcpy(&sctx->border_color_table[i], &state->border_color,
3556 sizeof(state->border_color));
3557 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3558 &state->border_color,
3559 sizeof(state->border_color));
3560 sctx->border_color_count++;
3561 }
3562
3563 border_color_index = i;
3564 }
3565 }
3566
3567 #ifdef DEBUG
3568 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3569 #endif
3570 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3571 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3572 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3573 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3574 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3575 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3576 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3577 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3578 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3579 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3580 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3581 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3582 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3583 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3584 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3585 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3586 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3587 S_008F38_MIP_POINT_PRECLAMP(1) |
3588 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3589 S_008F38_FILTER_PREC_FIX(1) |
3590 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3591 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3592 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3593 return rstate;
3594 }
3595
3596 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3597 {
3598 struct si_context *sctx = (struct si_context *)ctx;
3599
3600 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3601 return;
3602
3603 sctx->sample_mask.sample_mask = sample_mask;
3604 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3605 }
3606
3607 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3608 {
3609 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3610 unsigned mask = sctx->sample_mask.sample_mask;
3611
3612 /* Needed for line and polygon smoothing as well as for the Polaris
3613 * small primitive filter. We expect the state tracker to take care of
3614 * this for us.
3615 */
3616 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3617 (mask & 1 && sctx->blitter->running));
3618
3619 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3620 radeon_emit(cs, mask | (mask << 16));
3621 radeon_emit(cs, mask | (mask << 16));
3622 }
3623
3624 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3625 {
3626 #ifdef DEBUG
3627 struct si_sampler_state *s = state;
3628
3629 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3630 s->magic = 0;
3631 #endif
3632 free(state);
3633 }
3634
3635 /*
3636 * Vertex elements & buffers
3637 */
3638
3639 static void *si_create_vertex_elements(struct pipe_context *ctx,
3640 unsigned count,
3641 const struct pipe_vertex_element *elements)
3642 {
3643 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3644 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3645 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3646 int i;
3647
3648 assert(count <= SI_MAX_ATTRIBS);
3649 if (!v)
3650 return NULL;
3651
3652 v->count = count;
3653 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3654
3655 for (i = 0; i < count; ++i) {
3656 const struct util_format_description *desc;
3657 const struct util_format_channel_description *channel;
3658 unsigned data_format, num_format;
3659 int first_non_void;
3660 unsigned vbo_index = elements[i].vertex_buffer_index;
3661 unsigned char swizzle[4];
3662
3663 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3664 FREE(v);
3665 return NULL;
3666 }
3667
3668 if (!used[vbo_index]) {
3669 v->first_vb_use_mask |= 1 << i;
3670 used[vbo_index] = true;
3671 }
3672
3673 desc = util_format_description(elements[i].src_format);
3674 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3675 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3676 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3677 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3678 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3679
3680 v->format_size[i] = desc->block.bits / 8;
3681
3682 /* The hardware always treats the 2-bit alpha channel as
3683 * unsigned, so a shader workaround is needed. The affected
3684 * chips are VI and older except Stoney (GFX8.1).
3685 */
3686 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3687 sscreen->b.chip_class <= VI &&
3688 sscreen->b.family != CHIP_STONEY) {
3689 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3690 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3691 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3692 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3693 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3694 /* This isn't actually used in OpenGL. */
3695 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3696 }
3697 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3698 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3699 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3700 else
3701 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3702 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3703 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3704 if (channel->normalized) {
3705 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3706 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3707 else
3708 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3709 } else {
3710 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3711 }
3712 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3713 if (channel->normalized) {
3714 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3715 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3716 else
3717 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3718 } else {
3719 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3720 }
3721 }
3722 } else if (channel && channel->size == 64 &&
3723 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3724 switch (desc->nr_channels) {
3725 case 1:
3726 case 2:
3727 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3728 swizzle[0] = PIPE_SWIZZLE_X;
3729 swizzle[1] = PIPE_SWIZZLE_Y;
3730 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3731 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3732 break;
3733 case 3:
3734 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3735 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3736 swizzle[1] = PIPE_SWIZZLE_Y;
3737 swizzle[2] = PIPE_SWIZZLE_0;
3738 swizzle[3] = PIPE_SWIZZLE_0;
3739 break;
3740 case 4:
3741 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3742 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3743 swizzle[1] = PIPE_SWIZZLE_Y;
3744 swizzle[2] = PIPE_SWIZZLE_Z;
3745 swizzle[3] = PIPE_SWIZZLE_W;
3746 break;
3747 default:
3748 assert(0);
3749 }
3750 } else if (channel && desc->nr_channels == 3) {
3751 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3752
3753 if (channel->size == 8) {
3754 if (channel->pure_integer)
3755 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3756 else
3757 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3758 } else if (channel->size == 16) {
3759 if (channel->pure_integer)
3760 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3761 else
3762 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3763 }
3764 }
3765
3766 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3767 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3768 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3769 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3770 S_008F0C_NUM_FORMAT(num_format) |
3771 S_008F0C_DATA_FORMAT(data_format);
3772 }
3773 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3774
3775 return v;
3776 }
3777
3778 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3779 {
3780 struct si_context *sctx = (struct si_context *)ctx;
3781 struct si_vertex_element *v = (struct si_vertex_element*)state;
3782
3783 sctx->vertex_elements = v;
3784 sctx->vertex_buffers_dirty = true;
3785 sctx->do_update_shaders = true;
3786 }
3787
3788 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3789 {
3790 struct si_context *sctx = (struct si_context *)ctx;
3791
3792 if (sctx->vertex_elements == state)
3793 sctx->vertex_elements = NULL;
3794 FREE(state);
3795 }
3796
3797 static void si_set_vertex_buffers(struct pipe_context *ctx,
3798 unsigned start_slot, unsigned count,
3799 const struct pipe_vertex_buffer *buffers)
3800 {
3801 struct si_context *sctx = (struct si_context *)ctx;
3802 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3803 int i;
3804
3805 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3806
3807 if (buffers) {
3808 for (i = 0; i < count; i++) {
3809 const struct pipe_vertex_buffer *src = buffers + i;
3810 struct pipe_vertex_buffer *dsti = dst + i;
3811
3812 if (unlikely(src->user_buffer)) {
3813 /* Zero-stride attribs only. */
3814 assert(src->stride == 0);
3815
3816 /* Assume that the user_buffer comes from
3817 * gl_current_attrib, which implies it has
3818 * 4 * 8 bytes (for dvec4 attributes).
3819 *
3820 * Use const_uploader to upload into VRAM directly.
3821 */
3822 u_upload_data(sctx->b.b.const_uploader, 0, 32, 32,
3823 src->user_buffer,
3824 &dsti->buffer_offset,
3825 &dsti->buffer);
3826 dsti->stride = 0;
3827 } else {
3828 struct pipe_resource *buf = src->buffer;
3829
3830 pipe_resource_reference(&dsti->buffer, buf);
3831 dsti->buffer_offset = src->buffer_offset;
3832 dsti->stride = src->stride;
3833 r600_context_add_resource_size(ctx, buf);
3834 if (buf)
3835 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3836 }
3837 }
3838 } else {
3839 for (i = 0; i < count; i++) {
3840 pipe_resource_reference(&dst[i].buffer, NULL);
3841 }
3842 }
3843 sctx->vertex_buffers_dirty = true;
3844 }
3845
3846 static void si_set_index_buffer(struct pipe_context *ctx,
3847 const struct pipe_index_buffer *ib)
3848 {
3849 struct si_context *sctx = (struct si_context *)ctx;
3850
3851 if (ib) {
3852 struct pipe_resource *buf = ib->buffer;
3853
3854 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3855 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3856 r600_context_add_resource_size(ctx, buf);
3857 if (buf)
3858 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3859 } else {
3860 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3861 }
3862 }
3863
3864 /*
3865 * Misc
3866 */
3867
3868 static void si_set_tess_state(struct pipe_context *ctx,
3869 const float default_outer_level[4],
3870 const float default_inner_level[2])
3871 {
3872 struct si_context *sctx = (struct si_context *)ctx;
3873 struct pipe_constant_buffer cb;
3874 float array[8];
3875
3876 memcpy(array, default_outer_level, sizeof(float) * 4);
3877 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3878
3879 cb.buffer = NULL;
3880 cb.user_buffer = NULL;
3881 cb.buffer_size = sizeof(array);
3882
3883 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3884 (void*)array, sizeof(array),
3885 &cb.buffer_offset);
3886
3887 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3888 pipe_resource_reference(&cb.buffer, NULL);
3889 }
3890
3891 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3892 {
3893 struct si_context *sctx = (struct si_context *)ctx;
3894
3895 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3896 SI_CONTEXT_INV_GLOBAL_L2 |
3897 SI_CONTEXT_FLUSH_AND_INV_CB;
3898 sctx->framebuffer.do_update_surf_dirtiness = true;
3899 }
3900
3901 /* This only ensures coherency for shader image/buffer stores. */
3902 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3903 {
3904 struct si_context *sctx = (struct si_context *)ctx;
3905
3906 /* Subsequent commands must wait for all shader invocations to
3907 * complete. */
3908 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3909 SI_CONTEXT_CS_PARTIAL_FLUSH;
3910
3911 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3912 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3913 SI_CONTEXT_INV_VMEM_L1;
3914
3915 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3916 PIPE_BARRIER_SHADER_BUFFER |
3917 PIPE_BARRIER_TEXTURE |
3918 PIPE_BARRIER_IMAGE |
3919 PIPE_BARRIER_STREAMOUT_BUFFER |
3920 PIPE_BARRIER_GLOBAL_BUFFER)) {
3921 /* As far as I can tell, L1 contents are written back to L2
3922 * automatically at end of shader, but the contents of other
3923 * L1 caches might still be stale. */
3924 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3925 }
3926
3927 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3928 /* Indices are read through TC L2 since VI.
3929 * L1 isn't used.
3930 */
3931 if (sctx->screen->b.chip_class <= CIK)
3932 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3933 }
3934
3935 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3936 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3937 SI_CONTEXT_FLUSH_AND_INV_DB;
3938
3939 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3940 PIPE_BARRIER_INDIRECT_BUFFER))
3941 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3942 }
3943
3944 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3945 {
3946 struct pipe_blend_state blend;
3947
3948 memset(&blend, 0, sizeof(blend));
3949 blend.independent_blend_enable = true;
3950 blend.rt[0].colormask = 0xf;
3951 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3952 }
3953
3954 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3955 bool include_draw_vbo)
3956 {
3957 si_need_cs_space((struct si_context*)ctx);
3958 }
3959
3960 static void si_init_config(struct si_context *sctx);
3961
3962 void si_init_state_functions(struct si_context *sctx)
3963 {
3964 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3965 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3966 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3967 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3968 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3969
3970 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3971 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3972 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3973 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3974 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3975 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3976 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3977 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3978 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3979 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3980
3981 sctx->b.b.create_blend_state = si_create_blend_state;
3982 sctx->b.b.bind_blend_state = si_bind_blend_state;
3983 sctx->b.b.delete_blend_state = si_delete_blend_state;
3984 sctx->b.b.set_blend_color = si_set_blend_color;
3985
3986 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3987 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3988 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3989
3990 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3991 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3992 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3993
3994 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3995 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3996 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3997 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3998 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3999
4000 sctx->b.b.set_clip_state = si_set_clip_state;
4001 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4002
4003 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4004 sctx->b.b.get_sample_position = cayman_get_sample_position;
4005
4006 sctx->b.b.create_sampler_state = si_create_sampler_state;
4007 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4008
4009 sctx->b.b.create_sampler_view = si_create_sampler_view;
4010 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4011
4012 sctx->b.b.set_sample_mask = si_set_sample_mask;
4013
4014 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4015 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4016 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4017 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4018 sctx->b.b.set_index_buffer = si_set_index_buffer;
4019
4020 sctx->b.b.texture_barrier = si_texture_barrier;
4021 sctx->b.b.memory_barrier = si_memory_barrier;
4022 sctx->b.b.set_min_samples = si_set_min_samples;
4023 sctx->b.b.set_tess_state = si_set_tess_state;
4024
4025 sctx->b.b.set_active_query_state = si_set_active_query_state;
4026 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4027 sctx->b.save_qbo_state = si_save_qbo_state;
4028 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4029
4030 sctx->b.b.draw_vbo = si_draw_vbo;
4031
4032 si_init_config(sctx);
4033 }
4034
4035 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4036 {
4037 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4038 }
4039
4040 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4041 struct r600_texture *rtex,
4042 struct radeon_bo_metadata *md)
4043 {
4044 struct si_screen *sscreen = (struct si_screen*)rscreen;
4045 struct pipe_resource *res = &rtex->resource.b.b;
4046 static const unsigned char swizzle[] = {
4047 PIPE_SWIZZLE_X,
4048 PIPE_SWIZZLE_Y,
4049 PIPE_SWIZZLE_Z,
4050 PIPE_SWIZZLE_W
4051 };
4052 uint32_t desc[8], i;
4053 bool is_array = util_resource_is_array_texture(res);
4054
4055 /* DRM 2.x.x doesn't support this. */
4056 if (rscreen->info.drm_major != 3)
4057 return;
4058
4059 assert(rtex->dcc_separate_buffer == NULL);
4060 assert(rtex->fmask.size == 0);
4061
4062 /* Metadata image format format version 1:
4063 * [0] = 1 (metadata format identifier)
4064 * [1] = (VENDOR_ID << 16) | PCI_ID
4065 * [2:9] = image descriptor for the whole resource
4066 * [2] is always 0, because the base address is cleared
4067 * [9] is the DCC offset bits [39:8] from the beginning of
4068 * the buffer
4069 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4070 */
4071
4072 md->metadata[0] = 1; /* metadata image format version 1 */
4073
4074 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4075 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4076
4077 si_make_texture_descriptor(sscreen, rtex, true,
4078 res->target, res->format,
4079 swizzle, 0, res->last_level, 0,
4080 is_array ? res->array_size - 1 : 0,
4081 res->width0, res->height0, res->depth0,
4082 desc, NULL);
4083
4084 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4085 0, 0, rtex->surface.blk_w, false, desc);
4086
4087 /* Clear the base address and set the relative DCC offset. */
4088 desc[0] = 0;
4089 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4090 desc[7] = rtex->dcc_offset >> 8;
4091
4092 /* Dwords [2:9] contain the image descriptor. */
4093 memcpy(&md->metadata[2], desc, sizeof(desc));
4094 md->size_metadata = 10 * 4;
4095
4096 /* Dwords [10:..] contain the mipmap level offsets. */
4097 if (rscreen->chip_class <= VI) {
4098 for (i = 0; i <= res->last_level; i++)
4099 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4100
4101 md->size_metadata += (1 + res->last_level) * 4;
4102 }
4103 }
4104
4105 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4106 struct r600_texture *rtex,
4107 struct radeon_bo_metadata *md)
4108 {
4109 uint32_t *desc = &md->metadata[2];
4110
4111 if (rscreen->chip_class < VI)
4112 return;
4113
4114 /* Return if DCC is enabled. The texture should be set up with it
4115 * already.
4116 */
4117 if (md->size_metadata >= 11 * 4 &&
4118 md->metadata[0] != 0 &&
4119 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4120 G_008F28_COMPRESSION_EN(desc[6])) {
4121 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4122 return;
4123 }
4124
4125 /* Disable DCC. These are always set by texture_from_handle and must
4126 * be cleared here.
4127 */
4128 rtex->dcc_offset = 0;
4129 }
4130
4131 void si_init_screen_state_functions(struct si_screen *sscreen)
4132 {
4133 sscreen->b.b.is_format_supported = si_is_format_supported;
4134 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4135 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4136 }
4137
4138 static void
4139 si_write_harvested_raster_configs(struct si_context *sctx,
4140 struct si_pm4_state *pm4,
4141 unsigned raster_config,
4142 unsigned raster_config_1)
4143 {
4144 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4145 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4146 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4147 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4148 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4149 unsigned rb_per_se = num_rb / num_se;
4150 unsigned se_mask[4];
4151 unsigned se;
4152
4153 se_mask[0] = ((1 << rb_per_se) - 1);
4154 se_mask[1] = (se_mask[0] << rb_per_se);
4155 se_mask[2] = (se_mask[1] << rb_per_se);
4156 se_mask[3] = (se_mask[2] << rb_per_se);
4157
4158 se_mask[0] &= rb_mask;
4159 se_mask[1] &= rb_mask;
4160 se_mask[2] &= rb_mask;
4161 se_mask[3] &= rb_mask;
4162
4163 assert(num_se == 1 || num_se == 2 || num_se == 4);
4164 assert(sh_per_se == 1 || sh_per_se == 2);
4165 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4166
4167 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4168 * fields are for, so I'm leaving them as their default
4169 * values. */
4170
4171 for (se = 0; se < num_se; se++) {
4172 unsigned raster_config_se = raster_config;
4173 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4174 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4175 int idx = (se / 2) * 2;
4176
4177 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4178 raster_config_se &= C_028350_SE_MAP;
4179
4180 if (!se_mask[idx]) {
4181 raster_config_se |=
4182 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4183 } else {
4184 raster_config_se |=
4185 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4186 }
4187 }
4188
4189 pkr0_mask &= rb_mask;
4190 pkr1_mask &= rb_mask;
4191 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4192 raster_config_se &= C_028350_PKR_MAP;
4193
4194 if (!pkr0_mask) {
4195 raster_config_se |=
4196 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4197 } else {
4198 raster_config_se |=
4199 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4200 }
4201 }
4202
4203 if (rb_per_se >= 2) {
4204 unsigned rb0_mask = 1 << (se * rb_per_se);
4205 unsigned rb1_mask = rb0_mask << 1;
4206
4207 rb0_mask &= rb_mask;
4208 rb1_mask &= rb_mask;
4209 if (!rb0_mask || !rb1_mask) {
4210 raster_config_se &= C_028350_RB_MAP_PKR0;
4211
4212 if (!rb0_mask) {
4213 raster_config_se |=
4214 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4215 } else {
4216 raster_config_se |=
4217 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4218 }
4219 }
4220
4221 if (rb_per_se > 2) {
4222 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4223 rb1_mask = rb0_mask << 1;
4224 rb0_mask &= rb_mask;
4225 rb1_mask &= rb_mask;
4226 if (!rb0_mask || !rb1_mask) {
4227 raster_config_se &= C_028350_RB_MAP_PKR1;
4228
4229 if (!rb0_mask) {
4230 raster_config_se |=
4231 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4232 } else {
4233 raster_config_se |=
4234 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4235 }
4236 }
4237 }
4238 }
4239
4240 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4241 if (sctx->b.chip_class < CIK)
4242 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4243 SE_INDEX(se) | SH_BROADCAST_WRITES |
4244 INSTANCE_BROADCAST_WRITES);
4245 else
4246 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4247 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4248 S_030800_INSTANCE_BROADCAST_WRITES(1));
4249 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4250 }
4251
4252 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4253 if (sctx->b.chip_class < CIK)
4254 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4255 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4256 INSTANCE_BROADCAST_WRITES);
4257 else {
4258 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4259 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4260 S_030800_INSTANCE_BROADCAST_WRITES(1));
4261
4262 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4263 (!se_mask[2] && !se_mask[3]))) {
4264 raster_config_1 &= C_028354_SE_PAIR_MAP;
4265
4266 if (!se_mask[0] && !se_mask[1]) {
4267 raster_config_1 |=
4268 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4269 } else {
4270 raster_config_1 |=
4271 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4272 }
4273 }
4274
4275 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4276 }
4277 }
4278
4279 static void si_init_config(struct si_context *sctx)
4280 {
4281 struct si_screen *sscreen = sctx->screen;
4282 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4283 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4284 unsigned raster_config, raster_config_1;
4285 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4286 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4287
4288 if (!pm4)
4289 return;
4290
4291 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4292 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4293 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4294 si_pm4_cmd_end(pm4, false);
4295
4296 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4297 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4298
4299 /* FIXME calculate these values somehow ??? */
4300 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4301 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4302 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4303
4304 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4305 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4306
4307 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4308 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4309 if (sctx->b.chip_class < CIK)
4310 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4311 S_008A14_CLIP_VTX_REORDER_ENA(1));
4312
4313 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4314 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4315
4316 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4317
4318 switch (sctx->screen->b.family) {
4319 case CHIP_TAHITI:
4320 case CHIP_PITCAIRN:
4321 raster_config = 0x2a00126a;
4322 raster_config_1 = 0x00000000;
4323 break;
4324 case CHIP_VERDE:
4325 raster_config = 0x0000124a;
4326 raster_config_1 = 0x00000000;
4327 break;
4328 case CHIP_OLAND:
4329 raster_config = 0x00000082;
4330 raster_config_1 = 0x00000000;
4331 break;
4332 case CHIP_HAINAN:
4333 raster_config = 0x00000000;
4334 raster_config_1 = 0x00000000;
4335 break;
4336 case CHIP_BONAIRE:
4337 raster_config = 0x16000012;
4338 raster_config_1 = 0x00000000;
4339 break;
4340 case CHIP_HAWAII:
4341 raster_config = 0x3a00161a;
4342 raster_config_1 = 0x0000002e;
4343 break;
4344 case CHIP_FIJI:
4345 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4346 /* old kernels with old tiling config */
4347 raster_config = 0x16000012;
4348 raster_config_1 = 0x0000002a;
4349 } else {
4350 raster_config = 0x3a00161a;
4351 raster_config_1 = 0x0000002e;
4352 }
4353 break;
4354 case CHIP_POLARIS10:
4355 raster_config = 0x16000012;
4356 raster_config_1 = 0x0000002a;
4357 break;
4358 case CHIP_POLARIS11:
4359 case CHIP_POLARIS12:
4360 raster_config = 0x16000012;
4361 raster_config_1 = 0x00000000;
4362 break;
4363 case CHIP_TONGA:
4364 raster_config = 0x16000012;
4365 raster_config_1 = 0x0000002a;
4366 break;
4367 case CHIP_ICELAND:
4368 if (num_rb == 1)
4369 raster_config = 0x00000000;
4370 else
4371 raster_config = 0x00000002;
4372 raster_config_1 = 0x00000000;
4373 break;
4374 case CHIP_CARRIZO:
4375 raster_config = 0x00000002;
4376 raster_config_1 = 0x00000000;
4377 break;
4378 case CHIP_KAVERI:
4379 /* KV should be 0x00000002, but that causes problems with radeon */
4380 raster_config = 0x00000000; /* 0x00000002 */
4381 raster_config_1 = 0x00000000;
4382 break;
4383 case CHIP_KABINI:
4384 case CHIP_MULLINS:
4385 case CHIP_STONEY:
4386 raster_config = 0x00000000;
4387 raster_config_1 = 0x00000000;
4388 break;
4389 default:
4390 if (sctx->b.chip_class <= VI) {
4391 fprintf(stderr,
4392 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4393 raster_config = 0x00000000;
4394 raster_config_1 = 0x00000000;
4395 }
4396 break;
4397 }
4398
4399 if (sctx->b.chip_class <= VI) {
4400 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4401 /* Always use the default config when all backends are enabled
4402 * (or when we failed to determine the enabled backends).
4403 */
4404 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4405 raster_config);
4406 if (sctx->b.chip_class >= CIK)
4407 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4408 raster_config_1);
4409 } else {
4410 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4411 }
4412 }
4413
4414 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4415 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4416 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4417 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4418 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4419 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4420 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4421
4422 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4423 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4424 S_028230_ER_TRI(0xA) |
4425 S_028230_ER_POINT(0xA) |
4426 S_028230_ER_RECT(0xA) |
4427 /* Required by DX10_DIAMOND_TEST_ENA: */
4428 S_028230_ER_LINE_LR(0x1A) |
4429 S_028230_ER_LINE_RL(0x26) |
4430 S_028230_ER_LINE_TB(0xA) |
4431 S_028230_ER_LINE_BT(0xA));
4432 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4433 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4434 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4435 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4436 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4437 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4438 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4439
4440 if (sctx->b.chip_class >= GFX9) {
4441 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4442 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4443 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4444 } else {
4445 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4446 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4447 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4448 }
4449
4450 if (sctx->b.chip_class >= CIK) {
4451 /* If this is 0, Bonaire can hang even if GS isn't being used.
4452 * Other chips are unaffected. These are suboptimal values,
4453 * but we don't use on-chip GS.
4454 */
4455 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4456 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4457 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4458
4459 if (sctx->b.chip_class >= GFX9) {
4460 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4461 } else {
4462 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4463 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4464 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4465 }
4466 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4467
4468 if (sscreen->b.info.num_good_compute_units /
4469 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4470 /* Too few available compute units per SH. Disallowing
4471 * VS to run on CU0 could hurt us more than late VS
4472 * allocation would help.
4473 *
4474 * LATE_ALLOC_VS = 2 is the highest safe number.
4475 */
4476 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4477 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4478 } else {
4479 /* Set LATE_ALLOC_VS == 31. It should be less than
4480 * the number of scratch waves. Limitations:
4481 * - VS can't execute on CU0.
4482 * - If HS writes outputs to LDS, LS can't execute on CU0.
4483 */
4484 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4485 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4486 }
4487
4488 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4489 }
4490
4491 if (sctx->b.chip_class >= VI) {
4492 unsigned vgt_tess_distribution;
4493
4494 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4495 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4496 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4497 if (sctx->b.family < CHIP_POLARIS10)
4498 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4499 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4500
4501 vgt_tess_distribution =
4502 S_028B50_ACCUM_ISOLINE(32) |
4503 S_028B50_ACCUM_TRI(11) |
4504 S_028B50_ACCUM_QUAD(11) |
4505 S_028B50_DONUT_SPLIT(16);
4506
4507 /* Testing with Unigine Heaven extreme tesselation yielded best results
4508 * with TRAP_SPLIT = 3.
4509 */
4510 if (sctx->b.family == CHIP_FIJI ||
4511 sctx->b.family >= CHIP_POLARIS10)
4512 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4513
4514 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4515 } else {
4516 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4517 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4518 }
4519
4520 if (sctx->screen->b.has_rbplus)
4521 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4522
4523 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4524 if (sctx->b.chip_class >= CIK)
4525 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4526 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4527 RADEON_PRIO_BORDER_COLORS);
4528
4529 if (sctx->b.chip_class >= GFX9) {
4530 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
4531 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4532 /* TODO: We can use this to disable RBs for rendering to GART: */
4533 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4534 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4535 /* TODO: Enable the binner: */
4536 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4537 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
4538 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
4539 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4540 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4541 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4542 }
4543
4544 si_pm4_upload_indirect_buffer(sctx, pm4);
4545 sctx->init_config = pm4;
4546 }