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radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blending
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
76 {
77 return value * (1 << frac_bits);
78 }
79
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x)
82 {
83 return x <= 0 ? 0 :
84 x >= 4096 ? 0xffff : x * 16;
85 }
86
87 /*
88 * Inferred framebuffer and blender state.
89 *
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
92 */
93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_state_blend *blend = sctx->queued.named.blend;
97 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
98 * but you never know. */
99 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
100 unsigned i;
101
102 if (blend)
103 cb_target_mask &= blend->cb_target_mask;
104
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
108 *
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
110 */
111 if (blend && blend->dual_src_blend &&
112 sctx->ps_shader.cso &&
113 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
114 cb_target_mask = 0;
115
116 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
117
118 /* STONEY-specific register settings. */
119 if (sctx->b.family == CHIP_STONEY) {
120 unsigned spi_shader_col_format =
121 sctx->ps_shader.cso ?
122 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
123 unsigned sx_ps_downconvert = 0;
124 unsigned sx_blend_opt_epsilon = 0;
125 unsigned sx_blend_opt_control = 0;
126
127 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
128 struct r600_surface *surf =
129 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf)
134 continue;
135
136 format = G_028C70_FORMAT(surf->cb_color_info);
137 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
138 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
139 colormask = (cb_target_mask >> (i * 4)) & 0xf;
140
141 /* Set if RGB and A are present. */
142 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
143
144 if (format == V_028C70_COLOR_8 ||
145 format == V_028C70_COLOR_16 ||
146 format == V_028C70_COLOR_32)
147 has_rgb = !has_alpha;
148 else
149 has_rgb = true;
150
151 /* Check the colormask and export format. */
152 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
153 has_rgb = false;
154 if (!(colormask & PIPE_MASK_A))
155 has_alpha = false;
156
157 if (spi_format == V_028714_SPI_SHADER_ZERO) {
158 has_rgb = false;
159 has_alpha = false;
160 }
161
162 /* Disable value checking for disabled channels. */
163 if (!has_rgb)
164 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
165 if (!has_alpha)
166 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
167
168 /* Enable down-conversion for 32bpp and smaller formats. */
169 switch (format) {
170 case V_028C70_COLOR_8:
171 case V_028C70_COLOR_8_8:
172 case V_028C70_COLOR_8_8_8_8:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
175 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_5_6_5:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_1_5_5_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_4_4_4_4:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_32:
204 if (swap == V_0280A0_SWAP_STD &&
205 spi_format == V_028714_SPI_SHADER_32_R)
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
207 else if (swap == V_0280A0_SWAP_ALT_REV &&
208 spi_format == V_028714_SPI_SHADER_32_AR)
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
210 break;
211
212 case V_028C70_COLOR_16:
213 case V_028C70_COLOR_16_16:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
216 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
219 if (swap == V_0280A0_SWAP_STD ||
220 swap == V_0280A0_SWAP_STD_REV)
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
222 else
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
224 }
225 break;
226
227 case V_028C70_COLOR_10_11_11:
228 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
230 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_2_10_10_10:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
238 }
239 break;
240 }
241 }
242
243 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
244 sx_ps_downconvert = 0;
245 sx_blend_opt_epsilon = 0;
246 sx_blend_opt_control = 0;
247 }
248
249 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 R600_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
383 *src_factor = PIPE_BLENDFACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == PIPE_BLEND_SUBTRACT)
388 *func = PIPE_BLEND_REVERSE_SUBTRACT;
389 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
390 *func = PIPE_BLEND_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
397 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
398 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
399 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
401 }
402
403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
404 const struct pipe_blend_state *state,
405 unsigned mode)
406 {
407 struct si_context *sctx = (struct si_context*)ctx;
408 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
409 struct si_pm4_state *pm4 = &blend->pm4;
410 uint32_t sx_mrt_blend_opt[8] = {0};
411 uint32_t color_control = 0;
412
413 if (!blend)
414 return NULL;
415
416 blend->alpha_to_coverage = state->alpha_to_coverage;
417 blend->alpha_to_one = state->alpha_to_one;
418 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
419
420 if (state->logicop_enable) {
421 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
422 } else {
423 color_control |= S_028808_ROP3(0xcc);
424 }
425
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
432
433 if (state->alpha_to_coverage)
434 blend->need_src_alpha_4bit |= 0xf;
435
436 blend->cb_target_mask = 0;
437 for (int i = 0; i < 8; i++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j = state->independent_blend_enable ? i : 0;
440
441 unsigned eqRGB = state->rt[j].rgb_func;
442 unsigned srcRGB = state->rt[j].rgb_src_factor;
443 unsigned dstRGB = state->rt[j].rgb_dst_factor;
444 unsigned eqA = state->rt[j].alpha_func;
445 unsigned srcA = state->rt[j].alpha_src_factor;
446 unsigned dstA = state->rt[j].alpha_dst_factor;
447
448 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
449 unsigned blend_cntl = 0;
450
451 sx_mrt_blend_opt[i] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
454
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i >= 1 && blend->dual_src_blend) {
457 /* Vulkan does this for dual source blending. */
458 if (i == 1)
459 blend_cntl |= S_028780_ENABLE(1);
460
461 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
462 continue;
463 }
464
465 /* Only addition and subtraction equations are supported with
466 * dual source blending.
467 */
468 if (blend->dual_src_blend &&
469 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
470 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
471 assert(!"Unsupported equation for dual source blending");
472 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
473 continue;
474 }
475
476 /* cb_render_state will disable unused ones */
477 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
478
479 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
480 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
481 continue;
482 }
483
484 /* Blending optimizations for Stoney.
485 * These transformations don't change the behavior.
486 *
487 * First, get rid of DST in the blend factors:
488 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
489 */
490 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
491 PIPE_BLENDFACTOR_DST_COLOR,
492 PIPE_BLENDFACTOR_SRC_COLOR);
493 si_blend_remove_dst(&eqA, &srcA, &dstA,
494 PIPE_BLENDFACTOR_DST_COLOR,
495 PIPE_BLENDFACTOR_SRC_COLOR);
496 si_blend_remove_dst(&eqA, &srcA, &dstA,
497 PIPE_BLENDFACTOR_DST_ALPHA,
498 PIPE_BLENDFACTOR_SRC_ALPHA);
499
500 /* Look up the ideal settings from tables. */
501 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
502 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
503 srcA_opt = si_translate_blend_opt_factor(srcA, true);
504 dstA_opt = si_translate_blend_opt_factor(dstA, true);
505
506 /* Handle interdependencies. */
507 if (si_blend_factor_uses_dst(srcRGB))
508 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
509 if (si_blend_factor_uses_dst(srcA))
510 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
511
512 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
513 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
514 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
516 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
517
518 /* Set the final value. */
519 sx_mrt_blend_opt[i] =
520 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
521 S_028760_COLOR_DST_OPT(dstRGB_opt) |
522 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
523 S_028760_ALPHA_SRC_OPT(srcA_opt) |
524 S_028760_ALPHA_DST_OPT(dstA_opt) |
525 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
526
527 /* Set blend state. */
528 blend_cntl |= S_028780_ENABLE(1);
529 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
530 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
531 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
532
533 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
534 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
535 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
536 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
537 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
538 }
539 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
540
541 blend->blend_enable_4bit |= 0xfu << (i * 4);
542
543 /* This is only important for formats without alpha. */
544 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
545 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
547 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
549 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
550 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
551 }
552
553 if (blend->cb_target_mask) {
554 color_control |= S_028808_MODE(mode);
555 } else {
556 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
557 }
558
559 if (sctx->b.family == CHIP_STONEY) {
560 for (int i = 0; i < 8; i++)
561 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
562 sx_mrt_blend_opt[i]);
563
564 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
565 if (blend->dual_src_blend || state->logicop_enable ||
566 mode == V_028808_CB_RESOLVE)
567 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
568 }
569
570 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
571 return blend;
572 }
573
574 static void *si_create_blend_state(struct pipe_context *ctx,
575 const struct pipe_blend_state *state)
576 {
577 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
578 }
579
580 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
581 {
582 struct si_context *sctx = (struct si_context *)ctx;
583 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
584 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
585 sctx->do_update_shaders = true;
586 }
587
588 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
589 {
590 struct si_context *sctx = (struct si_context *)ctx;
591 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
592 }
593
594 static void si_set_blend_color(struct pipe_context *ctx,
595 const struct pipe_blend_color *state)
596 {
597 struct si_context *sctx = (struct si_context *)ctx;
598
599 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
600 return;
601
602 sctx->blend_color.state = *state;
603 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
604 }
605
606 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
607 {
608 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
609
610 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
611 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
612 }
613
614 /*
615 * Clipping
616 */
617
618 static void si_set_clip_state(struct pipe_context *ctx,
619 const struct pipe_clip_state *state)
620 {
621 struct si_context *sctx = (struct si_context *)ctx;
622 struct pipe_constant_buffer cb;
623
624 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
625 return;
626
627 sctx->clip_state.state = *state;
628 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
629
630 cb.buffer = NULL;
631 cb.user_buffer = state->ucp;
632 cb.buffer_offset = 0;
633 cb.buffer_size = 4*4*8;
634 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
635 pipe_resource_reference(&cb.buffer, NULL);
636 }
637
638 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
639 {
640 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
641
642 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
643 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
644 }
645
646 #define SIX_BITS 0x3F
647
648 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
649 {
650 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
651 struct si_shader *vs = si_get_vs_state(sctx);
652 struct tgsi_shader_info *info = si_get_vs_info(sctx);
653 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
654 unsigned window_space =
655 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
656 unsigned clipdist_mask =
657 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
658 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
659 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
660 unsigned total_mask;
661
662 if (vs->key.opt.hw_vs.clip_disable) {
663 assert(!info->culldist_writemask);
664 clipdist_mask = 0;
665 culldist_mask = 0;
666 }
667 total_mask = clipdist_mask | culldist_mask;
668
669 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
670 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
671 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
672 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
673 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
674 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
675 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
676 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
677 info->writes_edgeflag ||
678 info->writes_layer ||
679 info->writes_viewport_index) |
680 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
681 (rs->clip_plane_enable &
682 clipdist_mask) | (culldist_mask << 8));
683 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
684 rs->pa_cl_clip_cntl |
685 ucp_mask |
686 S_028810_CLIP_DISABLE(window_space));
687
688 /* reuse needs to be set off if we write oViewport */
689 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
690 S_028AB4_REUSE_OFF(info->writes_viewport_index));
691 }
692
693 /*
694 * inferred state between framebuffer and rasterizer
695 */
696 static void si_update_poly_offset_state(struct si_context *sctx)
697 {
698 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
699
700 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
701 return;
702
703 /* Use the user format, not db_render_format, so that the polygon
704 * offset behaves as expected by applications.
705 */
706 switch (sctx->framebuffer.state.zsbuf->texture->format) {
707 case PIPE_FORMAT_Z16_UNORM:
708 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
709 break;
710 default: /* 24-bit */
711 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
712 break;
713 case PIPE_FORMAT_Z32_FLOAT:
714 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
715 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
716 break;
717 }
718 }
719
720 /*
721 * Rasterizer
722 */
723
724 static uint32_t si_translate_fill(uint32_t func)
725 {
726 switch(func) {
727 case PIPE_POLYGON_MODE_FILL:
728 return V_028814_X_DRAW_TRIANGLES;
729 case PIPE_POLYGON_MODE_LINE:
730 return V_028814_X_DRAW_LINES;
731 case PIPE_POLYGON_MODE_POINT:
732 return V_028814_X_DRAW_POINTS;
733 default:
734 assert(0);
735 return V_028814_X_DRAW_POINTS;
736 }
737 }
738
739 static void *si_create_rs_state(struct pipe_context *ctx,
740 const struct pipe_rasterizer_state *state)
741 {
742 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
743 struct si_pm4_state *pm4 = &rs->pm4;
744 unsigned tmp, i;
745 float psize_min, psize_max;
746
747 if (!rs) {
748 return NULL;
749 }
750
751 rs->scissor_enable = state->scissor;
752 rs->clip_halfz = state->clip_halfz;
753 rs->two_side = state->light_twoside;
754 rs->multisample_enable = state->multisample;
755 rs->force_persample_interp = state->force_persample_interp;
756 rs->clip_plane_enable = state->clip_plane_enable;
757 rs->line_stipple_enable = state->line_stipple_enable;
758 rs->poly_stipple_enable = state->poly_stipple_enable;
759 rs->line_smooth = state->line_smooth;
760 rs->poly_smooth = state->poly_smooth;
761 rs->uses_poly_offset = state->offset_point || state->offset_line ||
762 state->offset_tri;
763 rs->clamp_fragment_color = state->clamp_fragment_color;
764 rs->flatshade = state->flatshade;
765 rs->sprite_coord_enable = state->sprite_coord_enable;
766 rs->rasterizer_discard = state->rasterizer_discard;
767 rs->pa_sc_line_stipple = state->line_stipple_enable ?
768 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
769 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
770 rs->pa_cl_clip_cntl =
771 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
772 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
773 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
774 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
775 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
776
777 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
778 S_0286D4_FLAT_SHADE_ENA(1) |
779 S_0286D4_PNT_SPRITE_ENA(1) |
780 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
781 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
782 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
783 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
784 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
785
786 /* point size 12.4 fixed point */
787 tmp = (unsigned)(state->point_size * 8.0);
788 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
789
790 if (state->point_size_per_vertex) {
791 psize_min = util_get_min_point_size(state);
792 psize_max = 8192;
793 } else {
794 /* Force the point size to be as if the vertex output was disabled. */
795 psize_min = state->point_size;
796 psize_max = state->point_size;
797 }
798 /* Divide by two, because 0.5 = 1 pixel. */
799 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
800 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
801 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
802
803 tmp = (unsigned)state->line_width * 8;
804 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
805 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
806 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
807 S_028A48_MSAA_ENABLE(state->multisample ||
808 state->poly_smooth ||
809 state->line_smooth) |
810 S_028A48_VPORT_SCISSOR_ENABLE(1));
811
812 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
813 S_028BE4_PIX_CENTER(state->half_pixel_center) |
814 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
815
816 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
817 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
818 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
819 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
820 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
821 S_028814_FACE(!state->front_ccw) |
822 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
823 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
824 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
825 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
826 state->fill_back != PIPE_POLYGON_MODE_FILL) |
827 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
828 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
829 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
830 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
831
832 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
833 for (i = 0; i < 3; i++) {
834 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
835 float offset_units = state->offset_units;
836 float offset_scale = state->offset_scale * 16.0f;
837 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
838
839 if (!state->offset_units_unscaled) {
840 switch (i) {
841 case 0: /* 16-bit zbuffer */
842 offset_units *= 4.0f;
843 pa_su_poly_offset_db_fmt_cntl =
844 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
845 break;
846 case 1: /* 24-bit zbuffer */
847 offset_units *= 2.0f;
848 pa_su_poly_offset_db_fmt_cntl =
849 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
850 break;
851 case 2: /* 32-bit zbuffer */
852 offset_units *= 1.0f;
853 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
854 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
855 break;
856 }
857 }
858
859 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
860 fui(offset_scale));
861 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
862 fui(offset_units));
863 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
864 fui(offset_scale));
865 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
866 fui(offset_units));
867 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
868 pa_su_poly_offset_db_fmt_cntl);
869 }
870
871 return rs;
872 }
873
874 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
875 {
876 struct si_context *sctx = (struct si_context *)ctx;
877 struct si_state_rasterizer *old_rs =
878 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
879 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
880
881 if (!state)
882 return;
883
884 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
885 si_mark_atom_dirty(sctx, &sctx->db_render_state);
886
887 /* Update the small primitive filter workaround if necessary. */
888 if (sctx->b.family >= CHIP_POLARIS10 &&
889 sctx->framebuffer.nr_samples > 1)
890 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
891 }
892
893 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
894
895 si_pm4_bind_state(sctx, rasterizer, rs);
896 si_update_poly_offset_state(sctx);
897
898 si_mark_atom_dirty(sctx, &sctx->clip_regs);
899 sctx->do_update_shaders = true;
900 }
901
902 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
903 {
904 struct si_context *sctx = (struct si_context *)ctx;
905
906 if (sctx->queued.named.rasterizer == state)
907 si_pm4_bind_state(sctx, poly_offset, NULL);
908 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
909 }
910
911 /*
912 * infeered state between dsa and stencil ref
913 */
914 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
915 {
916 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
917 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
918 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
919
920 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
921 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
922 S_028430_STENCILMASK(dsa->valuemask[0]) |
923 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
924 S_028430_STENCILOPVAL(1));
925 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
926 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
927 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
928 S_028434_STENCILOPVAL_BF(1));
929 }
930
931 static void si_set_stencil_ref(struct pipe_context *ctx,
932 const struct pipe_stencil_ref *state)
933 {
934 struct si_context *sctx = (struct si_context *)ctx;
935
936 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
937 return;
938
939 sctx->stencil_ref.state = *state;
940 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
941 }
942
943
944 /*
945 * DSA
946 */
947
948 static uint32_t si_translate_stencil_op(int s_op)
949 {
950 switch (s_op) {
951 case PIPE_STENCIL_OP_KEEP:
952 return V_02842C_STENCIL_KEEP;
953 case PIPE_STENCIL_OP_ZERO:
954 return V_02842C_STENCIL_ZERO;
955 case PIPE_STENCIL_OP_REPLACE:
956 return V_02842C_STENCIL_REPLACE_TEST;
957 case PIPE_STENCIL_OP_INCR:
958 return V_02842C_STENCIL_ADD_CLAMP;
959 case PIPE_STENCIL_OP_DECR:
960 return V_02842C_STENCIL_SUB_CLAMP;
961 case PIPE_STENCIL_OP_INCR_WRAP:
962 return V_02842C_STENCIL_ADD_WRAP;
963 case PIPE_STENCIL_OP_DECR_WRAP:
964 return V_02842C_STENCIL_SUB_WRAP;
965 case PIPE_STENCIL_OP_INVERT:
966 return V_02842C_STENCIL_INVERT;
967 default:
968 R600_ERR("Unknown stencil op %d", s_op);
969 assert(0);
970 break;
971 }
972 return 0;
973 }
974
975 static void *si_create_dsa_state(struct pipe_context *ctx,
976 const struct pipe_depth_stencil_alpha_state *state)
977 {
978 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
979 struct si_pm4_state *pm4 = &dsa->pm4;
980 unsigned db_depth_control;
981 uint32_t db_stencil_control = 0;
982
983 if (!dsa) {
984 return NULL;
985 }
986
987 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
988 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
989 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
990 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
991
992 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
993 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
994 S_028800_ZFUNC(state->depth.func) |
995 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
996
997 /* stencil */
998 if (state->stencil[0].enabled) {
999 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1000 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1001 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1002 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1003 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1004
1005 if (state->stencil[1].enabled) {
1006 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1007 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1008 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1009 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1010 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1011 }
1012 }
1013
1014 /* alpha */
1015 if (state->alpha.enabled) {
1016 dsa->alpha_func = state->alpha.func;
1017
1018 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1019 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1020 } else {
1021 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1022 }
1023
1024 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1025 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1026 if (state->depth.bounds_test) {
1027 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1028 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1029 }
1030
1031 return dsa;
1032 }
1033
1034 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1035 {
1036 struct si_context *sctx = (struct si_context *)ctx;
1037 struct si_state_dsa *dsa = state;
1038
1039 if (!state)
1040 return;
1041
1042 si_pm4_bind_state(sctx, dsa, dsa);
1043
1044 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1045 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1046 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1047 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1048 }
1049 sctx->do_update_shaders = true;
1050 }
1051
1052 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1053 {
1054 struct si_context *sctx = (struct si_context *)ctx;
1055 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1056 }
1057
1058 static void *si_create_db_flush_dsa(struct si_context *sctx)
1059 {
1060 struct pipe_depth_stencil_alpha_state dsa = {};
1061
1062 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1063 }
1064
1065 /* DB RENDER STATE */
1066
1067 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1068 {
1069 struct si_context *sctx = (struct si_context*)ctx;
1070
1071 /* Pipeline stat & streamout queries. */
1072 if (enable) {
1073 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1074 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1075 } else {
1076 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1077 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1078 }
1079
1080 /* Occlusion queries. */
1081 if (sctx->occlusion_queries_disabled != !enable) {
1082 sctx->occlusion_queries_disabled = !enable;
1083 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1084 }
1085 }
1086
1087 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1088 {
1089 struct si_context *sctx = (struct si_context*)ctx;
1090
1091 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1092 }
1093
1094 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1095 {
1096 struct si_context *sctx = (struct si_context*)ctx;
1097
1098 st->saved_compute = sctx->cs_shader_state.program;
1099
1100 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1101 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1102 }
1103
1104 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1105 {
1106 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1107 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1108 unsigned db_shader_control;
1109
1110 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1111
1112 /* DB_RENDER_CONTROL */
1113 if (sctx->dbcb_depth_copy_enabled ||
1114 sctx->dbcb_stencil_copy_enabled) {
1115 radeon_emit(cs,
1116 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1117 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1118 S_028000_COPY_CENTROID(1) |
1119 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1120 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1121 radeon_emit(cs,
1122 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1123 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1124 } else {
1125 radeon_emit(cs,
1126 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1127 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1128 }
1129
1130 /* DB_COUNT_CONTROL (occlusion queries) */
1131 if (sctx->b.num_occlusion_queries > 0 &&
1132 !sctx->occlusion_queries_disabled) {
1133 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1134
1135 if (sctx->b.chip_class >= CIK) {
1136 radeon_emit(cs,
1137 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1138 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1139 S_028004_ZPASS_ENABLE(1) |
1140 S_028004_SLICE_EVEN_ENABLE(1) |
1141 S_028004_SLICE_ODD_ENABLE(1));
1142 } else {
1143 radeon_emit(cs,
1144 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1145 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1146 }
1147 } else {
1148 /* Disable occlusion queries. */
1149 if (sctx->b.chip_class >= CIK) {
1150 radeon_emit(cs, 0);
1151 } else {
1152 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1153 }
1154 }
1155
1156 /* DB_RENDER_OVERRIDE2 */
1157 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1158 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1159 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1160 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1161
1162 db_shader_control = sctx->ps_db_shader_control;
1163
1164 /* Bug workaround for smoothing (overrasterization) on SI. */
1165 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1166 db_shader_control &= C_02880C_Z_ORDER;
1167 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1168 }
1169
1170 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1171 if (!rs || !rs->multisample_enable)
1172 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1173
1174 if (sctx->b.family == CHIP_STONEY &&
1175 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1176 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1177
1178 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1179 db_shader_control);
1180 }
1181
1182 /*
1183 * format translation
1184 */
1185 static uint32_t si_translate_colorformat(enum pipe_format format)
1186 {
1187 const struct util_format_description *desc = util_format_description(format);
1188
1189 #define HAS_SIZE(x,y,z,w) \
1190 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1191 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1192
1193 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1194 return V_028C70_COLOR_10_11_11;
1195
1196 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1197 return V_028C70_COLOR_INVALID;
1198
1199 /* hw cannot support mixed formats (except depth/stencil, since
1200 * stencil is not written to). */
1201 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1202 return V_028C70_COLOR_INVALID;
1203
1204 switch (desc->nr_channels) {
1205 case 1:
1206 switch (desc->channel[0].size) {
1207 case 8:
1208 return V_028C70_COLOR_8;
1209 case 16:
1210 return V_028C70_COLOR_16;
1211 case 32:
1212 return V_028C70_COLOR_32;
1213 }
1214 break;
1215 case 2:
1216 if (desc->channel[0].size == desc->channel[1].size) {
1217 switch (desc->channel[0].size) {
1218 case 8:
1219 return V_028C70_COLOR_8_8;
1220 case 16:
1221 return V_028C70_COLOR_16_16;
1222 case 32:
1223 return V_028C70_COLOR_32_32;
1224 }
1225 } else if (HAS_SIZE(8,24,0,0)) {
1226 return V_028C70_COLOR_24_8;
1227 } else if (HAS_SIZE(24,8,0,0)) {
1228 return V_028C70_COLOR_8_24;
1229 }
1230 break;
1231 case 3:
1232 if (HAS_SIZE(5,6,5,0)) {
1233 return V_028C70_COLOR_5_6_5;
1234 } else if (HAS_SIZE(32,8,24,0)) {
1235 return V_028C70_COLOR_X24_8_32_FLOAT;
1236 }
1237 break;
1238 case 4:
1239 if (desc->channel[0].size == desc->channel[1].size &&
1240 desc->channel[0].size == desc->channel[2].size &&
1241 desc->channel[0].size == desc->channel[3].size) {
1242 switch (desc->channel[0].size) {
1243 case 4:
1244 return V_028C70_COLOR_4_4_4_4;
1245 case 8:
1246 return V_028C70_COLOR_8_8_8_8;
1247 case 16:
1248 return V_028C70_COLOR_16_16_16_16;
1249 case 32:
1250 return V_028C70_COLOR_32_32_32_32;
1251 }
1252 } else if (HAS_SIZE(5,5,5,1)) {
1253 return V_028C70_COLOR_1_5_5_5;
1254 } else if (HAS_SIZE(10,10,10,2)) {
1255 return V_028C70_COLOR_2_10_10_10;
1256 }
1257 break;
1258 }
1259 return V_028C70_COLOR_INVALID;
1260 }
1261
1262 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1263 {
1264 if (SI_BIG_ENDIAN) {
1265 switch(colorformat) {
1266 /* 8-bit buffers. */
1267 case V_028C70_COLOR_8:
1268 return V_028C70_ENDIAN_NONE;
1269
1270 /* 16-bit buffers. */
1271 case V_028C70_COLOR_5_6_5:
1272 case V_028C70_COLOR_1_5_5_5:
1273 case V_028C70_COLOR_4_4_4_4:
1274 case V_028C70_COLOR_16:
1275 case V_028C70_COLOR_8_8:
1276 return V_028C70_ENDIAN_8IN16;
1277
1278 /* 32-bit buffers. */
1279 case V_028C70_COLOR_8_8_8_8:
1280 case V_028C70_COLOR_2_10_10_10:
1281 case V_028C70_COLOR_8_24:
1282 case V_028C70_COLOR_24_8:
1283 case V_028C70_COLOR_16_16:
1284 return V_028C70_ENDIAN_8IN32;
1285
1286 /* 64-bit buffers. */
1287 case V_028C70_COLOR_16_16_16_16:
1288 return V_028C70_ENDIAN_8IN16;
1289
1290 case V_028C70_COLOR_32_32:
1291 return V_028C70_ENDIAN_8IN32;
1292
1293 /* 128-bit buffers. */
1294 case V_028C70_COLOR_32_32_32_32:
1295 return V_028C70_ENDIAN_8IN32;
1296 default:
1297 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1298 }
1299 } else {
1300 return V_028C70_ENDIAN_NONE;
1301 }
1302 }
1303
1304 static uint32_t si_translate_dbformat(enum pipe_format format)
1305 {
1306 switch (format) {
1307 case PIPE_FORMAT_Z16_UNORM:
1308 return V_028040_Z_16;
1309 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1310 case PIPE_FORMAT_X8Z24_UNORM:
1311 case PIPE_FORMAT_Z24X8_UNORM:
1312 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1313 return V_028040_Z_24; /* deprecated on SI */
1314 case PIPE_FORMAT_Z32_FLOAT:
1315 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1316 return V_028040_Z_32_FLOAT;
1317 default:
1318 return V_028040_Z_INVALID;
1319 }
1320 }
1321
1322 /*
1323 * Texture translation
1324 */
1325
1326 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1327 enum pipe_format format,
1328 const struct util_format_description *desc,
1329 int first_non_void)
1330 {
1331 struct si_screen *sscreen = (struct si_screen*)screen;
1332 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1333 sscreen->b.info.drm_minor >= 31) ||
1334 sscreen->b.info.drm_major == 3;
1335 bool uniform = true;
1336 int i;
1337
1338 /* Colorspace (return non-RGB formats directly). */
1339 switch (desc->colorspace) {
1340 /* Depth stencil formats */
1341 case UTIL_FORMAT_COLORSPACE_ZS:
1342 switch (format) {
1343 case PIPE_FORMAT_Z16_UNORM:
1344 return V_008F14_IMG_DATA_FORMAT_16;
1345 case PIPE_FORMAT_X24S8_UINT:
1346 case PIPE_FORMAT_Z24X8_UNORM:
1347 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1348 return V_008F14_IMG_DATA_FORMAT_8_24;
1349 case PIPE_FORMAT_X8Z24_UNORM:
1350 case PIPE_FORMAT_S8X24_UINT:
1351 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1352 return V_008F14_IMG_DATA_FORMAT_24_8;
1353 case PIPE_FORMAT_S8_UINT:
1354 return V_008F14_IMG_DATA_FORMAT_8;
1355 case PIPE_FORMAT_Z32_FLOAT:
1356 return V_008F14_IMG_DATA_FORMAT_32;
1357 case PIPE_FORMAT_X32_S8X24_UINT:
1358 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1359 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1360 default:
1361 goto out_unknown;
1362 }
1363
1364 case UTIL_FORMAT_COLORSPACE_YUV:
1365 goto out_unknown; /* TODO */
1366
1367 case UTIL_FORMAT_COLORSPACE_SRGB:
1368 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1369 goto out_unknown;
1370 break;
1371
1372 default:
1373 break;
1374 }
1375
1376 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1377 if (!enable_compressed_formats)
1378 goto out_unknown;
1379
1380 switch (format) {
1381 case PIPE_FORMAT_RGTC1_SNORM:
1382 case PIPE_FORMAT_LATC1_SNORM:
1383 case PIPE_FORMAT_RGTC1_UNORM:
1384 case PIPE_FORMAT_LATC1_UNORM:
1385 return V_008F14_IMG_DATA_FORMAT_BC4;
1386 case PIPE_FORMAT_RGTC2_SNORM:
1387 case PIPE_FORMAT_LATC2_SNORM:
1388 case PIPE_FORMAT_RGTC2_UNORM:
1389 case PIPE_FORMAT_LATC2_UNORM:
1390 return V_008F14_IMG_DATA_FORMAT_BC5;
1391 default:
1392 goto out_unknown;
1393 }
1394 }
1395
1396 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1397 sscreen->b.family == CHIP_STONEY) {
1398 switch (format) {
1399 case PIPE_FORMAT_ETC1_RGB8:
1400 case PIPE_FORMAT_ETC2_RGB8:
1401 case PIPE_FORMAT_ETC2_SRGB8:
1402 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1403 case PIPE_FORMAT_ETC2_RGB8A1:
1404 case PIPE_FORMAT_ETC2_SRGB8A1:
1405 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1406 case PIPE_FORMAT_ETC2_RGBA8:
1407 case PIPE_FORMAT_ETC2_SRGBA8:
1408 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1409 case PIPE_FORMAT_ETC2_R11_UNORM:
1410 case PIPE_FORMAT_ETC2_R11_SNORM:
1411 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1412 case PIPE_FORMAT_ETC2_RG11_UNORM:
1413 case PIPE_FORMAT_ETC2_RG11_SNORM:
1414 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1415 default:
1416 goto out_unknown;
1417 }
1418 }
1419
1420 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1421 if (!enable_compressed_formats)
1422 goto out_unknown;
1423
1424 switch (format) {
1425 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1426 case PIPE_FORMAT_BPTC_SRGBA:
1427 return V_008F14_IMG_DATA_FORMAT_BC7;
1428 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1429 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1430 return V_008F14_IMG_DATA_FORMAT_BC6;
1431 default:
1432 goto out_unknown;
1433 }
1434 }
1435
1436 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1437 switch (format) {
1438 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1439 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1440 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1441 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1442 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1443 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1444 default:
1445 goto out_unknown;
1446 }
1447 }
1448
1449 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1450 if (!enable_compressed_formats)
1451 goto out_unknown;
1452
1453 if (!util_format_s3tc_enabled) {
1454 goto out_unknown;
1455 }
1456
1457 switch (format) {
1458 case PIPE_FORMAT_DXT1_RGB:
1459 case PIPE_FORMAT_DXT1_RGBA:
1460 case PIPE_FORMAT_DXT1_SRGB:
1461 case PIPE_FORMAT_DXT1_SRGBA:
1462 return V_008F14_IMG_DATA_FORMAT_BC1;
1463 case PIPE_FORMAT_DXT3_RGBA:
1464 case PIPE_FORMAT_DXT3_SRGBA:
1465 return V_008F14_IMG_DATA_FORMAT_BC2;
1466 case PIPE_FORMAT_DXT5_RGBA:
1467 case PIPE_FORMAT_DXT5_SRGBA:
1468 return V_008F14_IMG_DATA_FORMAT_BC3;
1469 default:
1470 goto out_unknown;
1471 }
1472 }
1473
1474 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1475 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1476 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1477 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1478 }
1479
1480 /* R8G8Bx_SNORM - TODO CxV8U8 */
1481
1482 /* hw cannot support mixed formats (except depth/stencil, since only
1483 * depth is read).*/
1484 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1485 goto out_unknown;
1486
1487 /* See whether the components are of the same size. */
1488 for (i = 1; i < desc->nr_channels; i++) {
1489 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1490 }
1491
1492 /* Non-uniform formats. */
1493 if (!uniform) {
1494 switch(desc->nr_channels) {
1495 case 3:
1496 if (desc->channel[0].size == 5 &&
1497 desc->channel[1].size == 6 &&
1498 desc->channel[2].size == 5) {
1499 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1500 }
1501 goto out_unknown;
1502 case 4:
1503 if (desc->channel[0].size == 5 &&
1504 desc->channel[1].size == 5 &&
1505 desc->channel[2].size == 5 &&
1506 desc->channel[3].size == 1) {
1507 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1508 }
1509 if (desc->channel[0].size == 10 &&
1510 desc->channel[1].size == 10 &&
1511 desc->channel[2].size == 10 &&
1512 desc->channel[3].size == 2) {
1513 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1514 }
1515 goto out_unknown;
1516 }
1517 goto out_unknown;
1518 }
1519
1520 if (first_non_void < 0 || first_non_void > 3)
1521 goto out_unknown;
1522
1523 /* uniform formats */
1524 switch (desc->channel[first_non_void].size) {
1525 case 4:
1526 switch (desc->nr_channels) {
1527 #if 0 /* Not supported for render targets */
1528 case 2:
1529 return V_008F14_IMG_DATA_FORMAT_4_4;
1530 #endif
1531 case 4:
1532 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1533 }
1534 break;
1535 case 8:
1536 switch (desc->nr_channels) {
1537 case 1:
1538 return V_008F14_IMG_DATA_FORMAT_8;
1539 case 2:
1540 return V_008F14_IMG_DATA_FORMAT_8_8;
1541 case 4:
1542 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1543 }
1544 break;
1545 case 16:
1546 switch (desc->nr_channels) {
1547 case 1:
1548 return V_008F14_IMG_DATA_FORMAT_16;
1549 case 2:
1550 return V_008F14_IMG_DATA_FORMAT_16_16;
1551 case 4:
1552 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1553 }
1554 break;
1555 case 32:
1556 switch (desc->nr_channels) {
1557 case 1:
1558 return V_008F14_IMG_DATA_FORMAT_32;
1559 case 2:
1560 return V_008F14_IMG_DATA_FORMAT_32_32;
1561 #if 0 /* Not supported for render targets */
1562 case 3:
1563 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1564 #endif
1565 case 4:
1566 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1567 }
1568 }
1569
1570 out_unknown:
1571 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1572 return ~0;
1573 }
1574
1575 static unsigned si_tex_wrap(unsigned wrap)
1576 {
1577 switch (wrap) {
1578 default:
1579 case PIPE_TEX_WRAP_REPEAT:
1580 return V_008F30_SQ_TEX_WRAP;
1581 case PIPE_TEX_WRAP_CLAMP:
1582 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1583 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1584 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1585 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1586 return V_008F30_SQ_TEX_CLAMP_BORDER;
1587 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1588 return V_008F30_SQ_TEX_MIRROR;
1589 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1590 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1591 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1592 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1593 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1594 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1595 }
1596 }
1597
1598 static unsigned si_tex_mipfilter(unsigned filter)
1599 {
1600 switch (filter) {
1601 case PIPE_TEX_MIPFILTER_NEAREST:
1602 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1603 case PIPE_TEX_MIPFILTER_LINEAR:
1604 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1605 default:
1606 case PIPE_TEX_MIPFILTER_NONE:
1607 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1608 }
1609 }
1610
1611 static unsigned si_tex_compare(unsigned compare)
1612 {
1613 switch (compare) {
1614 default:
1615 case PIPE_FUNC_NEVER:
1616 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1617 case PIPE_FUNC_LESS:
1618 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1619 case PIPE_FUNC_EQUAL:
1620 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1621 case PIPE_FUNC_LEQUAL:
1622 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1623 case PIPE_FUNC_GREATER:
1624 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1625 case PIPE_FUNC_NOTEQUAL:
1626 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1627 case PIPE_FUNC_GEQUAL:
1628 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1629 case PIPE_FUNC_ALWAYS:
1630 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1631 }
1632 }
1633
1634 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1635 unsigned nr_samples)
1636 {
1637 if (view_target == PIPE_TEXTURE_CUBE ||
1638 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1639 res_target = view_target;
1640 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1641 else if (res_target == PIPE_TEXTURE_CUBE ||
1642 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1643 res_target = PIPE_TEXTURE_2D_ARRAY;
1644
1645 switch (res_target) {
1646 default:
1647 case PIPE_TEXTURE_1D:
1648 return V_008F1C_SQ_RSRC_IMG_1D;
1649 case PIPE_TEXTURE_1D_ARRAY:
1650 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1651 case PIPE_TEXTURE_2D:
1652 case PIPE_TEXTURE_RECT:
1653 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1654 V_008F1C_SQ_RSRC_IMG_2D;
1655 case PIPE_TEXTURE_2D_ARRAY:
1656 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1657 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1658 case PIPE_TEXTURE_3D:
1659 return V_008F1C_SQ_RSRC_IMG_3D;
1660 case PIPE_TEXTURE_CUBE:
1661 case PIPE_TEXTURE_CUBE_ARRAY:
1662 return V_008F1C_SQ_RSRC_IMG_CUBE;
1663 }
1664 }
1665
1666 /*
1667 * Format support testing
1668 */
1669
1670 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1671 {
1672 return si_translate_texformat(screen, format, util_format_description(format),
1673 util_format_get_first_non_void_channel(format)) != ~0U;
1674 }
1675
1676 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1677 const struct util_format_description *desc,
1678 int first_non_void)
1679 {
1680 unsigned type;
1681 int i;
1682
1683 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1684 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1685
1686 assert(first_non_void >= 0);
1687 type = desc->channel[first_non_void].type;
1688
1689 if (type == UTIL_FORMAT_TYPE_FIXED)
1690 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1691
1692 if (desc->nr_channels == 4 &&
1693 desc->channel[0].size == 10 &&
1694 desc->channel[1].size == 10 &&
1695 desc->channel[2].size == 10 &&
1696 desc->channel[3].size == 2)
1697 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1698
1699 /* See whether the components are of the same size. */
1700 for (i = 0; i < desc->nr_channels; i++) {
1701 if (desc->channel[first_non_void].size != desc->channel[i].size)
1702 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1703 }
1704
1705 switch (desc->channel[first_non_void].size) {
1706 case 8:
1707 switch (desc->nr_channels) {
1708 case 1:
1709 return V_008F0C_BUF_DATA_FORMAT_8;
1710 case 2:
1711 return V_008F0C_BUF_DATA_FORMAT_8_8;
1712 case 3:
1713 case 4:
1714 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1715 }
1716 break;
1717 case 16:
1718 switch (desc->nr_channels) {
1719 case 1:
1720 return V_008F0C_BUF_DATA_FORMAT_16;
1721 case 2:
1722 return V_008F0C_BUF_DATA_FORMAT_16_16;
1723 case 3:
1724 case 4:
1725 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1726 }
1727 break;
1728 case 32:
1729 /* From the Southern Islands ISA documentation about MTBUF:
1730 * 'Memory reads of data in memory that is 32 or 64 bits do not
1731 * undergo any format conversion.'
1732 */
1733 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1734 !desc->channel[first_non_void].pure_integer)
1735 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1736
1737 switch (desc->nr_channels) {
1738 case 1:
1739 return V_008F0C_BUF_DATA_FORMAT_32;
1740 case 2:
1741 return V_008F0C_BUF_DATA_FORMAT_32_32;
1742 case 3:
1743 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1744 case 4:
1745 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1746 }
1747 break;
1748 }
1749
1750 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1751 }
1752
1753 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1754 const struct util_format_description *desc,
1755 int first_non_void)
1756 {
1757 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1758 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1759
1760 assert(first_non_void >= 0);
1761
1762 switch (desc->channel[first_non_void].type) {
1763 case UTIL_FORMAT_TYPE_SIGNED:
1764 if (desc->channel[first_non_void].normalized)
1765 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1766 else if (desc->channel[first_non_void].pure_integer)
1767 return V_008F0C_BUF_NUM_FORMAT_SINT;
1768 else
1769 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1770 break;
1771 case UTIL_FORMAT_TYPE_UNSIGNED:
1772 if (desc->channel[first_non_void].normalized)
1773 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1774 else if (desc->channel[first_non_void].pure_integer)
1775 return V_008F0C_BUF_NUM_FORMAT_UINT;
1776 else
1777 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1778 break;
1779 case UTIL_FORMAT_TYPE_FLOAT:
1780 default:
1781 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1782 }
1783 }
1784
1785 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1786 enum pipe_format format,
1787 unsigned usage)
1788 {
1789 const struct util_format_description *desc;
1790 int first_non_void;
1791 unsigned data_format;
1792
1793 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1794 PIPE_BIND_SAMPLER_VIEW |
1795 PIPE_BIND_VERTEX_BUFFER)) == 0);
1796
1797 desc = util_format_description(format);
1798
1799 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1800 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1801 * for read-only access (with caveats surrounding bounds checks), but
1802 * obviously fails for write access which we have to implement for
1803 * shader images. Luckily, OpenGL doesn't expect this to be supported
1804 * anyway, and so the only impact is on PBO uploads / downloads, which
1805 * shouldn't be expected to be fast for GL_RGB anyway.
1806 */
1807 if (desc->block.bits == 3 * 8 ||
1808 desc->block.bits == 3 * 16) {
1809 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1810 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1811 if (!usage)
1812 return 0;
1813 }
1814 }
1815
1816 first_non_void = util_format_get_first_non_void_channel(format);
1817 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1818 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1819 return 0;
1820
1821 return usage;
1822 }
1823
1824 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1825 {
1826 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1827 r600_translate_colorswap(format, false) != ~0U;
1828 }
1829
1830 static bool si_is_zs_format_supported(enum pipe_format format)
1831 {
1832 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1833 }
1834
1835 static boolean si_is_format_supported(struct pipe_screen *screen,
1836 enum pipe_format format,
1837 enum pipe_texture_target target,
1838 unsigned sample_count,
1839 unsigned usage)
1840 {
1841 unsigned retval = 0;
1842
1843 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1844 R600_ERR("r600: unsupported texture type %d\n", target);
1845 return false;
1846 }
1847
1848 if (!util_format_is_supported(format, usage))
1849 return false;
1850
1851 if (sample_count > 1) {
1852 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1853 return false;
1854
1855 if (usage & PIPE_BIND_SHADER_IMAGE)
1856 return false;
1857
1858 switch (sample_count) {
1859 case 2:
1860 case 4:
1861 case 8:
1862 break;
1863 case 16:
1864 if (format == PIPE_FORMAT_NONE)
1865 return true;
1866 else
1867 return false;
1868 default:
1869 return false;
1870 }
1871 }
1872
1873 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1874 PIPE_BIND_SHADER_IMAGE)) {
1875 if (target == PIPE_BUFFER) {
1876 retval |= si_is_vertex_format_supported(
1877 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1878 PIPE_BIND_SHADER_IMAGE));
1879 } else {
1880 if (si_is_sampler_format_supported(screen, format))
1881 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1882 PIPE_BIND_SHADER_IMAGE);
1883 }
1884 }
1885
1886 if ((usage & (PIPE_BIND_RENDER_TARGET |
1887 PIPE_BIND_DISPLAY_TARGET |
1888 PIPE_BIND_SCANOUT |
1889 PIPE_BIND_SHARED |
1890 PIPE_BIND_BLENDABLE)) &&
1891 si_is_colorbuffer_format_supported(format)) {
1892 retval |= usage &
1893 (PIPE_BIND_RENDER_TARGET |
1894 PIPE_BIND_DISPLAY_TARGET |
1895 PIPE_BIND_SCANOUT |
1896 PIPE_BIND_SHARED);
1897 if (!util_format_is_pure_integer(format) &&
1898 !util_format_is_depth_or_stencil(format))
1899 retval |= usage & PIPE_BIND_BLENDABLE;
1900 }
1901
1902 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1903 si_is_zs_format_supported(format)) {
1904 retval |= PIPE_BIND_DEPTH_STENCIL;
1905 }
1906
1907 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1908 retval |= si_is_vertex_format_supported(screen, format,
1909 PIPE_BIND_VERTEX_BUFFER);
1910 }
1911
1912 if ((usage & PIPE_BIND_LINEAR) &&
1913 !util_format_is_compressed(format) &&
1914 !(usage & PIPE_BIND_DEPTH_STENCIL))
1915 retval |= PIPE_BIND_LINEAR;
1916
1917 return retval == usage;
1918 }
1919
1920 /*
1921 * framebuffer handling
1922 */
1923
1924 static void si_choose_spi_color_formats(struct r600_surface *surf,
1925 unsigned format, unsigned swap,
1926 unsigned ntype, bool is_depth)
1927 {
1928 /* Alpha is needed for alpha-to-coverage.
1929 * Blending may be with or without alpha.
1930 */
1931 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1932 unsigned alpha = 0; /* exports alpha, but may not support blending */
1933 unsigned blend = 0; /* supports blending, but may not export alpha */
1934 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1935
1936 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1937 * Other chips have multiple choices, though they are not necessarily better.
1938 */
1939 switch (format) {
1940 case V_028C70_COLOR_5_6_5:
1941 case V_028C70_COLOR_1_5_5_5:
1942 case V_028C70_COLOR_5_5_5_1:
1943 case V_028C70_COLOR_4_4_4_4:
1944 case V_028C70_COLOR_10_11_11:
1945 case V_028C70_COLOR_11_11_10:
1946 case V_028C70_COLOR_8:
1947 case V_028C70_COLOR_8_8:
1948 case V_028C70_COLOR_8_8_8_8:
1949 case V_028C70_COLOR_10_10_10_2:
1950 case V_028C70_COLOR_2_10_10_10:
1951 if (ntype == V_028C70_NUMBER_UINT)
1952 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1953 else if (ntype == V_028C70_NUMBER_SINT)
1954 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1955 else
1956 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1957 break;
1958
1959 case V_028C70_COLOR_16:
1960 case V_028C70_COLOR_16_16:
1961 case V_028C70_COLOR_16_16_16_16:
1962 if (ntype == V_028C70_NUMBER_UNORM ||
1963 ntype == V_028C70_NUMBER_SNORM) {
1964 /* UNORM16 and SNORM16 don't support blending */
1965 if (ntype == V_028C70_NUMBER_UNORM)
1966 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1967 else
1968 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1969
1970 /* Use 32 bits per channel for blending. */
1971 if (format == V_028C70_COLOR_16) {
1972 if (swap == V_028C70_SWAP_STD) { /* R */
1973 blend = V_028714_SPI_SHADER_32_R;
1974 blend_alpha = V_028714_SPI_SHADER_32_AR;
1975 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1976 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1977 else
1978 assert(0);
1979 } else if (format == V_028C70_COLOR_16_16) {
1980 if (swap == V_028C70_SWAP_STD) { /* RG */
1981 blend = V_028714_SPI_SHADER_32_GR;
1982 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1983 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1984 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1985 else
1986 assert(0);
1987 } else /* 16_16_16_16 */
1988 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1989 } else if (ntype == V_028C70_NUMBER_UINT)
1990 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1991 else if (ntype == V_028C70_NUMBER_SINT)
1992 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1993 else if (ntype == V_028C70_NUMBER_FLOAT)
1994 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1995 else
1996 assert(0);
1997 break;
1998
1999 case V_028C70_COLOR_32:
2000 if (swap == V_028C70_SWAP_STD) { /* R */
2001 blend = normal = V_028714_SPI_SHADER_32_R;
2002 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2003 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2004 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2005 else
2006 assert(0);
2007 break;
2008
2009 case V_028C70_COLOR_32_32:
2010 if (swap == V_028C70_SWAP_STD) { /* RG */
2011 blend = normal = V_028714_SPI_SHADER_32_GR;
2012 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2013 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2014 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2015 else
2016 assert(0);
2017 break;
2018
2019 case V_028C70_COLOR_32_32_32_32:
2020 case V_028C70_COLOR_8_24:
2021 case V_028C70_COLOR_24_8:
2022 case V_028C70_COLOR_X24_8_32_FLOAT:
2023 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2024 break;
2025
2026 default:
2027 assert(0);
2028 return;
2029 }
2030
2031 /* The DB->CB copy needs 32_ABGR. */
2032 if (is_depth)
2033 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2034
2035 surf->spi_shader_col_format = normal;
2036 surf->spi_shader_col_format_alpha = alpha;
2037 surf->spi_shader_col_format_blend = blend;
2038 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2039 }
2040
2041 static void si_initialize_color_surface(struct si_context *sctx,
2042 struct r600_surface *surf)
2043 {
2044 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2045 unsigned color_info, color_attrib, color_view;
2046 unsigned format, swap, ntype, endian;
2047 const struct util_format_description *desc;
2048 int i;
2049 unsigned blend_clamp = 0, blend_bypass = 0;
2050
2051 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2052 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2053
2054 desc = util_format_description(surf->base.format);
2055 for (i = 0; i < 4; i++) {
2056 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2057 break;
2058 }
2059 }
2060 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2061 ntype = V_028C70_NUMBER_FLOAT;
2062 } else {
2063 ntype = V_028C70_NUMBER_UNORM;
2064 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2065 ntype = V_028C70_NUMBER_SRGB;
2066 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2067 if (desc->channel[i].pure_integer) {
2068 ntype = V_028C70_NUMBER_SINT;
2069 } else {
2070 assert(desc->channel[i].normalized);
2071 ntype = V_028C70_NUMBER_SNORM;
2072 }
2073 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2074 if (desc->channel[i].pure_integer) {
2075 ntype = V_028C70_NUMBER_UINT;
2076 } else {
2077 assert(desc->channel[i].normalized);
2078 ntype = V_028C70_NUMBER_UNORM;
2079 }
2080 }
2081 }
2082
2083 format = si_translate_colorformat(surf->base.format);
2084 if (format == V_028C70_COLOR_INVALID) {
2085 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2086 }
2087 assert(format != V_028C70_COLOR_INVALID);
2088 swap = r600_translate_colorswap(surf->base.format, false);
2089 endian = si_colorformat_endian_swap(format);
2090
2091 /* blend clamp should be set for all NORM/SRGB types */
2092 if (ntype == V_028C70_NUMBER_UNORM ||
2093 ntype == V_028C70_NUMBER_SNORM ||
2094 ntype == V_028C70_NUMBER_SRGB)
2095 blend_clamp = 1;
2096
2097 /* set blend bypass according to docs if SINT/UINT or
2098 8/24 COLOR variants */
2099 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2100 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2101 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2102 blend_clamp = 0;
2103 blend_bypass = 1;
2104 }
2105
2106 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2107 (format == V_028C70_COLOR_8 ||
2108 format == V_028C70_COLOR_8_8 ||
2109 format == V_028C70_COLOR_8_8_8_8))
2110 surf->color_is_int8 = true;
2111
2112 color_info = S_028C70_FORMAT(format) |
2113 S_028C70_COMP_SWAP(swap) |
2114 S_028C70_BLEND_CLAMP(blend_clamp) |
2115 S_028C70_BLEND_BYPASS(blend_bypass) |
2116 S_028C70_SIMPLE_FLOAT(1) |
2117 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2118 ntype != V_028C70_NUMBER_SNORM &&
2119 ntype != V_028C70_NUMBER_SRGB &&
2120 format != V_028C70_COLOR_8_24 &&
2121 format != V_028C70_COLOR_24_8) |
2122 S_028C70_NUMBER_TYPE(ntype) |
2123 S_028C70_ENDIAN(endian);
2124
2125 /* Intensity is implemented as Red, so treat it that way. */
2126 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2127 util_format_is_intensity(surf->base.format));
2128
2129 if (rtex->resource.b.b.nr_samples > 1) {
2130 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2131
2132 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2133 S_028C74_NUM_FRAGMENTS(log_samples);
2134
2135 if (rtex->fmask.size) {
2136 color_info |= S_028C70_COMPRESSION(1);
2137 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2138
2139 if (sctx->b.chip_class == SI) {
2140 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2141 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2142 }
2143 }
2144 }
2145
2146 surf->cb_color_view = color_view;
2147 surf->cb_color_info = color_info;
2148 surf->cb_color_attrib = color_attrib;
2149
2150 if (sctx->b.chip_class >= VI) {
2151 unsigned max_uncompressed_block_size = 2;
2152
2153 if (rtex->resource.b.b.nr_samples > 1) {
2154 if (rtex->surface.bpe == 1)
2155 max_uncompressed_block_size = 0;
2156 else if (rtex->surface.bpe == 2)
2157 max_uncompressed_block_size = 1;
2158 }
2159
2160 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2161 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2162 }
2163
2164 /* This must be set for fast clear to work without FMASK. */
2165 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2166 unsigned bankh = util_logbase2(rtex->surface.bankh);
2167 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2168 }
2169
2170 /* Determine pixel shader export format */
2171 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2172
2173 surf->color_initialized = true;
2174 }
2175
2176 static void si_init_depth_surface(struct si_context *sctx,
2177 struct r600_surface *surf)
2178 {
2179 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2180 unsigned level = surf->base.u.tex.level;
2181 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2182 unsigned format;
2183 uint32_t z_info, s_info, db_depth_info;
2184 uint64_t z_offs, s_offs;
2185 uint32_t db_htile_data_base, db_htile_surface;
2186
2187 format = si_translate_dbformat(rtex->db_render_format);
2188
2189 if (format == V_028040_Z_INVALID) {
2190 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2191 }
2192 assert(format != V_028040_Z_INVALID);
2193
2194 s_offs = z_offs = rtex->resource.gpu_address;
2195 z_offs += rtex->surface.level[level].offset;
2196 s_offs += rtex->surface.stencil_level[level].offset;
2197
2198 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2199
2200 z_info = S_028040_FORMAT(format);
2201 if (rtex->resource.b.b.nr_samples > 1) {
2202 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2203 }
2204
2205 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2206 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2207 else
2208 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2209
2210 if (sctx->b.chip_class >= CIK) {
2211 struct radeon_info *info = &sctx->screen->b.info;
2212 unsigned index = rtex->surface.tiling_index[level];
2213 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2214 unsigned macro_index = rtex->surface.macro_tile_index;
2215 unsigned tile_mode = info->si_tile_mode_array[index];
2216 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2217 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2218
2219 db_depth_info |=
2220 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2221 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2222 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2223 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2224 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2225 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2226 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2227 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2228 } else {
2229 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2230 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2231 tile_mode_index = si_tile_mode_index(rtex, level, true);
2232 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2233 }
2234
2235 /* HiZ aka depth buffer htile */
2236 /* use htile only for first level */
2237 if (rtex->htile_buffer && !level) {
2238 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2239 S_028040_ALLOW_EXPCLEAR(1);
2240
2241 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2242 /* Workaround: For a not yet understood reason, the
2243 * combination of MSAA, fast stencil clear and stencil
2244 * decompress messes with subsequent stencil buffer
2245 * uses. Problem was reproduced on Verde, Bonaire,
2246 * Tonga, and Carrizo.
2247 *
2248 * Disabling EXPCLEAR works around the problem.
2249 *
2250 * Check piglit's arb_texture_multisample-stencil-clear
2251 * test if you want to try changing this.
2252 */
2253 if (rtex->resource.b.b.nr_samples <= 1)
2254 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2255 } else if (!rtex->tc_compatible_htile) {
2256 /* Use all of the htile_buffer for depth if there's no stencil.
2257 * This must not be set when TC-compatible HTILE is enabled
2258 * due to a hw bug.
2259 */
2260 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2261 }
2262
2263 uint64_t va = rtex->htile_buffer->gpu_address;
2264 db_htile_data_base = va >> 8;
2265 db_htile_surface = S_028ABC_FULL_CACHE(1);
2266
2267 if (rtex->tc_compatible_htile) {
2268 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2269
2270 switch (rtex->resource.b.b.nr_samples) {
2271 case 0:
2272 case 1:
2273 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2274 break;
2275 case 2:
2276 case 4:
2277 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2278 break;
2279 case 8:
2280 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2281 break;
2282 default:
2283 assert(0);
2284 }
2285 }
2286 } else {
2287 db_htile_data_base = 0;
2288 db_htile_surface = 0;
2289 }
2290
2291 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2292
2293 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2294 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2295 surf->db_htile_data_base = db_htile_data_base;
2296 surf->db_depth_info = db_depth_info;
2297 surf->db_z_info = z_info;
2298 surf->db_stencil_info = s_info;
2299 surf->db_depth_base = z_offs >> 8;
2300 surf->db_stencil_base = s_offs >> 8;
2301 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2302 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2303 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2304 levelinfo->nblk_y) / 64 - 1);
2305 surf->db_htile_surface = db_htile_surface;
2306
2307 surf->depth_initialized = true;
2308 }
2309
2310 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2311 {
2312 for (int i = 0; i < state->nr_cbufs; ++i) {
2313 struct r600_surface *surf = NULL;
2314 struct r600_texture *rtex;
2315
2316 if (!state->cbufs[i])
2317 continue;
2318 surf = (struct r600_surface*)state->cbufs[i];
2319 rtex = (struct r600_texture*)surf->base.texture;
2320
2321 p_atomic_dec(&rtex->framebuffers_bound);
2322 }
2323 }
2324
2325 static void si_set_framebuffer_state(struct pipe_context *ctx,
2326 const struct pipe_framebuffer_state *state)
2327 {
2328 struct si_context *sctx = (struct si_context *)ctx;
2329 struct pipe_constant_buffer constbuf = {0};
2330 struct r600_surface *surf = NULL;
2331 struct r600_texture *rtex;
2332 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2333 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2334 int i;
2335
2336 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2337 if (!sctx->framebuffer.state.cbufs[i])
2338 continue;
2339
2340 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2341 if (rtex->dcc_gather_statistics)
2342 vi_separate_dcc_stop_query(ctx, rtex);
2343 }
2344
2345 /* Only flush TC when changing the framebuffer state, because
2346 * the only client not using TC that can change textures is
2347 * the framebuffer.
2348 *
2349 * Flush all CB and DB caches here because all buffers can be used
2350 * for write by both TC (with shader image stores) and CB/DB.
2351 */
2352 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2353 SI_CONTEXT_INV_GLOBAL_L2 |
2354 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2355 SI_CONTEXT_CS_PARTIAL_FLUSH;
2356
2357 /* Take the maximum of the old and new count. If the new count is lower,
2358 * dirtying is needed to disable the unbound colorbuffers.
2359 */
2360 sctx->framebuffer.dirty_cbufs |=
2361 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2362 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2363
2364 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2365 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2366
2367 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2368 sctx->framebuffer.spi_shader_col_format = 0;
2369 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2370 sctx->framebuffer.spi_shader_col_format_blend = 0;
2371 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2372 sctx->framebuffer.color_is_int8 = 0;
2373
2374 sctx->framebuffer.compressed_cb_mask = 0;
2375 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2376 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2377 sctx->framebuffer.any_dst_linear = false;
2378
2379 for (i = 0; i < state->nr_cbufs; i++) {
2380 if (!state->cbufs[i])
2381 continue;
2382
2383 surf = (struct r600_surface*)state->cbufs[i];
2384 rtex = (struct r600_texture*)surf->base.texture;
2385
2386 if (!surf->color_initialized) {
2387 si_initialize_color_surface(sctx, surf);
2388 }
2389
2390 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2391 sctx->framebuffer.spi_shader_col_format |=
2392 surf->spi_shader_col_format << (i * 4);
2393 sctx->framebuffer.spi_shader_col_format_alpha |=
2394 surf->spi_shader_col_format_alpha << (i * 4);
2395 sctx->framebuffer.spi_shader_col_format_blend |=
2396 surf->spi_shader_col_format_blend << (i * 4);
2397 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2398 surf->spi_shader_col_format_blend_alpha << (i * 4);
2399
2400 if (surf->color_is_int8)
2401 sctx->framebuffer.color_is_int8 |= 1 << i;
2402
2403 if (rtex->fmask.size) {
2404 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2405 }
2406
2407 if (rtex->surface.is_linear)
2408 sctx->framebuffer.any_dst_linear = true;
2409
2410 r600_context_add_resource_size(ctx, surf->base.texture);
2411
2412 p_atomic_inc(&rtex->framebuffers_bound);
2413
2414 if (rtex->dcc_gather_statistics) {
2415 /* Dirty tracking must be enabled for DCC usage analysis. */
2416 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2417 vi_separate_dcc_start_query(ctx, rtex);
2418 }
2419 }
2420
2421 if (state->zsbuf) {
2422 surf = (struct r600_surface*)state->zsbuf;
2423 rtex = (struct r600_texture*)surf->base.texture;
2424
2425 if (!surf->depth_initialized) {
2426 si_init_depth_surface(sctx, surf);
2427 }
2428 r600_context_add_resource_size(ctx, surf->base.texture);
2429 }
2430
2431 si_update_poly_offset_state(sctx);
2432 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2433 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2434
2435 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2436 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2437
2438 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2439 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2440 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2441
2442 /* Set sample locations as fragment shader constants. */
2443 switch (sctx->framebuffer.nr_samples) {
2444 case 1:
2445 constbuf.user_buffer = sctx->b.sample_locations_1x;
2446 break;
2447 case 2:
2448 constbuf.user_buffer = sctx->b.sample_locations_2x;
2449 break;
2450 case 4:
2451 constbuf.user_buffer = sctx->b.sample_locations_4x;
2452 break;
2453 case 8:
2454 constbuf.user_buffer = sctx->b.sample_locations_8x;
2455 break;
2456 case 16:
2457 constbuf.user_buffer = sctx->b.sample_locations_16x;
2458 break;
2459 default:
2460 R600_ERR("Requested an invalid number of samples %i.\n",
2461 sctx->framebuffer.nr_samples);
2462 assert(0);
2463 }
2464 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2465 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2466
2467 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2468 }
2469
2470 sctx->need_check_render_feedback = true;
2471 sctx->do_update_shaders = true;
2472 }
2473
2474 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2475 {
2476 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2477 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2478 unsigned i, nr_cbufs = state->nr_cbufs;
2479 struct r600_texture *tex = NULL;
2480 struct r600_surface *cb = NULL;
2481 unsigned cb_color_info = 0;
2482
2483 /* Colorbuffers. */
2484 for (i = 0; i < nr_cbufs; i++) {
2485 const struct radeon_surf_level *level_info;
2486 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2487 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2488 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2489
2490 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2491 continue;
2492
2493 cb = (struct r600_surface*)state->cbufs[i];
2494 if (!cb) {
2495 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2496 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2497 continue;
2498 }
2499
2500 tex = (struct r600_texture *)cb->base.texture;
2501 level_info = &tex->surface.level[cb->base.u.tex.level];
2502 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2503 &tex->resource, RADEON_USAGE_READWRITE,
2504 tex->resource.b.b.nr_samples > 1 ?
2505 RADEON_PRIO_COLOR_BUFFER_MSAA :
2506 RADEON_PRIO_COLOR_BUFFER);
2507
2508 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2509 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2510 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2511 RADEON_PRIO_CMASK);
2512 }
2513
2514 if (tex->dcc_separate_buffer)
2515 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2516 tex->dcc_separate_buffer,
2517 RADEON_USAGE_READWRITE,
2518 RADEON_PRIO_DCC);
2519
2520 /* Compute mutable surface parameters. */
2521 pitch_tile_max = level_info->nblk_x / 8 - 1;
2522 slice_tile_max = level_info->nblk_x *
2523 level_info->nblk_y / 64 - 1;
2524 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2525
2526 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2527 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2528 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2529 cb_color_attrib = cb->cb_color_attrib |
2530 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2531
2532 if (tex->fmask.size) {
2533 if (sctx->b.chip_class >= CIK)
2534 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2535 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2536 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2537 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2538 } else {
2539 /* This must be set for fast clear to work without FMASK. */
2540 if (sctx->b.chip_class >= CIK)
2541 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2542 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2543 cb_color_fmask = cb_color_base;
2544 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2545 }
2546
2547 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2548
2549 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2550 bool is_msaa_resolve_dst = state->cbufs[0] &&
2551 state->cbufs[0]->texture->nr_samples > 1 &&
2552 state->cbufs[1] == &cb->base &&
2553 state->cbufs[1]->texture->nr_samples <= 1;
2554
2555 if (!is_msaa_resolve_dst)
2556 cb_color_info |= S_028C70_DCC_ENABLE(1);
2557 }
2558
2559 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2560 sctx->b.chip_class >= VI ? 14 : 13);
2561 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2562 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2563 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2564 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2565 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2566 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2567 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2568 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2569 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2570 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2571 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2572 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2573 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2574
2575 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2576 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2577 tex->dcc_offset +
2578 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2579 }
2580 for (; i < 8 ; i++)
2581 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2582 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2583
2584 /* ZS buffer. */
2585 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2586 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2587 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2588
2589 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2590 &rtex->resource, RADEON_USAGE_READWRITE,
2591 zb->base.texture->nr_samples > 1 ?
2592 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2593 RADEON_PRIO_DEPTH_BUFFER);
2594
2595 if (zb->db_htile_data_base) {
2596 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2597 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2598 RADEON_PRIO_HTILE);
2599 }
2600
2601 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2602 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2603
2604 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2605 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2606 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2607 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2608 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2609 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2610 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2611 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2612 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2613 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2614 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2615
2616 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2617 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2618 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2619
2620 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2621 } else if (sctx->framebuffer.dirty_zsbuf) {
2622 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2623 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2624 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2625 }
2626
2627 /* Framebuffer dimensions. */
2628 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2629 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2630 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2631
2632 sctx->framebuffer.dirty_cbufs = 0;
2633 sctx->framebuffer.dirty_zsbuf = false;
2634 }
2635
2636 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2637 struct r600_atom *atom)
2638 {
2639 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2640 unsigned nr_samples = sctx->framebuffer.nr_samples;
2641
2642 /* Smoothing (only possible with nr_samples == 1) uses the same
2643 * sample locations as the MSAA it simulates.
2644 */
2645 if (nr_samples <= 1 && sctx->smoothing_enabled)
2646 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2647
2648 /* On Polaris, the small primitive filter uses the sample locations
2649 * even when MSAA is off, so we need to make sure they're set to 0.
2650 */
2651 if (sctx->b.family >= CHIP_POLARIS10)
2652 nr_samples = MAX2(nr_samples, 1);
2653
2654 if (nr_samples >= 1 &&
2655 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2656 sctx->msaa_sample_locs.nr_samples = nr_samples;
2657 cayman_emit_msaa_sample_locs(cs, nr_samples);
2658 }
2659
2660 if (sctx->b.family >= CHIP_POLARIS10) {
2661 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2662 unsigned small_prim_filter_cntl =
2663 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2664 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2665
2666 /* The alternative of setting sample locations to 0 would
2667 * require a DB flush to avoid Z errors, see
2668 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2669 */
2670 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2671 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2672
2673 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2674 small_prim_filter_cntl);
2675 }
2676 }
2677
2678 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2679 {
2680 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2681 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2682 /* 33% faster rendering to linear color buffers */
2683 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2684 unsigned sc_mode_cntl_1 =
2685 S_028A4C_WALK_SIZE(dst_is_linear) |
2686 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2687 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2688 /* always 1: */
2689 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2690 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2691 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2692 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2693 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2694 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2695
2696 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2697 sctx->ps_iter_samples,
2698 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2699 sc_mode_cntl_1);
2700 }
2701
2702 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2703 {
2704 struct si_context *sctx = (struct si_context *)ctx;
2705
2706 if (sctx->ps_iter_samples == min_samples)
2707 return;
2708
2709 sctx->ps_iter_samples = min_samples;
2710 sctx->do_update_shaders = true;
2711
2712 if (sctx->framebuffer.nr_samples > 1)
2713 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2714 }
2715
2716 /*
2717 * Samplers
2718 */
2719
2720 /**
2721 * Build the sampler view descriptor for a buffer texture.
2722 * @param state 256-bit descriptor; only the high 128 bits are filled in
2723 */
2724 void
2725 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2726 enum pipe_format format,
2727 unsigned offset, unsigned size,
2728 uint32_t *state)
2729 {
2730 const struct util_format_description *desc;
2731 int first_non_void;
2732 unsigned stride;
2733 unsigned num_records;
2734 unsigned num_format, data_format;
2735
2736 desc = util_format_description(format);
2737 first_non_void = util_format_get_first_non_void_channel(format);
2738 stride = desc->block.bits / 8;
2739 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2740 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2741
2742 num_records = size / stride;
2743 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2744
2745 if (screen->b.chip_class >= VI)
2746 num_records *= stride;
2747
2748 state[4] = 0;
2749 state[5] = S_008F04_STRIDE(stride);
2750 state[6] = num_records;
2751 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2752 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2753 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2754 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2755 S_008F0C_NUM_FORMAT(num_format) |
2756 S_008F0C_DATA_FORMAT(data_format);
2757 }
2758
2759 /**
2760 * Build the sampler view descriptor for a texture.
2761 */
2762 void
2763 si_make_texture_descriptor(struct si_screen *screen,
2764 struct r600_texture *tex,
2765 bool sampler,
2766 enum pipe_texture_target target,
2767 enum pipe_format pipe_format,
2768 const unsigned char state_swizzle[4],
2769 unsigned first_level, unsigned last_level,
2770 unsigned first_layer, unsigned last_layer,
2771 unsigned width, unsigned height, unsigned depth,
2772 uint32_t *state,
2773 uint32_t *fmask_state)
2774 {
2775 struct pipe_resource *res = &tex->resource.b.b;
2776 const struct util_format_description *desc;
2777 unsigned char swizzle[4];
2778 int first_non_void;
2779 unsigned num_format, data_format, type;
2780 uint64_t va;
2781
2782 desc = util_format_description(pipe_format);
2783
2784 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2785 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2786 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2787
2788 switch (pipe_format) {
2789 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2790 case PIPE_FORMAT_X24S8_UINT:
2791 case PIPE_FORMAT_X32_S8X24_UINT:
2792 case PIPE_FORMAT_X8Z24_UNORM:
2793 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2794 break;
2795 default:
2796 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2797 }
2798 } else {
2799 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2800 }
2801
2802 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2803
2804 switch (pipe_format) {
2805 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2806 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2807 break;
2808 default:
2809 if (first_non_void < 0) {
2810 if (util_format_is_compressed(pipe_format)) {
2811 switch (pipe_format) {
2812 case PIPE_FORMAT_DXT1_SRGB:
2813 case PIPE_FORMAT_DXT1_SRGBA:
2814 case PIPE_FORMAT_DXT3_SRGBA:
2815 case PIPE_FORMAT_DXT5_SRGBA:
2816 case PIPE_FORMAT_BPTC_SRGBA:
2817 case PIPE_FORMAT_ETC2_SRGB8:
2818 case PIPE_FORMAT_ETC2_SRGB8A1:
2819 case PIPE_FORMAT_ETC2_SRGBA8:
2820 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2821 break;
2822 case PIPE_FORMAT_RGTC1_SNORM:
2823 case PIPE_FORMAT_LATC1_SNORM:
2824 case PIPE_FORMAT_RGTC2_SNORM:
2825 case PIPE_FORMAT_LATC2_SNORM:
2826 case PIPE_FORMAT_ETC2_R11_SNORM:
2827 case PIPE_FORMAT_ETC2_RG11_SNORM:
2828 /* implies float, so use SNORM/UNORM to determine
2829 whether data is signed or not */
2830 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2831 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2832 break;
2833 default:
2834 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2835 break;
2836 }
2837 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2838 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2839 } else {
2840 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2841 }
2842 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2843 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2844 } else {
2845 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2846
2847 switch (desc->channel[first_non_void].type) {
2848 case UTIL_FORMAT_TYPE_FLOAT:
2849 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2850 break;
2851 case UTIL_FORMAT_TYPE_SIGNED:
2852 if (desc->channel[first_non_void].normalized)
2853 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2854 else if (desc->channel[first_non_void].pure_integer)
2855 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2856 else
2857 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2858 break;
2859 case UTIL_FORMAT_TYPE_UNSIGNED:
2860 if (desc->channel[first_non_void].normalized)
2861 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2862 else if (desc->channel[first_non_void].pure_integer)
2863 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2864 else
2865 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2866 }
2867 }
2868 }
2869
2870 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2871 if (data_format == ~0) {
2872 data_format = 0;
2873 }
2874
2875 if (!sampler &&
2876 (res->target == PIPE_TEXTURE_CUBE ||
2877 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2878 res->target == PIPE_TEXTURE_3D)) {
2879 /* For the purpose of shader images, treat cube maps and 3D
2880 * textures as 2D arrays. For 3D textures, the address
2881 * calculations for mipmaps are different, so we rely on the
2882 * caller to effectively disable mipmaps.
2883 */
2884 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2885
2886 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2887 } else {
2888 type = si_tex_dim(res->target, target, res->nr_samples);
2889 }
2890
2891 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2892 height = 1;
2893 depth = res->array_size;
2894 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2895 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2896 if (sampler || res->target != PIPE_TEXTURE_3D)
2897 depth = res->array_size;
2898 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2899 depth = res->array_size / 6;
2900
2901 state[0] = 0;
2902 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2903 S_008F14_NUM_FORMAT(num_format));
2904 state[2] = (S_008F18_WIDTH(width - 1) |
2905 S_008F18_HEIGHT(height - 1) |
2906 S_008F18_PERF_MOD(4));
2907 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2908 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2909 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2910 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2911 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2912 0 : first_level) |
2913 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2914 util_logbase2(res->nr_samples) :
2915 last_level) |
2916 S_008F1C_POW2_PAD(res->last_level > 0) |
2917 S_008F1C_TYPE(type));
2918 state[4] = S_008F20_DEPTH(depth - 1);
2919 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2920 S_008F24_LAST_ARRAY(last_layer));
2921 state[6] = 0;
2922 state[7] = 0;
2923
2924 if (tex->dcc_offset) {
2925 unsigned swap = r600_translate_colorswap(pipe_format, false);
2926
2927 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2928 } else {
2929 /* The last dword is unused by hw. The shader uses it to clear
2930 * bits in the first dword of sampler state.
2931 */
2932 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2933 if (first_level == last_level)
2934 state[7] = C_008F30_MAX_ANISO_RATIO;
2935 else
2936 state[7] = 0xffffffff;
2937 }
2938 }
2939
2940 /* Initialize the sampler view for FMASK. */
2941 if (tex->fmask.size) {
2942 uint32_t fmask_format;
2943
2944 va = tex->resource.gpu_address + tex->fmask.offset;
2945
2946 switch (res->nr_samples) {
2947 case 2:
2948 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2949 break;
2950 case 4:
2951 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2952 break;
2953 case 8:
2954 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2955 break;
2956 default:
2957 assert(0);
2958 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2959 }
2960
2961 fmask_state[0] = va >> 8;
2962 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2963 S_008F14_DATA_FORMAT(fmask_format) |
2964 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2965 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2966 S_008F18_HEIGHT(height - 1);
2967 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2968 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2969 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2970 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2971 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2972 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2973 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2974 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2975 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2976 S_008F24_LAST_ARRAY(last_layer);
2977 fmask_state[6] = 0;
2978 fmask_state[7] = 0;
2979 }
2980 }
2981
2982 /**
2983 * Create a sampler view.
2984 *
2985 * @param ctx context
2986 * @param texture texture
2987 * @param state sampler view template
2988 * @param width0 width0 override (for compressed textures as int)
2989 * @param height0 height0 override (for compressed textures as int)
2990 * @param force_level set the base address to the level (for compressed textures)
2991 */
2992 struct pipe_sampler_view *
2993 si_create_sampler_view_custom(struct pipe_context *ctx,
2994 struct pipe_resource *texture,
2995 const struct pipe_sampler_view *state,
2996 unsigned width0, unsigned height0,
2997 unsigned force_level)
2998 {
2999 struct si_context *sctx = (struct si_context*)ctx;
3000 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3001 struct r600_texture *tmp = (struct r600_texture*)texture;
3002 unsigned base_level, first_level, last_level;
3003 unsigned char state_swizzle[4];
3004 unsigned height, depth, width;
3005 unsigned last_layer = state->u.tex.last_layer;
3006 enum pipe_format pipe_format;
3007 const struct radeon_surf_level *surflevel;
3008
3009 if (!view)
3010 return NULL;
3011
3012 /* initialize base object */
3013 view->base = *state;
3014 view->base.texture = NULL;
3015 view->base.reference.count = 1;
3016 view->base.context = ctx;
3017
3018 assert(texture);
3019 pipe_resource_reference(&view->base.texture, texture);
3020
3021 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3022 state->format == PIPE_FORMAT_S8X24_UINT ||
3023 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3024 state->format == PIPE_FORMAT_S8_UINT)
3025 view->is_stencil_sampler = true;
3026
3027 /* Buffer resource. */
3028 if (texture->target == PIPE_BUFFER) {
3029 si_make_buffer_descriptor(sctx->screen,
3030 (struct r600_resource *)texture,
3031 state->format,
3032 state->u.buf.offset,
3033 state->u.buf.size,
3034 view->state);
3035 return &view->base;
3036 }
3037
3038 state_swizzle[0] = state->swizzle_r;
3039 state_swizzle[1] = state->swizzle_g;
3040 state_swizzle[2] = state->swizzle_b;
3041 state_swizzle[3] = state->swizzle_a;
3042
3043 base_level = 0;
3044 first_level = state->u.tex.first_level;
3045 last_level = state->u.tex.last_level;
3046 width = width0;
3047 height = height0;
3048 depth = texture->depth0;
3049
3050 if (force_level) {
3051 assert(force_level == first_level &&
3052 force_level == last_level);
3053 base_level = force_level;
3054 first_level = 0;
3055 last_level = 0;
3056 width = u_minify(width, force_level);
3057 height = u_minify(height, force_level);
3058 depth = u_minify(depth, force_level);
3059 }
3060
3061 /* This is not needed if state trackers set last_layer correctly. */
3062 if (state->target == PIPE_TEXTURE_1D ||
3063 state->target == PIPE_TEXTURE_2D ||
3064 state->target == PIPE_TEXTURE_RECT ||
3065 state->target == PIPE_TEXTURE_CUBE)
3066 last_layer = state->u.tex.first_layer;
3067
3068 /* Texturing with separate depth and stencil. */
3069 pipe_format = state->format;
3070
3071 /* Depth/stencil texturing sometimes needs separate texture. */
3072 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3073 if (!tmp->flushed_depth_texture &&
3074 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3075 pipe_resource_reference(&view->base.texture, NULL);
3076 FREE(view);
3077 return NULL;
3078 }
3079
3080 assert(tmp->flushed_depth_texture);
3081
3082 /* Override format for the case where the flushed texture
3083 * contains only Z or only S.
3084 */
3085 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3086 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3087
3088 tmp = tmp->flushed_depth_texture;
3089 }
3090
3091 surflevel = tmp->surface.level;
3092
3093 if (tmp->db_compatible) {
3094 if (!view->is_stencil_sampler)
3095 pipe_format = tmp->db_render_format;
3096
3097 switch (pipe_format) {
3098 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3099 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3100 break;
3101 case PIPE_FORMAT_X8Z24_UNORM:
3102 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3103 /* Z24 is always stored like this for DB
3104 * compatibility.
3105 */
3106 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3107 break;
3108 case PIPE_FORMAT_X24S8_UINT:
3109 case PIPE_FORMAT_S8X24_UINT:
3110 case PIPE_FORMAT_X32_S8X24_UINT:
3111 pipe_format = PIPE_FORMAT_S8_UINT;
3112 surflevel = tmp->surface.stencil_level;
3113 break;
3114 default:;
3115 }
3116 }
3117
3118 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3119 state->u.tex.first_level,
3120 state->format);
3121
3122 si_make_texture_descriptor(sctx->screen, tmp, true,
3123 state->target, pipe_format, state_swizzle,
3124 first_level, last_level,
3125 state->u.tex.first_layer, last_layer,
3126 width, height, depth,
3127 view->state, view->fmask_state);
3128
3129 view->base_level_info = &surflevel[base_level];
3130 view->base_level = base_level;
3131 view->block_width = util_format_get_blockwidth(pipe_format);
3132 return &view->base;
3133 }
3134
3135 static struct pipe_sampler_view *
3136 si_create_sampler_view(struct pipe_context *ctx,
3137 struct pipe_resource *texture,
3138 const struct pipe_sampler_view *state)
3139 {
3140 return si_create_sampler_view_custom(ctx, texture, state,
3141 texture ? texture->width0 : 0,
3142 texture ? texture->height0 : 0, 0);
3143 }
3144
3145 static void si_sampler_view_destroy(struct pipe_context *ctx,
3146 struct pipe_sampler_view *state)
3147 {
3148 struct si_sampler_view *view = (struct si_sampler_view *)state;
3149
3150 pipe_resource_reference(&state->texture, NULL);
3151 FREE(view);
3152 }
3153
3154 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3155 {
3156 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3157 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3158 (linear_filter &&
3159 (wrap == PIPE_TEX_WRAP_CLAMP ||
3160 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3161 }
3162
3163 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3164 {
3165 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3166 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3167
3168 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3169 state->border_color.ui[2] || state->border_color.ui[3]) &&
3170 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3171 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3172 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3173 }
3174
3175 static void *si_create_sampler_state(struct pipe_context *ctx,
3176 const struct pipe_sampler_state *state)
3177 {
3178 struct si_context *sctx = (struct si_context *)ctx;
3179 struct r600_common_screen *rscreen = sctx->b.screen;
3180 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3181 unsigned border_color_type, border_color_index = 0;
3182 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3183 : state->max_anisotropy;
3184 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3185
3186 if (!rstate) {
3187 return NULL;
3188 }
3189
3190 if (!sampler_state_needs_border_color(state))
3191 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3192 else if (state->border_color.f[0] == 0 &&
3193 state->border_color.f[1] == 0 &&
3194 state->border_color.f[2] == 0 &&
3195 state->border_color.f[3] == 0)
3196 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3197 else if (state->border_color.f[0] == 0 &&
3198 state->border_color.f[1] == 0 &&
3199 state->border_color.f[2] == 0 &&
3200 state->border_color.f[3] == 1)
3201 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3202 else if (state->border_color.f[0] == 1 &&
3203 state->border_color.f[1] == 1 &&
3204 state->border_color.f[2] == 1 &&
3205 state->border_color.f[3] == 1)
3206 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3207 else {
3208 int i;
3209
3210 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3211
3212 /* Check if the border has been uploaded already. */
3213 for (i = 0; i < sctx->border_color_count; i++)
3214 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3215 sizeof(state->border_color)) == 0)
3216 break;
3217
3218 if (i >= SI_MAX_BORDER_COLORS) {
3219 /* Getting 4096 unique border colors is very unlikely. */
3220 fprintf(stderr, "radeonsi: The border color table is full. "
3221 "Any new border colors will be just black. "
3222 "Please file a bug.\n");
3223 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3224 } else {
3225 if (i == sctx->border_color_count) {
3226 /* Upload a new border color. */
3227 memcpy(&sctx->border_color_table[i], &state->border_color,
3228 sizeof(state->border_color));
3229 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3230 &state->border_color,
3231 sizeof(state->border_color));
3232 sctx->border_color_count++;
3233 }
3234
3235 border_color_index = i;
3236 }
3237 }
3238
3239 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3240 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3241 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3242 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3243 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3244 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3245 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3246 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3247 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3248 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3249 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3250 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3251 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3252 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3253 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3254 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3255 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3256 S_008F38_MIP_POINT_PRECLAMP(1) |
3257 S_008F38_DISABLE_LSB_CEIL(1) |
3258 S_008F38_FILTER_PREC_FIX(1) |
3259 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3260 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3261 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3262 return rstate;
3263 }
3264
3265 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3266 {
3267 struct si_context *sctx = (struct si_context *)ctx;
3268
3269 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3270 return;
3271
3272 sctx->sample_mask.sample_mask = sample_mask;
3273 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3274 }
3275
3276 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3277 {
3278 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3279 unsigned mask = sctx->sample_mask.sample_mask;
3280
3281 /* Needed for line and polygon smoothing as well as for the Polaris
3282 * small primitive filter. We expect the state tracker to take care of
3283 * this for us.
3284 */
3285 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3286 (mask & 1 && sctx->blitter->running));
3287
3288 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3289 radeon_emit(cs, mask | (mask << 16));
3290 radeon_emit(cs, mask | (mask << 16));
3291 }
3292
3293 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3294 {
3295 free(state);
3296 }
3297
3298 /*
3299 * Vertex elements & buffers
3300 */
3301
3302 static void *si_create_vertex_elements(struct pipe_context *ctx,
3303 unsigned count,
3304 const struct pipe_vertex_element *elements)
3305 {
3306 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3307 int i;
3308
3309 assert(count <= SI_MAX_ATTRIBS);
3310 if (!v)
3311 return NULL;
3312
3313 v->count = count;
3314 for (i = 0; i < count; ++i) {
3315 const struct util_format_description *desc;
3316 unsigned data_format, num_format;
3317 int first_non_void;
3318
3319 desc = util_format_description(elements[i].src_format);
3320 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3321 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3322 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3323
3324 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3325 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3326 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3327 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3328 S_008F0C_NUM_FORMAT(num_format) |
3329 S_008F0C_DATA_FORMAT(data_format);
3330 v->format_size[i] = desc->block.bits / 8;
3331
3332 /* The hardware always treats the 2-bit alpha channel as
3333 * unsigned, so a shader workaround is needed.
3334 */
3335 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3336 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3337 v->fix_fetch |= SI_FIX_FETCH_A2_SNORM << (2 * i);
3338 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3339 v->fix_fetch |= SI_FIX_FETCH_A2_SSCALED << (2 * i);
3340 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3341 /* This isn't actually used in OpenGL. */
3342 v->fix_fetch |= SI_FIX_FETCH_A2_SINT << (2 * i);
3343 }
3344 }
3345
3346 /* We work around the fact that 8_8_8 and 16_16_16 data formats
3347 * do not exist by using the corresponding 4-component formats.
3348 * This requires a fixup of the descriptor for bounds checks.
3349 */
3350 if (desc->block.bits == 3 * 8 ||
3351 desc->block.bits == 3 * 16) {
3352 v->fix_size3 |= (desc->block.bits / 24) << (2 * i);
3353 }
3354 }
3355 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3356
3357 return v;
3358 }
3359
3360 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3361 {
3362 struct si_context *sctx = (struct si_context *)ctx;
3363 struct si_vertex_element *v = (struct si_vertex_element*)state;
3364
3365 sctx->vertex_elements = v;
3366 sctx->vertex_buffers_dirty = true;
3367 sctx->do_update_shaders = true;
3368 }
3369
3370 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3371 {
3372 struct si_context *sctx = (struct si_context *)ctx;
3373
3374 if (sctx->vertex_elements == state)
3375 sctx->vertex_elements = NULL;
3376 FREE(state);
3377 }
3378
3379 static void si_set_vertex_buffers(struct pipe_context *ctx,
3380 unsigned start_slot, unsigned count,
3381 const struct pipe_vertex_buffer *buffers)
3382 {
3383 struct si_context *sctx = (struct si_context *)ctx;
3384 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3385 int i;
3386
3387 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3388
3389 if (buffers) {
3390 for (i = 0; i < count; i++) {
3391 const struct pipe_vertex_buffer *src = buffers + i;
3392 struct pipe_vertex_buffer *dsti = dst + i;
3393 struct pipe_resource *buf = src->buffer;
3394
3395 pipe_resource_reference(&dsti->buffer, buf);
3396 dsti->buffer_offset = src->buffer_offset;
3397 dsti->stride = src->stride;
3398 r600_context_add_resource_size(ctx, buf);
3399 if (buf)
3400 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3401 }
3402 } else {
3403 for (i = 0; i < count; i++) {
3404 pipe_resource_reference(&dst[i].buffer, NULL);
3405 }
3406 }
3407 sctx->vertex_buffers_dirty = true;
3408 }
3409
3410 static void si_set_index_buffer(struct pipe_context *ctx,
3411 const struct pipe_index_buffer *ib)
3412 {
3413 struct si_context *sctx = (struct si_context *)ctx;
3414
3415 if (ib) {
3416 struct pipe_resource *buf = ib->buffer;
3417
3418 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3419 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3420 r600_context_add_resource_size(ctx, buf);
3421 if (buf)
3422 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3423 } else {
3424 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3425 }
3426 }
3427
3428 /*
3429 * Misc
3430 */
3431
3432 static void si_set_tess_state(struct pipe_context *ctx,
3433 const float default_outer_level[4],
3434 const float default_inner_level[2])
3435 {
3436 struct si_context *sctx = (struct si_context *)ctx;
3437 struct pipe_constant_buffer cb;
3438 float array[8];
3439
3440 memcpy(array, default_outer_level, sizeof(float) * 4);
3441 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3442
3443 cb.buffer = NULL;
3444 cb.user_buffer = NULL;
3445 cb.buffer_size = sizeof(array);
3446
3447 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3448 (void*)array, sizeof(array),
3449 &cb.buffer_offset);
3450
3451 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3452 pipe_resource_reference(&cb.buffer, NULL);
3453 }
3454
3455 static void si_texture_barrier(struct pipe_context *ctx)
3456 {
3457 struct si_context *sctx = (struct si_context *)ctx;
3458
3459 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3460 SI_CONTEXT_INV_GLOBAL_L2 |
3461 SI_CONTEXT_FLUSH_AND_INV_CB |
3462 SI_CONTEXT_CS_PARTIAL_FLUSH;
3463 }
3464
3465 /* This only ensures coherency for shader image/buffer stores. */
3466 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3467 {
3468 struct si_context *sctx = (struct si_context *)ctx;
3469
3470 /* Subsequent commands must wait for all shader invocations to
3471 * complete. */
3472 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3473 SI_CONTEXT_CS_PARTIAL_FLUSH;
3474
3475 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3476 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3477 SI_CONTEXT_INV_VMEM_L1;
3478
3479 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3480 PIPE_BARRIER_SHADER_BUFFER |
3481 PIPE_BARRIER_TEXTURE |
3482 PIPE_BARRIER_IMAGE |
3483 PIPE_BARRIER_STREAMOUT_BUFFER |
3484 PIPE_BARRIER_GLOBAL_BUFFER)) {
3485 /* As far as I can tell, L1 contents are written back to L2
3486 * automatically at end of shader, but the contents of other
3487 * L1 caches might still be stale. */
3488 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3489 }
3490
3491 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3492 /* Indices are read through TC L2 since VI.
3493 * L1 isn't used.
3494 */
3495 if (sctx->screen->b.chip_class <= CIK)
3496 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3497 }
3498
3499 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3500 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3501
3502 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3503 PIPE_BARRIER_INDIRECT_BUFFER))
3504 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3505 }
3506
3507 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3508 {
3509 struct pipe_blend_state blend;
3510
3511 memset(&blend, 0, sizeof(blend));
3512 blend.independent_blend_enable = true;
3513 blend.rt[0].colormask = 0xf;
3514 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3515 }
3516
3517 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3518 bool include_draw_vbo)
3519 {
3520 si_need_cs_space((struct si_context*)ctx);
3521 }
3522
3523 static void si_init_config(struct si_context *sctx);
3524
3525 void si_init_state_functions(struct si_context *sctx)
3526 {
3527 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3528 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3529 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3530 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3531 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3532
3533 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3534 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3535 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3536 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3537 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3538 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3539 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3540 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3541 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3542 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3543
3544 sctx->b.b.create_blend_state = si_create_blend_state;
3545 sctx->b.b.bind_blend_state = si_bind_blend_state;
3546 sctx->b.b.delete_blend_state = si_delete_blend_state;
3547 sctx->b.b.set_blend_color = si_set_blend_color;
3548
3549 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3550 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3551 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3552
3553 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3554 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3555 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3556
3557 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3558 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3559 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3560 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3561 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3562
3563 sctx->b.b.set_clip_state = si_set_clip_state;
3564 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3565
3566 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3567 sctx->b.b.get_sample_position = cayman_get_sample_position;
3568
3569 sctx->b.b.create_sampler_state = si_create_sampler_state;
3570 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3571
3572 sctx->b.b.create_sampler_view = si_create_sampler_view;
3573 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3574
3575 sctx->b.b.set_sample_mask = si_set_sample_mask;
3576
3577 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3578 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3579 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3580 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3581 sctx->b.b.set_index_buffer = si_set_index_buffer;
3582
3583 sctx->b.b.texture_barrier = si_texture_barrier;
3584 sctx->b.b.memory_barrier = si_memory_barrier;
3585 sctx->b.b.set_min_samples = si_set_min_samples;
3586 sctx->b.b.set_tess_state = si_set_tess_state;
3587
3588 sctx->b.b.set_active_query_state = si_set_active_query_state;
3589 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3590 sctx->b.save_qbo_state = si_save_qbo_state;
3591 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3592
3593 sctx->b.b.draw_vbo = si_draw_vbo;
3594
3595 si_init_config(sctx);
3596 }
3597
3598 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3599 {
3600 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3601 }
3602
3603 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3604 struct r600_texture *rtex,
3605 struct radeon_bo_metadata *md)
3606 {
3607 struct si_screen *sscreen = (struct si_screen*)rscreen;
3608 struct pipe_resource *res = &rtex->resource.b.b;
3609 static const unsigned char swizzle[] = {
3610 PIPE_SWIZZLE_X,
3611 PIPE_SWIZZLE_Y,
3612 PIPE_SWIZZLE_Z,
3613 PIPE_SWIZZLE_W
3614 };
3615 uint32_t desc[8], i;
3616 bool is_array = util_resource_is_array_texture(res);
3617
3618 /* DRM 2.x.x doesn't support this. */
3619 if (rscreen->info.drm_major != 3)
3620 return;
3621
3622 assert(rtex->dcc_separate_buffer == NULL);
3623 assert(rtex->fmask.size == 0);
3624
3625 /* Metadata image format format version 1:
3626 * [0] = 1 (metadata format identifier)
3627 * [1] = (VENDOR_ID << 16) | PCI_ID
3628 * [2:9] = image descriptor for the whole resource
3629 * [2] is always 0, because the base address is cleared
3630 * [9] is the DCC offset bits [39:8] from the beginning of
3631 * the buffer
3632 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3633 */
3634
3635 md->metadata[0] = 1; /* metadata image format version 1 */
3636
3637 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3638 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3639
3640 si_make_texture_descriptor(sscreen, rtex, true,
3641 res->target, res->format,
3642 swizzle, 0, res->last_level, 0,
3643 is_array ? res->array_size - 1 : 0,
3644 res->width0, res->height0, res->depth0,
3645 desc, NULL);
3646
3647 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3648 rtex->surface.blk_w, false, desc);
3649
3650 /* Clear the base address and set the relative DCC offset. */
3651 desc[0] = 0;
3652 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3653 desc[7] = rtex->dcc_offset >> 8;
3654
3655 /* Dwords [2:9] contain the image descriptor. */
3656 memcpy(&md->metadata[2], desc, sizeof(desc));
3657
3658 /* Dwords [10:..] contain the mipmap level offsets. */
3659 for (i = 0; i <= res->last_level; i++)
3660 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3661
3662 md->size_metadata = (11 + res->last_level) * 4;
3663 }
3664
3665 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3666 struct r600_texture *rtex,
3667 struct radeon_bo_metadata *md)
3668 {
3669 uint32_t *desc = &md->metadata[2];
3670
3671 if (rscreen->chip_class < VI)
3672 return;
3673
3674 /* Return if DCC is enabled. The texture should be set up with it
3675 * already.
3676 */
3677 if (md->size_metadata >= 11 * 4 &&
3678 md->metadata[0] != 0 &&
3679 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3680 G_008F28_COMPRESSION_EN(desc[6])) {
3681 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3682 return;
3683 }
3684
3685 /* Disable DCC. These are always set by texture_from_handle and must
3686 * be cleared here.
3687 */
3688 rtex->dcc_offset = 0;
3689 }
3690
3691 void si_init_screen_state_functions(struct si_screen *sscreen)
3692 {
3693 sscreen->b.b.is_format_supported = si_is_format_supported;
3694 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3695 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3696 }
3697
3698 static void
3699 si_write_harvested_raster_configs(struct si_context *sctx,
3700 struct si_pm4_state *pm4,
3701 unsigned raster_config,
3702 unsigned raster_config_1)
3703 {
3704 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3705 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3706 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3707 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3708 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3709 unsigned rb_per_se = num_rb / num_se;
3710 unsigned se_mask[4];
3711 unsigned se;
3712
3713 se_mask[0] = ((1 << rb_per_se) - 1);
3714 se_mask[1] = (se_mask[0] << rb_per_se);
3715 se_mask[2] = (se_mask[1] << rb_per_se);
3716 se_mask[3] = (se_mask[2] << rb_per_se);
3717
3718 se_mask[0] &= rb_mask;
3719 se_mask[1] &= rb_mask;
3720 se_mask[2] &= rb_mask;
3721 se_mask[3] &= rb_mask;
3722
3723 assert(num_se == 1 || num_se == 2 || num_se == 4);
3724 assert(sh_per_se == 1 || sh_per_se == 2);
3725 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3726
3727 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3728 * fields are for, so I'm leaving them as their default
3729 * values. */
3730
3731 for (se = 0; se < num_se; se++) {
3732 unsigned raster_config_se = raster_config;
3733 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3734 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3735 int idx = (se / 2) * 2;
3736
3737 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3738 raster_config_se &= C_028350_SE_MAP;
3739
3740 if (!se_mask[idx]) {
3741 raster_config_se |=
3742 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3743 } else {
3744 raster_config_se |=
3745 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3746 }
3747 }
3748
3749 pkr0_mask &= rb_mask;
3750 pkr1_mask &= rb_mask;
3751 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3752 raster_config_se &= C_028350_PKR_MAP;
3753
3754 if (!pkr0_mask) {
3755 raster_config_se |=
3756 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3757 } else {
3758 raster_config_se |=
3759 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3760 }
3761 }
3762
3763 if (rb_per_se >= 2) {
3764 unsigned rb0_mask = 1 << (se * rb_per_se);
3765 unsigned rb1_mask = rb0_mask << 1;
3766
3767 rb0_mask &= rb_mask;
3768 rb1_mask &= rb_mask;
3769 if (!rb0_mask || !rb1_mask) {
3770 raster_config_se &= C_028350_RB_MAP_PKR0;
3771
3772 if (!rb0_mask) {
3773 raster_config_se |=
3774 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3775 } else {
3776 raster_config_se |=
3777 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3778 }
3779 }
3780
3781 if (rb_per_se > 2) {
3782 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3783 rb1_mask = rb0_mask << 1;
3784 rb0_mask &= rb_mask;
3785 rb1_mask &= rb_mask;
3786 if (!rb0_mask || !rb1_mask) {
3787 raster_config_se &= C_028350_RB_MAP_PKR1;
3788
3789 if (!rb0_mask) {
3790 raster_config_se |=
3791 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3792 } else {
3793 raster_config_se |=
3794 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3795 }
3796 }
3797 }
3798 }
3799
3800 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3801 if (sctx->b.chip_class < CIK)
3802 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3803 SE_INDEX(se) | SH_BROADCAST_WRITES |
3804 INSTANCE_BROADCAST_WRITES);
3805 else
3806 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3807 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3808 S_030800_INSTANCE_BROADCAST_WRITES(1));
3809 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3810 }
3811
3812 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3813 if (sctx->b.chip_class < CIK)
3814 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3815 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3816 INSTANCE_BROADCAST_WRITES);
3817 else {
3818 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3819 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3820 S_030800_INSTANCE_BROADCAST_WRITES(1));
3821
3822 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3823 (!se_mask[2] && !se_mask[3]))) {
3824 raster_config_1 &= C_028354_SE_PAIR_MAP;
3825
3826 if (!se_mask[0] && !se_mask[1]) {
3827 raster_config_1 |=
3828 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3829 } else {
3830 raster_config_1 |=
3831 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3832 }
3833 }
3834
3835 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3836 }
3837 }
3838
3839 static void si_init_config(struct si_context *sctx)
3840 {
3841 struct si_screen *sscreen = sctx->screen;
3842 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3843 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3844 unsigned raster_config, raster_config_1;
3845 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3846 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3847
3848 if (!pm4)
3849 return;
3850
3851 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3852 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3853 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3854 si_pm4_cmd_end(pm4, false);
3855
3856 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3857 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3858
3859 /* FIXME calculate these values somehow ??? */
3860 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3861 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3862 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3863
3864 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3865 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3866
3867 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3868 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3869 if (sctx->b.chip_class < CIK)
3870 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3871 S_008A14_CLIP_VTX_REORDER_ENA(1));
3872
3873 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3874 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3875
3876 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3877
3878 switch (sctx->screen->b.family) {
3879 case CHIP_TAHITI:
3880 case CHIP_PITCAIRN:
3881 raster_config = 0x2a00126a;
3882 raster_config_1 = 0x00000000;
3883 break;
3884 case CHIP_VERDE:
3885 raster_config = 0x0000124a;
3886 raster_config_1 = 0x00000000;
3887 break;
3888 case CHIP_OLAND:
3889 raster_config = 0x00000082;
3890 raster_config_1 = 0x00000000;
3891 break;
3892 case CHIP_HAINAN:
3893 raster_config = 0x00000000;
3894 raster_config_1 = 0x00000000;
3895 break;
3896 case CHIP_BONAIRE:
3897 raster_config = 0x16000012;
3898 raster_config_1 = 0x00000000;
3899 break;
3900 case CHIP_HAWAII:
3901 raster_config = 0x3a00161a;
3902 raster_config_1 = 0x0000002e;
3903 break;
3904 case CHIP_FIJI:
3905 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3906 /* old kernels with old tiling config */
3907 raster_config = 0x16000012;
3908 raster_config_1 = 0x0000002a;
3909 } else {
3910 raster_config = 0x3a00161a;
3911 raster_config_1 = 0x0000002e;
3912 }
3913 break;
3914 case CHIP_POLARIS10:
3915 raster_config = 0x16000012;
3916 raster_config_1 = 0x0000002a;
3917 break;
3918 case CHIP_POLARIS11:
3919 raster_config = 0x16000012;
3920 raster_config_1 = 0x00000000;
3921 break;
3922 case CHIP_TONGA:
3923 raster_config = 0x16000012;
3924 raster_config_1 = 0x0000002a;
3925 break;
3926 case CHIP_ICELAND:
3927 if (num_rb == 1)
3928 raster_config = 0x00000000;
3929 else
3930 raster_config = 0x00000002;
3931 raster_config_1 = 0x00000000;
3932 break;
3933 case CHIP_CARRIZO:
3934 raster_config = 0x00000002;
3935 raster_config_1 = 0x00000000;
3936 break;
3937 case CHIP_KAVERI:
3938 /* KV should be 0x00000002, but that causes problems with radeon */
3939 raster_config = 0x00000000; /* 0x00000002 */
3940 raster_config_1 = 0x00000000;
3941 break;
3942 case CHIP_KABINI:
3943 case CHIP_MULLINS:
3944 case CHIP_STONEY:
3945 raster_config = 0x00000000;
3946 raster_config_1 = 0x00000000;
3947 break;
3948 default:
3949 fprintf(stderr,
3950 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3951 raster_config = 0x00000000;
3952 raster_config_1 = 0x00000000;
3953 break;
3954 }
3955
3956 /* Always use the default config when all backends are enabled
3957 * (or when we failed to determine the enabled backends).
3958 */
3959 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3960 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3961 raster_config);
3962 if (sctx->b.chip_class >= CIK)
3963 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3964 raster_config_1);
3965 } else {
3966 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3967 }
3968
3969 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3970 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3971 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3972 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3973 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3974 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3975 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3976
3977 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3978 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3979 S_028230_ER_TRI(0xA) |
3980 S_028230_ER_POINT(0xA) |
3981 S_028230_ER_RECT(0xA) |
3982 /* Required by DX10_DIAMOND_TEST_ENA: */
3983 S_028230_ER_LINE_LR(0x1A) |
3984 S_028230_ER_LINE_RL(0x26) |
3985 S_028230_ER_LINE_TB(0xA) |
3986 S_028230_ER_LINE_BT(0xA));
3987 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3988 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3989 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3990 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3991 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3992 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3993 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
3994
3995 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3996 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3997 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3998
3999 if (sctx->b.chip_class >= CIK) {
4000 /* If this is 0, Bonaire can hang even if GS isn't being used.
4001 * Other chips are unaffected. These are suboptimal values,
4002 * but we don't use on-chip GS.
4003 */
4004 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4005 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4006 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4007
4008 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4009 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4010 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4011 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4012
4013 if (sscreen->b.info.num_good_compute_units /
4014 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4015 /* Too few available compute units per SH. Disallowing
4016 * VS to run on CU0 could hurt us more than late VS
4017 * allocation would help.
4018 *
4019 * LATE_ALLOC_VS = 2 is the highest safe number.
4020 */
4021 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4022 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4023 } else {
4024 /* Set LATE_ALLOC_VS == 31. It should be less than
4025 * the number of scratch waves. Limitations:
4026 * - VS can't execute on CU0.
4027 * - If HS writes outputs to LDS, LS can't execute on CU0.
4028 */
4029 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4030 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4031 }
4032
4033 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4034 }
4035
4036 if (sctx->b.chip_class >= VI) {
4037 unsigned vgt_tess_distribution;
4038
4039 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4040 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4041 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4042 if (sctx->b.family < CHIP_POLARIS10)
4043 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4044 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4045
4046 vgt_tess_distribution =
4047 S_028B50_ACCUM_ISOLINE(32) |
4048 S_028B50_ACCUM_TRI(11) |
4049 S_028B50_ACCUM_QUAD(11) |
4050 S_028B50_DONUT_SPLIT(16);
4051
4052 /* Testing with Unigine Heaven extreme tesselation yielded best results
4053 * with TRAP_SPLIT = 3.
4054 */
4055 if (sctx->b.family == CHIP_FIJI ||
4056 sctx->b.family >= CHIP_POLARIS10)
4057 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4058
4059 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4060 } else {
4061 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4062 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4063 }
4064
4065 if (sctx->b.family == CHIP_STONEY)
4066 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4067
4068 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4069 if (sctx->b.chip_class >= CIK)
4070 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4071 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4072 RADEON_PRIO_BORDER_COLORS);
4073
4074 si_pm4_upload_indirect_buffer(sctx, pm4);
4075 sctx->init_config = pm4;
4076 }