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radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 if (!state->rt[j].colormask)
464 continue;
465
466 /* cb_render_state will disable unused ones */
467 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
468
469 if (!state->rt[j].blend_enable) {
470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
471 continue;
472 }
473
474 /* Blending optimizations for Stoney.
475 * These transformations don't change the behavior.
476 *
477 * First, get rid of DST in the blend factors:
478 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
479 */
480 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
481 PIPE_BLENDFACTOR_DST_COLOR,
482 PIPE_BLENDFACTOR_SRC_COLOR);
483 si_blend_remove_dst(&eqA, &srcA, &dstA,
484 PIPE_BLENDFACTOR_DST_COLOR,
485 PIPE_BLENDFACTOR_SRC_COLOR);
486 si_blend_remove_dst(&eqA, &srcA, &dstA,
487 PIPE_BLENDFACTOR_DST_ALPHA,
488 PIPE_BLENDFACTOR_SRC_ALPHA);
489
490 /* Look up the ideal settings from tables. */
491 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
492 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
493 srcA_opt = si_translate_blend_opt_factor(srcA, true);
494 dstA_opt = si_translate_blend_opt_factor(dstA, true);
495
496 /* Handle interdependencies. */
497 if (si_blend_factor_uses_dst(srcRGB))
498 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
499 if (si_blend_factor_uses_dst(srcA))
500 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
501
502 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
503 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
504 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
505 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
507
508 /* Set the final value. */
509 sx_mrt_blend_opt[i] =
510 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
511 S_028760_COLOR_DST_OPT(dstRGB_opt) |
512 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
513 S_028760_ALPHA_SRC_OPT(srcA_opt) |
514 S_028760_ALPHA_DST_OPT(dstA_opt) |
515 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
516
517 /* Set blend state. */
518 blend_cntl |= S_028780_ENABLE(1);
519 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
520 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
521 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
522
523 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
524 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
525 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
526 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
527 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
528 }
529 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
530
531 blend->blend_enable_4bit |= 0xfu << (i * 4);
532
533 /* This is only important for formats without alpha. */
534 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
535 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
536 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
537 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
538 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
539 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
540 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
541 }
542
543 if (blend->cb_target_mask) {
544 color_control |= S_028808_MODE(mode);
545 } else {
546 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
547 }
548
549 if (sctx->b.family == CHIP_STONEY) {
550 for (int i = 0; i < 8; i++)
551 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
552 sx_mrt_blend_opt[i]);
553
554 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
555 if (blend->dual_src_blend || state->logicop_enable ||
556 mode == V_028808_CB_RESOLVE)
557 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
558 }
559
560 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
561 return blend;
562 }
563
564 static void *si_create_blend_state(struct pipe_context *ctx,
565 const struct pipe_blend_state *state)
566 {
567 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
568 }
569
570 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
571 {
572 struct si_context *sctx = (struct si_context *)ctx;
573 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
574 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
575 }
576
577 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
578 {
579 struct si_context *sctx = (struct si_context *)ctx;
580 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
581 }
582
583 static void si_set_blend_color(struct pipe_context *ctx,
584 const struct pipe_blend_color *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587
588 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
589 return;
590
591 sctx->blend_color.state = *state;
592 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
593 }
594
595 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
596 {
597 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
598
599 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
600 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
601 }
602
603 /*
604 * Clipping
605 */
606
607 static void si_set_clip_state(struct pipe_context *ctx,
608 const struct pipe_clip_state *state)
609 {
610 struct si_context *sctx = (struct si_context *)ctx;
611 struct pipe_constant_buffer cb;
612
613 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
614 return;
615
616 sctx->clip_state.state = *state;
617 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
618
619 cb.buffer = NULL;
620 cb.user_buffer = state->ucp;
621 cb.buffer_offset = 0;
622 cb.buffer_size = 4*4*8;
623 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
624 pipe_resource_reference(&cb.buffer, NULL);
625 }
626
627 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
628 {
629 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
630
631 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
632 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
633 }
634
635 #define SIX_BITS 0x3F
636
637 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
638 {
639 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
640 struct tgsi_shader_info *info = si_get_vs_info(sctx);
641 unsigned window_space =
642 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
643 unsigned clipdist_mask =
644 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
645
646 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
647 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
648 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
649 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
650 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
651 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
652 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
653 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
654 info->writes_edgeflag ||
655 info->writes_layer ||
656 info->writes_viewport_index) |
657 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
658 (sctx->queued.named.rasterizer->clip_plane_enable &
659 clipdist_mask));
660 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
661 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
662 (clipdist_mask ? 0 :
663 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
664 S_028810_CLIP_DISABLE(window_space));
665
666 /* reuse needs to be set off if we write oViewport */
667 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
668 S_028AB4_REUSE_OFF(info->writes_viewport_index));
669 }
670
671 /*
672 * inferred state between framebuffer and rasterizer
673 */
674 static void si_update_poly_offset_state(struct si_context *sctx)
675 {
676 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
677
678 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
679 return;
680
681 switch (sctx->framebuffer.state.zsbuf->texture->format) {
682 case PIPE_FORMAT_Z16_UNORM:
683 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
684 break;
685 default: /* 24-bit */
686 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
687 break;
688 case PIPE_FORMAT_Z32_FLOAT:
689 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
690 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
691 break;
692 }
693 }
694
695 /*
696 * Rasterizer
697 */
698
699 static uint32_t si_translate_fill(uint32_t func)
700 {
701 switch(func) {
702 case PIPE_POLYGON_MODE_FILL:
703 return V_028814_X_DRAW_TRIANGLES;
704 case PIPE_POLYGON_MODE_LINE:
705 return V_028814_X_DRAW_LINES;
706 case PIPE_POLYGON_MODE_POINT:
707 return V_028814_X_DRAW_POINTS;
708 default:
709 assert(0);
710 return V_028814_X_DRAW_POINTS;
711 }
712 }
713
714 static void *si_create_rs_state(struct pipe_context *ctx,
715 const struct pipe_rasterizer_state *state)
716 {
717 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
718 struct si_pm4_state *pm4 = &rs->pm4;
719 unsigned tmp, i;
720 float psize_min, psize_max;
721
722 if (!rs) {
723 return NULL;
724 }
725
726 rs->scissor_enable = state->scissor;
727 rs->two_side = state->light_twoside;
728 rs->multisample_enable = state->multisample;
729 rs->force_persample_interp = state->force_persample_interp;
730 rs->clip_plane_enable = state->clip_plane_enable;
731 rs->line_stipple_enable = state->line_stipple_enable;
732 rs->poly_stipple_enable = state->poly_stipple_enable;
733 rs->line_smooth = state->line_smooth;
734 rs->poly_smooth = state->poly_smooth;
735 rs->uses_poly_offset = state->offset_point || state->offset_line ||
736 state->offset_tri;
737 rs->clamp_fragment_color = state->clamp_fragment_color;
738 rs->flatshade = state->flatshade;
739 rs->sprite_coord_enable = state->sprite_coord_enable;
740 rs->rasterizer_discard = state->rasterizer_discard;
741 rs->pa_sc_line_stipple = state->line_stipple_enable ?
742 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
743 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
744 rs->pa_cl_clip_cntl =
745 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
746 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
747 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
748 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
749 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
750
751 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
752 S_0286D4_FLAT_SHADE_ENA(1) |
753 S_0286D4_PNT_SPRITE_ENA(1) |
754 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
755 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
756 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
757 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
758 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
759
760 /* point size 12.4 fixed point */
761 tmp = (unsigned)(state->point_size * 8.0);
762 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
763
764 if (state->point_size_per_vertex) {
765 psize_min = util_get_min_point_size(state);
766 psize_max = 8192;
767 } else {
768 /* Force the point size to be as if the vertex output was disabled. */
769 psize_min = state->point_size;
770 psize_max = state->point_size;
771 }
772 /* Divide by two, because 0.5 = 1 pixel. */
773 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
774 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
775 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
776
777 tmp = (unsigned)state->line_width * 8;
778 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
779 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
780 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
781 S_028A48_MSAA_ENABLE(state->multisample ||
782 state->poly_smooth ||
783 state->line_smooth) |
784 S_028A48_VPORT_SCISSOR_ENABLE(1));
785
786 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
787 S_028BE4_PIX_CENTER(state->half_pixel_center) |
788 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
789
790 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
791 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
792 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
793 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
794 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
795 S_028814_FACE(!state->front_ccw) |
796 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
797 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
798 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
799 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
800 state->fill_back != PIPE_POLYGON_MODE_FILL) |
801 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
802 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
803 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
804 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
805
806 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
807 for (i = 0; i < 3; i++) {
808 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
809 float offset_units = state->offset_units;
810 float offset_scale = state->offset_scale * 16.0f;
811 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
812
813 switch (i) {
814 case 0: /* 16-bit zbuffer */
815 offset_units *= 4.0f;
816 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
817 break;
818 case 1: /* 24-bit zbuffer */
819 offset_units *= 2.0f;
820 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
821 break;
822 case 2: /* 32-bit zbuffer */
823 offset_units *= 1.0f;
824 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
825 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
826 break;
827 }
828
829 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
830 fui(offset_scale));
831 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
832 fui(offset_units));
833 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
834 fui(offset_scale));
835 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
836 fui(offset_units));
837 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
838 pa_su_poly_offset_db_fmt_cntl);
839 }
840
841 return rs;
842 }
843
844 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
845 {
846 struct si_context *sctx = (struct si_context *)ctx;
847 struct si_state_rasterizer *old_rs =
848 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
849 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
850
851 if (!state)
852 return;
853
854 if (sctx->framebuffer.nr_samples > 1 &&
855 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
856 si_mark_atom_dirty(sctx, &sctx->db_render_state);
857
858 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
859
860 si_pm4_bind_state(sctx, rasterizer, rs);
861 si_update_poly_offset_state(sctx);
862
863 si_mark_atom_dirty(sctx, &sctx->clip_regs);
864 }
865
866 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
867 {
868 struct si_context *sctx = (struct si_context *)ctx;
869
870 if (sctx->queued.named.rasterizer == state)
871 si_pm4_bind_state(sctx, poly_offset, NULL);
872 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
873 }
874
875 /*
876 * infeered state between dsa and stencil ref
877 */
878 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
879 {
880 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
881 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
882 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
883
884 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
885 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
886 S_028430_STENCILMASK(dsa->valuemask[0]) |
887 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
888 S_028430_STENCILOPVAL(1));
889 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
890 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
891 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
892 S_028434_STENCILOPVAL_BF(1));
893 }
894
895 static void si_set_stencil_ref(struct pipe_context *ctx,
896 const struct pipe_stencil_ref *state)
897 {
898 struct si_context *sctx = (struct si_context *)ctx;
899
900 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
901 return;
902
903 sctx->stencil_ref.state = *state;
904 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
905 }
906
907
908 /*
909 * DSA
910 */
911
912 static uint32_t si_translate_stencil_op(int s_op)
913 {
914 switch (s_op) {
915 case PIPE_STENCIL_OP_KEEP:
916 return V_02842C_STENCIL_KEEP;
917 case PIPE_STENCIL_OP_ZERO:
918 return V_02842C_STENCIL_ZERO;
919 case PIPE_STENCIL_OP_REPLACE:
920 return V_02842C_STENCIL_REPLACE_TEST;
921 case PIPE_STENCIL_OP_INCR:
922 return V_02842C_STENCIL_ADD_CLAMP;
923 case PIPE_STENCIL_OP_DECR:
924 return V_02842C_STENCIL_SUB_CLAMP;
925 case PIPE_STENCIL_OP_INCR_WRAP:
926 return V_02842C_STENCIL_ADD_WRAP;
927 case PIPE_STENCIL_OP_DECR_WRAP:
928 return V_02842C_STENCIL_SUB_WRAP;
929 case PIPE_STENCIL_OP_INVERT:
930 return V_02842C_STENCIL_INVERT;
931 default:
932 R600_ERR("Unknown stencil op %d", s_op);
933 assert(0);
934 break;
935 }
936 return 0;
937 }
938
939 static void *si_create_dsa_state(struct pipe_context *ctx,
940 const struct pipe_depth_stencil_alpha_state *state)
941 {
942 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
943 struct si_pm4_state *pm4 = &dsa->pm4;
944 unsigned db_depth_control;
945 uint32_t db_stencil_control = 0;
946
947 if (!dsa) {
948 return NULL;
949 }
950
951 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
952 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
953 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
954 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
955
956 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
957 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
958 S_028800_ZFUNC(state->depth.func) |
959 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
960
961 /* stencil */
962 if (state->stencil[0].enabled) {
963 db_depth_control |= S_028800_STENCIL_ENABLE(1);
964 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
965 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
966 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
967 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
968
969 if (state->stencil[1].enabled) {
970 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
971 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
972 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
973 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
974 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
975 }
976 }
977
978 /* alpha */
979 if (state->alpha.enabled) {
980 dsa->alpha_func = state->alpha.func;
981
982 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
983 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
984 } else {
985 dsa->alpha_func = PIPE_FUNC_ALWAYS;
986 }
987
988 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
989 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
990 if (state->depth.bounds_test) {
991 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
992 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
993 }
994
995 return dsa;
996 }
997
998 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
999 {
1000 struct si_context *sctx = (struct si_context *)ctx;
1001 struct si_state_dsa *dsa = state;
1002
1003 if (!state)
1004 return;
1005
1006 si_pm4_bind_state(sctx, dsa, dsa);
1007
1008 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1009 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1010 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1011 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1012 }
1013 }
1014
1015 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1016 {
1017 struct si_context *sctx = (struct si_context *)ctx;
1018 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1019 }
1020
1021 static void *si_create_db_flush_dsa(struct si_context *sctx)
1022 {
1023 struct pipe_depth_stencil_alpha_state dsa = {};
1024
1025 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1026 }
1027
1028 /* DB RENDER STATE */
1029
1030 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1031 {
1032 struct si_context *sctx = (struct si_context*)ctx;
1033
1034 /* Pipeline stat & streamout queries. */
1035 if (enable) {
1036 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1037 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1038 } else {
1039 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1040 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1041 }
1042
1043 /* Occlusion queries. */
1044 if (sctx->occlusion_queries_disabled != !enable) {
1045 sctx->occlusion_queries_disabled = !enable;
1046 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1047 }
1048 }
1049
1050 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1051 {
1052 struct si_context *sctx = (struct si_context*)ctx;
1053
1054 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1055 }
1056
1057 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1058 {
1059 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1060 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1061 unsigned db_shader_control;
1062
1063 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1064
1065 /* DB_RENDER_CONTROL */
1066 if (sctx->dbcb_depth_copy_enabled ||
1067 sctx->dbcb_stencil_copy_enabled) {
1068 radeon_emit(cs,
1069 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1070 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1071 S_028000_COPY_CENTROID(1) |
1072 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1073 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1074 radeon_emit(cs,
1075 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1076 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1077 } else {
1078 radeon_emit(cs,
1079 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1080 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1081 }
1082
1083 /* DB_COUNT_CONTROL (occlusion queries) */
1084 if (sctx->b.num_occlusion_queries > 0 &&
1085 !sctx->occlusion_queries_disabled) {
1086 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1087
1088 if (sctx->b.chip_class >= CIK) {
1089 radeon_emit(cs,
1090 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1091 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1092 S_028004_ZPASS_ENABLE(1) |
1093 S_028004_SLICE_EVEN_ENABLE(1) |
1094 S_028004_SLICE_ODD_ENABLE(1));
1095 } else {
1096 radeon_emit(cs,
1097 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1098 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1099 }
1100 } else {
1101 /* Disable occlusion queries. */
1102 if (sctx->b.chip_class >= CIK) {
1103 radeon_emit(cs, 0);
1104 } else {
1105 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1106 }
1107 }
1108
1109 /* DB_RENDER_OVERRIDE2 */
1110 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1111 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1112 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1113 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1114
1115 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1116 sctx->ps_db_shader_control;
1117
1118 /* Bug workaround for smoothing (overrasterization) on SI. */
1119 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1120 db_shader_control &= C_02880C_Z_ORDER;
1121 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1122 }
1123
1124 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1125 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1126 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1127
1128 if (sctx->b.family == CHIP_STONEY &&
1129 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1130 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1131
1132 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1133 db_shader_control);
1134 }
1135
1136 /*
1137 * format translation
1138 */
1139 static uint32_t si_translate_colorformat(enum pipe_format format)
1140 {
1141 const struct util_format_description *desc = util_format_description(format);
1142
1143 #define HAS_SIZE(x,y,z,w) \
1144 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1145 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1146
1147 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1148 return V_028C70_COLOR_10_11_11;
1149
1150 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1151 return V_028C70_COLOR_INVALID;
1152
1153 /* hw cannot support mixed formats (except depth/stencil, since
1154 * stencil is not written to). */
1155 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1156 return V_028C70_COLOR_INVALID;
1157
1158 switch (desc->nr_channels) {
1159 case 1:
1160 switch (desc->channel[0].size) {
1161 case 8:
1162 return V_028C70_COLOR_8;
1163 case 16:
1164 return V_028C70_COLOR_16;
1165 case 32:
1166 return V_028C70_COLOR_32;
1167 }
1168 break;
1169 case 2:
1170 if (desc->channel[0].size == desc->channel[1].size) {
1171 switch (desc->channel[0].size) {
1172 case 8:
1173 return V_028C70_COLOR_8_8;
1174 case 16:
1175 return V_028C70_COLOR_16_16;
1176 case 32:
1177 return V_028C70_COLOR_32_32;
1178 }
1179 } else if (HAS_SIZE(8,24,0,0)) {
1180 return V_028C70_COLOR_24_8;
1181 } else if (HAS_SIZE(24,8,0,0)) {
1182 return V_028C70_COLOR_8_24;
1183 }
1184 break;
1185 case 3:
1186 if (HAS_SIZE(5,6,5,0)) {
1187 return V_028C70_COLOR_5_6_5;
1188 } else if (HAS_SIZE(32,8,24,0)) {
1189 return V_028C70_COLOR_X24_8_32_FLOAT;
1190 }
1191 break;
1192 case 4:
1193 if (desc->channel[0].size == desc->channel[1].size &&
1194 desc->channel[0].size == desc->channel[2].size &&
1195 desc->channel[0].size == desc->channel[3].size) {
1196 switch (desc->channel[0].size) {
1197 case 4:
1198 return V_028C70_COLOR_4_4_4_4;
1199 case 8:
1200 return V_028C70_COLOR_8_8_8_8;
1201 case 16:
1202 return V_028C70_COLOR_16_16_16_16;
1203 case 32:
1204 return V_028C70_COLOR_32_32_32_32;
1205 }
1206 } else if (HAS_SIZE(5,5,5,1)) {
1207 return V_028C70_COLOR_1_5_5_5;
1208 } else if (HAS_SIZE(10,10,10,2)) {
1209 return V_028C70_COLOR_2_10_10_10;
1210 }
1211 break;
1212 }
1213 return V_028C70_COLOR_INVALID;
1214 }
1215
1216 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1217 {
1218 if (SI_BIG_ENDIAN) {
1219 switch(colorformat) {
1220 /* 8-bit buffers. */
1221 case V_028C70_COLOR_8:
1222 return V_028C70_ENDIAN_NONE;
1223
1224 /* 16-bit buffers. */
1225 case V_028C70_COLOR_5_6_5:
1226 case V_028C70_COLOR_1_5_5_5:
1227 case V_028C70_COLOR_4_4_4_4:
1228 case V_028C70_COLOR_16:
1229 case V_028C70_COLOR_8_8:
1230 return V_028C70_ENDIAN_8IN16;
1231
1232 /* 32-bit buffers. */
1233 case V_028C70_COLOR_8_8_8_8:
1234 case V_028C70_COLOR_2_10_10_10:
1235 case V_028C70_COLOR_8_24:
1236 case V_028C70_COLOR_24_8:
1237 case V_028C70_COLOR_16_16:
1238 return V_028C70_ENDIAN_8IN32;
1239
1240 /* 64-bit buffers. */
1241 case V_028C70_COLOR_16_16_16_16:
1242 return V_028C70_ENDIAN_8IN16;
1243
1244 case V_028C70_COLOR_32_32:
1245 return V_028C70_ENDIAN_8IN32;
1246
1247 /* 128-bit buffers. */
1248 case V_028C70_COLOR_32_32_32_32:
1249 return V_028C70_ENDIAN_8IN32;
1250 default:
1251 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1252 }
1253 } else {
1254 return V_028C70_ENDIAN_NONE;
1255 }
1256 }
1257
1258 static uint32_t si_translate_dbformat(enum pipe_format format)
1259 {
1260 switch (format) {
1261 case PIPE_FORMAT_Z16_UNORM:
1262 return V_028040_Z_16;
1263 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1264 case PIPE_FORMAT_X8Z24_UNORM:
1265 case PIPE_FORMAT_Z24X8_UNORM:
1266 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1267 return V_028040_Z_24; /* deprecated on SI */
1268 case PIPE_FORMAT_Z32_FLOAT:
1269 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1270 return V_028040_Z_32_FLOAT;
1271 default:
1272 return V_028040_Z_INVALID;
1273 }
1274 }
1275
1276 /*
1277 * Texture translation
1278 */
1279
1280 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1281 enum pipe_format format,
1282 const struct util_format_description *desc,
1283 int first_non_void)
1284 {
1285 struct si_screen *sscreen = (struct si_screen*)screen;
1286 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1287 sscreen->b.info.drm_minor >= 31) ||
1288 sscreen->b.info.drm_major == 3;
1289 boolean uniform = TRUE;
1290 int i;
1291
1292 /* Colorspace (return non-RGB formats directly). */
1293 switch (desc->colorspace) {
1294 /* Depth stencil formats */
1295 case UTIL_FORMAT_COLORSPACE_ZS:
1296 switch (format) {
1297 case PIPE_FORMAT_Z16_UNORM:
1298 return V_008F14_IMG_DATA_FORMAT_16;
1299 case PIPE_FORMAT_X24S8_UINT:
1300 case PIPE_FORMAT_Z24X8_UNORM:
1301 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1302 return V_008F14_IMG_DATA_FORMAT_8_24;
1303 case PIPE_FORMAT_X8Z24_UNORM:
1304 case PIPE_FORMAT_S8X24_UINT:
1305 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1306 return V_008F14_IMG_DATA_FORMAT_24_8;
1307 case PIPE_FORMAT_S8_UINT:
1308 return V_008F14_IMG_DATA_FORMAT_8;
1309 case PIPE_FORMAT_Z32_FLOAT:
1310 return V_008F14_IMG_DATA_FORMAT_32;
1311 case PIPE_FORMAT_X32_S8X24_UINT:
1312 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1313 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1314 default:
1315 goto out_unknown;
1316 }
1317
1318 case UTIL_FORMAT_COLORSPACE_YUV:
1319 goto out_unknown; /* TODO */
1320
1321 case UTIL_FORMAT_COLORSPACE_SRGB:
1322 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1323 goto out_unknown;
1324 break;
1325
1326 default:
1327 break;
1328 }
1329
1330 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1331 if (!enable_compressed_formats)
1332 goto out_unknown;
1333
1334 switch (format) {
1335 case PIPE_FORMAT_RGTC1_SNORM:
1336 case PIPE_FORMAT_LATC1_SNORM:
1337 case PIPE_FORMAT_RGTC1_UNORM:
1338 case PIPE_FORMAT_LATC1_UNORM:
1339 return V_008F14_IMG_DATA_FORMAT_BC4;
1340 case PIPE_FORMAT_RGTC2_SNORM:
1341 case PIPE_FORMAT_LATC2_SNORM:
1342 case PIPE_FORMAT_RGTC2_UNORM:
1343 case PIPE_FORMAT_LATC2_UNORM:
1344 return V_008F14_IMG_DATA_FORMAT_BC5;
1345 default:
1346 goto out_unknown;
1347 }
1348 }
1349
1350 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1351 sscreen->b.family == CHIP_STONEY) {
1352 switch (format) {
1353 case PIPE_FORMAT_ETC1_RGB8:
1354 case PIPE_FORMAT_ETC2_RGB8:
1355 case PIPE_FORMAT_ETC2_SRGB8:
1356 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1357 case PIPE_FORMAT_ETC2_RGB8A1:
1358 case PIPE_FORMAT_ETC2_SRGB8A1:
1359 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1360 case PIPE_FORMAT_ETC2_RGBA8:
1361 case PIPE_FORMAT_ETC2_SRGBA8:
1362 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1363 case PIPE_FORMAT_ETC2_R11_UNORM:
1364 case PIPE_FORMAT_ETC2_R11_SNORM:
1365 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1366 case PIPE_FORMAT_ETC2_RG11_UNORM:
1367 case PIPE_FORMAT_ETC2_RG11_SNORM:
1368 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1369 default:
1370 goto out_unknown;
1371 }
1372 }
1373
1374 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1375 if (!enable_compressed_formats)
1376 goto out_unknown;
1377
1378 switch (format) {
1379 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1380 case PIPE_FORMAT_BPTC_SRGBA:
1381 return V_008F14_IMG_DATA_FORMAT_BC7;
1382 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1383 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1384 return V_008F14_IMG_DATA_FORMAT_BC6;
1385 default:
1386 goto out_unknown;
1387 }
1388 }
1389
1390 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1391 switch (format) {
1392 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1393 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1394 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1395 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1396 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1397 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1398 default:
1399 goto out_unknown;
1400 }
1401 }
1402
1403 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1404 if (!enable_compressed_formats)
1405 goto out_unknown;
1406
1407 if (!util_format_s3tc_enabled) {
1408 goto out_unknown;
1409 }
1410
1411 switch (format) {
1412 case PIPE_FORMAT_DXT1_RGB:
1413 case PIPE_FORMAT_DXT1_RGBA:
1414 case PIPE_FORMAT_DXT1_SRGB:
1415 case PIPE_FORMAT_DXT1_SRGBA:
1416 return V_008F14_IMG_DATA_FORMAT_BC1;
1417 case PIPE_FORMAT_DXT3_RGBA:
1418 case PIPE_FORMAT_DXT3_SRGBA:
1419 return V_008F14_IMG_DATA_FORMAT_BC2;
1420 case PIPE_FORMAT_DXT5_RGBA:
1421 case PIPE_FORMAT_DXT5_SRGBA:
1422 return V_008F14_IMG_DATA_FORMAT_BC3;
1423 default:
1424 goto out_unknown;
1425 }
1426 }
1427
1428 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1429 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1430 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1431 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1432 }
1433
1434 /* R8G8Bx_SNORM - TODO CxV8U8 */
1435
1436 /* hw cannot support mixed formats (except depth/stencil, since only
1437 * depth is read).*/
1438 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1439 goto out_unknown;
1440
1441 /* See whether the components are of the same size. */
1442 for (i = 1; i < desc->nr_channels; i++) {
1443 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1444 }
1445
1446 /* Non-uniform formats. */
1447 if (!uniform) {
1448 switch(desc->nr_channels) {
1449 case 3:
1450 if (desc->channel[0].size == 5 &&
1451 desc->channel[1].size == 6 &&
1452 desc->channel[2].size == 5) {
1453 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1454 }
1455 goto out_unknown;
1456 case 4:
1457 if (desc->channel[0].size == 5 &&
1458 desc->channel[1].size == 5 &&
1459 desc->channel[2].size == 5 &&
1460 desc->channel[3].size == 1) {
1461 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1462 }
1463 if (desc->channel[0].size == 10 &&
1464 desc->channel[1].size == 10 &&
1465 desc->channel[2].size == 10 &&
1466 desc->channel[3].size == 2) {
1467 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1468 }
1469 goto out_unknown;
1470 }
1471 goto out_unknown;
1472 }
1473
1474 if (first_non_void < 0 || first_non_void > 3)
1475 goto out_unknown;
1476
1477 /* uniform formats */
1478 switch (desc->channel[first_non_void].size) {
1479 case 4:
1480 switch (desc->nr_channels) {
1481 #if 0 /* Not supported for render targets */
1482 case 2:
1483 return V_008F14_IMG_DATA_FORMAT_4_4;
1484 #endif
1485 case 4:
1486 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1487 }
1488 break;
1489 case 8:
1490 switch (desc->nr_channels) {
1491 case 1:
1492 return V_008F14_IMG_DATA_FORMAT_8;
1493 case 2:
1494 return V_008F14_IMG_DATA_FORMAT_8_8;
1495 case 4:
1496 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1497 }
1498 break;
1499 case 16:
1500 switch (desc->nr_channels) {
1501 case 1:
1502 return V_008F14_IMG_DATA_FORMAT_16;
1503 case 2:
1504 return V_008F14_IMG_DATA_FORMAT_16_16;
1505 case 4:
1506 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1507 }
1508 break;
1509 case 32:
1510 switch (desc->nr_channels) {
1511 case 1:
1512 return V_008F14_IMG_DATA_FORMAT_32;
1513 case 2:
1514 return V_008F14_IMG_DATA_FORMAT_32_32;
1515 #if 0 /* Not supported for render targets */
1516 case 3:
1517 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1518 #endif
1519 case 4:
1520 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1521 }
1522 }
1523
1524 out_unknown:
1525 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1526 return ~0;
1527 }
1528
1529 static unsigned si_tex_wrap(unsigned wrap)
1530 {
1531 switch (wrap) {
1532 default:
1533 case PIPE_TEX_WRAP_REPEAT:
1534 return V_008F30_SQ_TEX_WRAP;
1535 case PIPE_TEX_WRAP_CLAMP:
1536 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1537 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1538 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1539 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1540 return V_008F30_SQ_TEX_CLAMP_BORDER;
1541 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1542 return V_008F30_SQ_TEX_MIRROR;
1543 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1544 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1545 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1546 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1547 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1548 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1549 }
1550 }
1551
1552 static unsigned si_tex_mipfilter(unsigned filter)
1553 {
1554 switch (filter) {
1555 case PIPE_TEX_MIPFILTER_NEAREST:
1556 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1557 case PIPE_TEX_MIPFILTER_LINEAR:
1558 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1559 default:
1560 case PIPE_TEX_MIPFILTER_NONE:
1561 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1562 }
1563 }
1564
1565 static unsigned si_tex_compare(unsigned compare)
1566 {
1567 switch (compare) {
1568 default:
1569 case PIPE_FUNC_NEVER:
1570 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1571 case PIPE_FUNC_LESS:
1572 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1573 case PIPE_FUNC_EQUAL:
1574 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1575 case PIPE_FUNC_LEQUAL:
1576 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1577 case PIPE_FUNC_GREATER:
1578 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1579 case PIPE_FUNC_NOTEQUAL:
1580 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1581 case PIPE_FUNC_GEQUAL:
1582 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1583 case PIPE_FUNC_ALWAYS:
1584 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1585 }
1586 }
1587
1588 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1589 unsigned nr_samples)
1590 {
1591 if (view_target == PIPE_TEXTURE_CUBE ||
1592 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1593 res_target = view_target;
1594
1595 switch (res_target) {
1596 default:
1597 case PIPE_TEXTURE_1D:
1598 return V_008F1C_SQ_RSRC_IMG_1D;
1599 case PIPE_TEXTURE_1D_ARRAY:
1600 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1601 case PIPE_TEXTURE_2D:
1602 case PIPE_TEXTURE_RECT:
1603 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1604 V_008F1C_SQ_RSRC_IMG_2D;
1605 case PIPE_TEXTURE_2D_ARRAY:
1606 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1607 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1608 case PIPE_TEXTURE_3D:
1609 return V_008F1C_SQ_RSRC_IMG_3D;
1610 case PIPE_TEXTURE_CUBE:
1611 case PIPE_TEXTURE_CUBE_ARRAY:
1612 return V_008F1C_SQ_RSRC_IMG_CUBE;
1613 }
1614 }
1615
1616 /*
1617 * Format support testing
1618 */
1619
1620 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1621 {
1622 return si_translate_texformat(screen, format, util_format_description(format),
1623 util_format_get_first_non_void_channel(format)) != ~0U;
1624 }
1625
1626 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1627 const struct util_format_description *desc,
1628 int first_non_void)
1629 {
1630 unsigned type;
1631 int i;
1632
1633 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1634 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1635
1636 assert(first_non_void >= 0);
1637 type = desc->channel[first_non_void].type;
1638
1639 if (type == UTIL_FORMAT_TYPE_FIXED)
1640 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1641
1642 if (desc->nr_channels == 4 &&
1643 desc->channel[0].size == 10 &&
1644 desc->channel[1].size == 10 &&
1645 desc->channel[2].size == 10 &&
1646 desc->channel[3].size == 2)
1647 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1648
1649 /* See whether the components are of the same size. */
1650 for (i = 0; i < desc->nr_channels; i++) {
1651 if (desc->channel[first_non_void].size != desc->channel[i].size)
1652 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1653 }
1654
1655 switch (desc->channel[first_non_void].size) {
1656 case 8:
1657 switch (desc->nr_channels) {
1658 case 1:
1659 return V_008F0C_BUF_DATA_FORMAT_8;
1660 case 2:
1661 return V_008F0C_BUF_DATA_FORMAT_8_8;
1662 case 3:
1663 case 4:
1664 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1665 }
1666 break;
1667 case 16:
1668 switch (desc->nr_channels) {
1669 case 1:
1670 return V_008F0C_BUF_DATA_FORMAT_16;
1671 case 2:
1672 return V_008F0C_BUF_DATA_FORMAT_16_16;
1673 case 3:
1674 case 4:
1675 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1676 }
1677 break;
1678 case 32:
1679 /* From the Southern Islands ISA documentation about MTBUF:
1680 * 'Memory reads of data in memory that is 32 or 64 bits do not
1681 * undergo any format conversion.'
1682 */
1683 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1684 !desc->channel[first_non_void].pure_integer)
1685 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1686
1687 switch (desc->nr_channels) {
1688 case 1:
1689 return V_008F0C_BUF_DATA_FORMAT_32;
1690 case 2:
1691 return V_008F0C_BUF_DATA_FORMAT_32_32;
1692 case 3:
1693 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1694 case 4:
1695 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1696 }
1697 break;
1698 }
1699
1700 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1701 }
1702
1703 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1704 const struct util_format_description *desc,
1705 int first_non_void)
1706 {
1707 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1708 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1709
1710 assert(first_non_void >= 0);
1711
1712 switch (desc->channel[first_non_void].type) {
1713 case UTIL_FORMAT_TYPE_SIGNED:
1714 if (desc->channel[first_non_void].normalized)
1715 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1716 else if (desc->channel[first_non_void].pure_integer)
1717 return V_008F0C_BUF_NUM_FORMAT_SINT;
1718 else
1719 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1720 break;
1721 case UTIL_FORMAT_TYPE_UNSIGNED:
1722 if (desc->channel[first_non_void].normalized)
1723 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1724 else if (desc->channel[first_non_void].pure_integer)
1725 return V_008F0C_BUF_NUM_FORMAT_UINT;
1726 else
1727 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1728 break;
1729 case UTIL_FORMAT_TYPE_FLOAT:
1730 default:
1731 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1732 }
1733 }
1734
1735 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1736 {
1737 const struct util_format_description *desc;
1738 int first_non_void;
1739 unsigned data_format;
1740
1741 desc = util_format_description(format);
1742 first_non_void = util_format_get_first_non_void_channel(format);
1743 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1744 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1745 }
1746
1747 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1748 {
1749 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1750 r600_translate_colorswap(format, FALSE) != ~0U;
1751 }
1752
1753 static bool si_is_zs_format_supported(enum pipe_format format)
1754 {
1755 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1756 }
1757
1758 boolean si_is_format_supported(struct pipe_screen *screen,
1759 enum pipe_format format,
1760 enum pipe_texture_target target,
1761 unsigned sample_count,
1762 unsigned usage)
1763 {
1764 unsigned retval = 0;
1765
1766 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1767 R600_ERR("r600: unsupported texture type %d\n", target);
1768 return FALSE;
1769 }
1770
1771 if (!util_format_is_supported(format, usage))
1772 return FALSE;
1773
1774 if (sample_count > 1) {
1775 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1776 return FALSE;
1777
1778 switch (sample_count) {
1779 case 2:
1780 case 4:
1781 case 8:
1782 break;
1783 case 16:
1784 if (format == PIPE_FORMAT_NONE)
1785 return TRUE;
1786 else
1787 return FALSE;
1788 default:
1789 return FALSE;
1790 }
1791 }
1792
1793 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1794 PIPE_BIND_SHADER_IMAGE)) {
1795 if (target == PIPE_BUFFER) {
1796 if (si_is_vertex_format_supported(screen, format))
1797 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1798 PIPE_BIND_SHADER_IMAGE);
1799 } else {
1800 if (si_is_sampler_format_supported(screen, format))
1801 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1802 PIPE_BIND_SHADER_IMAGE);
1803 }
1804 }
1805
1806 if ((usage & (PIPE_BIND_RENDER_TARGET |
1807 PIPE_BIND_DISPLAY_TARGET |
1808 PIPE_BIND_SCANOUT |
1809 PIPE_BIND_SHARED |
1810 PIPE_BIND_BLENDABLE)) &&
1811 si_is_colorbuffer_format_supported(format)) {
1812 retval |= usage &
1813 (PIPE_BIND_RENDER_TARGET |
1814 PIPE_BIND_DISPLAY_TARGET |
1815 PIPE_BIND_SCANOUT |
1816 PIPE_BIND_SHARED);
1817 if (!util_format_is_pure_integer(format) &&
1818 !util_format_is_depth_or_stencil(format))
1819 retval |= usage & PIPE_BIND_BLENDABLE;
1820 }
1821
1822 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1823 si_is_zs_format_supported(format)) {
1824 retval |= PIPE_BIND_DEPTH_STENCIL;
1825 }
1826
1827 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1828 si_is_vertex_format_supported(screen, format)) {
1829 retval |= PIPE_BIND_VERTEX_BUFFER;
1830 }
1831
1832 if (usage & PIPE_BIND_TRANSFER_READ)
1833 retval |= PIPE_BIND_TRANSFER_READ;
1834 if (usage & PIPE_BIND_TRANSFER_WRITE)
1835 retval |= PIPE_BIND_TRANSFER_WRITE;
1836
1837 if ((usage & PIPE_BIND_LINEAR) &&
1838 !util_format_is_compressed(format) &&
1839 !(usage & PIPE_BIND_DEPTH_STENCIL))
1840 retval |= PIPE_BIND_LINEAR;
1841
1842 return retval == usage;
1843 }
1844
1845 /*
1846 * framebuffer handling
1847 */
1848
1849 static void si_choose_spi_color_formats(struct r600_surface *surf,
1850 unsigned format, unsigned swap,
1851 unsigned ntype, bool is_depth)
1852 {
1853 /* Alpha is needed for alpha-to-coverage.
1854 * Blending may be with or without alpha.
1855 */
1856 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1857 unsigned alpha = 0; /* exports alpha, but may not support blending */
1858 unsigned blend = 0; /* supports blending, but may not export alpha */
1859 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1860
1861 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1862 * Other chips have multiple choices, though they are not necessarily better.
1863 */
1864 switch (format) {
1865 case V_028C70_COLOR_5_6_5:
1866 case V_028C70_COLOR_1_5_5_5:
1867 case V_028C70_COLOR_5_5_5_1:
1868 case V_028C70_COLOR_4_4_4_4:
1869 case V_028C70_COLOR_10_11_11:
1870 case V_028C70_COLOR_11_11_10:
1871 case V_028C70_COLOR_8:
1872 case V_028C70_COLOR_8_8:
1873 case V_028C70_COLOR_8_8_8_8:
1874 case V_028C70_COLOR_10_10_10_2:
1875 case V_028C70_COLOR_2_10_10_10:
1876 if (ntype == V_028C70_NUMBER_UINT)
1877 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1878 else if (ntype == V_028C70_NUMBER_SINT)
1879 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1880 else
1881 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1882 break;
1883
1884 case V_028C70_COLOR_16:
1885 case V_028C70_COLOR_16_16:
1886 case V_028C70_COLOR_16_16_16_16:
1887 if (ntype == V_028C70_NUMBER_UNORM ||
1888 ntype == V_028C70_NUMBER_SNORM) {
1889 /* UNORM16 and SNORM16 don't support blending */
1890 if (ntype == V_028C70_NUMBER_UNORM)
1891 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1892 else
1893 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1894
1895 /* Use 32 bits per channel for blending. */
1896 if (format == V_028C70_COLOR_16) {
1897 if (swap == V_028C70_SWAP_STD) { /* R */
1898 blend = V_028714_SPI_SHADER_32_R;
1899 blend_alpha = V_028714_SPI_SHADER_32_AR;
1900 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1901 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1902 else
1903 assert(0);
1904 } else if (format == V_028C70_COLOR_16_16) {
1905 if (swap == V_028C70_SWAP_STD) { /* RG */
1906 blend = V_028714_SPI_SHADER_32_GR;
1907 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1908 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1909 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1910 else
1911 assert(0);
1912 } else /* 16_16_16_16 */
1913 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1914 } else if (ntype == V_028C70_NUMBER_UINT)
1915 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1916 else if (ntype == V_028C70_NUMBER_SINT)
1917 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1918 else if (ntype == V_028C70_NUMBER_FLOAT)
1919 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1920 else
1921 assert(0);
1922 break;
1923
1924 case V_028C70_COLOR_32:
1925 if (swap == V_028C70_SWAP_STD) { /* R */
1926 blend = normal = V_028714_SPI_SHADER_32_R;
1927 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1928 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1929 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1930 else
1931 assert(0);
1932 break;
1933
1934 case V_028C70_COLOR_32_32:
1935 if (swap == V_028C70_SWAP_STD) { /* RG */
1936 blend = normal = V_028714_SPI_SHADER_32_GR;
1937 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1938 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1939 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1940 else
1941 assert(0);
1942 break;
1943
1944 case V_028C70_COLOR_32_32_32_32:
1945 case V_028C70_COLOR_8_24:
1946 case V_028C70_COLOR_24_8:
1947 case V_028C70_COLOR_X24_8_32_FLOAT:
1948 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1949 break;
1950
1951 default:
1952 assert(0);
1953 return;
1954 }
1955
1956 /* The DB->CB copy needs 32_ABGR. */
1957 if (is_depth)
1958 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1959
1960 surf->spi_shader_col_format = normal;
1961 surf->spi_shader_col_format_alpha = alpha;
1962 surf->spi_shader_col_format_blend = blend;
1963 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1964 }
1965
1966 static void si_initialize_color_surface(struct si_context *sctx,
1967 struct r600_surface *surf)
1968 {
1969 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1970 unsigned color_info, color_attrib, color_view;
1971 unsigned format, swap, ntype, endian;
1972 const struct util_format_description *desc;
1973 int i;
1974 unsigned blend_clamp = 0, blend_bypass = 0;
1975
1976 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1977 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1978
1979 desc = util_format_description(surf->base.format);
1980 for (i = 0; i < 4; i++) {
1981 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1982 break;
1983 }
1984 }
1985 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1986 ntype = V_028C70_NUMBER_FLOAT;
1987 } else {
1988 ntype = V_028C70_NUMBER_UNORM;
1989 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1990 ntype = V_028C70_NUMBER_SRGB;
1991 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1992 if (desc->channel[i].pure_integer) {
1993 ntype = V_028C70_NUMBER_SINT;
1994 } else {
1995 assert(desc->channel[i].normalized);
1996 ntype = V_028C70_NUMBER_SNORM;
1997 }
1998 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1999 if (desc->channel[i].pure_integer) {
2000 ntype = V_028C70_NUMBER_UINT;
2001 } else {
2002 assert(desc->channel[i].normalized);
2003 ntype = V_028C70_NUMBER_UNORM;
2004 }
2005 }
2006 }
2007
2008 format = si_translate_colorformat(surf->base.format);
2009 if (format == V_028C70_COLOR_INVALID) {
2010 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2011 }
2012 assert(format != V_028C70_COLOR_INVALID);
2013 swap = r600_translate_colorswap(surf->base.format, FALSE);
2014 endian = si_colorformat_endian_swap(format);
2015
2016 /* blend clamp should be set for all NORM/SRGB types */
2017 if (ntype == V_028C70_NUMBER_UNORM ||
2018 ntype == V_028C70_NUMBER_SNORM ||
2019 ntype == V_028C70_NUMBER_SRGB)
2020 blend_clamp = 1;
2021
2022 /* set blend bypass according to docs if SINT/UINT or
2023 8/24 COLOR variants */
2024 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2025 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2026 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2027 blend_clamp = 0;
2028 blend_bypass = 1;
2029 }
2030
2031 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2032 (format == V_028C70_COLOR_8 ||
2033 format == V_028C70_COLOR_8_8 ||
2034 format == V_028C70_COLOR_8_8_8_8))
2035 surf->color_is_int8 = true;
2036
2037 color_info = S_028C70_FORMAT(format) |
2038 S_028C70_COMP_SWAP(swap) |
2039 S_028C70_BLEND_CLAMP(blend_clamp) |
2040 S_028C70_BLEND_BYPASS(blend_bypass) |
2041 S_028C70_NUMBER_TYPE(ntype) |
2042 S_028C70_ENDIAN(endian);
2043
2044 /* Intensity is implemented as Red, so treat it that way. */
2045 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2046 util_format_is_intensity(surf->base.format));
2047
2048 if (rtex->resource.b.b.nr_samples > 1) {
2049 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2050
2051 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2052 S_028C74_NUM_FRAGMENTS(log_samples);
2053
2054 if (rtex->fmask.size) {
2055 color_info |= S_028C70_COMPRESSION(1);
2056 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2057
2058 if (sctx->b.chip_class == SI) {
2059 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2060 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2061 }
2062 }
2063 }
2064
2065 surf->cb_color_view = color_view;
2066 surf->cb_color_info = color_info;
2067 surf->cb_color_attrib = color_attrib;
2068
2069 if (sctx->b.chip_class >= VI) {
2070 unsigned max_uncompressed_block_size = 2;
2071
2072 if (rtex->surface.nsamples > 1) {
2073 if (rtex->surface.bpe == 1)
2074 max_uncompressed_block_size = 0;
2075 else if (rtex->surface.bpe == 2)
2076 max_uncompressed_block_size = 1;
2077 }
2078
2079 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2080 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2081 }
2082
2083 /* This must be set for fast clear to work without FMASK. */
2084 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2085 unsigned bankh = util_logbase2(rtex->surface.bankh);
2086 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2087 }
2088
2089 /* Determine pixel shader export format */
2090 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2091
2092 surf->color_initialized = true;
2093 }
2094
2095 static void si_init_depth_surface(struct si_context *sctx,
2096 struct r600_surface *surf)
2097 {
2098 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2099 unsigned level = surf->base.u.tex.level;
2100 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2101 unsigned format;
2102 uint32_t z_info, s_info, db_depth_info;
2103 uint64_t z_offs, s_offs;
2104 uint32_t db_htile_data_base, db_htile_surface;
2105
2106 format = si_translate_dbformat(rtex->resource.b.b.format);
2107
2108 if (format == V_028040_Z_INVALID) {
2109 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2110 }
2111 assert(format != V_028040_Z_INVALID);
2112
2113 s_offs = z_offs = rtex->resource.gpu_address;
2114 z_offs += rtex->surface.level[level].offset;
2115 s_offs += rtex->surface.stencil_level[level].offset;
2116
2117 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2118
2119 z_info = S_028040_FORMAT(format);
2120 if (rtex->resource.b.b.nr_samples > 1) {
2121 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2122 }
2123
2124 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2125 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2126 else
2127 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2128
2129 if (sctx->b.chip_class >= CIK) {
2130 struct radeon_info *info = &sctx->screen->b.info;
2131 unsigned index = rtex->surface.tiling_index[level];
2132 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2133 unsigned macro_index = rtex->surface.macro_tile_index;
2134 unsigned tile_mode = info->si_tile_mode_array[index];
2135 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2136 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2137
2138 db_depth_info |=
2139 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2140 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2141 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2142 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2143 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2144 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2145 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2146 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2147 } else {
2148 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2149 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2150 tile_mode_index = si_tile_mode_index(rtex, level, true);
2151 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2152 }
2153
2154 /* HiZ aka depth buffer htile */
2155 /* use htile only for first level */
2156 if (rtex->htile_buffer && !level) {
2157 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2158 S_028040_ALLOW_EXPCLEAR(1);
2159
2160 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2161 /* Workaround: For a not yet understood reason, the
2162 * combination of MSAA, fast stencil clear and stencil
2163 * decompress messes with subsequent stencil buffer
2164 * uses. Problem was reproduced on Verde, Bonaire,
2165 * Tonga, and Carrizo.
2166 *
2167 * Disabling EXPCLEAR works around the problem.
2168 *
2169 * Check piglit's arb_texture_multisample-stencil-clear
2170 * test if you want to try changing this.
2171 */
2172 if (rtex->resource.b.b.nr_samples <= 1)
2173 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2174 } else
2175 /* Use all of the htile_buffer for depth if there's no stencil. */
2176 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2177
2178 uint64_t va = rtex->htile_buffer->gpu_address;
2179 db_htile_data_base = va >> 8;
2180 db_htile_surface = S_028ABC_FULL_CACHE(1);
2181 } else {
2182 db_htile_data_base = 0;
2183 db_htile_surface = 0;
2184 }
2185
2186 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2187
2188 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2189 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2190 surf->db_htile_data_base = db_htile_data_base;
2191 surf->db_depth_info = db_depth_info;
2192 surf->db_z_info = z_info;
2193 surf->db_stencil_info = s_info;
2194 surf->db_depth_base = z_offs >> 8;
2195 surf->db_stencil_base = s_offs >> 8;
2196 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2197 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2198 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2199 levelinfo->nblk_y) / 64 - 1);
2200 surf->db_htile_surface = db_htile_surface;
2201
2202 surf->depth_initialized = true;
2203 }
2204
2205 void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2206 {
2207 for (int i = 0; i < state->nr_cbufs; ++i) {
2208 struct r600_surface *surf = NULL;
2209 struct r600_texture *rtex;
2210
2211 if (!state->cbufs[i])
2212 continue;
2213 surf = (struct r600_surface*)state->cbufs[i];
2214 rtex = (struct r600_texture*)surf->base.texture;
2215
2216 p_atomic_dec(&rtex->framebuffers_bound);
2217 }
2218 }
2219
2220 static void si_set_framebuffer_state(struct pipe_context *ctx,
2221 const struct pipe_framebuffer_state *state)
2222 {
2223 struct si_context *sctx = (struct si_context *)ctx;
2224 struct pipe_constant_buffer constbuf = {0};
2225 struct r600_surface *surf = NULL;
2226 struct r600_texture *rtex;
2227 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2228 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2229 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2230 int i;
2231
2232 /* Only flush TC when changing the framebuffer state, because
2233 * the only client not using TC that can change textures is
2234 * the framebuffer.
2235 *
2236 * Flush all CB and DB caches here because all buffers can be used
2237 * for write by both TC (with shader image stores) and CB/DB.
2238 */
2239 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2240 SI_CONTEXT_INV_GLOBAL_L2 |
2241 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2242 SI_CONTEXT_CS_PARTIAL_FLUSH;
2243
2244 /* Take the maximum of the old and new count. If the new count is lower,
2245 * dirtying is needed to disable the unbound colorbuffers.
2246 */
2247 sctx->framebuffer.dirty_cbufs |=
2248 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2249 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2250
2251 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2252 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2253
2254 sctx->framebuffer.spi_shader_col_format = 0;
2255 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2256 sctx->framebuffer.spi_shader_col_format_blend = 0;
2257 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2258 sctx->framebuffer.color_is_int8 = 0;
2259
2260 sctx->framebuffer.compressed_cb_mask = 0;
2261 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2262 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2263 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2264 util_format_is_pure_integer(state->cbufs[0]->format);
2265 sctx->framebuffer.any_dst_linear = false;
2266
2267 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2268 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2269
2270 for (i = 0; i < state->nr_cbufs; i++) {
2271 if (!state->cbufs[i])
2272 continue;
2273
2274 surf = (struct r600_surface*)state->cbufs[i];
2275 rtex = (struct r600_texture*)surf->base.texture;
2276
2277 if (!surf->color_initialized) {
2278 si_initialize_color_surface(sctx, surf);
2279 }
2280
2281 sctx->framebuffer.spi_shader_col_format |=
2282 surf->spi_shader_col_format << (i * 4);
2283 sctx->framebuffer.spi_shader_col_format_alpha |=
2284 surf->spi_shader_col_format_alpha << (i * 4);
2285 sctx->framebuffer.spi_shader_col_format_blend |=
2286 surf->spi_shader_col_format_blend << (i * 4);
2287 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2288 surf->spi_shader_col_format_blend_alpha << (i * 4);
2289
2290 if (surf->color_is_int8)
2291 sctx->framebuffer.color_is_int8 |= 1 << i;
2292
2293 if (rtex->fmask.size && rtex->cmask.size) {
2294 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2295 }
2296
2297 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2298 sctx->framebuffer.any_dst_linear = true;
2299
2300 r600_context_add_resource_size(ctx, surf->base.texture);
2301
2302 p_atomic_inc(&rtex->framebuffers_bound);
2303 }
2304 /* Set the second SPI format for possible dual-src blending. */
2305 if (i == 1 && surf) {
2306 sctx->framebuffer.spi_shader_col_format |=
2307 surf->spi_shader_col_format << (i * 4);
2308 sctx->framebuffer.spi_shader_col_format_alpha |=
2309 surf->spi_shader_col_format_alpha << (i * 4);
2310 sctx->framebuffer.spi_shader_col_format_blend |=
2311 surf->spi_shader_col_format_blend << (i * 4);
2312 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2313 surf->spi_shader_col_format_blend_alpha << (i * 4);
2314 }
2315
2316 if (state->zsbuf) {
2317 surf = (struct r600_surface*)state->zsbuf;
2318
2319 if (!surf->depth_initialized) {
2320 si_init_depth_surface(sctx, surf);
2321 }
2322 r600_context_add_resource_size(ctx, surf->base.texture);
2323 }
2324
2325 si_update_poly_offset_state(sctx);
2326 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2327 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2328
2329 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2330 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2331
2332 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2333 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2334 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2335
2336 /* Set sample locations as fragment shader constants. */
2337 switch (sctx->framebuffer.nr_samples) {
2338 case 1:
2339 constbuf.user_buffer = sctx->b.sample_locations_1x;
2340 break;
2341 case 2:
2342 constbuf.user_buffer = sctx->b.sample_locations_2x;
2343 break;
2344 case 4:
2345 constbuf.user_buffer = sctx->b.sample_locations_4x;
2346 break;
2347 case 8:
2348 constbuf.user_buffer = sctx->b.sample_locations_8x;
2349 break;
2350 case 16:
2351 constbuf.user_buffer = sctx->b.sample_locations_16x;
2352 break;
2353 default:
2354 R600_ERR("Requested an invalid number of samples %i.\n",
2355 sctx->framebuffer.nr_samples);
2356 assert(0);
2357 }
2358 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2359 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2360
2361 /* Smoothing (only possible with nr_samples == 1) uses the same
2362 * sample locations as the MSAA it simulates.
2363 *
2364 * Therefore, don't update the sample locations when
2365 * transitioning from no AA to smoothing-equivalent AA, and
2366 * vice versa.
2367 */
2368 if ((sctx->framebuffer.nr_samples != 1 ||
2369 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2370 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2371 old_nr_samples != 1))
2372 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2373 }
2374
2375 sctx->need_check_render_feedback = true;
2376 }
2377
2378 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2379 {
2380 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2381 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2382 unsigned i, nr_cbufs = state->nr_cbufs;
2383 struct r600_texture *tex = NULL;
2384 struct r600_surface *cb = NULL;
2385 unsigned cb_color_info = 0;
2386
2387 /* Colorbuffers. */
2388 for (i = 0; i < nr_cbufs; i++) {
2389 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2390 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2391 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2392
2393 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2394 continue;
2395
2396 cb = (struct r600_surface*)state->cbufs[i];
2397 if (!cb) {
2398 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2399 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2400 continue;
2401 }
2402
2403 tex = (struct r600_texture *)cb->base.texture;
2404 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2405 &tex->resource, RADEON_USAGE_READWRITE,
2406 tex->surface.nsamples > 1 ?
2407 RADEON_PRIO_COLOR_BUFFER_MSAA :
2408 RADEON_PRIO_COLOR_BUFFER);
2409
2410 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2411 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2412 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2413 RADEON_PRIO_CMASK);
2414 }
2415
2416 /* Compute mutable surface parameters. */
2417 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2418 slice_tile_max = cb->level_info->nblk_x *
2419 cb->level_info->nblk_y / 64 - 1;
2420 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2421
2422 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2423 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2424 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2425 cb_color_attrib = cb->cb_color_attrib |
2426 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2427
2428 if (tex->fmask.size) {
2429 if (sctx->b.chip_class >= CIK)
2430 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2431 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2432 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2433 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2434 } else {
2435 /* This must be set for fast clear to work without FMASK. */
2436 if (sctx->b.chip_class >= CIK)
2437 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2438 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2439 cb_color_fmask = cb_color_base;
2440 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2441 }
2442
2443 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2444
2445 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2446 bool is_msaa_resolve_dst = state->cbufs[0] &&
2447 state->cbufs[0]->texture->nr_samples > 1 &&
2448 state->cbufs[1] == &cb->base &&
2449 state->cbufs[1]->texture->nr_samples <= 1;
2450
2451 if (!is_msaa_resolve_dst)
2452 cb_color_info |= S_028C70_DCC_ENABLE(1);
2453 }
2454
2455 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2456 sctx->b.chip_class >= VI ? 14 : 13);
2457 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2458 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2459 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2460 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2461 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2462 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2463 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2464 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2465 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2466 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2467 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2468 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2469 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2470
2471 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2472 radeon_emit(cs, (tex->resource.gpu_address +
2473 tex->dcc_offset +
2474 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2475 }
2476 /* set CB_COLOR1_INFO for possible dual-src blending */
2477 if (i == 1 && state->cbufs[0] &&
2478 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2479 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2480 cb_color_info);
2481 i++;
2482 }
2483 for (; i < 8 ; i++)
2484 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2485 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2486
2487 /* ZS buffer. */
2488 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2489 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2490 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2491
2492 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2493 &rtex->resource, RADEON_USAGE_READWRITE,
2494 zb->base.texture->nr_samples > 1 ?
2495 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2496 RADEON_PRIO_DEPTH_BUFFER);
2497
2498 if (zb->db_htile_data_base) {
2499 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2500 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2501 RADEON_PRIO_HTILE);
2502 }
2503
2504 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2505 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2506
2507 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2508 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2509 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2510 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2511 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2512 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2513 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2514 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2515 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2516 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2517 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2518
2519 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2520 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2521 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2522
2523 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2524 } else if (sctx->framebuffer.dirty_zsbuf) {
2525 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2526 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2527 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2528 }
2529
2530 /* Framebuffer dimensions. */
2531 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2532 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2533 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2534
2535 sctx->framebuffer.dirty_cbufs = 0;
2536 sctx->framebuffer.dirty_zsbuf = false;
2537 }
2538
2539 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2540 struct r600_atom *atom)
2541 {
2542 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2543 unsigned nr_samples = sctx->framebuffer.nr_samples;
2544
2545 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2546 SI_NUM_SMOOTH_AA_SAMPLES);
2547 }
2548
2549 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2550 {
2551 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2552 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2553 /* 33% faster rendering to linear color buffers */
2554 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2555 unsigned sc_mode_cntl_1 =
2556 S_028A4C_WALK_SIZE(dst_is_linear) |
2557 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2558 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2559 /* always 1: */
2560 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2561 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2562 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2563 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2564 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2565 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2566
2567 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2568 sctx->ps_iter_samples,
2569 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2570 sc_mode_cntl_1);
2571 }
2572
2573 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2574 {
2575 struct si_context *sctx = (struct si_context *)ctx;
2576
2577 if (sctx->ps_iter_samples == min_samples)
2578 return;
2579
2580 sctx->ps_iter_samples = min_samples;
2581
2582 if (sctx->framebuffer.nr_samples > 1)
2583 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2584 }
2585
2586 /*
2587 * Samplers
2588 */
2589
2590 /**
2591 * Build the sampler view descriptor for a buffer texture.
2592 * @param state 256-bit descriptor; only the high 128 bits are filled in
2593 */
2594 void
2595 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2596 enum pipe_format format,
2597 unsigned first_element, unsigned last_element,
2598 uint32_t *state)
2599 {
2600 const struct util_format_description *desc;
2601 int first_non_void;
2602 uint64_t va;
2603 unsigned stride;
2604 unsigned num_records;
2605 unsigned num_format, data_format;
2606
2607 desc = util_format_description(format);
2608 first_non_void = util_format_get_first_non_void_channel(format);
2609 stride = desc->block.bits / 8;
2610 va = buf->gpu_address + first_element * stride;
2611 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2612 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2613
2614 num_records = last_element + 1 - first_element;
2615 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2616
2617 if (screen->b.chip_class >= VI)
2618 num_records *= stride;
2619
2620 state[4] = va;
2621 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2622 S_008F04_STRIDE(stride);
2623 state[6] = num_records;
2624 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2625 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2626 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2627 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2628 S_008F0C_NUM_FORMAT(num_format) |
2629 S_008F0C_DATA_FORMAT(data_format);
2630 }
2631
2632 /**
2633 * Build the sampler view descriptor for a texture.
2634 */
2635 void
2636 si_make_texture_descriptor(struct si_screen *screen,
2637 struct r600_texture *tex,
2638 bool sampler,
2639 enum pipe_texture_target target,
2640 enum pipe_format pipe_format,
2641 const unsigned char state_swizzle[4],
2642 unsigned first_level, unsigned last_level,
2643 unsigned first_layer, unsigned last_layer,
2644 unsigned width, unsigned height, unsigned depth,
2645 uint32_t *state,
2646 uint32_t *fmask_state)
2647 {
2648 struct pipe_resource *res = &tex->resource.b.b;
2649 const struct util_format_description *desc;
2650 unsigned char swizzle[4];
2651 int first_non_void;
2652 unsigned num_format, data_format, type;
2653 uint64_t va;
2654
2655 desc = util_format_description(pipe_format);
2656
2657 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2658 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2659 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2660
2661 switch (pipe_format) {
2662 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2663 case PIPE_FORMAT_X24S8_UINT:
2664 case PIPE_FORMAT_X32_S8X24_UINT:
2665 case PIPE_FORMAT_X8Z24_UNORM:
2666 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2667 break;
2668 default:
2669 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2670 }
2671 } else {
2672 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2673 }
2674
2675 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2676
2677 switch (pipe_format) {
2678 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2679 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2680 break;
2681 default:
2682 if (first_non_void < 0) {
2683 if (util_format_is_compressed(pipe_format)) {
2684 switch (pipe_format) {
2685 case PIPE_FORMAT_DXT1_SRGB:
2686 case PIPE_FORMAT_DXT1_SRGBA:
2687 case PIPE_FORMAT_DXT3_SRGBA:
2688 case PIPE_FORMAT_DXT5_SRGBA:
2689 case PIPE_FORMAT_BPTC_SRGBA:
2690 case PIPE_FORMAT_ETC2_SRGB8:
2691 case PIPE_FORMAT_ETC2_SRGB8A1:
2692 case PIPE_FORMAT_ETC2_SRGBA8:
2693 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2694 break;
2695 case PIPE_FORMAT_RGTC1_SNORM:
2696 case PIPE_FORMAT_LATC1_SNORM:
2697 case PIPE_FORMAT_RGTC2_SNORM:
2698 case PIPE_FORMAT_LATC2_SNORM:
2699 case PIPE_FORMAT_ETC2_R11_SNORM:
2700 case PIPE_FORMAT_ETC2_RG11_SNORM:
2701 /* implies float, so use SNORM/UNORM to determine
2702 whether data is signed or not */
2703 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2704 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2705 break;
2706 default:
2707 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2708 break;
2709 }
2710 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2711 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2712 } else {
2713 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2714 }
2715 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2716 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2717 } else {
2718 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2719
2720 switch (desc->channel[first_non_void].type) {
2721 case UTIL_FORMAT_TYPE_FLOAT:
2722 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2723 break;
2724 case UTIL_FORMAT_TYPE_SIGNED:
2725 if (desc->channel[first_non_void].normalized)
2726 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2727 else if (desc->channel[first_non_void].pure_integer)
2728 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2729 else
2730 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2731 break;
2732 case UTIL_FORMAT_TYPE_UNSIGNED:
2733 if (desc->channel[first_non_void].normalized)
2734 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2735 else if (desc->channel[first_non_void].pure_integer)
2736 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2737 else
2738 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2739 }
2740 }
2741 }
2742
2743 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2744 if (data_format == ~0) {
2745 data_format = 0;
2746 }
2747
2748 if (!sampler &&
2749 (res->target == PIPE_TEXTURE_CUBE ||
2750 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2751 res->target == PIPE_TEXTURE_3D)) {
2752 /* For the purpose of shader images, treat cube maps and 3D
2753 * textures as 2D arrays. For 3D textures, the address
2754 * calculations for mipmaps are different, so we rely on the
2755 * caller to effectively disable mipmaps.
2756 */
2757 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2758
2759 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2760 } else {
2761 type = si_tex_dim(res->target, target, res->nr_samples);
2762 }
2763
2764 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2765 height = 1;
2766 depth = res->array_size;
2767 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2768 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2769 if (sampler || res->target != PIPE_TEXTURE_3D)
2770 depth = res->array_size;
2771 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2772 depth = res->array_size / 6;
2773
2774 state[0] = 0;
2775 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2776 S_008F14_NUM_FORMAT(num_format));
2777 state[2] = (S_008F18_WIDTH(width - 1) |
2778 S_008F18_HEIGHT(height - 1));
2779 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2780 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2781 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2782 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2783 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2784 0 : first_level) |
2785 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2786 util_logbase2(res->nr_samples) :
2787 last_level) |
2788 S_008F1C_POW2_PAD(res->last_level > 0) |
2789 S_008F1C_TYPE(type));
2790 state[4] = S_008F20_DEPTH(depth - 1);
2791 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2792 S_008F24_LAST_ARRAY(last_layer));
2793 state[6] = 0;
2794 state[7] = 0;
2795
2796 if (tex->dcc_offset) {
2797 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2798
2799 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2800 } else {
2801 /* The last dword is unused by hw. The shader uses it to clear
2802 * bits in the first dword of sampler state.
2803 */
2804 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2805 if (first_level == last_level)
2806 state[7] = C_008F30_MAX_ANISO_RATIO;
2807 else
2808 state[7] = 0xffffffff;
2809 }
2810 }
2811
2812 /* Initialize the sampler view for FMASK. */
2813 if (tex->fmask.size) {
2814 uint32_t fmask_format;
2815
2816 va = tex->resource.gpu_address + tex->fmask.offset;
2817
2818 switch (res->nr_samples) {
2819 case 2:
2820 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2821 break;
2822 case 4:
2823 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2824 break;
2825 case 8:
2826 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2827 break;
2828 default:
2829 assert(0);
2830 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2831 }
2832
2833 fmask_state[0] = va >> 8;
2834 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2835 S_008F14_DATA_FORMAT(fmask_format) |
2836 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2837 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2838 S_008F18_HEIGHT(height - 1);
2839 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2840 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2841 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2842 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2843 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2844 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2845 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2846 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2847 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2848 S_008F24_LAST_ARRAY(last_layer);
2849 fmask_state[6] = 0;
2850 fmask_state[7] = 0;
2851 }
2852 }
2853
2854 /**
2855 * Create a sampler view.
2856 *
2857 * @param ctx context
2858 * @param texture texture
2859 * @param state sampler view template
2860 * @param width0 width0 override (for compressed textures as int)
2861 * @param height0 height0 override (for compressed textures as int)
2862 * @param force_level set the base address to the level (for compressed textures)
2863 */
2864 struct pipe_sampler_view *
2865 si_create_sampler_view_custom(struct pipe_context *ctx,
2866 struct pipe_resource *texture,
2867 const struct pipe_sampler_view *state,
2868 unsigned width0, unsigned height0,
2869 unsigned force_level)
2870 {
2871 struct si_context *sctx = (struct si_context*)ctx;
2872 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2873 struct r600_texture *tmp = (struct r600_texture*)texture;
2874 unsigned base_level, first_level, last_level;
2875 unsigned char state_swizzle[4];
2876 unsigned height, depth, width;
2877 unsigned last_layer = state->u.tex.last_layer;
2878 enum pipe_format pipe_format;
2879 const struct radeon_surf_level *surflevel;
2880
2881 if (!view)
2882 return NULL;
2883
2884 /* initialize base object */
2885 view->base = *state;
2886 view->base.texture = NULL;
2887 view->base.reference.count = 1;
2888 view->base.context = ctx;
2889
2890 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2891 if (!texture) {
2892 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2893 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2894 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2895 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2896 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2897 return &view->base;
2898 }
2899
2900 pipe_resource_reference(&view->base.texture, texture);
2901
2902 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2903 state->format == PIPE_FORMAT_S8X24_UINT ||
2904 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2905 state->format == PIPE_FORMAT_S8_UINT)
2906 view->is_stencil_sampler = true;
2907
2908 /* Buffer resource. */
2909 if (texture->target == PIPE_BUFFER) {
2910 si_make_buffer_descriptor(sctx->screen,
2911 (struct r600_resource *)texture,
2912 state->format,
2913 state->u.buf.first_element,
2914 state->u.buf.last_element,
2915 view->state);
2916
2917 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2918 return &view->base;
2919 }
2920
2921 state_swizzle[0] = state->swizzle_r;
2922 state_swizzle[1] = state->swizzle_g;
2923 state_swizzle[2] = state->swizzle_b;
2924 state_swizzle[3] = state->swizzle_a;
2925
2926 base_level = 0;
2927 first_level = state->u.tex.first_level;
2928 last_level = state->u.tex.last_level;
2929 width = width0;
2930 height = height0;
2931 depth = texture->depth0;
2932
2933 if (force_level) {
2934 assert(force_level == first_level &&
2935 force_level == last_level);
2936 base_level = force_level;
2937 first_level = 0;
2938 last_level = 0;
2939 width = u_minify(width, force_level);
2940 height = u_minify(height, force_level);
2941 depth = u_minify(depth, force_level);
2942 }
2943
2944 /* This is not needed if state trackers set last_layer correctly. */
2945 if (state->target == PIPE_TEXTURE_1D ||
2946 state->target == PIPE_TEXTURE_2D ||
2947 state->target == PIPE_TEXTURE_RECT ||
2948 state->target == PIPE_TEXTURE_CUBE)
2949 last_layer = state->u.tex.first_layer;
2950
2951 /* Texturing with separate depth and stencil. */
2952 pipe_format = state->format;
2953 surflevel = tmp->surface.level;
2954
2955 if (tmp->is_depth && !tmp->is_flushing_texture) {
2956 switch (pipe_format) {
2957 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2958 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2959 break;
2960 case PIPE_FORMAT_X8Z24_UNORM:
2961 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2962 /* Z24 is always stored like this. */
2963 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2964 break;
2965 case PIPE_FORMAT_X24S8_UINT:
2966 case PIPE_FORMAT_S8X24_UINT:
2967 case PIPE_FORMAT_X32_S8X24_UINT:
2968 pipe_format = PIPE_FORMAT_S8_UINT;
2969 surflevel = tmp->surface.stencil_level;
2970 break;
2971 default:;
2972 }
2973 }
2974
2975 si_make_texture_descriptor(sctx->screen, tmp, true,
2976 state->target, pipe_format, state_swizzle,
2977 first_level, last_level,
2978 state->u.tex.first_layer, last_layer,
2979 width, height, depth,
2980 view->state, view->fmask_state);
2981
2982 view->base_level_info = &surflevel[base_level];
2983 view->base_level = base_level;
2984 view->block_width = util_format_get_blockwidth(pipe_format);
2985 return &view->base;
2986 }
2987
2988 static struct pipe_sampler_view *
2989 si_create_sampler_view(struct pipe_context *ctx,
2990 struct pipe_resource *texture,
2991 const struct pipe_sampler_view *state)
2992 {
2993 return si_create_sampler_view_custom(ctx, texture, state,
2994 texture ? texture->width0 : 0,
2995 texture ? texture->height0 : 0, 0);
2996 }
2997
2998 static void si_sampler_view_destroy(struct pipe_context *ctx,
2999 struct pipe_sampler_view *state)
3000 {
3001 struct si_sampler_view *view = (struct si_sampler_view *)state;
3002
3003 if (state->texture && state->texture->target == PIPE_BUFFER)
3004 LIST_DELINIT(&view->list);
3005
3006 pipe_resource_reference(&state->texture, NULL);
3007 FREE(view);
3008 }
3009
3010 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3011 {
3012 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3013 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3014 (linear_filter &&
3015 (wrap == PIPE_TEX_WRAP_CLAMP ||
3016 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3017 }
3018
3019 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3020 {
3021 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3022 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3023
3024 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3025 state->border_color.ui[2] || state->border_color.ui[3]) &&
3026 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3027 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3028 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3029 }
3030
3031 static void *si_create_sampler_state(struct pipe_context *ctx,
3032 const struct pipe_sampler_state *state)
3033 {
3034 struct si_context *sctx = (struct si_context *)ctx;
3035 struct r600_common_screen *rscreen = sctx->b.screen;
3036 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3037 unsigned border_color_type, border_color_index = 0;
3038 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3039 : state->max_anisotropy;
3040 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3041
3042 if (!rstate) {
3043 return NULL;
3044 }
3045
3046 if (!sampler_state_needs_border_color(state))
3047 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3048 else if (state->border_color.f[0] == 0 &&
3049 state->border_color.f[1] == 0 &&
3050 state->border_color.f[2] == 0 &&
3051 state->border_color.f[3] == 0)
3052 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3053 else if (state->border_color.f[0] == 0 &&
3054 state->border_color.f[1] == 0 &&
3055 state->border_color.f[2] == 0 &&
3056 state->border_color.f[3] == 1)
3057 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3058 else if (state->border_color.f[0] == 1 &&
3059 state->border_color.f[1] == 1 &&
3060 state->border_color.f[2] == 1 &&
3061 state->border_color.f[3] == 1)
3062 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3063 else {
3064 int i;
3065
3066 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3067
3068 /* Check if the border has been uploaded already. */
3069 for (i = 0; i < sctx->border_color_count; i++)
3070 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3071 sizeof(state->border_color)) == 0)
3072 break;
3073
3074 if (i >= SI_MAX_BORDER_COLORS) {
3075 /* Getting 4096 unique border colors is very unlikely. */
3076 fprintf(stderr, "radeonsi: The border color table is full. "
3077 "Any new border colors will be just black. "
3078 "Please file a bug.\n");
3079 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3080 } else {
3081 if (i == sctx->border_color_count) {
3082 /* Upload a new border color. */
3083 memcpy(&sctx->border_color_table[i], &state->border_color,
3084 sizeof(state->border_color));
3085 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3086 &state->border_color,
3087 sizeof(state->border_color));
3088 sctx->border_color_count++;
3089 }
3090
3091 border_color_index = i;
3092 }
3093 }
3094
3095 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3096 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3097 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3098 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3099 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3100 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3101 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3102 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3103 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3104 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3105 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3106 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3107 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3108 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3109 S_008F38_MIP_POINT_PRECLAMP(1) |
3110 S_008F38_DISABLE_LSB_CEIL(1) |
3111 S_008F38_FILTER_PREC_FIX(1) |
3112 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3113 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3114 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3115 return rstate;
3116 }
3117
3118 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3119 {
3120 struct si_context *sctx = (struct si_context *)ctx;
3121
3122 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3123 return;
3124
3125 sctx->sample_mask.sample_mask = sample_mask;
3126 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3127 }
3128
3129 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3130 {
3131 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3132 unsigned mask = sctx->sample_mask.sample_mask;
3133
3134 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3135 radeon_emit(cs, mask | (mask << 16));
3136 radeon_emit(cs, mask | (mask << 16));
3137 }
3138
3139 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3140 {
3141 free(state);
3142 }
3143
3144 /*
3145 * Vertex elements & buffers
3146 */
3147
3148 static void *si_create_vertex_elements(struct pipe_context *ctx,
3149 unsigned count,
3150 const struct pipe_vertex_element *elements)
3151 {
3152 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3153 int i;
3154
3155 assert(count <= SI_MAX_ATTRIBS);
3156 if (!v)
3157 return NULL;
3158
3159 v->count = count;
3160 for (i = 0; i < count; ++i) {
3161 const struct util_format_description *desc;
3162 unsigned data_format, num_format;
3163 int first_non_void;
3164
3165 desc = util_format_description(elements[i].src_format);
3166 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3167 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3168 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3169
3170 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3171 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3172 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3173 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3174 S_008F0C_NUM_FORMAT(num_format) |
3175 S_008F0C_DATA_FORMAT(data_format);
3176 v->format_size[i] = desc->block.bits / 8;
3177 }
3178 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3179
3180 return v;
3181 }
3182
3183 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3184 {
3185 struct si_context *sctx = (struct si_context *)ctx;
3186 struct si_vertex_element *v = (struct si_vertex_element*)state;
3187
3188 sctx->vertex_elements = v;
3189 sctx->vertex_buffers_dirty = true;
3190 }
3191
3192 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3193 {
3194 struct si_context *sctx = (struct si_context *)ctx;
3195
3196 if (sctx->vertex_elements == state)
3197 sctx->vertex_elements = NULL;
3198 FREE(state);
3199 }
3200
3201 static void si_set_vertex_buffers(struct pipe_context *ctx,
3202 unsigned start_slot, unsigned count,
3203 const struct pipe_vertex_buffer *buffers)
3204 {
3205 struct si_context *sctx = (struct si_context *)ctx;
3206 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3207 int i;
3208
3209 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3210
3211 if (buffers) {
3212 for (i = 0; i < count; i++) {
3213 const struct pipe_vertex_buffer *src = buffers + i;
3214 struct pipe_vertex_buffer *dsti = dst + i;
3215
3216 pipe_resource_reference(&dsti->buffer, src->buffer);
3217 dsti->buffer_offset = src->buffer_offset;
3218 dsti->stride = src->stride;
3219 r600_context_add_resource_size(ctx, src->buffer);
3220 }
3221 } else {
3222 for (i = 0; i < count; i++) {
3223 pipe_resource_reference(&dst[i].buffer, NULL);
3224 }
3225 }
3226 sctx->vertex_buffers_dirty = true;
3227 }
3228
3229 static void si_set_index_buffer(struct pipe_context *ctx,
3230 const struct pipe_index_buffer *ib)
3231 {
3232 struct si_context *sctx = (struct si_context *)ctx;
3233
3234 if (ib) {
3235 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3236 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3237 r600_context_add_resource_size(ctx, ib->buffer);
3238 } else {
3239 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3240 }
3241 }
3242
3243 /*
3244 * Misc
3245 */
3246
3247 static void si_set_tess_state(struct pipe_context *ctx,
3248 const float default_outer_level[4],
3249 const float default_inner_level[2])
3250 {
3251 struct si_context *sctx = (struct si_context *)ctx;
3252 struct pipe_constant_buffer cb;
3253 float array[8];
3254
3255 memcpy(array, default_outer_level, sizeof(float) * 4);
3256 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3257
3258 cb.buffer = NULL;
3259 cb.user_buffer = NULL;
3260 cb.buffer_size = sizeof(array);
3261
3262 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3263 (void*)array, sizeof(array),
3264 &cb.buffer_offset);
3265
3266 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3267 pipe_resource_reference(&cb.buffer, NULL);
3268 }
3269
3270 static void si_texture_barrier(struct pipe_context *ctx)
3271 {
3272 struct si_context *sctx = (struct si_context *)ctx;
3273
3274 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3275 SI_CONTEXT_INV_GLOBAL_L2 |
3276 SI_CONTEXT_FLUSH_AND_INV_CB |
3277 SI_CONTEXT_CS_PARTIAL_FLUSH;
3278 }
3279
3280 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3281 {
3282 struct si_context *sctx = (struct si_context *)ctx;
3283
3284 /* Subsequent commands must wait for all shader invocations to
3285 * complete. */
3286 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3287 SI_CONTEXT_CS_PARTIAL_FLUSH;
3288
3289 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3290 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3291 SI_CONTEXT_INV_VMEM_L1;
3292
3293 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3294 PIPE_BARRIER_SHADER_BUFFER |
3295 PIPE_BARRIER_TEXTURE |
3296 PIPE_BARRIER_IMAGE |
3297 PIPE_BARRIER_STREAMOUT_BUFFER |
3298 PIPE_BARRIER_GLOBAL_BUFFER)) {
3299 /* As far as I can tell, L1 contents are written back to L2
3300 * automatically at end of shader, but the contents of other
3301 * L1 caches might still be stale. */
3302 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3303 }
3304
3305 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3306 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3307
3308 /* Indices are read through TC L2 since VI. */
3309 if (sctx->screen->b.chip_class <= CIK)
3310 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3311 }
3312
3313 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3314 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3315
3316 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3317 PIPE_BARRIER_FRAMEBUFFER |
3318 PIPE_BARRIER_INDIRECT_BUFFER)) {
3319 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3320 *
3321 * We need to make sure that TC L1 & L2 are written back to
3322 * memory, because neither CPU accesses nor CB fetches consider
3323 * TC, but there's no need to invalidate any TC cache lines. */
3324 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3325 }
3326 }
3327
3328 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3329 {
3330 struct pipe_blend_state blend;
3331
3332 memset(&blend, 0, sizeof(blend));
3333 blend.independent_blend_enable = true;
3334 blend.rt[0].colormask = 0xf;
3335 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3336 }
3337
3338 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3339 bool include_draw_vbo)
3340 {
3341 si_need_cs_space((struct si_context*)ctx);
3342 }
3343
3344 static void si_init_config(struct si_context *sctx);
3345
3346 void si_init_state_functions(struct si_context *sctx)
3347 {
3348 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3349 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3350 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3351 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3352 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3353
3354 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3355 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3356 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3357 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3358 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3359 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3360 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3361 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3362 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3363 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3364 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3365
3366 sctx->b.b.create_blend_state = si_create_blend_state;
3367 sctx->b.b.bind_blend_state = si_bind_blend_state;
3368 sctx->b.b.delete_blend_state = si_delete_blend_state;
3369 sctx->b.b.set_blend_color = si_set_blend_color;
3370
3371 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3372 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3373 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3374
3375 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3376 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3377 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3378
3379 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3380 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3381 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3382 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3383 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3384
3385 sctx->b.b.set_clip_state = si_set_clip_state;
3386 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3387
3388 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3389 sctx->b.b.get_sample_position = cayman_get_sample_position;
3390
3391 sctx->b.b.create_sampler_state = si_create_sampler_state;
3392 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3393
3394 sctx->b.b.create_sampler_view = si_create_sampler_view;
3395 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3396
3397 sctx->b.b.set_sample_mask = si_set_sample_mask;
3398
3399 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3400 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3401 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3402 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3403 sctx->b.b.set_index_buffer = si_set_index_buffer;
3404
3405 sctx->b.b.texture_barrier = si_texture_barrier;
3406 sctx->b.b.memory_barrier = si_memory_barrier;
3407 sctx->b.b.set_min_samples = si_set_min_samples;
3408 sctx->b.b.set_tess_state = si_set_tess_state;
3409
3410 sctx->b.b.set_active_query_state = si_set_active_query_state;
3411 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3412 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3413
3414 sctx->b.b.draw_vbo = si_draw_vbo;
3415
3416 si_init_config(sctx);
3417 }
3418
3419 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3420 {
3421 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3422 }
3423
3424 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3425 struct r600_texture *rtex,
3426 struct radeon_bo_metadata *md)
3427 {
3428 struct si_screen *sscreen = (struct si_screen*)rscreen;
3429 struct pipe_resource *res = &rtex->resource.b.b;
3430 static const unsigned char swizzle[] = {
3431 PIPE_SWIZZLE_X,
3432 PIPE_SWIZZLE_Y,
3433 PIPE_SWIZZLE_Z,
3434 PIPE_SWIZZLE_W
3435 };
3436 uint32_t desc[8], i;
3437 bool is_array = util_resource_is_array_texture(res);
3438
3439 /* DRM 2.x.x doesn't support this. */
3440 if (rscreen->info.drm_major != 3)
3441 return;
3442
3443 assert(rtex->fmask.size == 0);
3444
3445 /* Metadata image format format version 1:
3446 * [0] = 1 (metadata format identifier)
3447 * [1] = (VENDOR_ID << 16) | PCI_ID
3448 * [2:9] = image descriptor for the whole resource
3449 * [2] is always 0, because the base address is cleared
3450 * [9] is the DCC offset bits [39:8] from the beginning of
3451 * the buffer
3452 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3453 */
3454
3455 md->metadata[0] = 1; /* metadata image format version 1 */
3456
3457 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3458 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3459
3460 si_make_texture_descriptor(sscreen, rtex, true,
3461 res->target, res->format,
3462 swizzle, 0, res->last_level, 0,
3463 is_array ? res->array_size - 1 : 0,
3464 res->width0, res->height0, res->depth0,
3465 desc, NULL);
3466
3467 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3468 rtex->surface.blk_w, false, desc);
3469
3470 /* Clear the base address and set the relative DCC offset. */
3471 desc[0] = 0;
3472 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3473 desc[7] = rtex->dcc_offset >> 8;
3474
3475 /* Dwords [2:9] contain the image descriptor. */
3476 memcpy(&md->metadata[2], desc, sizeof(desc));
3477
3478 /* Dwords [10:..] contain the mipmap level offsets. */
3479 for (i = 0; i <= res->last_level; i++)
3480 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3481
3482 md->size_metadata = (11 + res->last_level) * 4;
3483 }
3484
3485 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3486 struct r600_texture *rtex,
3487 struct radeon_bo_metadata *md)
3488 {
3489 uint32_t *desc = &md->metadata[2];
3490
3491 if (rscreen->chip_class < VI)
3492 return;
3493
3494 /* Return if DCC is enabled. The texture should be set up with it
3495 * already.
3496 */
3497 if (md->size_metadata >= 11 * 4 &&
3498 md->metadata[0] != 0 &&
3499 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3500 G_008F28_COMPRESSION_EN(desc[6])) {
3501 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3502 return;
3503 }
3504
3505 /* Disable DCC. These are always set by texture_from_handle and must
3506 * be cleared here.
3507 */
3508 rtex->dcc_offset = 0;
3509 }
3510
3511 void si_init_screen_state_functions(struct si_screen *sscreen)
3512 {
3513 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3514 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3515 }
3516
3517 static void
3518 si_write_harvested_raster_configs(struct si_context *sctx,
3519 struct si_pm4_state *pm4,
3520 unsigned raster_config,
3521 unsigned raster_config_1)
3522 {
3523 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3524 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3525 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3526 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3527 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3528 unsigned rb_per_se = num_rb / num_se;
3529 unsigned se_mask[4];
3530 unsigned se;
3531
3532 se_mask[0] = ((1 << rb_per_se) - 1);
3533 se_mask[1] = (se_mask[0] << rb_per_se);
3534 se_mask[2] = (se_mask[1] << rb_per_se);
3535 se_mask[3] = (se_mask[2] << rb_per_se);
3536
3537 se_mask[0] &= rb_mask;
3538 se_mask[1] &= rb_mask;
3539 se_mask[2] &= rb_mask;
3540 se_mask[3] &= rb_mask;
3541
3542 assert(num_se == 1 || num_se == 2 || num_se == 4);
3543 assert(sh_per_se == 1 || sh_per_se == 2);
3544 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3545
3546 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3547 * fields are for, so I'm leaving them as their default
3548 * values. */
3549
3550 for (se = 0; se < num_se; se++) {
3551 unsigned raster_config_se = raster_config;
3552 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3553 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3554 int idx = (se / 2) * 2;
3555
3556 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3557 raster_config_se &= C_028350_SE_MAP;
3558
3559 if (!se_mask[idx]) {
3560 raster_config_se |=
3561 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3562 } else {
3563 raster_config_se |=
3564 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3565 }
3566 }
3567
3568 pkr0_mask &= rb_mask;
3569 pkr1_mask &= rb_mask;
3570 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3571 raster_config_se &= C_028350_PKR_MAP;
3572
3573 if (!pkr0_mask) {
3574 raster_config_se |=
3575 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3576 } else {
3577 raster_config_se |=
3578 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3579 }
3580 }
3581
3582 if (rb_per_se >= 2) {
3583 unsigned rb0_mask = 1 << (se * rb_per_se);
3584 unsigned rb1_mask = rb0_mask << 1;
3585
3586 rb0_mask &= rb_mask;
3587 rb1_mask &= rb_mask;
3588 if (!rb0_mask || !rb1_mask) {
3589 raster_config_se &= C_028350_RB_MAP_PKR0;
3590
3591 if (!rb0_mask) {
3592 raster_config_se |=
3593 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3594 } else {
3595 raster_config_se |=
3596 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3597 }
3598 }
3599
3600 if (rb_per_se > 2) {
3601 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3602 rb1_mask = rb0_mask << 1;
3603 rb0_mask &= rb_mask;
3604 rb1_mask &= rb_mask;
3605 if (!rb0_mask || !rb1_mask) {
3606 raster_config_se &= C_028350_RB_MAP_PKR1;
3607
3608 if (!rb0_mask) {
3609 raster_config_se |=
3610 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3611 } else {
3612 raster_config_se |=
3613 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3614 }
3615 }
3616 }
3617 }
3618
3619 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3620 if (sctx->b.chip_class < CIK)
3621 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3622 SE_INDEX(se) | SH_BROADCAST_WRITES |
3623 INSTANCE_BROADCAST_WRITES);
3624 else
3625 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3626 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3627 S_030800_INSTANCE_BROADCAST_WRITES(1));
3628 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3629 }
3630
3631 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3632 if (sctx->b.chip_class < CIK)
3633 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3634 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3635 INSTANCE_BROADCAST_WRITES);
3636 else {
3637 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3638 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3639 S_030800_INSTANCE_BROADCAST_WRITES(1));
3640
3641 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3642 (!se_mask[2] && !se_mask[3]))) {
3643 raster_config_1 &= C_028354_SE_PAIR_MAP;
3644
3645 if (!se_mask[0] && !se_mask[1]) {
3646 raster_config_1 |=
3647 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3648 } else {
3649 raster_config_1 |=
3650 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3651 }
3652 }
3653
3654 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3655 }
3656 }
3657
3658 static void si_init_config(struct si_context *sctx)
3659 {
3660 struct si_screen *sscreen = sctx->screen;
3661 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3662 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3663 unsigned raster_config, raster_config_1;
3664 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3665 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3666 int i;
3667
3668 if (!pm4)
3669 return;
3670
3671 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3672 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3673 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3674 si_pm4_cmd_end(pm4, false);
3675
3676 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3677 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3678
3679 /* FIXME calculate these values somehow ??? */
3680 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3681 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3682 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3683
3684 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3685 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3686
3687 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3688 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3689 if (sctx->b.chip_class < CIK)
3690 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3691 S_008A14_CLIP_VTX_REORDER_ENA(1));
3692
3693 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3694 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3695
3696 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3697
3698 for (i = 0; i < 16; i++) {
3699 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3700 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3701 }
3702
3703 switch (sctx->screen->b.family) {
3704 case CHIP_TAHITI:
3705 case CHIP_PITCAIRN:
3706 raster_config = 0x2a00126a;
3707 raster_config_1 = 0x00000000;
3708 break;
3709 case CHIP_VERDE:
3710 raster_config = 0x0000124a;
3711 raster_config_1 = 0x00000000;
3712 break;
3713 case CHIP_OLAND:
3714 raster_config = 0x00000082;
3715 raster_config_1 = 0x00000000;
3716 break;
3717 case CHIP_HAINAN:
3718 raster_config = 0x00000000;
3719 raster_config_1 = 0x00000000;
3720 break;
3721 case CHIP_BONAIRE:
3722 raster_config = 0x16000012;
3723 raster_config_1 = 0x00000000;
3724 break;
3725 case CHIP_HAWAII:
3726 raster_config = 0x3a00161a;
3727 raster_config_1 = 0x0000002e;
3728 break;
3729 case CHIP_FIJI:
3730 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3731 /* old kernels with old tiling config */
3732 raster_config = 0x16000012;
3733 raster_config_1 = 0x0000002a;
3734 } else {
3735 raster_config = 0x3a00161a;
3736 raster_config_1 = 0x0000002e;
3737 }
3738 break;
3739 case CHIP_POLARIS10:
3740 raster_config = 0x16000012;
3741 raster_config_1 = 0x0000002a;
3742 break;
3743 case CHIP_POLARIS11:
3744 raster_config = 0x16000012;
3745 raster_config_1 = 0x00000000;
3746 break;
3747 case CHIP_TONGA:
3748 raster_config = 0x16000012;
3749 raster_config_1 = 0x0000002a;
3750 break;
3751 case CHIP_ICELAND:
3752 if (num_rb == 1)
3753 raster_config = 0x00000000;
3754 else
3755 raster_config = 0x00000002;
3756 raster_config_1 = 0x00000000;
3757 break;
3758 case CHIP_CARRIZO:
3759 raster_config = 0x00000002;
3760 raster_config_1 = 0x00000000;
3761 break;
3762 case CHIP_KAVERI:
3763 /* KV should be 0x00000002, but that causes problems with radeon */
3764 raster_config = 0x00000000; /* 0x00000002 */
3765 raster_config_1 = 0x00000000;
3766 break;
3767 case CHIP_KABINI:
3768 case CHIP_MULLINS:
3769 case CHIP_STONEY:
3770 raster_config = 0x00000000;
3771 raster_config_1 = 0x00000000;
3772 break;
3773 default:
3774 fprintf(stderr,
3775 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3776 raster_config = 0x00000000;
3777 raster_config_1 = 0x00000000;
3778 break;
3779 }
3780
3781 /* Always use the default config when all backends are enabled
3782 * (or when we failed to determine the enabled backends).
3783 */
3784 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3785 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3786 raster_config);
3787 if (sctx->b.chip_class >= CIK)
3788 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3789 raster_config_1);
3790 } else {
3791 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3792 }
3793
3794 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3795 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3796 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3797 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3798 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3799 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3800 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3801
3802 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3803 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3804 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3805 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3806 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3807 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3808 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3809 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3810 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3811 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3812 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3813
3814 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3815 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3816 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3817
3818 if (sctx->b.chip_class >= CIK) {
3819 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3820 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3821 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3822
3823 if (sscreen->b.info.num_good_compute_units /
3824 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3825 /* Too few available compute units per SH. Disallowing
3826 * VS to run on CU0 could hurt us more than late VS
3827 * allocation would help.
3828 *
3829 * LATE_ALLOC_VS = 2 is the highest safe number.
3830 */
3831 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3832 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3833 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3834 } else {
3835 /* Set LATE_ALLOC_VS == 31. It should be less than
3836 * the number of scratch waves. Limitations:
3837 * - VS can't execute on CU0.
3838 * - If HS writes outputs to LDS, LS can't execute on CU0.
3839 */
3840 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3841 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3842 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3843 }
3844
3845 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3846 }
3847
3848 if (sctx->b.chip_class >= VI) {
3849 unsigned vgt_tess_distribution;
3850
3851 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3852 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3853 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3854 if (sctx->b.family < CHIP_POLARIS10)
3855 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3856 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3857
3858 vgt_tess_distribution =
3859 S_028B50_ACCUM_ISOLINE(32) |
3860 S_028B50_ACCUM_TRI(11) |
3861 S_028B50_ACCUM_QUAD(11) |
3862 S_028B50_DONUT_SPLIT(16);
3863
3864 /* Testing with Unigine Heaven extreme tesselation yielded best results
3865 * with TRAP_SPLIT = 3.
3866 */
3867 if (sctx->b.family == CHIP_FIJI ||
3868 sctx->b.family >= CHIP_POLARIS10)
3869 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3870
3871 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3872 } else {
3873 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3874 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3875 }
3876
3877 if (sctx->b.family == CHIP_STONEY)
3878 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3879
3880 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3881 if (sctx->b.chip_class >= CIK)
3882 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3883 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3884 RADEON_PRIO_BORDER_COLORS);
3885
3886 si_pm4_upload_indirect_buffer(sctx, pm4);
3887 sctx->init_config = pm4;
3888 }