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radeonsi: extract the texture descriptor computation into its own function
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.info.r600_num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.num_render_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
242 * is that:
243 * - The blend state mask is 0xf most of the time.
244 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
245 * so COLOR1 is enabled pretty much all the time.
246 * So CB_TARGET_MASK is the only register that can disable COLOR1.
247 *
248 * Another reason is to avoid a hang with dual source blending.
249 */
250 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
251 {
252 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
253 struct si_state_blend *blend = sctx->queued.named.blend;
254 uint32_t cb_target_mask = 0, i;
255
256 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
257 if (sctx->framebuffer.state.cbufs[i])
258 cb_target_mask |= 0xf << (4*i);
259
260 if (blend)
261 cb_target_mask &= blend->cb_target_mask;
262
263 /* Avoid a hang that happens when dual source blending is enabled
264 * but there is not enough color outputs. This is undefined behavior,
265 * so disable color writes completely.
266 *
267 * Reproducible with Unigine Heaven 4.0 and drirc missing.
268 */
269 if (blend && blend->dual_src_blend &&
270 sctx->ps_shader.cso &&
271 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
272 cb_target_mask = 0;
273
274 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
275
276 /* STONEY-specific register settings. */
277 if (sctx->b.family == CHIP_STONEY) {
278 unsigned spi_shader_col_format =
279 sctx->ps_shader.cso ?
280 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
281 unsigned sx_ps_downconvert = 0;
282 unsigned sx_blend_opt_epsilon = 0;
283 unsigned sx_blend_opt_control = 0;
284
285 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
286 struct r600_surface *surf =
287 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
288 unsigned format, swap, spi_format, colormask;
289 bool has_alpha, has_rgb;
290
291 if (!surf)
292 continue;
293
294 format = G_028C70_FORMAT(surf->cb_color_info);
295 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
296 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
297 colormask = (cb_target_mask >> (i * 4)) & 0xf;
298
299 /* Set if RGB and A are present. */
300 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
301
302 if (format == V_028C70_COLOR_8 ||
303 format == V_028C70_COLOR_16 ||
304 format == V_028C70_COLOR_32)
305 has_rgb = !has_alpha;
306 else
307 has_rgb = true;
308
309 /* Check the colormask and export format. */
310 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
311 has_rgb = false;
312 if (!(colormask & PIPE_MASK_A))
313 has_alpha = false;
314
315 if (spi_format == V_028714_SPI_SHADER_ZERO) {
316 has_rgb = false;
317 has_alpha = false;
318 }
319
320 /* Disable value checking for disabled channels. */
321 if (!has_rgb)
322 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
323 if (!has_alpha)
324 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
325
326 /* Enable down-conversion for 32bpp and smaller formats. */
327 switch (format) {
328 case V_028C70_COLOR_8:
329 case V_028C70_COLOR_8_8:
330 case V_028C70_COLOR_8_8_8_8:
331 /* For 1 and 2-channel formats, use the superset thereof. */
332 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
333 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
335 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
336 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
337 }
338 break;
339
340 case V_028C70_COLOR_5_6_5:
341 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
342 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
343 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
344 }
345 break;
346
347 case V_028C70_COLOR_1_5_5_5:
348 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
349 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
350 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
351 }
352 break;
353
354 case V_028C70_COLOR_4_4_4_4:
355 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
356 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
357 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
358 }
359 break;
360
361 case V_028C70_COLOR_32:
362 if (swap == V_0280A0_SWAP_STD &&
363 spi_format == V_028714_SPI_SHADER_32_R)
364 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
365 else if (swap == V_0280A0_SWAP_ALT_REV &&
366 spi_format == V_028714_SPI_SHADER_32_AR)
367 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
368 break;
369
370 case V_028C70_COLOR_16:
371 case V_028C70_COLOR_16_16:
372 /* For 1-channel formats, use the superset thereof. */
373 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
374 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
377 if (swap == V_0280A0_SWAP_STD ||
378 swap == V_0280A0_SWAP_STD_REV)
379 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
380 else
381 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
382 }
383 break;
384
385 case V_028C70_COLOR_10_11_11:
386 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
387 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
388 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
389 }
390 break;
391
392 case V_028C70_COLOR_2_10_10_10:
393 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
394 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
395 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
396 }
397 break;
398 }
399 }
400
401 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
402 sx_ps_downconvert = 0;
403 sx_blend_opt_epsilon = 0;
404 sx_blend_opt_control = 0;
405 }
406
407 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
408 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
409 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
410 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
411 }
412 }
413
414 /*
415 * Blender functions
416 */
417
418 static uint32_t si_translate_blend_function(int blend_func)
419 {
420 switch (blend_func) {
421 case PIPE_BLEND_ADD:
422 return V_028780_COMB_DST_PLUS_SRC;
423 case PIPE_BLEND_SUBTRACT:
424 return V_028780_COMB_SRC_MINUS_DST;
425 case PIPE_BLEND_REVERSE_SUBTRACT:
426 return V_028780_COMB_DST_MINUS_SRC;
427 case PIPE_BLEND_MIN:
428 return V_028780_COMB_MIN_DST_SRC;
429 case PIPE_BLEND_MAX:
430 return V_028780_COMB_MAX_DST_SRC;
431 default:
432 R600_ERR("Unknown blend function %d\n", blend_func);
433 assert(0);
434 break;
435 }
436 return 0;
437 }
438
439 static uint32_t si_translate_blend_factor(int blend_fact)
440 {
441 switch (blend_fact) {
442 case PIPE_BLENDFACTOR_ONE:
443 return V_028780_BLEND_ONE;
444 case PIPE_BLENDFACTOR_SRC_COLOR:
445 return V_028780_BLEND_SRC_COLOR;
446 case PIPE_BLENDFACTOR_SRC_ALPHA:
447 return V_028780_BLEND_SRC_ALPHA;
448 case PIPE_BLENDFACTOR_DST_ALPHA:
449 return V_028780_BLEND_DST_ALPHA;
450 case PIPE_BLENDFACTOR_DST_COLOR:
451 return V_028780_BLEND_DST_COLOR;
452 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
453 return V_028780_BLEND_SRC_ALPHA_SATURATE;
454 case PIPE_BLENDFACTOR_CONST_COLOR:
455 return V_028780_BLEND_CONSTANT_COLOR;
456 case PIPE_BLENDFACTOR_CONST_ALPHA:
457 return V_028780_BLEND_CONSTANT_ALPHA;
458 case PIPE_BLENDFACTOR_ZERO:
459 return V_028780_BLEND_ZERO;
460 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
461 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
462 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
463 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
464 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
465 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
466 case PIPE_BLENDFACTOR_INV_DST_COLOR:
467 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
468 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
469 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
470 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
471 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
472 case PIPE_BLENDFACTOR_SRC1_COLOR:
473 return V_028780_BLEND_SRC1_COLOR;
474 case PIPE_BLENDFACTOR_SRC1_ALPHA:
475 return V_028780_BLEND_SRC1_ALPHA;
476 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
477 return V_028780_BLEND_INV_SRC1_COLOR;
478 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
479 return V_028780_BLEND_INV_SRC1_ALPHA;
480 default:
481 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
482 assert(0);
483 break;
484 }
485 return 0;
486 }
487
488 static uint32_t si_translate_blend_opt_function(int blend_func)
489 {
490 switch (blend_func) {
491 case PIPE_BLEND_ADD:
492 return V_028760_OPT_COMB_ADD;
493 case PIPE_BLEND_SUBTRACT:
494 return V_028760_OPT_COMB_SUBTRACT;
495 case PIPE_BLEND_REVERSE_SUBTRACT:
496 return V_028760_OPT_COMB_REVSUBTRACT;
497 case PIPE_BLEND_MIN:
498 return V_028760_OPT_COMB_MIN;
499 case PIPE_BLEND_MAX:
500 return V_028760_OPT_COMB_MAX;
501 default:
502 return V_028760_OPT_COMB_BLEND_DISABLED;
503 }
504 }
505
506 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
507 {
508 switch (blend_fact) {
509 case PIPE_BLENDFACTOR_ZERO:
510 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
511 case PIPE_BLENDFACTOR_ONE:
512 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
513 case PIPE_BLENDFACTOR_SRC_COLOR:
514 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
515 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
516 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
517 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
518 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
519 case PIPE_BLENDFACTOR_SRC_ALPHA:
520 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
521 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
522 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
523 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
524 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
525 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
526 default:
527 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
528 }
529 }
530
531 /**
532 * Get rid of DST in the blend factors by commuting the operands:
533 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
534 */
535 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
536 unsigned *dst_factor, unsigned expected_dst,
537 unsigned replacement_src)
538 {
539 if (*src_factor == expected_dst &&
540 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
541 *src_factor = PIPE_BLENDFACTOR_ZERO;
542 *dst_factor = replacement_src;
543
544 /* Commuting the operands requires reversing subtractions. */
545 if (*func == PIPE_BLEND_SUBTRACT)
546 *func = PIPE_BLEND_REVERSE_SUBTRACT;
547 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
548 *func = PIPE_BLEND_SUBTRACT;
549 }
550 }
551
552 static bool si_blend_factor_uses_dst(unsigned factor)
553 {
554 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
555 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
556 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
557 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
558 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
559 }
560
561 static void *si_create_blend_state_mode(struct pipe_context *ctx,
562 const struct pipe_blend_state *state,
563 unsigned mode)
564 {
565 struct si_context *sctx = (struct si_context*)ctx;
566 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
567 struct si_pm4_state *pm4 = &blend->pm4;
568 uint32_t sx_mrt_blend_opt[8] = {0};
569 uint32_t color_control = 0;
570
571 if (!blend)
572 return NULL;
573
574 blend->alpha_to_coverage = state->alpha_to_coverage;
575 blend->alpha_to_one = state->alpha_to_one;
576 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
577
578 if (state->logicop_enable) {
579 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
580 } else {
581 color_control |= S_028808_ROP3(0xcc);
582 }
583
584 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
585 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
586 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
587 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
590
591 if (state->alpha_to_coverage)
592 blend->need_src_alpha_4bit |= 0xf;
593
594 blend->cb_target_mask = 0;
595 for (int i = 0; i < 8; i++) {
596 /* state->rt entries > 0 only written if independent blending */
597 const int j = state->independent_blend_enable ? i : 0;
598
599 unsigned eqRGB = state->rt[j].rgb_func;
600 unsigned srcRGB = state->rt[j].rgb_src_factor;
601 unsigned dstRGB = state->rt[j].rgb_dst_factor;
602 unsigned eqA = state->rt[j].alpha_func;
603 unsigned srcA = state->rt[j].alpha_src_factor;
604 unsigned dstA = state->rt[j].alpha_dst_factor;
605
606 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
607 unsigned blend_cntl = 0;
608
609 sx_mrt_blend_opt[i] =
610 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
611 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
612
613 if (!state->rt[j].colormask)
614 continue;
615
616 /* cb_render_state will disable unused ones */
617 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
618
619 if (!state->rt[j].blend_enable) {
620 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
621 continue;
622 }
623
624 /* Blending optimizations for Stoney.
625 * These transformations don't change the behavior.
626 *
627 * First, get rid of DST in the blend factors:
628 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
629 */
630 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
631 PIPE_BLENDFACTOR_DST_COLOR,
632 PIPE_BLENDFACTOR_SRC_COLOR);
633 si_blend_remove_dst(&eqA, &srcA, &dstA,
634 PIPE_BLENDFACTOR_DST_COLOR,
635 PIPE_BLENDFACTOR_SRC_COLOR);
636 si_blend_remove_dst(&eqA, &srcA, &dstA,
637 PIPE_BLENDFACTOR_DST_ALPHA,
638 PIPE_BLENDFACTOR_SRC_ALPHA);
639
640 /* Look up the ideal settings from tables. */
641 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
642 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
643 srcA_opt = si_translate_blend_opt_factor(srcA, true);
644 dstA_opt = si_translate_blend_opt_factor(dstA, true);
645
646 /* Handle interdependencies. */
647 if (si_blend_factor_uses_dst(srcRGB))
648 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
649 if (si_blend_factor_uses_dst(srcA))
650 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
651
652 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
653 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
654 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
656 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
657
658 /* Set the final value. */
659 sx_mrt_blend_opt[i] =
660 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
661 S_028760_COLOR_DST_OPT(dstRGB_opt) |
662 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
663 S_028760_ALPHA_SRC_OPT(srcA_opt) |
664 S_028760_ALPHA_DST_OPT(dstA_opt) |
665 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
666
667 /* Set blend state. */
668 blend_cntl |= S_028780_ENABLE(1);
669 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
670 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
671 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
672
673 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
674 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
675 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
676 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
677 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
678 }
679 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
680
681 blend->blend_enable_4bit |= 0xf << (i * 4);
682
683 /* This is only important for formats without alpha. */
684 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
685 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
687 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
689 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
690 blend->need_src_alpha_4bit |= 0xf << (i * 4);
691 }
692
693 if (blend->cb_target_mask) {
694 color_control |= S_028808_MODE(mode);
695 } else {
696 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
697 }
698
699 if (sctx->b.family == CHIP_STONEY) {
700 for (int i = 0; i < 8; i++)
701 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
702 sx_mrt_blend_opt[i]);
703
704 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
705 if (blend->dual_src_blend || state->logicop_enable ||
706 mode == V_028808_CB_RESOLVE)
707 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
708 }
709
710 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
711 return blend;
712 }
713
714 static void *si_create_blend_state(struct pipe_context *ctx,
715 const struct pipe_blend_state *state)
716 {
717 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
718 }
719
720 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
721 {
722 struct si_context *sctx = (struct si_context *)ctx;
723 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
724 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
725 }
726
727 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
728 {
729 struct si_context *sctx = (struct si_context *)ctx;
730 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
731 }
732
733 static void si_set_blend_color(struct pipe_context *ctx,
734 const struct pipe_blend_color *state)
735 {
736 struct si_context *sctx = (struct si_context *)ctx;
737
738 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
739 return;
740
741 sctx->blend_color.state = *state;
742 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
743 }
744
745 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
746 {
747 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
748
749 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
750 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
751 }
752
753 /*
754 * Clipping, scissors and viewport
755 */
756
757 static void si_set_clip_state(struct pipe_context *ctx,
758 const struct pipe_clip_state *state)
759 {
760 struct si_context *sctx = (struct si_context *)ctx;
761 struct pipe_constant_buffer cb;
762
763 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
764 return;
765
766 sctx->clip_state.state = *state;
767 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
768
769 cb.buffer = NULL;
770 cb.user_buffer = state->ucp;
771 cb.buffer_offset = 0;
772 cb.buffer_size = 4*4*8;
773 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
774 pipe_resource_reference(&cb.buffer, NULL);
775 }
776
777 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
778 {
779 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
780
781 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
782 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
783 }
784
785 #define SIX_BITS 0x3F
786
787 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
788 {
789 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
790 struct tgsi_shader_info *info = si_get_vs_info(sctx);
791 unsigned window_space =
792 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
793 unsigned clipdist_mask =
794 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
795
796 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
797 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
798 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
799 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
800 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
801 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
802 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
803 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
804 info->writes_edgeflag ||
805 info->writes_layer ||
806 info->writes_viewport_index) |
807 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
808 (sctx->queued.named.rasterizer->clip_plane_enable &
809 clipdist_mask));
810 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
811 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
812 (clipdist_mask ? 0 :
813 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
814 S_028810_CLIP_DISABLE(window_space));
815
816 /* reuse needs to be set off if we write oViewport */
817 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
818 S_028AB4_REUSE_OFF(info->writes_viewport_index));
819 }
820
821 static void si_set_scissor_states(struct pipe_context *ctx,
822 unsigned start_slot,
823 unsigned num_scissors,
824 const struct pipe_scissor_state *state)
825 {
826 struct si_context *sctx = (struct si_context *)ctx;
827 int i;
828
829 for (i = 0; i < num_scissors; i++)
830 sctx->scissors.states[start_slot + i] = state[i];
831
832 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
833 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
834 }
835
836 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
837 {
838 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
839 struct pipe_scissor_state *states = sctx->scissors.states;
840 unsigned mask = sctx->scissors.dirty_mask;
841
842 /* The simple case: Only 1 viewport is active. */
843 if (mask & 1 &&
844 !si_get_vs_info(sctx)->writes_viewport_index) {
845 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
846 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
847 S_028250_TL_Y(states[0].miny) |
848 S_028250_WINDOW_OFFSET_DISABLE(1));
849 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
850 S_028254_BR_Y(states[0].maxy));
851 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
852 return;
853 }
854
855 while (mask) {
856 int start, count, i;
857
858 u_bit_scan_consecutive_range(&mask, &start, &count);
859
860 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
861 start * 4 * 2, count * 2);
862 for (i = start; i < start+count; i++) {
863 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
864 S_028250_TL_Y(states[i].miny) |
865 S_028250_WINDOW_OFFSET_DISABLE(1));
866 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
867 S_028254_BR_Y(states[i].maxy));
868 }
869 }
870 sctx->scissors.dirty_mask = 0;
871 }
872
873 static void si_set_viewport_states(struct pipe_context *ctx,
874 unsigned start_slot,
875 unsigned num_viewports,
876 const struct pipe_viewport_state *state)
877 {
878 struct si_context *sctx = (struct si_context *)ctx;
879 int i;
880
881 for (i = 0; i < num_viewports; i++)
882 sctx->viewports.states[start_slot + i] = state[i];
883
884 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
885 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
886 }
887
888 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
889 {
890 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
891 struct pipe_viewport_state *states = sctx->viewports.states;
892 unsigned mask = sctx->viewports.dirty_mask;
893
894 /* The simple case: Only 1 viewport is active. */
895 if (mask & 1 &&
896 !si_get_vs_info(sctx)->writes_viewport_index) {
897 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
898 radeon_emit(cs, fui(states[0].scale[0]));
899 radeon_emit(cs, fui(states[0].translate[0]));
900 radeon_emit(cs, fui(states[0].scale[1]));
901 radeon_emit(cs, fui(states[0].translate[1]));
902 radeon_emit(cs, fui(states[0].scale[2]));
903 radeon_emit(cs, fui(states[0].translate[2]));
904 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
905 return;
906 }
907
908 while (mask) {
909 int start, count, i;
910
911 u_bit_scan_consecutive_range(&mask, &start, &count);
912
913 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
914 start * 4 * 6, count * 6);
915 for (i = start; i < start+count; i++) {
916 radeon_emit(cs, fui(states[i].scale[0]));
917 radeon_emit(cs, fui(states[i].translate[0]));
918 radeon_emit(cs, fui(states[i].scale[1]));
919 radeon_emit(cs, fui(states[i].translate[1]));
920 radeon_emit(cs, fui(states[i].scale[2]));
921 radeon_emit(cs, fui(states[i].translate[2]));
922 }
923 }
924 sctx->viewports.dirty_mask = 0;
925 }
926
927 /*
928 * inferred state between framebuffer and rasterizer
929 */
930 static void si_update_poly_offset_state(struct si_context *sctx)
931 {
932 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
933
934 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
935 return;
936
937 switch (sctx->framebuffer.state.zsbuf->texture->format) {
938 case PIPE_FORMAT_Z16_UNORM:
939 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
940 break;
941 default: /* 24-bit */
942 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
943 break;
944 case PIPE_FORMAT_Z32_FLOAT:
945 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
946 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
947 break;
948 }
949 }
950
951 /*
952 * Rasterizer
953 */
954
955 static uint32_t si_translate_fill(uint32_t func)
956 {
957 switch(func) {
958 case PIPE_POLYGON_MODE_FILL:
959 return V_028814_X_DRAW_TRIANGLES;
960 case PIPE_POLYGON_MODE_LINE:
961 return V_028814_X_DRAW_LINES;
962 case PIPE_POLYGON_MODE_POINT:
963 return V_028814_X_DRAW_POINTS;
964 default:
965 assert(0);
966 return V_028814_X_DRAW_POINTS;
967 }
968 }
969
970 static void *si_create_rs_state(struct pipe_context *ctx,
971 const struct pipe_rasterizer_state *state)
972 {
973 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
974 struct si_pm4_state *pm4 = &rs->pm4;
975 unsigned tmp, i;
976 float psize_min, psize_max;
977
978 if (!rs) {
979 return NULL;
980 }
981
982 rs->two_side = state->light_twoside;
983 rs->multisample_enable = state->multisample;
984 rs->force_persample_interp = state->force_persample_interp;
985 rs->clip_plane_enable = state->clip_plane_enable;
986 rs->line_stipple_enable = state->line_stipple_enable;
987 rs->poly_stipple_enable = state->poly_stipple_enable;
988 rs->line_smooth = state->line_smooth;
989 rs->poly_smooth = state->poly_smooth;
990 rs->uses_poly_offset = state->offset_point || state->offset_line ||
991 state->offset_tri;
992 rs->clamp_fragment_color = state->clamp_fragment_color;
993 rs->flatshade = state->flatshade;
994 rs->sprite_coord_enable = state->sprite_coord_enable;
995 rs->rasterizer_discard = state->rasterizer_discard;
996 rs->pa_sc_line_stipple = state->line_stipple_enable ?
997 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
998 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
999 rs->pa_cl_clip_cntl =
1000 S_028810_PS_UCP_MODE(3) |
1001 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1002 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1003 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1004 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1005 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1006
1007 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
1008 S_0286D4_FLAT_SHADE_ENA(1) |
1009 S_0286D4_PNT_SPRITE_ENA(1) |
1010 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1011 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1012 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1013 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1014 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1015
1016 /* point size 12.4 fixed point */
1017 tmp = (unsigned)(state->point_size * 8.0);
1018 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1019
1020 if (state->point_size_per_vertex) {
1021 psize_min = util_get_min_point_size(state);
1022 psize_max = 8192;
1023 } else {
1024 /* Force the point size to be as if the vertex output was disabled. */
1025 psize_min = state->point_size;
1026 psize_max = state->point_size;
1027 }
1028 /* Divide by two, because 0.5 = 1 pixel. */
1029 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1030 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
1031 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
1032
1033 tmp = (unsigned)state->line_width * 8;
1034 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
1035 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
1036 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1037 S_028A48_MSAA_ENABLE(state->multisample ||
1038 state->poly_smooth ||
1039 state->line_smooth) |
1040 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
1041
1042 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
1043 S_028BE4_PIX_CENTER(state->half_pixel_center) |
1044 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
1045
1046 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1047 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1048 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1049 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1050 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1051 S_028814_FACE(!state->front_ccw) |
1052 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1053 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1054 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1055 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
1056 state->fill_back != PIPE_POLYGON_MODE_FILL) |
1057 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1058 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
1059 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
1060 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
1061
1062 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1063 for (i = 0; i < 3; i++) {
1064 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1065 float offset_units = state->offset_units;
1066 float offset_scale = state->offset_scale * 16.0f;
1067
1068 switch (i) {
1069 case 0: /* 16-bit zbuffer */
1070 offset_units *= 4.0f;
1071 break;
1072 case 1: /* 24-bit zbuffer */
1073 offset_units *= 2.0f;
1074 break;
1075 case 2: /* 32-bit zbuffer */
1076 offset_units *= 1.0f;
1077 break;
1078 }
1079
1080 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1081 fui(offset_scale));
1082 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1083 fui(offset_units));
1084 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1085 fui(offset_scale));
1086 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1087 fui(offset_units));
1088 }
1089
1090 return rs;
1091 }
1092
1093 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1094 {
1095 struct si_context *sctx = (struct si_context *)ctx;
1096 struct si_state_rasterizer *old_rs =
1097 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1098 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1099
1100 if (!state)
1101 return;
1102
1103 if (sctx->framebuffer.nr_samples > 1 &&
1104 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1105 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1106
1107 si_pm4_bind_state(sctx, rasterizer, rs);
1108 si_update_poly_offset_state(sctx);
1109
1110 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1111 }
1112
1113 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1114 {
1115 struct si_context *sctx = (struct si_context *)ctx;
1116
1117 if (sctx->queued.named.rasterizer == state)
1118 si_pm4_bind_state(sctx, poly_offset, NULL);
1119 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1120 }
1121
1122 /*
1123 * infeered state between dsa and stencil ref
1124 */
1125 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1126 {
1127 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1128 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1129 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1130
1131 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1132 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1133 S_028430_STENCILMASK(dsa->valuemask[0]) |
1134 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1135 S_028430_STENCILOPVAL(1));
1136 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1137 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1138 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1139 S_028434_STENCILOPVAL_BF(1));
1140 }
1141
1142 static void si_set_stencil_ref(struct pipe_context *ctx,
1143 const struct pipe_stencil_ref *state)
1144 {
1145 struct si_context *sctx = (struct si_context *)ctx;
1146
1147 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1148 return;
1149
1150 sctx->stencil_ref.state = *state;
1151 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1152 }
1153
1154
1155 /*
1156 * DSA
1157 */
1158
1159 static uint32_t si_translate_stencil_op(int s_op)
1160 {
1161 switch (s_op) {
1162 case PIPE_STENCIL_OP_KEEP:
1163 return V_02842C_STENCIL_KEEP;
1164 case PIPE_STENCIL_OP_ZERO:
1165 return V_02842C_STENCIL_ZERO;
1166 case PIPE_STENCIL_OP_REPLACE:
1167 return V_02842C_STENCIL_REPLACE_TEST;
1168 case PIPE_STENCIL_OP_INCR:
1169 return V_02842C_STENCIL_ADD_CLAMP;
1170 case PIPE_STENCIL_OP_DECR:
1171 return V_02842C_STENCIL_SUB_CLAMP;
1172 case PIPE_STENCIL_OP_INCR_WRAP:
1173 return V_02842C_STENCIL_ADD_WRAP;
1174 case PIPE_STENCIL_OP_DECR_WRAP:
1175 return V_02842C_STENCIL_SUB_WRAP;
1176 case PIPE_STENCIL_OP_INVERT:
1177 return V_02842C_STENCIL_INVERT;
1178 default:
1179 R600_ERR("Unknown stencil op %d", s_op);
1180 assert(0);
1181 break;
1182 }
1183 return 0;
1184 }
1185
1186 static void *si_create_dsa_state(struct pipe_context *ctx,
1187 const struct pipe_depth_stencil_alpha_state *state)
1188 {
1189 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1190 struct si_pm4_state *pm4 = &dsa->pm4;
1191 unsigned db_depth_control;
1192 uint32_t db_stencil_control = 0;
1193
1194 if (!dsa) {
1195 return NULL;
1196 }
1197
1198 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1199 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1200 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1201 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1202
1203 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1204 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1205 S_028800_ZFUNC(state->depth.func) |
1206 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1207
1208 /* stencil */
1209 if (state->stencil[0].enabled) {
1210 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1211 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1212 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1213 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1214 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1215
1216 if (state->stencil[1].enabled) {
1217 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1218 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1219 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1220 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1221 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1222 }
1223 }
1224
1225 /* alpha */
1226 if (state->alpha.enabled) {
1227 dsa->alpha_func = state->alpha.func;
1228
1229 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1230 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1231 } else {
1232 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1233 }
1234
1235 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1236 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1237 if (state->depth.bounds_test) {
1238 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1239 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1240 }
1241
1242 return dsa;
1243 }
1244
1245 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1246 {
1247 struct si_context *sctx = (struct si_context *)ctx;
1248 struct si_state_dsa *dsa = state;
1249
1250 if (!state)
1251 return;
1252
1253 si_pm4_bind_state(sctx, dsa, dsa);
1254
1255 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1256 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1257 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1258 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1259 }
1260 }
1261
1262 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1263 {
1264 struct si_context *sctx = (struct si_context *)ctx;
1265 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1266 }
1267
1268 static void *si_create_db_flush_dsa(struct si_context *sctx)
1269 {
1270 struct pipe_depth_stencil_alpha_state dsa = {};
1271
1272 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1273 }
1274
1275 /* DB RENDER STATE */
1276
1277 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1278 {
1279 struct si_context *sctx = (struct si_context*)ctx;
1280
1281 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1282 }
1283
1284 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1285 {
1286 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1287 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1288 unsigned db_shader_control;
1289
1290 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1291
1292 /* DB_RENDER_CONTROL */
1293 if (sctx->dbcb_depth_copy_enabled ||
1294 sctx->dbcb_stencil_copy_enabled) {
1295 radeon_emit(cs,
1296 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1297 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1298 S_028000_COPY_CENTROID(1) |
1299 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1300 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1301 radeon_emit(cs,
1302 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1303 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1304 } else {
1305 radeon_emit(cs,
1306 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1307 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1308 }
1309
1310 /* DB_COUNT_CONTROL (occlusion queries) */
1311 if (sctx->b.num_occlusion_queries > 0) {
1312 if (sctx->b.chip_class >= CIK) {
1313 radeon_emit(cs,
1314 S_028004_PERFECT_ZPASS_COUNTS(1) |
1315 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1316 S_028004_ZPASS_ENABLE(1) |
1317 S_028004_SLICE_EVEN_ENABLE(1) |
1318 S_028004_SLICE_ODD_ENABLE(1));
1319 } else {
1320 radeon_emit(cs,
1321 S_028004_PERFECT_ZPASS_COUNTS(1) |
1322 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1323 }
1324 } else {
1325 /* Disable occlusion queries. */
1326 if (sctx->b.chip_class >= CIK) {
1327 radeon_emit(cs, 0);
1328 } else {
1329 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1330 }
1331 }
1332
1333 /* DB_RENDER_OVERRIDE2 */
1334 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1335 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1336 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1337
1338 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1339 sctx->ps_db_shader_control;
1340
1341 /* Bug workaround for smoothing (overrasterization) on SI. */
1342 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1343 db_shader_control &= C_02880C_Z_ORDER;
1344 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1345 }
1346
1347 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1348 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1349 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1350
1351 if (sctx->b.family == CHIP_STONEY &&
1352 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1353 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1354
1355 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1356 db_shader_control);
1357 }
1358
1359 /*
1360 * format translation
1361 */
1362 static uint32_t si_translate_colorformat(enum pipe_format format)
1363 {
1364 const struct util_format_description *desc = util_format_description(format);
1365
1366 #define HAS_SIZE(x,y,z,w) \
1367 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1368 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1369
1370 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1371 return V_028C70_COLOR_10_11_11;
1372
1373 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1374 return V_028C70_COLOR_INVALID;
1375
1376 switch (desc->nr_channels) {
1377 case 1:
1378 switch (desc->channel[0].size) {
1379 case 8:
1380 return V_028C70_COLOR_8;
1381 case 16:
1382 return V_028C70_COLOR_16;
1383 case 32:
1384 return V_028C70_COLOR_32;
1385 }
1386 break;
1387 case 2:
1388 if (desc->channel[0].size == desc->channel[1].size) {
1389 switch (desc->channel[0].size) {
1390 case 8:
1391 return V_028C70_COLOR_8_8;
1392 case 16:
1393 return V_028C70_COLOR_16_16;
1394 case 32:
1395 return V_028C70_COLOR_32_32;
1396 }
1397 } else if (HAS_SIZE(8,24,0,0)) {
1398 return V_028C70_COLOR_24_8;
1399 } else if (HAS_SIZE(24,8,0,0)) {
1400 return V_028C70_COLOR_8_24;
1401 }
1402 break;
1403 case 3:
1404 if (HAS_SIZE(5,6,5,0)) {
1405 return V_028C70_COLOR_5_6_5;
1406 } else if (HAS_SIZE(32,8,24,0)) {
1407 return V_028C70_COLOR_X24_8_32_FLOAT;
1408 }
1409 break;
1410 case 4:
1411 if (desc->channel[0].size == desc->channel[1].size &&
1412 desc->channel[0].size == desc->channel[2].size &&
1413 desc->channel[0].size == desc->channel[3].size) {
1414 switch (desc->channel[0].size) {
1415 case 4:
1416 return V_028C70_COLOR_4_4_4_4;
1417 case 8:
1418 return V_028C70_COLOR_8_8_8_8;
1419 case 16:
1420 return V_028C70_COLOR_16_16_16_16;
1421 case 32:
1422 return V_028C70_COLOR_32_32_32_32;
1423 }
1424 } else if (HAS_SIZE(5,5,5,1)) {
1425 return V_028C70_COLOR_1_5_5_5;
1426 } else if (HAS_SIZE(10,10,10,2)) {
1427 return V_028C70_COLOR_2_10_10_10;
1428 }
1429 break;
1430 }
1431 return V_028C70_COLOR_INVALID;
1432 }
1433
1434 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1435 {
1436 if (SI_BIG_ENDIAN) {
1437 switch(colorformat) {
1438 /* 8-bit buffers. */
1439 case V_028C70_COLOR_8:
1440 return V_028C70_ENDIAN_NONE;
1441
1442 /* 16-bit buffers. */
1443 case V_028C70_COLOR_5_6_5:
1444 case V_028C70_COLOR_1_5_5_5:
1445 case V_028C70_COLOR_4_4_4_4:
1446 case V_028C70_COLOR_16:
1447 case V_028C70_COLOR_8_8:
1448 return V_028C70_ENDIAN_8IN16;
1449
1450 /* 32-bit buffers. */
1451 case V_028C70_COLOR_8_8_8_8:
1452 case V_028C70_COLOR_2_10_10_10:
1453 case V_028C70_COLOR_8_24:
1454 case V_028C70_COLOR_24_8:
1455 case V_028C70_COLOR_16_16:
1456 return V_028C70_ENDIAN_8IN32;
1457
1458 /* 64-bit buffers. */
1459 case V_028C70_COLOR_16_16_16_16:
1460 return V_028C70_ENDIAN_8IN16;
1461
1462 case V_028C70_COLOR_32_32:
1463 return V_028C70_ENDIAN_8IN32;
1464
1465 /* 128-bit buffers. */
1466 case V_028C70_COLOR_32_32_32_32:
1467 return V_028C70_ENDIAN_8IN32;
1468 default:
1469 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1470 }
1471 } else {
1472 return V_028C70_ENDIAN_NONE;
1473 }
1474 }
1475
1476 static uint32_t si_translate_dbformat(enum pipe_format format)
1477 {
1478 switch (format) {
1479 case PIPE_FORMAT_Z16_UNORM:
1480 return V_028040_Z_16;
1481 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1482 case PIPE_FORMAT_X8Z24_UNORM:
1483 case PIPE_FORMAT_Z24X8_UNORM:
1484 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1485 return V_028040_Z_24; /* deprecated on SI */
1486 case PIPE_FORMAT_Z32_FLOAT:
1487 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1488 return V_028040_Z_32_FLOAT;
1489 default:
1490 return V_028040_Z_INVALID;
1491 }
1492 }
1493
1494 /*
1495 * Texture translation
1496 */
1497
1498 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1499 enum pipe_format format,
1500 const struct util_format_description *desc,
1501 int first_non_void)
1502 {
1503 struct si_screen *sscreen = (struct si_screen*)screen;
1504 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1505 sscreen->b.info.drm_minor >= 31) ||
1506 sscreen->b.info.drm_major == 3;
1507 boolean uniform = TRUE;
1508 int i;
1509
1510 /* Colorspace (return non-RGB formats directly). */
1511 switch (desc->colorspace) {
1512 /* Depth stencil formats */
1513 case UTIL_FORMAT_COLORSPACE_ZS:
1514 switch (format) {
1515 case PIPE_FORMAT_Z16_UNORM:
1516 return V_008F14_IMG_DATA_FORMAT_16;
1517 case PIPE_FORMAT_X24S8_UINT:
1518 case PIPE_FORMAT_Z24X8_UNORM:
1519 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1520 return V_008F14_IMG_DATA_FORMAT_8_24;
1521 case PIPE_FORMAT_X8Z24_UNORM:
1522 case PIPE_FORMAT_S8X24_UINT:
1523 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1524 return V_008F14_IMG_DATA_FORMAT_24_8;
1525 case PIPE_FORMAT_S8_UINT:
1526 return V_008F14_IMG_DATA_FORMAT_8;
1527 case PIPE_FORMAT_Z32_FLOAT:
1528 return V_008F14_IMG_DATA_FORMAT_32;
1529 case PIPE_FORMAT_X32_S8X24_UINT:
1530 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1531 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1532 default:
1533 goto out_unknown;
1534 }
1535
1536 case UTIL_FORMAT_COLORSPACE_YUV:
1537 goto out_unknown; /* TODO */
1538
1539 case UTIL_FORMAT_COLORSPACE_SRGB:
1540 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1541 goto out_unknown;
1542 break;
1543
1544 default:
1545 break;
1546 }
1547
1548 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1549 if (!enable_compressed_formats)
1550 goto out_unknown;
1551
1552 switch (format) {
1553 case PIPE_FORMAT_RGTC1_SNORM:
1554 case PIPE_FORMAT_LATC1_SNORM:
1555 case PIPE_FORMAT_RGTC1_UNORM:
1556 case PIPE_FORMAT_LATC1_UNORM:
1557 return V_008F14_IMG_DATA_FORMAT_BC4;
1558 case PIPE_FORMAT_RGTC2_SNORM:
1559 case PIPE_FORMAT_LATC2_SNORM:
1560 case PIPE_FORMAT_RGTC2_UNORM:
1561 case PIPE_FORMAT_LATC2_UNORM:
1562 return V_008F14_IMG_DATA_FORMAT_BC5;
1563 default:
1564 goto out_unknown;
1565 }
1566 }
1567
1568 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1569 sscreen->b.family >= CHIP_STONEY) {
1570 switch (format) {
1571 case PIPE_FORMAT_ETC1_RGB8:
1572 case PIPE_FORMAT_ETC2_RGB8:
1573 case PIPE_FORMAT_ETC2_SRGB8:
1574 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1575 case PIPE_FORMAT_ETC2_RGB8A1:
1576 case PIPE_FORMAT_ETC2_SRGB8A1:
1577 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1578 case PIPE_FORMAT_ETC2_RGBA8:
1579 case PIPE_FORMAT_ETC2_SRGBA8:
1580 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1581 case PIPE_FORMAT_ETC2_R11_UNORM:
1582 case PIPE_FORMAT_ETC2_R11_SNORM:
1583 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1584 case PIPE_FORMAT_ETC2_RG11_UNORM:
1585 case PIPE_FORMAT_ETC2_RG11_SNORM:
1586 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1587 default:
1588 goto out_unknown;
1589 }
1590 }
1591
1592 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1593 if (!enable_compressed_formats)
1594 goto out_unknown;
1595
1596 switch (format) {
1597 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1598 case PIPE_FORMAT_BPTC_SRGBA:
1599 return V_008F14_IMG_DATA_FORMAT_BC7;
1600 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1601 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1602 return V_008F14_IMG_DATA_FORMAT_BC6;
1603 default:
1604 goto out_unknown;
1605 }
1606 }
1607
1608 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1609 switch (format) {
1610 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1611 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1612 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1613 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1614 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1615 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1616 default:
1617 goto out_unknown;
1618 }
1619 }
1620
1621 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1622 if (!enable_compressed_formats)
1623 goto out_unknown;
1624
1625 if (!util_format_s3tc_enabled) {
1626 goto out_unknown;
1627 }
1628
1629 switch (format) {
1630 case PIPE_FORMAT_DXT1_RGB:
1631 case PIPE_FORMAT_DXT1_RGBA:
1632 case PIPE_FORMAT_DXT1_SRGB:
1633 case PIPE_FORMAT_DXT1_SRGBA:
1634 return V_008F14_IMG_DATA_FORMAT_BC1;
1635 case PIPE_FORMAT_DXT3_RGBA:
1636 case PIPE_FORMAT_DXT3_SRGBA:
1637 return V_008F14_IMG_DATA_FORMAT_BC2;
1638 case PIPE_FORMAT_DXT5_RGBA:
1639 case PIPE_FORMAT_DXT5_SRGBA:
1640 return V_008F14_IMG_DATA_FORMAT_BC3;
1641 default:
1642 goto out_unknown;
1643 }
1644 }
1645
1646 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1647 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1648 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1649 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1650 }
1651
1652 /* R8G8Bx_SNORM - TODO CxV8U8 */
1653
1654 /* See whether the components are of the same size. */
1655 for (i = 1; i < desc->nr_channels; i++) {
1656 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1657 }
1658
1659 /* Non-uniform formats. */
1660 if (!uniform) {
1661 switch(desc->nr_channels) {
1662 case 3:
1663 if (desc->channel[0].size == 5 &&
1664 desc->channel[1].size == 6 &&
1665 desc->channel[2].size == 5) {
1666 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1667 }
1668 goto out_unknown;
1669 case 4:
1670 if (desc->channel[0].size == 5 &&
1671 desc->channel[1].size == 5 &&
1672 desc->channel[2].size == 5 &&
1673 desc->channel[3].size == 1) {
1674 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1675 }
1676 if (desc->channel[0].size == 10 &&
1677 desc->channel[1].size == 10 &&
1678 desc->channel[2].size == 10 &&
1679 desc->channel[3].size == 2) {
1680 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1681 }
1682 goto out_unknown;
1683 }
1684 goto out_unknown;
1685 }
1686
1687 if (first_non_void < 0 || first_non_void > 3)
1688 goto out_unknown;
1689
1690 /* uniform formats */
1691 switch (desc->channel[first_non_void].size) {
1692 case 4:
1693 switch (desc->nr_channels) {
1694 #if 0 /* Not supported for render targets */
1695 case 2:
1696 return V_008F14_IMG_DATA_FORMAT_4_4;
1697 #endif
1698 case 4:
1699 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1700 }
1701 break;
1702 case 8:
1703 switch (desc->nr_channels) {
1704 case 1:
1705 return V_008F14_IMG_DATA_FORMAT_8;
1706 case 2:
1707 return V_008F14_IMG_DATA_FORMAT_8_8;
1708 case 4:
1709 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1710 }
1711 break;
1712 case 16:
1713 switch (desc->nr_channels) {
1714 case 1:
1715 return V_008F14_IMG_DATA_FORMAT_16;
1716 case 2:
1717 return V_008F14_IMG_DATA_FORMAT_16_16;
1718 case 4:
1719 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1720 }
1721 break;
1722 case 32:
1723 switch (desc->nr_channels) {
1724 case 1:
1725 return V_008F14_IMG_DATA_FORMAT_32;
1726 case 2:
1727 return V_008F14_IMG_DATA_FORMAT_32_32;
1728 #if 0 /* Not supported for render targets */
1729 case 3:
1730 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1731 #endif
1732 case 4:
1733 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1734 }
1735 }
1736
1737 out_unknown:
1738 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1739 return ~0;
1740 }
1741
1742 static unsigned si_tex_wrap(unsigned wrap)
1743 {
1744 switch (wrap) {
1745 default:
1746 case PIPE_TEX_WRAP_REPEAT:
1747 return V_008F30_SQ_TEX_WRAP;
1748 case PIPE_TEX_WRAP_CLAMP:
1749 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1750 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1751 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1752 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1753 return V_008F30_SQ_TEX_CLAMP_BORDER;
1754 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1755 return V_008F30_SQ_TEX_MIRROR;
1756 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1757 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1758 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1759 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1760 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1761 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1762 }
1763 }
1764
1765 static unsigned si_tex_filter(unsigned filter)
1766 {
1767 switch (filter) {
1768 default:
1769 case PIPE_TEX_FILTER_NEAREST:
1770 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1771 case PIPE_TEX_FILTER_LINEAR:
1772 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1773 }
1774 }
1775
1776 static unsigned si_tex_mipfilter(unsigned filter)
1777 {
1778 switch (filter) {
1779 case PIPE_TEX_MIPFILTER_NEAREST:
1780 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1781 case PIPE_TEX_MIPFILTER_LINEAR:
1782 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1783 default:
1784 case PIPE_TEX_MIPFILTER_NONE:
1785 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1786 }
1787 }
1788
1789 static unsigned si_tex_compare(unsigned compare)
1790 {
1791 switch (compare) {
1792 default:
1793 case PIPE_FUNC_NEVER:
1794 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1795 case PIPE_FUNC_LESS:
1796 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1797 case PIPE_FUNC_EQUAL:
1798 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1799 case PIPE_FUNC_LEQUAL:
1800 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1801 case PIPE_FUNC_GREATER:
1802 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1803 case PIPE_FUNC_NOTEQUAL:
1804 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1805 case PIPE_FUNC_GEQUAL:
1806 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1807 case PIPE_FUNC_ALWAYS:
1808 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1809 }
1810 }
1811
1812 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1813 unsigned nr_samples)
1814 {
1815 if (view_target == PIPE_TEXTURE_CUBE ||
1816 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1817 res_target = view_target;
1818
1819 switch (res_target) {
1820 default:
1821 case PIPE_TEXTURE_1D:
1822 return V_008F1C_SQ_RSRC_IMG_1D;
1823 case PIPE_TEXTURE_1D_ARRAY:
1824 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1825 case PIPE_TEXTURE_2D:
1826 case PIPE_TEXTURE_RECT:
1827 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1828 V_008F1C_SQ_RSRC_IMG_2D;
1829 case PIPE_TEXTURE_2D_ARRAY:
1830 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1831 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1832 case PIPE_TEXTURE_3D:
1833 return V_008F1C_SQ_RSRC_IMG_3D;
1834 case PIPE_TEXTURE_CUBE:
1835 case PIPE_TEXTURE_CUBE_ARRAY:
1836 return V_008F1C_SQ_RSRC_IMG_CUBE;
1837 }
1838 }
1839
1840 /*
1841 * Format support testing
1842 */
1843
1844 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1845 {
1846 return si_translate_texformat(screen, format, util_format_description(format),
1847 util_format_get_first_non_void_channel(format)) != ~0U;
1848 }
1849
1850 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1851 const struct util_format_description *desc,
1852 int first_non_void)
1853 {
1854 unsigned type = desc->channel[first_non_void].type;
1855 int i;
1856
1857 if (type == UTIL_FORMAT_TYPE_FIXED)
1858 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1859
1860 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1861 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1862
1863 if (desc->nr_channels == 4 &&
1864 desc->channel[0].size == 10 &&
1865 desc->channel[1].size == 10 &&
1866 desc->channel[2].size == 10 &&
1867 desc->channel[3].size == 2)
1868 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1869
1870 /* See whether the components are of the same size. */
1871 for (i = 0; i < desc->nr_channels; i++) {
1872 if (desc->channel[first_non_void].size != desc->channel[i].size)
1873 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1874 }
1875
1876 switch (desc->channel[first_non_void].size) {
1877 case 8:
1878 switch (desc->nr_channels) {
1879 case 1:
1880 return V_008F0C_BUF_DATA_FORMAT_8;
1881 case 2:
1882 return V_008F0C_BUF_DATA_FORMAT_8_8;
1883 case 3:
1884 case 4:
1885 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1886 }
1887 break;
1888 case 16:
1889 switch (desc->nr_channels) {
1890 case 1:
1891 return V_008F0C_BUF_DATA_FORMAT_16;
1892 case 2:
1893 return V_008F0C_BUF_DATA_FORMAT_16_16;
1894 case 3:
1895 case 4:
1896 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1897 }
1898 break;
1899 case 32:
1900 /* From the Southern Islands ISA documentation about MTBUF:
1901 * 'Memory reads of data in memory that is 32 or 64 bits do not
1902 * undergo any format conversion.'
1903 */
1904 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1905 !desc->channel[first_non_void].pure_integer)
1906 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1907
1908 switch (desc->nr_channels) {
1909 case 1:
1910 return V_008F0C_BUF_DATA_FORMAT_32;
1911 case 2:
1912 return V_008F0C_BUF_DATA_FORMAT_32_32;
1913 case 3:
1914 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1915 case 4:
1916 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1917 }
1918 break;
1919 }
1920
1921 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1922 }
1923
1924 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1925 const struct util_format_description *desc,
1926 int first_non_void)
1927 {
1928 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1929 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1930
1931 switch (desc->channel[first_non_void].type) {
1932 case UTIL_FORMAT_TYPE_SIGNED:
1933 if (desc->channel[first_non_void].normalized)
1934 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1935 else if (desc->channel[first_non_void].pure_integer)
1936 return V_008F0C_BUF_NUM_FORMAT_SINT;
1937 else
1938 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1939 break;
1940 case UTIL_FORMAT_TYPE_UNSIGNED:
1941 if (desc->channel[first_non_void].normalized)
1942 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1943 else if (desc->channel[first_non_void].pure_integer)
1944 return V_008F0C_BUF_NUM_FORMAT_UINT;
1945 else
1946 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1947 break;
1948 case UTIL_FORMAT_TYPE_FLOAT:
1949 default:
1950 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1951 }
1952 }
1953
1954 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1955 {
1956 const struct util_format_description *desc;
1957 int first_non_void;
1958 unsigned data_format;
1959
1960 desc = util_format_description(format);
1961 first_non_void = util_format_get_first_non_void_channel(format);
1962 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1963 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1964 }
1965
1966 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1967 {
1968 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1969 r600_translate_colorswap(format) != ~0U;
1970 }
1971
1972 static bool si_is_zs_format_supported(enum pipe_format format)
1973 {
1974 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1975 }
1976
1977 boolean si_is_format_supported(struct pipe_screen *screen,
1978 enum pipe_format format,
1979 enum pipe_texture_target target,
1980 unsigned sample_count,
1981 unsigned usage)
1982 {
1983 unsigned retval = 0;
1984
1985 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1986 R600_ERR("r600: unsupported texture type %d\n", target);
1987 return FALSE;
1988 }
1989
1990 if (!util_format_is_supported(format, usage))
1991 return FALSE;
1992
1993 if (sample_count > 1) {
1994 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1995 return FALSE;
1996
1997 switch (sample_count) {
1998 case 2:
1999 case 4:
2000 case 8:
2001 break;
2002 default:
2003 return FALSE;
2004 }
2005 }
2006
2007 if (usage & PIPE_BIND_SAMPLER_VIEW) {
2008 if (target == PIPE_BUFFER) {
2009 if (si_is_vertex_format_supported(screen, format))
2010 retval |= PIPE_BIND_SAMPLER_VIEW;
2011 } else {
2012 if (si_is_sampler_format_supported(screen, format))
2013 retval |= PIPE_BIND_SAMPLER_VIEW;
2014 }
2015 }
2016
2017 if ((usage & (PIPE_BIND_RENDER_TARGET |
2018 PIPE_BIND_DISPLAY_TARGET |
2019 PIPE_BIND_SCANOUT |
2020 PIPE_BIND_SHARED |
2021 PIPE_BIND_BLENDABLE)) &&
2022 si_is_colorbuffer_format_supported(format)) {
2023 retval |= usage &
2024 (PIPE_BIND_RENDER_TARGET |
2025 PIPE_BIND_DISPLAY_TARGET |
2026 PIPE_BIND_SCANOUT |
2027 PIPE_BIND_SHARED);
2028 if (!util_format_is_pure_integer(format) &&
2029 !util_format_is_depth_or_stencil(format))
2030 retval |= usage & PIPE_BIND_BLENDABLE;
2031 }
2032
2033 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2034 si_is_zs_format_supported(format)) {
2035 retval |= PIPE_BIND_DEPTH_STENCIL;
2036 }
2037
2038 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
2039 si_is_vertex_format_supported(screen, format)) {
2040 retval |= PIPE_BIND_VERTEX_BUFFER;
2041 }
2042
2043 if (usage & PIPE_BIND_TRANSFER_READ)
2044 retval |= PIPE_BIND_TRANSFER_READ;
2045 if (usage & PIPE_BIND_TRANSFER_WRITE)
2046 retval |= PIPE_BIND_TRANSFER_WRITE;
2047
2048 return retval == usage;
2049 }
2050
2051 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
2052 {
2053 unsigned tile_mode_index = 0;
2054
2055 if (stencil) {
2056 tile_mode_index = rtex->surface.stencil_tiling_index[level];
2057 } else {
2058 tile_mode_index = rtex->surface.tiling_index[level];
2059 }
2060 return tile_mode_index;
2061 }
2062
2063 /*
2064 * framebuffer handling
2065 */
2066
2067 static void si_choose_spi_color_formats(struct r600_surface *surf,
2068 unsigned format, unsigned swap,
2069 unsigned ntype, bool is_depth)
2070 {
2071 /* Alpha is needed for alpha-to-coverage.
2072 * Blending may be with or without alpha.
2073 */
2074 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2075 unsigned alpha = 0; /* exports alpha, but may not support blending */
2076 unsigned blend = 0; /* supports blending, but may not export alpha */
2077 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2078
2079 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2080 * Other chips have multiple choices, though they are not necessarily better.
2081 */
2082 switch (format) {
2083 case V_028C70_COLOR_5_6_5:
2084 case V_028C70_COLOR_1_5_5_5:
2085 case V_028C70_COLOR_5_5_5_1:
2086 case V_028C70_COLOR_4_4_4_4:
2087 case V_028C70_COLOR_10_11_11:
2088 case V_028C70_COLOR_11_11_10:
2089 case V_028C70_COLOR_8:
2090 case V_028C70_COLOR_8_8:
2091 case V_028C70_COLOR_8_8_8_8:
2092 case V_028C70_COLOR_10_10_10_2:
2093 case V_028C70_COLOR_2_10_10_10:
2094 if (ntype == V_028C70_NUMBER_UINT)
2095 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2096 else if (ntype == V_028C70_NUMBER_SINT)
2097 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2098 else
2099 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2100 break;
2101
2102 case V_028C70_COLOR_16:
2103 case V_028C70_COLOR_16_16:
2104 case V_028C70_COLOR_16_16_16_16:
2105 if (ntype == V_028C70_NUMBER_UNORM ||
2106 ntype == V_028C70_NUMBER_SNORM) {
2107 /* UNORM16 and SNORM16 don't support blending */
2108 if (ntype == V_028C70_NUMBER_UNORM)
2109 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2110 else
2111 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2112
2113 /* Use 32 bits per channel for blending. */
2114 if (format == V_028C70_COLOR_16) {
2115 if (swap == V_028C70_SWAP_STD) { /* R */
2116 blend = V_028714_SPI_SHADER_32_R;
2117 blend_alpha = V_028714_SPI_SHADER_32_AR;
2118 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2119 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2120 else
2121 assert(0);
2122 } else if (format == V_028C70_COLOR_16_16) {
2123 if (swap == V_028C70_SWAP_STD) { /* RG */
2124 blend = V_028714_SPI_SHADER_32_GR;
2125 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2126 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2127 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2128 else
2129 assert(0);
2130 } else /* 16_16_16_16 */
2131 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2132 } else if (ntype == V_028C70_NUMBER_UINT)
2133 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2134 else if (ntype == V_028C70_NUMBER_SINT)
2135 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2136 else if (ntype == V_028C70_NUMBER_FLOAT)
2137 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2138 else
2139 assert(0);
2140 break;
2141
2142 case V_028C70_COLOR_32:
2143 if (swap == V_028C70_SWAP_STD) { /* R */
2144 blend = normal = V_028714_SPI_SHADER_32_R;
2145 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2146 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2147 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2148 else
2149 assert(0);
2150 break;
2151
2152 case V_028C70_COLOR_32_32:
2153 if (swap == V_028C70_SWAP_STD) { /* RG */
2154 blend = normal = V_028714_SPI_SHADER_32_GR;
2155 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2156 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2157 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2158 else
2159 assert(0);
2160 break;
2161
2162 case V_028C70_COLOR_32_32_32_32:
2163 case V_028C70_COLOR_8_24:
2164 case V_028C70_COLOR_24_8:
2165 case V_028C70_COLOR_X24_8_32_FLOAT:
2166 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2167 break;
2168
2169 default:
2170 assert(0);
2171 return;
2172 }
2173
2174 /* The DB->CB copy needs 32_ABGR. */
2175 if (is_depth)
2176 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2177
2178 surf->spi_shader_col_format = normal;
2179 surf->spi_shader_col_format_alpha = alpha;
2180 surf->spi_shader_col_format_blend = blend;
2181 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2182 }
2183
2184 static void si_initialize_color_surface(struct si_context *sctx,
2185 struct r600_surface *surf)
2186 {
2187 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2188 unsigned level = surf->base.u.tex.level;
2189 uint64_t offset = rtex->surface.level[level].offset;
2190 unsigned pitch, slice;
2191 unsigned color_info, color_attrib, color_pitch, color_view;
2192 unsigned tile_mode_index;
2193 unsigned format, swap, ntype, endian;
2194 const struct util_format_description *desc;
2195 int i;
2196 unsigned blend_clamp = 0, blend_bypass = 0;
2197
2198 /* Layered rendering doesn't work with LINEAR_GENERAL.
2199 * (LINEAR_ALIGNED and others work) */
2200 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2201 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2202 offset += rtex->surface.level[level].slice_size *
2203 surf->base.u.tex.first_layer;
2204 color_view = 0;
2205 } else {
2206 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2207 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2208 }
2209
2210 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2211 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2212 if (slice) {
2213 slice = slice - 1;
2214 }
2215
2216 tile_mode_index = si_tile_mode_index(rtex, level, false);
2217
2218 desc = util_format_description(surf->base.format);
2219 for (i = 0; i < 4; i++) {
2220 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2221 break;
2222 }
2223 }
2224 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2225 ntype = V_028C70_NUMBER_FLOAT;
2226 } else {
2227 ntype = V_028C70_NUMBER_UNORM;
2228 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2229 ntype = V_028C70_NUMBER_SRGB;
2230 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2231 if (desc->channel[i].pure_integer) {
2232 ntype = V_028C70_NUMBER_SINT;
2233 } else {
2234 assert(desc->channel[i].normalized);
2235 ntype = V_028C70_NUMBER_SNORM;
2236 }
2237 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2238 if (desc->channel[i].pure_integer) {
2239 ntype = V_028C70_NUMBER_UINT;
2240 } else {
2241 assert(desc->channel[i].normalized);
2242 ntype = V_028C70_NUMBER_UNORM;
2243 }
2244 }
2245 }
2246
2247 format = si_translate_colorformat(surf->base.format);
2248 if (format == V_028C70_COLOR_INVALID) {
2249 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2250 }
2251 assert(format != V_028C70_COLOR_INVALID);
2252 swap = r600_translate_colorswap(surf->base.format);
2253 endian = si_colorformat_endian_swap(format);
2254
2255 /* blend clamp should be set for all NORM/SRGB types */
2256 if (ntype == V_028C70_NUMBER_UNORM ||
2257 ntype == V_028C70_NUMBER_SNORM ||
2258 ntype == V_028C70_NUMBER_SRGB)
2259 blend_clamp = 1;
2260
2261 /* set blend bypass according to docs if SINT/UINT or
2262 8/24 COLOR variants */
2263 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2264 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2265 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2266 blend_clamp = 0;
2267 blend_bypass = 1;
2268 }
2269
2270 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2271 (format == V_028C70_COLOR_8 ||
2272 format == V_028C70_COLOR_8_8 ||
2273 format == V_028C70_COLOR_8_8_8_8))
2274 surf->color_is_int8 = true;
2275
2276 color_info = S_028C70_FORMAT(format) |
2277 S_028C70_COMP_SWAP(swap) |
2278 S_028C70_BLEND_CLAMP(blend_clamp) |
2279 S_028C70_BLEND_BYPASS(blend_bypass) |
2280 S_028C70_NUMBER_TYPE(ntype) |
2281 S_028C70_ENDIAN(endian);
2282
2283 color_pitch = S_028C64_TILE_MAX(pitch);
2284
2285 /* Intensity is implemented as Red, so treat it that way. */
2286 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2287 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1 ||
2288 util_format_is_intensity(surf->base.format));
2289
2290 if (rtex->resource.b.b.nr_samples > 1) {
2291 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2292
2293 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2294 S_028C74_NUM_FRAGMENTS(log_samples);
2295
2296 if (rtex->fmask.size) {
2297 color_info |= S_028C70_COMPRESSION(1);
2298 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2299
2300 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2301
2302 if (sctx->b.chip_class == SI) {
2303 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2304 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2305 }
2306 if (sctx->b.chip_class >= CIK) {
2307 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2308 }
2309 }
2310 }
2311
2312 offset += rtex->resource.gpu_address;
2313
2314 surf->cb_color_base = offset >> 8;
2315 surf->cb_color_pitch = color_pitch;
2316 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2317 surf->cb_color_view = color_view;
2318 surf->cb_color_info = color_info;
2319 surf->cb_color_attrib = color_attrib;
2320
2321 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2322 unsigned max_uncompressed_block_size = 2;
2323
2324 if (rtex->surface.nsamples > 1) {
2325 if (rtex->surface.bpe == 1)
2326 max_uncompressed_block_size = 0;
2327 else if (rtex->surface.bpe == 2)
2328 max_uncompressed_block_size = 1;
2329 }
2330
2331 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2332 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2333 surf->cb_dcc_base = (rtex->resource.gpu_address +
2334 rtex->dcc_offset +
2335 rtex->surface.level[level].dcc_offset) >> 8;
2336 }
2337
2338 if (rtex->fmask.size) {
2339 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2340 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2341 } else {
2342 /* This must be set for fast clear to work without FMASK. */
2343 surf->cb_color_fmask = surf->cb_color_base;
2344 surf->cb_color_fmask_slice = surf->cb_color_slice;
2345 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2346
2347 if (sctx->b.chip_class == SI) {
2348 unsigned bankh = util_logbase2(rtex->surface.bankh);
2349 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2350 }
2351
2352 if (sctx->b.chip_class >= CIK) {
2353 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2354 }
2355 }
2356
2357 /* Determine pixel shader export format */
2358 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2359
2360 surf->color_initialized = true;
2361 }
2362
2363 static void si_init_depth_surface(struct si_context *sctx,
2364 struct r600_surface *surf)
2365 {
2366 struct si_screen *sscreen = sctx->screen;
2367 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2368 unsigned level = surf->base.u.tex.level;
2369 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2370 unsigned format, tile_mode_index, array_mode;
2371 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2372 uint32_t z_info, s_info, db_depth_info;
2373 uint64_t z_offs, s_offs;
2374 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2375
2376 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2377 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2378 case PIPE_FORMAT_X8Z24_UNORM:
2379 case PIPE_FORMAT_Z24X8_UNORM:
2380 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2381 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2382 break;
2383 case PIPE_FORMAT_Z32_FLOAT:
2384 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2385 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2386 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2387 break;
2388 case PIPE_FORMAT_Z16_UNORM:
2389 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2390 break;
2391 default:
2392 assert(0);
2393 }
2394
2395 format = si_translate_dbformat(rtex->resource.b.b.format);
2396
2397 if (format == V_028040_Z_INVALID) {
2398 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2399 }
2400 assert(format != V_028040_Z_INVALID);
2401
2402 s_offs = z_offs = rtex->resource.gpu_address;
2403 z_offs += rtex->surface.level[level].offset;
2404 s_offs += rtex->surface.stencil_level[level].offset;
2405
2406 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2407
2408 z_info = S_028040_FORMAT(format);
2409 if (rtex->resource.b.b.nr_samples > 1) {
2410 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2411 }
2412
2413 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2414 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2415 else
2416 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2417
2418 if (sctx->b.chip_class >= CIK) {
2419 switch (rtex->surface.level[level].mode) {
2420 case RADEON_SURF_MODE_2D:
2421 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2422 break;
2423 case RADEON_SURF_MODE_1D:
2424 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2425 case RADEON_SURF_MODE_LINEAR:
2426 default:
2427 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2428 break;
2429 }
2430 tile_split = rtex->surface.tile_split;
2431 stile_split = rtex->surface.stencil_tile_split;
2432 macro_aspect = rtex->surface.mtilea;
2433 bankw = rtex->surface.bankw;
2434 bankh = rtex->surface.bankh;
2435 tile_split = cik_tile_split(tile_split);
2436 stile_split = cik_tile_split(stile_split);
2437 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2438 bankw = cik_bank_wh(bankw);
2439 bankh = cik_bank_wh(bankh);
2440 nbanks = si_num_banks(sscreen, rtex);
2441 tile_mode_index = si_tile_mode_index(rtex, level, false);
2442 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2443
2444 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2445 S_02803C_PIPE_CONFIG(pipe_config) |
2446 S_02803C_BANK_WIDTH(bankw) |
2447 S_02803C_BANK_HEIGHT(bankh) |
2448 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2449 S_02803C_NUM_BANKS(nbanks);
2450 z_info |= S_028040_TILE_SPLIT(tile_split);
2451 s_info |= S_028044_TILE_SPLIT(stile_split);
2452 } else {
2453 tile_mode_index = si_tile_mode_index(rtex, level, false);
2454 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2455 tile_mode_index = si_tile_mode_index(rtex, level, true);
2456 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2457 }
2458
2459 /* HiZ aka depth buffer htile */
2460 /* use htile only for first level */
2461 if (rtex->htile_buffer && !level) {
2462 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2463 S_028040_ALLOW_EXPCLEAR(1);
2464
2465 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2466 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2467 else
2468 /* Use all of the htile_buffer for depth if there's no stencil. */
2469 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2470
2471 uint64_t va = rtex->htile_buffer->gpu_address;
2472 db_htile_data_base = va >> 8;
2473 db_htile_surface = S_028ABC_FULL_CACHE(1);
2474 } else {
2475 db_htile_data_base = 0;
2476 db_htile_surface = 0;
2477 }
2478
2479 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2480
2481 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2482 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2483 surf->db_htile_data_base = db_htile_data_base;
2484 surf->db_depth_info = db_depth_info;
2485 surf->db_z_info = z_info;
2486 surf->db_stencil_info = s_info;
2487 surf->db_depth_base = z_offs >> 8;
2488 surf->db_stencil_base = s_offs >> 8;
2489 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2490 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2491 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2492 levelinfo->nblk_y) / 64 - 1);
2493 surf->db_htile_surface = db_htile_surface;
2494 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2495
2496 surf->depth_initialized = true;
2497 }
2498
2499 static void si_set_framebuffer_state(struct pipe_context *ctx,
2500 const struct pipe_framebuffer_state *state)
2501 {
2502 struct si_context *sctx = (struct si_context *)ctx;
2503 struct pipe_constant_buffer constbuf = {0};
2504 struct r600_surface *surf = NULL;
2505 struct r600_texture *rtex;
2506 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2507 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2508 int i;
2509
2510 /* Only flush TC when changing the framebuffer state, because
2511 * the only client not using TC that can change textures is
2512 * the framebuffer.
2513 *
2514 * Flush all CB and DB caches here because all buffers can be used
2515 * for write by both TC (with shader image stores) and CB/DB.
2516 */
2517 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2518 SI_CONTEXT_INV_GLOBAL_L2 |
2519 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2520
2521 /* Take the maximum of the old and new count. If the new count is lower,
2522 * dirtying is needed to disable the unbound colorbuffers.
2523 */
2524 sctx->framebuffer.dirty_cbufs |=
2525 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2526 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2527
2528 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2529
2530 sctx->framebuffer.spi_shader_col_format = 0;
2531 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2532 sctx->framebuffer.spi_shader_col_format_blend = 0;
2533 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2534 sctx->framebuffer.color_is_int8 = 0;
2535
2536 sctx->framebuffer.compressed_cb_mask = 0;
2537 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2538 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2539 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2540 util_format_is_pure_integer(state->cbufs[0]->format);
2541
2542 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2543 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2544
2545 for (i = 0; i < state->nr_cbufs; i++) {
2546 if (!state->cbufs[i])
2547 continue;
2548
2549 surf = (struct r600_surface*)state->cbufs[i];
2550 rtex = (struct r600_texture*)surf->base.texture;
2551
2552 if (!surf->color_initialized) {
2553 si_initialize_color_surface(sctx, surf);
2554 }
2555
2556 sctx->framebuffer.spi_shader_col_format |=
2557 surf->spi_shader_col_format << (i * 4);
2558 sctx->framebuffer.spi_shader_col_format_alpha |=
2559 surf->spi_shader_col_format_alpha << (i * 4);
2560 sctx->framebuffer.spi_shader_col_format_blend |=
2561 surf->spi_shader_col_format_blend << (i * 4);
2562 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2563 surf->spi_shader_col_format_blend_alpha << (i * 4);
2564
2565 if (surf->color_is_int8)
2566 sctx->framebuffer.color_is_int8 |= 1 << i;
2567
2568 if (rtex->fmask.size && rtex->cmask.size) {
2569 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2570 }
2571 r600_context_add_resource_size(ctx, surf->base.texture);
2572 }
2573 /* Set the second SPI format for possible dual-src blending. */
2574 if (i == 1 && surf) {
2575 sctx->framebuffer.spi_shader_col_format |=
2576 surf->spi_shader_col_format << (i * 4);
2577 sctx->framebuffer.spi_shader_col_format_alpha |=
2578 surf->spi_shader_col_format_alpha << (i * 4);
2579 sctx->framebuffer.spi_shader_col_format_blend |=
2580 surf->spi_shader_col_format_blend << (i * 4);
2581 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2582 surf->spi_shader_col_format_blend_alpha << (i * 4);
2583 }
2584
2585 if (state->zsbuf) {
2586 surf = (struct r600_surface*)state->zsbuf;
2587
2588 if (!surf->depth_initialized) {
2589 si_init_depth_surface(sctx, surf);
2590 }
2591 r600_context_add_resource_size(ctx, surf->base.texture);
2592 }
2593
2594 si_update_poly_offset_state(sctx);
2595 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2596 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2597
2598 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2599 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2600 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2601
2602 /* Set sample locations as fragment shader constants. */
2603 switch (sctx->framebuffer.nr_samples) {
2604 case 1:
2605 constbuf.user_buffer = sctx->b.sample_locations_1x;
2606 break;
2607 case 2:
2608 constbuf.user_buffer = sctx->b.sample_locations_2x;
2609 break;
2610 case 4:
2611 constbuf.user_buffer = sctx->b.sample_locations_4x;
2612 break;
2613 case 8:
2614 constbuf.user_buffer = sctx->b.sample_locations_8x;
2615 break;
2616 case 16:
2617 constbuf.user_buffer = sctx->b.sample_locations_16x;
2618 break;
2619 default:
2620 assert(0);
2621 }
2622 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2623 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2624 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2625
2626 /* Smoothing (only possible with nr_samples == 1) uses the same
2627 * sample locations as the MSAA it simulates.
2628 *
2629 * Therefore, don't update the sample locations when
2630 * transitioning from no AA to smoothing-equivalent AA, and
2631 * vice versa.
2632 */
2633 if ((sctx->framebuffer.nr_samples != 1 ||
2634 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2635 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2636 old_nr_samples != 1))
2637 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2638 }
2639 }
2640
2641 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2642 {
2643 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2644 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2645 unsigned i, nr_cbufs = state->nr_cbufs;
2646 struct r600_texture *tex = NULL;
2647 struct r600_surface *cb = NULL;
2648
2649 /* Colorbuffers. */
2650 for (i = 0; i < nr_cbufs; i++) {
2651 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2652 continue;
2653
2654 cb = (struct r600_surface*)state->cbufs[i];
2655 if (!cb) {
2656 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2657 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2658 continue;
2659 }
2660
2661 tex = (struct r600_texture *)cb->base.texture;
2662 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2663 &tex->resource, RADEON_USAGE_READWRITE,
2664 tex->surface.nsamples > 1 ?
2665 RADEON_PRIO_COLOR_BUFFER_MSAA :
2666 RADEON_PRIO_COLOR_BUFFER);
2667
2668 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2669 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2670 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2671 RADEON_PRIO_CMASK);
2672 }
2673
2674 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2675 sctx->b.chip_class >= VI ? 14 : 13);
2676 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2677 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2678 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2679 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2680 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2681 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2682 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2683 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2684 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2685 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2686 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2687 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2688 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2689
2690 if (sctx->b.chip_class >= VI)
2691 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2692 }
2693 /* set CB_COLOR1_INFO for possible dual-src blending */
2694 if (i == 1 && state->cbufs[0] &&
2695 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2696 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2697 cb->cb_color_info | tex->cb_color_info);
2698 i++;
2699 }
2700 for (; i < 8 ; i++)
2701 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2702 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2703
2704 /* ZS buffer. */
2705 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2706 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2707 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2708
2709 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2710 &rtex->resource, RADEON_USAGE_READWRITE,
2711 zb->base.texture->nr_samples > 1 ?
2712 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2713 RADEON_PRIO_DEPTH_BUFFER);
2714
2715 if (zb->db_htile_data_base) {
2716 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2717 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2718 RADEON_PRIO_HTILE);
2719 }
2720
2721 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2722 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2723
2724 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2725 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2726 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2727 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2728 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2729 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2730 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2731 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2732 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2733 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2734 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2735
2736 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2737 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2738 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2739
2740 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2741 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2742 zb->pa_su_poly_offset_db_fmt_cntl);
2743 } else if (sctx->framebuffer.dirty_zsbuf) {
2744 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2745 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2746 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2747 }
2748
2749 /* Framebuffer dimensions. */
2750 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2751 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2752 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2753
2754 sctx->framebuffer.dirty_cbufs = 0;
2755 sctx->framebuffer.dirty_zsbuf = false;
2756 }
2757
2758 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2759 struct r600_atom *atom)
2760 {
2761 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2762 unsigned nr_samples = sctx->framebuffer.nr_samples;
2763
2764 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2765 SI_NUM_SMOOTH_AA_SAMPLES);
2766 }
2767
2768 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2769 {
2770 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2771
2772 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2773 sctx->ps_iter_samples,
2774 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2775 }
2776
2777
2778 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2779 {
2780 struct si_context *sctx = (struct si_context *)ctx;
2781
2782 if (sctx->ps_iter_samples == min_samples)
2783 return;
2784
2785 sctx->ps_iter_samples = min_samples;
2786
2787 if (sctx->framebuffer.nr_samples > 1)
2788 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2789 }
2790
2791 /*
2792 * Samplers
2793 */
2794
2795 /**
2796 * Build the sampler view descriptor for a buffer texture.
2797 * @param state 256-bit descriptor; only the high 128 bits are filled in
2798 */
2799 static void
2800 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2801 enum pipe_format format,
2802 unsigned first_element, unsigned last_element,
2803 uint32_t *state)
2804 {
2805 const struct util_format_description *desc;
2806 int first_non_void;
2807 uint64_t va;
2808 unsigned stride;
2809 unsigned num_records;
2810 unsigned num_format, data_format;
2811
2812 desc = util_format_description(format);
2813 first_non_void = util_format_get_first_non_void_channel(format);
2814 stride = desc->block.bits / 8;
2815 va = buf->gpu_address + first_element * stride;
2816 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2817 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2818
2819 num_records = last_element + 1 - first_element;
2820 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2821
2822 if (screen->b.chip_class >= VI)
2823 num_records *= stride;
2824
2825 state[4] = va;
2826 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2827 S_008F04_STRIDE(stride);
2828 state[6] = num_records;
2829 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2830 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2831 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2832 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2833 S_008F0C_NUM_FORMAT(num_format) |
2834 S_008F0C_DATA_FORMAT(data_format);
2835 }
2836
2837 /**
2838 * Build the sampler view descriptor for a texture.
2839 */
2840 static void
2841 si_make_texture_descriptor(struct si_screen *screen,
2842 struct r600_texture *tex,
2843 enum pipe_texture_target target,
2844 enum pipe_format pipe_format,
2845 const unsigned char state_swizzle[4],
2846 unsigned base_level, unsigned first_level, unsigned last_level,
2847 unsigned first_layer, unsigned last_layer,
2848 unsigned width, unsigned height, unsigned depth,
2849 uint32_t *state,
2850 uint32_t *fmask_state)
2851 {
2852 struct pipe_resource *res = &tex->resource.b.b;
2853 const struct radeon_surf_level *surflevel = tex->surface.level;
2854 const struct util_format_description *desc;
2855 unsigned char swizzle[4];
2856 int first_non_void;
2857 unsigned num_format, data_format;
2858 uint32_t pitch;
2859 uint64_t va;
2860
2861 /* Texturing with separate depth and stencil. */
2862 if (tex->is_depth && !tex->is_flushing_texture) {
2863 switch (pipe_format) {
2864 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2865 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2866 break;
2867 case PIPE_FORMAT_X8Z24_UNORM:
2868 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2869 /* Z24 is always stored like this. */
2870 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2871 break;
2872 case PIPE_FORMAT_X24S8_UINT:
2873 case PIPE_FORMAT_S8X24_UINT:
2874 case PIPE_FORMAT_X32_S8X24_UINT:
2875 pipe_format = PIPE_FORMAT_S8_UINT;
2876 surflevel = tex->surface.stencil_level;
2877 break;
2878 default:;
2879 }
2880 }
2881
2882 desc = util_format_description(pipe_format);
2883
2884 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2885 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2886 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2887
2888 switch (pipe_format) {
2889 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2890 case PIPE_FORMAT_X24S8_UINT:
2891 case PIPE_FORMAT_X32_S8X24_UINT:
2892 case PIPE_FORMAT_X8Z24_UNORM:
2893 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2894 break;
2895 default:
2896 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2897 }
2898 } else {
2899 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2900 }
2901
2902 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2903
2904 switch (pipe_format) {
2905 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2906 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2907 break;
2908 default:
2909 if (first_non_void < 0) {
2910 if (util_format_is_compressed(pipe_format)) {
2911 switch (pipe_format) {
2912 case PIPE_FORMAT_DXT1_SRGB:
2913 case PIPE_FORMAT_DXT1_SRGBA:
2914 case PIPE_FORMAT_DXT3_SRGBA:
2915 case PIPE_FORMAT_DXT5_SRGBA:
2916 case PIPE_FORMAT_BPTC_SRGBA:
2917 case PIPE_FORMAT_ETC2_SRGB8:
2918 case PIPE_FORMAT_ETC2_SRGB8A1:
2919 case PIPE_FORMAT_ETC2_SRGBA8:
2920 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2921 break;
2922 case PIPE_FORMAT_RGTC1_SNORM:
2923 case PIPE_FORMAT_LATC1_SNORM:
2924 case PIPE_FORMAT_RGTC2_SNORM:
2925 case PIPE_FORMAT_LATC2_SNORM:
2926 case PIPE_FORMAT_ETC2_R11_SNORM:
2927 case PIPE_FORMAT_ETC2_RG11_SNORM:
2928 /* implies float, so use SNORM/UNORM to determine
2929 whether data is signed or not */
2930 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2931 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2932 break;
2933 default:
2934 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2935 break;
2936 }
2937 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2938 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2939 } else {
2940 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2941 }
2942 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2943 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2944 } else {
2945 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2946
2947 switch (desc->channel[first_non_void].type) {
2948 case UTIL_FORMAT_TYPE_FLOAT:
2949 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2950 break;
2951 case UTIL_FORMAT_TYPE_SIGNED:
2952 if (desc->channel[first_non_void].normalized)
2953 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2954 else if (desc->channel[first_non_void].pure_integer)
2955 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2956 else
2957 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2958 break;
2959 case UTIL_FORMAT_TYPE_UNSIGNED:
2960 if (desc->channel[first_non_void].normalized)
2961 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2962 else if (desc->channel[first_non_void].pure_integer)
2963 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2964 else
2965 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2966 }
2967 }
2968 }
2969
2970 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2971 if (data_format == ~0) {
2972 data_format = 0;
2973 }
2974
2975 if (res->target == PIPE_TEXTURE_1D_ARRAY) {
2976 height = 1;
2977 depth = res->array_size;
2978 } else if (res->target == PIPE_TEXTURE_2D_ARRAY) {
2979 depth = res->array_size;
2980 } else if (res->target == PIPE_TEXTURE_CUBE_ARRAY)
2981 depth = res->array_size / 6;
2982
2983 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2984 va = tex->resource.gpu_address + surflevel[base_level].offset;
2985
2986 state[0] = va >> 8;
2987 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2988 S_008F14_DATA_FORMAT(data_format) |
2989 S_008F14_NUM_FORMAT(num_format));
2990 state[2] = (S_008F18_WIDTH(width - 1) |
2991 S_008F18_HEIGHT(height - 1));
2992 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2993 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2994 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2995 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2996 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2997 0 : first_level) |
2998 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2999 util_logbase2(res->nr_samples) :
3000 last_level) |
3001 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
3002 S_008F1C_POW2_PAD(res->last_level > 0) |
3003 S_008F1C_TYPE(si_tex_dim(res->target, target, res->nr_samples)));
3004 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
3005 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
3006 S_008F24_LAST_ARRAY(last_layer));
3007
3008 if (tex->dcc_offset) {
3009 unsigned swap = r600_translate_colorswap(pipe_format);
3010
3011 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3012 state[7] = (tex->resource.gpu_address +
3013 tex->dcc_offset +
3014 surflevel[base_level].dcc_offset) >> 8;
3015 } else {
3016 state[6] = 0;
3017 state[7] = 0;
3018 }
3019
3020 /* Initialize the sampler view for FMASK. */
3021 if (tex->fmask.size) {
3022 uint32_t fmask_format;
3023
3024 va = tex->resource.gpu_address + tex->fmask.offset;
3025
3026 switch (res->nr_samples) {
3027 case 2:
3028 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3029 break;
3030 case 4:
3031 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3032 break;
3033 case 8:
3034 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3035 break;
3036 default:
3037 assert(0);
3038 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3039 }
3040
3041 fmask_state[0] = va >> 8;
3042 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3043 S_008F14_DATA_FORMAT(fmask_format) |
3044 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3045 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3046 S_008F18_HEIGHT(height - 1);
3047 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3048 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3049 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3050 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3051 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3052 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3053 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3054 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3055 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3056 S_008F24_LAST_ARRAY(last_layer);
3057 fmask_state[6] = 0;
3058 fmask_state[7] = 0;
3059 }
3060 }
3061
3062 /**
3063 * Create a sampler view.
3064 *
3065 * @param ctx context
3066 * @param texture texture
3067 * @param state sampler view template
3068 * @param width0 width0 override (for compressed textures as int)
3069 * @param height0 height0 override (for compressed textures as int)
3070 * @param force_level set the base address to the level (for compressed textures)
3071 */
3072 struct pipe_sampler_view *
3073 si_create_sampler_view_custom(struct pipe_context *ctx,
3074 struct pipe_resource *texture,
3075 const struct pipe_sampler_view *state,
3076 unsigned width0, unsigned height0,
3077 unsigned force_level)
3078 {
3079 struct si_context *sctx = (struct si_context*)ctx;
3080 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3081 struct r600_texture *tmp = (struct r600_texture*)texture;
3082 unsigned base_level, first_level, last_level;
3083 unsigned char state_swizzle[4];
3084 unsigned height, depth, width;
3085 unsigned last_layer = state->u.tex.last_layer;
3086
3087 if (!view)
3088 return NULL;
3089
3090 /* initialize base object */
3091 view->base = *state;
3092 view->base.texture = NULL;
3093 view->base.reference.count = 1;
3094 view->base.context = ctx;
3095
3096 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3097 if (!texture) {
3098 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3099 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3100 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3101 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3102 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3103 return &view->base;
3104 }
3105
3106 pipe_resource_reference(&view->base.texture, texture);
3107
3108 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3109 state->format == PIPE_FORMAT_S8X24_UINT ||
3110 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3111 state->format == PIPE_FORMAT_S8_UINT)
3112 view->is_stencil_sampler = true;
3113
3114 /* Buffer resource. */
3115 if (texture->target == PIPE_BUFFER) {
3116 si_make_buffer_descriptor(sctx->screen,
3117 (struct r600_resource *)texture,
3118 state->format,
3119 state->u.buf.first_element,
3120 state->u.buf.last_element,
3121 view->state);
3122
3123 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3124 return &view->base;
3125 }
3126
3127 state_swizzle[0] = state->swizzle_r;
3128 state_swizzle[1] = state->swizzle_g;
3129 state_swizzle[2] = state->swizzle_b;
3130 state_swizzle[3] = state->swizzle_a;
3131
3132 base_level = 0;
3133 first_level = state->u.tex.first_level;
3134 last_level = state->u.tex.last_level;
3135 width = width0;
3136 height = height0;
3137 depth = texture->depth0;
3138
3139 if (force_level) {
3140 assert(force_level == first_level &&
3141 force_level == last_level);
3142 base_level = force_level;
3143 first_level = 0;
3144 last_level = 0;
3145 width = u_minify(width, force_level);
3146 height = u_minify(height, force_level);
3147 depth = u_minify(depth, force_level);
3148 }
3149
3150 /* This is not needed if state trackers set last_layer correctly. */
3151 if (state->target == PIPE_TEXTURE_1D ||
3152 state->target == PIPE_TEXTURE_2D ||
3153 state->target == PIPE_TEXTURE_RECT ||
3154 state->target == PIPE_TEXTURE_CUBE)
3155 last_layer = state->u.tex.first_layer;
3156
3157 si_make_texture_descriptor(sctx->screen, tmp, state->target,
3158 state->format, state_swizzle,
3159 base_level, first_level, last_level,
3160 state->u.tex.first_layer, last_layer,
3161 width, height, depth,
3162 view->state, view->fmask_state);
3163
3164 return &view->base;
3165 }
3166
3167 static struct pipe_sampler_view *
3168 si_create_sampler_view(struct pipe_context *ctx,
3169 struct pipe_resource *texture,
3170 const struct pipe_sampler_view *state)
3171 {
3172 return si_create_sampler_view_custom(ctx, texture, state,
3173 texture ? texture->width0 : 0,
3174 texture ? texture->height0 : 0, 0);
3175 }
3176
3177 static void si_sampler_view_destroy(struct pipe_context *ctx,
3178 struct pipe_sampler_view *state)
3179 {
3180 struct si_sampler_view *view = (struct si_sampler_view *)state;
3181
3182 if (state->texture && state->texture->target == PIPE_BUFFER)
3183 LIST_DELINIT(&view->list);
3184
3185 pipe_resource_reference(&state->texture, NULL);
3186 FREE(view);
3187 }
3188
3189 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3190 {
3191 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3192 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3193 (linear_filter &&
3194 (wrap == PIPE_TEX_WRAP_CLAMP ||
3195 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3196 }
3197
3198 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3199 {
3200 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3201 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3202
3203 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3204 state->border_color.ui[2] || state->border_color.ui[3]) &&
3205 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3206 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3207 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3208 }
3209
3210 static void *si_create_sampler_state(struct pipe_context *ctx,
3211 const struct pipe_sampler_state *state)
3212 {
3213 struct si_context *sctx = (struct si_context *)ctx;
3214 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3215 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
3216 unsigned border_color_type, border_color_index = 0;
3217
3218 if (!rstate) {
3219 return NULL;
3220 }
3221
3222 if (!sampler_state_needs_border_color(state))
3223 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3224 else if (state->border_color.f[0] == 0 &&
3225 state->border_color.f[1] == 0 &&
3226 state->border_color.f[2] == 0 &&
3227 state->border_color.f[3] == 0)
3228 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3229 else if (state->border_color.f[0] == 0 &&
3230 state->border_color.f[1] == 0 &&
3231 state->border_color.f[2] == 0 &&
3232 state->border_color.f[3] == 1)
3233 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3234 else if (state->border_color.f[0] == 1 &&
3235 state->border_color.f[1] == 1 &&
3236 state->border_color.f[2] == 1 &&
3237 state->border_color.f[3] == 1)
3238 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3239 else {
3240 int i;
3241
3242 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3243
3244 /* Check if the border has been uploaded already. */
3245 for (i = 0; i < sctx->border_color_count; i++)
3246 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3247 sizeof(state->border_color)) == 0)
3248 break;
3249
3250 if (i >= SI_MAX_BORDER_COLORS) {
3251 /* Getting 4096 unique border colors is very unlikely. */
3252 fprintf(stderr, "radeonsi: The border color table is full. "
3253 "Any new border colors will be just black. "
3254 "Please file a bug.\n");
3255 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3256 } else {
3257 if (i == sctx->border_color_count) {
3258 /* Upload a new border color. */
3259 memcpy(&sctx->border_color_table[i], &state->border_color,
3260 sizeof(state->border_color));
3261 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3262 &state->border_color,
3263 sizeof(state->border_color));
3264 sctx->border_color_count++;
3265 }
3266
3267 border_color_index = i;
3268 }
3269 }
3270
3271 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3272 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3273 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3274 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
3275 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3276 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3277 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
3278 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3279 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3280 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3281 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
3282 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
3283 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
3284 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3285 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3286 return rstate;
3287 }
3288
3289 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3290 {
3291 struct si_context *sctx = (struct si_context *)ctx;
3292
3293 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3294 return;
3295
3296 sctx->sample_mask.sample_mask = sample_mask;
3297 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3298 }
3299
3300 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3301 {
3302 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3303 unsigned mask = sctx->sample_mask.sample_mask;
3304
3305 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3306 radeon_emit(cs, mask | (mask << 16));
3307 radeon_emit(cs, mask | (mask << 16));
3308 }
3309
3310 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3311 {
3312 free(state);
3313 }
3314
3315 /*
3316 * Vertex elements & buffers
3317 */
3318
3319 static void *si_create_vertex_elements(struct pipe_context *ctx,
3320 unsigned count,
3321 const struct pipe_vertex_element *elements)
3322 {
3323 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3324 int i;
3325
3326 assert(count < SI_MAX_ATTRIBS);
3327 if (!v)
3328 return NULL;
3329
3330 v->count = count;
3331 for (i = 0; i < count; ++i) {
3332 const struct util_format_description *desc;
3333 unsigned data_format, num_format;
3334 int first_non_void;
3335
3336 desc = util_format_description(elements[i].src_format);
3337 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3338 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3339 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3340
3341 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3342 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3343 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3344 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3345 S_008F0C_NUM_FORMAT(num_format) |
3346 S_008F0C_DATA_FORMAT(data_format);
3347 v->format_size[i] = desc->block.bits / 8;
3348 }
3349 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3350
3351 return v;
3352 }
3353
3354 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3355 {
3356 struct si_context *sctx = (struct si_context *)ctx;
3357 struct si_vertex_element *v = (struct si_vertex_element*)state;
3358
3359 sctx->vertex_elements = v;
3360 sctx->vertex_buffers_dirty = true;
3361 }
3362
3363 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3364 {
3365 struct si_context *sctx = (struct si_context *)ctx;
3366
3367 if (sctx->vertex_elements == state)
3368 sctx->vertex_elements = NULL;
3369 FREE(state);
3370 }
3371
3372 static void si_set_vertex_buffers(struct pipe_context *ctx,
3373 unsigned start_slot, unsigned count,
3374 const struct pipe_vertex_buffer *buffers)
3375 {
3376 struct si_context *sctx = (struct si_context *)ctx;
3377 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3378 int i;
3379
3380 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3381
3382 if (buffers) {
3383 for (i = 0; i < count; i++) {
3384 const struct pipe_vertex_buffer *src = buffers + i;
3385 struct pipe_vertex_buffer *dsti = dst + i;
3386
3387 pipe_resource_reference(&dsti->buffer, src->buffer);
3388 dsti->buffer_offset = src->buffer_offset;
3389 dsti->stride = src->stride;
3390 r600_context_add_resource_size(ctx, src->buffer);
3391 }
3392 } else {
3393 for (i = 0; i < count; i++) {
3394 pipe_resource_reference(&dst[i].buffer, NULL);
3395 }
3396 }
3397 sctx->vertex_buffers_dirty = true;
3398 }
3399
3400 static void si_set_index_buffer(struct pipe_context *ctx,
3401 const struct pipe_index_buffer *ib)
3402 {
3403 struct si_context *sctx = (struct si_context *)ctx;
3404
3405 if (ib) {
3406 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3407 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3408 r600_context_add_resource_size(ctx, ib->buffer);
3409 } else {
3410 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3411 }
3412 }
3413
3414 /*
3415 * Misc
3416 */
3417 static void si_set_polygon_stipple(struct pipe_context *ctx,
3418 const struct pipe_poly_stipple *state)
3419 {
3420 struct si_context *sctx = (struct si_context *)ctx;
3421 struct pipe_resource *tex;
3422 struct pipe_sampler_view *view;
3423 bool is_zero = true;
3424 bool is_one = true;
3425 int i;
3426
3427 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3428 * the resource is NULL/invalid. Take advantage of this fact and skip
3429 * texture allocation if the stipple pattern is constant.
3430 *
3431 * This is an optimization for the common case when stippling isn't
3432 * used but set_polygon_stipple is still called by st/mesa.
3433 */
3434 for (i = 0; i < Elements(state->stipple); i++) {
3435 is_zero = is_zero && state->stipple[i] == 0;
3436 is_one = is_one && state->stipple[i] == 0xffffffff;
3437 }
3438
3439 if (is_zero || is_one) {
3440 struct pipe_sampler_view templ = {{0}};
3441
3442 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3443 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3444 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3445 /* The pattern should be inverted in the texture. */
3446 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3447
3448 view = ctx->create_sampler_view(ctx, NULL, &templ);
3449 } else {
3450 /* Create a new texture. */
3451 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3452 if (!tex)
3453 return;
3454
3455 view = util_pstipple_create_sampler_view(ctx, tex);
3456 pipe_resource_reference(&tex, NULL);
3457 }
3458
3459 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3460 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3461 pipe_sampler_view_reference(&view, NULL);
3462
3463 /* Bind the sampler state if needed. */
3464 if (!sctx->pstipple_sampler_state) {
3465 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3466 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3467 SI_POLY_STIPPLE_SAMPLER, 1,
3468 &sctx->pstipple_sampler_state);
3469 }
3470 }
3471
3472 static void si_set_tess_state(struct pipe_context *ctx,
3473 const float default_outer_level[4],
3474 const float default_inner_level[2])
3475 {
3476 struct si_context *sctx = (struct si_context *)ctx;
3477 struct pipe_constant_buffer cb;
3478 float array[8];
3479
3480 memcpy(array, default_outer_level, sizeof(float) * 4);
3481 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3482
3483 cb.buffer = NULL;
3484 cb.user_buffer = NULL;
3485 cb.buffer_size = sizeof(array);
3486
3487 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3488 (void*)array, sizeof(array),
3489 &cb.buffer_offset);
3490
3491 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3492 SI_DRIVER_STATE_CONST_BUF, &cb);
3493 pipe_resource_reference(&cb.buffer, NULL);
3494 }
3495
3496 static void si_texture_barrier(struct pipe_context *ctx)
3497 {
3498 struct si_context *sctx = (struct si_context *)ctx;
3499
3500 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3501 SI_CONTEXT_INV_GLOBAL_L2 |
3502 SI_CONTEXT_FLUSH_AND_INV_CB;
3503 }
3504
3505 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3506 {
3507 struct pipe_blend_state blend;
3508
3509 memset(&blend, 0, sizeof(blend));
3510 blend.independent_blend_enable = true;
3511 blend.rt[0].colormask = 0xf;
3512 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3513 }
3514
3515 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3516 bool include_draw_vbo)
3517 {
3518 si_need_cs_space((struct si_context*)ctx);
3519 }
3520
3521 static void si_init_config(struct si_context *sctx);
3522
3523 void si_init_state_functions(struct si_context *sctx)
3524 {
3525 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3526 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3527 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3528
3529 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3530 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3531 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3532 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3533 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3534 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3535 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3536 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3537 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3538 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3539 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3540 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3541 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3542
3543 sctx->b.b.create_blend_state = si_create_blend_state;
3544 sctx->b.b.bind_blend_state = si_bind_blend_state;
3545 sctx->b.b.delete_blend_state = si_delete_blend_state;
3546 sctx->b.b.set_blend_color = si_set_blend_color;
3547
3548 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3549 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3550 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3551
3552 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3553 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3554 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3555
3556 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3557 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3558 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3559 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3560 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3561
3562 sctx->b.b.set_clip_state = si_set_clip_state;
3563 sctx->b.b.set_scissor_states = si_set_scissor_states;
3564 sctx->b.b.set_viewport_states = si_set_viewport_states;
3565 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3566
3567 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3568 sctx->b.b.get_sample_position = cayman_get_sample_position;
3569
3570 sctx->b.b.create_sampler_state = si_create_sampler_state;
3571 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3572
3573 sctx->b.b.create_sampler_view = si_create_sampler_view;
3574 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3575
3576 sctx->b.b.set_sample_mask = si_set_sample_mask;
3577
3578 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3579 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3580 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3581 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3582 sctx->b.b.set_index_buffer = si_set_index_buffer;
3583
3584 sctx->b.b.texture_barrier = si_texture_barrier;
3585 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3586 sctx->b.b.set_min_samples = si_set_min_samples;
3587 sctx->b.b.set_tess_state = si_set_tess_state;
3588
3589 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3590 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3591
3592 sctx->b.b.draw_vbo = si_draw_vbo;
3593
3594 if (sctx->b.chip_class >= CIK) {
3595 sctx->b.dma_copy = cik_sdma_copy;
3596 } else {
3597 sctx->b.dma_copy = si_dma_copy;
3598 }
3599
3600 si_init_config(sctx);
3601 }
3602
3603 static void
3604 si_write_harvested_raster_configs(struct si_context *sctx,
3605 struct si_pm4_state *pm4,
3606 unsigned raster_config,
3607 unsigned raster_config_1)
3608 {
3609 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3610 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3611 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3612 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3613 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3614 unsigned rb_per_se = num_rb / num_se;
3615 unsigned se_mask[4];
3616 unsigned se;
3617
3618 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3619 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3620 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3621 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3622
3623 assert(num_se == 1 || num_se == 2 || num_se == 4);
3624 assert(sh_per_se == 1 || sh_per_se == 2);
3625 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3626
3627 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3628 * fields are for, so I'm leaving them as their default
3629 * values. */
3630
3631 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3632 (!se_mask[2] && !se_mask[3]))) {
3633 raster_config_1 &= C_028354_SE_PAIR_MAP;
3634
3635 if (!se_mask[0] && !se_mask[1]) {
3636 raster_config_1 |=
3637 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3638 } else {
3639 raster_config_1 |=
3640 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3641 }
3642 }
3643
3644 for (se = 0; se < num_se; se++) {
3645 unsigned raster_config_se = raster_config;
3646 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3647 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3648 int idx = (se / 2) * 2;
3649
3650 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3651 raster_config_se &= C_028350_SE_MAP;
3652
3653 if (!se_mask[idx]) {
3654 raster_config_se |=
3655 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3656 } else {
3657 raster_config_se |=
3658 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3659 }
3660 }
3661
3662 pkr0_mask &= rb_mask;
3663 pkr1_mask &= rb_mask;
3664 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3665 raster_config_se &= C_028350_PKR_MAP;
3666
3667 if (!pkr0_mask) {
3668 raster_config_se |=
3669 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3670 } else {
3671 raster_config_se |=
3672 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3673 }
3674 }
3675
3676 if (rb_per_se >= 2) {
3677 unsigned rb0_mask = 1 << (se * rb_per_se);
3678 unsigned rb1_mask = rb0_mask << 1;
3679
3680 rb0_mask &= rb_mask;
3681 rb1_mask &= rb_mask;
3682 if (!rb0_mask || !rb1_mask) {
3683 raster_config_se &= C_028350_RB_MAP_PKR0;
3684
3685 if (!rb0_mask) {
3686 raster_config_se |=
3687 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3688 } else {
3689 raster_config_se |=
3690 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3691 }
3692 }
3693
3694 if (rb_per_se > 2) {
3695 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3696 rb1_mask = rb0_mask << 1;
3697 rb0_mask &= rb_mask;
3698 rb1_mask &= rb_mask;
3699 if (!rb0_mask || !rb1_mask) {
3700 raster_config_se &= C_028350_RB_MAP_PKR1;
3701
3702 if (!rb0_mask) {
3703 raster_config_se |=
3704 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3705 } else {
3706 raster_config_se |=
3707 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3708 }
3709 }
3710 }
3711 }
3712
3713 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3714 if (sctx->b.chip_class < CIK)
3715 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3716 SE_INDEX(se) | SH_BROADCAST_WRITES |
3717 INSTANCE_BROADCAST_WRITES);
3718 else
3719 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3720 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3721 S_030800_INSTANCE_BROADCAST_WRITES(1));
3722 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3723 if (sctx->b.chip_class >= CIK)
3724 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3725 }
3726
3727 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3728 if (sctx->b.chip_class < CIK)
3729 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3730 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3731 INSTANCE_BROADCAST_WRITES);
3732 else
3733 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3734 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3735 S_030800_INSTANCE_BROADCAST_WRITES(1));
3736 }
3737
3738 static void si_init_config(struct si_context *sctx)
3739 {
3740 struct si_screen *sscreen = sctx->screen;
3741 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3742 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3743 unsigned raster_config, raster_config_1;
3744 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3745 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3746 int i;
3747
3748 if (!pm4)
3749 return;
3750
3751 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3752 si_pm4_cmd_add(pm4, 0x80000000);
3753 si_pm4_cmd_add(pm4, 0x80000000);
3754 si_pm4_cmd_end(pm4, false);
3755
3756 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3757 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3758
3759 /* FIXME calculate these values somehow ??? */
3760 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3761 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3762 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3763
3764 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3765 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3766
3767 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3768 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3769 if (sctx->b.chip_class < CIK)
3770 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3771 S_008A14_CLIP_VTX_REORDER_ENA(1));
3772
3773 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3774 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3775
3776 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3777
3778 for (i = 0; i < 16; i++) {
3779 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3780 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3781 }
3782
3783 switch (sctx->screen->b.family) {
3784 case CHIP_TAHITI:
3785 case CHIP_PITCAIRN:
3786 raster_config = 0x2a00126a;
3787 raster_config_1 = 0x00000000;
3788 break;
3789 case CHIP_VERDE:
3790 raster_config = 0x0000124a;
3791 raster_config_1 = 0x00000000;
3792 break;
3793 case CHIP_OLAND:
3794 raster_config = 0x00000082;
3795 raster_config_1 = 0x00000000;
3796 break;
3797 case CHIP_HAINAN:
3798 raster_config = 0x00000000;
3799 raster_config_1 = 0x00000000;
3800 break;
3801 case CHIP_BONAIRE:
3802 raster_config = 0x16000012;
3803 raster_config_1 = 0x00000000;
3804 break;
3805 case CHIP_HAWAII:
3806 raster_config = 0x3a00161a;
3807 raster_config_1 = 0x0000002e;
3808 break;
3809 case CHIP_FIJI:
3810 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3811 /* old kernels with old tiling config */
3812 raster_config = 0x16000012;
3813 raster_config_1 = 0x0000002a;
3814 } else {
3815 raster_config = 0x3a00161a;
3816 raster_config_1 = 0x0000002e;
3817 }
3818 break;
3819 case CHIP_TONGA:
3820 raster_config = 0x16000012;
3821 raster_config_1 = 0x0000002a;
3822 break;
3823 case CHIP_ICELAND:
3824 raster_config = 0x00000002;
3825 raster_config_1 = 0x00000000;
3826 break;
3827 case CHIP_CARRIZO:
3828 raster_config = 0x00000002;
3829 raster_config_1 = 0x00000000;
3830 break;
3831 case CHIP_KAVERI:
3832 /* KV should be 0x00000002, but that causes problems with radeon */
3833 raster_config = 0x00000000; /* 0x00000002 */
3834 raster_config_1 = 0x00000000;
3835 break;
3836 case CHIP_KABINI:
3837 case CHIP_MULLINS:
3838 case CHIP_STONEY:
3839 raster_config = 0x00000000;
3840 raster_config_1 = 0x00000000;
3841 break;
3842 default:
3843 fprintf(stderr,
3844 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3845 raster_config = 0x00000000;
3846 raster_config_1 = 0x00000000;
3847 break;
3848 }
3849
3850 /* Always use the default config when all backends are enabled
3851 * (or when we failed to determine the enabled backends).
3852 */
3853 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3854 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3855 raster_config);
3856 if (sctx->b.chip_class >= CIK)
3857 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3858 raster_config_1);
3859 } else {
3860 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3861 }
3862
3863 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3864 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3865 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3866 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3867 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3868 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3869 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3870
3871 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3872 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3873 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3874 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3875 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3876 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3877 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3878 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3879 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3880 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3881 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3882 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3883 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3884 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3885 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3886
3887 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3888 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3889 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3890
3891 if (sctx->b.chip_class >= CIK) {
3892 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3893 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3894 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3895
3896 if (sscreen->b.info.num_good_compute_units /
3897 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3898 /* Too few available compute units per SH. Disallowing
3899 * VS to run on CU0 could hurt us more than late VS
3900 * allocation would help.
3901 *
3902 * LATE_ALLOC_VS = 2 is the highest safe number.
3903 */
3904 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3905 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3906 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3907 } else {
3908 /* Set LATE_ALLOC_VS == 31. It should be less than
3909 * the number of scratch waves. Limitations:
3910 * - VS can't execute on CU0.
3911 * - If HS writes outputs to LDS, LS can't execute on CU0.
3912 */
3913 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3914 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3915 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3916 }
3917
3918 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3919 }
3920
3921 if (sctx->b.chip_class >= VI) {
3922 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3923 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3924 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3925 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3926 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3927 }
3928
3929 if (sctx->b.family == CHIP_STONEY)
3930 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3931
3932 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3933 if (sctx->b.chip_class >= CIK)
3934 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3935 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3936 RADEON_PRIO_BORDER_COLORS);
3937
3938 si_pm4_upload_indirect_buffer(sctx, pm4);
3939 sctx->init_config = pm4;
3940 }