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[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef SI_STATE_H
26 #define SI_STATE_H
27
28 #include "si_pm4.h"
29
30 #include "pipebuffer/pb_slab.h"
31 #include "util/u_blitter.h"
32
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
35
36 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
37 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
38 #define SI_NUM_CONST_BUFFERS 16
39 #define SI_NUM_IMAGES 16
40 #define SI_NUM_SHADER_BUFFERS 16
41
42 struct si_screen;
43 struct si_shader;
44 struct si_shader_selector;
45 struct si_texture;
46 struct si_qbo_state;
47
48 struct si_state_blend {
49 struct si_pm4_state pm4;
50 uint32_t cb_target_mask;
51 /* Set 0xf or 0x0 (4 bits) per render target if the following is
52 * true. ANDed with spi_shader_col_format.
53 */
54 unsigned cb_target_enabled_4bit;
55 unsigned blend_enable_4bit;
56 unsigned need_src_alpha_4bit;
57 unsigned commutative_4bit;
58 bool alpha_to_coverage:1;
59 bool alpha_to_one:1;
60 bool dual_src_blend:1;
61 bool logicop_enable:1;
62 };
63
64 struct si_state_rasterizer {
65 struct si_pm4_state pm4;
66 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
67 struct si_pm4_state *pm4_poly_offset;
68 unsigned pa_sc_line_stipple;
69 unsigned pa_cl_clip_cntl;
70 float line_width;
71 float max_point_size;
72 unsigned sprite_coord_enable:8;
73 unsigned clip_plane_enable:8;
74 unsigned half_pixel_center:1;
75 unsigned flatshade:1;
76 unsigned two_side:1;
77 unsigned multisample_enable:1;
78 unsigned force_persample_interp:1;
79 unsigned line_stipple_enable:1;
80 unsigned poly_stipple_enable:1;
81 unsigned line_smooth:1;
82 unsigned poly_smooth:1;
83 unsigned uses_poly_offset:1;
84 unsigned clamp_fragment_color:1;
85 unsigned clamp_vertex_color:1;
86 unsigned rasterizer_discard:1;
87 unsigned scissor_enable:1;
88 unsigned clip_halfz:1;
89 };
90
91 struct si_dsa_stencil_ref_part {
92 uint8_t valuemask[2];
93 uint8_t writemask[2];
94 };
95
96 struct si_dsa_order_invariance {
97 /** Whether the final result in Z/S buffers is guaranteed to be
98 * invariant under changes to the order in which fragments arrive. */
99 bool zs:1;
100
101 /** Whether the set of fragments that pass the combined Z/S test is
102 * guaranteed to be invariant under changes to the order in which
103 * fragments arrive. */
104 bool pass_set:1;
105
106 /** Whether the last fragment that passes the combined Z/S test at each
107 * sample is guaranteed to be invariant under changes to the order in
108 * which fragments arrive. */
109 bool pass_last:1;
110 };
111
112 struct si_state_dsa {
113 struct si_pm4_state pm4;
114 struct si_dsa_stencil_ref_part stencil_ref;
115
116 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
117 struct si_dsa_order_invariance order_invariance[2];
118
119 ubyte alpha_func:3;
120 bool depth_enabled:1;
121 bool depth_write_enabled:1;
122 bool stencil_enabled:1;
123 bool stencil_write_enabled:1;
124 bool db_can_write:1;
125
126 };
127
128 struct si_stencil_ref {
129 struct pipe_stencil_ref state;
130 struct si_dsa_stencil_ref_part dsa_part;
131 };
132
133 struct si_vertex_elements
134 {
135 struct si_resource *instance_divisor_factor_buffer;
136 uint32_t rsrc_word3[SI_MAX_ATTRIBS];
137 uint16_t src_offset[SI_MAX_ATTRIBS];
138 uint8_t fix_fetch[SI_MAX_ATTRIBS];
139 uint8_t format_size[SI_MAX_ATTRIBS];
140 uint8_t vertex_buffer_index[SI_MAX_ATTRIBS];
141
142 /* Bitmask of elements that always need a fixup to be applied. */
143 uint16_t fix_fetch_always;
144
145 /* Bitmask of elements whose fetch should always be opencoded. */
146 uint16_t fix_fetch_opencode;
147
148 /* Bitmask of elements which need to be opencoded if the vertex buffer
149 * is unaligned. */
150 uint16_t fix_fetch_unaligned;
151
152 /* For elements in fix_fetch_unaligned: whether the effective
153 * element load size as seen by the hardware is a dword (as opposed
154 * to a short).
155 */
156 uint16_t hw_load_is_dword;
157
158 /* Bitmask of vertex buffers requiring alignment check */
159 uint16_t vb_alignment_check_mask;
160
161 uint8_t count;
162 bool uses_instance_divisors;
163
164 uint16_t first_vb_use_mask;
165 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
166 uint16_t desc_list_byte_size;
167 uint16_t instance_divisor_is_one; /* bitmask of inputs */
168 uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
169 };
170
171 union si_state {
172 struct {
173 struct si_state_blend *blend;
174 struct si_state_rasterizer *rasterizer;
175 struct si_state_dsa *dsa;
176 struct si_pm4_state *poly_offset;
177 struct si_pm4_state *ls;
178 struct si_pm4_state *hs;
179 struct si_pm4_state *es;
180 struct si_pm4_state *gs;
181 struct si_pm4_state *vgt_shader_config;
182 struct si_pm4_state *vs;
183 struct si_pm4_state *ps;
184 } named;
185 struct si_pm4_state *array[0];
186 };
187
188 #define SI_STATE_IDX(name) \
189 (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
190 #define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
191 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
192
193 static inline unsigned si_states_that_always_roll_context(void)
194 {
195 return (SI_STATE_BIT(blend) |
196 SI_STATE_BIT(rasterizer) |
197 SI_STATE_BIT(dsa) |
198 SI_STATE_BIT(poly_offset) |
199 SI_STATE_BIT(vgt_shader_config));
200 }
201
202 union si_state_atoms {
203 struct {
204 /* The order matters. */
205 struct si_atom render_cond;
206 struct si_atom streamout_begin;
207 struct si_atom streamout_enable; /* must be after streamout_begin */
208 struct si_atom framebuffer;
209 struct si_atom msaa_sample_locs;
210 struct si_atom db_render_state;
211 struct si_atom dpbb_state;
212 struct si_atom msaa_config;
213 struct si_atom sample_mask;
214 struct si_atom cb_render_state;
215 struct si_atom blend_color;
216 struct si_atom clip_regs;
217 struct si_atom clip_state;
218 struct si_atom shader_pointers;
219 struct si_atom guardband;
220 struct si_atom scissors;
221 struct si_atom viewports;
222 struct si_atom stencil_ref;
223 struct si_atom spi_map;
224 struct si_atom scratch_state;
225 struct si_atom window_rectangles;
226 } s;
227 struct si_atom array[0];
228 };
229
230 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / \
231 sizeof(struct si_atom)))
232 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
233
234 static inline unsigned si_atoms_that_always_roll_context(void)
235 {
236 return (SI_ATOM_BIT(streamout_begin) |
237 SI_ATOM_BIT(streamout_enable) |
238 SI_ATOM_BIT(framebuffer) |
239 SI_ATOM_BIT(msaa_sample_locs) |
240 SI_ATOM_BIT(sample_mask) |
241 SI_ATOM_BIT(blend_color) |
242 SI_ATOM_BIT(clip_state) |
243 SI_ATOM_BIT(scissors) |
244 SI_ATOM_BIT(viewports) |
245 SI_ATOM_BIT(stencil_ref) |
246 SI_ATOM_BIT(scratch_state) |
247 SI_ATOM_BIT(window_rectangles));
248 }
249
250 struct si_shader_data {
251 uint32_t sh_base[SI_NUM_SHADERS];
252 };
253
254 /* The list of registers whose emitted values are remembered by si_context. */
255 enum si_tracked_reg {
256 SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
257 SI_TRACKED_DB_COUNT_CONTROL,
258
259 SI_TRACKED_DB_RENDER_OVERRIDE2,
260 SI_TRACKED_DB_SHADER_CONTROL,
261
262 SI_TRACKED_CB_TARGET_MASK,
263 SI_TRACKED_CB_DCC_CONTROL,
264
265 SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
266 SI_TRACKED_SX_BLEND_OPT_EPSILON,
267 SI_TRACKED_SX_BLEND_OPT_CONTROL,
268
269 SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */
270 SI_TRACKED_PA_SC_AA_CONFIG,
271
272 SI_TRACKED_DB_EQAA,
273 SI_TRACKED_PA_SC_MODE_CNTL_1,
274
275 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
276 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
277
278 SI_TRACKED_PA_CL_VS_OUT_CNTL,
279 SI_TRACKED_PA_CL_CLIP_CNTL,
280
281 SI_TRACKED_PA_SC_BINNER_CNTL_0,
282 SI_TRACKED_DB_DFSM_CONTROL,
283
284 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
285 SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
286 SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
287 SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
288
289 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
290 SI_TRACKED_PA_SU_VTX_CNTL,
291
292 SI_TRACKED_PA_SC_CLIPRECT_RULE,
293
294 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
295
296 SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 4 consecutive registers */
297 SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
298 SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
299 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE,
300
301 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
302 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
303
304 SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */
305 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
306 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
307 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
308
309 SI_TRACKED_VGT_GS_INSTANCE_CNT,
310 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
311 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
312 SI_TRACKED_VGT_GS_MODE,
313 SI_TRACKED_VGT_PRIMITIVEID_EN,
314 SI_TRACKED_VGT_REUSE_OFF,
315 SI_TRACKED_SPI_VS_OUT_CONFIG,
316 SI_TRACKED_SPI_SHADER_POS_FORMAT,
317 SI_TRACKED_PA_CL_VTE_CNTL,
318
319 SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
320 SI_TRACKED_SPI_PS_INPUT_ADDR,
321
322 SI_TRACKED_SPI_BARYC_CNTL,
323 SI_TRACKED_SPI_PS_IN_CONTROL,
324
325 SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */
326 SI_TRACKED_SPI_SHADER_COL_FORMAT,
327
328 SI_TRACKED_CB_SHADER_MASK,
329 SI_TRACKED_VGT_TF_PARAM,
330 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
331
332 SI_NUM_TRACKED_REGS,
333 };
334
335 struct si_tracked_regs {
336 uint64_t reg_saved;
337 uint32_t reg_value[SI_NUM_TRACKED_REGS];
338 uint32_t spi_ps_input_cntl[32];
339 };
340
341 /* Private read-write buffer slots. */
342 enum {
343 SI_ES_RING_ESGS,
344 SI_GS_RING_ESGS,
345
346 SI_RING_GSVS,
347
348 SI_VS_STREAMOUT_BUF0,
349 SI_VS_STREAMOUT_BUF1,
350 SI_VS_STREAMOUT_BUF2,
351 SI_VS_STREAMOUT_BUF3,
352
353 SI_HS_CONST_DEFAULT_TESS_LEVELS,
354 SI_VS_CONST_INSTANCE_DIVISORS,
355 SI_VS_CONST_CLIP_PLANES,
356 SI_PS_CONST_POLY_STIPPLE,
357 SI_PS_CONST_SAMPLE_POSITIONS,
358
359 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
360 SI_PS_IMAGE_COLORBUF0,
361 SI_PS_IMAGE_COLORBUF0_HI,
362 SI_PS_IMAGE_COLORBUF0_FMASK,
363 SI_PS_IMAGE_COLORBUF0_FMASK_HI,
364
365 SI_NUM_RW_BUFFERS,
366 };
367
368 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
369 * are contiguous:
370 *
371 * 0 - rw buffers
372 * 1 - vertex const and shader buffers
373 * 2 - vertex samplers and images
374 * 3 - fragment const and shader buffer
375 * ...
376 * 11 - compute const and shader buffers
377 * 12 - compute samplers and images
378 */
379 enum {
380 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
381 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
382 SI_NUM_SHADER_DESCS,
383 };
384
385 #define SI_DESCS_RW_BUFFERS 0
386 #define SI_DESCS_FIRST_SHADER 1
387 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
388 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
389 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
390 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
391
392 #define SI_DESCS_SHADER_MASK(name) \
393 u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
394 PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
395 SI_NUM_SHADER_DESCS)
396
397 static inline unsigned
398 si_const_and_shader_buffer_descriptors_idx(unsigned shader)
399 {
400 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
401 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
402 }
403
404 static inline unsigned
405 si_sampler_and_image_descriptors_idx(unsigned shader)
406 {
407 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
408 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
409 }
410
411 /* This represents descriptors in memory, such as buffer resources,
412 * image resources, and sampler states.
413 */
414 struct si_descriptors {
415 /* The list of descriptors in malloc'd memory. */
416 uint32_t *list;
417 /* The list in mapped GPU memory. */
418 uint32_t *gpu_list;
419
420 /* The buffer where the descriptors have been uploaded. */
421 struct si_resource *buffer;
422 uint64_t gpu_address;
423
424 /* The maximum number of descriptors. */
425 uint32_t num_elements;
426
427 /* Slots that are used by currently-bound shaders.
428 * It determines which slots are uploaded.
429 */
430 uint32_t first_active_slot;
431 uint32_t num_active_slots;
432
433 /* The SH register offset relative to USER_DATA*_0 where the pointer
434 * to the descriptor array will be stored. */
435 short shader_userdata_offset;
436 /* The size of one descriptor. */
437 ubyte element_dw_size;
438 /* If there is only one slot enabled, bind it directly instead of
439 * uploading descriptors. -1 if disabled. */
440 signed char slot_index_to_bind_directly;
441 };
442
443 struct si_buffer_resources {
444 struct pipe_resource **buffers; /* this has num_buffers elements */
445
446 enum radeon_bo_priority priority:6;
447 enum radeon_bo_priority priority_constbuf:6;
448
449 /* The i-th bit is set if that element is enabled (non-NULL resource). */
450 unsigned enabled_mask;
451 unsigned writable_mask;
452 };
453
454 #define si_pm4_state_changed(sctx, member) \
455 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
456
457 #define si_pm4_state_enabled_and_changed(sctx, member) \
458 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
459
460 #define si_pm4_bind_state(sctx, member, value) \
461 do { \
462 (sctx)->queued.named.member = (value); \
463 (sctx)->dirty_states |= SI_STATE_BIT(member); \
464 } while(0)
465
466 #define si_pm4_delete_state(sctx, member, value) \
467 do { \
468 if ((sctx)->queued.named.member == (value)) { \
469 (sctx)->queued.named.member = NULL; \
470 } \
471 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
472 SI_STATE_IDX(member)); \
473 } while(0)
474
475 /* si_descriptors.c */
476 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
477 struct si_texture *tex,
478 const struct legacy_surf_level *base_level_info,
479 unsigned base_level, unsigned first_level,
480 unsigned block_width, bool is_stencil,
481 uint32_t *state);
482 void si_update_ps_colorbuf0_slot(struct si_context *sctx);
483 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
484 uint slot, struct pipe_constant_buffer *cbuf);
485 void si_get_shader_buffers(struct si_context *sctx,
486 enum pipe_shader_type shader,
487 uint start_slot, uint count,
488 struct pipe_shader_buffer *sbuf);
489 void si_set_ring_buffer(struct si_context *sctx, uint slot,
490 struct pipe_resource *buffer,
491 unsigned stride, unsigned num_records,
492 bool add_tid, bool swizzle,
493 unsigned element_size, unsigned index_stride, uint64_t offset);
494 void si_init_all_descriptors(struct si_context *sctx);
495 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
496 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
497 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
498 void si_release_all_descriptors(struct si_context *sctx);
499 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx);
500 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
501 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
502 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf,
503 const uint8_t *ptr, unsigned size, uint32_t *const_offset);
504 void si_update_all_texture_descriptors(struct si_context *sctx);
505 void si_shader_change_notify(struct si_context *sctx);
506 void si_update_needs_color_decompress_masks(struct si_context *sctx);
507 void si_emit_graphics_shader_pointers(struct si_context *sctx);
508 void si_emit_compute_shader_pointers(struct si_context *sctx);
509 void si_set_rw_buffer(struct si_context *sctx,
510 uint slot, const struct pipe_constant_buffer *input);
511 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
512 const struct pipe_shader_buffer *sbuffer);
513 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
514 uint64_t new_active_mask);
515 void si_set_active_descriptors_for_shader(struct si_context *sctx,
516 struct si_shader_selector *sel);
517 bool si_bindless_descriptor_can_reclaim_slab(void *priv,
518 struct pb_slab_entry *entry);
519 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
520 unsigned entry_size,
521 unsigned group_index);
522 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
523 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
524 uint64_t old_va);
525 /* si_state.c */
526 void si_init_state_compute_functions(struct si_context *sctx);
527 void si_init_state_functions(struct si_context *sctx);
528 void si_init_screen_state_functions(struct si_screen *sscreen);
529 void
530 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
531 enum pipe_format format,
532 unsigned offset, unsigned size,
533 uint32_t *state);
534 void
535 si_make_texture_descriptor(struct si_screen *screen,
536 struct si_texture *tex,
537 bool sampler,
538 enum pipe_texture_target target,
539 enum pipe_format pipe_format,
540 const unsigned char state_swizzle[4],
541 unsigned first_level, unsigned last_level,
542 unsigned first_layer, unsigned last_layer,
543 unsigned width, unsigned height, unsigned depth,
544 uint32_t *state,
545 uint32_t *fmask_state);
546 struct pipe_sampler_view *
547 si_create_sampler_view_custom(struct pipe_context *ctx,
548 struct pipe_resource *texture,
549 const struct pipe_sampler_view *state,
550 unsigned width0, unsigned height0,
551 unsigned force_level);
552 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
553 void si_update_ps_iter_samples(struct si_context *sctx);
554 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
555 void si_set_occlusion_query_state(struct si_context *sctx,
556 bool old_perfect_enable);
557
558 /* si_state_binning.c */
559 void si_emit_dpbb_state(struct si_context *sctx);
560
561 /* si_state_shaders.c */
562 void *si_get_ir_binary(struct si_shader_selector *sel);
563 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
564 struct si_shader *shader);
565 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
566 struct si_shader *shader,
567 bool insert_into_disk_cache);
568 bool si_update_shaders(struct si_context *sctx);
569 void si_init_shader_functions(struct si_context *sctx);
570 bool si_init_shader_cache(struct si_screen *sscreen);
571 void si_destroy_shader_cache(struct si_screen *sscreen);
572 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
573 struct util_queue_fence *ready_fence,
574 struct si_compiler_ctx_state *compiler_ctx_state,
575 void *job, util_queue_execute_func execute);
576 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
577 uint32_t *const_and_shader_buffers,
578 uint64_t *samplers_and_images);
579
580 /* si_state_draw.c */
581 void si_emit_cache_flush(struct si_context *sctx);
582 void si_trace_emit(struct si_context *sctx);
583 void si_init_draw_functions(struct si_context *sctx);
584
585 /* si_state_msaa.c */
586 void si_init_msaa_functions(struct si_context *sctx);
587 void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
588
589 /* si_state_streamout.c */
590 void si_streamout_buffers_dirty(struct si_context *sctx);
591 void si_emit_streamout_end(struct si_context *sctx);
592 void si_update_prims_generated_query_state(struct si_context *sctx,
593 unsigned type, int diff);
594 void si_init_streamout_functions(struct si_context *sctx);
595
596
597 static inline unsigned si_get_constbuf_slot(unsigned slot)
598 {
599 /* Constant buffers are in slots [16..31], ascending */
600 return SI_NUM_SHADER_BUFFERS + slot;
601 }
602
603 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
604 {
605 /* shader buffers are in slots [15..0], descending */
606 return SI_NUM_SHADER_BUFFERS - 1 - slot;
607 }
608
609 static inline unsigned si_get_sampler_slot(unsigned slot)
610 {
611 /* samplers are in slots [8..39], ascending */
612 return SI_NUM_IMAGES / 2 + slot;
613 }
614
615 static inline unsigned si_get_image_slot(unsigned slot)
616 {
617 /* images are in slots [15..0] (sampler slots [7..0]), descending */
618 return SI_NUM_IMAGES - 1 - slot;
619 }
620
621 #endif