src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef SI_STATE_H
  26 #define SI_STATE_H
  27
  28 #include "si_pm4.h"
  29
  30 #include "pipebuffer/pb_slab.h"
  31 #include "util/u_blitter.h"
  32
  33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
  34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
  35
  36 #define SI_NUM_VERTEX_BUFFERS           SI_MAX_ATTRIBS
  37 #define SI_NUM_SAMPLERS                 32 /* OpenGL textures units per shader */
  38 #define SI_NUM_CONST_BUFFERS            16
  39 #define SI_NUM_IMAGES                   16
  40 #define SI_NUM_SHADER_BUFFERS           16
  41
  42 struct si_screen;
  43 struct si_shader;
  44 struct si_shader_ctx_state;
  45 struct si_shader_selector;
  46 struct si_texture;
  47 struct si_qbo_state;
  48
  49 struct si_state_blend {
  50         struct si_pm4_state     pm4;
  51         uint32_t                cb_target_mask;
  52         /* Set 0xf or 0x0 (4 bits) per render target if the following is
  53          * true. ANDed with spi_shader_col_format.
  54          */
  55         unsigned                cb_target_enabled_4bit;
  56         unsigned                blend_enable_4bit;
  57         unsigned                need_src_alpha_4bit;
  58         unsigned                commutative_4bit;
  59         bool                    alpha_to_coverage:1;
  60         bool                    alpha_to_one:1;
  61         bool                    dual_src_blend:1;
  62         bool                    logicop_enable:1;
  63 };
  64
  65 struct si_state_rasterizer {
  66         struct si_pm4_state     pm4;
  67         /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
  68         struct si_pm4_state     *pm4_poly_offset;
  69         unsigned                pa_sc_line_stipple;
  70         unsigned                pa_cl_clip_cntl;
  71         float                   line_width;
  72         float                   max_point_size;
  73         unsigned                sprite_coord_enable:8;
  74         unsigned                clip_plane_enable:8;
  75         unsigned                half_pixel_center:1;
  76         unsigned                flatshade:1;
  77         unsigned                two_side:1;
  78         unsigned                multisample_enable:1;
  79         unsigned                force_persample_interp:1;
  80         unsigned                line_stipple_enable:1;
  81         unsigned                poly_stipple_enable:1;
  82         unsigned                line_smooth:1;
  83         unsigned                poly_smooth:1;
  84         unsigned                uses_poly_offset:1;
  85         unsigned                clamp_fragment_color:1;
  86         unsigned                clamp_vertex_color:1;
  87         unsigned                rasterizer_discard:1;
  88         unsigned                scissor_enable:1;
  89         unsigned                clip_halfz:1;
  90 };
  91
  92 struct si_dsa_stencil_ref_part {
  93         uint8_t                 valuemask[2];
  94         uint8_t                 writemask[2];
  95 };
  96
  97 struct si_dsa_order_invariance {
  98         /** Whether the final result in Z/S buffers is guaranteed to be
  99          * invariant under changes to the order in which fragments arrive. */
 100         bool zs:1;
 101
 102         /** Whether the set of fragments that pass the combined Z/S test is
 103          * guaranteed to be invariant under changes to the order in which
 104          * fragments arrive. */
 105         bool pass_set:1;
 106
 107         /** Whether the last fragment that passes the combined Z/S test at each
 108          * sample is guaranteed to be invariant under changes to the order in
 109          * which fragments arrive. */
 110         bool pass_last:1;
 111 };
 112
 113 struct si_state_dsa {
 114         struct si_pm4_state             pm4;
 115         struct si_dsa_stencil_ref_part  stencil_ref;
 116
 117         /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
 118         struct si_dsa_order_invariance  order_invariance[2];
 119
 120         ubyte                           alpha_func:3;
 121         bool                            depth_enabled:1;
 122         bool                            depth_write_enabled:1;
 123         bool                            stencil_enabled:1;
 124         bool                            stencil_write_enabled:1;
 125         bool                            db_can_write:1;
 126
 127 };
 128
 129 struct si_stencil_ref {
 130         struct pipe_stencil_ref         state;
 131         struct si_dsa_stencil_ref_part  dsa_part;
 132 };
 133
 134 struct si_vertex_elements
 135 {
 136         struct si_resource              *instance_divisor_factor_buffer;
 137         uint32_t                        rsrc_word3[SI_MAX_ATTRIBS];
 138         uint16_t                        src_offset[SI_MAX_ATTRIBS];
 139         uint8_t                         fix_fetch[SI_MAX_ATTRIBS];
 140         uint8_t                         format_size[SI_MAX_ATTRIBS];
 141         uint8_t                         vertex_buffer_index[SI_MAX_ATTRIBS];
 142
 143         /* Bitmask of elements that always need a fixup to be applied. */
 144         uint16_t                        fix_fetch_always;
 145
 146         /* Bitmask of elements whose fetch should always be opencoded. */
 147         uint16_t                        fix_fetch_opencode;
 148
 149         /* Bitmask of elements which need to be opencoded if the vertex buffer
 150          * is unaligned. */
 151         uint16_t                        fix_fetch_unaligned;
 152
 153         /* For elements in fix_fetch_unaligned: whether the effective
 154          * element load size as seen by the hardware is a dword (as opposed
 155          * to a short).
 156          */
 157         uint16_t                        hw_load_is_dword;
 158
 159         /* Bitmask of vertex buffers requiring alignment check */
 160         uint16_t                        vb_alignment_check_mask;
 161
 162         uint8_t                         count;
 163         bool                            uses_instance_divisors;
 164
 165         uint16_t                        first_vb_use_mask;
 166         /* Vertex buffer descriptor list size aligned for optimal prefetch. */
 167         uint16_t                        desc_list_byte_size;
 168         uint16_t                        instance_divisor_is_one; /* bitmask of inputs */
 169         uint16_t                        instance_divisor_is_fetched;  /* bitmask of inputs */
 170 };
 171
 172 union si_state {
 173         struct {
 174                 struct si_state_blend           *blend;
 175                 struct si_state_rasterizer      *rasterizer;
 176                 struct si_state_dsa             *dsa;
 177                 struct si_pm4_state             *poly_offset;
 178                 struct si_pm4_state             *ls;
 179                 struct si_pm4_state             *hs;
 180                 struct si_pm4_state             *es;
 181                 struct si_pm4_state             *gs;
 182                 struct si_pm4_state             *vgt_shader_config;
 183                 struct si_pm4_state             *vs;
 184                 struct si_pm4_state             *ps;
 185         } named;
 186         struct si_pm4_state     *array[0];
 187 };
 188
 189 #define SI_STATE_IDX(name) \
 190         (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
 191 #define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
 192 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
 193
 194 static inline unsigned si_states_that_always_roll_context(void)
 195 {
 196         return (SI_STATE_BIT(blend) |
 197                 SI_STATE_BIT(rasterizer) |
 198                 SI_STATE_BIT(dsa) |
 199                 SI_STATE_BIT(poly_offset) |
 200                 SI_STATE_BIT(vgt_shader_config));
 201 }
 202
 203 union si_state_atoms {
 204         struct {
 205                 /* The order matters. */
 206                 struct si_atom render_cond;
 207                 struct si_atom streamout_begin;
 208                 struct si_atom streamout_enable; /* must be after streamout_begin */
 209                 struct si_atom framebuffer;
 210                 struct si_atom msaa_sample_locs;
 211                 struct si_atom db_render_state;
 212                 struct si_atom dpbb_state;
 213                 struct si_atom msaa_config;
 214                 struct si_atom sample_mask;
 215                 struct si_atom cb_render_state;
 216                 struct si_atom blend_color;
 217                 struct si_atom clip_regs;
 218                 struct si_atom clip_state;
 219                 struct si_atom shader_pointers;
 220                 struct si_atom guardband;
 221                 struct si_atom scissors;
 222                 struct si_atom viewports;
 223                 struct si_atom stencil_ref;
 224                 struct si_atom spi_map;
 225                 struct si_atom scratch_state;
 226                 struct si_atom window_rectangles;
 227         } s;
 228         struct si_atom array[0];
 229 };
 230
 231 #define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / \
 232                                  sizeof(struct si_atom)))
 233 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct si_atom*))
 234
 235 static inline unsigned si_atoms_that_always_roll_context(void)
 236 {
 237         return (SI_ATOM_BIT(streamout_begin) |
 238                 SI_ATOM_BIT(streamout_enable) |
 239                 SI_ATOM_BIT(framebuffer) |
 240                 SI_ATOM_BIT(msaa_sample_locs) |
 241                 SI_ATOM_BIT(sample_mask) |
 242                 SI_ATOM_BIT(blend_color) |
 243                 SI_ATOM_BIT(clip_state) |
 244                 SI_ATOM_BIT(scissors) |
 245                 SI_ATOM_BIT(viewports) |
 246                 SI_ATOM_BIT(stencil_ref) |
 247                 SI_ATOM_BIT(scratch_state) |
 248                 SI_ATOM_BIT(window_rectangles));
 249 }
 250
 251 struct si_shader_data {
 252         uint32_t                sh_base[SI_NUM_SHADERS];
 253 };
 254
 255 /* The list of registers whose emitted values are remembered by si_context. */
 256 enum si_tracked_reg {
 257         SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
 258         SI_TRACKED_DB_COUNT_CONTROL,
 259
 260         SI_TRACKED_DB_RENDER_OVERRIDE2,
 261         SI_TRACKED_DB_SHADER_CONTROL,
 262
 263         SI_TRACKED_CB_TARGET_MASK,
 264         SI_TRACKED_CB_DCC_CONTROL,
 265
 266         SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
 267         SI_TRACKED_SX_BLEND_OPT_EPSILON,
 268         SI_TRACKED_SX_BLEND_OPT_CONTROL,
 269
 270         SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */
 271         SI_TRACKED_PA_SC_AA_CONFIG,
 272
 273         SI_TRACKED_DB_EQAA,
 274         SI_TRACKED_PA_SC_MODE_CNTL_1,
 275
 276         SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
 277         SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
 278
 279         SI_TRACKED_PA_CL_VS_OUT_CNTL,
 280         SI_TRACKED_PA_CL_CLIP_CNTL,
 281
 282         SI_TRACKED_PA_SC_BINNER_CNTL_0,
 283         SI_TRACKED_DB_DFSM_CONTROL,
 284
 285         SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
 286         SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
 287         SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
 288         SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
 289
 290         SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
 291         SI_TRACKED_PA_SU_VTX_CNTL,
 292
 293         SI_TRACKED_PA_SC_CLIPRECT_RULE,
 294
 295         SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
 296
 297         SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 4 consecutive registers */
 298         SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
 299         SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
 300         SI_TRACKED_VGT_GS_OUT_PRIM_TYPE,
 301
 302         SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
 303         SI_TRACKED_VGT_GS_MAX_VERT_OUT,
 304
 305         SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */
 306         SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
 307         SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
 308         SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
 309
 310         SI_TRACKED_VGT_GS_INSTANCE_CNT,
 311         SI_TRACKED_VGT_GS_ONCHIP_CNTL,
 312         SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
 313         SI_TRACKED_VGT_GS_MODE,
 314         SI_TRACKED_VGT_PRIMITIVEID_EN,
 315         SI_TRACKED_VGT_REUSE_OFF,
 316         SI_TRACKED_SPI_VS_OUT_CONFIG,
 317         SI_TRACKED_SPI_SHADER_POS_FORMAT,
 318         SI_TRACKED_PA_CL_VTE_CNTL,
 319
 320         SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
 321         SI_TRACKED_SPI_PS_INPUT_ADDR,
 322
 323         SI_TRACKED_SPI_BARYC_CNTL,
 324         SI_TRACKED_SPI_PS_IN_CONTROL,
 325
 326         SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */
 327         SI_TRACKED_SPI_SHADER_COL_FORMAT,
 328
 329         SI_TRACKED_CB_SHADER_MASK,
 330         SI_TRACKED_VGT_TF_PARAM,
 331         SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
 332
 333         SI_NUM_TRACKED_REGS,
 334 };
 335
 336 struct si_tracked_regs {
 337         uint64_t                reg_saved;
 338         uint32_t                reg_value[SI_NUM_TRACKED_REGS];
 339         uint32_t                spi_ps_input_cntl[32];
 340 };
 341
 342 /* Private read-write buffer slots. */
 343 enum {
 344         SI_ES_RING_ESGS,
 345         SI_GS_RING_ESGS,
 346
 347         SI_RING_GSVS,
 348
 349         SI_VS_STREAMOUT_BUF0,
 350         SI_VS_STREAMOUT_BUF1,
 351         SI_VS_STREAMOUT_BUF2,
 352         SI_VS_STREAMOUT_BUF3,
 353
 354         SI_HS_CONST_DEFAULT_TESS_LEVELS,
 355         SI_VS_CONST_INSTANCE_DIVISORS,
 356         SI_VS_CONST_CLIP_PLANES,
 357         SI_PS_CONST_POLY_STIPPLE,
 358         SI_PS_CONST_SAMPLE_POSITIONS,
 359
 360         /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
 361         SI_PS_IMAGE_COLORBUF0,
 362         SI_PS_IMAGE_COLORBUF0_HI,
 363         SI_PS_IMAGE_COLORBUF0_FMASK,
 364         SI_PS_IMAGE_COLORBUF0_FMASK_HI,
 365
 366         SI_NUM_RW_BUFFERS,
 367 };
 368
 369 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
 370  * are contiguous:
 371  *
 372  *  0 - rw buffers
 373  *  1 - vertex const and shader buffers
 374  *  2 - vertex samplers and images
 375  *  3 - fragment const and shader buffer
 376  *   ...
 377  *  11 - compute const and shader buffers
 378  *  12 - compute samplers and images
 379  */
 380 enum {
 381         SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 382         SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 383         SI_NUM_SHADER_DESCS,
 384 };
 385
 386 #define SI_DESCS_RW_BUFFERS            0
 387 #define SI_DESCS_FIRST_SHADER          1
 388 #define SI_DESCS_FIRST_COMPUTE         (SI_DESCS_FIRST_SHADER + \
 389                                         PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
 390 #define SI_NUM_DESCS                   (SI_DESCS_FIRST_SHADER + \
 391                                         SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
 392
 393 #define SI_DESCS_SHADER_MASK(name) \
 394         u_bit_consecutive(SI_DESCS_FIRST_SHADER + \
 395                           PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
 396                           SI_NUM_SHADER_DESCS)
 397
 398 static inline unsigned
 399 si_const_and_shader_buffer_descriptors_idx(unsigned shader)
 400 {
 401         return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
 402                SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
 403 }
 404
 405 static inline unsigned
 406 si_sampler_and_image_descriptors_idx(unsigned shader)
 407 {
 408         return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
 409                SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
 410 }
 411
 412 /* This represents descriptors in memory, such as buffer resources,
 413  * image resources, and sampler states.
 414  */
 415 struct si_descriptors {
 416         /* The list of descriptors in malloc'd memory. */
 417         uint32_t *list;
 418         /* The list in mapped GPU memory. */
 419         uint32_t *gpu_list;
 420
 421         /* The buffer where the descriptors have been uploaded. */
 422         struct si_resource *buffer;
 423         uint64_t gpu_address;
 424
 425         /* The maximum number of descriptors. */
 426         uint32_t num_elements;
 427
 428         /* Slots that are used by currently-bound shaders.
 429          * It determines which slots are uploaded.
 430          */
 431         uint32_t first_active_slot;
 432         uint32_t num_active_slots;
 433
 434         /* The SH register offset relative to USER_DATA*_0 where the pointer
 435          * to the descriptor array will be stored. */
 436         short shader_userdata_offset;
 437         /* The size of one descriptor. */
 438         ubyte element_dw_size;
 439         /* If there is only one slot enabled, bind it directly instead of
 440          * uploading descriptors. -1 if disabled. */
 441         signed char slot_index_to_bind_directly;
 442 };
 443
 444 struct si_buffer_resources {
 445         struct pipe_resource            **buffers; /* this has num_buffers elements */
 446
 447         enum radeon_bo_priority         priority:6;
 448         enum radeon_bo_priority         priority_constbuf:6;
 449
 450         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 451         unsigned                        enabled_mask;
 452         unsigned                        writable_mask;
 453 };
 454
 455 #define si_pm4_state_changed(sctx, member) \
 456         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 457
 458 #define si_pm4_state_enabled_and_changed(sctx, member) \
 459         ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
 460
 461 #define si_pm4_bind_state(sctx, member, value) \
 462         do { \
 463                 (sctx)->queued.named.member = (value); \
 464                 (sctx)->dirty_states |= SI_STATE_BIT(member); \
 465         } while(0)
 466
 467 #define si_pm4_delete_state(sctx, member, value) \
 468         do { \
 469                 if ((sctx)->queued.named.member == (value)) { \
 470                         (sctx)->queued.named.member = NULL; \
 471                 } \
 472                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 473                                   SI_STATE_IDX(member)); \
 474         } while(0)
 475
 476 /* si_descriptors.c */
 477 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 478                                     struct si_texture *tex,
 479                                     const struct legacy_surf_level *base_level_info,
 480                                     unsigned base_level, unsigned first_level,
 481                                     unsigned block_width, bool is_stencil,
 482                                     uint32_t *state);
 483 void si_update_ps_colorbuf0_slot(struct si_context *sctx);
 484 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
 485                                  uint slot, struct pipe_constant_buffer *cbuf);
 486 void si_get_shader_buffers(struct si_context *sctx,
 487                            enum pipe_shader_type shader,
 488                            uint start_slot, uint count,
 489                            struct pipe_shader_buffer *sbuf);
 490 void si_set_ring_buffer(struct si_context *sctx, uint slot,
 491                         struct pipe_resource *buffer,
 492                         unsigned stride, unsigned num_records,
 493                         bool add_tid, bool swizzle,
 494                         unsigned element_size, unsigned index_stride, uint64_t offset);
 495 void si_init_all_descriptors(struct si_context *sctx);
 496 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
 497 bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
 498 bool si_upload_compute_shader_descriptors(struct si_context *sctx);
 499 void si_release_all_descriptors(struct si_context *sctx);
 500 void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx);
 501 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
 502 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 503 void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf,
 504                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 505 void si_update_all_texture_descriptors(struct si_context *sctx);
 506 void si_shader_change_notify(struct si_context *sctx);
 507 void si_update_needs_color_decompress_masks(struct si_context *sctx);
 508 void si_emit_graphics_shader_pointers(struct si_context *sctx);
 509 void si_emit_compute_shader_pointers(struct si_context *sctx);
 510 void si_set_rw_buffer(struct si_context *sctx,
 511                       uint slot, const struct pipe_constant_buffer *input);
 512 void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
 513                              const struct pipe_shader_buffer *sbuffer);
 514 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
 515                                uint64_t new_active_mask);
 516 void si_set_active_descriptors_for_shader(struct si_context *sctx,
 517                                           struct si_shader_selector *sel);
 518 bool si_bindless_descriptor_can_reclaim_slab(void *priv,
 519                                              struct pb_slab_entry *entry);
 520 struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap,
 521                                                   unsigned entry_size,
 522                                                   unsigned group_index);
 523 void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
 524 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf,
 525                       uint64_t old_va);
 526 /* si_state.c */
 527 void si_init_state_compute_functions(struct si_context *sctx);
 528 void si_init_state_functions(struct si_context *sctx);
 529 void si_init_screen_state_functions(struct si_screen *sscreen);
 530 void
 531 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
 532                           enum pipe_format format,
 533                           unsigned offset, unsigned size,
 534                           uint32_t *state);
 535 void
 536 si_make_texture_descriptor(struct si_screen *screen,
 537                            struct si_texture *tex,
 538                            bool sampler,
 539                            enum pipe_texture_target target,
 540                            enum pipe_format pipe_format,
 541                            const unsigned char state_swizzle[4],
 542                            unsigned first_level, unsigned last_level,
 543                            unsigned first_layer, unsigned last_layer,
 544                            unsigned width, unsigned height, unsigned depth,
 545                            uint32_t *state,
 546                            uint32_t *fmask_state);
 547 struct pipe_sampler_view *
 548 si_create_sampler_view_custom(struct pipe_context *ctx,
 549                               struct pipe_resource *texture,
 550                               const struct pipe_sampler_view *state,
 551                               unsigned width0, unsigned height0,
 552                               unsigned force_level);
 553 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
 554 void si_update_ps_iter_samples(struct si_context *sctx);
 555 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
 556 void si_set_occlusion_query_state(struct si_context *sctx,
 557                                   bool old_perfect_enable);
 558
 559 /* si_state_binning.c */
 560 void si_emit_dpbb_state(struct si_context *sctx);
 561
 562 /* si_state_shaders.c */
 563 void *si_get_ir_binary(struct si_shader_selector *sel);
 564 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
 565                                  struct si_shader *shader);
 566 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
 567                                    struct si_shader *shader,
 568                                    bool insert_into_disk_cache);
 569 bool si_update_shaders(struct si_context *sctx);
 570 void si_init_shader_functions(struct si_context *sctx);
 571 bool si_init_shader_cache(struct si_screen *sscreen);
 572 void si_destroy_shader_cache(struct si_screen *sscreen);
 573 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
 574                                  struct util_queue_fence *ready_fence,
 575                                  struct si_compiler_ctx_state *compiler_ctx_state,
 576                                  void *job, util_queue_execute_func execute);
 577 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
 578                               uint32_t *const_and_shader_buffers,
 579                               uint64_t *samplers_and_images);
 580 int si_shader_select_with_key(struct si_screen *sscreen,
 581                               struct si_shader_ctx_state *state,
 582                               struct si_compiler_ctx_state *compiler_state,
 583                               struct si_shader_key *key,
 584                               int thread_index,
 585                               bool optimized_or_none);
 586
 587 /* si_state_draw.c */
 588 void si_emit_cache_flush(struct si_context *sctx);
 589 void si_trace_emit(struct si_context *sctx);
 590 void si_init_draw_functions(struct si_context *sctx);
 591
 592 /* si_state_msaa.c */
 593 void si_init_msaa_functions(struct si_context *sctx);
 594 void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
 595
 596 /* si_state_streamout.c */
 597 void si_streamout_buffers_dirty(struct si_context *sctx);
 598 void si_emit_streamout_end(struct si_context *sctx);
 599 void si_update_prims_generated_query_state(struct si_context *sctx,
 600                                            unsigned type, int diff);
 601 void si_init_streamout_functions(struct si_context *sctx);
 602
 603
 604 static inline unsigned si_get_constbuf_slot(unsigned slot)
 605 {
 606         /* Constant buffers are in slots [16..31], ascending */
 607         return SI_NUM_SHADER_BUFFERS + slot;
 608 }
 609
 610 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
 611 {
 612         /* shader buffers are in slots [15..0], descending */
 613         return SI_NUM_SHADER_BUFFERS - 1 - slot;
 614 }
 615
 616 static inline unsigned si_get_sampler_slot(unsigned slot)
 617 {
 618         /* samplers are in slots [8..39], ascending */
 619         return SI_NUM_IMAGES / 2 + slot;
 620 }
 621
 622 static inline unsigned si_get_image_slot(unsigned slot)
 623 {
 624         /* images are in slots [15..0] (sampler slots [7..0]), descending */
 625         return SI_NUM_IMAGES - 1 - slot;
 626 }
 627
 628 #endif