2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
36 #define SI_MAX_ATTRIBS 16
37 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
38 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
39 #define SI_NUM_CONST_BUFFERS 16
40 #define SI_NUM_IMAGES 16
41 #define SI_NUM_SHADER_BUFFERS 16
45 struct si_shader_selector
;
47 struct si_state_blend
{
48 struct si_pm4_state pm4
;
49 uint32_t cb_target_mask
;
50 bool alpha_to_coverage
;
53 /* Set 0xf or 0x0 (4 bits) per render target if the following is
54 * true. ANDed with spi_shader_col_format.
56 unsigned blend_enable_4bit
;
57 unsigned need_src_alpha_4bit
;
60 struct si_state_rasterizer
{
61 struct si_pm4_state pm4
;
62 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
63 struct si_pm4_state pm4_poly_offset
[3];
66 bool multisample_enable
;
67 bool force_persample_interp
;
68 bool line_stipple_enable
;
69 unsigned sprite_coord_enable
;
70 unsigned pa_sc_line_stipple
;
71 unsigned pa_cl_clip_cntl
;
72 unsigned clip_plane_enable
;
73 bool poly_stipple_enable
;
76 bool uses_poly_offset
;
77 bool clamp_fragment_color
;
78 bool clamp_vertex_color
;
79 bool rasterizer_discard
;
84 struct si_dsa_stencil_ref_part
{
90 struct si_pm4_state pm4
;
92 struct si_dsa_stencil_ref_part stencil_ref
;
95 struct si_stencil_ref
{
96 struct r600_atom atom
;
97 struct pipe_stencil_ref state
;
98 struct si_dsa_stencil_ref_part dsa_part
;
101 struct si_vertex_element
104 unsigned first_vb_use_mask
;
105 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
106 unsigned desc_list_byte_size
;
108 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
109 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
110 uint32_t format_size
[SI_MAX_ATTRIBS
];
111 struct pipe_vertex_element elements
[SI_MAX_ATTRIBS
];
112 bool uses_instance_divisors
;
117 struct si_state_blend
*blend
;
118 struct si_state_rasterizer
*rasterizer
;
119 struct si_state_dsa
*dsa
;
120 struct si_pm4_state
*poly_offset
;
121 struct si_pm4_state
*ls
;
122 struct si_pm4_state
*hs
;
123 struct si_pm4_state
*es
;
124 struct si_pm4_state
*gs
;
125 struct si_pm4_state
*vgt_shader_config
;
126 struct si_pm4_state
*vs
;
127 struct si_pm4_state
*ps
;
129 struct si_pm4_state
*array
[0];
132 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
134 union si_state_atoms
{
136 /* The order matters. */
137 struct r600_atom
*prefetch_L2
;
138 struct r600_atom
*render_cond
;
139 struct r600_atom
*streamout_begin
;
140 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
141 struct r600_atom
*framebuffer
;
142 struct r600_atom
*msaa_sample_locs
;
143 struct r600_atom
*db_render_state
;
144 struct r600_atom
*msaa_config
;
145 struct r600_atom
*sample_mask
;
146 struct r600_atom
*cb_render_state
;
147 struct r600_atom
*blend_color
;
148 struct r600_atom
*clip_regs
;
149 struct r600_atom
*clip_state
;
150 struct r600_atom
*shader_userdata
;
151 struct r600_atom
*scissors
;
152 struct r600_atom
*viewports
;
153 struct r600_atom
*stencil_ref
;
154 struct r600_atom
*spi_map
;
155 struct r600_atom
*scratch_state
;
157 struct r600_atom
*array
[0];
160 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
162 struct si_shader_data
{
163 struct r600_atom atom
;
164 uint32_t sh_base
[SI_NUM_SHADERS
];
167 /* Private read-write buffer slots. */
174 SI_VS_STREAMOUT_BUF0
,
175 SI_VS_STREAMOUT_BUF1
,
176 SI_VS_STREAMOUT_BUF2
,
177 SI_VS_STREAMOUT_BUF3
,
179 SI_HS_CONST_DEFAULT_TESS_LEVELS
,
180 SI_VS_CONST_CLIP_PLANES
,
181 SI_PS_CONST_POLY_STIPPLE
,
182 SI_PS_CONST_SAMPLE_POSITIONS
,
187 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
191 * 1 - vertex const buffers
192 * 2 - vertex shader buffers
194 * 5 - fragment const buffers
196 * 21 - compute const buffers
200 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
201 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
205 #define SI_DESCS_RW_BUFFERS 0
206 #define SI_DESCS_FIRST_SHADER 1
207 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
208 PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
209 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
210 SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
212 /* This represents descriptors in memory, such as buffer resources,
213 * image resources, and sampler states.
215 struct si_descriptors
{
216 /* The list of descriptors in malloc'd memory. */
218 /* The list in mapped GPU memory. */
220 /* The size of one descriptor. */
221 unsigned element_dw_size
;
222 /* The maximum number of descriptors. */
223 unsigned num_elements
;
225 /* The buffer where the descriptors have been uploaded. */
226 struct r600_resource
*buffer
;
227 int buffer_offset
; /* can be negative if not using lower slots */
229 /* Offset in CE RAM */
232 /* Slots allocated in CE RAM. If we get active slots outside of this
233 * range, direct uploads to memory will be used instead. This basically
234 * governs switching between onchip (CE) and offchip (upload) modes.
236 unsigned first_ce_slot
;
237 unsigned num_ce_slots
;
239 /* Slots that are used by currently-bound shaders.
240 * With CE: It determines which slots are dumped to L2.
241 * It doesn't skip uploads to CE RAM.
242 * Without CE: It determines which slots are uploaded.
244 unsigned first_active_slot
;
245 unsigned num_active_slots
;
247 /* Slots that have been changed and need to be uploaded. */
250 /* Whether CE is used to upload this descriptor array. */
253 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
254 * array will be stored. */
255 unsigned shader_userdata_offset
;
258 struct si_sampler_views
{
259 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
260 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
262 /* The i-th bit is set if that element is enabled (non-NULL resource). */
263 unsigned enabled_mask
;
266 struct si_buffer_resources
{
267 enum radeon_bo_usage shader_usage
; /* READ, WRITE, or READWRITE */
268 enum radeon_bo_usage shader_usage_constbuf
;
269 enum radeon_bo_priority priority
;
270 enum radeon_bo_priority priority_constbuf
;
271 struct pipe_resource
**buffers
; /* this has num_buffers elements */
273 /* The i-th bit is set if that element is enabled (non-NULL resource). */
274 unsigned enabled_mask
;
277 #define si_pm4_block_idx(member) \
278 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
280 #define si_pm4_state_changed(sctx, member) \
281 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
283 #define si_pm4_bind_state(sctx, member, value) \
285 (sctx)->queued.named.member = (value); \
286 (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
289 #define si_pm4_delete_state(sctx, member, value) \
291 if ((sctx)->queued.named.member == (value)) { \
292 (sctx)->queued.named.member = NULL; \
294 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
295 si_pm4_block_idx(member)); \
298 /* si_descriptors.c */
299 void si_ce_save_all_descriptors_at_ib_end(struct si_context
* sctx
);
300 void si_ce_restore_all_descriptors_at_ib_start(struct si_context
*sctx
);
301 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
);
302 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
303 struct r600_texture
*tex
,
304 const struct legacy_surf_level
*base_level_info
,
305 unsigned base_level
, unsigned first_level
,
306 unsigned block_width
, bool is_stencil
,
308 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
309 uint slot
, struct pipe_constant_buffer
*cbuf
);
310 void si_get_shader_buffers(struct si_context
*sctx
,
311 enum pipe_shader_type shader
,
312 uint start_slot
, uint count
,
313 struct pipe_shader_buffer
*sbuf
);
314 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
315 struct pipe_resource
*buffer
,
316 unsigned stride
, unsigned num_records
,
317 bool add_tid
, bool swizzle
,
318 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
319 void si_init_all_descriptors(struct si_context
*sctx
);
320 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
);
321 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
);
322 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
);
323 void si_release_all_descriptors(struct si_context
*sctx
);
324 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
325 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
326 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
327 void si_update_all_texture_descriptors(struct si_context
*sctx
);
328 void si_shader_change_notify(struct si_context
*sctx
);
329 void si_update_needs_color_decompress_masks(struct si_context
*sctx
);
330 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
331 struct r600_atom
*atom
);
332 void si_emit_compute_shader_userdata(struct si_context
*sctx
);
333 void si_set_rw_buffer(struct si_context
*sctx
,
334 uint slot
, const struct pipe_constant_buffer
*input
);
335 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
336 uint64_t new_active_mask
);
337 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
338 struct si_shader_selector
*sel
);
341 struct si_shader_selector
;
343 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
344 struct r600_atom
**list_elem
,
345 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
346 void si_init_state_functions(struct si_context
*sctx
);
347 void si_init_screen_state_functions(struct si_screen
*sscreen
);
349 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
350 enum pipe_format format
,
351 unsigned offset
, unsigned size
,
354 si_make_texture_descriptor(struct si_screen
*screen
,
355 struct r600_texture
*tex
,
357 enum pipe_texture_target target
,
358 enum pipe_format pipe_format
,
359 const unsigned char state_swizzle
[4],
360 unsigned first_level
, unsigned last_level
,
361 unsigned first_layer
, unsigned last_layer
,
362 unsigned width
, unsigned height
, unsigned depth
,
364 uint32_t *fmask_state
);
365 struct pipe_sampler_view
*
366 si_create_sampler_view_custom(struct pipe_context
*ctx
,
367 struct pipe_resource
*texture
,
368 const struct pipe_sampler_view
*state
,
369 unsigned width0
, unsigned height0
,
370 unsigned force_level
);
372 /* si_state_shader.c */
373 bool si_update_shaders(struct si_context
*sctx
);
374 void si_init_shader_functions(struct si_context
*sctx
);
375 bool si_init_shader_cache(struct si_screen
*sscreen
);
376 void si_destroy_shader_cache(struct si_screen
*sscreen
);
377 void si_init_shader_selector_async(void *job
, int thread_index
);
378 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
379 uint32_t *const_and_shader_buffers
,
380 uint64_t *samplers_and_images
);
382 /* si_state_draw.c */
383 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
);
384 void si_emit_cache_flush(struct si_context
*sctx
);
385 void si_ce_pre_draw_synchronization(struct si_context
*sctx
);
386 void si_ce_post_draw_synchronization(struct si_context
*sctx
);
387 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
388 void si_trace_emit(struct si_context
*sctx
);
391 static inline unsigned
392 si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
395 return rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
397 return rtex
->surface
.u
.legacy
.tiling_index
[level
];
400 static inline unsigned si_get_constbuf_slot(unsigned slot
)
402 /* Constant buffers are in slots [16..31], ascending */
403 return SI_NUM_SHADER_BUFFERS
+ slot
;
406 static inline unsigned si_get_shaderbuf_slot(unsigned slot
)
408 /* shader buffers are in slots [15..0], descending */
409 return SI_NUM_SHADER_BUFFERS
- 1 - slot
;
412 static inline unsigned si_get_sampler_slot(unsigned slot
)
414 /* samplers are in slots [8..39], ascending */
415 return SI_NUM_IMAGES
/ 2 + slot
;
418 static inline unsigned si_get_image_slot(unsigned slot
)
420 /* images are in slots [15..0] (sampler slots [7..0]), descending */
421 return SI_NUM_IMAGES
- 1 - slot
;