2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
31 #include "radeon/r600_pipe_common.h"
33 #define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
34 #define SI_MAX_ATTRIBS 16
39 struct si_state_blend
{
40 struct si_pm4_state pm4
;
41 uint32_t cb_target_mask
;
46 struct si_state_rasterizer
{
47 struct si_pm4_state pm4
;
48 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
49 struct si_pm4_state pm4_poly_offset
[3];
52 bool multisample_enable
;
53 bool line_stipple_enable
;
54 unsigned sprite_coord_enable
;
55 unsigned pa_sc_line_stipple
;
56 unsigned pa_cl_clip_cntl
;
57 unsigned clip_plane_enable
;
58 bool poly_stipple_enable
;
61 bool uses_poly_offset
;
64 struct si_dsa_stencil_ref_part
{
70 struct si_pm4_state pm4
;
72 struct si_dsa_stencil_ref_part stencil_ref
;
75 struct si_stencil_ref
{
76 struct r600_atom atom
;
77 struct pipe_stencil_ref state
;
78 struct si_dsa_stencil_ref_part dsa_part
;
81 struct si_vertex_element
84 uint32_t rsrc_word3
[SI_MAX_ATTRIBS
];
85 uint32_t format_size
[SI_MAX_ATTRIBS
];
86 struct pipe_vertex_element elements
[SI_MAX_ATTRIBS
];
91 struct si_state_blend
*blend
;
92 struct si_state_rasterizer
*rasterizer
;
93 struct si_state_dsa
*dsa
;
94 struct si_pm4_state
*poly_offset
;
95 struct si_pm4_state
*ls
;
96 struct si_pm4_state
*hs
;
97 struct si_pm4_state
*es
;
98 struct si_pm4_state
*gs
;
99 struct si_pm4_state
*vgt_shader_config
;
100 struct si_pm4_state
*vs
;
101 struct si_pm4_state
*ps
;
103 struct si_pm4_state
*array
[0];
106 union si_state_atoms
{
108 /* The order matters. */
109 struct r600_atom
*cache_flush
;
110 struct r600_atom
*streamout_begin
;
111 struct r600_atom
*streamout_enable
; /* must be after streamout_begin */
112 struct r600_atom
*framebuffer
;
113 struct r600_atom
*msaa_sample_locs
;
114 struct r600_atom
*db_render_state
;
115 struct r600_atom
*msaa_config
;
116 struct r600_atom
*sample_mask
;
117 struct r600_atom
*cb_target_mask
;
118 struct r600_atom
*blend_color
;
119 struct r600_atom
*clip_regs
;
120 struct r600_atom
*clip_state
;
121 struct r600_atom
*shader_userdata
;
122 struct r600_atom
*scissors
;
123 struct r600_atom
*viewports
;
124 struct r600_atom
*stencil_ref
;
125 struct r600_atom
*spi_map
;
127 struct r600_atom
*array
[0];
130 #define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
132 struct si_shader_data
{
133 struct r600_atom atom
;
134 uint32_t sh_base
[SI_NUM_SHADERS
];
137 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
138 #define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
139 #define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
141 /* User sampler views: 0..15
142 * Polygon stipple tex: 16
143 * FMASK sampler views: 17..33 (no sampler states)
145 #define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
146 #define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
147 #define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
149 /* User constant buffers: 0..15
150 * Driver state constants: 16
152 #define SI_NUM_USER_CONST_BUFFERS 16
153 #define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
154 #define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
156 /* Read-write buffer slots.
159 * Streamout buffers: 2..5
161 #define SI_RING_TESS_FACTOR 0 /* for HS (TCS) */
162 #define SI_RING_ESGS 0 /* for ES, GS */
163 #define SI_RING_GSVS 1 /* for GS, VS */
164 #define SI_RING_GSVS_1 2 /* 1, 2, 3 for GS */
165 #define SI_RING_GSVS_2 3
166 #define SI_RING_GSVS_3 4
167 #define SI_NUM_RING_BUFFERS 5
168 #define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
169 #define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
171 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
174 /* This represents descriptors in memory, such as buffer resources,
175 * image resources, and sampler states.
177 struct si_descriptors
{
178 /* The list of descriptors in malloc'd memory. */
180 /* The size of one descriptor. */
181 unsigned element_dw_size
;
182 /* The maximum number of descriptors. */
183 unsigned num_elements
;
184 /* Whether the list has been changed and should be re-uploaded. */
187 /* The buffer where the descriptors have been uploaded. */
188 struct r600_resource
*buffer
;
189 unsigned buffer_offset
;
191 /* The i-th bit is set if that element is enabled (non-NULL resource). */
192 uint64_t enabled_mask
;
194 /* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
195 * array will be stored. */
196 unsigned shader_userdata_offset
;
197 /* Whether the pointer should be re-emitted. */
201 struct si_sampler_views
{
202 struct si_descriptors desc
;
203 struct pipe_sampler_view
*views
[SI_NUM_SAMPLER_VIEWS
];
206 struct si_sampler_states
{
207 struct si_descriptors desc
;
208 void *saved_states
[2]; /* saved for u_blitter */
211 struct si_buffer_resources
{
212 struct si_descriptors desc
;
213 enum radeon_bo_usage shader_usage
; /* READ, WRITE, or READWRITE */
214 enum radeon_bo_priority priority
;
215 struct pipe_resource
**buffers
; /* this has num_buffers elements */
218 #define si_pm4_block_idx(member) \
219 (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
221 #define si_pm4_state_changed(sctx, member) \
222 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
224 #define si_pm4_bind_state(sctx, member, value) \
226 (sctx)->queued.named.member = (value); \
229 #define si_pm4_delete_state(sctx, member, value) \
231 if ((sctx)->queued.named.member == (value)) { \
232 (sctx)->queued.named.member = NULL; \
234 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
235 si_pm4_block_idx(member)); \
238 /* si_descriptors.c */
239 void si_set_ring_buffer(struct pipe_context
*ctx
, uint shader
, uint slot
,
240 struct pipe_resource
*buffer
,
241 unsigned stride
, unsigned num_records
,
242 bool add_tid
, bool swizzle
,
243 unsigned element_size
, unsigned index_stride
, uint64_t offset
);
244 void si_init_all_descriptors(struct si_context
*sctx
);
245 bool si_upload_shader_descriptors(struct si_context
*sctx
);
246 void si_release_all_descriptors(struct si_context
*sctx
);
247 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
);
248 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
249 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
);
250 void si_shader_change_notify(struct si_context
*sctx
);
251 void si_emit_shader_userdata(struct si_context
*sctx
, struct r600_atom
*atom
);
254 struct si_shader_selector
;
256 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
257 struct r600_atom
**list_elem
,
258 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
));
259 boolean
si_is_format_supported(struct pipe_screen
*screen
,
260 enum pipe_format format
,
261 enum pipe_texture_target target
,
262 unsigned sample_count
,
264 void si_init_state_functions(struct si_context
*sctx
);
265 unsigned cik_bank_wh(unsigned bankwh
);
266 unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
);
267 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
);
268 unsigned cik_tile_split(unsigned tile_split
);
269 unsigned si_array_mode(unsigned mode
);
270 uint32_t si_num_banks(struct si_screen
*sscreen
, struct r600_texture
*tex
);
271 unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
);
272 struct pipe_sampler_view
*
273 si_create_sampler_view_custom(struct pipe_context
*ctx
,
274 struct pipe_resource
*texture
,
275 const struct pipe_sampler_view
*state
,
276 unsigned width0
, unsigned height0
,
277 unsigned force_level
);
279 /* si_state_shader.c */
280 bool si_update_shaders(struct si_context
*sctx
);
281 void si_init_shader_functions(struct si_context
*sctx
);
283 /* si_state_draw.c */
284 void si_emit_cache_flush(struct si_context
*sctx
, struct r600_atom
*atom
);
285 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
);
286 void si_trace_emit(struct si_context
*sctx
);