src/gallium/drivers/radeonsi/si_state.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef SI_STATE_H
  28 #define SI_STATE_H
  29
  30 #include "si_pm4.h"
  31 #include "radeon/r600_pipe_common.h"
  32
  33 struct si_screen;
  34 struct si_shader;
  35
  36 struct si_state_blend {
  37         struct si_pm4_state     pm4;
  38         uint32_t                cb_target_mask;
  39         bool                    alpha_to_one;
  40 };
  41
  42 struct si_state_sample_mask {
  43         struct si_pm4_state     pm4;
  44         uint16_t                sample_mask;
  45 };
  46
  47 struct si_state_scissor {
  48         struct si_pm4_state             pm4;
  49         struct pipe_scissor_state       scissor;
  50 };
  51
  52 struct si_state_viewport {
  53         struct si_pm4_state             pm4;
  54         struct pipe_viewport_state      viewport;
  55 };
  56
  57 struct si_state_rasterizer {
  58         struct si_pm4_state     pm4;
  59         bool                    flatshade;
  60         bool                    two_side;
  61         bool                    multisample_enable;
  62         bool                    line_stipple_enable;
  63         unsigned                sprite_coord_enable;
  64         unsigned                pa_sc_line_stipple;
  65         unsigned                pa_su_sc_mode_cntl;
  66         unsigned                pa_cl_clip_cntl;
  67         unsigned                pa_cl_vs_out_cntl;
  68         unsigned                clip_plane_enable;
  69         float                   offset_units;
  70         float                   offset_scale;
  71 };
  72
  73 struct si_state_dsa {
  74         struct si_pm4_state     pm4;
  75         float                   alpha_ref;
  76         unsigned                alpha_func;
  77         unsigned                db_render_control;
  78         uint8_t                 valuemask[2];
  79         uint8_t                 writemask[2];
  80 };
  81
  82 struct si_vertex_element
  83 {
  84         unsigned                        count;
  85         uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
  86         uint32_t                        format_size[PIPE_MAX_ATTRIBS];
  87         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
  88 };
  89
  90 union si_state {
  91         struct {
  92                 struct si_pm4_state             *init;
  93                 struct si_state_blend           *blend;
  94                 struct si_pm4_state             *blend_color;
  95                 struct si_pm4_state             *clip;
  96                 struct si_state_sample_mask     *sample_mask;
  97                 struct si_state_scissor         *scissor;
  98                 struct si_state_viewport        *viewport;
  99                 struct si_state_rasterizer      *rasterizer;
 100                 struct si_state_dsa             *dsa;
 101                 struct si_pm4_state             *fb_rs;
 102                 struct si_pm4_state             *fb_blend;
 103                 struct si_pm4_state             *dsa_stencil_ref;
 104                 struct si_pm4_state             *ta_bordercolor_base;
 105                 struct si_pm4_state             *es;
 106                 struct si_pm4_state             *gs;
 107                 struct si_pm4_state             *gs_rings;
 108                 struct si_pm4_state             *gs_onoff;
 109                 struct si_pm4_state             *vs;
 110                 struct si_pm4_state             *ps;
 111                 struct si_pm4_state             *spi;
 112                 struct si_pm4_state             *draw_info;
 113                 struct si_pm4_state             *draw;
 114         } named;
 115         struct si_pm4_state     *array[0];
 116 };
 117
 118 #define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
 119
 120 /* User sampler views:   0..15
 121  * FMASK sampler views: 16..31 (no sampler states)
 122  */
 123 #define SI_FMASK_TEX_OFFSET             SI_NUM_USER_SAMPLERS
 124 #define SI_NUM_SAMPLER_VIEWS            (SI_FMASK_TEX_OFFSET + SI_NUM_USER_SAMPLERS)
 125 #define SI_NUM_SAMPLER_STATES           SI_NUM_USER_SAMPLERS
 126
 127 /* User constant buffers:   0..15
 128  * Driver state constants:  16
 129  */
 130 #define SI_NUM_USER_CONST_BUFFERS       16
 131 #define SI_DRIVER_STATE_CONST_BUF       SI_NUM_USER_CONST_BUFFERS
 132 #define SI_NUM_CONST_BUFFERS            (SI_DRIVER_STATE_CONST_BUF + 1)
 133
 134 /* Read-write buffer slots.
 135  *
 136  * Ring buffers:        0..1
 137  * Streamout buffers:   2..5
 138  */
 139 #define SI_RING_ESGS            0
 140 #define SI_RING_GSVS            1
 141 #define SI_NUM_RING_BUFFERS     2
 142 #define SI_SO_BUF_OFFSET        SI_NUM_RING_BUFFERS
 143 #define SI_NUM_RW_BUFFERS       (SI_SO_BUF_OFFSET + 4)
 144
 145 #define SI_NUM_VERTEX_BUFFERS   16
 146
 147
 148 /* This represents resource descriptors in memory, such as buffer resources,
 149  * image resources, and sampler states.
 150  */
 151 struct si_descriptors {
 152         struct r600_atom atom;
 153
 154         /* The size of one resource descriptor. */
 155         unsigned element_dw_size;
 156         /* The maximum number of resource descriptors. */
 157         unsigned num_elements;
 158
 159         /* The buffer where resource descriptors are stored. */
 160         struct r600_resource *buffer;
 161         unsigned buffer_offset;
 162
 163         /* The i-th bit is set if that element is dirty (changed but not emitted). */
 164         unsigned dirty_mask;
 165         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 166         unsigned enabled_mask;
 167
 168         /* We can't update descriptors directly because the GPU might be
 169          * reading them at the same time, so we have to update them
 170          * in a copy-on-write manner. Each such copy is called a context,
 171          * which is just another array descriptors in the same buffer. */
 172         unsigned current_context_id;
 173         /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
 174         unsigned context_size;
 175
 176         /* The shader userdata register where the 64-bit pointer to the descriptor
 177          * array will be stored. */
 178         unsigned shader_userdata_reg;
 179 };
 180
 181 struct si_sampler_views {
 182         struct si_descriptors           desc;
 183         struct pipe_sampler_view        *views[SI_NUM_SAMPLER_VIEWS];
 184         uint32_t                        *desc_data[SI_NUM_SAMPLER_VIEWS];
 185 };
 186
 187 struct si_sampler_states {
 188         struct si_descriptors           desc;
 189         uint32_t                        *desc_data[SI_NUM_SAMPLER_STATES];
 190         void                            *saved_states[2]; /* saved for u_blitter */
 191 };
 192
 193 struct si_buffer_resources {
 194         struct si_descriptors           desc;
 195         unsigned                        num_buffers;
 196         enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
 197         enum radeon_bo_priority         priority;
 198         struct pipe_resource            **buffers; /* this has num_buffers elements */
 199         uint32_t                        *desc_storage; /* this has num_buffers*4 elements */
 200         uint32_t                        **desc_data; /* an array of pointers pointing to desc_storage */
 201 };
 202
 203 #define si_pm4_block_idx(member) \
 204         (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
 205
 206 #define si_pm4_state_changed(sctx, member) \
 207         ((sctx)->queued.named.member != (sctx)->emitted.named.member)
 208
 209 #define si_pm4_bind_state(sctx, member, value) \
 210         do { \
 211                 (sctx)->queued.named.member = (value); \
 212         } while(0)
 213
 214 #define si_pm4_delete_state(sctx, member, value) \
 215         do { \
 216                 if ((sctx)->queued.named.member == (value)) { \
 217                         (sctx)->queued.named.member = NULL; \
 218                 } \
 219                 si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \
 220                                   si_pm4_block_idx(member)); \
 221         } while(0)
 222
 223 #define si_pm4_set_state(sctx, member, value) \
 224         do { \
 225                 if ((sctx)->queued.named.member != (value)) { \
 226                         si_pm4_free_state(sctx, \
 227                                 (struct si_pm4_state *)(sctx)->queued.named.member, \
 228                                 si_pm4_block_idx(member)); \
 229                         (sctx)->queued.named.member = (value); \
 230                 } \
 231         } while(0)
 232
 233 /* si_descriptors.c */
 234 void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
 235                                 unsigned start, unsigned count, void **states);
 236 void si_update_vertex_buffers(struct si_context *sctx);
 237 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 238                         struct pipe_resource *buffer,
 239                         unsigned stride, unsigned num_records,
 240                         bool add_tid, bool swizzle,
 241                         unsigned element_size, unsigned index_stride);
 242 void si_init_all_descriptors(struct si_context *sctx);
 243 void si_release_all_descriptors(struct si_context *sctx);
 244 void si_all_descriptors_begin_new_cs(struct si_context *sctx);
 245 void si_copy_buffer(struct si_context *sctx,
 246                     struct pipe_resource *dst, struct pipe_resource *src,
 247                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 248 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
 249                             const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 250
 251 /* si_state.c */
 252 struct si_shader_selector;
 253
 254 boolean si_is_format_supported(struct pipe_screen *screen,
 255                                enum pipe_format format,
 256                                enum pipe_texture_target target,
 257                                unsigned sample_count,
 258                                unsigned usage);
 259 int si_shader_select(struct pipe_context *ctx,
 260                      struct si_shader_selector *sel);
 261 void si_make_dummy_ps(struct si_context *sctx);
 262 void si_init_state_functions(struct si_context *sctx);
 263 void si_init_config(struct si_context *sctx);
 264 unsigned cik_bank_wh(unsigned bankwh);
 265 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 266 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 267 unsigned cik_tile_split(unsigned tile_split);
 268 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
 269 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 270
 271 /* si_state_draw.c */
 272 extern const struct r600_atom si_atom_cache_flush;
 273 extern const struct r600_atom si_atom_msaa_config;
 274 void si_shader_init_pm4_state(struct si_shader *shader);
 275 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
 276 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 277
 278 /* si_commands.c */
 279 void si_cmd_context_control(struct si_pm4_state *pm4);
 280 void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
 281                          uint64_t index_base, uint32_t index_count,
 282                          uint32_t initiator, bool predicate);
 283 void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
 284                             uint32_t initiator, bool predicate);
 285 void si_cmd_draw_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 286                           uint32_t indirect_offset, uint32_t base_vtx_loc,
 287                           uint32_t start_inst_loc, bool predicate);
 288 void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
 289                                 uint64_t index_va, uint32_t index_max_size,
 290                                 uint32_t indirect_offset, uint32_t base_vtx_loc,
 291                                 uint32_t start_inst_loc, bool predicate);
 292
 293 #endif